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    /spacewiresystemc
    from Rev 33 to Rev 34
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Rev 33 → Rev 34

/trunk/rtl/RTL_VB/fifo_rx.v
54,9 → 54,6
reg block_read;
reg block_write;
 
wire [AWIDTH-1:0] wr;
wire [AWIDTH-1:0] rd;
 
reg [AWIDTH-1:0] credit_counter;
 
//Write pointer
65,6 → 62,76
if (!reset)
begin
wr_ptr <= {(AWIDTH){1'b0}};
mem[0] <= {(DWIDTH){1'b0}};
mem[1] <= {(DWIDTH){1'b0}};
mem[2] <= {(DWIDTH){1'b0}};
mem[3] <= {(DWIDTH){1'b0}};
mem[4] <= {(DWIDTH){1'b0}};
mem[5] <= {(DWIDTH){1'b0}};
mem[6] <= {(DWIDTH){1'b0}};
mem[7] <= {(DWIDTH){1'b0}};
mem[8] <= {(DWIDTH){1'b0}};
mem[9] <= {(DWIDTH){1'b0}};
mem[10] <= {(DWIDTH){1'b0}};
 
mem[11] <= {(DWIDTH){1'b0}};
mem[12] <= {(DWIDTH){1'b0}};
mem[13] <= {(DWIDTH){1'b0}};
mem[14] <= {(DWIDTH){1'b0}};
mem[15] <= {(DWIDTH){1'b0}};
mem[16] <= {(DWIDTH){1'b0}};
mem[17] <= {(DWIDTH){1'b0}};
mem[18] <= {(DWIDTH){1'b0}};
mem[19] <= {(DWIDTH){1'b0}};
mem[20] <= {(DWIDTH){1'b0}};
mem[21] <= {(DWIDTH){1'b0}};
 
mem[22] <= {(DWIDTH){1'b0}};
mem[23] <= {(DWIDTH){1'b0}};
mem[24] <= {(DWIDTH){1'b0}};
mem[25] <= {(DWIDTH){1'b0}};
mem[26] <= {(DWIDTH){1'b0}};
mem[27] <= {(DWIDTH){1'b0}};
mem[28] <= {(DWIDTH){1'b0}};
mem[29] <= {(DWIDTH){1'b0}};
mem[30] <= {(DWIDTH){1'b0}};
mem[31] <= {(DWIDTH){1'b0}};
mem[32] <= {(DWIDTH){1'b0}};
 
 
mem[33] <= {(DWIDTH){1'b0}};
mem[34] <= {(DWIDTH){1'b0}};
mem[35] <= {(DWIDTH){1'b0}};
mem[36] <= {(DWIDTH){1'b0}};
mem[37] <= {(DWIDTH){1'b0}};
mem[38] <= {(DWIDTH){1'b0}};
mem[39] <= {(DWIDTH){1'b0}};
mem[40] <= {(DWIDTH){1'b0}};
mem[41] <= {(DWIDTH){1'b0}};
mem[42] <= {(DWIDTH){1'b0}};
mem[43] <= {(DWIDTH){1'b0}};
 
mem[44] <= {(DWIDTH){1'b0}};
mem[45] <= {(DWIDTH){1'b0}};
mem[46] <= {(DWIDTH){1'b0}};
mem[47] <= {(DWIDTH){1'b0}};
mem[48] <= {(DWIDTH){1'b0}};
mem[49] <= {(DWIDTH){1'b0}};
mem[50] <= {(DWIDTH){1'b0}};
mem[51] <= {(DWIDTH){1'b0}};
mem[52] <= {(DWIDTH){1'b0}};
mem[53] <= {(DWIDTH){1'b0}};
mem[54] <= {(DWIDTH){1'b0}};
 
mem[55] <= {(DWIDTH){1'b0}};
mem[56] <= {(DWIDTH){1'b0}};
mem[57] <= {(DWIDTH){1'b0}};
mem[58] <= {(DWIDTH){1'b0}};
mem[59] <= {(DWIDTH){1'b0}};
mem[60] <= {(DWIDTH){1'b0}};
mem[61] <= {(DWIDTH){1'b0}};
mem[62] <= {(DWIDTH){1'b0}};
mem[63] <= {(DWIDTH){1'b0}};
block_write <= 1'b0;
overflow_credit_error<=1'b0;
end
73,13 → 140,17
if(block_write)
begin
if(!wr_en)
block_write <= 1'b0;
begin
block_write <= 1'b0;
wr_ptr <= wr_ptr + 6'd1;
end
//mem[wr_ptr-6'd1]<=data_in;
end
else if (wr_en && !f_full)
begin
block_write <= 1'b1;
mem[wr_ptr]<=data_in;
wr_ptr <= wr;
 
end
 
if(wr_en && credit_counter > 6'd55)
104,31 → 175,44
else
begin
 
if (wr_en && !f_full && !block_write)
if((wr_en && !f_full && !block_write) && (rd_en && !f_empty && !block_read))
begin
if(rd_en && !f_empty && !block_read)
begin
counter <= counter;
end
if(rd_ptr == 6'd8 || rd_ptr == 6'd16 || rd_ptr == 6'd24 || rd_ptr == 6'd32 || rd_ptr == 6'd40 || rd_ptr == 6'd48 || rd_ptr == 6'd56 || rd_ptr == 6'd63)
credit_counter <= credit_counter - 6'd1 + 6'd8;
else
begin
counter <= counter + 6'd1;
end
 
credit_counter <= credit_counter - 6'd1;
credit_counter <= credit_counter - 6'd1;
end
else if (wr_en && !f_full && !block_write)
begin
credit_counter <= credit_counter - 6'd1;
end
else if(rd_en && !f_empty && !block_read)
begin
if(rd_ptr == 6'd8 || rd_ptr == 6'd16 || rd_ptr == 6'd24 || rd_ptr == 6'd32 || rd_ptr == 6'd40 || rd_ptr == 6'd48 || rd_ptr == 6'd56 || rd_ptr == 6'd63)
begin
credit_counter <= credit_counter + 6'd8;
end
end
else
credit_counter <= credit_counter;
 
if((wr_en && !f_full && !block_write) && (rd_en && !f_empty && !block_read))
begin
counter <= counter;
end
else if (wr_en && !f_full && !block_write)
begin
counter <= counter + 6'd1;
end
else if(rd_en && !f_empty && !block_read)
begin
counter <= counter - 6'd1;
end
else
begin
counter <= counter;
end
 
 
 
 
if(counter == 6'd63)
begin
f_full <= 1'b1;
146,7 → 230,6
begin
f_empty <= 1'b0;
end
 
end
end
 
171,29 → 254,28
begin
open_slot_fct<= 1'b0;
end
if(block_read == 1)
 
if(block_read)
begin
if(!rd_en)
begin
block_read<= 1'b0;
 
data_out <= mem[rd_ptr];
end
end
else
if(rd_en && !f_empty)
begin
rd_ptr <= rd;
block_read<= 1'b1;
rd_ptr <= rd_ptr+ 6'd1;
end
else
begin
data_out <= mem[rd_ptr];
end
data_out <= mem[rd_ptr];
 
end
end
 
//assign f_empty = ((wr_ptr - rd_ptr) == 6'd0)?1'b1:1'b0;
assign wr = (wr_en && !f_full)?wr_ptr + 6'd1:wr_ptr + 6'd0;
assign rd = (rd_en && !f_empty)?rd_ptr+ 6'd1:rd_ptr + 6'd0;
//assign wr = (wr_en && !f_full)?wr_ptr + 6'd1:wr_ptr + 6'd0;
//assign rd = (rd_en && !f_empty)?rd_ptr+ 6'd1:rd_ptr + 6'd0;
 
endmodule
/trunk/rtl/RTL_VB/fifo_tx.v
52,8 → 52,6
reg block_read;
reg block_write;
 
wire [AWIDTH-1:0] wr;
wire [AWIDTH-1:0] rd;
 
//Write pointer
always@(posedge clock or negedge reset)
60,20 → 58,97
begin
if (!reset)
begin
wr_ptr <= {(AWIDTH){1'b0}};
mem[0] <= {(DWIDTH){1'b0}};
mem[1] <= {(DWIDTH){1'b0}};
mem[2] <= {(DWIDTH){1'b0}};
mem[3] <= {(DWIDTH){1'b0}};
mem[4] <= {(DWIDTH){1'b0}};
mem[5] <= {(DWIDTH){1'b0}};
mem[6] <= {(DWIDTH){1'b0}};
mem[7] <= {(DWIDTH){1'b0}};
mem[8] <= {(DWIDTH){1'b0}};
mem[9] <= {(DWIDTH){1'b0}};
mem[10] <= {(DWIDTH){1'b0}};
 
mem[11] <= {(DWIDTH){1'b0}};
mem[12] <= {(DWIDTH){1'b0}};
mem[13] <= {(DWIDTH){1'b0}};
mem[14] <= {(DWIDTH){1'b0}};
mem[15] <= {(DWIDTH){1'b0}};
mem[16] <= {(DWIDTH){1'b0}};
mem[17] <= {(DWIDTH){1'b0}};
mem[18] <= {(DWIDTH){1'b0}};
mem[19] <= {(DWIDTH){1'b0}};
mem[20] <= {(DWIDTH){1'b0}};
mem[21] <= {(DWIDTH){1'b0}};
 
mem[22] <= {(DWIDTH){1'b0}};
mem[23] <= {(DWIDTH){1'b0}};
mem[24] <= {(DWIDTH){1'b0}};
mem[25] <= {(DWIDTH){1'b0}};
mem[26] <= {(DWIDTH){1'b0}};
mem[27] <= {(DWIDTH){1'b0}};
mem[28] <= {(DWIDTH){1'b0}};
mem[29] <= {(DWIDTH){1'b0}};
mem[30] <= {(DWIDTH){1'b0}};
mem[31] <= {(DWIDTH){1'b0}};
mem[32] <= {(DWIDTH){1'b0}};
 
 
mem[33] <= {(DWIDTH){1'b0}};
mem[34] <= {(DWIDTH){1'b0}};
mem[35] <= {(DWIDTH){1'b0}};
mem[36] <= {(DWIDTH){1'b0}};
mem[37] <= {(DWIDTH){1'b0}};
mem[38] <= {(DWIDTH){1'b0}};
mem[39] <= {(DWIDTH){1'b0}};
mem[40] <= {(DWIDTH){1'b0}};
mem[41] <= {(DWIDTH){1'b0}};
mem[42] <= {(DWIDTH){1'b0}};
mem[43] <= {(DWIDTH){1'b0}};
 
mem[44] <= {(DWIDTH){1'b0}};
mem[45] <= {(DWIDTH){1'b0}};
mem[46] <= {(DWIDTH){1'b0}};
mem[47] <= {(DWIDTH){1'b0}};
mem[48] <= {(DWIDTH){1'b0}};
mem[49] <= {(DWIDTH){1'b0}};
mem[50] <= {(DWIDTH){1'b0}};
mem[51] <= {(DWIDTH){1'b0}};
mem[52] <= {(DWIDTH){1'b0}};
mem[53] <= {(DWIDTH){1'b0}};
mem[54] <= {(DWIDTH){1'b0}};
 
mem[55] <= {(DWIDTH){1'b0}};
mem[56] <= {(DWIDTH){1'b0}};
mem[57] <= {(DWIDTH){1'b0}};
mem[58] <= {(DWIDTH){1'b0}};
mem[59] <= {(DWIDTH){1'b0}};
mem[60] <= {(DWIDTH){1'b0}};
mem[61] <= {(DWIDTH){1'b0}};
mem[62] <= {(DWIDTH){1'b0}};
mem[63] <= {(DWIDTH){1'b0}};
 
wr_ptr <= {(AWIDTH){1'b0}};
block_write <= 1'b0;
end
else if(block_write)
else
begin
if(!wr_en)
block_write <= 1'b0;
if(block_write)
begin
if(!wr_en)
begin
block_write <= 1'b0;
wr_ptr <= wr_ptr + 6'd1;
end
end
else if (wr_en && !f_full)
begin
block_write <= 1'b1;
mem[wr_ptr]<=data_in;
end
end
else if (wr_en && !f_full)
begin
block_write <= 1'b1;
mem[wr_ptr]<=data_in;
wr_ptr <= wr;
end
end
 
//FULL - EMPTY COUNTER
82,28 → 157,29
begin
if (!reset)
begin
f_full <= 1'b0;
f_empty<= 1'b1;
f_full <= 1'b0;
f_empty <= 1'b1;
counter <= {(AWIDTH){1'b0}};
end
else
begin
 
if (wr_en && !f_full && !block_write)
if((wr_en && !f_full && !block_write) && (rd_en && !f_empty && !block_read))
begin
if(rd_en && !f_empty && !block_read)
begin
counter <= counter;
end
else
begin
counter <= counter + 6'd1;
end
counter <= counter;
end
else if (wr_en && !f_full && !block_write)
begin
counter <= counter + 6'd1;
end
else if(rd_en && !f_empty && !block_read)
begin
counter <= counter - 6'd1;
end
else
begin
counter <= counter;
end
 
if(counter == 6'd63)
begin
131,32 → 207,31
begin
if (!reset)
begin
rd_ptr <= {(AWIDTH){1'b0}};
data_out <= 9'd0;
write_tx <= 1'b0;
rd_ptr <= {(AWIDTH){1'b0}};
data_out <= 9'd0;
write_tx <= 1'b0;
block_read <= 1'b0;
end
else
begin
 
if(block_read == 1)
if(block_read)
begin
if(!rd_en)
begin
block_read<= 1'b0;
 
data_out <= mem[rd_ptr];
end
end
else if(rd_en && !f_empty)
begin
rd_ptr <= rd;
block_read<= 1'b1;
rd_ptr <= rd_ptr+ 6'd1;
end
else
begin
data_out <= mem[rd_ptr];
end
 
if(rd_en == 1'b1)
data_out <= mem[rd_ptr];
 
if(rd_en)
begin
write_tx<= 1'b0;
end
171,7 → 246,7
end
 
//assign f_empty = ((wr_ptr - rd_ptr) == 6'd0)?1'b1:1'b0;
assign wr = (wr_en && !f_full)?wr_ptr + 6'd1:wr_ptr + 6'd0;
assign rd = (rd_en && !f_empty)?rd_ptr+ 6'd1:rd_ptr + 6'd0;
//assign wr = (wr_en && !f_full)?wr_ptr + 6'd1:wr_ptr + 6'd0;
//assign rd = (rd_en && !f_empty)?rd_ptr+ 6'd1:rd_ptr + 6'd0;
 
endmodule
/trunk/rtl/RTL_VB/rx_spw.v
168,7 → 168,7
begin
posedge_p = 1'b0;
 
if((rx_din ^ rx_sin) == 1'b1)
if(rx_din ^ rx_sin)
begin
posedge_p = 1'b1;
end
605,7 → 605,7
if(control[2:0] != 3'd7)
begin
rx_data_flag <= {dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
data <= dta_timec_p;
data <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
data_l_r <= data;
last_is_control <=1'b0;
last_is_data <=1'b1;
/trunk/rtl/RTL_VB/spw_ulight_con_top_x.v
1,3 → 1,35
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module spw_ulight_con_top_x(
input ppll_100_MHZ,
input ppllclk,
/trunk/rtl/RTL_VB/tx_spw.v
609,7 → 609,7
begin
enable_fct = 1'b1;
end
else if((txwrite_tx && fct_counter_receive > 6'd0 && !hold_null && !hold_time_code && !hold_fct) == 1'b1 )
else if((txwrite_tx && !ready_tx_data && fct_counter_receive > 6'd0 && !hold_null && !hold_time_code && !hold_fct) == 1'b1 )
begin
enable_n_char = 1'b1;
end
723,7 → 723,7
if(enable_null)
begin
 
ready_tx_data <= 1'b0;
//ready_tx_data <= 1'b0;
ready_tx_timecode <= 1'b0;
//hold_null <= 1'b0;
hold_fct <= 1'b0;
755,20 → 755,30
else
block_sum_fct_send <= block_sum_fct_send;
 
if(global_counter_transfer == 4'd7)
begin
hold_null <= 1'b0;
end
else
begin
hold_null <= 1'b1;
end
 
if(first_time)
begin
first_time <= 1'b0;
hold_null <= 1'b1;
//hold_null <= 1'b1;
global_counter_transfer <= global_counter_transfer + 4'd1;
end
else if(global_counter_transfer != 4'd7)
begin
hold_null <= 1'b1;
//hold_null <= 1'b1;
global_counter_transfer <= global_counter_transfer + 4'd1;
end
else
begin
hold_null <= 1'b0;
//hold_null <= 1'b0;
ready_tx_data <= 1'b0;
last_type <= NULL;
global_counter_transfer <= 4'd0;
end
775,7 → 785,7
end
else if(enable_fct)
begin
ready_tx_data <= 1'b0;
//ready_tx_data <= 1'b0;
ready_tx_timecode <= 1'b0;
 
hold_null <= 1'b0;
796,10 → 806,23
else
block_sum <= block_sum;
 
if(global_counter_transfer == 4'd2)
ready_tx_data <= 1'b0;
else
ready_tx_data <= ready_tx_data;
 
if(global_counter_transfer == 4'd3)
begin
hold_fct <= 1'b0;
end
else
begin
hold_fct <= 1'b1;
end
 
if(global_counter_transfer != 4'd3)
begin
hold_fct <= 1'b1;
//hold_fct <= 1'b1;
global_counter_transfer <= global_counter_transfer + 4'd1;
//
if(send_fct_now && !block_sum_fct_send)
816,7 → 839,7
end
else
begin
hold_fct <= 1'b0;
//hold_fct <= 1'b0;
global_counter_transfer <= 4'd0;
fct_flag <= fct_flag - 3'd1;
last_type <=FCT;
830,7 → 853,7
hold_data <= 1'b0;
//hold_time_code <= 1'b0;
ready_tx_data <= 1'b0;
//ready_tx_data <= 1'b0;
 
if(gotfct_tx && !block_sum)
begin
849,6 → 872,15
ready_tx_timecode <= 1'b1;
end
 
if(global_counter_transfer == 4'd13)
begin
hold_time_code <= 1'b0;
end
else
begin
hold_time_code <= 1'b0;
end
 
//
if(send_fct_now && !block_sum_fct_send)
begin
862,7 → 894,7
else
block_sum_fct_send <= block_sum_fct_send;
 
if(global_counter_transfer < 4'd13)
if(global_counter_transfer != 4'd13)
begin
global_counter_transfer <= global_counter_transfer + 4'd1;
timecode_s <= {timecode_ss[13:10],2'd2,timecode_tx_i[7:0]};
869,6 → 901,7
end
else
begin
ready_tx_data <= 1'b0;
last_timein_control_flag_tx <= timecode_tx_i;
global_counter_transfer <= 4'd0;
last_type <= TIMEC;
900,16 → 933,18
 
if(global_counter_transfer == 4'd9)
begin
hold_data <= 1'b0;
ready_tx_data <= 1'b1;
end
else
begin
ready_tx_data <= 1'b0;
hold_data <= 1'b1;
end
 
if(global_counter_transfer != 4'd9)
begin
hold_data <= 1'b1;
 
global_counter_transfer <= global_counter_transfer + 4'd1;
txdata_flagctrl_tx_last <= data_tx_i;
 
927,7 → 962,6
end
else
begin
hold_data <= 1'b0;
global_counter_transfer <= 4'd0;
fct_counter_receive <= fct_counter_receive - 6'd1;
last_type <= DATA;
939,18 → 973,20
 
if(global_counter_transfer == 4'd3)
begin
hold_data <= 1'b0;
ready_tx_data <= 1'b1;
end
else
begin
hold_data <= 1'b1;
ready_tx_data <= 1'b0;
end
 
if(global_counter_transfer != 4'd3)
begin
hold_data <= 1'b1;
 
global_counter_transfer <= global_counter_transfer + 4'd1;
txdata_flagctrl_tx_last <= data_tx_i;
txdata_flagctrl_tx_last <= txdata_flagctrl_tx_last;
 
if(gotfct_tx && !block_sum)
begin
966,11 → 1002,17
end
else
begin
 
hold_data <= 1'b0;
global_counter_transfer <= 4'd0;
fct_counter_receive <= fct_counter_receive - 6'd1;
last_type <=EOP;
 
if(data_tx_i[1:0] == 2'b00)
begin
last_type <=EOP;
end
else if(data_tx_i[1:0] == 2'b01)
begin
last_type <=EEP;
end
end
end
 

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