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/synchronous_reset_fifo/trunk/test/fifo_testcase.sv
0,0 → 1,76
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "fifo_testcase.sv" ////
//// ////
//// This file is part of the "synchronous_reset_fifo" project ////
//// http://opencores.com/project,synchronous_reset_fifo ////
//// ////
//// Author: ////
//// - Madhumangal Javanthieswaran (madhu54321@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
/************************************************************************
Design Name : synchronous_reset_fifo
Module Name : fifo_testcase.v
Description :
Date : 19/12/2011
Author : Madhumangal Javanthieswaran
Email : j.madhumangal@gmail.com
Company :
Version : 1.0
Revision : 0.0
************************************************************************/
program fifo_testcase (fifo_if.DR_MP dr_if,fifo_if.RC_MP rc_if);
initial
begin
fifo_top.DUV_IF.sync_reset;
fifo_top.DUV_IF.sync_reset;
fifo_top.DUV_IF.sync_reset;
fifo_top.DUV_IF.write;
fifo_top.DUV_IF.read;
fifo_top.DUV_IF.write_read;
fifo_top.DUV_IF.sync_reset;
fifo_top.DUV_IF.fifo_empty;
fifo_top.DUV_IF.sync_reset;
fifo_top.DUV_IF.fifo_full;
#100 $finish;
end
 
endprogram:fifo_testcase
/synchronous_reset_fifo/trunk/rtl/fifo.v
0,0 → 1,113
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "fifo.v" ////
//// ////
//// This file is part of the "synchronous_reset_fifo" project ////
//// http://opencores.com/project,synchronous_reset_fifo ////
//// ////
//// Author: ////
//// - Madhumangal Javanthieswaran (madhu54321@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
/************************************************************************
Design Name : synchronous_reset_fifo
Module Name : fifo.v
Description :
Date : 19/12/2011
Author : Madhumangal Javanthieswaran
Email : j.madhumangal@gmail.com
Company :
Version : 1.0
Revision : 0.0
************************************************************************/
//Fifo size definitions
 
//Fifo Module
module fifo(clock,write_enb,read_enb,data_in,data_out,empty,full,resetn);
 
parameter WIDTH = 8;
parameter DEPTH = 16;
parameter POINTER_SIZE = 5;
 
//Inputs
input clock;
input resetn;
input write_enb;
input read_enb;
input [WIDTH-1:0] data_in;
//Outputs
output [WIDTH-1:0] data_out;
output empty;
output full;
 
//Wires and Internal Registers
wire empty;
wire full;
reg [WIDTH-1:0] memory [0:DEPTH-1];
reg [POINTER_SIZE-1:0] write_ptr;
reg [POINTER_SIZE-1:0] read_ptr;
reg [WIDTH-1:0] data_out;
 
 
//Asynchronous Logic
//FIFO full and empty logic
 
assign empty = ((write_ptr - read_ptr)== 5'b00000) ? 1'b1 : 1'b0;
assign full = ((write_ptr - read_ptr) == 5'b10000) ? 1'b1 : 1'b0;
 
//Synchronous Logic
//FIFO write and read logic
always@(posedge clock)
begin
if (resetn == 1'b0)
begin
write_ptr <= 5'b00000;
read_ptr <= 5'b00000;
data_out <= 8'b00000000;
end
else
//Simultaneous Read and Write
begin
if ((write_enb == 1'b1) && (full == 1'b0))
begin
memory[write_ptr] <= data_in;
write_ptr <= write_ptr + 1;
end
end
begin
if ((read_enb == 1'b1) && (empty == 1'b0))
begin
data_out <= memory[read_ptr];
read_ptr <= read_ptr + 1;
end
end
end
endmodule
/synchronous_reset_fifo/trunk/env/fifo_if.sv
0,0 → 1,180
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "fifo_if.sv" ////
//// ////
//// This file is part of the "synchronous_reset_fifo" project ////
//// http://opencores.com/project,synchronous_reset_fifo ////
//// ////
//// Author: ////
//// - Madhumangal Javanthieswaran (madhu54321@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
/************************************************************************
Design Name : synchronous_reset_fifo
Module Name : fifo_if.sv
Description :
Date : 19/12/2011
Author : Madhumangal Javanthieswaran
Email : j.madhumangal@gmail.com
Company :
Version : 1.0
Revision : 0.0
************************************************************************/
interface fifo_if(input bit clock);
 
//Fifo size definitions
parameter WIDTH = 8;
parameter DEPTH = 16;
parameter POINTER_SIZE = 5;
 
 
//Inputs
logic resetn;
logic write_enb;
logic read_enb;
logic [WIDTH-1:0] data_in;
 
//Outputs
logic [WIDTH-1:0] data_out;
logic empty;
logic full;
 
clocking dr_cb @(posedge clock);
output resetn;
output write_enb;
output read_enb;
output data_in;
endclocking
 
clocking rcv_cb @(posedge clock);
input data_out;
input empty;
input full;
endclocking
 
//modport DUV_IF(input clock,resetn,write_enb,read_enb,data_in, output data_out,empty,full);
 
modport DR_MP(clocking dr_cb);
modport RC_MP(clocking rcv_cb);
 
 
task sync_reset;
begin
dr_cb.resetn <= 0;
dr_cb.read_enb <= 0;
dr_cb.write_enb <= 0;
//repeat(2)
@(dr_cb);
repeat(2)
@(rcv_cb);
if(rcv_cb.data_out == 8'd0)
$display($time,"sync_reset works");
else
$display($time,"sync_reset error");
end
endtask:sync_reset
 
task write;
begin
dr_cb.resetn <= 1;
dr_cb.write_enb <= 1;
dr_cb.data_in <= 8'd85;
@(dr_cb);
$display($time,"write works");
end
endtask:write
 
task read;
begin
dr_cb.resetn <= 1;
dr_cb.read_enb <= 1;
repeat(2)
@(rcv_cb);
if(rcv_cb.data_out == 8'd85)
$display($time,"read works");
else
$display($time,"read error");
//@(rcv_cb);
end
endtask:read
 
task write_read;
begin
dr_cb.resetn <= 1;
dr_cb.write_enb <= 1;
dr_cb.data_in <= 8'd170;
dr_cb.read_enb <= 1;
repeat(2)
@(dr_cb);
repeat(2)
@(rcv_cb);
if(rcv_cb.data_out == 8'd170)
$display($time,"write_read works");
else
$display($time,"write_read error");
end
endtask:write_read
 
task fifo_full;
begin
dr_cb.resetn <= 1;
dr_cb.write_enb <= 1;
dr_cb.read_enb <= 0;
dr_cb.data_in <= $random;
repeat(16)
@(dr_cb);
//repeat(16)
@(rcv_cb);
if(rcv_cb.full == 1)
$display($time,"fifo_full works");
else
$display($time,"fifo_full error");
end
endtask
 
task fifo_empty;
begin
dr_cb.resetn <= 1;
dr_cb.write_enb <= 0;
dr_cb.read_enb <= 1;
repeat(2)
@(dr_cb);
if(rcv_cb.empty == 1)
$display($time,"fifo_empty works");
else
$display($time,"fifo_empty error");
end
endtask
 
 
endinterface:fifo_if
/synchronous_reset_fifo/trunk/env/fifo_top.sv
0,0 → 1,74
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "fifo_top.sv" ////
//// ////
//// This file is part of the "synchronous_reset_fifo" project ////
//// http://opencores.com/project,synchronous_reset_fifo ////
//// ////
//// Author: ////
//// - Madhumangal Javanthieswaran (madhu54321@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
/************************************************************************
Design Name : synchronous_reset_fifo
Module Name : fifo_top.sv
Description :
Date : 19/12/2011
Author : Madhumangal Javanthieswaran
Email : j.madhumangal@gmail.com
Company :
Version : 1.0
Revision : 0.0
************************************************************************/
module fifo_top();
bit clock;
 
fifo_if DUV_IF(clock);
 
fifo RTL_IF(.clock(clock),
.resetn(DUV_IF.resetn),
.write_enb(DUV_IF.write_enb),
.read_enb(DUV_IF.read_enb),
.data_in(DUV_IF.data_in),
.data_out(DUV_IF.data_out),
.empty(DUV_IF.empty),
.full(DUV_IF.full)
);
 
fifo_testcase TEST_IF(DUV_IF,DUV_IF);
 
initial
clock = 0;
 
always
begin
#10 clock = ~ clock;
end
 
endmodule:fifo_top
/synchronous_reset_fifo/trunk/sim/Makefile
0,0 → 1,45
# Makefile for fifo - Functionality Testing and Regression Testing
RTL = ../rtl/fifo.v
work = work
COVOP = -coveropt 3 +cover=bcft +acc
SVTB1= ../env/fifo_if.sv ../env/fifo_top.sv
INC = +incdir+../env +incdir+../lib
TEST = ../test/fifo_testcase.sv
#TEST1 = ../test/test1.sv
#TEST2 = ../test/test2.sv
VSIMOPT= -coverage -novopt -sva -sv_seed random -l sim_log.txt work.fifo_top
VSIMCOV= coverage save -onexit -assert -directive -cvg -codeAll mem_cov
VSIMBATCH= -c -do "$(VSIMCOV); run -all; exit"
 
report:
firefox covhtmlreport/pages/__frametop.htm
 
lib:
vlib $(work)
vmap work $(work)
 
sv_cmp: lib comp0
run_sim:
vsim $(VSIMOPT) $(VSIMBATCH)
vcover report -html mem_cov
 
gui:
vsim $(VSIMOPT)
comp0:
vlog -work $(work) $(COVOP) $(RTL) $(SVTB1) $(INC) $(TEST)
comp1:
vlog -work $(work) $(COVOP) $(RTL) $(SVTB1) $(INC) $(TEST1)
comp2:
vlog -work $(work) $(COVOP) $(RTL) $(SVTB1) $(INC) $(TEST2)
 
run_gui: clean lib comp0 gui
run_test: clean lib comp0 run_sim
run_test1: clean lib comp1 run_sim
run_test2: clean lib comp2 run_sim
 
clean:
rm -rf modelsim.* transcript* vlog.* work vsim.wlf fcover* covhtml* mem_cov* *.txt
/synchronous_reset_fifo/trunk/Verification_Plan_fifo.txt
0,0 → 1,17
---------------------------------------------------------------------------------------------
* Feature Extraction
---------------------------------------------------------------------------------------------
- Write to FIFO
 
- Read from Fifo
 
- Simultaneous Read and Write operation
 
- Full Condition
 
- Empty Condition
 
- Fifo read when empty
_____________________________________________________________________________________________
 

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