URL
https://opencores.org/ocsvn/tiny_tate_bilinear_pairing/tiny_tate_bilinear_pairing/trunk
Subversion Repositories tiny_tate_bilinear_pairing
Compare Revisions
- This comparison shows the changes necessary to convert path
/tiny_tate_bilinear_pairing/trunk
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/testbench/test_tiny_cmd.v
40,13 → 40,10
#100; |
|
// Add stimulus here |
reset = 1; // keep FSM silent |
// init x, y |
#(`P/2); #(`P); |
// addr[3] = x |
sel = 1; w = 1; |
addr = 0; |
data = 0; |
#(`P); // without this write, next write will fail. bug ? :( |
addr = 3; |
data = 194'h288162298554054820552a05426081a1842886a58916a6249; |
#(`P); |
61,14 → 58,23
addr = 7; |
#(`P); |
|
sel = 0; |
sel = 1; w = 0; /*read back*/ |
addr = 3; #(`P); |
$display("xp = %h", out); |
addr = 5; #(`P); |
$display("yp = %h", out); |
addr = 6; #(`P); |
$display("xq = %h", out); |
addr = 7; #(`P); |
$display("yq = %h", out); |
|
reset = 0; |
$finish; |
|
@(posedge clk); |
reset = 1; #(`P*3); reset = 0; // shorter reset signal makes FSM direct done. bug :( |
|
sel = 0; w = 0; |
@(posedge done); |
@(negedge clk); |
sel = 1; w = 0; |
addr = 0; #(`P); // first read fails. bug ? |
addr = 3; #(`P); |
$display("xp = %h", out); |
addr = 5; #(`P); |
89,6 → 95,18
$display("t4 = %h", out); |
addr = 14; #(`P); |
$display("t5 = %h", out); |
addr = 15; #(`P); |
$display("R0 = %h", out); |
addr = 17; #(`P); |
$display("R1 = %h", out); |
addr = 18; #(`P); |
$display("R2 = %h", out); |
addr = 19; #(`P); |
$display("R3 = %h", out); |
addr = 20; #(`P); |
$display("R4 = %h", out); |
addr = 21; #(`P); |
$display("R5 = %h", out); |
|
$finish; |
end |
/rtl/tiny.v
36,8 → 36,8
/* for const */ |
wire [197:0] const0_out, const1_out; |
wire const0_effective, const1_effective; |
/* for mux */ |
wire [197:0] mux0_out, mux1_out; |
/* for muxer */ |
wire [197:0] muxer0_out, muxer1_out; |
/* for ROM */ |
wire [8:0] rom_addr; |
wire [25:0] rom_q; |
57,11 → 57,11
const1 (clk, ram_b_addr, const1_out, const1_effective); |
ram |
ram0 (clk, ram_a_w, ram_a_addr, data, ram_a_data_out, ram_b_w, ram_b_addr[5:0], ram_b_data_in, ram_b_data_out); |
mux |
mux0 (ram_a_data_out, const0_out, const0_effective, mux0_out), |
mux1 (ram_b_data_out, const1_out, const1_effective, mux1_out); |
muxer |
muxer0 (ram_a_data_out, const0_out, const0_effective, muxer0_out), |
muxer1 (ram_b_data_out, const1_out, const1_effective, muxer1_out); |
PE |
pe0 (clk, reset, pe_ctrl, mux1_out, mux0_out[193:0], mux0_out[193:0], ram_b_data_in[193:0]); |
pe0 (clk, reset, pe_ctrl, muxer1_out, muxer0_out[193:0], muxer0_out[193:0], ram_b_data_in[193:0]); |
|
assign ram_b_data_in[197:194] = 0; |
endmodule |
78,7 → 78,7
assign w_out = sel & w_in; |
endmodule |
|
module mux(from_ram, from_const, const_effective, out); |
module muxer(from_ram, from_const, const_effective, out); |
input [197:0] from_ram, from_const; |
input const_effective; |
output [197:0] out; |
/rtl/const.v
38,13 → 38,13
begin |
effective <= 1; |
case (addr) |
1: out <= 0; |
2: out <= 1; |
1: out <= 198'd0; |
2: out <= 198'd1; |
4: out <= {6'b000101, 192'd0}; |
8: out <= {6'b001001, 192'd0}; |
16: out <= {6'b010101, 192'd0}; |
default: |
begin out <= 0; effective <= 0; end |
begin out <= 198'd0; effective <= 0; end |
endcase |
end |
endmodule |