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Subversion Repositories tiny_tate_bilinear_pairing

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    /tiny_tate_bilinear_pairing/trunk
    from Rev 4 to Rev 5
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Rev 4 → Rev 5

/testbench/test_tiny_cmd.v File deleted
/testbench/test_tiny_cubic.v File deleted
/testbench/test_tiny_ram.v File deleted
/testbench/test_rom.v File deleted
/testbench/test_ram.v
1,43 → 1,41
`timescale 1ns / 1ps
`define P 20
 
`define P 20 // clock period
 
module test_ram;
 
// Inputs
reg clk;
reg a_wr;
reg [6:0] a_addr;
reg [197:0] a_din;
reg b_wr;
reg [6:0] b_addr;
reg [197:0] b_din;
reg reset;
reg sel;
reg [5:0] addr;
reg w;
reg [197:0] data;
 
// Outputs
wire [197:0] a_dout;
wire [197:0] b_dout;
wire [197:0] out;
wire done;
 
// Instantiate the Unit Under Test (UUT)
ram uut (
tiny uut (
.clk(clk),
.a_wr(a_wr),
.a_addr(a_addr),
.a_din(a_din),
.a_dout(a_dout),
.b_wr(b_wr),
.b_addr(b_addr),
.b_din(b_din),
.b_dout(b_dout)
.reset(reset),
.sel(sel),
.addr(addr),
.w(w),
.data(data),
.out(out),
.done(done)
);
 
initial begin
// Initialize Inputs
clk = 0;
a_wr = 0;
a_addr = 0;
a_din = 0;
b_wr = 0;
b_addr = 0;
b_din = 0;
reset = 0;
sel = 0;
addr = 0;
w = 0;
data = 0;
 
// Wait 100 ns for global reset to finish
#100;
44,12 → 42,39
// Add stimulus here
@ (negedge clk);
a_addr = 1;
#(`P*2);
// write
sel = 1; w = 1;
data = 198'h115a25886512165251569195908560596a6695612620504191;
addr = 0;
#(`P);
data = 198'h1559546442405a181195655549614540592955a15a26984015;
addr = 3;
#(`P);
// not write
w = 0;
data = 198'h12222222222222222222222222222222222222222222222222;
addr = 3;
#(`P);
// read
sel = 1; w = 0;
addr = 0;
#(`P);
if (out !== 198'h115a25886512165251569195908560596a6695612620504191)
$display("E");
 
addr = 3;
#(`P);
if (out !== 198'h1559546442405a181195655549614540592955a15a26984015)
$display("E");
 
#(`P);
$display("Good");
$finish;
end
 
initial #100 forever #(`P/2) clk = ~clk;
endmodule
 
/testbench/test_tiny.v
0,0 → 1,118
`timescale 1ns / 1ps
`define P 20 // clock period
 
module test_tiny;
 
// Inputs
reg clk;
reg reset;
reg sel;
reg [5:0] addr;
reg w;
reg [197:0] data;
 
// Outputs
wire [197:0] out;
wire done;
 
// Instantiate the Unit Under Test (UUT)
tiny uut (
.clk(clk),
.reset(reset),
.sel(sel),
.addr(addr),
.w(w),
.data(data),
.out(out),
.done(done)
);
 
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
sel = 0;
addr = 0;
w = 0;
data = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 1; // keep FSM silent
// init x, y
write(3, 194'h288162298554054820552a05426081a1842886a58916a6249);
write(5, 194'h2895955069089214054596a189a4420556589054140941695);
write(6, 194'h288162298554054820552a05426081a1842886a58916a6249);
write(7, 194'h2895955069089214054596a189a4420556589054140941695);
/* read back. uncomment me if error happens */
/* read(3);
$display("xp = %h", out);
read(5);
$display("yp = %h", out);
read(6);
$display("xq = %h", out);
read(7);
$display("yq = %h", out);*/
reset = 0;
sel = 0; w = 0;
@(posedge done);
@(negedge clk);
read(3);
check(194'h288162298554054820552a05426081a1842886a58916a624a);
read(5);
check(194'h146a6aa0960461280a8a69524658810aa9a460a828068296a);
read(6);
check(194'h288162298554054820552a05426081a1842886a58916a6249);
read(7);
check(194'h2895955069089214054596a189a4420556589054140941695);
read(9);
check(194'h0580908654985206a92415296589411858a9211984160a180);
read(10);
check(194'h0501a2129024a92511058540424059509a55982a065252924);
read(11);
check(194'h06624689a2149059841a814409946196a92a06595029a2994);
read(12);
check(194'h2a10a642a56aa9a26458a801285221820aa98226402100889);
read(13);
check(194'h06a99a1556a662900898a49026640509924a1210121809886);
read(14);
check(194'h2a88582860a80605825150584a8a8099491029242961a5685);
$display("Good");
$finish;
end
 
initial #100 forever #(`P/2) clk = ~clk;
 
task write;
input [6:0] adr;
input [197:0] dat;
begin
sel = 1;
w = 1;
addr = adr;
data = dat;
#(`P);
end
endtask
 
task read;
input [6:0] adr;
begin
sel = 1;
w = 0;
addr = adr;
#(`P);
end
endtask;
 
task check;
input [197:0] wish;
begin
if (out !== wish)
begin $display("Error!"); $finish; end
end
endtask
endmodule
 
/testbench/test_pe.v
1,7 → 1,7
`timescale 1ns / 1ps
`define P 20
 
module test_PE;
module test_pe;
 
// Inputs
reg clk;
49,8 → 49,7
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=11'b00000_111111; #(33*`P);
ctrl=0; #`P;
if(out !== wish) $display("E");
check;
// test cubic
d0 = {6'b10101, 192'd0};
62,11 → 61,10
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=1; #(33*`P);
ctrl=0; #`P;
if(out !== wish) $display("E");
check;
// test add
d0 = {6'b101, 192'd0};
d0 = {6'b000101, 192'd0};
d1 = 194'h0994544a41588446516618a14691a545542521a4158868428;
d2 = 194'h1901269451681914415481656104980811a5a555155546949;
wish = 194'h16954a129284915a928a9916a4954141659a96092a11a2165;
75,11 → 73,10
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=11'b10001; #(33*`P);
ctrl=0; #`P;
if(out !== wish) $display("E");
check;
 
// test sub
d0 = {6'b1001, 192'd0};
d0 = {6'b001001, 192'd0};
d1 = 194'h0994544a41588446516618a14691a545542521a4158868428;
d2 = 194'h1901269451681914415481656104980811a5a555155546949;
wish = 194'h209661a62020aa6210125a481599194946404852006625aa2;
88,12 → 85,19
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=11'b10001; #(33*`P);
ctrl=0; #`P;
if(out !== wish) $display("E");
check;
 
$display("Good!");
$finish;
end
 
initial #100 forever #(`P/2) clk = ~clk;
 
task check;
begin
if (out !== wish)
begin $display("E %h %h", out, wish); $finish; end
end
endtask
endmodule
 
/testbench/test_fsm.v
1,7 → 1,7
`timescale 1ns / 1ps
`define P 20 // clock period
 
module test_FSM;
module test_fsm;
 
// Inputs
reg clk;
/testbench/test_const.v
5,7 → 5,7
 
// Inputs
reg clk;
reg [4:0] addr;
reg [5:0] addr;
 
// Outputs
wire [197:0] out;
34,14 → 34,15
#(`P); check;
addr = 2; w_out = 1;
#(`P); check;
addr = 4; w_out = {4'b0101, 194'd0};
addr = 4; w_out = {6'b000101, 192'd0};
#(`P); check;
addr = 8; w_out = {4'b0110, 194'd0};
addr = 8; w_out = {6'b001001, 192'd0};
#(`P); check;
addr = 16; w_out = {6'b010101, 192'd0};
#(`P); check;
addr = 0; w_out = 0; w_effective = 0;
#(`P); check;
$display("Good");
$finish;
end
 
50,7 → 51,7
task check;
begin
if (out !== w_out || effective !== w_effective)
$display("E");
$display("E %d %h %h", addr, out, w_out);
end
endtask
endmodule
/testbench/test_pairing.v
0,0 → 1,151
`timescale 1ns / 1ps
`define P 20 // clock period
 
module test_pairing;
 
// Inputs
reg clk;
reg reset;
reg sel;
reg [5:0] addr;
reg w;
reg update;
reg ready;
reg i;
 
// Outputs
wire done;
wire o;
 
// Buffers
reg [197:0] out;
 
// Instantiate the Unit Under Test (UUT)
pairing uut (
.clk(clk),
.reset(reset),
.sel(sel),
.addr(addr),
.w(w),
.update(update),
.ready(ready),
.i(i),
.o(o),
.done(done)
);
 
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
sel = 0;
addr = 0;
w = 0;
update = 0;
ready = 0;
i = 0;
out = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
/* keep FSM silent */
reset = 1;
/* init xp, yp, xq, yq */
write(3, 194'h288162298554054820552a05426081a1842886a58916a6249);
write(5, 194'h2895955069089214054596a189a4420556589054140941695);
write(6, 194'h288162298554054820552a05426081a1842886a58916a6249);
write(7, 194'h2895955069089214054596a189a4420556589054140941695);
/* read back. uncomment me if error happens */
/* read(3);
$display("xp = %h", out);
read(5);
$display("yp = %h", out);
read(6);
$display("xq = %h", out);
read(7);
$display("yq = %h", out);*/
reset = 0;
sel = 0; w = 0;
@(posedge done);
@(negedge clk);
read(3);
check(194'h288162298554054820552a05426081a1842886a58916a624a);
read(5);
check(194'h146a6aa0960461280a8a69524658810aa9a460a828068296a);
read(6);
check(194'h288162298554054820552a05426081a1842886a58916a6249);
read(7);
check(194'h2895955069089214054596a189a4420556589054140941695);
read(9);
check(194'h0580908654985206a92415296589411858a9211984160a180);
read(10);
check(194'h0501a2129024a92511058540424059509a55982a065252924);
read(11);
check(194'h06624689a2149059841a814409946196a92a06595029a2994);
read(12);
check(194'h2a10a642a56aa9a26458a801285221820aa98226402100889);
read(13);
check(194'h06a99a1556a662900898a49026640509924a1210121809886);
read(14);
check(194'h2a88582860a80605825150584a8a8099491029242961a5685);
$display("Good");
$finish;
end
 
initial #100 forever #(`P/2) clk = ~clk;
 
task write;
input [5:0] adr;
input [197:0] dat;
integer j;
begin
sel = 1;
w = 0;
addr = adr;
update = 1;
#`P;
update = 0;
ready = 1;
for(j=0;j<198;j=j+1)
begin
i = dat[j];
#`P;
end
ready = 0;
w = 1; #`P; w = 0;
end
endtask
 
task read;
input [5:0] adr;
integer j;
begin
sel = 1;
w = 0;
addr = adr;
#`P;
update = 1;
#`P;
update = 0;
out = 0;
ready = 1;
for(j=0;j<198;j=j+1)
begin
out = {o, out[197:1]};
#`P;
end
end
endtask
task check;
input [197:0] wish;
begin
if (out !== wish)
begin $display("Error!"); $finish; end
end
endtask
endmodule
 
/rtl/pairing.v
0,0 → 1,47
/*
Copyright 2012 Homer Hsing
This file is part of Tiny Tate Bilinear Pairing Core.
 
Tiny Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
Tiny Tate Bilinear Pairing Core is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
 
You should have received a copy of the GNU Lesser General Public License
along with Tiny Tate Bilinear Pairing Core. If not, see http://www.gnu.org/licenses/lgpl.txt
*/
 
module pairing(clk, reset, sel, addr, w, update, ready, i, o, done);
input clk;
input reset; // for the arithmethic core
input sel;
input [5:0] addr;
input w;
input update; // update reg_in & reg_out
input ready; // shift reg_in & reg_out
input i;
output o;
output done;
reg [197:0] reg_in, reg_out;
wire [197:0] out;
assign o = reg_out[0];
tiny
tiny0 (clk, reset, sel, addr, w, reg_in, out, done);
always @ (posedge clk) // write LSB firstly
if (update) reg_in <= 0;
else if (ready) reg_in <= {i,reg_in[197:1]};
always @ (posedge clk) // read LSB firstly
if (update) reg_out <= out;
else if (ready) reg_out <= reg_out>>1;
endmodule

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