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/trunk/rtl/rom.v
0,0 → 1,41
/*
Copyright 2012 Homer Hsing
This file is part of Tiny Tate Bilinear Pairing Core.
 
Tiny Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
Tiny Tate Bilinear Pairing Core is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
 
You should have received a copy of the GNU Lesser General Public License
along with Tiny Tate Bilinear Pairing Core. If not, see http://www.gnu.org/licenses/lgpl.txt
*/
 
/*
* the $ctrl$ field in the first cmd is the running number of the second command.
* 0: rom_q <= {6'd1, 1'd0, 7'd0, 7'd0, 11'd0}; // repeat 1 time
* 1: rom_q <= {6'd2, 1'd1, 7'd2, 7'd3, 11'd4}; // repeat 1 times
* 2: rom_q <= {6'd3, 1'd0, 7'd5, 7'd6, 11'd7}; // repeat 2 times
* 3: rom_q <= {6'd1, 1'd1, 7'd8, 7'd9, 11'ha}; // repeat 3 time
* the number one command runs two times. don't put valid command there :)
*/
module rom (clk, addr, out);
input clk;
input [9:0] addr;
output reg [31:0] out;
always @(posedge clk)
case (addr) // test addr[3] = addr[2] + addr[2]
0: out <= {6'd1, 1'd0, 7'd0, 7'd0, 11'd0}; // blank
1: out <= {6'd1, 1'd0, 7'd0, 7'd2, 11'b0}; // read addr[2]
2: out <= {6'd2, 1'd0, 7'd4, 7'd2, 11'b11000000000}; // load d1, read addr[2], command_add
3: out <= {6'd1, 1'd1, 7'd3, 7'd0, 11'b00111010001}; // load d0, d2, d3
default: out <= 0;
endcase
endmodule
/trunk/rtl/ram.v
0,0 → 1,64
/*
Copyright 2012 Homer Hsing
This file is part of Tiny Tate Bilinear Pairing Core.
 
Tiny Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
Tiny Tate Bilinear Pairing Core is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
 
You should have received a copy of the GNU Lesser General Public License
along with Tiny Tate Bilinear Pairing Core. If not, see http://www.gnu.org/licenses/lgpl.txt
*/
 
module ram #(
parameter DATA = 198,
parameter ADDR = 7
) (
input clk,
 
// Port A
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
 
// Shared memory
reg [DATA-1:0] mem [(2**ADDR)-1:0];
 
initial begin : init
integer i;
for(i = 0; i < 2**ADDR; i = i + 1)
mem[i] = 0;
end
 
// Port A
always @(posedge clk) begin
if(a_wr) begin
mem[a_addr] <= a_din;
end
a_dout <= mem[a_addr];
end
 
// Port B
always @(posedge clk) begin
if(b_wr) begin
mem[b_addr] <= b_din;
end
b_dout <= mem[b_addr];
end
 
endmodule
/trunk/rtl/tiny.v
0,0 → 1,87
/*
Copyright 2012 Homer Hsing
This file is part of Tiny Tate Bilinear Pairing Core.
 
Tiny Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
Tiny Tate Bilinear Pairing Core is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
 
You should have received a copy of the GNU Lesser General Public License
along with Tiny Tate Bilinear Pairing Core. If not, see http://www.gnu.org/licenses/lgpl.txt
*/
 
module tiny(clk, reset, sel, addr, w, data, out, done);
input clk, reset;
input sel;
input [6:0] addr;
input w;
input [197:0] data;
output [197:0] out;
output done;
 
/* for FSM */
wire [6:0] fsm_addr;
/* for RAM */
wire [6:0] ram_a_addr, ram_b_addr;
wire [197:0] ram_b_data_in;
wire ram_a_w, ram_b_w;
wire [197:0] ram_a_data_out, ram_b_data_out;
/* for const */
wire [197:0] const0_out, const1_out;
wire const0_effective, const1_effective;
/* for mux */
wire [197:0] mux0_out, mux1_out;
/* for ROM */
wire [9:0] rom_addr;
wire [31:0] rom_q;
/* for PE */
wire [10:0] pe_ctrl;
assign out = ram_a_data_out;
select
select0 (sel, addr, fsm_addr, w, ram_a_addr, ram_a_w);
rom
rom0 (clk, rom_addr, rom_q);
FSM
fsm0 (clk, reset, rom_addr, rom_q, fsm_addr, ram_b_addr, ram_b_w, pe_ctrl, done);
const
const0 (clk, ram_a_addr, const0_out, const0_effective),
const1 (clk, ram_b_addr, const1_out, const1_effective);
ram
ram0 (clk, ram_a_w, ram_a_addr, data, ram_a_data_out, ram_b_w, ram_b_addr, ram_b_data_in, ram_b_data_out);
mux
mux0 (ram_a_data_out, const0_out, const0_effective, mux0_out),
mux1 (ram_b_data_out, const1_out, const1_effective, mux1_out);
PE
pe0 (clk, reset, pe_ctrl, mux1_out, mux0_out[193:0], mux0_out[193:0], ram_b_data_in[193:0]);
assign ram_b_data_in[197:194] = 0;
endmodule
 
module select(sel, addr_in, addr_fsm_in, w_in, addr_out, w_out);
input sel;
input [6:0] addr_in;
input [6:0] addr_fsm_in;
input w_in;
output [6:0] addr_out;
output w_out;
assign addr_out = sel ? addr_in : addr_fsm_in;
assign w_out = sel & w_in;
endmodule
 
module mux(from_ram, from_const, const_effective, out);
input [197:0] from_ram, from_const;
input const_effective;
output [197:0] out;
assign out = const_effective ? from_const : from_ram;
endmodule
/trunk/rtl/pe.v
0,0 → 1,154
/*
Copyright 2012 Homer Hsing
This file is part of Tiny Tate Bilinear Pairing Core.
 
Tiny Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
Tiny Tate Bilinear Pairing Core is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
 
You should have received a copy of the GNU Lesser General Public License
along with Tiny Tate Bilinear Pairing Core. If not, see http://www.gnu.org/licenses/lgpl.txt
*/
 
`define M 97 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
 
/* PE: processing element */
module PE(clk, reset, ctrl, d0, d1, d2, out);
input clk;
input reset;
input [10:0] ctrl;
input [197:0] d0;
input [`WIDTH:0] d1, d2;
output [`WIDTH:0] out;
reg [197:0] R0;
reg [`WIDTH:0] R1, R2, R3;
wire [1:0] e0, e1, e2; /* part of R0 */
wire [`WIDTH:0] ppg0, ppg1, ppg2, /* output of PPG */
mx0, mx1, mx2, mx3, mx4, mx5, mx6, /* output of MUX */
ad0, ad1, ad2, /* output of GF(3^m) adder */
cu0, cu1, cu2, /* output of cubic */
mo0, mo1, mo2, /* output of mod_p */
t0, t1, t2;
wire c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10;
assign {c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10} = ctrl;
assign mx0 = c0 ? d1 : ad2;
assign mx1 = c2 ? d2 : ad2;
always @ (posedge clk)
if(reset) R1 <= 0;
else if (c1) R1 <= mx0;
always @ (posedge clk)
if(reset) R2 <= 0;
else if (c3) R2 <= mx1;
always @ (posedge clk)
if(reset) R0 <= 0;
else if (c4) R0 <= d0;
else if (c5) R0 <= R0 << 6;
assign {e2,e1,e0} = R0[197:192];
PPG
ppg_0 (e0, R1, ppg0),
ppg_1 (e1, R2, ppg1),
ppg_2 (e2, R1, ppg2);
v0 v0_ (ppg0, cu0);
v1 v1_ (ppg1, cu1);
v2 v2_ (ppg2, cu2);
assign mx2 = c6 ? ppg0 : cu0;
assign mx3 = c6 ? ppg1 : cu1;
assign mx4 = c6 ? mo1 : cu2;
assign mx5 = c7 ? mo2 : R3;
mod_p
mod_p_0 (mx3, mo0),
mod_p_1 (ppg2, t0),
mod_p_2 (t0, mo1),
mod_p_3 (R3, t1),
mod_p_4 (t1, t2),
mod_p_5 (t2, mo2);
assign mx6 = c9 ? mo0 : mx3;
f3m_add
f3m_add_0 (mx2, mx6, ad0),
f3m_add_1 (mx4, c8 ? mx5 : 0, ad1),
f3m_add_2 (ad0, ad1, ad2);
always @ (posedge clk)
if (reset) R3 <= 0;
else if (c10) R3 <= ad2;
assign out = R3;
endmodule
 
// C = (x*B mod p(x))
module mod_p(B, C);
input [`WIDTH:0] B;
output [`WIDTH:0] C;
wire [`WIDTH+2:0] A;
assign A = {B[`WIDTH:0], 2'd0}; // A == B*x
wire [1:0] w0;
f3_mult m0 (A[195:194], 2'd2, w0);
f3_add s0 (A[1:0], {w0[0], w0[1]}, C[1:0]); //f3_sub s0 (A[1:0], w0, C[1:0]);
assign C[23:2] = A[23:2];
wire [1:0] w12;
f3_mult m12 (A[195:194], 2'd1, w12);
f3_add s12 (A[25:24], {w12[0], w12[1]}, C[25:24]); // f3_sub s12 (A[25:24], w12, C[25:24]);
assign C[193:26] = A[193:26];
endmodule
 
// PPG: partial product generator, C == A*d in GF(3^m)
module PPG(d, A, C);
input [1:0] d;
input [`WIDTH:0] A;
output [`WIDTH:0] C;
genvar i;
generate
for (i=0; i < `M; i=i+1)
begin: ppg0
f3_mult f3_mult_0 (d, A[2*i+1:2*i], C[2*i+1:2*i]);
end
endgenerate
endmodule
 
// f3m_add: C = A + B, in field F_{3^M}
module f3m_add(A, B, C);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for(i=0; i<`M; i=i+1) begin: aa
f3_add aa(A[(2*i+1) : 2*i], B[(2*i+1) : 2*i], C[(2*i+1) : 2*i]);
end
endgenerate
endmodule
 
// f3_add: C == A+B (mod 3)
module f3_add(A, B, C);
input [1:0] A, B;
output [1:0] C;
wire a0, a1, b0, b1, c0, c1;
assign {a1, a0} = A;
assign {b1, b0} = B;
assign C = {c1, c0};
assign c0 = ( a0 & ~a1 & ~b0 & ~b1) |
(~a0 & ~a1 & b0 & ~b1) |
(~a0 & a1 & ~b0 & b1) ;
assign c1 = (~a0 & a1 & ~b0 & ~b1) |
( a0 & ~a1 & b0 & ~b1) |
(~a0 & ~a1 & ~b0 & b1) ;
endmodule
 
// f3_mult: C = A*B (mod 3)
module f3_mult(A, B, C);
input [1:0] A;
input [1:0] B;
output [1:0] C;
wire a0, a1, b0, b1;
assign {a1, a0} = A;
assign {b1, b0} = B;
assign C[0] = (~a1 & a0 & ~b1 & b0) | (a1 & ~a0 & b1 & ~b0);
assign C[1] = (~a1 & a0 & b1 & ~b0) | (a1 & ~a0 & ~b1 & b0);
endmodule
/trunk/rtl/cubic.v
0,0 → 1,327
/*
Copyright 2012 Homer Hsing
This file is part of Tiny Tate Bilinear Pairing Core.
 
Tiny Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
Tiny Tate Bilinear Pairing Core is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
 
You should have received a copy of the GNU Lesser General Public License
along with Tiny Tate Bilinear Pairing Core. If not, see http://www.gnu.org/licenses/lgpl.txt
*/
 
/* v0(a)+v1(a)+v2(a) == a^3 in GF(3^m) */
 
/* c == v0(a) */
module v0(a, c);
input [193:0] a;
output [193:0] c;
assign c[1:0] = a[1:0];
assign c[3:2] = a[131:130];
assign c[5:4] = a[67:66];
assign c[7:6] = a[3:2];
assign c[9:8] = a[133:132];
assign c[11:10] = a[69:68];
assign c[13:12] = a[5:4];
assign c[15:14] = a[135:134];
assign c[17:16] = a[71:70];
assign c[19:18] = a[193:192];
assign c[21:20] = {a[128], a[129]};
assign c[23:22] = a[73:72];
assign c[25:24] = {a[178], a[179]};
assign c[27:26] = a[131:130];
assign c[29:28] = {a[66], a[67]};
assign c[31:30] = {a[180], a[181]};
assign c[33:32] = a[133:132];
assign c[35:34] = {a[68], a[69]};
assign c[37:36] = {a[182], a[183]};
assign c[39:38] = a[127:126];
assign c[41:40] = {a[70], a[71]};
assign c[43:42] = {a[184], a[185]};
assign c[45:44] = a[145:144];
assign c[47:46] = a[81:80];
assign c[49:48] = a[17:16];
assign c[51:50] = a[147:146];
assign c[53:52] = a[83:82];
assign c[55:54] = a[19:18];
assign c[57:56] = a[149:148];
assign c[59:58] = a[85:84];
assign c[61:60] = a[21:20];
assign c[63:62] = a[135:134];
assign c[65:64] = a[87:86];
assign c[67:66] = {a[192], a[193]};
assign c[69:68] = a[145:144];
assign c[71:70] = {a[80], a[81]};
assign c[73:72] = a[25:24];
assign c[75:74] = a[147:146];
assign c[77:76] = {a[82], a[83]};
assign c[79:78] = a[27:26];
assign c[81:80] = a[149:148];
assign c[83:82] = {a[84], a[85]};
assign c[85:84] = a[29:28];
assign c[87:86] = a[143:142];
assign c[89:88] = {a[86], a[87]};
assign c[91:90] = a[31:30];
assign c[93:92] = a[161:160];
assign c[95:94] = a[97:96];
assign c[97:96] = a[33:32];
assign c[99:98] = a[163:162];
assign c[101:100] = a[99:98];
assign c[103:102] = a[35:34];
assign c[105:104] = a[165:164];
assign c[107:106] = a[101:100];
assign c[109:108] = a[37:36];
assign c[111:110] = a[151:150];
assign c[113:112] = a[103:102];
assign c[115:114] = a[39:38];
assign c[117:116] = a[161:160];
assign c[119:118] = {a[96], a[97]};
assign c[121:120] = a[41:40];
assign c[123:122] = a[163:162];
assign c[125:124] = {a[98], a[99]};
assign c[127:126] = a[43:42];
assign c[129:128] = a[165:164];
assign c[131:130] = {a[100], a[101]};
assign c[133:132] = a[45:44];
assign c[135:134] = a[159:158];
assign c[137:136] = {a[102], a[103]};
assign c[139:138] = a[47:46];
assign c[141:140] = a[177:176];
assign c[143:142] = a[113:112];
assign c[145:144] = a[49:48];
assign c[147:146] = a[179:178];
assign c[149:148] = a[115:114];
assign c[151:150] = a[51:50];
assign c[153:152] = a[181:180];
assign c[155:154] = a[117:116];
assign c[157:156] = a[53:52];
assign c[159:158] = a[167:166];
assign c[161:160] = a[119:118];
assign c[163:162] = a[55:54];
assign c[165:164] = a[177:176];
assign c[167:166] = {a[112], a[113]};
assign c[169:168] = a[57:56];
assign c[171:170] = a[179:178];
assign c[173:172] = {a[114], a[115]};
assign c[175:174] = a[59:58];
assign c[177:176] = a[181:180];
assign c[179:178] = {a[116], a[117]};
assign c[181:180] = a[61:60];
assign c[183:182] = a[175:174];
assign c[185:184] = {a[118], a[119]};
assign c[187:186] = a[63:62];
assign c[189:188] = a[193:192];
assign c[191:190] = a[129:128];
assign c[193:192] = a[65:64];
endmodule
/* c == v1(a) */
module v1(a, c);
input [193:0] a;
output [193:0] c;
assign c[1:0] = a[179:178];
assign c[3:2] = {a[122], a[123]};
assign c[5:4] = 0;
assign c[7:6] = a[181:180];
assign c[9:8] = {a[124], a[125]};
assign c[11:10] = 0;
assign c[13:12] = a[183:182];
assign c[15:14] = {a[126], a[127]};
assign c[17:16] = 0;
assign c[19:18] = a[7:6];
assign c[21:20] = a[137:136];
assign c[23:22] = 0;
assign c[25:24] = a[9:8];
assign c[27:26] = a[139:138];
assign c[29:28] = a[75:74];
assign c[31:30] = a[11:10];
assign c[33:32] = a[125:124];
assign c[35:34] = a[77:76];
assign c[37:36] = a[13:12];
assign c[39:38] = a[135:134];
assign c[41:40] = a[79:78];
assign c[43:42] = a[15:14];
assign c[45:44] = a[129:128];
assign c[47:46] = {a[72], a[73]};
assign c[49:48] = {a[186], a[187]};
assign c[51:50] = a[139:138];
assign c[53:52] = {a[74], a[75]};
assign c[55:54] = {a[188], a[189]};
assign c[57:56] = a[133:132];
assign c[59:58] = {a[76], a[77]};
assign c[61:60] = {a[190], a[191]};
assign c[63:62] = a[151:150];
assign c[65:64] = {a[78], a[79]};
assign c[67:66] = a[23:22];
assign c[69:68] = a[137:136];
assign c[71:70] = a[89:88];
assign c[73:72] = 0;
assign c[75:74] = a[155:154];
assign c[77:76] = a[91:90];
assign c[79:78] = 0;
assign c[81:80] = a[141:140];
assign c[83:82] = a[93:92];
assign c[85:84] = 0;
assign c[87:86] = a[151:150];
assign c[89:88] = a[95:94];
assign c[91:90] = 0;
assign c[93:92] = a[145:144];
assign c[95:94] = {a[88], a[89]};
assign c[97:96] = 0;
assign c[99:98] = a[155:154];
assign c[101:100] = {a[90], a[91]};
assign c[103:102] = 0;
assign c[105:104] = a[149:148];
assign c[107:106] = {a[92], a[93]};
assign c[109:108] = 0;
assign c[111:110] = a[167:166];
assign c[113:112] = {a[94], a[95]};
assign c[115:114] = 0;
assign c[117:116] = a[153:152];
assign c[119:118] = a[105:104];
assign c[121:120] = 0;
assign c[123:122] = a[171:170];
assign c[125:124] = a[107:106];
assign c[127:126] = 0;
assign c[129:128] = a[157:156];
assign c[131:130] = a[109:108];
assign c[133:132] = 0;
assign c[135:134] = a[167:166];
assign c[137:136] = a[111:110];
assign c[139:138] = 0;
assign c[141:140] = a[161:160];
assign c[143:142] = {a[104], a[105]};
assign c[145:144] = 0;
assign c[147:146] = a[171:170];
assign c[149:148] = {a[106], a[107]};
assign c[151:150] = 0;
assign c[153:152] = a[165:164];
assign c[155:154] = {a[108], a[109]};
assign c[157:156] = 0;
assign c[159:158] = a[183:182];
assign c[161:160] = {a[110], a[111]};
assign c[163:162] = 0;
assign c[165:164] = a[169:168];
assign c[167:166] = a[121:120];
assign c[169:168] = 0;
assign c[171:170] = a[187:186];
assign c[173:172] = a[123:122];
assign c[175:174] = 0;
assign c[177:176] = a[173:172];
assign c[179:178] = a[125:124];
assign c[181:180] = 0;
assign c[183:182] = a[183:182];
assign c[185:184] = a[127:126];
assign c[187:186] = 0;
assign c[189:188] = a[177:176];
assign c[191:190] = {a[120], a[121]};
assign c[193:192] = 0;
endmodule
/* c == v2(a) */
module v2(a, c);
input [193:0] a;
output [193:0] c;
assign c[1:0] = a[187:186];
assign c[3:2] = 0;
assign c[5:4] = 0;
assign c[7:6] = a[189:188];
assign c[9:8] = 0;
assign c[11:10] = 0;
assign c[13:12] = a[191:190];
assign c[15:14] = 0;
assign c[17:16] = 0;
assign c[19:18] = a[185:184];
assign c[21:20] = 0;
assign c[23:22] = 0;
assign c[25:24] = 0;
assign c[27:26] = a[123:122];
assign c[29:28] = 0;
assign c[31:30] = 0;
assign c[33:32] = a[141:140];
assign c[35:34] = 0;
assign c[37:36] = 0;
assign c[39:38] = a[143:142];
assign c[41:40] = 0;
assign c[43:42] = 0;
assign c[45:44] = a[137:136];
assign c[47:46] = 0;
assign c[49:48] = 0;
assign c[51:50] = a[131:130];
assign c[53:52] = 0;
assign c[55:54] = 0;
assign c[57:56] = a[141:140];
assign c[59:58] = 0;
assign c[61:60] = 0;
assign c[63:62] = a[143:142];
assign c[65:64] = 0;
assign c[67:66] = 0;
assign c[69:68] = a[153:152];
assign c[71:70] = 0;
assign c[73:72] = 0;
assign c[75:74] = a[139:138];
assign c[77:76] = 0;
assign c[79:78] = 0;
assign c[81:80] = a[157:156];
assign c[83:82] = 0;
assign c[85:84] = 0;
assign c[87:86] = a[159:158];
assign c[89:88] = 0;
assign c[91:90] = 0;
assign c[93:92] = a[153:152];
assign c[95:94] = 0;
assign c[97:96] = 0;
assign c[99:98] = a[147:146];
assign c[101:100] = 0;
assign c[103:102] = 0;
assign c[105:104] = a[157:156];
assign c[107:106] = 0;
assign c[109:108] = 0;
assign c[111:110] = a[159:158];
assign c[113:112] = 0;
assign c[115:114] = 0;
assign c[117:116] = a[169:168];
assign c[119:118] = 0;
assign c[121:120] = 0;
assign c[123:122] = a[155:154];
assign c[125:124] = 0;
assign c[127:126] = 0;
assign c[129:128] = a[173:172];
assign c[131:130] = 0;
assign c[133:132] = 0;
assign c[135:134] = a[175:174];
assign c[137:136] = 0;
assign c[139:138] = 0;
assign c[141:140] = a[169:168];
assign c[143:142] = 0;
assign c[145:144] = 0;
assign c[147:146] = a[163:162];
assign c[149:148] = 0;
assign c[151:150] = 0;
assign c[153:152] = a[173:172];
assign c[155:154] = 0;
assign c[157:156] = 0;
assign c[159:158] = a[175:174];
assign c[161:160] = 0;
assign c[163:162] = 0;
assign c[165:164] = a[185:184];
assign c[167:166] = 0;
assign c[169:168] = 0;
assign c[171:170] = a[171:170];
assign c[173:172] = 0;
assign c[175:174] = 0;
assign c[177:176] = a[189:188];
assign c[179:178] = 0;
assign c[181:180] = 0;
assign c[183:182] = a[191:190];
assign c[185:184] = 0;
assign c[187:186] = 0;
assign c[189:188] = a[185:184];
assign c[191:190] = 0;
assign c[193:192] = 0;
endmodule
/trunk/rtl/fsm.v
0,0 → 1,75
/*
Copyright 2011,2012 City University of Hong Kong
Homer Hsing is the author.
This file is part of Tate Bilinear Pairing Core.
 
Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
Tate Bilinear Pairing Core is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
 
You should have received a copy of the GNU Lesser General Public License
along with Tate Bilinear Pairing Core. If not, see http://www.gnu.org/licenses/lgpl.txt
*/
 
/* FSM: finite state machine
* halt if $ctrl == 0$
*/
module FSM(clk, reset, rom_addr, rom_q, ram_a_addr, ram_b_addr, ram_b_w, pe_ctrl, done);
input clk;
input reset;
output [9:0] rom_addr; /* command id */
input [31:0] rom_q; /* command value */
output done;
output [6:0] ram_a_addr; /* a field of $rom_q$ */
output [6:0] ram_b_addr; /* a field of $rom_q$ */
output ram_b_w; /* a field of $rom_q$ */
output [10:0] pe_ctrl; /* a field of $rom_q$ */
reg [9:0] rom_addr;
reg [5:0] ctrl; /* in fact a counter */
reg done;
 
/* I had attempted to avoid finite state machine for a whole day, but I conceded. :) */
parameter S0 = 3'b001, S1 = 3'b010, S2 = 3'b100;
reg [2:0] state;
assign {ram_b_w, ram_b_addr, ram_a_addr, pe_ctrl} = rom_q[25:0];
 
always @ (posedge clk)
if (reset)
begin
state <= S0; rom_addr <= 0;
ctrl <= 0; done <= 0;
end
else
begin
done <= 0;
case (state)
S0:
begin
case (rom_q[31:26])
0: begin state <= S2; done <= 1; end
1: rom_addr <= rom_addr + 1;
default: begin state <= S1; ctrl <= rom_q[31:26]-1; end
endcase
end
S1:
begin
if (ctrl == 1)
begin
rom_addr <= rom_addr + 1;
state <= S0;
end
else
ctrl <= ctrl - 1;
end
endcase
end
endmodule
/trunk/rtl/const.v
0,0 → 1,49
/*
Copyright 2012 Homer Hsing
This file is part of Tiny Tate Bilinear Pairing Core.
 
Tiny Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
Tiny Tate Bilinear Pairing Core is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
 
You should have received a copy of the GNU Lesser General Public License
along with Tiny Tate Bilinear Pairing Core. If not, see http://www.gnu.org/licenses/lgpl.txt
*/
 
/*
* the module of constants
*
* addr out effective
* 1 0 1
* 2 1 1
* 4 + 1
* 8 - 1
* 16 cubic 1
* other 0 0
*/
module const (clk, addr, out, effective);
input clk;
input [6:0] addr;
output reg [197:0] out;
output reg effective; // active high if out is effective
always @ (posedge clk)
begin
effective <= 1;
case (addr)
7'b1: out <= 0;
7'b10: out <= 1;
7'b100: out <= {6'b000101, 192'd0};
7'b1000: out <= {6'b001001, 192'd0};
7'b10000: out <= {6'b010101, 192'd0};
default: begin out <= 0; effective <= 0; end
endcase
end
endmodule

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