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URL https://opencores.org/ocsvn/tiny_tate_bilinear_pairing/tiny_tate_bilinear_pairing/trunk

Subversion Repositories tiny_tate_bilinear_pairing

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    /tiny_tate_bilinear_pairing
    from Rev 5 to Rev 6
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Rev 5 → Rev 6

/trunk/rtl/ram.v
47,18 → 47,20
 
// Port A
always @(posedge clk) begin
a_dout <= mem[a_addr];
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
a_dout <= mem[a_addr];
end
 
// Port B
always @(posedge clk) begin
b_dout <= mem[b_addr];
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
b_dout <= mem[b_addr];
end
 
endmodule
/trunk/rtl/fsm.v
59,10 → 59,10
endcase
 
/* we support two loops with 48 loop times */
parameter LOOP1_START = 22,
LOOP1_END = 117,
LOOP2_START = 280,
LOOP2_END = 293;
parameter LOOP1_START = 9'd22,
LOOP1_END = 9'd117,
LOOP2_START = 9'd280,
LOOP2_END = 9'd293;
reg [46:0] loop1, loop2;
always @ (posedge clk)
107,7 → 107,7
default: ram_a_addr=0;
endcase
parameter CMD_ADD=4, CMD_SUB=8, CMD_CUBIC=16,
parameter CMD_ADD=6'd4, CMD_SUB=6'd8, CMD_CUBIC=6'd16,
ADD=2'd0, SUB=2'd1, CUBIC=2'd2, MULT=2'd3;
 
always @ (posedge clk)
154,5 → 154,5
default: ram_b_addr=0;
endcase
 
assign ram_b_w = (state==WRITE) ? 1 : 0;
assign ram_b_w = (state==WRITE) ? 1'b1 : 1'b0;
endmodule

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