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GNU LESSER GENERAL PUBLIC LICENSE
Version 2.1, February 1999
 
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That's all there is to it!
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n +0000000015 00000 n +0000002960 00000 n +0000010405 00000 n +0000010730 00000 n +0000011744 00000 n +0000011219 00000 n +0000018467 00000 n +0000010446 00000 n +0000010476 00000 n +0000009791 00000 n +0000002980 00000 n +0000004796 00000 n +0000010517 00000 n +0000010547 00000 n +0000009953 00000 n +0000004817 00000 n +0000007167 00000 n +0000010588 00000 n +0000010618 00000 n +0000010115 00000 n +0000007188 00000 n +0000009610 00000 n +0000010659 00000 n +0000010689 00000 n +0000012278 00000 n +0000018683 00000 n +0000011523 00000 n +trailer +<< /Size 32 /Root 1 0 R /Info 2 0 R +/ID [<17FD5896A0448A9DF5F43C971ADE1C70><17FD5896A0448A9DF5F43C971ADE1C70>] +>> +startxref +33808 +%%EOF
/trunk/qtwosComp.v
0,0 → 1,54
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:44:20 08/24/2011
// Design Name:
// Module Name: twosComp
// Project Name:
// Target Devices:
// Tool versions:
// Description: Performs the 2's complement of an N-bit fixed-pont number
// The result is 2N bits long...
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module qtwosComp #(
parameter Q = 15,
parameter N = 32
)
(
input [N-2:0] a,
output [2*N-1:0] b
);
 
reg [2*N-1:0] data;
reg [2*N-1:0] flip;
reg [2*N-1:0] out;
assign b = out;
always @(a)
begin
data <= a; //if you dont put the value into a 2Nb register, when you flip the bits it wont work right
end
always @(data) // This will generate a warning, as a is not referenced
// This is okay, however, as "data" is directly computed from "a"
 
begin
flip <= ~a;
end
always @(flip)
begin
out <= flip + 1;
end
 
endmodule
/trunk/Test_mult.v
0,0 → 1,62
`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:36:55 06/27/2013
// Design Name: qmult
// Module Name: I:/Projects/xilinx/FPInterface/Tester/Tran3005/Test_mult.v
// Project Name: Trancendental
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: qmult
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Test_mult;
 
// Inputs
reg [31:0] i_multiplicand;
reg [31:0] i_multiplier;
 
// Outputs
wire [31:0] o_result;
wire ovr;
// Instantiate the Unit Under Test (UUT)
qmult #(19,32) uut (
.i_multiplicand(i_multiplicand),
.i_multiplier(i_multiplier),
.o_result(o_result),
.ovr(ovr)
);
 
initial begin
$monitor ("%b,%b,%b,%b", i_multiplicand, i_multiplier, o_result, ovr); // Monitor the stuff we care about
// Initialize Inputs
i_multiplicand = 32'b00000000000110010010000111111011; //pi = 3.141592
i_multiplicand[31] = 0; // i_multiplicand sign
i_multiplier[31] = 0; // i_multiplier sign
i_multiplier[30:0] = 0;
 
// Wait 100 ns for global reset to finish
#100;
#100 i_multiplier[0] = 1; // 1.91E-6
end
 
// Add stimulus here
always begin
#10 i_multiplier[30:0] = (i_multiplier[30:0] << 1) + 1; // Why not??
end
endmodule
 
/trunk/TestDiv.v
0,0 → 1,93
`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:48:08 12/29/2013
// Design Name: qdiv
// Module Name: G:/Tran3005/TestDiv.v
// Project Name: Trancendental
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: qdiv
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
 
module TestDiv;
 
// Inputs
reg [31:0] i_dividend;
reg [31:0] i_divisor;
reg i_start;
reg i_clk;
 
// Outputs
wire [31:0] o_quotient_out;
wire o_complete;
wire o_overflow;
 
// Instantiate the Unit Under Test (UUT)
qdiv uut (
.i_dividend(i_dividend),
.i_divisor(i_divisor),
.i_start(i_start),
.i_clk(i_clk),
.o_quotient_out(o_quotient_out),
.o_complete(o_complete),
.o_overflow(o_overflow)
);
 
reg [10:0] count;
 
initial begin
// Initialize Inputs
i_dividend = 1;
i_divisor = 1;
i_start = 0;
i_clk = 0;
count <= 0;
 
// Wait 100 ns for global reset to finish
#100;
 
// Add stimulus here
forever #2 i_clk = ~i_clk;
end
always @(posedge i_clk) begin
if (count == 47) begin
count <= 0;
i_start <= 1'b1;
end
else begin
count <= count + 1;
i_start <= 1'b0;
end
end
 
always @(count) begin
if (count == 47) begin
if ( i_divisor > 32'h1FFFFFFF ) begin
i_divisor <= 1;
i_dividend = (i_dividend << 1) + 3;
end
else
i_divisor = (i_divisor << 1) + 1;
end
end
always @(posedge o_complete)
$display ("%b,%b,%b, %b", i_dividend, i_divisor, o_quotient_out, o_overflow); // Monitor the stuff we care about
 
endmodule
 
/trunk/qmult.v
0,0 → 1,62
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:21:14 08/24/2011
// Design Name:
// Module Name: q15_mult
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module qmult #(
//Parameterized values
parameter Q = 15,
parameter N = 32
)
(
input [N-1:0] i_multiplicand,
input [N-1:0] i_multiplier,
output [N-1:0] o_result,
output reg ovr
);
// The underlying assumption, here, is that both fixed-point values are of the same length (N,Q)
// Because of this, the results will be of length N+N = 2N bits....
// This also simplifies the hand-back of results, as the binimal point
// will always be in the same location...
reg [2*N-1:0] r_result; // Multiplication by 2 values of N bits requires a
// register that is N+N = 2N deep...
reg [N-1:0] r_RetVal;
//--------------------------------------------------------------------------------
assign o_result = r_RetVal; // Only handing back the same number of bits as we received...
// with fixed point in same location...
//---------------------------------------------------------------------------------
always @(i_multiplicand, i_multiplier) begin // Do the multiply any time the inputs change
r_result <= i_multiplicand[N-2:0] * i_multiplier[N-2:0]; // Removing the sign bits from the multiply - that
// would introduce *big* errors
ovr <= 1'b0; // reset overflow flag to zero
end
// This always block will throw a warning, as it uses a & b, but only acts on changes in result...
always @(r_result) begin // Any time the result changes, we need to recompute the sign bit,
r_RetVal[N-1] <= i_multiplicand[N-1] ^ i_multiplier[N-1]; // which is the XOR of the input sign bits... (you do the truth table...)
r_RetVal[N-2:0] <= r_result[N-2+Q:Q]; // And we also need to push the proper N bits of result up to
// the calling entity...
if (r_result[2*N-2:N-1+Q] > 0) // And finally, we need to check for an overflow
ovr <= 1'b1;
end
 
endmodule
/trunk/Tes_add.v
0,0 → 1,86
`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:35:03 06/30/2013
// Design Name: qadd
// Module Name: I:/Projects/xilinx/FPInterface/Tester/Tran3005/Tes_add.v
// Project Name: Trancendental
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: qadd
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
 
module Tes_add;
 
// Inputs
reg [31:0] a;
reg [31:0] b;
 
// Outputs
wire [31:0] c;
 
// Instantiate the Unit Under Test (UUT)
qadd #(19,32) uut (
.a(a),
.b(b),
.c(c)
);
 
// These are to monitor the values...
wire [30:0] c_out;
wire [30:0] a_in;
wire [30:0] b_in;
wire a_sign;
wire b_sign;
wire c_sign;
assign a_in = a[30:0];
assign b_in = b[30:0];
assign c_out = c[30:0];
assign a_sign = a[31];
assign b_sign = b[31];
assign c_sign = c[31];
initial begin
// Initialize Inputs
a[30:0] = 0;
a[31] = 0;
b[31] = 1;
b[30:0] = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
forever begin
#1 a = a+5179347; // why not?
a[31] = 0; // a is negative...
b[31] = 1;
if (a[30:0] > 2.1E9) // input will always be "positive"
begin
a = 0;
b[31] = 1; // b is negative...
b[30:0] = b[30:0] + 3779351;
end
end
 
end
endmodule
 
/trunk/qdiv.v
0,0 → 1,96
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:39:14 08/24/2011
// Design Name:
// Module Name: divider
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Based on my description on youtube:
// http://youtu.be/TEnaPMYiuR8
//
//////////////////////////////////////////////////////////////////////////////////
module qdiv #(
//Parameterized values
parameter Q = 15,
parameter N = 32
)
(
input [N-1:0] i_dividend,
input [N-1:0] i_divisor,
input i_start,
input i_clk,
output [N-1:0] o_quotient_out,
output o_complete,
output o_overflow
);
reg [2*N+Q-3:0] reg_working_quotient; // Our working copy of the quotient
reg [N-1:0] reg_quotient; // Final quotient
reg [N-2+Q:0] reg_working_dividend; // Working copy of the dividend
reg [2*N+Q-3:0] reg_working_divisor; // Working copy of the divisor
reg [N:0] reg_count; // This is obviously a lot bigger than it needs to be, as we only need
// count to N-1+Q but, computing that number of bits requires a
// logarithm (base 2), and I don't know how to do that in a
// way that will work for everyone
reg reg_done; // Computation completed flag
reg reg_sign; // The quotient's sign bit
reg reg_overflow; // Overflow flag
initial reg_done = 1'b1; // Initial state is to not be doing anything
initial reg_overflow = 1'b0; // And there should be no woverflow present
initial reg_sign = 1'b0; // And the sign should be positive
assign o_quotient_out[N-2:0] = reg_working_quotient; // The division results
assign o_quotient_out[N-1] = reg_sign; // The sign of the quotient
assign o_complete = reg_done;
assign o_overflow = reg_overflow;
always @( posedge i_clk ) begin
if( reg_done && i_start ) begin // This is our startup condition
// Need to check for a divide by zero right here, I think....
reg_done <= 1'b0; // We're not done
reg_count <= N+Q-2; // Set the count
reg_working_quotient <= 0; // Clear out the quotient register
reg_working_dividend <= 0; // Clear out the dividend register
reg_working_divisor <= 0; // Clear out the divisor register
reg_overflow <= 1'b0; // Clear the overflow register
 
reg_working_dividend[N+Q-2:Q] <= i_dividend[N-2:0]; // Left-align the dividend in its working register
reg_working_divisor[2*N+Q-3:N+Q-1] <= i_divisor[N-2:0]; // Left-align the divisor into its working register
 
reg_sign <= i_dividend[N-1] ^ i_divisor[N-1]; // Set the sign bit
end
else if(!reg_done) begin
reg_working_divisor <= reg_working_divisor >> 1; // Right shift the divisor (that is, divide it by two - aka reduce the divisor)
reg_count <= reg_count - 1; // Decrement the count
 
// If the dividend is greater than the divisor
if(reg_working_dividend >= reg_working_divisor) begin
reg_working_quotient[reg_count] <= 1'b1; // Set the quotient bit
reg_working_dividend <= reg_working_dividend - reg_working_divisor; // and subtract the divisor from the dividend
end
//stop condition
if(reg_count == 0) begin
reg_done <= 1'b1; // If we're done, it's time to tell the calling process
if (reg_working_quotient[2*N+Q-3:N]>0)
reg_overflow <= 1'b1;
end
else
reg_count <= reg_count - 1;
end
end
endmodule
/trunk/TestMultS.v
0,0 → 1,96
`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:01:19 01/02/2014
// Design Name: qmults
// Module Name: F:/FixedPoint/TestMultS.v
// Project Name: FixedPoint
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: qmults
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
 
module TestMultS;
 
// Inputs
reg [31:0] i_multiplicand;
reg [31:0] i_multiplier;
reg i_start;
reg i_clk;
 
// Outputs
wire [31:0] o_result_out;
wire o_complete;
wire o_overflow;
 
// Instantiate the Unit Under Test (UUT)
qmults uut (
.i_multiplicand(i_multiplicand),
.i_multiplier(i_multiplier),
.i_start(i_start),
.i_clk(i_clk),
.o_result_out(o_result_out),
.o_complete(o_complete),
.o_overflow(o_overflow)
);
 
reg [10:0] count;
 
initial begin
// Initialize Inputs
i_multiplicand = 0;
i_multiplier = 0;
i_start = 0;
i_clk = 0;
count = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Add stimulus here
forever #2 i_clk = ~i_clk;
end
always @(posedge i_clk) begin
if (count == 47) begin
count <= 0;
i_start <= 1'b1;
end
else begin
count <= count + 1;
i_start <= 1'b0;
end
end
 
always @(count) begin
if (count == 47) begin
if ( i_multiplier > 32'h1FFFFFFF ) begin
i_multiplier <= 1;
i_multiplicand = (i_multiplicand << 1) + 3;
end
else
i_multiplier = (i_multiplier << 1) + 1;
end
end
always @(posedge o_complete)
$display ("%b,%b,%b,%b", i_multiplicand, i_multiplier, o_result_out, o_overflow); // Monitor the stuff we care about
 
 
endmodule
 
/trunk/qmults.v
0,0 → 1,90
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:33:36 01/02/2014
// Design Name:
// Module Name: qmults
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module qmults#(
//Parameterized values
parameter Q = 15,
parameter N = 32
)
(
input [N-1:0] i_multiplicand,
input [N-1:0] i_multiplier,
input i_start,
input i_clk,
output [N-1:0] o_result_out,
output o_complete,
output o_overflow
);
 
reg [2*N-2:0] reg_working_result; // a place to accumulate our result
reg [2*N-2:0] reg_multiplier_temp; // a working copy of the multiplier
reg [N-1:0] reg_multiplicand_temp; // a working copy of the umultiplicand
reg [N:0] reg_count; // This is obviously a lot bigger than it needs to be, as we only need
// count to N, but computing that number of bits requires a
// logarithm (base 2), and I don't know how to do that in a
// way that will work for every possibility
reg reg_done; // Computation completed flag
reg reg_sign; // The result's sign bit
reg reg_overflow; // Overflow flag
initial reg_done = 1'b1; // Initial state is to not be doing anything
initial reg_overflow = 1'b0; // And there should be no woverflow present
initial reg_sign = 1'b0; // And the sign should be positive
assign o_result_out[N-2:0] = reg_working_result[N-2+Q:Q]; // The multiplication results
assign o_result_out[N-1] = reg_sign; // The sign of the result
assign o_complete = reg_done; // "Done" flag
assign o_overflow = reg_overflow; // Overflow flag
always @( posedge i_clk ) begin
if( reg_done && i_start ) begin // This is our startup condition
reg_done <= 1'b0; // We're not done
reg_count <= 0; // Reset the count
reg_working_result <= 0; // Clear out the result register
reg_multiplier_temp <= 0; // Clear out the multiplier register
reg_multiplicand_temp <= 0; // Clear out the multiplicand register
reg_overflow <= 1'b0; // Clear the overflow register
 
reg_multiplicand_temp <= i_multiplicand[N-2:0]; // Load the multiplicand in its working register and lose the sign bit
reg_multiplier_temp <= i_multiplier[N-2:0]; // Load the multiplier into its working register and lose the sign bit
 
reg_sign <= i_multiplicand[N-1] ^ i_multiplier[N-1]; // Set the sign bit
end
 
else if (!reg_done) begin
if (reg_multiplicand_temp[reg_count] == 1'b1) // if the appropriate multiplicand bit is 1
reg_working_result <= reg_working_result + reg_multiplier_temp; // then add the temp multiplier
reg_multiplier_temp <= reg_multiplier_temp << 1; // Do a left-shift on the multiplier
reg_count <= reg_count + 1; // Increment the count
 
//stop condition
if(reg_count == N) begin
reg_done <= 1'b1; // If we're done, it's time to tell the calling process
if (reg_working_result[2*N-2:N-1+Q] > 0) // Check for an overflow
reg_overflow <= 1'b1;
// else
// reg_count <= reg_count + 1; // Increment the count
end
end
end
endmodule
/trunk/ReadMe.txt
0,0 → 1,239
Verilog Fixed point math library
 
Original work by Sam Skalicky, originally found here:
http://opencores.org/project,fixed_point_arithmetic_parameterized
 
Extended, updated, and heavily commented by Tom Burke (tomburkeii@gmail.com)
 
This library includes the basic math functions for the Verilog Language,
for implementation on FPGAs.
 
All units have been simulated and synthesized for Xilinx Spartan 3E devices
using the Xilinx ISE WebPack tools v14.7
 
These math routines use a signed magnitude Q,N format, where N is the total
number of bits used, and Q is the number of fractional bits used. For
instance, 15,32 would represent a 32-bit number with 15 fractional bits,
16 integer bits, and 1 sign bit as shown below:
 
|1|<- N-Q-1 bits ->|<--- Q bits -->|
|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|
 
This library contains the following modules:
qadd.v - Addition module; adds 2 numbers of any sign.
qdiv.v - Division module; divides two numbers using a right-shift and
subtract algorithm - requires an input clock
qmult.v - Multiplication module; purely combinational for systems that
will support it
qmults.v - Multiplication module; uses a left-shift and add algorithm -
requires an input clock (for systems that cannot support
the synthesis of a combinational multiplier)
Test_add.v - Test fixture for the qadd.v module
Test_mult.v - Test fixture for the qmult.v module
TestDiv.v - Test fixture for the qdiv.v module
TestMultS.v - Test fixture for the qmults.v module
 
These math routines default to a (Q,N) of (15,32), but are easily customizable
to your application by changing their input parameters. For instance, an
unmodified use of (15,32) would look something like this:
 
qadd my_adder(
.a(addend_a),
.b(addend_b),
.c(result)
);
 
To change this to an (8,23) notation, for instance, the same module would be
instantiated thusly:
 
qadd #(8,23) my_adder(
.a(addend_a),
.b(addend_b),
.c(result)
);
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The following is a description of each module
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
qadd.v - A simple combinational addition module.
 
sum = addend + addend
 
Input format:
|1|<- N-Q-1 bits ->|<--- Q bits -->|
|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|
 
Inputs:
a - addend 1
b - addend 2
 
Output format:
|1|<- N-Q-1 bits ->|<--- Q bits -->|
|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|
 
Output:
c - result
NOTE: There is no error detection for an overflow. It is up to the designer
to ensure that an overflow cannot occur!!
 
Example usage:
qadd #(Q,N) my_adder(
.a(addend_a),
.b(addend_b),
.c(result)
);
For subtraction, set the sign bit for the negative number. (subtraction is
the addition of a negative, right?)
 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
qmult.v - A simple combinational multiplication module.
 
Input format:
|1|<- N-Q-1 bits ->|<--- Q bits -->|
|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|
 
Inputs:
i_multiplicand - multiplicand
i_multiplier - multiplier
 
Output format:
|1|<- N-Q-1 bits ->|<--- Q bits -->|
|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|
 
Output:
o_result - result
ovr - overflow flag
NOTE: This module assumes a system that supports the synthesis of
combinational multipliers. If your device/synthesizer does not
support this for your particular application, then use the
"qmults.v" module.
 
NOTE: Notice that the output format is identical to the input format! To
properly use this module, you need to either ensure that you maximum
result never exceeds the format, or incorporate the overflow flag
into your design
 
Example usage:
qmult #(Q,N) my_multiplier(
.i_multiplicand(multiplicand),
.i_multiplier(multiplier),
.o_result(result),
.ovr(overflow_flag)
);
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
qmults.v - A multi-clock multiplication module that uses a left-shift
and add algorithm.
result = multiplicand x multiplier
 
Input format:
|1|<- N-Q-1 bits ->|<--- Q bits -->|
|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|
 
Inputs:
i_multiplicand - multiplicand
i_multiplier - multiplier
i_start - Start flag; set this bit high ("1") to start the
operation when the last operation is completed. This
bit is ignored until o_complete is asserted.
i_clk - input clock; internal workings occur on the rising edge
 
Output format:
|1|<- N-Q-1 bits ->|<--- Q bits -->|
|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|
 
Output:
o_result_out - result
o_complete - computation complete flag; asserted ("1") when the
operation is completed
o_overflow - overflow flag; asserted ("1") to indicate that an
overflow has occurred.
NOTE: This module is "time deterministic ." - that is, it should always
take the same number of clock cycles to complete an operation,
regardless of the inputs (N+1 clocks)
 
NOTE: Notice that the output format is identical to the input format! To
properly use this module, you need to either ensure that you maximum
result never exceeds the format, or incorporate the overflow flag
into your design
 
Example usage:
qmults #(Q,N) my_multiplier(
.i_multiplicand(multiplicand),
.i_multiplier(multiplier),
.i_start(start),
.i_clk(clock),
.o_result(result),
.o_complete(done),
.o_overflow(overflow_flag)
);
The qmults.v module begins computation when the start conditions are met:
o_complete == 1'b1;
i_start == 1'b1;
 
 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
qdiv.v - A multi-clock division module that uses a right-shift
and add algorithm.
 
quotient = dividend / divisor
 
Input format:
|1|<- N-Q-1 bits ->|<--- Q bits -->|
|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|
 
Inputs:
i_dividend - dividend
i_divisor - divisor
i_start - Start flag; set this bit high ("1") to start the
operation when the last operation is completed. This
bit is ignored until o_complete is asserted.
i_clk - input clock; internal workings occur on the rising edge
 
Output format:
|1|<- N-Q-1 bits ->|<--- Q bits -->|
|S|IIIIIIIIIIIIIIII|FFFFFFFFFFFFFFF|
 
Output:
o_quotient_out - result
o_complete - computation complete flag; asserted ("1") when the
operation is completed
o_overflow - overflow flag; asserted ("1") to indicate that an
overflow has occurred.
NOTE: This module is "time deterministic ." - that is, it should always
take the same number of clock cycles to complete an operation,
regardless of the inputs (N+Q+1 clocks)
 
NOTE: Notice that the output format is identical to the input format! To
properly use this module, you need to either ensure that you maximum
result never exceeds the format, or incorporate the overflow flag
into your design
 
Example usage:
qdiv #(Q,N) my_divider(
.i_dividend(dividend),
.i_divisor(divisor),
.i_start(start),
.i_clk(clock),
.o_quotient_out(result),
.o_complete(done),
.o_overflow(overflow_flag)
);
The qdiv.v module begins computation when the start conditions are met:
o_complete == 1'b1;
i_start == 1'b1;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Suggestions, Kudos, or Complaints? Feel free to contact me - but remember,
this stuff is free!
 
 
 
/trunk/Test_add.v
0,0 → 1,86
`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:35:03 06/30/2013
// Design Name: qadd
// Module Name: I:/Projects/xilinx/FPInterface/Tester/Tran3005/Tes_add.v
// Project Name: Trancendental
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: qadd
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
 
module Test_add;
 
// Inputs
reg [31:0] a;
reg [31:0] b;
 
// Outputs
wire [31:0] c;
 
// Instantiate the Unit Under Test (UUT)
qadd #(19,32) uut (
.a(a),
.b(b),
.c(c)
);
 
// These are to monitor the values...
wire [30:0] c_out;
wire [30:0] a_in;
wire [30:0] b_in;
wire a_sign;
wire b_sign;
wire c_sign;
assign a_in = a[30:0];
assign b_in = b[30:0];
assign c_out = c[30:0];
assign a_sign = a[31];
assign b_sign = b[31];
assign c_sign = c[31];
initial begin
// Initialize Inputs
a[30:0] = 0;
a[31] = 0;
b[31] = 1;
b[30:0] = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
forever begin
#1 a = a+5179347; // why not?
a[31] = 0; // a is negative...
b[31] = 1;
if (a[30:0] > 2.1E9) // input will always be "positive"
begin
a = 0;
b[31] = 1; // b is negative...
b[30:0] = b[30:0] + 3779351;
end
end
 
end
endmodule
 
/trunk/qadd.v
0,0 → 1,72
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:28:18 08/24/2011
// Design Name:
// Module Name: q15_add
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module qadd #(
//Parameterized values
parameter Q = 15,
parameter N = 32
)
(
input [N-1:0] a,
input [N-1:0] b,
output [N-1:0] c
);
 
reg [N-1:0] res;
 
assign c = res;
 
always @(a,b) begin
// both negative or both positive
if(a[N-1] == b[N-1]) begin // Since they have the same sign, absolute magnitude increases
res[N-2:0] = a[N-2:0] + b[N-2:0]; // So we just add the two numbers
res[N-1] = a[N-1]; // and set the sign appropriately... Doesn't matter which one we use,
// they both have the same sign
// Do the sign last, on the off-chance there was an overflow...
end // Not doing any error checking on this...
// one of them is negative...
else if(a[N-1] == 0 && b[N-1] == 1) begin // subtract a-b
if( a[N-2:0] > b[N-2:0] ) begin // if a is greater than b,
res[N-2:0] = a[N-2:0] - b[N-2:0]; // then just subtract b from a
res[N-1] = 0; // and manually set the sign to positive
end
else begin // if a is less than b,
res[N-2:0] = b[N-2:0] - a[N-2:0]; // we'll actually subtract a from b to avoid a 2's complement answer
if (res[N-2:0] == 0)
res[N-1] = 0; // I don't like negative zero....
else
res[N-1] = 1; // and manually set the sign to negative
end
end
else begin // subtract b-a (a negative, b positive)
if( a[N-2:0] > b[N-2:0] ) begin // if a is greater than b,
res[N-2:0] = a[N-2:0] - b[N-2:0]; // we'll actually subtract b from a to avoid a 2's complement answer
if (res[N-2:0] == 0)
res[N-1] = 0; // I don't like negative zero....
else
res[N-1] = 1; // and manually set the sign to negative
end
else begin // if a is less than b,
res[N-2:0] = b[N-2:0] - a[N-2:0]; // then just subtract a from b
res[N-1] = 0; // and manually set the sign to positive
end
end
end
endmodule

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