URL
https://opencores.org/ocsvn/w11/w11/trunk
Subversion Repositories w11
Compare Revisions
- This comparison shows the changes necessary to convert path
/w11/trunk
- from Rev 30 to Rev 29
- ↔ Reverse comparison
Rev 30 → Rev 29
/tools/tcl/ibd_rhrp/.cvsignore
File deleted
/tools/tcl/ibd_rhrp/util.tcl
File deleted
tools/tcl/ibd_rhrp
Property changes :
Deleted: svn:ignore
## -1,34 +0,0 ##
-*.dep_ghdl
-*.dep_isim
-*.dep_xst
-work-obj93.cf
-*.vcd
-*.ghw
-*.sav
-*.tmp
-*.exe
-ise
-xflow.his
-*.ngc
-*.ncd
-*.pcf
-*.bit
-*.msk
-isim
-isim.log
-isim.wdb
-fuse.log
-*_[sft]sim.vhd
-*_tsim.sdf
-*_xst.log
-*_tra.log
-*_twr.log
-*_map.log
-*_par.log
-*_tsi.log
-*_pad.log
-*_bgn.log
-*_svn.log
-*_sum.log
-*_[dsft]sim.log
-pkgIndex.tcl
Index: tools/tcl/ibd_ibmon/util.tcl
===================================================================
--- tools/tcl/ibd_ibmon/util.tcl (revision 30)
+++ tools/tcl/ibd_ibmon/util.tcl (nonexistent)
@@ -1,282 +0,0 @@
-# $Id: util.tcl 668 2015-04-25 14:31:19Z mueller $
-#
-# Copyright 2015- by Walter F.J. Mueller
-#
-# This program is free software; you may redistribute and/or modify it under
-# the terms of the GNU General Public License as published by the Free
-# Software Foundation, either version 2, or at your option any later version.
-#
-# This program is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-# for complete details.
-#
-# Revision History:
-# Date Rev Version Comment
-# 2015-04-25 668 1.0 Initial version
-#
-
-package provide ibd_ibmon 1.0
-
-package require rutil
-package require rlink
-
-namespace eval ibd_ibmon {
- #
- # setup register descriptions for ibd_ibmon
- #
- regdsc CNTL {conena 5} {remena 4} {locena 3} {wena 2} {stop 1} {start 0}
- regdsc STAT {bsize 15 3} {wrap 0}
- regdsc ADDR {laddr 15 14} {waddr 1 2}
- #
- regdsc DAT3 {burst 15} {tout 14} {nak 13} {ack 12} \
- {busy 11} {we 9} {rmw 8} {ndlymsb 7 8}
- regdsc DAT2 {ndlylsb 15 6} {nbusy 9 10}
- regdsc DAT0 {be1 15} {be0 14} {racc 13} {addr 12 12} {cacc 0}
- #
- # 'pseudo register', describes 1st word in return list element of read proc
- # all flag bits from DAT3 and DAT0
- regdsc FLAGS {burst 11} {tout 10} {nak 9} {ack 8} \
- {busy 7} {cacc 5} {racc 4} {rmw 3} {be1 2} {be0 1} {we 0}
- #
- # setup: amap definitions for rbd_rbmon
- #
- proc setup {{cpu "cpu0"} {base 0160000}} {
- $cpu imap -insert im.cntl [expr {$base + 000}]
- $cpu imap -insert im.stat [expr {$base + 002}]
- $cpu imap -insert im.hilim [expr {$base + 004}]
- $cpu imap -insert im.lolim [expr {$base + 006}]
- $cpu imap -insert im.addr [expr {$base + 010}]
- $cpu imap -insert im.data [expr {$base + 012}]
- }
- #
- # init: reset rbd_rbmon (stop, reset alim)
- #
- proc init {{cpu "cpu0"}} {
- $cpu cp \
- -wibr im.cntl [regbld ibd_ibmon::CNTL stop] \
- -wibr im.hilim 0177776 \
- -wibr im.lolim 0160000 \
- -wibr im.addr 0x0000
- }
- #
- # start: start the rbmon
- #
- proc start {{cpu "cpu0"} {opts {}}} {
- array set defs { conena 1 remena 1 locena 1 wena 1 }
- array set defs $opts
- $cpu cp -wibr im.cntl [regbld ibd_ibmon::CNTL start \
- [list wena $defs(wena)] \
- [list locena $defs(locena)] \
- [list remena $defs(remena)] \
- [list conena $defs(conena)] \
- ]
- }
- #
- # stop: stop the rbmon
- #
- proc stop {{cpu "cpu0"}} {
- $cpu cp -wibr im.cntl [regbld ibd_ibmon::CNTL stop]
- }
- #
- # read: read nent last entries (by default all)
- #
- proc read {{cpu "cpu0"} {nent -1}} {
- $cpu cp -ribr im.addr raddr \
- -ribr im.stat rstat
-
- set bsize [regget ibd_ibmon::STAT(bsize) $rstat]
- set amax [expr {( 512 << $bsize ) - 1}]
- if {$nent == -1} { set nent $amax }
-
- set laddr [regget ibd_ibmon::ADDR(laddr) $raddr]
- set nval $laddr
- if {[regget ibd_ibmon::STAT(wrap) $rstat]} { set nval $amax }
-
- if {$nent > $nval} {set nent $nval}
- if {$nent == 0} { return {} }
-
- set caddr [expr {( $laddr - $nent ) & $amax}]
- $cpu cp -wibr im.addr [regbld ibd_ibmon::ADDR [list laddr $caddr]]
-
- set rval {}
-
- set nrest $nent
- while {$nrest > 0} {
- set nblk [expr {$nrest << 2}]
- if {$nblk > 256} {set nblk 256}
- set iaddr [$cpu imap im.data]
- $cpu cp -rbibr $iaddr $nblk rawdat
-
- foreach {d0 d1 d2 d3} $rawdat {
- set d3burst [regget ibd_ibmon::DAT3(burst) $d3]
- set d3tout [regget ibd_ibmon::DAT3(tout) $d3]
- set d3nak [regget ibd_ibmon::DAT3(nak) $d3]
- set d3ack [regget ibd_ibmon::DAT3(ack) $d3]
- set d3busy [regget ibd_ibmon::DAT3(busy) $d3]
- set d3we [regget ibd_ibmon::DAT3(we) $d3]
- set d3rmw [regget ibd_ibmon::DAT3(rmw) $d3]
- set d0be1 [regget ibd_ibmon::DAT0(be1) $d0]
- set d0be0 [regget ibd_ibmon::DAT0(be0) $d0]
- set d0racc [regget ibd_ibmon::DAT0(racc) $d0]
- set d0addr [regget ibd_ibmon::DAT0(addr) $d0]
- set d0cacc [regget ibd_ibmon::DAT0(cacc) $d0]
-
- set eflag [regbld ibd_ibmon::FLAGS \
- [list burst $d3burst] \
- [list tout $d3tout] \
- [list nak $d3nak] \
- [list ack $d3ack] \
- [list busy $d3busy] \
- [list cacc $d0cacc] \
- [list racc $d0racc] \
- [list rmw $d3rmw] \
- [list be1 $d0be1] \
- [list be0 $d0be0] \
- [list we $d3we] \
- ]
-
- set edelay [expr {( [regget ibd_ibmon::DAT3(ndlymsb) $d3] << 6 ) |
- [regget ibd_ibmon::DAT2(ndlylsb) $d2] }]
- set enbusy [regget ibd_ibmon::DAT2(nbusy) $d2]
- set edata $d1
- set eaddr [expr {0160000 | ($d0addr<<1)}]
- lappend rval [list $eflag $eaddr $edata $edelay $enbusy]
- }
-
- set nrest [expr {$nrest - ( $nblk >> 2 ) }]
- }
-
- $cpu cp -wibr im.addr $raddr
-
- return $rval
- }
- #
- # print: print ibmon data (optionally also read them)
- #
- proc print {{cpu "cpu0"} {mondat -1}} {
-
- if {[llength $mondat] == 1} {
- set ele [lindex $mondat 0]
- if {[llength $ele] == 1} {
- set nent [lindex $ele 0]
- set mondat [read $cpu $nent]
- }
- }
-
- set rval {}
- set edlymax 16383
-
- set eind [expr {1 - [llength $mondat] }]
- append rval \
- " ind addr data delay nbsy btnab-crm10w acc-mode"
-
- set mtout [regbld ibd_ibmon::FLAGS tout ]
- set mnak [regbld ibd_ibmon::FLAGS nak ]
- set mack [regbld ibd_ibmon::FLAGS ack ]
- set mbusy [regbld ibd_ibmon::FLAGS busy ]
- set mcacc [regbld ibd_ibmon::FLAGS cacc ]
- set mracc [regbld ibd_ibmon::FLAGS racc ]
- set mrmw [regbld ibd_ibmon::FLAGS rmw ]
- set mbe1 [regbld ibd_ibmon::FLAGS be1 ]
- set mbe0 [regbld ibd_ibmon::FLAGS be0 ]
- set mwe [regbld ibd_ibmon::FLAGS we ]
-
- foreach {ele} $mondat {
- foreach {eflag eaddr edata edly enbusy} $ele { break }
-
- set ftout [expr {$eflag & $mtout} ]
- set fnak [expr {$eflag & $mnak} ]
- set fack [expr {$eflag & $mack} ]
- set fbusy [expr {$eflag & $mbusy} ]
- set fcacc [expr {$eflag & $mcacc} ]
- set fracc [expr {$eflag & $mracc} ]
- set frmw [expr {$eflag & $mrmw} ]
- set fbe1 [expr {$eflag & $mbe1} ]
- set fbe0 [expr {$eflag & $mbe0} ]
- set fwe [expr {$eflag & $mwe} ]
-
- set prw "r"
- set pmod " "
- set pwe1 " "
- set pwe0 " "
-
- if {$fwe } {
- set prw "w"
- set pwe1 "0"
- set pwe0 "0"
- if {$fbe1} { set pwe1 "1"}
- if {$fbe0} { set pwe0 "1"}
- }
- if {$frmw} { set pmod "m"}
-
- set prmw "$pmod$prw$pwe1$pwe0"
- set pacc "loc"
- if {$fcacc} { set pacc "con"}
- if {$fracc} { set pacc "rem"}
-
- set pedly [expr {$edly!=$edlymax ? [format "%5d" $edly] : " --"}]
- set ename [format "%6.6o" $eaddr]
- set comment ""
- if {$fnak} {append comment " NAK=1!"}
- if {$ftout} {append comment " TOUT=1!"}
- if {[$cpu imap -testaddr $eaddr]} {set ename [$cpu imap -name $eaddr]}
- append rval [format \
- "\n%5d %-10s %6.6o %5s %4d %s %s %s %s" \
- $eind $ename $edata $pedly $enbusy [pbvi b12 $eflag] \
- $prmw $pacc $comment]
- incr eind
- }
-
- return $rval
- }
-
- #
- # raw_edata: prepare edata lists for raw data reads in tests
- # args is list of {eflag eaddr edata enbusy} sublists
-
- proc raw_edata {edat emsk args} {
- upvar $edat uedat
- upvar $emsk uemsk
- set uedat {}
- set uemsk {}
-
- set m3 [rutil::com16 [regbld ibd_ibmon::DAT3 {ndlymsb -1}]]; # all but ndly
- set m2 [rutil::com16 [regbld ibd_ibmon::DAT2 {ndlylsb -1}]]; # all but ndly
- set m1 0xffff
- set m0 0xffff
-
- foreach line $args {
- foreach {eflags eaddr edata enbusy} $line { break }
- set d3 [regbld ibd_ibmon::DAT3 [list flags $eflags]]
- set d2 [regbld ibd_ibmon::DAT2 [list nbusy $enbusy]]
- if {$edata ne ""} {
- set m1 0xffff
- set d1 $edata
- } else {
- set m1 0x0000
- set d1 0x0000
- }
- set d0 $eaddr
-
- lappend uedat $d0 $d1 $d2 $d3
- lappend uemsk $m0 $m1 $m2 $m3
- }
-
- return ""
- }
-
- #
- # raw_check: check raw data against expect values prepared by raw_edata
- #
- proc raw_check {{cpu "cpu0"} edat emsk} {
-
- $cpu cp \
- -ribr im.addr -edata [llength $edat] \
- -wibr im.addr 0 \
- -rbibr im.data [llength $edat] -edata $edat $emsk \
- -ribr im.addr -edata [llength $edat]
- return ""
- }
-
-}
Index: tools/tcl/ibd_ibmon/.cvsignore
===================================================================
--- tools/tcl/ibd_ibmon/.cvsignore (revision 30)
+++ tools/tcl/ibd_ibmon/.cvsignore (nonexistent)
@@ -1 +0,0 @@
-pkgIndex.tcl
Index: tools/tcl/ibd_ibmon
===================================================================
--- tools/tcl/ibd_ibmon (revision 30)
+++ tools/tcl/ibd_ibmon (nonexistent)
tools/tcl/ibd_ibmon
Property changes :
Deleted: svn:ignore
## -1,34 +0,0 ##
-*.dep_ghdl
-*.dep_isim
-*.dep_xst
-work-obj93.cf
-*.vcd
-*.ghw
-*.sav
-*.tmp
-*.exe
-ise
-xflow.his
-*.ngc
-*.ncd
-*.pcf
-*.bit
-*.msk
-isim
-isim.log
-isim.wdb
-fuse.log
-*_[sft]sim.vhd
-*_tsim.sdf
-*_xst.log
-*_tra.log
-*_twr.log
-*_map.log
-*_par.log
-*_tsi.log
-*_pad.log
-*_bgn.log
-*_svn.log
-*_sum.log
-*_[dsft]sim.log
-pkgIndex.tcl
Index: tools/tcl/rbemon/test_regs.tcl
===================================================================
--- tools/tcl/rbemon/test_regs.tcl (revision 30)
+++ tools/tcl/rbemon/test_regs.tcl (revision 29)
@@ -1,6 +1,6 @@
-# $Id: test_regs.tcl 661 2015-04-03 18:28:41Z mueller $
+# $Id: test_regs.tcl 516 2013-05-05 21:24:52Z mueller $
#
-# Copyright 2011-2015 by Walter F.J. Mueller
+# Copyright 2011-2013 by Walter F.J. Mueller
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
@@ -13,7 +13,6 @@
#
# Revision History:
# Date Rev Version Comment
-# 2015-04-03 661 1.1 drop estatdef, use estaterr; fix test 4
# 2011-12-18 440 1.0.1 increase npoll in "CNTL.clr->0" test
# 2011-04-02 375 1.0 Initial version
#
@@ -29,6 +28,8 @@
# Basic tests with rbd_eyemon registers
#
proc test_regs {} {
+ set esdval 0x00
+ set esdmsk [regbld rlink::STAT {stat -1}]
#
set errcnt 0
rlc errcnt -clear
@@ -40,7 +41,7 @@
# ensure that last value 0x0 -> go=0
foreach val [list [regbld rbemon::CNTL ena01] [regbld rbemon::CNTL ena10] \
[regbld rbemon::CNTL go] 0x0 ] {
- rlc exec \
+ rlc exec -estatdef $esdval $esdmsk \
-wreg em.cntl $val \
-rreg em.cntl -edata $val
}
@@ -48,7 +49,7 @@
#-------------------------------------------------------------------------
rlc log " test 1b: write/read rdiv"
foreach val [list [regbld rbemon::RDIV {rdiv -1}] 0x0 ] {
- rlc exec \
+ rlc exec -estatdef $esdval $esdmsk \
-wreg em.rdiv $val \
-rreg em.rdiv -edata $val
}
@@ -57,7 +58,7 @@
rlc log " test 1c: write/read addr"
set amax [regget rbemon::ADDR(addr) -1]
foreach addr [list 0x1 $amax 0x0] {
- rlc exec \
+ rlc exec -estatdef $esdval $esdmsk \
-wreg em.addr $addr \
-rreg em.addr -edata $addr
}
@@ -65,7 +66,7 @@
#-------------------------------------------------------------------------
rlc log " test 2: verify addr increments on data reads"
foreach addr [list 0x0 0x011 [expr {$amax - 1}]] {
- rlc exec \
+ rlc exec -estatdef $esdval $esdmsk \
-wreg em.addr $addr \
-rreg em.data \
-rreg em.addr -edata [expr {( $addr + 1 ) & $amax}] \
@@ -76,17 +77,20 @@
#-------------------------------------------------------------------------
rlc log " test 3: verify rberr on DATA write and DATE read if in go state"
rlc exec \
- -wreg em.data 0x0000 -estaterr \
- -wreg em.cntl [regbld rbemon::CNTL go] \
- -rreg em.data -estaterr
+ -wreg em.data 0x0000 -estat [regbld rlink::STAT rberr] $esdmsk \
+ -wreg em.cntl [regbld rbemon::CNTL go] -estat $esdval $esdmsk \
+ -rreg em.data -estat [regbld rlink::STAT rberr] $esdmsk
#
#-------------------------------------------------------------------------
rlc log " test 4: verify that CNTL.clr returns to 0"
- set npoll 64; # wait 64 rbus cycles, than test
- rlc exec \
+ set npoll 48
+ set edat {}
+ set emsk {}
+ for {set i 0} {$i < $npoll} {incr i} { lappend edat 0x0000 }
+ for {set i 1} {$i < $npoll} {incr i} { lappend emsk 0xffff }
+ rlc exec -estatdef $esdval $esdmsk \
-wreg em.cntl [regbld rbemon::CNTL clr] \
- -rblk em.cntl $npoll \
- -rreg em.cntl -edata 0x0
+ -rblk em.cntl $npoll -edata $edat $emsk
#
incr errcnt [rlc errcnt -clear]
return $errcnt
Index: tools/tcl/rw11/util.tcl
===================================================================
--- tools/tcl/rw11/util.tcl (revision 30)
+++ tools/tcl/rw11/util.tcl (revision 29)
@@ -1,4 +1,4 @@
-# $Id: util.tcl 675 2015-05-08 21:05:08Z mueller $
+# $Id: util.tcl 632 2015-01-11 12:30:03Z mueller $
#
# Copyright 2013-2015 by Walter F.J. Mueller
#
@@ -13,10 +13,7 @@
#
# Revision History:
# Date Rev Version Comment
-# 2015-05-08 675 1.3.2 w11a start/stop/suspend overhaul
-# 2015-03-28 660 1.3.1 add setup_cntl
-# 2015-03-21 659 1.3 setup_sys: add RPRM (later renamed to RHRP)
-# 2015-01-09 632 1.2.3 setup_sys: use rlc set; setup_sys: add RL11
+# 2015-01-09 632 1.2.3 setup_sys: use rlc set; setup_sys: add rl11
# 2014-07-26 575 1.2.2 run_pdpcp: add tout argument
# 2014-06-27 565 1.2.1 temporarily hide RL11
# 2014-06-08 561 1.2 setup_sys: add RL11
@@ -34,17 +31,7 @@
namespace eval rw11 {
#
- # setup register descriptions for rw11 -------------------------------------
- #
- # rlink stat usage for rw11
- regdsc STAT {cmderr 7} {cmdmerr 6} {cpususp 5} {cpugo 4} \
- {attn 3} {rbtout 2} {rbnak 1} {rberr 0}
-
- # check cmderr and rb(tout|nak|err)
- variable STAT_DEFMASK [regbld rw11::STAT cmderr rbtout rbnak rberr]
-
- #
- # setup_cpu: create w11 cpu system -----------------------------------------
+ # setup_cpu: create w11 cpu system
#
proc setup_cpu {} {
rlc set baseaddr 16
@@ -52,12 +39,12 @@
rlc set basestat 2
rlink::setup; # basic rlink defs
rw11 rlw rls w11a 1; # create 1 w11a cpu
- cpu0 cp -creset; # reset CPU
+ cpu0 cp -reset; # reset CPU
return ""
}
#
- # setup_sys: create full system --------------------------------------------
+ # setup_sys: create full system
#
proc setup_sys {} {
if {[info commands rlw] eq ""} {
@@ -67,7 +54,6 @@
cpu0 add dl11 -base 0176500 -lam 2
cpu0 add rk11
cpu0 add rl11
- cpu0 add rhrp
cpu0 add lp11
cpu0 add pc11
rlw start
@@ -75,7 +61,7 @@
}
#
- # setup_tt: setup terminals ------------------------------------------------
+ # setup_tt: setup terminals
#
proc setup_tt {{cpu "cpu0"} {optlist {}}} {
# process and check options
@@ -122,7 +108,7 @@
}
#
- # setup_ostr: setup Ostream device (currently lp or pp) --------------------
+ # setup_ostr: setup Ostream device (currently lp or pp)
#
proc setup_ostr {cpu unit optlist} {
# process and check options
@@ -149,7 +135,7 @@
}
#
- # setup_lp: setup printer --------------------------------------------------
+ # setup_lp: setup printer
#
proc setup_lp {{cpu "cpu0"} {optlist {}}} {
# process and check options
@@ -160,7 +146,7 @@
}
}
#
- # setup_pp: setup paper puncher --------------------------------------------
+ # setup_pp: setup paper puncher
#
proc setup_pp {{cpu "cpu0"} {optlist {}}} {
# process and check options
@@ -172,7 +158,7 @@
}
#
- # run_pdpcp: execute pdpcp type command file -------------------------------
+ # run_pdpcp: execute pdpcp type command file
#
proc run_pdpcp {fname {tout 10.} {cpu "cpu0"}} {
rlc errcnt -clear
@@ -185,23 +171,4 @@
return $errcnt
}
- #
- # setup_cntl: setup a controller (used for I/O test benches) ---------------
- #
- proc setup_cntl {cpu ctype cname} {
- if {![rlw get started]} { # start rlw, if needed
- rlw start
- rls server -stop
- }
-
- set ccmd ${cpu}${cname}; # build controller command
- if {[info commands $ccmd] eq ""} { # create controller, if needed
- $cpu add $ctype
- }
- if {![$ccmd get started]} { # start it, if needed
- $ccmd start
- }
- return ""
- }
-
}
/tools/tcl/rw11/tbench.tcl
1,6 → 1,6
# $Id: tbench.tcl 676 2015-05-09 16:31:54Z mueller $ |
# $Id: tbench.tcl 607 2014-11-30 20:02:48Z mueller $ |
# |
# Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
# This program is free software; you may redistribute and/or modify it under |
# the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-05-09 676 2.1 use 'rlc log -bare' instead of 'puts' |
# 2014-11-30 607 2.0 use new rlink v4 iface |
# 2013-04-26 510 1.0 Initial version (extracted from util.tcl) |
# |
44,7 → 43,7
set fh [open "$::env(RETROBASE)/tools/tbench/$fname"] |
while {[gets $fh line] >= 0} { |
if {[string match "#*" $line]} { |
if {[string match "##*" $line]} { rlc log -bare $line } |
if {[string match "##*" $line]} { puts $line } |
} elseif {[string match "@*" $line]} { |
incr errcnt [tbench_list $line] |
} else { |
55,7 → 54,7
} else { |
incr errcnt [tbench_step $lname] |
} |
rlc log -bare [format "%s: %s" $lname [rutil::errcnt2txt $errcnt]] |
puts [format "%s: %s" $lname [rutil::errcnt2txt $errcnt]] |
return $errcnt |
} |
|
67,7 → 66,7
set cpu cpu0 |
source "$::env(RETROBASE)/tools/tbench/$fname" |
set errcnt [rlc errcnt] |
rlc log -bare [format "%s: %s" $fname [rutil::errcnt2txt $errcnt]] |
puts [format "%s: %s" $fname [rutil::errcnt2txt $errcnt]] |
return $errcnt |
} |
|
/tools/tcl/rlink/util.tcl
1,4 → 1,4
# $Id: util.tcl 661 2015-04-03 18:28:41Z mueller $ |
# $Id: util.tcl 617 2014-12-21 14:18:53Z mueller $ |
# |
# Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
27,11 → 27,9
|
namespace eval rlink { |
regdsc STAT {stat 7 4} {attn 3} {rbtout 2} {rbnak 1} {rberr 0} |
variable STAT_DEFMASK [regbld rlink::STAT rbtout rbnak rberr] |
|
regdsc RLCNTL {anena 15} {atoena 14} {atoval 7 8} |
regdsc RLSTAT {lcmd 15 8} {babo 7} {rbsize 2 3} |
|
# |
# 'pseudo register', describes 3rd word in return list element for -rlist |
regdsc FLAGS {vol 16} \ |
{chkdata 13} {chkstat 12} \ |
/tools/tcl/rutil/util.tcl
1,6 → 1,6
# $Id: util.tcl 661 2015-04-03 18:28:41Z mueller $ |
# $Id: util.tcl 619 2014-12-23 13:17:41Z mueller $ |
# |
# Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
# This program is free software; you may redistribute and/or modify it under |
# the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-03-28 660 1,0,4 add com8 and com16 |
# 2014-12-23 619 1.0.3 regget: add check for unknown field descriptor |
# 2014-07-12 569 1.0.2 add sxt16 and sxt32 |
# 2013-05-09 517 1.0.1 add optlist2arr |
203,7 → 202,6
} |
return $rval |
} |
|
# |
# errcnt2txt: returns "PASS" if 0 and "FAIL" otherwise --------------------- |
# |
211,7 → 209,6
if {$errcnt} {return "FAIL"} |
return "PASS" |
} |
|
# |
# sxt16: 16 bit sign extend ------------------------------------------------ |
# |
233,20 → 230,6
} |
|
# |
# com8: 8 bit complement --------------------------------------------------- |
# |
proc com8 {val} { |
return [expr (~$val) & 0xff] |
} |
|
# |
# com16: 16 bit complement ------------------------------------------------ |
# |
proc com16 {val} { |
return [expr (~$val) & 0xffff] |
} |
|
# |
# ! export reg... procs to global scope ------------------------------------ |
# |
|
/tools/tcl/rbtest/test_labo.tcl
File deleted
/tools/tcl/rbtest/test_data.tcl
1,6 → 1,6
# $Id: test_data.tcl 661 2015-04-03 18:28:41Z mueller $ |
# $Id: test_data.tcl 617 2014-12-21 14:18:53Z mueller $ |
# |
# Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
# This program is free software; you may redistribute and/or modify it under |
# the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-04-03 661 2.1 drop estatdef, use estattout |
# 2014-12-21 617 2.0.1 use rbtout stat bit for timeout |
# 2014-11-09 603 2.0 use rlink v4 address layout and iface |
# 2011-03-27 374 1.0 Initial version |
33,6 → 32,8
# rbd_tester is embedded in the design (e.g. stat and attn connections) |
# |
proc test_data {} { |
set esdval 0x00 |
set esdmsk [regbld rlink::STAT {stat -1}] |
# |
set errcnt 0 |
rlc errcnt -clear |
49,14 → 50,14
te.stat 0x0000 0x0000 \ |
te.data 0xffff 0xffff \ |
te.data 0x0000 0x0000 ] { |
rlc exec -wreg $addr $valw |
rlc exec -rreg $addr -edata $valr |
rlc exec -wreg $addr $valw -estat $esdval $esdmsk |
rlc exec -rreg $addr -edata $valr -estat $esdval $esdmsk |
} |
# |
# |
rlc log " test 1b: as test 1a, use clists, check cntl,stat,data distinct" |
foreach {valc vals vald} [list 0x1 0x2 0x3 0x0 0x0 0x0] { |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.cntl $valc \ |
-wreg te.stat $vals \ |
-wreg te.data $vald \ |
67,19 → 68,19
# |
#------------------------------------------------------------------------- |
rlc log " test 2: verify that large nbusy causes timeout" |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.data 0xdead \ |
-rreg te.data -edata 0xdead \ |
-wreg te.cntl [regbld rbtest::CNTL {nbusy 0x3ff}] \ |
-wreg te.data 0xbeaf -estattout \ |
-rreg te.data -estattout \ |
-wreg te.data 0xbeaf -estat [regbld rlink::STAT rbtout] $esdmsk \ |
-rreg te.data -estat [regbld rlink::STAT rbtout] $esdmsk \ |
-wreg te.cntl 0x0000 \ |
-rreg te.data -edata 0xdead |
-rreg te.data -edata 0xdead -edata 0xdead |
# |
# ------------------------------------------------------------------------- |
rlc log " test 3a: verify that init 001 clears cntl,stat and not data" |
set valc [regbld rbtest::CNTL {nbusy 1}] |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.cntl $valc \ |
-wreg te.stat 0x0002 \ |
-wreg te.data 0x1234 \ |
89,7 → 90,7
-wreg te.data 0x1234 |
rlc log " test 3b: verify that init 010 clears data and not cntl,stat" |
set valc [regbld rbtest::CNTL {nbusy 2}] |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.cntl $valc \ |
-wreg te.stat 0x0003 \ |
-wreg te.data 0x4321 \ |
98,7 → 99,7
-rreg te.stat -edata 0x0003 \ |
-wreg te.data 0x0 |
rlc log " test 3c: verify that init 011 clears data and cntl,stat" |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.cntl [regbld rbtest::CNTL {nbusy 3}] \ |
-wreg te.stat 0x0004 \ |
-wreg te.data 0xabcd \ |
111,7 → 112,7
rlc log " test 4: test that te.ncyc returns # of cycles for te.data w&r" |
foreach nbusy {0x03 0x07 0x0f 0x1f 0x00} { |
set valc [regbld rbtest::CNTL [list nbusy $nbusy]] |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.cntl $valc \ |
-wreg te.data [expr {$nbusy | ( $nbusy << 8 ) }] \ |
-rreg te.ncyc -edata [expr {$nbusy + 1 }] \ |
/tools/tcl/rbtest/util.tcl
1,4 → 1,4
# $Id: util.tcl 661 2015-04-03 18:28:41Z mueller $ |
# $Id: util.tcl 617 2014-12-21 14:18:53Z mueller $ |
# |
# Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
58,13 → 58,13
# restore te.cntl |
|
proc nbusymax {} { |
set esdmsk [regbld rlink::STAT rbtout rbnak rberr] |
rlc exec \ |
set esdmsk [regbld rlink::STAT {stat -1} attn] |
rlc exec -estatdef 0 $esdmsk \ |
-rreg te.cntl sav_cntl \ |
-wreg te.cntl [regbld rbtest::CNTL {nbusy -1}] \ |
-rreg te.data -estat [regbld rlink::STAT rbtout] $esdmsk \ |
-rreg te.ncyc ncyc |
rlc exec \ |
rlc exec -estatdef 0 $esdmsk \ |
-wreg te.cntl $sav_cntl |
return [expr {$ncyc - 1}] |
} |
72,7 → 72,10
# probe: determine rbd_tester environment (max nbusy, stat and attn wiring) |
# |
proc probe {} { |
set esdmsktout [regbld rlink::STAT rbnak rberr] |
set esdval 0x00 |
set esdmsk [regbld rlink::STAT {stat -1}] |
set esdmsktout [regbld rlink::STAT {stat -1} rbtout] |
set esdmskattn [regbld rlink::STAT {stat -1} attn] |
set rbusy {} |
set rstat {} |
set rattn {} |
87,9 → 90,9
set nbusy [expr {$nbusy0 + $j}] |
set valc [regbld rbtest::CNTL [list nbusy $nbusy]] |
rlc exec \ |
-wreg te.cntl $valc \ |
-wreg te.data 0x0000 statwr -estat 0x0 $esdmsktout \ |
-rreg te.data dummy statrd -estat 0x0 $esdmsktout |
-wreg te.cntl $valc -estat $esdval $esdmsk\ |
-wreg te.data 0x0000 statwr -estat $esdval $esdmsktout \ |
-rreg te.data dummy statrd -estat $esdval $esdmsktout |
if {[llength $wrerr] == 0 && [regget rlink::STAT(rbnak) $statwr] != 0} { |
lappend wrerr $i $j $nbusy |
} |
104,7 → 107,7
# probe stat wiring |
# |
for {set i 0} { $i < 4 } {incr i} { |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.stat [expr {1 << $i}] \ |
-rreg te.data dummy statrd |
lappend rstat [list $i [regget rlink::STAT(stat) $statrd]] |
115,7 → 118,7
# |
rlc exec -attn |
for {set i 0} { $i < 16 } {incr i} { |
rlc exec \ |
rlc exec -estatdef $esdval $esdmskattn \ |
-wreg te.attn [expr {1 << $i}] \ |
-attn attnpat |
lappend rattn [list $i $attnpat] |
/tools/tcl/rbtest/test_fifo.tcl
1,6 → 1,6
# $Id: test_fifo.tcl 662 2015-04-05 08:02:54Z mueller $ |
# $Id: test_fifo.tcl 603 2014-11-09 22:50:26Z mueller $ |
# |
# Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
# This program is free software; you may redistribute and/or modify it under |
# the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-04-03 661 2.1 drop estatdef; use estaterr |
# 2014-11-09 603 2.0 use rlink v4 address layout and iface |
# 2011-03-27 374 1.0 Initial version |
# 2011-03-13 369 0.1 First draft |
30,6 → 29,8
# Basic tests with cntl and fifo registers. |
# |
proc test_fifo {} { |
set esdval 0x00 |
set esdmsk [regbld rlink::STAT {stat -1}] |
# |
set errcnt 0 |
rlc errcnt -clear |
41,11 → 42,11
#------------------------------------------------------------------------- |
rlc log " test 1: fifo write/read with wreg/rreg" |
# single word |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.fifo 0x0000 \ |
-rreg te.fifo -estat 0x00 |
-rreg te.fifo -estat 0x0000 |
# three words |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.fifo 0xdead \ |
-wreg te.fifo 0xbeaf \ |
-wreg te.fifo 0x1234 \ |
54,24 → 55,24
-rreg te.fifo -edata 0x1234 |
# |
#------------------------------------------------------------------------- |
rlc log " test 2: fifo write/read with wblk/rblk and -edone" |
rlc log " test 2: fifo write/read with wblk/rblk" |
# two words |
set blk {0x1111 0x2222} |
rlc exec \ |
-wblk te.fifo $blk -edone [llength $blk] \ |
-rblk te.fifo [llength $blk] -edata $blk -edone [llength $blk] |
rlc exec -estatdef $esdval $esdmsk \ |
-wblk te.fifo $blk \ |
-rblk te.fifo [llength $blk] -edata $blk |
# six words |
set blk {0x3333 0x4444 0x5555 0x6666 0x7777 0x8888} |
rlc exec \ |
-wblk te.fifo $blk -edone [llength $blk] \ |
-rblk te.fifo [llength $blk] -edata $blk -edone [llength $blk] |
rlc exec -estatdef $esdval $esdmsk \ |
-wblk te.fifo $blk \ |
-rblk te.fifo [llength $blk] -edata $blk |
# |
#------------------------------------------------------------------------- |
rlc log " test 3a: fifo read error (write 3, read 4) and -edone" |
rlc log " test 3a: fifo read error (write 3, read 4)" |
set blk {0xdead 0xbeaf 0x1234} |
rlc exec \ |
-wblk te.fifo $blk -edone [llength $blk] \ |
-rblk te.fifo 4 -edata $blk -edone 3 -estaterr |
rlc exec -estatdef $esdval $esdmsk \ |
-wblk te.fifo $blk \ |
-rblk te.fifo 4 -edata $blk -estat [regbld rlink::STAT rberr] $esdmsk |
# |
# |
rlc log " test 3b: fifo write error (write 17, read 16)" |
79,21 → 80,21
for { set i 0 } { $i < 17 } { incr i } { |
lappend blk [expr {$i | ( $i << 8 ) }] |
} |
rlc exec \ |
-wblk te.fifo $blk -edone 16 -estaterr \ |
-rblk te.fifo 16 -edata [lrange $blk 0 15] -edone 16 |
rlc exec -estatdef $esdval $esdmsk \ |
-wblk te.fifo $blk -estat [regbld rlink::STAT rberr] $esdmsk \ |
-rblk te.fifo 16 -edata [lrange $blk 0 15] |
# |
#------------------------------------------------------------------------- |
rlc log " test 4a: verify that init 100 clears fifo and not cntl&data" |
# check fifo empty; write a value; clear fifo via init; check fifo empty |
# check that cntl and data not affected |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.cntl [regbld rbtest::CNTL {nbusy 0x1}] \ |
-wreg te.data 0x1234 \ |
-rreg te.fifo -estaterr \ |
-rreg te.fifo -estat [regbld rlink::STAT rberr] $esdmsk \ |
-wreg te.fifo 0x4321 \ |
-init te.cntl [regbld rbtest::INIT fifo] \ |
-rreg te.fifo -estaterr \ |
-rreg te.fifo -estat [regbld rlink::STAT rberr] $esdmsk \ |
-rreg te.cntl -edata [regbld rbtest::CNTL {nbusy 0x1}] \ |
-rreg te.data -edata 0x1234 |
# |
101,7 → 102,7
rlc log " test 6: test that te.ncyc returns # of cycles for te.fifo w&r" |
foreach nbusy {0x03 0x07 0x0f 0x1f 0x00} { |
set valc [regbld rbtest::CNTL [list nbusy $nbusy]] |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.cntl $valc \ |
-wreg te.fifo [expr {$nbusy | ( $nbusy << 8 ) }] \ |
-rreg te.ncyc -edata [expr {$nbusy + 1 }] \ |
117,7 → 118,7
set bcode [expr {32 * $i + 2 * $j}] |
lappend blk [expr {( $bcode << 8 ) | ( $bcode + 1 )}] |
} |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wblk te.fifo $blk \ |
-rblk te.fifo [llength $blk] -edata $blk |
} |
/tools/tcl/rbtest/test_attn.tcl
1,6 → 1,6
# $Id: test_attn.tcl 661 2015-04-03 18:28:41Z mueller $ |
# $Id: test_attn.tcl 603 2014-11-09 22:50:26Z mueller $ |
# |
# Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
# This program is free software; you may redistribute and/or modify it under |
# the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-04-03 661 2.1 drop estatdef (stat err check default now) |
# 2014-11-09 603 2.0 use rlink v4 address layout and iface |
# 2011-03-27 374 1.0 Initial version |
# 2011-03-20 372 0.1 First Draft |
33,6 → 32,9
# quit if nothing to do... |
if {$attnmsk == 0} {return 0} |
# |
set esdval 0x00 |
set esdmsk [regbld rlink::STAT {stat -1} attn] |
# |
set apats {} |
for {set i 0} {$i < 16} {incr i} { |
set apat [expr {1 << $i}] |
50,7 → 52,7
#------------------------------------------------------------------------- |
rlc log " test 1: verify connection of attn bits" |
foreach apat $apats { |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.attn $apat \ |
-rreg te.cntl -estat [regbld rlink::STAT attn] \ |
-attn -edata $apat \ |
61,9 → 63,9
#------------------------------------------------------------------------- |
rlc log " test 2: verify that attn flags accumulate" |
foreach apat $apats { |
rlc exec -wreg te.attn $apat |
rlc exec -wreg te.attn $apat -estat $esdval $esdmsk |
} |
rlc exec -attn -edata $attnmsk |
rlc exec -attn -edata $attnmsk -estat $esdval $esdmsk |
|
# |
#------------------------------------------------------------------------- |
/tools/tcl/rbtest/test_all.tcl
1,6 → 1,6
# $Id: test_all.tcl 662 2015-04-05 08:02:54Z mueller $ |
# $Id: test_all.tcl 375 2011-04-02 07:56:47Z mueller $ |
# |
# Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
# This program is free software; you may redistribute and/or modify it under |
# the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-04-03 662 1.1 add test_labo |
# 2011-03-27 374 1.0 Initial version |
# 2011-03-13 369 0.1 First draft |
# |
29,7 → 28,6
set errcnt 0 |
incr errcnt [rbtest::test_data] |
incr errcnt [rbtest::test_fifo] |
incr errcnt [rbtest::test_labo] |
incr errcnt [rbtest::test_stat $statmsk] |
incr errcnt [rbtest::test_attn $attnmsk] |
return $errcnt |
/tools/tcl/rbmoni/test_regs.tcl
1,6 → 1,6
# $Id: test_regs.tcl 661 2015-04-03 18:28:41Z mueller $ |
# $Id: test_regs.tcl 622 2014-12-28 20:45:26Z mueller $ |
# |
# Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
# This program is free software; you may redistribute and/or modify it under |
# the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-04-03 661 2.1 drop estatdef (stat err check default now) |
# 2014-12-27 622 2.0 rbd_rbmon reorganized, supports now 16 bit addresses |
# 2011-03-27 374 1.0 Initial version |
# 2011-03-13 369 0.1 First Draft |
30,6 → 29,8
# Basic tests with rbtester registers |
# |
proc test_regs {} { |
set esdval 0x00 |
set esdmsk [regbld rlink::STAT {stat -1}] |
# |
set errcnt 0 |
rlc errcnt -clear |
38,7 → 39,7
# |
#------------------------------------------------------------------------- |
rlc log " test 1: write/read cntl" |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg rm.cntl [regbld rbmoni::CNTL start] \ |
-rreg rm.cntl -edata [regbld rbmoni::CNTL start] \ |
-wreg rm.cntl [regbld rbmoni::CNTL stop] \ |
50,7 → 51,7
# |
#------------------------------------------------------------------------- |
rlc log " test 2: read stat" |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-rreg rm.stat rstat |
set bsize [regget rbmoni::STAT(bsize) $rstat] |
set amax [expr {( 512 << $bsize ) - 1}] |
59,7 → 60,7
rlc log " test 3: write/read hilim/lolim" |
foreach {lolim hilim} {0xffff 0x0000 \ |
0x0000 0xfffb} { |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg rm.lolim $lolim -wreg rm.hilim $hilim \ |
-rreg rm.lolim -edata $lolim -rreg rm.hilim -edata $hilim |
} |
68,7 → 69,7
rlc log " test 4: write/read addr" |
foreach {laddr waddr} [list 0x0000 0 0x0000 3 $amax 0 $amax 3] { |
set addr [regbld rbmoni::ADDR [list laddr $laddr] [list waddr $waddr]] |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg rm.addr $addr \ |
-rreg rm.addr -edata $addr |
} |
75,7 → 76,7
# |
#------------------------------------------------------------------------- |
rlc log " test 5: verify that cntl.go 0->1 clear addr" |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg rm.cntl [regbld rbmoni::CNTL stop] \ |
-rreg rm.cntl -edata 0x0 \ |
-wreg rm.addr [regbld rbmoni::ADDR [list laddr $amax]] \ |
/tools/tcl/rbmoni/test_rbtest.tcl
1,6 → 1,6
# $Id: test_rbtest.tcl 661 2015-04-03 18:28:41Z mueller $ |
# $Id: test_rbtest.tcl 619 2014-12-23 13:17:41Z mueller $ |
# |
# Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
# This program is free software; you may redistribute and/or modify it under |
# the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-04-03 661 2.1 drop estatdef; fix test 5 (wrong regs accessed) |
# 2014-12-22 619 2.0 adopt to new rbd_rbmon and rlink v4 |
# 2011-03-27 374 1.0 Initial version |
# 2011-03-13 369 0.1 First Draft |
31,6 → 30,8
# Basic tests with rbtester registers |
# |
proc test_rbtest {{print 0}} { |
set esdval 0x00 |
set esdmsk [regbld rlink::STAT {stat -1}] |
# |
set errcnt 0 |
rlc errcnt -clear |
56,7 → 57,7
set vtedata 0x1234 |
|
# write/read te.stat and te.data with rbmoni on; check that 4 lines aquired |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg rm.cntl [regbld rbmoni::CNTL start] \ |
-wreg te.stat $vtestat \ |
-wreg te.data $vtedata \ |
78,7 → 79,7
# |
#------------------------------------------------------------------------- |
rlc log " test 1a: read all in one rblk" |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg rm.addr 0x0000 \ |
-rblk rm.data 16 -edata $edat $emsk \ |
-rreg rm.addr -edata 16 |
88,7 → 89,7
rlc log " test 1b: random address with rreg" |
foreach addr {0x1 0x3 0x5 0x7 0x6 0x4 0x2 0x0 \ |
0x9 0xb 0xd 0xf 0xe 0xc 0xa 0x8} { |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg rm.addr $addr \ |
-rreg rm.data -edata [lindex $edat $addr] [lindex $emsk $addr] \ |
-rreg rm.addr -edata [expr {$addr + 1}] |
99,7 → 100,7
rlc log " test 1c: random address with rblk length 2" |
foreach addr {0x1 0x3 0x5 0x7 0x6 0x4 0x2 0x0 \ |
0x9 0xb 0xd 0xe 0xc 0xa 0x8} { |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg rm.addr $addr \ |
-rblk rm.data 2 -edata [lrange $edat $addr [expr {$addr + 1}] ] \ |
[lrange $emsk $addr [expr {$addr + 1}] ] \ |
116,7 → 117,7
[list [regbld rbmoni::FLAGS ack ] $atedata $vtedata 0] |
# |
rbmoni::start |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.data $vtedata \ |
-rreg te.data -edata $vtedata |
rbmoni::stop |
138,7 → 139,7
[list [regbld rbmoni::FLAGS ack we] $atecntl 0 0] |
# |
rbmoni::start |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.cntl $nbusy_1 \ |
-wreg te.data $vtedata \ |
-wreg te.cntl $nbusy_4 \ |
162,7 → 163,7
[list [regbld rbmoni::FLAGS ack we] $atecntl 0 0] |
# |
rbmoni::start |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.cntl $vtecntl \ |
-wreg te.data $vtedata -estat [regbld rlink::STAT rbtout] \ |
-rreg te.data -edata 0x5555 -estat [regbld rlink::STAT rbtout] \ |
181,7 → 182,7
[list [regbld rbmoni::FLAGS nak ] $atelnak {} 0] |
# |
rbmoni::start |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.lnak $vtelnak -estat [regbld rlink::STAT rbnak] \ |
-rreg te.lnak -estat [regbld rlink::STAT rbnak] |
rbmoni::stop |
201,7 → 202,7
[list [regbld rbmoni::FLAGS ack we] $atecntl 0 0] |
# |
rbmoni::start |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.cntl $vtecntl \ |
-wreg te.lnak $vtelnak -estat [regbld rlink::STAT rbnak] \ |
-rreg te.lnak -estat [regbld rlink::STAT rbnak] \ |
221,7 → 222,7
[list [regbld rbmoni::FLAGS ack err ] $atefifo {} 0] |
# |
rbmoni::start |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.fifo $vtefifo \ |
-rreg te.fifo -edata $vtefifo \ |
-rreg te.fifo -estat [regbld rlink::STAT rberr] |
243,11 → 244,11
[list [regbld rbmoni::FLAGS ack we] $atecntl 0 0] |
# |
rbmoni::start |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.cntl $vtecntl \ |
-wreg te.fifo $vtefifo \ |
-rreg te.fifo -edata $vtefifo \ |
-rreg te.fifo -estaterr \ |
-rreg te.fifo -estat [regbld rlink::STAT rberr] \ |
-wreg te.cntl 0x0 |
rbmoni::stop |
if {$print} {puts [print]} |
265,7 → 266,7
[list [regbld rbmoni::FLAGS ack ] $atecntl 0 0] |
# |
rbmoni::start |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-wreg te.cntl $vtecntl \ |
-init te.cntl $vteinit \ |
-rreg te.cntl -edata 0 |
292,7 → 293,7
[list [regbld rbmoni::FLAGS nak init] $atecntl $vteinit 0] |
# |
rbmoni::start |
rlc exec \ |
rlc exec -estatdef $esdval $esdmsk \ |
-init te.cntl $vteinit \ |
-wblk te.fifo $vtefifo \ |
-wreg te.cntl $nbusy_2 \ |
309,7 → 310,7
rlc exec -wreg rm.lolim $atencyc \ |
-wreg rm.hilim $atedinc |
|
# now access all regs (except attn,lnak), but only ncyc,data,dinc recorded |
# now access all regs, but only ncyc,data,dinc should be recorded |
raw_edata edat emsk \ |
[list [regbld rbmoni::FLAGS ack ] $atencyc 0x0001 0] \ |
[list [regbld rbmoni::FLAGS ack we] $atedata 0x2345 0] \ |
319,12 → 320,14
rbmoni::start |
rlc exec -rreg te.cntl \ |
-rreg te.stat \ |
-rreg te.attn \ |
-rreg te.ncyc \ |
-wreg te.data 0x2345 \ |
-wreg te.fifo 0xbeaf \ |
-rreg te.dinc -edata 0x2345 \ |
-rreg te.fifo -edata 0xbeaf \ |
-rreg te.data -edata 0x2346 |
-rreg te.data -edata 0x2346 \ |
-rreg te.lnak |
rbmoni::stop |
if {$print} {puts [print]} |
raw_check $edat $emsk |
/tools/tcl/rbmoni/util.tcl
1,6 → 1,6
# $Id: util.tcl 661 2015-04-03 18:28:41Z mueller $ |
# $Id: util.tcl 619 2014-12-23 13:17:41Z mueller $ |
# |
# Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
# This program is free software; you may redistribute and/or modify it under |
# the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-04-03 661 3.1 drop estatdef; invert mask in raw_edata |
# 2014-12-23 619 3.0 rbd_rbmon reorganized, supports now 16 bit addresses |
# 2014-11-09 603 2.0 use rlink v4 address layout |
# 2011-03-27 374 1.0 Initial version |
218,10 → 217,10
set uedat {} |
set uemsk {} |
|
set m3 [rutil::com16 [regbld rbmoni::DAT3 {ndlymsb -1}]]; # all but ndlymsb |
set m2 [rutil::com16 [regbld rbmoni::DAT2 {ndlylsb -1}]]; # all but ndlylsb |
set m1 0xffff |
set m0 0xffff |
set m3 [regbld rbmoni::DAT3 {ndlymsb -1}] |
set m2 [regbld rbmoni::DAT2 {ndlylsb -1}] |
set m1 0 |
set m0 0 |
|
foreach line $args { |
foreach {eflags eaddr edata enbusy} $line { break } |
228,10 → 227,10
set d3 [regbld rbmoni::DAT3 [list flags $eflags]] |
set d2 [regbld rbmoni::DAT2 [list nbusy $enbusy]] |
if {$edata ne ""} { |
set m1 0xffff |
set m1 0x0000 |
set d1 $edata |
} else { |
set m1 0x0000 |
set m1 0xffff |
set d1 0x0000 |
} |
set d0 $eaddr |
248,7 → 247,7
# |
proc raw_check {edat emsk} { |
|
rlc exec \ |
rlc exec -estatdef 0x0 [regbld rlink::STAT {stat -1}] \ |
-rreg rm.addr -edata [llength $edat] \ |
-wreg rm.addr 0 \ |
-rblk rm.data [llength $edat] -edata $edat $emsk \ |
/tools/tcl/setup_packages
1,5 → 1,5
#! /usr/bin/env tclshcpp |
# $Id: setup_packages 668 2015-04-25 14:31:19Z mueller $ |
# $Id: setup_packages 601 2014-11-07 22:44:43Z mueller $ |
# |
pkg_mkIndex -verbose ../lib \ |
librlinktpp.so \ |
7,17 → 7,14
librutiltpp.so \ |
librwxxtpp.so |
# |
pkg_mkIndex -verbose rutil *.tcl |
pkg_mkIndex -verbose rlink *.tcl |
pkg_mkIndex -verbose rbtest *.tcl |
pkg_mkIndex -verbose rbmoni *.tcl |
pkg_mkIndex -verbose rbbram *.tcl |
pkg_mkIndex -verbose rbs3hio *.tcl |
pkg_mkIndex -verbose rbemon *.tcl |
pkg_mkIndex -verbose rutil *.tcl |
pkg_mkIndex -verbose rlink *.tcl |
pkg_mkIndex -verbose rbtest *.tcl |
pkg_mkIndex -verbose rbmoni *.tcl |
pkg_mkIndex -verbose rbbram *.tcl |
pkg_mkIndex -verbose rbs3hio *.tcl |
pkg_mkIndex -verbose rbemon *.tcl |
# |
pkg_mkIndex -verbose rw11 *.tcl |
pkg_mkIndex -verbose rw11 *.tcl |
# |
pkg_mkIndex -verbose ibd_ibmon *.tcl |
pkg_mkIndex -verbose ibd_rhrp *.tcl |
# |
pkg_mkIndex -verbose tst_rlink *.tcl |
/tools/src/librw11/Rw11CntlRHRP.cpp
File deleted
/tools/src/librw11/Rw11CntlRHRP.hpp
File deleted
/tools/src/librw11/Rw11CntlRHRP.ipp
File deleted
/tools/src/librw11/Rw11UnitRHRP.ipp
File deleted
/tools/src/librw11/Rw11UnitRHRP.hpp
File deleted
/tools/src/librw11/Rw11UnitRHRP.cpp
File deleted
/tools/src/librw11/Rw11CntlRK11.cpp
1,4 → 1,4
// $Id: Rw11CntlRK11.cpp 669 2015-04-26 21:20:32Z mueller $ |
// $Id: Rw11CntlRK11.cpp 647 2015-02-17 22:35:36Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Other credits: |
26,7 → 26,7
|
/*! |
\file |
\version $Id: Rw11CntlRK11.cpp 669 2015-04-26 21:20:32Z mueller $ |
\version $Id: Rw11CntlRK11.cpp 647 2015-02-17 22:35:36Z mueller $ |
\brief Implemenation of Rw11CntlRK11. |
*/ |
|
194,13 → 194,13
|
// add device register address ibus and rbus mappings |
// done here because now Cntl bound to Cpu and Cntl probed |
Cpu().AllIAddrMapInsert(Name()+".ds", Base() + kRKDS); |
Cpu().AllIAddrMapInsert(Name()+".er", Base() + kRKER); |
Cpu().AllIAddrMapInsert(Name()+".cs", Base() + kRKCS); |
Cpu().AllIAddrMapInsert(Name()+".wc", Base() + kRKWC); |
Cpu().AllIAddrMapInsert(Name()+".ba", Base() + kRKBA); |
Cpu().AllIAddrMapInsert(Name()+".da", Base() + kRKDA); |
Cpu().AllIAddrMapInsert(Name()+".mr", Base() + kRKMR); |
Cpu().AllAddrMapInsert(Name()+".ds", Base() + kRKDS); |
Cpu().AllAddrMapInsert(Name()+".er", Base() + kRKER); |
Cpu().AllAddrMapInsert(Name()+".cs", Base() + kRKCS); |
Cpu().AllAddrMapInsert(Name()+".wc", Base() + kRKWC); |
Cpu().AllAddrMapInsert(Name()+".ba", Base() + kRKBA); |
Cpu().AllAddrMapInsert(Name()+".da", Base() + kRKDA); |
Cpu().AllAddrMapInsert(Name()+".mr", Base() + kRKMR); |
|
// setup primary info clist |
fPrimClist.Clear(); |
364,11 → 364,11
<< " da=" << RosPrintBvi(rkda,8) |
<< " ad=" << RosPrintBvi(addr,8,18) |
<< " fu=" << fumnemo[fu&0x7] |
<< " pa=" << dr |
<< " dchs=" << dr |
<< "," << RosPrintf(cy,"d",3) |
<< "," << hd |
<< "," << RosPrintf(se,"d",2) |
<< " la,nw=" << RosPrintf(lba,"d",4) |
<< " lba,nw=" << RosPrintf(lba,"d",4) |
<< "," << RosPrintf(nwrd,"d",5); |
} |
|
425,7 → 425,7
AddErrorExit(clist, rker); |
} else { |
fRdma.QueueDiskWrite(addr, nwrd, |
Rw11Cpu::kCPAH_M_22BIT|Rw11Cpu::kCPAH_M_UBMAP, |
Rw11Cpu::kCp_ah_m_22bit|Rw11Cpu::kCp_ah_m_ubmap, |
lba, &unit); |
} |
|
438,7 → 438,7
AddErrorExit(clist, rker); |
} else { |
fRdma.QueueDiskRead(addr, nwrd, |
Rw11Cpu::kCPAH_M_22BIT|Rw11Cpu::kCPAH_M_UBMAP, |
Rw11Cpu::kCp_ah_m_22bit|Rw11Cpu::kCp_ah_m_ubmap, |
lba, &unit); |
} |
|
451,7 → 451,7
AddErrorExit(clist, rker); |
} else { |
fRdma.QueueDiskWriteCheck(addr, nwrd, |
Rw11Cpu::kCPAH_M_22BIT|Rw11Cpu::kCPAH_M_UBMAP, |
Rw11Cpu::kCp_ah_m_22bit|Rw11Cpu::kCp_ah_m_ubmap, |
lba, &unit); |
} |
|
/tools/src/librw11/Rw11UnitDisk.ipp
1,4 → 1,4
// $Id: Rw11UnitDisk.ipp 659 2015-03-22 23:15:51Z mueller $ |
// $Id: Rw11UnitDisk.ipp 647 2015-02-17 22:35:36Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-03-21 659 1.0.2 add fEnabled, Enabled() |
// 2015-02-18 647 1.0.1 add Nwrd2Nblk() |
// 2013-04-19 507 1.0 Initial version |
// 2013-02-19 490 0.1 First draft |
21,7 → 20,7
|
/*! |
\file |
\version $Id: Rw11UnitDisk.ipp 659 2015-03-22 23:15:51Z mueller $ |
\version $Id: Rw11UnitDisk.ipp 647 2015-02-17 22:35:36Z mueller $ |
\brief Implemenation (inline) of Rw11UnitDisk. |
*/ |
|
39,14 → 38,6
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline bool Rw11UnitDisk::Enabled() const |
{ |
return fEnabled; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline size_t Rw11UnitDisk::NCylinder() const |
{ |
return fNCyl; |
/tools/src/librw11/Rw11CntlRL11.hpp
1,4 → 1,4
// $Id: Rw11CntlRL11.hpp 665 2015-04-07 07:13:49Z mueller $ |
// $Id: Rw11CntlRL11.hpp 653 2015-03-01 12:53:01Z mueller $ |
// |
// Copyright 2014-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
20,7 → 20,7
|
/*! |
\file |
\version $Id: Rw11CntlRL11.hpp 665 2015-04-07 07:13:49Z mueller $ |
\version $Id: Rw11CntlRL11.hpp 653 2015-03-01 12:53:01Z mueller $ |
\brief Declaration of class Rw11CntlRL11. |
*/ |
|
59,10 → 59,10
static const uint16_t kIbaddr = 0174400; //!< RL11 default address |
static const int kLam = 5; //!< RL11 default lam |
|
static const uint16_t kRLCS = 000; //!< RLCS reg offset |
static const uint16_t kRLBA = 002; //!< RLBA reg offset |
static const uint16_t kRLDA = 004; //!< RLDA reg offset |
static const uint16_t kRLMP = 006; //!< RLMP reg offset |
static const uint16_t kRLCS = 000; //!< RLCS register address offset |
static const uint16_t kRLBA = 002; //!< RLBA register address offset |
static const uint16_t kRLDA = 004; //!< RLDA register address offset |
static const uint16_t kRLMP = 006; //!< RLMP register address offset |
|
static const uint16_t kProbeOff = kRLCS; //!< probe address offset (rlcs) |
static const bool kProbeInt = true; //!< probe int active |
/tools/src/librw11/Makefile
1,4 → 1,4
# $Id: Makefile 664 2015-04-06 12:02:17Z mueller $ |
# $Id: Makefile 626 2015-01-03 14:41:37Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
32,7 → 32,6
OBJ_all += Rw11CntlPC11.o Rw11UnitPC11.o |
OBJ_all += Rw11CntlRL11.o Rw11UnitRL11.o |
OBJ_all += Rw11CntlRK11.o Rw11UnitRK11.o |
OBJ_all += Rw11CntlRHRP.o Rw11UnitRHRP.o |
OBJ_all += Rw11Virt.o |
OBJ_all += Rw11VirtTerm.o Rw11VirtTermPty.o Rw11VirtTermTcp.o |
OBJ_all += Rw11VirtDisk.o Rw11VirtDiskFile.o |
/tools/src/librw11/Rw11UnitRL11.cpp
1,4 → 1,4
// $Id: Rw11UnitRL11.cpp 659 2015-03-22 23:15:51Z mueller $ |
// $Id: Rw11UnitRL11.cpp 653 2015-03-01 12:53:01Z mueller $ |
// |
// Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,13 → 13,12
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-03-21 659 1.0.1 BUGFIX: SetType(): set fType; |
// 2014-06-08 561 1.0 Initial version |
// --------------------------------------------------------------------------- |
|
/*! |
\file |
\version $Id: Rw11UnitRL11.cpp 659 2015-03-22 23:15:51Z mueller $ |
\version $Id: Rw11UnitRL11.cpp 653 2015-03-01 12:53:01Z mueller $ |
\brief Implemenation of Rw11UnitRL11. |
*/ |
|
51,7 → 50,6
{ |
// setup disk geometry: rl01 and rl02 supported, default rl02 |
fType = "rl02"; |
fEnabled = true; |
fNCyl = 512; |
fNHead = 2; |
fNSect = 40; |
83,8 → 81,6
throw Rexception("Rw11UnitRL11::SetType", |
string("Bad args: only types 'rl01' and 'rl02' supported")); |
} |
|
fType = type; |
fNBlock = fNCyl*fNHead*fNSect; |
return; |
} |
/tools/src/librw11/Rw11Cpu.cpp
1,6 → 1,6
// $Id: Rw11Cpu.cpp 675 2015-05-08 21:05:08Z mueller $ |
// $Id: Rw11Cpu.cpp 632 2015-01-11 12:30:03Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,10 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-05-08 675 1.2.3 w11a start/stop/suspend overhaul |
// 2015-04-25 668 1.2.2 add AddRbibr(), AddWbibr() |
// 2015-04-03 661 1.2.1 add kStat_M_* defs |
// 2015-03-21 659 1.2 add RAddrMap |
// 2015-01-01 626 1.1 Adopt for rlink v4 and 4k ibus window |
// 2014-12-21 617 1.0.3 use kStat_M_RbTout for rbus timeout |
// 2014-08-02 576 1.0.2 adopt rename of LastExpect->SetLastExpect |
27,7 → 23,7
|
/*! |
\file |
\version $Id: Rw11Cpu.cpp 675 2015-05-08 21:05:08Z mueller $ |
\version $Id: Rw11Cpu.cpp 632 2015-01-11 12:30:03Z mueller $ |
\brief Implemenation of Rw11Cpu. |
*/ |
#include <stdlib.h> |
62,61 → 58,53
//------------------------------------------+----------------------------------- |
// constants definitions |
|
const uint16_t Rw11Cpu::kCPCONF; |
const uint16_t Rw11Cpu::kCPCNTL; |
const uint16_t Rw11Cpu::kCPSTAT; |
const uint16_t Rw11Cpu::kCPPSW; |
const uint16_t Rw11Cpu::kCPAL; |
const uint16_t Rw11Cpu::kCPAH; |
const uint16_t Rw11Cpu::kCPMEM; |
const uint16_t Rw11Cpu::kCPMEMI; |
const uint16_t Rw11Cpu::kCPR0; |
const uint16_t Rw11Cpu::kCPPC; |
const uint16_t Rw11Cpu::kCPMEMBE; |
const uint16_t Rw11Cpu::kCp_addr_conf; |
const uint16_t Rw11Cpu::kCp_addr_cntl; |
const uint16_t Rw11Cpu::kCp_addr_stat; |
const uint16_t Rw11Cpu::kCp_addr_psw; |
const uint16_t Rw11Cpu::kCp_addr_al; |
const uint16_t Rw11Cpu::kCp_addr_ah; |
const uint16_t Rw11Cpu::kCp_addr_mem; |
const uint16_t Rw11Cpu::kCp_addr_memi; |
const uint16_t Rw11Cpu::kCp_addr_r0; |
const uint16_t Rw11Cpu::kCp_addr_pc; |
const uint16_t Rw11Cpu::kCp_addr_membe; |
|
const uint16_t Rw11Cpu::kCPFUNC_NOOP; |
const uint16_t Rw11Cpu::kCPFUNC_START; |
const uint16_t Rw11Cpu::kCPFUNC_STOP; |
const uint16_t Rw11Cpu::kCPFUNC_STEP; |
const uint16_t Rw11Cpu::kCPFUNC_CRESET; |
const uint16_t Rw11Cpu::kCPFUNC_BRESET; |
const uint16_t Rw11Cpu::kCPFUNC_SUSPEND; |
const uint16_t Rw11Cpu::kCPFUNC_RESUME; |
const uint16_t Rw11Cpu::kCp_func_noop; |
const uint16_t Rw11Cpu::kCp_func_start; |
const uint16_t Rw11Cpu::kCp_func_stop; |
const uint16_t Rw11Cpu::kCp_func_cont; |
const uint16_t Rw11Cpu::kCp_func_step; |
const uint16_t Rw11Cpu::kCp_func_reset; |
|
const uint16_t Rw11Cpu::kCPSTAT_M_SuspExt; |
const uint16_t Rw11Cpu::kCPSTAT_M_SuspInt; |
const uint16_t Rw11Cpu::kCPSTAT_M_CpuRust; |
const uint16_t Rw11Cpu::kCPSTAT_V_CpuRust; |
const uint16_t Rw11Cpu::kCPSTAT_B_CpuRust; |
const uint16_t Rw11Cpu::kCPSTAT_M_CpuSusp; |
const uint16_t Rw11Cpu::kCPSTAT_M_CpuGo; |
const uint16_t Rw11Cpu::kCPSTAT_M_CmdMErr; |
const uint16_t Rw11Cpu::kCPSTAT_M_CmdErr; |
const uint16_t Rw11Cpu::kCp_stat_m_cpurust; |
const uint16_t Rw11Cpu::kCp_stat_v_cpurust; |
const uint16_t Rw11Cpu::kCp_stat_b_cpurust; |
const uint16_t Rw11Cpu::kCp_stat_m_cpuhalt; |
const uint16_t Rw11Cpu::kCp_stat_m_cpugo; |
const uint16_t Rw11Cpu::kCp_stat_m_cmdmerr; |
const uint16_t Rw11Cpu::kCp_stat_m_cmderr; |
|
const uint16_t Rw11Cpu::kCPURUST_INIT; |
const uint16_t Rw11Cpu::kCPURUST_HALT; |
const uint16_t Rw11Cpu::kCPURUST_RESET; |
const uint16_t Rw11Cpu::kCPURUST_STOP; |
const uint16_t Rw11Cpu::kCPURUST_STEP; |
const uint16_t Rw11Cpu::kCPURUST_SUSP; |
const uint16_t Rw11Cpu::kCPURUST_RUNS; |
const uint16_t Rw11Cpu::kCPURUST_VECFET; |
const uint16_t Rw11Cpu::kCPURUST_RECRSV; |
const uint16_t Rw11Cpu::kCPURUST_SFAIL; |
const uint16_t Rw11Cpu::kCPURUST_VFAIL; |
const uint16_t Rw11Cpu::kCp_cpurust_init; |
const uint16_t Rw11Cpu::kCp_cpurust_halt; |
const uint16_t Rw11Cpu::kCp_cpurust_reset; |
const uint16_t Rw11Cpu::kCp_cpurust_stop; |
const uint16_t Rw11Cpu::kCp_cpurust_step; |
const uint16_t Rw11Cpu::kCp_cpurust_susp; |
const uint16_t Rw11Cpu::kCp_cpurust_runs; |
const uint16_t Rw11Cpu::kCp_cpurust_vecfet; |
const uint16_t Rw11Cpu::kCp_cpurust_recrsv; |
const uint16_t Rw11Cpu::kCp_cpurust_sfail; |
const uint16_t Rw11Cpu::kCp_cpurust_vfail; |
|
const uint16_t Rw11Cpu::kCPAH_M_ADDR; |
const uint16_t Rw11Cpu::kCPAH_M_22BIT; |
const uint16_t Rw11Cpu::kCPAH_M_UBMAP; |
const uint16_t Rw11Cpu::kCp_ah_m_addr; |
const uint16_t Rw11Cpu::kCp_ah_m_22bit; |
const uint16_t Rw11Cpu::kCp_ah_m_ubmap; |
|
const uint16_t Rw11Cpu::kCPMEMBE_M_STICK; |
const uint16_t Rw11Cpu::kCPMEMBE_M_BE; |
const uint16_t Rw11Cpu::kCp_membe_m_stick; |
const uint16_t Rw11Cpu::kCp_membe_m_be; |
|
|
const uint8_t Rw11Cpu::kStat_M_CmdErr; |
const uint8_t Rw11Cpu::kStat_M_CmdMErr; |
const uint8_t Rw11Cpu::kStat_M_CpuHalt; |
const uint8_t Rw11Cpu::kStat_M_CpuGo; |
|
//------------------------------------------+----------------------------------- |
//! Constructor |
|
132,7 → 120,6
fCpuGoCond(), |
fCntlMap(), |
fIAddrMap(), |
fRAddrMap(), |
fStats() |
{} |
|
149,48 → 136,52
{ |
fpW11 = pw11; |
// add control port address rbus mappings |
AllRAddrMapInsert("conf" , Base()+kCPCONF); |
AllRAddrMapInsert("cntl" , Base()+kCPCNTL); |
AllRAddrMapInsert("stat" , Base()+kCPSTAT); |
AllRAddrMapInsert("psw" , Base()+kCPPSW); |
AllRAddrMapInsert("al" , Base()+kCPAL); |
AllRAddrMapInsert("ah" , Base()+kCPAH); |
AllRAddrMapInsert("mem" , Base()+kCPMEM); |
AllRAddrMapInsert("memi" , Base()+kCPMEMI); |
AllRAddrMapInsert("r0" , Base()+kCPR0); |
AllRAddrMapInsert("r1" , Base()+kCPR0+1); |
AllRAddrMapInsert("r2" , Base()+kCPR0+2); |
AllRAddrMapInsert("r3" , Base()+kCPR0+3); |
AllRAddrMapInsert("r4" , Base()+kCPR0+4); |
AllRAddrMapInsert("r5" , Base()+kCPR0+5); |
AllRAddrMapInsert("sp" , Base()+kCPR0+6); |
AllRAddrMapInsert("pc" , Base()+kCPR0+7); |
AllRAddrMapInsert("membe",Base()+kCPMEMBE); |
// name base: 'cn.', where n is cpu index |
string cbase = "c"; |
cbase += '0'+Index(); |
cbase += '.'; |
Connect().AddrMapInsert(cbase+"conf", Base()+kCp_addr_conf); |
Connect().AddrMapInsert(cbase+"cntl", Base()+kCp_addr_cntl); |
Connect().AddrMapInsert(cbase+"stat", Base()+kCp_addr_stat); |
Connect().AddrMapInsert(cbase+"psw" , Base()+kCp_addr_psw); |
Connect().AddrMapInsert(cbase+"al" , Base()+kCp_addr_al); |
Connect().AddrMapInsert(cbase+"ah" , Base()+kCp_addr_ah); |
Connect().AddrMapInsert(cbase+"mem" , Base()+kCp_addr_mem); |
Connect().AddrMapInsert(cbase+"memi", Base()+kCp_addr_memi); |
Connect().AddrMapInsert(cbase+"r0" , Base()+kCp_addr_r0); |
Connect().AddrMapInsert(cbase+"r1" , Base()+kCp_addr_r0+1); |
Connect().AddrMapInsert(cbase+"r2" , Base()+kCp_addr_r0+2); |
Connect().AddrMapInsert(cbase+"r3" , Base()+kCp_addr_r0+3); |
Connect().AddrMapInsert(cbase+"r4" , Base()+kCp_addr_r0+4); |
Connect().AddrMapInsert(cbase+"r5" , Base()+kCp_addr_r0+5); |
Connect().AddrMapInsert(cbase+"sp" , Base()+kCp_addr_r0+6); |
Connect().AddrMapInsert(cbase+"pc" , Base()+kCp_addr_r0+7); |
Connect().AddrMapInsert(cbase+"membe",Base()+kCp_addr_membe); |
|
// add cpu register address ibus and rbus mappings |
AllIAddrMapInsert("psw" , 0177776); |
AllIAddrMapInsert("stklim" , 0177774); |
AllIAddrMapInsert("pirq" , 0177772); |
AllIAddrMapInsert("mbrk" , 0177770); |
AllIAddrMapInsert("cpuerr" , 0177766); |
AllIAddrMapInsert("sysid" , 0177764); |
AllIAddrMapInsert("hisize" , 0177762); |
AllIAddrMapInsert("losize" , 0177760); |
AllAddrMapInsert("psw" , 0177776); |
AllAddrMapInsert("stklim" , 0177774); |
AllAddrMapInsert("pirq" , 0177772); |
AllAddrMapInsert("mbrk" , 0177770); |
AllAddrMapInsert("cpuerr" , 0177766); |
AllAddrMapInsert("sysid" , 0177764); |
AllAddrMapInsert("hisize" , 0177762); |
AllAddrMapInsert("losize" , 0177760); |
|
AllIAddrMapInsert("hm" , 0177752); |
AllIAddrMapInsert("maint" , 0177750); |
AllIAddrMapInsert("cntrl" , 0177746); |
AllIAddrMapInsert("syserr" , 0177744); |
AllIAddrMapInsert("hiaddr" , 0177742); |
AllIAddrMapInsert("loaddr" , 0177740); |
AllAddrMapInsert("hm" , 0177752); |
AllAddrMapInsert("maint" , 0177750); |
AllAddrMapInsert("cntrl" , 0177746); |
AllAddrMapInsert("syserr" , 0177744); |
AllAddrMapInsert("hiaddr" , 0177742); |
AllAddrMapInsert("loaddr" , 0177740); |
|
AllIAddrMapInsert("ssr2" , 0177576); |
AllIAddrMapInsert("ssr1" , 0177574); |
AllIAddrMapInsert("ssr0" , 0177572); |
AllAddrMapInsert("ssr2" , 0177576); |
AllAddrMapInsert("ssr1" , 0177574); |
AllAddrMapInsert("ssr0" , 0177572); |
|
AllIAddrMapInsert("sdreg" , 0177570); |
AllAddrMapInsert("sdreg" , 0177570); |
|
AllIAddrMapInsert("ssr3" , 0172516); |
AllAddrMapInsert("ssr3" , 0172516); |
|
// add mmu segment register files |
string sdr = "sdr"; |
197,18 → 188,18
string sar = "sar"; |
for (char i=0; i<8; i++) { |
char ichar = '0'+i; |
AllIAddrMapInsert(sdr+"ki."+ichar, 0172300+2*i); |
AllIAddrMapInsert(sdr+"kd."+ichar, 0172320+2*i); |
AllIAddrMapInsert(sar+"ki."+ichar, 0172340+2*i); |
AllIAddrMapInsert(sar+"kd."+ichar, 0172360+2*i); |
AllIAddrMapInsert(sdr+"si."+ichar, 0172200+2*i); |
AllIAddrMapInsert(sdr+"sd."+ichar, 0172220+2*i); |
AllIAddrMapInsert(sar+"si."+ichar, 0172240+2*i); |
AllIAddrMapInsert(sar+"sd."+ichar, 0172260+2*i); |
AllIAddrMapInsert(sdr+"ui."+ichar, 0177600+2*i); |
AllIAddrMapInsert(sdr+"ud."+ichar, 0177620+2*i); |
AllIAddrMapInsert(sar+"ui."+ichar, 0177640+2*i); |
AllIAddrMapInsert(sar+"ud."+ichar, 0177660+2*i); |
AllAddrMapInsert(sdr+"ki."+ichar, 0172300+2*i); |
AllAddrMapInsert(sdr+"kd."+ichar, 0172320+2*i); |
AllAddrMapInsert(sar+"ki."+ichar, 0172340+2*i); |
AllAddrMapInsert(sar+"kd."+ichar, 0172360+2*i); |
AllAddrMapInsert(sdr+"si."+ichar, 0172200+2*i); |
AllAddrMapInsert(sdr+"sd."+ichar, 0172220+2*i); |
AllAddrMapInsert(sar+"si."+ichar, 0172240+2*i); |
AllAddrMapInsert(sar+"sd."+ichar, 0172260+2*i); |
AllAddrMapInsert(sdr+"ui."+ichar, 0177600+2*i); |
AllAddrMapInsert(sdr+"ud."+ichar, 0177620+2*i); |
AllAddrMapInsert(sar+"ui."+ichar, 0177640+2*i); |
AllAddrMapInsert(sar+"ud."+ichar, 0177660+2*i); |
} |
|
return; |
298,9 → 289,9
|
int Rw11Cpu::AddMembe(RlinkCommandList& clist, uint16_t be, bool stick) |
{ |
uint16_t data = be & kCPMEMBE_M_BE; |
if (stick) data |= kCPMEMBE_M_STICK; |
return clist.AddWreg(fBase+kCPMEMBE, data); |
uint16_t data = be & kCp_membe_m_be; |
if (stick) data |= kCp_membe_m_stick; |
return clist.AddWreg(fBase+kCp_addr_membe, data); |
} |
|
//------------------------------------------+----------------------------------- |
327,35 → 318,14
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
int Rw11Cpu::AddRbibr(RlinkCommandList& clist, uint16_t ibaddr, size_t size) |
{ |
if ((ibaddr & 0160001) != 0160000) |
throw Rexception("Rw11Cpu::AddRbibr", "ibaddr out of IO page or odd"); |
|
return clist.AddRblk(IbusRemoteAddr(ibaddr), size); |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
int Rw11Cpu::AddWbibr(RlinkCommandList& clist, uint16_t ibaddr, |
std::vector<uint16_t> block) |
{ |
if ((ibaddr & 0160001) != 0160000) |
throw Rexception("Rw11Cpu::AddWbibr", "ibaddr out of IO page or odd"); |
|
return clist.AddWblk(IbusRemoteAddr(ibaddr), block); |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
int Rw11Cpu::AddLalh(RlinkCommandList& clist, uint32_t addr, uint16_t mode) |
{ |
uint16_t al = uint16_t(addr); |
uint16_t ah = uint16_t(addr>>16) & kCPAH_M_ADDR; |
ah |= mode & (kCPAH_M_22BIT|kCPAH_M_UBMAP); |
int ind = clist.AddWreg(fBase+kCPAL, al); |
clist.AddWreg(fBase+kCPAH, ah); |
uint16_t ah = uint16_t(addr>>16) & kCp_ah_m_addr; |
ah |= mode & (kCp_ah_m_22bit|kCp_ah_m_ubmap); |
int ind = clist.AddWreg(fBase+kCp_addr_al, al); |
clist.AddWreg(fBase+kCp_addr_ah, ah); |
return ind; |
} |
|
373,7 → 343,7
int ind = AddLalh(clist, addr, mode); |
while (size > 0) { |
size_t bsize = (size>blkmax) ? blkmax : size; |
clist.AddRblk(fBase+kCPMEMI, buf, bsize); |
clist.AddRblk(fBase+kCp_addr_memi, buf, bsize); |
buf += bsize; |
size -= bsize; |
} |
395,7 → 365,7
int ind = AddLalh(clist, addr, mode); |
while (size > 0) { |
size_t bsize = (size>blkmax) ? blkmax : size; |
clist.AddWblk(fBase+kCPMEMI, buf, bsize); |
clist.AddWblk(fBase+kCp_addr_memi, buf, bsize); |
buf += bsize; |
size -= bsize; |
} |
414,8 → 384,8
while (nword>ndone) { |
size_t nblk = min(blkmax, nword-ndone); |
RlinkCommandList clist; |
clist.AddWreg(fBase+kCPAL, addr+2*ndone); |
clist.AddRblk(fBase+kCPMEMI, data.data()+ndone, nblk); |
clist.AddWreg(fBase+kCp_addr_al, addr+2*ndone); |
clist.AddRblk(fBase+kCp_addr_memi, data.data()+ndone, nblk); |
if (!Server().Exec(clist, emsg)) return false; |
ndone += nblk; |
} |
434,8 → 404,8
while (nword>ndone) { |
size_t nblk = min(blkmax, nword-ndone); |
RlinkCommandList clist; |
clist.AddWreg(fBase+kCPAL, addr+2*ndone); |
clist.AddWblk(fBase+kCPMEMI, data.data()+ndone, nblk); |
clist.AddWreg(fBase+kCp_addr_al, addr+2*ndone); |
clist.AddWblk(fBase+kCp_addr_memi, data.data()+ndone, nblk); |
if (!Server().Exec(clist, emsg)) return false; |
ndone += nblk; |
} |
456,13 → 426,13
int iib = -1; |
int irb = -1; |
if (dsc.fProbeInt) { |
clist.AddWreg(fBase+kCPAL, dsc.fAddr); |
iib = clist.AddRreg(fBase+kCPMEM); |
clist.SetLastExpectStatus(0,0); // disable stat check |
clist.AddWreg(fBase+kCp_addr_al, dsc.fAddr); |
iib = clist.AddRreg(fBase+kCp_addr_mem); |
clist.SetLastExpect(new RlinkCommandExpect(0,0xff)); // disable stat check |
} |
if (dsc.fProbeRem) { |
irb = AddRibr(clist, dsc.fAddr); |
clist.SetLastExpectStatus(0,0); // disable stat check |
clist.SetLastExpect(new RlinkCommandExpect(0,0xff)); // disable stat check |
} |
|
Server().Exec(clist); |
708,10 → 678,8
if (!MemWrite(aload, code, emsg)) return false; |
|
RlinkCommandList clist; |
clist.AddWreg(fBase+kCPCNTL, kCPFUNC_STOP); // stop, just in case |
clist.AddWreg(fBase+kCPCNTL, kCPFUNC_CRESET); // init cpu and bus |
clist.AddWreg(fBase+kCPPC, astart); // load PC |
clist.AddWreg(fBase+kCPCNTL, kCPFUNC_START); // and start |
clist.AddWreg(fBase+kCp_addr_pc, astart); |
clist.AddWreg(fBase+kCp_addr_cntl, kCp_func_start); |
SetCpuGoUp(); |
if (!Server().Exec(clist, emsg)) return false; |
|
735,7 → 703,7
|
void Rw11Cpu::SetCpuGoDown(uint16_t stat) |
{ |
if ((stat & kCPSTAT_M_CpuGo) == 0) { |
if ((stat & kCp_stat_m_cpugo) == 0) { |
boost::lock_guard<boost::mutex> lock(fCpuGoMutex); |
fCpuGo = false; |
fCpuStat = stat; |
764,19 → 732,14
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
void Rw11Cpu::AllIAddrMapInsert(const std::string& name, uint16_t ibaddr) |
void Rw11Cpu::AllAddrMapInsert(const std::string& name, uint16_t ibaddr) |
{ |
string rbname = "i"; |
rbname += '0'+Index(); |
rbname += '.'; |
rbname += name; |
Connect().AddrMapInsert(rbname, IbusRemoteAddr(ibaddr)); |
IAddrMapInsert(name, ibaddr); |
uint16_t rbaddr = IbusRemoteAddr(ibaddr); |
RAddrMapInsert(name, rbaddr); |
|
// add ix. to name in common Connect AddrMap to keep name unique |
string cname = "i"; |
cname += '0'+Index(); |
cname += '.'; |
cname += name; |
Connect().AddrMapInsert(cname, rbaddr); |
|
return; |
} |
|
783,27 → 746,10
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
void Rw11Cpu::AllRAddrMapInsert(const std::string& name, uint16_t rbaddr) |
{ |
RAddrMapInsert(name, rbaddr); |
|
// add cx. to name in common Connect AddrMap to keep name unique |
string cname = "c"; |
cname += '0'+Index(); |
cname += '.'; |
cname += name; |
Connect().AddrMapInsert(cname, rbaddr); |
|
return; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
void Rw11Cpu::W11AttnHandler() |
{ |
RlinkCommandList clist; |
clist.AddRreg(fBase+kCPSTAT); |
clist.AddRreg(fBase+kCp_addr_stat); |
Server().Exec(clist); |
SetCpuGoDown(clist[0].Data()); |
return; |
830,7 → 776,6
<< " : " << it->second << endl; |
} |
fIAddrMap.Dump(os, ind+2, "fIAddrMap: "); |
fRAddrMap.Dump(os, ind+2, "fRAddrMap: "); |
fStats.Dump(os, ind+2, "fStats: "); |
return; |
} |
/tools/src/librw11/Rw11UnitDisk.hpp
1,4 → 1,4
// $Id: Rw11UnitDisk.hpp 680 2015-05-14 13:29:46Z mueller $ |
// $Id: Rw11UnitDisk.hpp 647 2015-02-17 22:35:36Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-03-21 659 1.0.2 add fEnabled, Enabled() |
// 2015-02-18 647 1.0.1 add Nwrd2Nblk() |
// 2013-04-19 507 1.0 Initial version |
// 2013-02-19 490 0.1 First draft |
22,7 → 21,7
|
/*! |
\file |
\version $Id: Rw11UnitDisk.hpp 680 2015-05-14 13:29:46Z mueller $ |
\version $Id: Rw11UnitDisk.hpp 647 2015-02-17 22:35:36Z mueller $ |
\brief Declaration of class Rw11UnitDisk. |
*/ |
|
43,7 → 42,6
virtual void SetType(const std::string& type); |
|
const std::string& Type() const; |
virtual bool Enabled() const; |
size_t NCylinder() const; |
size_t NHead() const; |
size_t NSector() const; |
66,14 → 64,13
virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; |
|
protected: |
std::string fType; //!< drive type |
bool fEnabled; //!< unit enabled |
size_t fNCyl; //!< # cylinder |
size_t fNHead; //!< # heads (aka surfaces) |
size_t fNSect; //!< # sectors |
size_t fBlksize; //!< block size (in bytes) |
size_t fNBlock; //!< # blocks |
bool fWProt; //!< unit write protected |
std::string fType; |
size_t fNCyl; |
size_t fNHead; |
size_t fNSect; |
size_t fBlksize; |
size_t fNBlock; |
bool fWProt; |
}; |
|
} // end namespace Retro |
/tools/src/librw11/Rw11CntlRL11.cpp
1,4 → 1,4
// $Id: Rw11CntlRL11.cpp 669 2015-04-26 21:20:32Z mueller $ |
// $Id: Rw11CntlRL11.cpp 655 2015-03-04 20:35:21Z mueller $ |
// |
// Copyright 2014-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Other credits: |
23,7 → 23,7
|
/*! |
\file |
\version $Id: Rw11CntlRL11.cpp 669 2015-04-26 21:20:32Z mueller $ |
\version $Id: Rw11CntlRL11.cpp 655 2015-03-04 20:35:21Z mueller $ |
\brief Implemenation of Rw11CntlRL11. |
*/ |
|
233,10 → 233,10
|
// add device register address ibus and rbus mappings |
// done here because now Cntl bound to Cpu and Cntl probed |
Cpu().AllIAddrMapInsert(Name()+".cs", Base() + kRLCS); |
Cpu().AllIAddrMapInsert(Name()+".ba", Base() + kRLBA); |
Cpu().AllIAddrMapInsert(Name()+".da", Base() + kRLDA); |
Cpu().AllIAddrMapInsert(Name()+".mp", Base() + kRLMP); |
Cpu().AllAddrMapInsert(Name()+".cs", Base() + kRLCS); |
Cpu().AllAddrMapInsert(Name()+".ba", Base() + kRLBA); |
Cpu().AllAddrMapInsert(Name()+".da", Base() + kRLDA); |
Cpu().AllAddrMapInsert(Name()+".mp", Base() + kRLMP); |
|
// setup primary info clist |
fPrimClist.Clear(); |
269,8 → 269,8
RlinkCommandList clist; |
|
// only two mayor drive states are used |
// on: st=lock; ho=1; bh=1; co=0; wl=? ( file attached) |
// off: st=load; ho=0; bh=1; co=1; (no file attached) |
// on: st=lock; ho=1; bh=1; co=0; wl=? ( file connected) |
// off: st=load; ho=0; bh=1; co=1; (no file connected) |
|
uint16_t sta = 0; |
if (unit.Type() == "rl02") // is it RL02 |
430,11 → 430,11
<< " da=" << RosPrintBvi(rlda,8) |
<< " ad=" << RosPrintBvi(addr,8,18) |
<< " fu=" << fumnemo[fu&0x7] |
<< " pa=" << ds |
<< " ds=" << ds |
<< "," << RosPrintf(ca,"d",3) |
<< "," << hs |
<< "," << RosPrintf(sa,"d",2) |
<< " la,nw=" << RosPrintf(lba,"d",5) |
<< " lba,nw=" << RosPrintf(lba,"d",5) |
<< ","; |
if (nwrd==65536) lmsg << " (0)"; else lmsg << RosPrintf(nwrd,"d",4); |
if (ovr) lmsg << "!"; |
527,7 → 527,7
AddErrorExit(clist, kERR_M_DE); |
} else { |
fRdma.QueueDiskWrite(addr, nwrd, |
Rw11Cpu::kCPAH_M_22BIT|Rw11Cpu::kCPAH_M_UBMAP, |
Rw11Cpu::kCp_ah_m_22bit|Rw11Cpu::kCp_ah_m_ubmap, |
lba, &unit); |
} |
|
534,7 → 534,7
} else if (fu == kFUNC_WCHK) { // Write Check ------------------- |
fStats.Inc(kStatNFuncWchk ); |
fRdma.QueueDiskWriteCheck(addr, nwrd, |
Rw11Cpu::kCPAH_M_22BIT|Rw11Cpu::kCPAH_M_UBMAP, |
Rw11Cpu::kCp_ah_m_22bit|Rw11Cpu::kCp_ah_m_ubmap, |
lba, &unit); |
|
} else if (fu == kFUNC_READ || // Read or |
542,7 → 542,7
fStats.Inc(fu==kFUNC_READ ? kStatNFuncRead : kStatNFuncRnhc); |
|
fRdma.QueueDiskRead(addr, nwrd, |
Rw11Cpu::kCPAH_M_22BIT|Rw11Cpu::kCPAH_M_UBMAP, |
Rw11Cpu::kCp_ah_m_22bit|Rw11Cpu::kCp_ah_m_ubmap, |
lba, &unit); |
} |
|
/tools/src/librw11/Rw11CntlRK11.hpp
1,4 → 1,4
// $Id: Rw11CntlRK11.hpp 665 2015-04-07 07:13:49Z mueller $ |
// $Id: Rw11CntlRK11.hpp 647 2015-02-17 22:35:36Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
23,7 → 23,7
|
/*! |
\file |
\version $Id: Rw11CntlRK11.hpp 665 2015-04-07 07:13:49Z mueller $ |
\version $Id: Rw11CntlRK11.hpp 647 2015-02-17 22:35:36Z mueller $ |
\brief Declaration of class Rw11CntlRK11. |
*/ |
|
62,13 → 62,13
static const uint16_t kIbaddr = 0177400; //!< RK11 default address |
static const int kLam = 4; //!< RK11 default lam |
|
static const uint16_t kRKDS = 000; //!< RKDS reg offset |
static const uint16_t kRKER = 002; //!< RKER reg offset |
static const uint16_t kRKCS = 004; //!< RKCS reg offset |
static const uint16_t kRKWC = 006; //!< RKWC reg offset |
static const uint16_t kRKBA = 010; //!< RKBA reg offset |
static const uint16_t kRKDA = 012; //!< RKDA reg offset |
static const uint16_t kRKMR = 014; //!< RKMR reg offset |
static const uint16_t kRKDS = 000; //!< RKDS register address offset |
static const uint16_t kRKER = 002; //!< RKER register address offset |
static const uint16_t kRKCS = 004; //!< RKCS register address offset |
static const uint16_t kRKWC = 006; //!< RKWC register address offset |
static const uint16_t kRKBA = 010; //!< RKBA register address offset |
static const uint16_t kRKDA = 012; //!< RKDA register address offset |
static const uint16_t kRKMR = 014; //!< RKMR register address offset |
|
static const uint16_t kProbeOff = kRKCS; //!< probe address offset (rkcs) |
static const bool kProbeInt = true; //!< probe int active |
/tools/src/librw11/Rw11CntlDL11.cpp
1,4 → 1,4
// $Id: Rw11CntlDL11.cpp 659 2015-03-22 23:15:51Z mueller $ |
// $Id: Rw11CntlDL11.cpp 632 2015-01-11 12:30:03Z mueller $ |
// |
// Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
23,7 → 23,7
|
/*! |
\file |
\version $Id: Rw11CntlDL11.cpp 659 2015-03-22 23:15:51Z mueller $ |
\version $Id: Rw11CntlDL11.cpp 632 2015-01-11 12:30:03Z mueller $ |
\brief Implemenation of Rw11CntlDL11. |
*/ |
|
111,10 → 111,10
|
// add device register address ibus and rbus mappings |
// done here because now Cntl bound to Cpu and Cntl probed |
Cpu().AllIAddrMapInsert(Name()+".rcsr", Base() + kRCSR); |
Cpu().AllIAddrMapInsert(Name()+".rbuf", Base() + kRBUF); |
Cpu().AllIAddrMapInsert(Name()+".xcsr", Base() + kXCSR); |
Cpu().AllIAddrMapInsert(Name()+".xbuf", Base() + kXBUF); |
Cpu().AllAddrMapInsert(Name()+".rcsr", Base() + kRCSR); |
Cpu().AllAddrMapInsert(Name()+".rbuf", Base() + kRBUF); |
Cpu().AllAddrMapInsert(Name()+".xcsr", Base() + kXCSR); |
Cpu().AllAddrMapInsert(Name()+".xbuf", Base() + kXBUF); |
|
// setup primary info clist |
fPrimClist.Clear(); |
/tools/src/librw11/Rw11CntlPC11.hpp
1,4 → 1,4
// $Id: Rw11CntlPC11.hpp 665 2015-04-07 07:13:49Z mueller $ |
// $Id: Rw11CntlPC11.hpp 623 2014-12-29 19:11:40Z mueller $ |
// |
// Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
20,7 → 20,7
|
/*! |
\file |
\version $Id: Rw11CntlPC11.hpp 665 2015-04-07 07:13:49Z mueller $ |
\version $Id: Rw11CntlPC11.hpp 623 2014-12-29 19:11:40Z mueller $ |
\brief Declaration of class Rw11CntlPC11. |
*/ |
|
53,10 → 53,10
static const uint16_t kIbaddr = 0177550; //!< PC11 default address |
static const int kLam = 10; //!< PC11 default lam |
|
static const uint16_t kRCSR = 000; //!< RCSR reg offset |
static const uint16_t kRBUF = 002; //!< RBUF reg offset |
static const uint16_t kPCSR = 004; //!< PCSR reg offset |
static const uint16_t kPBUF = 006; //!< PBUF reg offset |
static const uint16_t kRCSR = 000; //!< RCSR register address offset |
static const uint16_t kRBUF = 002; //!< RBUF register address offset |
static const uint16_t kPCSR = 004; //!< PCSR register address offset |
static const uint16_t kPBUF = 006; //!< PBUF register address offset |
|
static const uint16_t kUnit_PR = 0; //<! unit number of paper reader |
static const uint16_t kUnit_PP = 1; //<! unit number of paper puncher |
/tools/src/librw11/Rw11Cpu.hpp
1,4 → 1,4
// $Id: Rw11Cpu.hpp 675 2015-05-08 21:05:08Z mueller $ |
// $Id: Rw11Cpu.hpp 626 2015-01-03 14:41:37Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,10 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-05-08 675 1.2.3 w11a start/stop/suspend overhaul |
// 2015-04-25 668 1.2.2 add AddRbibr(), AddWbibr() |
// 2015-04-03 661 1.2.1 add kStat_M_* defs |
// 2015-03-21 659 1.2 add RAddrMap; add AllRAddrMapInsert(); |
// 2015-01-01 626 1.1 Adopt for rlink v4 and 4k ibus window; add IAddrMap |
// 2013-04-14 506 1.0.1 add AddLalh(),AddRMem(),AddWMem() |
// 2013-04-12 504 1.0 Initial version |
26,7 → 22,7
|
/*! |
\file |
\version $Id: Rw11Cpu.hpp 675 2015-05-08 21:05:08Z mueller $ |
\version $Id: Rw11Cpu.hpp 626 2015-01-03 14:41:37Z mueller $ |
\brief Declaration of class Rw11Cpu. |
*/ |
|
92,20 → 88,15
int AddWibr(RlinkCommandList& clist, uint16_t ibaddr, |
uint16_t data); |
|
int AddRbibr(RlinkCommandList& clist, uint16_t ibaddr, |
size_t size); |
int AddWbibr(RlinkCommandList& clist, uint16_t ibaddr, |
std::vector<uint16_t> block); |
|
int AddLalh(RlinkCommandList& clist, uint32_t addr, |
uint16_t mode=kCPAH_M_22BIT); |
uint16_t mode=kCp_ah_m_22bit); |
int AddRMem(RlinkCommandList& clist, uint32_t addr, |
uint16_t* buf, size_t size, |
uint16_t mode=kCPAH_M_22BIT, |
uint16_t mode=kCp_ah_m_22bit, |
bool singleblk=false); |
int AddWMem(RlinkCommandList& clist, uint32_t addr, |
const uint16_t* buf, size_t size, |
uint16_t mode=kCPAH_M_22BIT, |
uint16_t mode=kCp_ah_m_22bit, |
bool singleblk=false); |
|
bool MemRead(uint16_t addr, std::vector<uint16_t>& data, |
126,8 → 117,7
uint16_t CpuStat() const; |
|
uint16_t IbusRemoteAddr(uint16_t ibaddr) const; |
void AllIAddrMapInsert(const std::string& name, uint16_t ibaddr); |
void AllRAddrMapInsert(const std::string& name, uint16_t rbaddr); |
void AllAddrMapInsert(const std::string& name, uint16_t ibaddr); |
|
bool IAddrMapInsert(const std::string& name, uint16_t ibaddr); |
bool IAddrMapErase(const std::string& name); |
135,12 → 125,6
void IAddrMapClear(); |
const RlinkAddrMap& IAddrMap() const; |
|
bool RAddrMapInsert(const std::string& name, uint16_t rbaddr); |
bool RAddrMapErase(const std::string& name); |
bool RAddrMapErase(uint16_t rbaddr); |
void RAddrMapClear(); |
const RlinkAddrMap& RAddrMap() const; |
|
void W11AttnHandler(); |
|
const Rstats& Stats() const; |
147,62 → 131,52
virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; |
|
// some constants (also defined in cpp) |
static const uint16_t kCPCONF = 0x0000; //!< CPCONF reg offset |
static const uint16_t kCPCNTL = 0x0001; //!< CPADDR reg offset |
static const uint16_t kCPSTAT = 0x0002; //!< CPSTAT reg offset |
static const uint16_t kCPPSW = 0x0003; //!< CPPSW reg offset |
static const uint16_t kCPAL = 0x0004; //!< CPAL reg offset |
static const uint16_t kCPAH = 0x0005; //!< CPAH reg offset |
static const uint16_t kCPMEM = 0x0006; //!< CPMEM reg offset |
static const uint16_t kCPMEMI = 0x0007; //!< CPMEMI reg offset |
static const uint16_t kCPR0 = 0x0008; //!< CPR0 reg offset |
static const uint16_t kCPPC = 0x000f; //!< CPPC reg offset |
static const uint16_t kCPMEMBE = 0x0010; //!< CPMEMBE reg offset |
static const uint16_t kCp_addr_conf = 0x0000; //!< |
static const uint16_t kCp_addr_cntl = 0x0001; //!< |
static const uint16_t kCp_addr_stat = 0x0002; //!< |
static const uint16_t kCp_addr_psw = 0x0003; //!< |
static const uint16_t kCp_addr_al = 0x0004; //!< |
static const uint16_t kCp_addr_ah = 0x0005; //!< |
static const uint16_t kCp_addr_mem = 0x0006; //!< |
static const uint16_t kCp_addr_memi = 0x0007; //!< |
static const uint16_t kCp_addr_r0 = 0x0008; //!< |
static const uint16_t kCp_addr_pc = 0x000f; //!< |
static const uint16_t kCp_addr_membe = 0x0010; //!< |
|
static const uint16_t kCPFUNC_NOOP = 0x0000; //!< |
static const uint16_t kCPFUNC_START = 0x0001; //!< |
static const uint16_t kCPFUNC_STOP = 0x0002; //!< |
static const uint16_t kCPFUNC_STEP = 0x0003; //!< |
static const uint16_t kCPFUNC_CRESET = 0x0004; //!< |
static const uint16_t kCPFUNC_BRESET = 0x0005; //!< |
static const uint16_t kCPFUNC_SUSPEND = 0x0006; //!< |
static const uint16_t kCPFUNC_RESUME = 0x0007; //!< |
static const uint16_t kCp_func_noop = 0x0000; //!< |
static const uint16_t kCp_func_start = 0x0001; //!< |
static const uint16_t kCp_func_stop = 0x0002; //!< |
static const uint16_t kCp_func_cont = 0x0003; //!< |
static const uint16_t kCp_func_step = 0x0004; //!< |
static const uint16_t kCp_func_reset = 0x000f; //!< |
|
static const uint16_t kCPSTAT_M_SuspExt = kWBit09; //!< |
static const uint16_t kCPSTAT_M_SuspInt = kWBit08; //!< |
static const uint16_t kCPSTAT_M_CpuRust = 0x00f0; //!< |
static const uint16_t kCPSTAT_V_CpuRust = 4; //!< |
static const uint16_t kCPSTAT_B_CpuRust = 0x000f; //!< |
static const uint16_t kCPSTAT_M_CpuSusp = kWBit03; //!< |
static const uint16_t kCPSTAT_M_CpuGo = kWBit02; //!< |
static const uint16_t kCPSTAT_M_CmdMErr = kWBit01; //!< |
static const uint16_t kCPSTAT_M_CmdErr = kWBit00; //!< |
static const uint16_t kCp_stat_m_cpurust = 0x00f0; //!< |
static const uint16_t kCp_stat_v_cpurust = 4; //!< |
static const uint16_t kCp_stat_b_cpurust = 0x000f; //!< |
static const uint16_t kCp_stat_m_cpuhalt = kWBit03; //!< |
static const uint16_t kCp_stat_m_cpugo = kWBit02; //!< |
static const uint16_t kCp_stat_m_cmdmerr = kWBit01; //!< |
static const uint16_t kCp_stat_m_cmderr = kWBit00; //!< |
|
static const uint16_t kCPURUST_INIT = 0x0; //!< cpu in init state |
static const uint16_t kCPURUST_HALT = 0x1; //!< cpu executed HALT |
static const uint16_t kCPURUST_RESET = 0x2; //!< cpu was reset |
static const uint16_t kCPURUST_STOP = 0x3; //!< cpu was stopped |
static const uint16_t kCPURUST_STEP = 0x4; //!< cpu was stepped |
static const uint16_t kCPURUST_SUSP = 0x5; //!< cpu was suspended |
static const uint16_t kCPURUST_RUNS = 0x7; //!< cpu running |
static const uint16_t kCPURUST_VECFET = 0x8; //!< vector fetch halt |
static const uint16_t kCPURUST_RECRSV = 0x9; //!< rec red-stack halt |
static const uint16_t kCPURUST_SFAIL = 0xa; //!< sequencer failure |
static const uint16_t kCPURUST_VFAIL = 0xb; //!< vmbox failure |
static const uint16_t kCp_cpurust_init = 0x0; //!< cpu in init state |
static const uint16_t kCp_cpurust_halt = 0x1; //!< cpu executed HALT |
static const uint16_t kCp_cpurust_reset = 0x2; //!< cpu was reset |
static const uint16_t kCp_cpurust_stop = 0x3; //!< cpu was stopped |
static const uint16_t kCp_cpurust_step = 0x4; //!< cpu was stepped |
static const uint16_t kCp_cpurust_susp = 0x5; //!< cpu was suspended |
static const uint16_t kCp_cpurust_runs = 0x7; //!< cpu running |
static const uint16_t kCp_cpurust_vecfet = 0x8; //!< vector fetch halt |
static const uint16_t kCp_cpurust_recrsv = 0x9; //!< rec red-stack halt |
static const uint16_t kCp_cpurust_sfail = 0xa; //!< sequencer failure |
static const uint16_t kCp_cpurust_vfail = 0xb; //!< vmbox failure |
|
static const uint16_t kCPAH_M_ADDR = 0x003f; //!< |
static const uint16_t kCPAH_M_22BIT = kWBit06; //!< |
static const uint16_t kCPAH_M_UBMAP = kWBit07; //!< |
static const uint16_t kCp_ah_m_addr = 0x003f; //!< |
static const uint16_t kCp_ah_m_22bit = kWBit06; //!< |
static const uint16_t kCp_ah_m_ubmap = kWBit07; //!< |
|
static const uint16_t kCPMEMBE_M_STICK = kWBit02; //!< |
static const uint16_t kCPMEMBE_M_BE = 0x0003; //!< |
static const uint16_t kCp_membe_m_stick = kWBit02; //!< |
static const uint16_t kCp_membe_m_be = 0x0003; //!< |
|
// defs for the four status bits defined by w11 rbus iface |
static const uint8_t kStat_M_CmdErr = kBBit07; //!< stat: cmderr flag |
static const uint8_t kStat_M_CmdMErr = kBBit06; //!< stat: cmdmerr flag |
static const uint8_t kStat_M_CpuHalt = kBBit05; //!< stat: cpuhalt flag |
static const uint8_t kStat_M_CpuGo = kBBit04; //!< stat: cpugo flag |
|
private: |
Rw11Cpu() {} //!< default ctor blocker |
|
218,7 → 192,6
boost::condition_variable fCpuGoCond; |
cmap_t fCntlMap; //!< name->cntl map |
RlinkAddrMap fIAddrMap; //!< ibus name<->address mapping |
RlinkAddrMap fRAddrMap; //!< rbus name<->address mapping |
Rstats fStats; //!< statistics |
}; |
|
/tools/src/librw11/Rw11CntlLP11.cpp
1,4 → 1,4
// $Id: Rw11CntlLP11.cpp 659 2015-03-22 23:15:51Z mueller $ |
// $Id: Rw11CntlLP11.cpp 625 2014-12-30 16:17:45Z mueller $ |
// |
// Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
21,7 → 21,7
|
/*! |
\file |
\version $Id: Rw11CntlLP11.cpp 659 2015-03-22 23:15:51Z mueller $ |
\version $Id: Rw11CntlLP11.cpp 625 2014-12-30 16:17:45Z mueller $ |
\brief Implemenation of Rw11CntlLP11. |
*/ |
|
101,8 → 101,8
|
// add device register address ibus and rbus mappings |
// done here because now Cntl bound to Cpu and Cntl probed |
Cpu().AllIAddrMapInsert(Name()+".csr", Base() + kCSR); |
Cpu().AllIAddrMapInsert(Name()+".buf", Base() + kBUF); |
Cpu().AllAddrMapInsert(Name()+".csr", Base() + kCSR); |
Cpu().AllAddrMapInsert(Name()+".buf", Base() + kBUF); |
|
// setup primary info clist |
fPrimClist.Clear(); |
/tools/src/librw11/Rw11CntlPC11.cpp
1,4 → 1,4
// $Id: Rw11CntlPC11.cpp 659 2015-03-22 23:15:51Z mueller $ |
// $Id: Rw11CntlPC11.cpp 625 2014-12-30 16:17:45Z mueller $ |
// |
// Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
20,7 → 20,7
|
/*! |
\file |
\version $Id: Rw11CntlPC11.cpp 659 2015-03-22 23:15:51Z mueller $ |
\version $Id: Rw11CntlPC11.cpp 625 2014-12-30 16:17:45Z mueller $ |
\brief Implemenation of Rw11CntlPC11. |
*/ |
|
109,10 → 109,10
|
// add device register address ibus and rbus mappings |
// done here because now Cntl bound to Cpu and Cntl probed |
Cpu().AllIAddrMapInsert(Name()+".rcsr", Base() + kRCSR); |
Cpu().AllIAddrMapInsert(Name()+".rbuf", Base() + kRBUF); |
Cpu().AllIAddrMapInsert(Name()+".pcsr", Base() + kPCSR); |
Cpu().AllIAddrMapInsert(Name()+".pbuf", Base() + kPBUF); |
Cpu().AllAddrMapInsert(Name()+".rcsr", Base() + kRCSR); |
Cpu().AllAddrMapInsert(Name()+".rbuf", Base() + kRBUF); |
Cpu().AllAddrMapInsert(Name()+".pcsr", Base() + kPCSR); |
Cpu().AllAddrMapInsert(Name()+".pbuf", Base() + kPBUF); |
|
// setup primary info clist |
fPrimClist.Clear(); |
/tools/src/librw11/Rw11CntlDL11.hpp
1,4 → 1,4
// $Id: Rw11CntlDL11.hpp 665 2015-04-07 07:13:49Z mueller $ |
// $Id: Rw11CntlDL11.hpp 623 2014-12-29 19:11:40Z mueller $ |
// |
// Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
22,7 → 22,7
|
/*! |
\file |
\version $Id: Rw11CntlDL11.hpp 665 2015-04-07 07:13:49Z mueller $ |
\version $Id: Rw11CntlDL11.hpp 623 2014-12-29 19:11:40Z mueller $ |
\brief Declaration of class Rw11CntlDL11. |
*/ |
|
56,10 → 56,10
static const uint16_t kIbaddr = 0177560; //!< DL11 default address |
static const int kLam = 1; //!< DL11 default lam |
|
static const uint16_t kRCSR = 000; //!< RCSR reg offset |
static const uint16_t kRBUF = 002; //!< RBUF reg offset |
static const uint16_t kXCSR = 004; //!< XCSR reg offset |
static const uint16_t kXBUF = 006; //!< XBUF reg offset |
static const uint16_t kRCSR = 000; //!< RCSR register address offset |
static const uint16_t kRBUF = 002; //!< RBUF register address offset |
static const uint16_t kXCSR = 004; //!< XCSR register address offset |
static const uint16_t kXBUF = 006; //!< XBUF register address offset |
|
static const uint16_t kProbeOff = kRCSR; //!< probe address offset (rcsr) |
static const bool kProbeInt = true; //!< probe int active |
/tools/src/librw11/Rw11Cpu.ipp
1,6 → 1,6
// $Id: Rw11Cpu.ipp 659 2015-03-22 23:15:51Z mueller $ |
// $Id: Rw11Cpu.ipp 621 2014-12-26 21:20:05Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-03-21 659 1.2 add RAddrMap |
// 2014-12-25 621 1.1 Adopt for 4k word ibus window; add IAddrMap |
// 2013-04-12 504 1.0 Initial version |
// 2013-01-27 478 0.1 First draft |
21,7 → 20,7
|
/*! |
\file |
\version $Id: Rw11Cpu.ipp 659 2015-03-22 23:15:51Z mueller $ |
\version $Id: Rw11Cpu.ipp 621 2014-12-26 21:20:05Z mueller $ |
\brief Implemenation (inline) of Rw11Cpu. |
*/ |
|
159,46 → 158,6
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline bool Rw11Cpu::RAddrMapInsert(const std::string& name, uint16_t ibaddr) |
{ |
return fRAddrMap.Insert(name, ibaddr); |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline bool Rw11Cpu::RAddrMapErase(const std::string& name) |
{ |
return fRAddrMap.Erase(name); |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline bool Rw11Cpu::RAddrMapErase(uint16_t ibaddr) |
{ |
return fRAddrMap.Erase(ibaddr); |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline void Rw11Cpu::RAddrMapClear() |
{ |
return fRAddrMap.Clear(); |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline const RlinkAddrMap& Rw11Cpu::RAddrMap() const |
{ |
return fRAddrMap; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline const Rstats& Rw11Cpu::Stats() const |
{ |
return fStats; |
/tools/src/librw11/Rw11CntlLP11.hpp
1,4 → 1,4
// $Id: Rw11CntlLP11.hpp 665 2015-04-07 07:13:49Z mueller $ |
// $Id: Rw11CntlLP11.hpp 623 2014-12-29 19:11:40Z mueller $ |
// |
// Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
20,7 → 20,7
|
/*! |
\file |
\version $Id: Rw11CntlLP11.hpp 665 2015-04-07 07:13:49Z mueller $ |
\version $Id: Rw11CntlLP11.hpp 623 2014-12-29 19:11:40Z mueller $ |
\brief Declaration of class Rw11CntlLP11. |
*/ |
|
50,8 → 50,8
static const uint16_t kIbaddr = 0177514; //!< LP11 default address |
static const int kLam = 8; //!< LP11 default lam |
|
static const uint16_t kCSR = 000; //!< CSR reg offset |
static const uint16_t kBUF = 002; //!< BUF reg offset |
static const uint16_t kCSR = 000; //!< CSR register address offset |
static const uint16_t kBUF = 002; //!< BUF register address offset |
|
static const uint16_t kProbeOff = kCSR; //!< probe address offset (rcsr) |
static const bool kProbeInt = true; //!< probe int active |
/tools/src/librw11/Rw11UnitVirt.ipp
1,6 → 1,6
// $Id: Rw11UnitVirt.ipp 680 2015-05-14 13:29:46Z mueller $ |
// $Id: Rw11UnitVirt.ipp 600 2014-11-02 22:33:02Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-05-13 680 1.2 Attach(): check for Enabled() |
// 2014-11-02 600 1.1.1 add (bool) cast, needed in 4.8.2 |
// 2013-05-03 515 1.1 use AttachDone(),DetachCleanup(),DetachDone() |
// 2013-03-03 494 1.0 Initial version |
22,7 → 21,7
|
/*! |
\file |
\version $Id: Rw11UnitVirt.ipp 680 2015-05-14 13:29:46Z mueller $ |
\version $Id: Rw11UnitVirt.ipp 600 2014-11-02 22:33:02Z mueller $ |
\brief Implemenation (inline) of Rw11UnitVirt. |
*/ |
|
74,10 → 73,6
// synchronize with server thread |
boost::lock_guard<RlinkConnect> lock(Connect()); |
if (fpVirt) Detach(); |
if (!Enabled()) { |
emsg.Init("Rw11UnitVirt::Attach","unit not enabled"); |
return false; |
} |
fpVirt.reset(TV::New(url, this, emsg)); |
if (fpVirt) AttachDone(); |
return (bool)fpVirt; |
/tools/src/librw11/Rw11UnitDisk.cpp
1,4 → 1,4
// $Id: Rw11UnitDisk.cpp 659 2015-03-22 23:15:51Z mueller $ |
// $Id: Rw11UnitDisk.cpp 561 2014-06-09 17:22:50Z mueller $ |
// |
// Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-03-21 659 1.0.1 add fEnabled, Enabled() |
// 2013-04-19 507 1.0 Initial version |
// 2013-02-19 490 0.1 First draft |
// --------------------------------------------------------------------------- |
20,7 → 19,7
|
/*! |
\file |
\version $Id: Rw11UnitDisk.cpp 659 2015-03-22 23:15:51Z mueller $ |
\version $Id: Rw11UnitDisk.cpp 561 2014-06-09 17:22:50Z mueller $ |
\brief Implemenation of Rw11UnitDisk. |
*/ |
|
44,7 → 43,6
Rw11UnitDisk::Rw11UnitDisk(Rw11Cntl* pcntl, size_t index) |
: Rw11UnitVirt<Rw11VirtDisk>(pcntl, index), |
fType(), |
fEnabled(false), |
fNCyl(0), |
fNHead(0), |
fNSect(0), |
103,7 → 101,6
RosFill bl(ind); |
os << bl << (text?text:"--") << "Rw11UnitDisk @ " << this << endl; |
os << bl << " fType: " << fType << endl; |
os << bl << " fEnabled: " << fEnabled << endl; |
os << bl << " fNCyl: " << fNCyl << endl; |
os << bl << " fNHead: " << fNHead << endl; |
os << bl << " fNSect: " << fNSect << endl; |
/tools/src/librw11/Rw11Unit.hpp
1,6 → 1,6
// $Id: Rw11Unit.hpp 680 2015-05-14 13:29:46Z mueller $ |
// $Id: Rw11Unit.hpp 515 2013-05-04 17:28:59Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-05-13 680 1.1.1 add Enabled() |
// 2013-05-03 515 1.1 use AttachDone(),DetachCleanup(),DetachDone() |
// 2013-05-01 513 1.0.1 add fAttachOpts, (Set)AttachOpts() |
// 2013-03-06 495 1.0 Initial version |
23,7 → 22,7
|
/*! |
\file |
\version $Id: Rw11Unit.hpp 680 2015-05-14 13:29:46Z mueller $ |
\version $Id: Rw11Unit.hpp 515 2013-05-04 17:28:59Z mueller $ |
\brief Declaration of class Rw11Unit. |
*/ |
|
62,8 → 61,6
RlinkConnect& Connect() const; |
RlogFile& LogFile() const; |
|
virtual bool Enabled() const; |
|
virtual bool Attach(const std::string& url, RerrMsg& emsg); |
virtual void Detach(); |
|
/tools/src/librw11/Rw11Unit.cpp
1,6 → 1,6
// $Id: Rw11Unit.cpp 680 2015-05-14 13:29:46Z mueller $ |
// $Id: Rw11Unit.cpp 515 2013-05-04 17:28:59Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-05-13 680 1.1.1 add Enabled() |
// 2013-05-03 515 1.1 use AttachDone(),DetachCleanup(),DetachDone() |
// 2013-03-06 495 1.0 Initial version |
// 2013-02-13 488 0.1 First draft |
21,7 → 20,7
|
/*! |
\file |
\version $Id: Rw11Unit.cpp 680 2015-05-14 13:29:46Z mueller $ |
\version $Id: Rw11Unit.cpp 515 2013-05-04 17:28:59Z mueller $ |
\brief Implemenation of Rw11Unit. |
*/ |
|
58,14 → 57,6
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
bool Rw11Unit::Enabled() const |
{ |
return true; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
bool Rw11Unit::Attach(const std::string& url, RerrMsg& emsg) |
{ |
emsg.Init("Rw11Unit::Attach","attach not available for this device type"); |
/tools/src/librw11/Rw11UnitRK11.cpp
1,4 → 1,4
// $Id: Rw11UnitRK11.cpp 659 2015-03-22 23:15:51Z mueller $ |
// $Id: Rw11UnitRK11.cpp 509 2013-04-21 20:46:20Z mueller $ |
// |
// Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
19,7 → 19,7
|
/*! |
\file |
\version $Id: Rw11UnitRK11.cpp 659 2015-03-22 23:15:51Z mueller $ |
\version $Id: Rw11UnitRK11.cpp 509 2013-04-21 20:46:20Z mueller $ |
\brief Implemenation of Rw11UnitRK11. |
*/ |
|
49,7 → 49,6
{ |
// setup disk geometry: only rk05 supported, no rk05f ! |
fType = "rk05"; |
fEnabled = true; |
fNCyl = 203; |
fNHead = 2; |
fNSect = 12; |
/tools/src/librwxxtpp/RtclRw11CntlRHRP.hpp
File deleted
/tools/src/librwxxtpp/RtclRw11CntlRHRP.cpp
File deleted
/tools/src/librwxxtpp/RtclRw11UnitRHRP.cpp
File deleted
/tools/src/librwxxtpp/RtclRw11UnitRHRP.hpp
File deleted
/tools/src/librwxxtpp/RtclRw11Cpu.cpp
1,6 → 1,6
// $Id: RtclRw11Cpu.cpp 675 2015-05-08 21:05:08Z mueller $ |
// $Id: RtclRw11Cpu.cpp 631 2015-01-09 21:36:51Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,12 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-05-04 674 1.2.2 w11a start/stop/suspend overhaul |
// 2015-04-25 668 1.2.1 M_cp: add -rbibr, wbibr; GetRAddr: drop odd check |
// 2015-04-03 661 1.2 expect logic: drop estatdef, use LastExpect.. |
// 2015-03-28 660 1.1.4 M_cp: add -estat(err|nak|tout) |
// 2015-03-21 659 1.1.3 rename M_amap->M_imap; add M_rmap; add GetRAddr() |
// add -rreg,...,-init and -[rw]ma |
// 2014-12-29 623 1.1.2 add M_amap; M_cp: add -print and -dump |
// 2014-12-20 616 1.1.1 M_cp: add -edone for BlockDone checking |
// 2014-11-30 607 1.1 new rlink v4 iface |
33,7 → 27,7
|
/*! |
\file |
\version $Id: RtclRw11Cpu.cpp 675 2015-05-08 21:05:08Z mueller $ |
\version $Id: RtclRw11Cpu.cpp 631 2015-01-09 21:36:51Z mueller $ |
\brief Implemenation of RtclRw11Cpu. |
*/ |
|
86,8 → 80,7
fSets() |
{ |
AddMeth("add", boost::bind(&RtclRw11Cpu::M_add, this, _1)); |
AddMeth("imap", boost::bind(&RtclRw11Cpu::M_imap, this, _1)); |
AddMeth("rmap", boost::bind(&RtclRw11Cpu::M_rmap, this, _1)); |
AddMeth("amap", boost::bind(&RtclRw11Cpu::M_amap, this, _1)); |
AddMeth("cp", boost::bind(&RtclRw11Cpu::M_cp, this, _1)); |
AddMeth("wtcpu", boost::bind(&RtclRw11Cpu::M_wtcpu, this, _1)); |
AddMeth("deposit", boost::bind(&RtclRw11Cpu::M_deposit, this, _1)); |
121,7 → 114,7
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
int RtclRw11Cpu::M_imap(RtclArgs& args) |
int RtclRw11Cpu::M_amap(RtclArgs& args) |
{ |
static RtclNameSet optset("-name|-testname|-testaddr|-insert|-erase|-print"); |
|
132,7 → 125,7
uint16_t addr=0; |
|
if (args.NextOpt(opt, optset)) { |
if (opt == "-name") { // imap -name addr |
if (opt == "-name") { // amap -name addr |
if (!args.GetArg("addr", addr)) return kERR; |
if (!args.AllDone()) return kERR; |
string tstname; |
143,19 → 136,19
"' not mapped"); |
} |
|
} else if (opt == "-testname") { // imap -testname name |
} else if (opt == "-testname") { // amap -testname name |
if (!args.GetArg("name", name)) return kERR; |
if (!args.AllDone()) return kERR; |
uint16_t tstaddr; |
args.SetResult(int(addrmap.Find(name, tstaddr))); |
|
} else if (opt == "-testaddr") { // imap -testaddr addr |
} else if (opt == "-testaddr") { // amap -testaddr addr |
if (!args.GetArg("addr", addr)) return kERR; |
if (!args.AllDone()) return kERR; |
string tstname; |
args.SetResult(int(addrmap.Find(addr, tstname))); |
|
} else if (opt == "-insert") { // imap -insert name addr |
} else if (opt == "-insert") { // amap -insert name addr |
uint16_t tstaddr; |
string tstname; |
int tstint; |
173,13 → 166,13
args.PeekArgString(-1) + "'"); |
Obj().IAddrMapInsert(name, addr); |
|
} else if (opt == "-erase") { // imap -erase name |
} else if (opt == "-erase") { // amap -erase name |
if (!args.GetArg("name", name)) return kERR; |
if (!args.AllDone()) return kERR; |
if (!Obj().IAddrMapErase(name)) |
return args.Quit(string("-E: no mapping defined for '") + name + "'"); |
|
} else if (opt == "-print") { // imap -print |
} else if (opt == "-print") { // amap -print |
if (!args.AllDone()) return kERR; |
ostringstream sos; |
addrmap.Print(sos); |
189,7 → 182,7
} else { |
if (!args.OptValid()) return kERR; |
if (!args.GetArg("?name", name)) return kERR; |
if (args.NOptMiss()==0) { // imap name |
if (args.NOptMiss()==0) { // amap name |
uint16_t tstaddr; |
if(addrmap.Find(name, tstaddr)) { |
args.SetResult(int(tstaddr)); |
197,7 → 190,7
return args.Quit(string("-E: no mapping defined for '") + name + "'"); |
} |
|
} else { // imap |
} else { // amap |
RtclOPtr plist(Tcl_NewListObj(0, nullptr)); |
const RlinkAddrMap::amap_t amap = addrmap.Amap(); |
for (RlinkAddrMap::amap_cit_t it=amap.begin(); it!=amap.end(); it++) { |
216,123 → 209,19
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
int RtclRw11Cpu::M_rmap(RtclArgs& args) |
{ |
static RtclNameSet optset("-name|-testname|-testaddr|-insert|-erase|-print"); |
|
const RlinkAddrMap& lmap = Obj().RAddrMap(); // local map |
const RlinkAddrMap& cmap = Connect().AddrMap(); // common map |
|
string opt; |
string name; |
uint16_t addr=0; |
|
if (args.NextOpt(opt, optset)) { |
if (opt == "-name") { // rmap -name addr |
if (!args.GetArg("addr", addr)) return kERR; |
if (!args.AllDone()) return kERR; |
string tstname; |
if(lmap.Find(addr, tstname)) { |
args.SetResult(tstname); |
} else if(cmap.Find(addr, tstname)) { |
args.SetResult(tstname); |
} else { |
return args.Quit(string("-E: address '") + args.PeekArgString(-1) + |
"' not mapped"); |
} |
|
} else if (opt == "-testname") { // rmap -testname name |
if (!args.GetArg("name", name)) return kERR; |
if (!args.AllDone()) return kERR; |
uint16_t tstaddr; |
args.SetResult(int(lmap.Find(name, tstaddr))); |
|
} else if (opt == "-testaddr") { // rmap -testaddr addr |
if (!args.GetArg("addr", addr)) return kERR; |
if (!args.AllDone()) return kERR; |
string tstname; |
args.SetResult(int(lmap.Find(addr, tstname))); |
|
} else if (opt == "-insert") { // rmap -insert name addr |
uint16_t tstaddr; |
string tstname; |
int tstint; |
if (!args.GetArg("name", name)) return kERR; |
// enforce that the name is not a valid representation of an int |
if (Tcl_GetIntFromObj(nullptr, args[args.NDone()-1], &tstint) == kOK) |
return args.Quit(string("-E: name should not look like an int but '")+ |
name + "' does"); |
if (!args.GetArg("addr", addr)) return kERR; |
if (!args.AllDone()) return kERR; |
if (lmap.Find(name, tstaddr)) |
return args.Quit(string("-E: mapping already defined for '")+name+"'"); |
if (lmap.Find(addr, tstname)) |
return args.Quit(string("-E: mapping already defined for address '") + |
args.PeekArgString(-1) + "'"); |
Obj().RAddrMapInsert(name, addr); |
|
} else if (opt == "-erase") { // rmap -erase name |
if (!args.GetArg("name", name)) return kERR; |
if (!args.AllDone()) return kERR; |
if (!Obj().RAddrMapErase(name)) |
return args.Quit(string("-E: no mapping defined for '") + name + "'"); |
|
} else if (opt == "-print") { // rmap -print |
if (!args.AllDone()) return kERR; |
ostringstream sos; |
lmap.Print(sos); |
args.AppendResultLines(sos); |
} |
|
} else { |
if (!args.OptValid()) return kERR; |
if (!args.GetArg("?name", name)) return kERR; |
if (args.NOptMiss()==0) { // rmap name |
uint16_t tstaddr; |
if(lmap.Find(name, tstaddr)) { |
args.SetResult(int(tstaddr)); |
} else if(cmap.Find(name, tstaddr)) { |
args.SetResult(int(tstaddr)); |
} else { |
return args.Quit(string("-E: no mapping defined for '") + name + "'"); |
} |
|
} else { // rmap |
RtclOPtr plist(Tcl_NewListObj(0, nullptr)); |
const RlinkAddrMap::amap_t amap = lmap.Amap(); |
for (RlinkAddrMap::amap_cit_t it=amap.begin(); it!=amap.end(); it++) { |
Tcl_Obj* tpair[2]; |
tpair[0] = Tcl_NewIntObj(it->first); |
tpair[1] = Tcl_NewStringObj((it->second).c_str(),(it->second).length()); |
Tcl_ListObjAppendElement(nullptr, plist, Tcl_NewListObj(2, tpair)); |
} |
args.SetResult(plist); |
} |
} |
|
return kOK; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
int RtclRw11Cpu::M_cp(RtclArgs& args) |
{ |
static RtclNameSet optset("-rreg|-rblk|-wreg|-wblk|-labo|-attn|-init|" |
"-rr|-rr0|-rr1|-rr2|-rr3|-rr4|-rr5|-rr6|-rr7|" |
static RtclNameSet optset("-rr|-rr0|-rr1|-rr2|-rr3|-rr4|-rr5|-rr6|-rr7|" |
"-wr|-wr0|-wr1|-wr2|-wr3|-wr4|-wr5|-wr6|-wr7|" |
"-rsp|-rpc|-wsp|-wpc|" |
"-rps|-wps|" |
"-ral|-rah|-wal|-wah|-wa|" |
"-rm|-rmi|-rma|-wm|-wmi|-wma|-brm|-bwm|" |
"-start|-stop|-step|-creset|-breset|" |
"-suspend|-resume|" |
"-stapc|" |
"-rmembe|-wmembe|-ribr|-rbibr|-wibr|-wbibr|" |
"-rm|-rmi|-wm|-wmi|-brm|-bwm|" |
"-stapc|-start|-stop|-continue|-step|-reset|" |
"-rmembe|-wmembe|-ribr|-wibr|" |
"-rconf|-rstat|" |
"-edata|-edone|-estat|" |
"-estaterr|-estatnak|-estattout|" |
"-print|-dump"); |
"-edata|-edone|-estat|-estatdef|" |
"-print|-dump|"); |
|
Tcl_Interp* interp = args.Interp(); |
|
345,6 → 234,9
string varprint; |
string vardump; |
|
uint8_t estatdef_val = 0x00; |
uint8_t estatdef_msk = 0xff; |
|
bool setcpugo = false; |
|
while (args.NextOpt(opt, optset)) { |
358,107 → 250,58
|
int regnum = 0; |
if (opt.substr(0,3) == "-rr" || opt.substr(0,3) == "-wr" ) { |
if (opt.length() == 3) { // -rr n or -wr n option |
if (opt.length() == 3) { |
if (!args.GetArg("regnum", regnum, 0, 7)) return kERR; |
} else if (opt.length() == 4 && opt[3] >= '0' && opt[3] <= '7') { |
} else { |
regnum = opt[3] - '0'; |
opt = opt.substr(0,3); |
regnum &= 0x7; // to be sure... |
} |
opt = opt.substr(0,3); |
} |
|
if (opt == "-rreg") { // -rreg addr ?varData ?varStat --- |
uint16_t addr; |
if (!GetRAddr(args, addr)) return kERR; |
if (opt == "-rr") { // -rr* ?varData ?varStat -------- |
if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddRreg(addr); |
clist.AddRreg(base + Rw11Cpu::kCp_addr_r0 + regnum); |
|
} else if (opt == "-rblk") { // -rblk addr size ?varData ?varStat |
uint16_t addr; |
int32_t bsize; |
if (!GetRAddr(args, addr)) return kERR; |
if (!args.GetArg("bsize", bsize, 1, Connect().BlockSizeMax())) return kERR; |
if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddRblk(addr, (size_t) bsize); |
|
} else if (opt == "-wreg") { // -wreg addr data ?varStat ------- |
uint16_t addr; |
uint16_t data; |
if (!GetRAddr(args, addr)) return kERR; |
if (!args.GetArg("data", data)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddWreg(addr, data); |
|
} else if (opt == "-wblk") { // -wblk addr block ?varStat ------ |
uint16_t addr; |
vector<uint16_t> block; |
if (!GetRAddr(args, addr)) return kERR; |
if (!args.GetArg("data", block, 1, Connect().BlockSizeMax())) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddWblk(addr, block); |
|
} else if (opt == "-labo") { // -labo varData ?varStat --------- |
if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddLabo(); |
|
} else if (opt == "-attn") { // -attn varData ?varStat --------- |
if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddAttn(); |
|
} else if (opt == "-init") { // -init addr data ?varStat ------- |
uint16_t addr; |
uint16_t data; |
if (!GetRAddr(args, addr)) return kERR; |
if (!args.GetArg("data", data)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddInit(addr, data); |
|
} else if (opt == "-rr") { // -rr* ?varData ?varStat -------- |
if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddRreg(base + Rw11Cpu::kCPR0 + regnum); |
|
} else if (opt == "-wr") { // -wr* data ?varStat ------------ |
uint16_t data; |
if (!args.GetArg("data", data)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddWreg(base + Rw11Cpu::kCPR0 + regnum, data); |
clist.AddWreg(base + Rw11Cpu::kCp_addr_r0 + regnum, data); |
|
} else if (opt == "-rps") { // -rps ?varData ?varStat -------- |
if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddRreg(base + Rw11Cpu::kCPPSW); |
clist.AddRreg(base + Rw11Cpu::kCp_addr_psw); |
|
} else if (opt == "-wps") { // -wps data ?varStat ------------ |
uint16_t data; |
if (!args.GetArg("data", data)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddWreg(base + Rw11Cpu::kCPPSW, data); |
clist.AddWreg(base + Rw11Cpu::kCp_addr_psw, data); |
|
} else if (opt == "-ral") { // -ral ?varData ?varStat -------- |
if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddRreg(base + Rw11Cpu::kCPAL); |
clist.AddRreg(base + Rw11Cpu::kCp_addr_al); |
|
} else if (opt == "-rah") { // -rah ?varData ?varStat -------- |
if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddRreg(base + Rw11Cpu::kCPAH); |
clist.AddRreg(base + Rw11Cpu::kCp_addr_ah); |
|
} else if (opt == "-wal") { // -wal data ?varStat ------------ |
uint16_t ibaddr; |
if (!GetIAddr(args, ibaddr)) return kERR; |
uint16_t data; |
if (!args.GetArg("al", data)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddWreg(base + Rw11Cpu::kCPAL, ibaddr); |
clist.AddWreg(base + Rw11Cpu::kCp_addr_al, data); |
|
} else if (opt == "-wah") { // -wah data ?varStat ------------ |
uint16_t data; |
if (!args.GetArg("ah", data)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddWreg(base + Rw11Cpu::kCPAH, data); |
clist.AddWreg(base + Rw11Cpu::kCp_addr_ah, data); |
|
} else if (opt == "-wa") { // -wa addr ?varStat [-p22 -ubm]-- |
uint32_t addr; |
471,106 → 314,78
while (args.NextSubOpt(subopt, suboptset)>=0) { // loop for sub-options |
if (!args.OptValid()) return kERR; |
if (subopt == "-p22") { // -p22 |
ah |= Rw11Cpu::kCPAH_M_22BIT; |
ah |= Rw11Cpu::kCp_ah_m_22bit; |
} else if (subopt == "-ubm") { // -ubm |
ah |= Rw11Cpu::kCPAH_M_UBMAP; |
ah |= Rw11Cpu::kCp_ah_m_ubmap; |
} |
} |
clist.AddWreg(base + Rw11Cpu::kCPAL, al); |
if (ah!=0) clist.AddWreg(base + Rw11Cpu::kCPAH, ah); |
clist.AddWreg(base + Rw11Cpu::kCp_addr_al, al); |
if (ah!=0) clist.AddWreg(base + Rw11Cpu::kCp_addr_ah, ah); |
|
} else if (opt == "-rm" || // -rm(i) ?varData ?varStat ------ |
opt == "-rmi") { |
uint16_t addr = opt=="-rm" ? Rw11Cpu::kCPMEM : |
Rw11Cpu::kCPMEMI; |
uint16_t addr = opt=="-rm" ? Rw11Cpu::kCp_addr_mem : |
Rw11Cpu::kCp_addr_memi; |
if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddRreg(base + addr); |
|
} else if (opt == "-rma") { // -rma addr ?varData ?varStat --- |
uint16_t ibaddr; |
if (!GetIAddr(args, ibaddr)) return kERR; |
// bind expects to memi access, which is second command |
if (!GetVarName(args, "??varData", lsize+1, vardata)) return kERR; |
if (!GetVarName(args, "??varStat", lsize+1, varstat)) return kERR; |
clist.AddWreg(base + Rw11Cpu::kCPAL, ibaddr); |
clist.AddRreg(base + Rw11Cpu::kCPMEMI); |
|
} else if (opt == "-wm" || // -wm(i) data ?varStat - |
opt == "-wmi") { |
uint16_t addr = opt=="-wm" ? Rw11Cpu::kCPMEM : |
Rw11Cpu::kCPMEMI; |
uint16_t addr = opt=="-wm" ? Rw11Cpu::kCp_addr_mem : |
Rw11Cpu::kCp_addr_memi; |
uint16_t data; |
if (!args.GetArg("data", data)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddWreg(base + addr, data); |
|
} else if (opt == "-wma") { // -wma addr data ?varStat ------- |
uint16_t ibaddr; |
uint16_t data; |
if (!GetIAddr(args, ibaddr)) return kERR; |
if (!args.GetArg("data", data)) return kERR; |
// bind expects to memi access, which is second command |
if (!GetVarName(args, "??varStat", lsize+1, varstat)) return kERR; |
clist.AddWreg(base + Rw11Cpu::kCPAL, ibaddr); |
clist.AddWreg(base + Rw11Cpu::kCPMEMI, data); |
|
} else if (opt == "-brm") { // -brm size ?varData ?varStat --- |
int32_t bsize; |
if (!args.GetArg("bsize", bsize, 1, 256)) return kERR; |
if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddRblk(base + Rw11Cpu::kCPMEMI, (size_t) bsize); |
clist.AddRblk(base + Rw11Cpu::kCp_addr_memi, (size_t) bsize); |
|
} else if (opt == "-bwm") { // -bwm block ?varStat ----------- |
vector<uint16_t> block; |
if (!args.GetArg("data", block, 1, 256)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddWblk(base + Rw11Cpu::kCPMEMI, block); |
clist.AddWblk(base + Rw11Cpu::kCp_addr_memi, block); |
|
} else if (opt == "-stapc") { // -stapc addr ?varStat ---------- |
uint16_t data; |
if (!args.GetArg("data", data)) return kERR; |
if (!GetVarName(args, "??varStat", lsize+1, varstat)) return kERR; |
clist.AddWreg(base + Rw11Cpu::kCp_addr_pc, data); |
clist.AddWreg(base + Rw11Cpu::kCp_addr_cntl, Rw11Cpu::kCp_func_start); |
setcpugo = true; |
|
} else if (opt == "-start") { // -start ?varStat --------------- |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_START); |
clist.AddWreg(base + Rw11Cpu::kCp_addr_cntl, Rw11Cpu::kCp_func_start); |
setcpugo = true; |
|
} else if (opt == "-stop") { // -stop ?varStat ---------------- |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_STOP); |
clist.AddWreg(base + Rw11Cpu::kCp_addr_cntl, Rw11Cpu::kCp_func_stop); |
|
} else if (opt == "-step") { // -step ?varStat ---------------- |
} else if (opt == "-continue") { // -continue ?varStat ------------ |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_STEP); |
clist.AddWreg(base + Rw11Cpu::kCp_addr_cntl, Rw11Cpu::kCp_func_cont); |
setcpugo = true; |
|
} else if (opt == "-creset") { // -creset ?varStat -------------- |
} else if (opt == "-step") { // -step ?varStat ---------------- |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_CRESET); |
clist.AddWreg(base + Rw11Cpu::kCp_addr_cntl, Rw11Cpu::kCp_func_step); |
|
} else if (opt == "-breset") { // -breset ?varStat -------------- |
} else if (opt == "-reset") { // -reset ?varStat --------------- |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_BRESET); |
clist.AddWreg(base + Rw11Cpu::kCp_addr_cntl, Rw11Cpu::kCp_func_reset); |
|
} else if (opt == "-suspend") { // -suspend ?varStat ------------- |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_SUSPEND); |
|
} else if (opt == "-resume") { // -resume ?varStat -------------- |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_RESUME); |
|
} else if (opt == "-stapc") { // -stapc addr ?varStat ---------- |
uint16_t data; |
if (!args.GetArg("data", data)) return kERR; |
if (!GetVarName(args, "??varStat", lsize+1, varstat)) return kERR; |
clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_STOP); |
clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_CRESET); |
clist.AddWreg(base + Rw11Cpu::kCPPC, data); |
clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_START); |
setcpugo = true; |
|
} else if (opt == "-rmembe") { // -rmembe ?varData ?varStat ------ |
if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddRreg(base + Rw11Cpu::kCPMEMBE); |
clist.AddRreg(base + Rw11Cpu::kCp_addr_membe); |
|
} else if (opt == "-wmembe") { // -wmembe be ?varStat [-stick] - |
uint16_t be; |
588,7 → 403,7
} |
Obj().AddMembe(clist, be, stick); |
|
} else if (opt == "-ribr") { // -ribr iba ?varData ?varStat ---- |
} else if (opt == "-ribr") { // -ribr off ?varData ?varStat ---- |
uint16_t ibaddr; |
if (!GetIAddr(args, ibaddr)) return kERR; |
if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; |
595,17 → 410,8
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
Obj().AddRibr(clist, ibaddr); |
|
} else if (opt == "-rbibr") { // -rbibr iba size ?varData ?varStat |
} else if (opt == "-wibr") { // -wibr off data ?varStat -------- |
uint16_t ibaddr; |
int32_t bsize; |
if (!GetIAddr(args, ibaddr)) return kERR; |
if (!args.GetArg("bsize", bsize, 1, Connect().BlockSizeMax())) return kERR; |
if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
Obj().AddRbibr(clist, ibaddr, (size_t) bsize); |
|
} else if (opt == "-wibr") { // -wibr iba data ?varStat -------- |
uint16_t ibaddr; |
uint16_t data; |
if (!GetIAddr(args, ibaddr)) return kERR; |
if (!args.GetArg("data", data)) return kERR; |
612,26 → 418,23
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
Obj().AddWibr(clist, ibaddr, data); |
|
} else if (opt == "-wbibr") { // -wbibr iba block data ?varStat - |
uint16_t ibaddr; |
vector<uint16_t> block; |
if (!GetIAddr(args, ibaddr)) return kERR; |
if (!args.GetArg("data", block, 1, Connect().BlockSizeMax())) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
Obj().AddWbibr(clist, ibaddr, block); |
|
} else if (opt == "-rconf") { // -rconf ?varData ?varStat ------ |
if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddRreg(base + Rw11Cpu::kCPCONF); |
clist.AddRreg(base + Rw11Cpu::kCp_addr_conf); |
|
} else if (opt == "-rstat") { // -rstat ?varData ?varStat ------ |
if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; |
if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; |
clist.AddRreg(base + Rw11Cpu::kCPSTAT); |
clist.AddRreg(base + Rw11Cpu::kCp_addr_stat); |
|
} else if (opt == "-edata") { // -edata data ?mask -------------- |
if (!ClistNonEmpty(args, clist)) return kERR; |
if (lsize == 0) |
return args.Quit("-E: -edata not allowed on empty command list"); |
if (clist[lsize-1].Expect()==0) { |
clist[lsize-1].SetExpect(new RlinkCommandExpect(estatdef_val, |
estatdef_msk)); |
} |
if (clist[lsize-1].Command() == RlinkCommand::kCmdRblk) { |
vector<uint16_t> data; |
vector<uint16_t> mask; |
638,54 → 441,54
size_t bsize = clist[lsize-1].BlockSize(); |
if (!args.GetArg("data", data, 0, bsize)) return kERR; |
if (!args.GetArg("??mask", mask, 0, bsize)) return kERR; |
clist.SetLastExpectBlock(data, mask); |
clist[lsize-1].Expect()->SetBlock(data, mask); |
} else { |
uint16_t data=0; |
uint16_t mask=0xffff; |
uint16_t mask=0; |
if (!args.GetArg("data", data)) return kERR; |
if (!args.GetArg("??mask", mask)) return kERR; |
clist.SetLastExpectData(data, mask); |
clist[lsize-1].Expect()->SetData(data, mask); |
} |
|
} else if (opt == "-edone") { // -edone done -------------------- |
if (!ClistNonEmpty(args, clist)) return kERR; |
if (lsize == 0) |
return args.Quit("-E: -edone not allowed on empty command list"); |
uint16_t done=0; |
if (!args.GetArg("done", done)) return kERR; |
if (clist[lsize-1].Expect()==0) { |
clist[lsize-1].SetExpect(new RlinkCommandExpect(estatdef_val, |
estatdef_msk)); |
} |
uint8_t cmd = clist[lsize-1].Command(); |
if (cmd == RlinkCommand::kCmdRblk || |
cmd == RlinkCommand::kCmdWblk) { |
clist.SetLastExpectDone(done); |
clist[lsize-1].Expect()->SetDone(done); |
} else { |
return args.Quit("-E: -edone allowed only after -rblk,-wblk"); |
} |
|
} else if (opt == "-estat") { // -estat stat ?mask -------------- |
if (!ClistNonEmpty(args, clist)) return kERR; |
} else if (opt == "-estat") { // -estat ?stat ?mask ------------- |
if (lsize == 0) |
return args.Quit("-E: -estat not allowed on empty command list"); |
uint8_t stat=0; |
uint8_t mask=0xff; |
if (!args.GetArg("stat", stat)) return kERR; |
uint8_t mask=0; |
if (!args.GetArg("??stat", stat)) return kERR; |
if (!args.GetArg("??mask", mask)) return kERR; |
clist.SetLastExpectStatus(stat, mask); |
if (args.NOptMiss() == 2) mask = 0xff; |
if (clist[lsize-1].Expect()==0) { |
clist[lsize-1].SetExpect(new RlinkCommandExpect()); |
} |
clist[lsize-1].Expect()->SetStatus(stat, mask); |
|
} else if (opt == "-estaterr" || // -estaterr ---------------------- |
opt == "-estatnak" || // -estatnak ---------------------- |
opt == "-estattout" || // -estattout --------------------- |
opt == "-estatmerr") { // -estatmerr --------------------- |
if (!ClistNonEmpty(args, clist)) return kERR; |
uint8_t val = 0; |
uint8_t msk = RlinkCommand::kStat_M_RbTout | |
RlinkCommand::kStat_M_RbNak | |
RlinkCommand::kStat_M_RbErr; |
if (opt == "-estaterr") val = RlinkCommand::kStat_M_RbErr; |
if (opt == "-estatnak") val = RlinkCommand::kStat_M_RbNak; |
if (opt == "-estattout") val = RlinkCommand::kStat_M_RbTout; |
if (opt == "-estatmerr") { |
val = Rw11Cpu::kStat_M_CmdMErr; |
msk |= Rw11Cpu::kStat_M_CmdMErr | |
Rw11Cpu::kStat_M_CmdErr; |
} |
clist.SetLastExpectStatus(val, msk); |
|
} else if (opt == "-estatdef") { // -estatdef ?stat ?mask ----------- |
uint8_t stat=0; |
uint8_t mask=0; |
if (!args.GetArg("??stat", stat)) return kERR; |
if (!args.GetArg("??mask", mask)) return kERR; |
if (args.NOptMiss() == 2) mask = 0xff; |
estatdef_val = stat; |
estatdef_msk = mask; |
|
} else if (opt == "-print") { // -print ?varRes ----------------- |
varprint = "-"; |
if (!args.GetArg("??varRes", varprint)) return kERR; |
694,8 → 497,18
if (!args.GetArg("??varRes", vardump)) return kERR; |
} |
|
} // while (args.NextOpt(opt, optset)) |
if (estatdef_msk != 0xff && // estatdef defined |
lsize != clist.Size()) { // and cmd added to clist |
for (size_t i=lsize; i<clist.Size(); i++) { // loop over new cmds |
if (clist[i].Expect()==0) { // if no stat |
clist[i].SetExpect(new RlinkCommandExpect(estatdef_val, |
estatdef_msk)); |
} |
} |
} |
|
} |
|
int nact = 0; |
if (varprint == "-") nact += 1; |
if (vardump == "-") nact += 1; |
744,7 → 557,7
|
if (!varprint.empty()) { |
ostringstream sos; |
clist.Print(sos, &Connect().AddrMap(), |
clist.Print(sos, Connect().Context(), &Connect().AddrMap(), |
Connect().LogBaseAddr(), Connect().LogBaseData(), |
Connect().LogBaseStat()); |
RtclOPtr pobj(Rtcl::NewLinesObj(sos)); |
807,7 → 620,7
if (reset) { // reset requested |
uint16_t base = Obj().Base(); |
RlinkCommandList clist; |
clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_STOP); |
clist.AddWreg(base + Rw11Cpu::kCp_addr_cntl, Rw11Cpu::kCp_func_stop); |
RerrMsg emsg; |
if (!Connect().Exec(clist, emsg)) return args.Quit(emsg); |
} |
1215,9 → 1028,9
while (args.NextOpt(opt, optset)) { |
if (opt == "-pcps" || opt == "-r0ps") { |
RlinkCommandList clist; |
size_t i_pc = clist.AddRreg(base + Rw11Cpu::kCPPC); |
size_t i_psw = clist.AddRreg(base + Rw11Cpu::kCPPSW); |
size_t i_stat = clist.AddRreg(base + Rw11Cpu::kCPSTAT); |
size_t i_pc = clist.AddRreg(base + Rw11Cpu::kCp_addr_pc); |
size_t i_psw = clist.AddRreg(base + Rw11Cpu::kCp_addr_psw); |
size_t i_stat = clist.AddRreg(base + Rw11Cpu::kCp_addr_stat); |
if (!Server().Exec(clist, emsg)) return args.Quit(emsg); |
uint16_t psw = clist[i_psw].Data(); |
uint16_t stat = clist[i_stat].Data(); |
1234,7 → 1047,7
|
if (r0ps) { |
clist.Clear(); |
for (size_t i=0; i<7; i++) clist.AddRreg(base + Rw11Cpu::kCPR0+i); |
for (size_t i=0; i<7; i++) clist.AddRreg(base + Rw11Cpu::kCp_addr_r0+i); |
if (!Server().Exec(clist, emsg)) return args.Quit(emsg); |
for (size_t i=0; i<7; i++) regs[i] = clist[i].Data(); |
} |
1261,7 → 1074,7
|
} else if (opt == "-r0r5") { |
RlinkCommandList clist; |
for (size_t i=0; i<6; i++) clist.AddRreg(base + Rw11Cpu::kCPR0+i); |
for (size_t i=0; i<6; i++) clist.AddRreg(base + Rw11Cpu::kCp_addr_r0+i); |
if (!Server().Exec(clist, emsg)) return args.Quit(emsg); |
sos << "R0-R5:"; |
for (size_t i=0; i<6; i++) sos << " " << RosPrintBvi(clist[i].Data(),8); |
1282,18 → 1095,18
{ |
boost::lock_guard<RlinkConnect> lock(Connect()); |
RlinkCommandList clist; |
clist.AddWreg(base + Rw11Cpu::kCPAL, 0177572); |
clist.AddRblk(base + Rw11Cpu::kCPMEMI, mmr, 3); |
clist.AddWreg(base + Rw11Cpu::kCPAL, 0172516); |
clist.AddRblk(base + Rw11Cpu::kCPMEMI, mmr+3, 1); |
clist.AddWreg(base + Rw11Cpu::kCp_addr_al, 0177572); |
clist.AddRblk(base + Rw11Cpu::kCp_addr_memi, mmr, 3); |
clist.AddWreg(base + Rw11Cpu::kCp_addr_al, 0172516); |
clist.AddRblk(base + Rw11Cpu::kCp_addr_memi, mmr+3, 1); |
if (!Server().Exec(clist, emsg)) return args.Quit(emsg); |
clist.Clear(); |
clist.AddWreg(base + Rw11Cpu::kCPAL, 0172300); |
clist.AddRblk(base + Rw11Cpu::kCPMEMI, asr[0], 32); |
clist.AddWreg(base + Rw11Cpu::kCPAL, 0172200); |
clist.AddRblk(base + Rw11Cpu::kCPMEMI, asr[1], 32); |
clist.AddWreg(base + Rw11Cpu::kCPAL, 0177600); |
clist.AddRblk(base + Rw11Cpu::kCPMEMI, asr[2], 32); |
clist.AddWreg(base + Rw11Cpu::kCp_addr_al, 0172300); |
clist.AddRblk(base + Rw11Cpu::kCp_addr_memi, asr[0], 32); |
clist.AddWreg(base + Rw11Cpu::kCp_addr_al, 0172200); |
clist.AddRblk(base + Rw11Cpu::kCp_addr_memi, asr[1], 32); |
clist.AddWreg(base + Rw11Cpu::kCp_addr_al, 0177600); |
clist.AddRblk(base + Rw11Cpu::kCp_addr_memi, asr[2], 32); |
if (!Server().Exec(clist, emsg)) return args.Quit(emsg); |
} |
uint16_t mmr1_0_reg = (mmr[1] ) & 07; |
1351,8 → 1164,8
} else if (opt == "-ubmap") { |
uint16_t ubmap[64]; |
RlinkCommandList clist; |
clist.AddWreg(base + Rw11Cpu::kCPAL, 0170200); |
clist.AddRblk(base + Rw11Cpu::kCPMEMI, ubmap, 64); |
clist.AddWreg(base + Rw11Cpu::kCp_addr_al, 0170200); |
clist.AddRblk(base + Rw11Cpu::kCp_addr_memi, ubmap, 64); |
if (!Server().Exec(clist, emsg)) return args.Quit(emsg); |
sos << "unibus map:" << endl; |
for (size_t i = 0; i<=7; i++) { |
1474,43 → 1287,6
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
bool RtclRw11Cpu::GetRAddr(RtclArgs& args, uint16_t& rbaddr) |
{ |
Tcl_Obj* pobj=0; |
if (!args.GetArg("rbaddr", pobj)) return kERR; |
|
int tstint; |
// if a number is given.. |
if (Tcl_GetIntFromObj(nullptr, pobj, &tstint) == kOK) { |
if (tstint >= 0 && tstint <= 0xffff) { |
rbaddr = (uint16_t)tstint; |
} else { |
args.AppendResult("-E: value '", Tcl_GetString(pobj), |
"' for 'addr' out of range 0...0xffff", |
nullptr); |
return false; |
} |
// if a name is given |
} else { |
string name(Tcl_GetString(pobj)); |
uint16_t tstaddr; |
if (Obj().RAddrMap().Find(name, tstaddr)) { |
rbaddr = tstaddr; |
} else if (Connect().AddrMap().Find(name, tstaddr)) { |
rbaddr = tstaddr; |
} else { |
args.AppendResult("-E: no address mapping known for '", |
Tcl_GetString(pobj), "'", nullptr); |
return false; |
} |
} |
|
return true; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
bool RtclRw11Cpu::GetVarName(RtclArgs& args, const char* argname, |
size_t nind, |
std::vector<std::string>& varname) |
1531,17 → 1307,4
return true; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
bool RtclRw11Cpu::ClistNonEmpty(RtclArgs& args, const RlinkCommandList& clist) |
{ |
if (clist.Size() == 0) { |
args.AppendResult("-E: -edata, -edone, or -estat " |
"not allowed on empty command list", nullptr); |
return false; |
} |
return true; |
} |
|
} // end namespace Retro |
/tools/src/librwxxtpp/Makefile
1,4 → 1,4
# $Id: Makefile 664 2015-04-06 12:02:17Z mueller $ |
# $Id: Makefile 602 2014-11-08 21:42:47Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
37,7 → 37,6
OBJ_all += RtclRw11CntlPC11.o RtclRw11UnitPC11.o |
OBJ_all += RtclRw11CntlRK11.o RtclRw11UnitRK11.o |
OBJ_all += RtclRw11CntlRL11.o RtclRw11UnitRL11.o |
OBJ_all += RtclRw11CntlRHRP.o RtclRw11UnitRHRP.o |
# |
DEP_all = $(OBJ_all:.o=.dep) |
# |
/tools/src/librwxxtpp/RtclRw11.cpp
1,6 → 1,6
// $Id: RtclRw11.cpp 660 2015-03-29 22:10:16Z mueller $ |
// $Id: RtclRw11.cpp 632 2015-01-11 12:30:03Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-03-28 660 1.0.1 add M_get |
// 2014-12-25 621 1.1 adopt to 4k word ibus window |
// 2013-03-06 495 1.0 Initial version |
// 2013-01-27 478 0.1 First Draft |
21,7 → 20,7
|
/*! |
\file |
\version $Id: RtclRw11.cpp 660 2015-03-29 22:10:16Z mueller $ |
\version $Id: RtclRw11.cpp 632 2015-01-11 12:30:03Z mueller $ |
\brief Implemenation of class RtclRw11. |
*/ |
|
56,17 → 55,11
|
RtclRw11::RtclRw11(Tcl_Interp* interp, const char* name) |
: RtclProxyOwned<Rw11>("Rw11", interp, name, new Rw11()), |
fspServ(), |
fGets() |
fspServ() |
{ |
AddMeth("get", boost::bind(&RtclRw11::M_get, this, _1)); |
AddMeth("start", boost::bind(&RtclRw11::M_start, this, _1)); |
AddMeth("dump", boost::bind(&RtclRw11::M_dump, this, _1)); |
AddMeth("$default", boost::bind(&RtclRw11::M_default, this, _1)); |
|
Rw11* pobj = &Obj(); |
fGets.Add<bool> ("started",boost::bind(&Rw11::IsStarted, pobj)); |
|
} |
|
//------------------------------------------+----------------------------------- |
122,20 → 115,10
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
int RtclRw11::M_get(RtclArgs& args) |
{ |
// synchronize with server thread |
boost::lock_guard<RlinkConnect> lock(Obj().Connect()); |
return fGets.M_get(args); |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
int RtclRw11::M_start(RtclArgs& args) |
{ |
if (!args.AllDone()) return kERR; |
if (Obj().IsStarted()) return args.Quit("-E: already started"); |
if (Obj().IsStarted()) return args.Quit("already started"); |
Obj().Start(); |
return kOK; |
} |
/tools/src/librwxxtpp/RtclRw11CntlFactory.cpp
1,4 → 1,4
// $Id: RtclRw11CntlFactory.cpp 664 2015-04-06 12:02:17Z mueller $ |
// $Id: RtclRw11CntlFactory.cpp 630 2015-01-04 22:43:32Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-03-21 659 1.1.3 add RPRM (later renamed to RHRP) |
// 2015-01-04 630 1.1.2 RL11 back in |
// 2014-06-27 565 1.1.1 temporarily hide RL11 |
// 2014-06-08 561 1.1.0 add RL11 |
24,7 → 23,7
|
/*! |
\file |
\version $Id: RtclRw11CntlFactory.cpp 664 2015-04-06 12:02:17Z mueller $ |
\version $Id: RtclRw11CntlFactory.cpp 630 2015-01-04 22:43:32Z mueller $ |
\brief Implemenation of global function RtclRw11CntlFactory. |
*/ |
|
35,7 → 34,6
#include "RtclRw11CntlDL11.hpp" |
#include "RtclRw11CntlRK11.hpp" |
#include "RtclRw11CntlRL11.hpp" |
#include "RtclRw11CntlRHRP.hpp" |
#include "RtclRw11CntlLP11.hpp" |
#include "RtclRw11CntlPC11.hpp" |
|
68,11 → 66,6
if(pobj->FactoryCmdConfig(args, cpu) != TCL_OK) return TCL_ERROR; |
pobj.release(); |
|
} else if (type == "rhrp") { // rhrp -------------------------- |
unique_ptr<RtclRw11CntlRHRP> pobj(new RtclRw11CntlRHRP()); |
if(pobj->FactoryCmdConfig(args, cpu) != TCL_OK) return TCL_ERROR; |
pobj.release(); |
|
} else if (type == "lp11") { // lp11 -------------------------- |
unique_ptr<RtclRw11CntlLP11> pobj(new RtclRw11CntlLP11()); |
if(pobj->FactoryCmdConfig(args, cpu) != TCL_OK) return TCL_ERROR; |
/tools/src/librwxxtpp/RtclRw11Cpu.hpp
1,6 → 1,6
// $Id: RtclRw11Cpu.hpp 661 2015-04-03 18:28:41Z mueller $ |
// $Id: RtclRw11Cpu.hpp 621 2014-12-26 21:20:05Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,8 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-03 661 1.0.4 add ClistNonEmpty() |
// 2015-03-21 659 1.0.3 rename M_amap->M_imap; add M_rmap; add GetRAddr() |
// 2014-12-25 621 1.0.2 add M_amap |
// 2013-04-26 511 1.0.1 add M_show |
// 2013-04-02 502 1.0 Initial version |
24,7 → 22,7
|
/*! |
\file |
\version $Id: RtclRw11Cpu.hpp 661 2015-04-03 18:28:41Z mueller $ |
\version $Id: RtclRw11Cpu.hpp 621 2014-12-26 21:20:05Z mueller $ |
\brief Declaration of class RtclRw11Cpu. |
*/ |
|
54,8 → 52,7
|
protected: |
int M_add(RtclArgs& args); |
int M_imap(RtclArgs& args); |
int M_rmap(RtclArgs& args); |
int M_amap(RtclArgs& args); |
int M_cp(RtclArgs& args); |
int M_wtcpu(RtclArgs& args); |
int M_deposit(RtclArgs& args); |
77,11 → 74,8
RlinkConnect& Connect(); |
|
bool GetIAddr(RtclArgs& args, uint16_t& ibaddr); |
bool GetRAddr(RtclArgs& args, uint16_t& rbaddr); |
bool GetVarName(RtclArgs& args, const char* argname, |
size_t nind, std::vector<std::string>& varname); |
bool ClistNonEmpty(RtclArgs& args, |
const RlinkCommandList& clist); |
|
protected: |
RtclGetList fGets; |
/tools/src/librwxxtpp/RtclRw11Cntl.hpp
1,4 → 1,4
// $Id: RtclRw11Cntl.hpp 660 2015-03-29 22:10:16Z mueller $ |
// $Id: RtclRw11Cntl.hpp 627 2015-01-04 11:36:37Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-03-27 660 1.1.1 add M_start |
// 2015-01-03 627 1.1 M_stats now virtual |
// 2013-03-06 495 1.0 Initial version |
// 2013-02-08 484 0.1 First draft |
22,7 → 21,7
|
/*! |
\file |
\version $Id: RtclRw11Cntl.hpp 660 2015-03-29 22:10:16Z mueller $ |
\version $Id: RtclRw11Cntl.hpp 627 2015-01-04 11:36:37Z mueller $ |
\brief Declaration of class RtclRw11Cntl. |
*/ |
|
54,7 → 53,6
int M_get(RtclArgs& args); |
int M_set(RtclArgs& args); |
int M_probe(RtclArgs& args); |
int M_start(RtclArgs& args); |
virtual int M_stats(RtclArgs& args); |
int M_dump(RtclArgs& args); |
int M_default(RtclArgs& args); |
/tools/src/librwxxtpp/RtclRw11UnitDisk.cpp
1,6 → 1,6
// $Id: RtclRw11UnitDisk.cpp 680 2015-05-14 13:29:46Z mueller $ |
// $Id: RtclRw11UnitDisk.cpp 509 2013-04-21 20:46:20Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,8 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-05-14 680 1.1.1 fGets: remove enabled, now in RtclRw11UnitBase |
// 2015-03-21 659 1.1 fGets: add enabled |
// 2013-04-19 507 1.0 Initial version |
// 2013-02-22 490 0.1 First draft |
// --------------------------------------------------------------------------- |
21,7 → 19,7
|
/*! |
\file |
\version $Id: RtclRw11UnitDisk.cpp 680 2015-05-14 13:29:46Z mueller $ |
\version $Id: RtclRw11UnitDisk.cpp 509 2013-04-21 20:46:20Z mueller $ |
\brief Implemenation of RtclRw11UnitDisk. |
*/ |
|
/tools/src/librwxxtpp/RtclRw11Cntl.cpp
1,6 → 1,6
// $Id: RtclRw11Cntl.cpp 660 2015-03-29 22:10:16Z mueller $ |
// $Id: RtclRw11Cntl.cpp 504 2013-04-13 15:37:24Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-03-27 660 1.0.1 add M_start |
// 2013-03-06 495 1.0 Initial version |
// 2013-02-08 484 0.1 First draft |
// --------------------------------------------------------------------------- |
20,7 → 19,7
|
/*! |
\file |
\version $Id: RtclRw11Cntl.cpp 660 2015-03-29 22:10:16Z mueller $ |
\version $Id: RtclRw11Cntl.cpp 504 2013-04-13 15:37:24Z mueller $ |
\brief Implemenation of RtclRw11Cntl. |
*/ |
|
52,7 → 51,6
AddMeth("get", boost::bind(&RtclRw11Cntl::M_get, this, _1)); |
AddMeth("set", boost::bind(&RtclRw11Cntl::M_set, this, _1)); |
AddMeth("probe", boost::bind(&RtclRw11Cntl::M_probe, this, _1)); |
AddMeth("start", boost::bind(&RtclRw11Cntl::M_start, this, _1)); |
AddMeth("stats", boost::bind(&RtclRw11Cntl::M_stats, this, _1)); |
AddMeth("dump", boost::bind(&RtclRw11Cntl::M_dump, this, _1)); |
AddMeth("$default", boost::bind(&RtclRw11Cntl::M_default, this, _1)); |
97,17 → 95,6
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
int RtclRw11Cntl::M_start(RtclArgs& args) |
{ |
if (!args.AllDone()) return kERR; |
Obj().Probe(); |
Obj().Start(); |
return kOK; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
int RtclRw11Cntl::M_stats(RtclArgs& args) |
{ |
RtclStats::Context cntx; |
/tools/src/librwxxtpp/RtclRw11UnitBase.ipp
1,6 → 1,6
// $Id: RtclRw11UnitBase.ipp 680 2015-05-14 13:29:46Z mueller $ |
// $Id: RtclRw11UnitBase.ipp 504 2013-04-13 15:37:24Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-05-14 680 1.1 fGets: add enabled (moved from RtclRw11UnitDisk) |
// 2013-03-06 495 1.0 Initial version |
// 2013-02-16 488 0.1 First draft |
// --------------------------------------------------------------------------- |
20,7 → 19,7
|
/*! |
\file |
\version $Id: RtclRw11UnitBase.ipp 680 2015-05-14 13:29:46Z mueller $ |
\version $Id: RtclRw11UnitBase.ipp 504 2013-04-13 15:37:24Z mueller $ |
\brief Implemenation (all inline) of RtclRw11UnitBase. |
*/ |
|
45,9 → 44,8
{ |
AddMeth("stats", boost::bind(&RtclRw11UnitBase<TO>::M_stats, this, _1)); |
TO* pobj = fspObj.get(); |
fGets.Add<size_t> ("index", boost::bind(&TO::Index, pobj)); |
fGets.Add<std::string> ("name", boost::bind(&TO::Name, pobj)); |
fGets.Add<bool> ("enabled", boost::bind(&TO::Enabled, pobj)); |
fGets.Add<size_t> ("index", boost::bind(&TO::Index, pobj)); |
fGets.Add<std::string> ("name", boost::bind(&TO::Name, pobj)); |
} |
|
//------------------------------------------+----------------------------------- |
/tools/src/librwxxtpp/RtclRw11.hpp
1,6 → 1,6
// $Id: RtclRw11.hpp 660 2015-03-29 22:10:16Z mueller $ |
// $Id: RtclRw11.hpp 504 2013-04-13 15:37:24Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-03-28 660 1.0.1 add M_get |
// 2013-03-06 495 1.0 Initial version |
// 2013-01-27 478 0.1 First draft |
// --------------------------------------------------------------------------- |
20,7 → 19,7
|
/*! |
\file |
\version $Id: RtclRw11.hpp 660 2015-03-29 22:10:16Z mueller $ |
\version $Id: RtclRw11.hpp 504 2013-04-13 15:37:24Z mueller $ |
\brief Declaration of class RtclRw11. |
*/ |
|
33,7 → 32,6
#include "boost/shared_ptr.hpp" |
|
#include "librtcltools/RtclProxyOwned.hpp" |
#include "librtcltools/RtclGetList.hpp" |
|
#include "librlink/RlinkServer.hpp" |
#include "librw11/Rw11.hpp" |
48,7 → 46,6
virtual int ClassCmdConfig(RtclArgs& args); |
|
protected: |
int M_get(RtclArgs& args); |
int M_start(RtclArgs& args); |
int M_dump(RtclArgs& args); |
int M_default(RtclArgs& args); |
55,7 → 52,6
|
protected: |
boost::shared_ptr<RlinkServer> fspServ; |
RtclGetList fGets; |
}; |
|
} // end namespace Retro |
/tools/src/librlink/RlinkConnect.hpp
1,4 → 1,4
// $Id: RlinkConnect.hpp 666 2015-04-12 21:17:54Z mueller $ |
// $Id: RlinkConnect.hpp 632 2015-01-11 12:30:03Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,8 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-12 666 2.3 add LinkInit,LinkInitDone; transfer xon |
// 2015-04-02 661 2.2 expect logic: stat expect in Command, invert mask |
// 2015-01-06 631 2.1 full rlink v4 implementation |
// 2014-12-25 621 2.0.2 Reorganize packet send/revd stats |
// 2014-12-20 616 2.0.1 add BlockDone expect checks |
37,7 → 35,7
|
/*! |
\file |
\version $Id: RlinkConnect.hpp 666 2015-04-12 21:17:54Z mueller $ |
\version $Id: RlinkConnect.hpp 632 2015-01-11 12:30:03Z mueller $ |
\brief Declaration of class \c RlinkConnect. |
*/ |
|
82,9 → 80,6
bool IsOpen() const; |
RlinkPort* Port() const; |
|
bool LinkInit(RerrMsg& emsg); |
bool LinkInitDone() const; |
|
RlinkContext& Context(); |
|
void SetServer(RlinkServer* pserv); |
190,10 → 185,9
kStatNInit, //!< init commands |
kStatNRblkWord, //!< words rcvd with rblk |
kStatNWblkWord, //!< words send with wblk |
kStatNExpData, //!< expect for data defined |
kStatNExpDone, //!< expect for done defined |
kStatNExpStat, //!< expect for stat explicit |
kStatNNoExpStat, //!< no expect for stat |
kStatNExpData, //!< Expect() for data defined |
kStatNExpDone, //!< Expect() for done defined |
kStatNExpStat, //!< Expect() for stat defined |
kStatNChkData, //!< expect data failed |
kStatNChkDone, //!< expect done failed |
kStatNChkStat, //!< expect stat failed |
207,12 → 201,12
|
protected: |
bool ExecPart(RlinkCommandList& clist, size_t ibeg, size_t iend, |
RerrMsg& emsg); |
RerrMsg& emsg, RlinkContext& cntx); |
|
void EncodeRequest(RlinkCommandList& clist, size_t ibeg, |
size_t iend); |
int DecodeResponse(RlinkCommandList& clist, size_t ibeg, |
size_t iend); |
int DecodeResponse(RlinkCommandList& clist, size_t ibeg, |
size_t iend, RlinkContext& cntx); |
bool DecodeAttnNotify(uint16_t& apat); |
bool ReadResponse(double timeout, RerrMsg& emsg); |
void AcceptResponse(); |
221,8 → 215,6
|
protected: |
boost::scoped_ptr<RlinkPort> fpPort; //!< ptr to port |
bool fLinkInitDeferred; //!< noinit attr seen on Open |
bool fLinkInitDone; //!< LinkInit done |
RlinkServer* fpServ; //!< ptr to server (optional) |
uint8_t fSeqNumber[8]; //!< command sequence number |
RlinkPacketBufSnd fSndPkt; //!< send packet buffer |
/tools/src/librlink/RlinkConnect.ipp
1,4 → 1,4
// $Id: RlinkConnect.ipp 666 2015-04-12 21:17:54Z mueller $ |
// $Id: RlinkConnect.ipp 632 2015-01-11 12:30:03Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-12 666 2.2 add LinkInit,LinkInitDone; transfer xon |
// 2015-01-06 631 2.1 full rlink v4 implementation |
// 2013-03-05 495 1.2.1 add Exec() without emsg (will send emsg to LogFile) |
// 2013-02-23 492 1.2 use scoped_ptr for Port; Close allways allowed |
26,7 → 25,7
|
/*! |
\file |
\version $Id: RlinkConnect.ipp 666 2015-04-12 21:17:54Z mueller $ |
\version $Id: RlinkConnect.ipp 632 2015-01-11 12:30:03Z mueller $ |
\brief Implemenation (inline) of RlinkConnect. |
*/ |
|
52,14 → 51,6
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline bool RlinkConnect::LinkInitDone() const |
{ |
return fLinkInitDone; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline RlinkContext& RlinkConnect::Context() |
{ |
return fContext; |
/tools/src/librlink/RlinkPort.cpp
1,6 → 1,6
// $Id: RlinkPort.cpp 666 2015-04-12 21:17:54Z mueller $ |
// $Id: RlinkPort.cpp 632 2015-01-11 12:30:03Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-11 666 1.3 add fXon, XonEnable() |
// 2014-12-10 611 1.2.4 add time stamps for Read/Write for logs |
// 2014-11-29 607 1.2.3 BUGFIX: fix time handling on RawRead() |
// 2014-11-23 606 1.2.2 use Rtools::TimeOfDayAsDouble() |
31,7 → 30,7
|
/*! |
\file |
\version $Id: RlinkPort.cpp 666 2015-04-12 21:17:54Z mueller $ |
\version $Id: RlinkPort.cpp 632 2015-01-11 12:30:03Z mueller $ |
\brief Implemenation of RlinkPort. |
*/ |
|
73,7 → 72,6
RlinkPort::RlinkPort() |
: fIsOpen(false), |
fUrl(), |
fXon(false), |
fFdRead(-1), |
fFdWrite(-1), |
fspLog(), |
297,7 → 295,6
|
os << bl << " fIsOpen: " << (int)fIsOpen << endl; |
fUrl.Dump(os, ind+2, "fUrl: "); |
os << bl << " fXon: " << fXon << endl; |
os << bl << " fFdRead: " << fFdRead << endl; |
os << bl << " fFdWrite: " << fFdWrite << endl; |
os << bl << " fspLog: " << fspLog.get() << endl; |
/tools/src/librlink/RlinkPort.hpp
1,6 → 1,6
// $Id: RlinkPort.hpp 666 2015-04-12 21:17:54Z mueller $ |
// $Id: RlinkPort.hpp 632 2015-01-11 12:30:03Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-11 666 1.3 add fXon, XonEnable() |
// 2014-12-10 611 1.2.2 add time stamps for Read/Write for logs |
// 2013-05-01 513 1.2.1 fTraceLevel now uint32_t |
// 2013-02-23 492 1.2 use RparseUrl |
28,7 → 27,7
|
/*! |
\file |
\version $Id: RlinkPort.hpp 666 2015-04-12 21:17:54Z mueller $ |
\version $Id: RlinkPort.hpp 632 2015-01-11 12:30:03Z mueller $ |
\brief Declaration of class RlinkPort. |
*/ |
|
67,7 → 66,6
bool IsOpen() const; |
|
const RparseUrl& Url() const; |
bool XonEnable() const; |
|
int FdRead() const; |
int FdWrite() const; |
103,7 → 101,6
protected: |
bool fIsOpen; //!< is open flag |
RparseUrl fUrl; //!< parsed url |
bool fXon; //!< xon attribute set |
int fFdRead; //!< fd for read |
int fFdWrite; //!< fd for write |
boost::shared_ptr<RlogFile> fspLog; //!< log file ptr |
/tools/src/librlink/RlinkServer.cpp
1,4 → 1,4
// $Id: RlinkServer.cpp 662 2015-04-05 08:02:54Z mueller $ |
// $Id: RlinkServer.cpp 632 2015-01-11 12:30:03Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-04 662 1.2 BUGFIX: fix race in Stop(), use UnStop() |
// 2015-01-10 632 2.2 Exec() without emsg now void, will throw |
// 2014-12-30 625 2.1 adopt to Rlink V4 attn logic |
// 2014-12-21 617 2.0.1 use kStat_M_RbTout for rbus timeout |
26,7 → 25,7
|
/*! |
\file |
\version $Id: RlinkServer.cpp 662 2015-04-05 08:02:54Z mueller $ |
\version $Id: RlinkServer.cpp 632 2015-01-11 12:30:03Z mueller $ |
\brief Implemenation of RlinkServer. |
*/ |
|
68,9 → 67,10
fTraceLevel(0), |
fStats() |
{ |
fContext.SetStatus(0, RlinkCommand::kStat_M_RbTout | |
RlinkCommand::kStat_M_RbNak | |
RlinkCommand::kStat_M_RbErr); |
fContext.SetStatus(0, |
~(RlinkCommand::kStat_M_RbTout | |
RlinkCommand::kStat_M_RbNak | |
RlinkCommand::kStat_M_RbErr)); |
|
fELoop.AddPollHandler(boost::bind(&RlinkServer::WakeupHandler, this, _1), |
fWakeupEvent, POLLIN); |
414,7 → 414,6
rlinkfd, POLLIN); |
|
// and start server thread |
fELoop.UnStop(); |
fServerThread = boost::thread(boost::bind(&RlinkServerEventLoop::EventLoop, |
&fELoop)); |
|
/tools/src/librlink/RlinkPortTerm.cpp
1,4 → 1,4
// $Id: RlinkPortTerm.cpp 666 2015-04-12 21:17:54Z mueller $ |
// $Id: RlinkPortTerm.cpp 641 2015-02-01 22:12:15Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-12 666 1.3 drop xon/xoff excaping; add noinit attribute |
// 2015-02-01 641 1.2 support custom baud rates (5M,6M,10M,12M) |
// 2013-02-23 492 1.1 use RparseUrl |
// 2011-12-18 440 1.0.4 add kStatNPort stats; Open(): autoadd /dev/tty, |
27,7 → 26,7
|
/*! |
\file |
\version $Id: RlinkPortTerm.cpp 666 2015-04-12 21:17:54Z mueller $ |
\version $Id: RlinkPortTerm.cpp 641 2015-02-01 22:12:15Z mueller $ |
\brief Implemenation of RlinkPortTerm. |
*/ |
|
59,6 → 58,7
// constants definitions |
const uint8_t RlinkPortTerm::kc_xon; |
const uint8_t RlinkPortTerm::kc_xoff; |
const uint8_t RlinkPortTerm::kc_xesc; |
|
//------------------------------------------+----------------------------------- |
//! Default constructor |
65,7 → 65,10
|
RlinkPortTerm::RlinkPortTerm() |
: RlinkPort() |
{} |
{ |
fStats.Define(kStatNPortTxXesc, "NPortTxXesc", "Tx XESC escapes"); |
fStats.Define(kStatNPortRxXesc, "NPortRxXesc", "Rx XESC escapes"); |
} |
|
//------------------------------------------+----------------------------------- |
//! Destructor |
82,7 → 85,7
{ |
Close(); |
|
if (!fUrl.Set(url, "|baud=|break|cts|xon|noinit|", emsg)) return false; |
if (!fUrl.Set(url, "|baud=|break|cts|xon|", emsg)) return false; |
|
// if path doesn't start with a '/' prepend a '/dev/tty' |
if (fUrl.Path().substr(0,1) != "/") { |
173,7 → 176,8
|
bool use_cts = fUrl.FindOpt("cts"); |
bool use_xon = fUrl.FindOpt("xon"); |
fXon = use_xon; |
fUseXon = use_xon; |
fPendXesc = false; |
|
fTiosNew = fTiosOld; |
|
314,6 → 318,78
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
int RlinkPortTerm::Read(uint8_t* buf, size_t size, double timeout, |
RerrMsg& emsg) |
{ |
int irc; |
if (fUseXon) { |
uint8_t* po = buf; |
if (fRxBuf.size() < size) fRxBuf.resize(size); |
|
// repeat read until at least one byte returned (or an error occurs) |
// this avoids that the Read() returns with 0 in case only one byte is |
// seen and this is a kc_xesc. At most two iterations possible because |
// in 2nd iteration fPendXesc must be set and thus po pushed. |
while (po == buf) { |
irc = RlinkPort::Read(fRxBuf.data(), size, timeout, emsg); |
if (irc <= 0) break; |
uint8_t* pi = fRxBuf.data(); |
for (int i=0; i<irc; i++) { |
uint8_t c = *pi++; |
if (fPendXesc) { |
*po++ = ~c; |
fPendXesc = false; |
} else if (c == kc_xesc) { |
fStats.Inc(kStatNPortRxXesc); |
fPendXesc = true; |
} else { |
*po++ = c; |
} |
} |
irc = po - buf; // set irc to # of unescaped bytes |
} |
|
} else { |
irc = RlinkPort::Read(buf, size, timeout, emsg); |
} |
|
return irc; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
int RlinkPortTerm::Write(const uint8_t* buf, size_t size, RerrMsg& emsg) |
{ |
int irc = 0; |
|
if (fUseXon) { |
fTxBuf.clear(); |
const uint8_t* pc = buf; |
|
for (size_t i=0; i<size; i++) { |
uint8_t c = *pc++; |
if (c==kc_xon || c==kc_xoff || c==kc_xesc) { |
fStats.Inc(kStatNPortTxXesc); |
fTxBuf.push_back(kc_xesc); |
fTxBuf.push_back(~c); |
} else { |
fTxBuf.push_back(c); |
} |
} |
int irce = RlinkPort::Write(fTxBuf.data(), fTxBuf.size(), emsg); |
if (irce == (int)fTxBuf.size()) irc = size; |
} else { |
irc = RlinkPort::Write(buf, size, emsg); |
} |
|
/* tcdrain(fFdWrite);*/ |
return irc; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
void RlinkPortTerm::Dump(std::ostream& os, int ind, const char* text) const |
{ |
RosFill bl(ind); |
/tools/src/librlink/RlinkCommand.cpp
1,4 → 1,4
// $Id: RlinkCommand.cpp 662 2015-04-05 08:02:54Z mueller $ |
// $Id: RlinkCommand.cpp 643 2015-02-07 17:41:53Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-02 661 1.3 expect logic: add stat check, Print() without cntx |
// 2015-02-07 642 1.2.3 Print()+Dump(): adopt for large nblk; |
// 2014-12-21 617 1.2.2 use kStat_M_RbTout for rbus timeout |
// 2014-12-20 616 1.2.1 Print(): display BlockDone; add kFlagChkDone |
27,7 → 26,7
|
/*! |
\file |
\version $Id: RlinkCommand.cpp 662 2015-04-05 08:02:54Z mueller $ |
\version $Id: RlinkCommand.cpp 643 2015-02-07 17:41:53Z mueller $ |
\brief Implemenation of class RlinkCommand. |
*/ |
|
98,9 → 97,6
fStatus(0), |
fFlags(0), |
fRcvSize(0), |
fExpectStatusSet(false), |
fExpectStatusVal(0), |
fExpectStatusMsk(0x0), |
fpExpect(nullptr) |
{} |
|
118,9 → 114,6
fStatus(rhs.fStatus), |
fFlags(rhs.fFlags), |
fRcvSize(rhs.fRcvSize), |
fExpectStatusSet(rhs.fExpectStatusSet), |
fExpectStatusVal(rhs.fExpectStatusVal), |
fExpectStatusMsk(rhs.fExpectStatusMsk), |
fpExpect(rhs.fpExpect ? new RlinkCommandExpect(*rhs.fpExpect) : nullptr) |
{} |
|
263,7 → 256,7
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
void RlinkCommand::Print(std::ostream& os, |
void RlinkCommand::Print(std::ostream& os, const RlinkContext& cntx, |
const RlinkAddrMap* pamap, size_t abase, |
size_t dbase, size_t sbase) const |
{ |
270,17 → 263,17
uint8_t ccode = Command(); |
|
// separator + command mnemonic, code and flags |
// separator: ++ first in packet |
// -- non-first in packet |
// -! +! labo with abort |
// -. +. labo canceled command |
|
char sep0 = TestFlagAny(kFlagPktBeg) ? '+' : '-'; |
char sep1 = sep0; |
if (ccode==kCmdLabo && fData) sep1 = '!'; // indicate aborting labo |
if (TestFlagAny(kFlagLabo)) sep1 = '.'; // indicate aborted command |
|
os << sep0 << sep1 << " " << CommandName(ccode) |
// separator: ++ first in packet |
// -- non-first in packet |
// ?? FIXME_code: separator for labo canceled commands |
const char* sep = "??"; |
if (TestFlagAny(kFlagPktBeg)) { |
sep = "++"; |
} else { |
sep = "--"; |
} |
|
os << sep << " " << CommandName(ccode) |
<< " (" << RosPrintBvi(Request(), 8) |
<< "," << RosPrintBvi(fFlags, 16, 20) |
<< ")"; |
297,12 → 290,6
} |
} |
|
// don't write more that command and address for canceled commands |
if (TestFlagAny(kFlagLabo)) { |
os << " CANCELED" << endl; |
return; |
} |
|
// data field (scalar) |
if (ccode== kCmdRreg || ccode==kCmdWreg || |
ccode== kCmdLabo || ccode==kCmdAttn || |
314,7 → 301,7
if (TestFlagAny(kFlagChkData)) { |
os << "#"; |
os << " D=" << RosPrintBvi(fpExpect->DataValue(), dbase); |
if (fpExpect->DataMask() != 0xffff) { |
if (fpExpect->DataMask() != 0x0000) { |
os << "," << RosPrintBvi(fpExpect->DataMask(), dbase); |
} |
} else if (fpExpect->DataIsChecked()) { |
348,14 → 335,16
|
// status field |
os << " s=" << RosPrintBvi(fStatus, sbase); |
uint8_t scval = fpExpect ? fpExpect->StatusValue() : cntx.StatusValue(); |
uint8_t scmsk = fpExpect ? fpExpect->StatusMask() : cntx.StatusMask(); |
if (TestFlagAny(kFlagChkStat)) { |
os << "#"; |
os << " S=" << RosPrintBvi(fExpectStatusVal, sbase); |
if (fExpectStatusMsk != 0xff) { |
os << "," << RosPrintBvi(fExpectStatusMsk, sbase); |
os << " S=" << RosPrintBvi(scval, sbase); |
if (scmsk != 0x00) { |
os << "," << RosPrintBvi(scmsk, sbase); |
} |
} else { |
os << (StatusIsChecked() ? (ExpectStatusSet() ? "|" : "!") : " " ); |
os << ( scmsk != 0xff ? "!" : " " ); |
} |
|
if (TestFlagAny(kFlagDone)) { |
407,7 → 396,7
os << "\n FAIL d[" << RosPrintf(i,"d",4) << "]: " |
<< RosPrintBvi(pdat[i], dbase) << "#" |
<< " D=" << RosPrintBvi(evalvec[i], dbase); |
if (i < emskvec.size() && emskvec[i]!=0xffff) { |
if (i < emskvec.size() && emskvec[i]!=0x0000) { |
os << "," << RosPrintBvi(emskvec[i], dbase); |
} |
} |
461,10 → 450,8
} |
os << endl; |
} |
os << bl << " fExpectStatusVal:" << RosPrintBvi(fExpectStatusVal,0) << endl; |
os << bl << " fExpectStatusMsk:" << RosPrintBvi(fExpectStatusMsk,0) << endl; |
if (fpExpect) fpExpect->Dump(os, ind+2, "fpExpect: "); |
|
|
return; |
} |
|
508,21 → 495,18
RlinkCommand& RlinkCommand::operator=(const RlinkCommand& rhs) |
{ |
if (&rhs == this) return *this; |
fRequest = rhs.fRequest; |
fAddress = rhs.fAddress; |
fData = rhs.fData; |
fBlock = rhs.fBlock; |
fpBlockExt = rhs.fpBlockExt; |
fBlockExtSize = rhs.fBlockExtSize; |
fBlockDone = rhs.fBlockDone; |
fStatus = rhs.fStatus; |
fFlags = rhs.fFlags; |
fRcvSize = rhs.fRcvSize; |
fExpectStatusSet = rhs.fExpectStatusSet; |
fExpectStatusVal = rhs.fExpectStatusVal; |
fExpectStatusMsk = rhs.fExpectStatusMsk; |
fRequest = rhs.fRequest; |
fAddress = rhs.fAddress; |
fData = rhs.fData; |
fBlock = rhs.fBlock; |
fpBlockExt = rhs.fpBlockExt; |
fBlockExtSize = rhs.fBlockExtSize; |
fBlockDone = rhs.fBlockDone; |
fStatus = rhs.fStatus; |
fFlags = rhs.fFlags; |
fRcvSize = rhs.fRcvSize; |
delete fpExpect; |
fpExpect = rhs.fpExpect ? new RlinkCommandExpect(*rhs.fpExpect) : 0; |
fpExpect = rhs.fpExpect ? new RlinkCommandExpect(*rhs.fpExpect) : 0; |
return *this; |
} |
|
/tools/src/librlink/RlinkPortCuff.cpp
1,6 → 1,6
// $Id: RlinkPortCuff.cpp 666 2015-04-12 21:17:54Z mueller $ |
// $Id: RlinkPortCuff.cpp 632 2015-01-11 12:30:03Z mueller $ |
// |
// Copyright 2012-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2012-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-12 666 1.1.3 add noinit attribute |
// 2014-08-22 584 1.1.2 use nullptr |
// 2013-05-17 521 1.1.1 use Rtools::String2Long |
// 2013-02-23 492 1.1 use RparseUrl |
25,7 → 24,7
|
/*! |
\file |
\version $Id: RlinkPortCuff.cpp 666 2015-04-12 21:17:54Z mueller $ |
\version $Id: RlinkPortCuff.cpp 632 2015-01-11 12:30:03Z mueller $ |
\brief Implemenation of RlinkPortCuff. |
*/ |
|
98,7 → 97,7
|
if (IsOpen()) Close(); |
|
if (!fUrl.Set(url, "|trace|noinit|", emsg)) return false; |
if (!fUrl.Set(url, "|trace|", emsg)) return false; |
|
// initialize USB context |
irc = libusb_init(&fpUsbContext); |
/tools/src/librlink/RlinkConnect.cpp
1,4 → 1,4
// $Id: RlinkConnect.cpp 679 2015-05-13 17:38:46Z mueller $ |
// $Id: RlinkConnect.cpp 632 2015-01-11 12:30:03Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,9 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-05-10 678 2.3.1 WaitAttn(): BUGFIX: return 0. (not -1.) if poll |
// 2015-04-12 666 2.3 add LinkInit,LinkInitDone; transfer xon |
// 2015-04-02 661 2.2 expect logic: stat expect in Command, invert mask |
// 2015-01-06 631 2.1 full rlink v4 implementation |
// 2014-12-10 611 2.0 re-organize for rlink v4 |
// 2014-08-26 587 1.5 start accept rlink v4 protocol (partially...) |
36,7 → 33,7
|
/*! |
\file |
\version $Id: RlinkConnect.cpp 679 2015-05-13 17:38:46Z mueller $ |
\version $Id: RlinkConnect.cpp 632 2015-01-11 12:30:03Z mueller $ |
\brief Implemenation of RlinkConnect. |
*/ |
|
94,8 → 91,6
|
RlinkConnect::RlinkConnect() |
: fpPort(), |
fLinkInitDeferred(false), |
fLinkInitDone(false), |
fpServ(nullptr), |
fSndPkt(), |
fRcvPkt(), |
102,12 → 97,12
fContext(), |
fAddrMap(), |
fStats(), |
fLogBaseAddr(16), // addr default radix: hex |
fLogBaseData(16), // data default radix: hex |
fLogBaseStat(16), // stat default radix: hex |
fPrintLevel(2), // default print: error and checks |
fDumpLevel(0), // default dump: no |
fTraceLevel(0), // default trace: no |
fLogBaseAddr(16), |
fLogBaseData(16), |
fLogBaseStat(16), |
fPrintLevel(0), |
fDumpLevel(0), |
fTraceLevel(0), |
fspLog(new RlogFile(&cout)), |
fConnectMutex(), |
fAttnNotiPatt(0), |
116,11 → 111,7
fRbufSize(2048) |
{ |
for (size_t i=0; i<8; i++) fSeqNumber[i] = 0; |
|
fContext.SetStatus(0, RlinkCommand::kStat_M_RbTout | |
RlinkCommand::kStat_M_RbNak | |
RlinkCommand::kStat_M_RbErr); |
|
|
// Statistic setup |
fStats.Define(kStatNExec, "NExec", "Exec() calls"); |
fStats.Define(kStatNExecPart, "NExecPart", "ExecPart() calls"); |
134,12 → 125,11
fStats.Define(kStatNInit, "NInit", "init commands"); |
fStats.Define(kStatNRblkWord, "NRblkWord", "words rcvd with rblk"); |
fStats.Define(kStatNWblkWord, "NWblkWord", "words send with wblk"); |
fStats.Define(kStatNExpData, "NExpData", "expect for data defined"); |
fStats.Define(kStatNExpDone, "NExpDone", "expect for done defined"); |
fStats.Define(kStatNExpStat, "NExpStat", "expect for stat explicit"); |
fStats.Define(kStatNNoExpStat,"NNoExpStat","no expect for stat"); |
fStats.Define(kStatNExpData, "NExpData", "Expect() for data defined"); |
fStats.Define(kStatNExpDone, "NExpDone", "Expect() for done defined"); |
fStats.Define(kStatNExpStat, "NExpStat", "Expect() for stat defined"); |
fStats.Define(kStatNChkData, "NChkData", "expect data failed"); |
fStats.Define(kStatNChkDone, "NChkDone", "expect done failed"); |
fStats.Define(kStatNChkDone, "NChkData", "expect done failed"); |
fStats.Define(kStatNChkStat, "NChkStat", "expect stat failed"); |
fStats.Define(kStatNSndOob, "NSndOob", "SndOob() calls"); |
fStats.Define(kStatNErrMiss, "NErrMiss", "decode: missing data"); |
166,22 → 156,26
fpPort.reset(RlinkPortFactory::Open(name, emsg)); |
if (!fpPort) return false; |
|
fSndPkt.SetXonEscape(fpPort->XonEnable()); // transfer XON enable |
|
fpPort->SetLogFile(fspLog); |
fpPort->SetTraceLevel(fTraceLevel); |
|
fLinkInitDone = false; |
fRbufSize = 2048; // use minimum (2kB) as startup |
fSysId = 0xffffffff; |
|
if (! fpPort->Url().FindOpt("noinit")) { |
if (!LinkInit(emsg)) { |
Close(); |
return false; |
} |
RlinkCommandList clist; |
clist.AddRreg(kRbaddr_RLSTAT); |
clist.AddRreg(kRbaddr_RLID1); |
clist.AddRreg(kRbaddr_RLID0); |
|
if (!Exec(clist, emsg)) { |
Close(); |
return false; |
} |
|
uint16_t rlstat = clist[0].Data(); |
uint16_t rlid1 = clist[1].Data(); |
uint16_t rlid0 = clist[2].Data(); |
|
fRbufSize = size_t(1) << (10 + (rlstat & kRLSTAT_M_RBSize)); |
fSysId = uint32_t(rlid1)<<16 | uint32_t(rlid0); |
|
return true; |
} |
|
205,32 → 199,6
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
bool RlinkConnect::LinkInit(RerrMsg& emsg) |
{ |
if (fLinkInitDone) return true; |
|
RlinkCommandList clist; |
clist.AddRreg(kRbaddr_RLSTAT); |
clist.AddRreg(kRbaddr_RLID1); |
clist.AddRreg(kRbaddr_RLID0); |
|
if (!Exec(clist, emsg)) return false; |
|
fLinkInitDone = true; |
|
uint16_t rlstat = clist[0].Data(); |
uint16_t rlid1 = clist[1].Data(); |
uint16_t rlid0 = clist[2].Data(); |
|
fRbufSize = size_t(1) << (10 + (rlstat & kRLSTAT_M_RBSize)); |
fSysId = uint32_t(rlid1)<<16 | uint32_t(rlid0); |
|
return true; |
} |
|
//------------------------------------------+----------------------------------- |
//! Indicates whether server is active. |
/*! |
\returns \c true if server active. |
308,8 → 276,6
|
clist.ClearLaboIndex(); |
|
uint8_t defstatval = cntx.StatusValue(); |
uint8_t defstatmsk = cntx.StatusMask(); |
size_t size = clist.Size(); |
|
for (size_t i=0; i<size; i++) { |
332,11 → 298,6
RlinkCommand::kFlagPktEnd | |
RlinkCommand::kFlagErrNak | |
RlinkCommand::kFlagErrDec); |
|
// setup default status check unless explicit check defined |
if (!cmd.ExpectStatusSet()) { |
cmd.SetExpectStatusDefault(defstatval, defstatmsk); |
} |
} |
|
// old split volative logic. Currently dormant |
351,13 → 312,13
break; |
} |
} |
bool rc = ExecPart(clist, ibeg, iend, emsg); |
bool rc = ExecPart(clist, ibeg, iend, emsg, cntx); |
if (!rc) return rc; |
ibeg = iend+1; |
} |
#endif |
|
bool rc = ExecPart(clist, 0, size-1, emsg); |
bool rc = ExecPart(clist, 0, size-1, emsg, cntx); |
if (!rc) return rc; |
|
bool checkseen = false; |
381,7 → 342,8
if (errorseen) loglevel = 1; |
if (loglevel <= fPrintLevel) { |
RlogMsg lmsg(*fspLog); |
clist.Print(lmsg(), &AddrMap(), fLogBaseAddr, fLogBaseData, fLogBaseStat); |
clist.Print(lmsg(), cntx, &AddrMap(), fLogBaseAddr, fLogBaseData, |
fLogBaseStat); |
} |
if (loglevel <= fDumpLevel) { |
RlogMsg lmsg(*fspLog); |
455,7 → 417,7
} |
|
// quit if poll only (zero timeout) |
if (timeout == 0.) return 0.; |
if (timeout == 0.) return -1.; |
|
// wait for new notifier |
double tnow = Rtools::TimeOfDayAsDouble(); |
629,8 → 591,6
os << bl << " fpPort: " << fpPort.get() << endl; |
} |
|
os << bl << " fLinkInitDone: " << fLinkInitDone << endl; |
|
os << bl << " fpServ: " << fpServ << endl; |
os << bl << " fSeqNumber: "; |
for (size_t i=0; i<8; i++) os << RosPrintBvi(fSeqNumber[i],16) << " "; |
687,7 → 647,7
//! FIXME_docs |
|
bool RlinkConnect::ExecPart(RlinkCommandList& clist, size_t ibeg, size_t iend, |
RerrMsg& emsg) |
RerrMsg& emsg, RlinkContext& cntx) |
{ |
if (ibeg>iend || iend>=clist.Size()) |
throw Rexception("RlinkConnect::ExecPart()", |
706,7 → 666,7
bool ok = ReadResponse(15., emsg); |
if (!ok) Rexception("RlinkConnect::ExecPart()","faulty response"); |
|
int ncmd = DecodeResponse(clist, ibeg, iend); |
int ncmd = DecodeResponse(clist, ibeg, iend, cntx); |
if (ncmd != int(iend-ibeg+1)) { |
clist.Dump(cout); |
throw Rexception("RlinkConnect::ExecPart()","incomplete response"); |
804,8 → 764,8
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
int RlinkConnect::DecodeResponse(RlinkCommandList& clist, size_t ibeg, |
size_t iend) |
int RlinkConnect::DecodeResponse(RlinkCommandList& clist, size_t ibeg, |
size_t iend, RlinkContext& cntx) |
{ |
size_t ncmd = 0; |
|
912,6 → 872,7
} else { |
if (expect.DataIsChecked()) fStats.Inc(kStatNExpData); |
} |
if (expect.StatusIsChecked()) fStats.Inc(kStatNExpStat); |
|
if (ccode==RlinkCommand::kCmdRreg || |
ccode==RlinkCommand::kCmdLabo || |
933,18 → 894,19
fStats.Inc(kStatNChkDone); |
cmd.SetFlagBit(RlinkCommand::kFlagChkDone); |
} |
} |
if (!expect.StatusCheck(cmd.Status())) { |
fStats.Inc(kStatNChkStat); |
cmd.SetFlagBit(RlinkCommand::kFlagChkStat); |
} |
|
} else { // no expect, use context |
if (!cntx.StatusCheck(cmd.Status())) { |
fStats.Inc(kStatNChkStat); |
cmd.SetFlagBit(RlinkCommand::kFlagChkStat); |
} |
} // if (cmd.Expect()) |
|
// status check, now independent of Expect object |
if (cmd.ExpectStatusSet()) fStats.Inc(kStatNExpStat); |
if (!cmd.StatusIsChecked()) fStats.Inc(kStatNNoExpStat); |
if (!cmd.StatusCheck()) { |
fStats.Inc(kStatNChkStat); |
cmd.SetFlagBit(RlinkCommand::kFlagChkStat); |
} |
|
} // for (size_t i=ibeg; i<=iend; i++) |
|
// FIXME_code: check that all data is consumed !! |
/tools/src/librlink/RlinkPacketBufSnd.cpp
1,6 → 1,6
// $Id: RlinkPacketBufSnd.cpp 666 2015-04-12 21:17:54Z mueller $ |
// $Id: RlinkPacketBufSnd.cpp 621 2014-12-26 21:20:05Z mueller $ |
// |
// Copyright 2014-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-11 666 1.1 handle xon/xoff escaping, add (Set)XonEscape() |
// 2014-12-25 621 1.0.1 Reorganize packet send/revd stats |
// 2014-11-15 604 1.0 Initial version |
// 2014-11-02 600 0.1 First draft (re-organize PacketBuf for rlink v4) |
21,7 → 20,7
|
/*! |
\file |
\version $Id: RlinkPacketBufSnd.cpp 666 2015-04-12 21:17:54Z mueller $ |
\version $Id: RlinkPacketBufSnd.cpp 621 2014-12-26 21:20:05Z mueller $ |
\brief Implemenation of class RlinkPacketBuf. |
*/ |
|
48,13 → 47,11
//! Default constructor |
|
RlinkPacketBufSnd::RlinkPacketBufSnd() |
: fXonEscape(false), |
fRawBuf() |
: fRawBuf() |
{ |
// Statistic setup |
fStats.Define(kStatNTxPktByt, "NTxPktByt", "Tx packet bytes send"); |
fStats.Define(kStatNTxEsc, "NTxEsc", "Tx esc escapes"); |
fStats.Define(kStatNTxXEsc, "NTxXEsc", "Tx xon escapes"); |
fStats.Define(kStatNTxEsc, "NTxEsc", "Tx data escapes"); |
} |
|
//------------------------------------------+----------------------------------- |
91,8 → 88,7
|
bool RlinkPacketBufSnd::SndPacket(RlinkPort* port, RerrMsg& emsg) |
{ |
size_t nesc = 0; |
size_t nxesc = 0; |
size_t nesc = 0; |
|
fRawBuf.reserve(2*fPktBuf.size()+4); // max. size of raw data |
fRawBuf.clear(); |
103,32 → 99,16
uint8_t* pi = fPktBuf.data(); |
for (size_t i=0; i<ni; i++) { |
uint8_t c = *pi++; |
|
if (c == kSymEsc) { |
PutRawEsc(kEcEsc); |
nesc += 1; |
continue; |
} else { |
fRawBuf.push_back(c); |
} |
|
if (fXonEscape) { |
if (c == kSymXon) { |
PutRawEsc(kEcXon); |
nxesc += 1; |
continue; |
} |
if (c == kSymXoff) { |
PutRawEsc(kEcXoff); |
nxesc += 1; |
continue; |
} |
} |
|
fRawBuf.push_back(c); |
} |
|
PutRawEsc(kEcEop); // <EOP> |
fStats.Inc(kStatNTxEsc, double(nesc)); |
fStats.Inc(kStatNTxXEsc, double(nxesc)); |
fStats.Inc(kStatNTxEsc , double(nesc)); |
|
bool sndok = SndRaw(port, emsg); |
if (sndok) fStats.Inc(kStatNTxPktByt, double(PktSize())); |
152,8 → 132,6
fRawBuf.push_back(uint8_t((data>>4) & 0x000f)); // DATA ( 7: 4) |
fRawBuf.push_back(uint8_t((data>>8) & 0x000f)); // DATA (11: 8) |
fRawBuf.push_back(uint8_t((data>>12) & 0x000f)); // DATA (15:12) |
fRawBuf.push_back(0); // send two filler zero's to ensure that |
fRawBuf.push_back(0); // comma handlers are in ground state |
|
return SndRaw(port, emsg); |
} |
216,8 → 194,6
RosFill bl(ind); |
os << bl << (text?text:"--") << "RlinkPacketBufSnd @ " << this << endl; |
|
os << bl << " fXonEscape: " << fXonEscape << endl; |
|
size_t rawbufsize = fRawBuf.size(); |
os << bl << " fRawBuf(size): " << RosPrintf(rawbufsize,"d",4); |
size_t ncol = max(1, (80-ind-4-6)/(2+1)); |
/tools/src/librlink/RlinkPacketBufSnd.hpp
1,6 → 1,6
// $Id: RlinkPacketBufSnd.hpp 666 2015-04-12 21:17:54Z mueller $ |
// $Id: RlinkPacketBufSnd.hpp 621 2014-12-26 21:20:05Z mueller $ |
// |
// Copyright 2014-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-11 666 1.1 handle xon/xoff escaping, add (Set)XonEscape() |
// 2014-12-25 621 1.0.1 Reorganize packet send/revd stats |
// 2014-11-14 604 1.0 Initial version |
// 2014-11-02 600 0.1 First draft (re-organize PacketBuf for rlink v4) |
22,7 → 21,7
|
/*! |
\file |
\version $Id: RlinkPacketBufSnd.hpp 666 2015-04-12 21:17:54Z mueller $ |
\version $Id: RlinkPacketBufSnd.hpp 621 2014-12-26 21:20:05Z mueller $ |
\brief Declaration of class RlinkPacketBufSnd. |
*/ |
|
40,9 → 39,6
RlinkPacketBufSnd(); |
~RlinkPacketBufSnd(); |
|
void SetXonEscape(bool xon); |
bool XonEscape() const; |
|
void Init(); |
|
void PutWithCrc(uint8_t data); |
67,8 → 63,7
// statistics counter indices |
enum stats { |
kStatNTxPktByt=0, //!< Tx packet bytes send |
kStatNTxEsc, //!< Tx esc escapes |
kStatNTxXEsc //!< Tx xon escapes |
kStatNTxEsc //!< Tx data escapes |
}; |
|
protected: |
75,7 → 70,6
bool SndRaw(RlinkPort* port, RerrMsg& emsg); |
|
protected: |
bool fXonEscape; //!< escape XON/XOFF |
std::vector<uint8_t> fRawBuf; //!< raw data buffer |
}; |
|
/tools/src/librlink/RlinkCommandExpect.hpp
1,6 → 1,6
// $Id: RlinkCommandExpect.hpp 661 2015-04-03 18:28:41Z mueller $ |
// $Id: RlinkCommandExpect.hpp 616 2014-12-21 10:09:25Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-02 661 1.2 expect logic: remove stat from Expect, invert mask |
// 2014-12-20 616 1.1 add Done count methods (for rblk/wblk) |
// 2011-03-12 368 1.0 Initial version |
// 2011-01-15 355 0.1 First draft |
22,7 → 21,7
|
/*! |
\file |
\version $Id: RlinkCommandExpect.hpp 661 2015-04-03 18:28:41Z mueller $ |
\version $Id: RlinkCommandExpect.hpp 616 2014-12-21 10:09:25Z mueller $ |
\brief Declaration of class RlinkCommandExpect. |
*/ |
|
38,12 → 37,17
public: |
|
RlinkCommandExpect(); |
RlinkCommandExpect(uint16_t data, uint16_t datamsk=0xffff); |
RlinkCommandExpect(const std::vector<uint16_t>& block); |
RlinkCommandExpect(const std::vector<uint16_t>& block, |
explicit RlinkCommandExpect(uint8_t stat, uint8_t statmsk=0); |
RlinkCommandExpect(uint8_t stat, uint8_t statmsk, |
uint16_t data, uint16_t datamsk=0); |
RlinkCommandExpect(uint8_t stat, uint8_t statmsk, |
const std::vector<uint16_t>& block); |
RlinkCommandExpect(uint8_t stat, uint8_t statmsk, |
const std::vector<uint16_t>& block, |
const std::vector<uint16_t>& blockmsk); |
~RlinkCommandExpect(); |
|
void SetStatus(uint8_t stat, uint8_t statmsk=0); |
void SetData(uint16_t data, uint16_t datamsk=0); |
void SetDone(uint16_t done, bool check=true); |
void SetBlock(const std::vector<uint16_t>& block); |
50,6 → 54,8
void SetBlock(const std::vector<uint16_t>& block, |
const std::vector<uint16_t>& blockmsk); |
|
uint8_t StatusValue() const; |
uint8_t StatusMask() const; |
uint16_t DataValue() const; |
uint16_t DataMask() const; |
uint16_t DoneValue() const; |
56,11 → 62,13
const std::vector<uint16_t>& BlockValue() const; |
const std::vector<uint16_t>& BlockMask() const; |
|
bool StatusCheck(uint8_t val) const; |
bool DataCheck(uint16_t val) const; |
bool DoneCheck(uint16_t val) const; |
bool BlockCheck(size_t ind, uint16_t val) const; |
size_t BlockCheck(const uint16_t* pval, size_t size) const; |
|
bool StatusIsChecked() const; |
bool DataIsChecked() const; |
bool DoneIsChecked() const; |
bool BlockIsChecked(size_t ind) const; |
68,6 → 76,8
void Dump(std::ostream& os, int ind=0, const char* text=0) const; |
|
protected: |
uint8_t fStatusVal; //!< status value |
uint8_t fStatusMsk; //!< status mask |
uint16_t fDataVal; //!< data value |
uint16_t fDataMsk; //!< data mask |
std::vector<uint16_t> fBlockVal; //!< block value |
/tools/src/librlink/RlinkCommandExpect.ipp
1,6 → 1,6
// $Id: RlinkCommandExpect.ipp 661 2015-04-03 18:28:41Z mueller $ |
// $Id: RlinkCommandExpect.ipp 616 2014-12-21 10:09:25Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-02 661 1.2 expect logic: remove stat from Expect, invert mask |
// 2014-12-20 616 1.1 add Done count methods (for rblk/wblk) |
// 2011-03-12 368 1.0 Initial version |
// 2011-01-15 355 0.1 First draft |
21,7 → 20,7
|
/*! |
\file |
\version $Id: RlinkCommandExpect.ipp 661 2015-04-03 18:28:41Z mueller $ |
\version $Id: RlinkCommandExpect.ipp 616 2014-12-21 10:09:25Z mueller $ |
\brief Implemenation (inline) of class RlinkCommandExpect. |
*/ |
|
31,6 → 30,16
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline void RlinkCommandExpect::SetStatus(uint8_t stat, uint8_t statmsk) |
{ |
fStatusVal = stat; |
fStatusMsk = statmsk; |
return; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline void RlinkCommandExpect::SetData(uint16_t data, uint16_t datamsk) |
{ |
fDataVal = data; |
44,7 → 53,7
inline void RlinkCommandExpect::SetDone(uint16_t done, bool check) |
{ |
fDataVal = done; |
fDataMsk = check ? 0xffff : 0x0; |
fDataMsk = check ? 0 : 0xffff; |
return; |
} |
|
72,6 → 81,22
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline uint8_t RlinkCommandExpect::StatusValue() const |
{ |
return fStatusVal; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline uint8_t RlinkCommandExpect::StatusMask() const |
{ |
return fStatusMsk; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline uint16_t RlinkCommandExpect::DataValue() const |
{ |
return fDataVal; |
112,9 → 137,17
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline bool RlinkCommandExpect::StatusCheck(uint8_t val) const |
{ |
return (val|fStatusMsk) == (fStatusVal|fStatusMsk); |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline bool RlinkCommandExpect::DataCheck(uint16_t val) const |
{ |
return (val & fDataMsk) == fDataVal; |
return (val|fDataMsk) == (fDataVal|fDataMsk); |
} |
|
//------------------------------------------+----------------------------------- |
128,9 → 161,17
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline bool RlinkCommandExpect::StatusIsChecked() const |
{ |
return fStatusMsk != 0xff; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline bool RlinkCommandExpect::DataIsChecked() const |
{ |
return fDataMsk != 0x0; |
return fDataMsk != 0xffff; |
} |
|
//------------------------------------------+----------------------------------- |
138,7 → 179,7
|
inline bool RlinkCommandExpect::DoneIsChecked() const |
{ |
return fDataMsk != 0x0; |
return fDataMsk == 0; |
} |
|
} // end namespace Retro |
/tools/src/librlink/RlinkCommand.hpp
1,6 → 1,6
// $Id: RlinkCommand.hpp 661 2015-04-03 18:28:41Z mueller $ |
// $Id: RlinkCommand.hpp 617 2014-12-21 14:18:53Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-02 661 1.3 expect logic: add stat check, Print() without cntx |
// 2014-12-21 617 1.2.2 use kStat_M_RbTout for rbus timeout |
// 2014-12-20 616 1.2.1 add kFlagChkDone |
// 2014-12-06 609 1.2 new rlink v4 iface |
25,7 → 24,7
|
/*! |
\file |
\version $Id: RlinkCommand.hpp 661 2015-04-03 18:28:41Z mueller $ |
\version $Id: RlinkCommand.hpp 617 2014-12-21 14:18:53Z mueller $ |
\brief Declaration of class RlinkCommand. |
*/ |
|
75,10 → 74,7
void SetFlagBit(uint32_t mask); |
void ClearFlagBit(uint32_t mask); |
void SetRcvSize(size_t rsize); |
|
void SetExpect(RlinkCommandExpect* pexp); |
void SetExpectStatus(uint8_t stat, uint8_t statmsk=0xff); |
void SetExpectStatusDefault(uint8_t stat=0, uint8_t statmsk=0x0); |
|
uint8_t Request() const; |
uint8_t Command() const; |
96,17 → 92,11
bool TestFlagAny(uint32_t mask) const; |
bool TestFlagAll(uint32_t mask) const; |
size_t RcvSize() const; |
|
RlinkCommandExpect* Expect() const; |
uint8_t ExpectStatusValue() const; |
uint8_t ExpectStatusMask() const; |
bool ExpectStatusSet() const; |
bool StatusCheck() const; |
bool StatusIsChecked() const; |
|
void Print(std::ostream& os, const RlinkAddrMap* pamap=0, |
size_t abase=16, size_t dbase=16, |
size_t sbase=16) const; |
void Print(std::ostream& os, const RlinkContext& cntx, |
const RlinkAddrMap* pamap=0, size_t abase=16, |
size_t dbase=16, size_t sbase=16) const; |
void Dump(std::ostream& os, int ind=0, const char* text=0) const; |
|
static const char* CommandName(uint8_t cmd); |
160,9 → 150,6
uint8_t fStatus; //!< rlink command status |
uint32_t fFlags; //!< state bits |
size_t fRcvSize; //!< receive size for command |
bool fExpectStatusSet; //!< stat chk set explicitely |
uint8_t fExpectStatusVal; //!< status value |
uint8_t fExpectStatusMsk; //!< status mask |
RlinkCommandExpect* fpExpect; //!< pointer to expect container |
}; |
|
/tools/src/librlink/RlinkPacketBufSnd.ipp
1,6 → 1,6
// $Id: RlinkPacketBufSnd.ipp 666 2015-04-12 21:17:54Z mueller $ |
// $Id: RlinkPacketBufSnd.ipp 606 2014-11-24 07:08:51Z mueller $ |
// |
// Copyright 2014-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-11 666 1.1 handle xon/xoff escaping, add (Set)XonEscape() |
// 2014-11-08 602 1.0 Initial version |
// 2014-11-02 600 0.1 First draft (re-organize PacketBuf for rlink v4) |
// --------------------------------------------------------------------------- |
20,7 → 19,7
|
/*! |
\file |
\version $Id: RlinkPacketBufSnd.ipp 666 2015-04-12 21:17:54Z mueller $ |
\version $Id: RlinkPacketBufSnd.ipp 606 2014-11-24 07:08:51Z mueller $ |
\brief Implemenation (inline) of class RlinkPacketBuf. |
*/ |
|
40,23 → 39,6
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline void RlinkPacketBufSnd::SetXonEscape(bool xon) |
{ |
fXonEscape = xon; |
return; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline bool RlinkPacketBufSnd::XonEscape() const |
{ |
return fXonEscape; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline void RlinkPacketBufSnd::PutWithCrc(uint16_t data) |
{ |
uint8_t datl = data & 0xff; |
/tools/src/librlink/RlinkPortFifo.cpp
1,6 → 1,6
// $Id: RlinkPortFifo.cpp 666 2015-04-12 21:17:54Z mueller $ |
// $Id: RlinkPortFifo.cpp 607 2014-11-30 20:02:48Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2011-2013 y Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-12 666 1.2 add xon,noinit attributes |
// 2013-02-23 492 1.1 use RparseUrl |
// 2011-03-27 374 1.0 Initial version |
// 2011-01-15 356 0.1 First draft |
21,7 → 20,7
|
/*! |
\file |
\version $Id: RlinkPortFifo.cpp 666 2015-04-12 21:17:54Z mueller $ |
\version $Id: RlinkPortFifo.cpp 607 2014-11-30 20:02:48Z mueller $ |
\brief Implemenation of RlinkPortFifo. |
*/ |
|
65,7 → 64,7
{ |
if (IsOpen()) Close(); |
|
if (!fUrl.Set(url, "|keep|xon|noinit|", emsg)) return false; |
if (!fUrl.Set(url, "|keep|", emsg)) return false; |
|
// Note: _rx fifo must be opened before the _tx fifo, otherwise the test |
// bench might close with EOF on read prematurely (is a race condition). |
80,8 → 79,7
return false; |
} |
|
fXon = fUrl.FindOpt("xon"); |
fIsOpen = true; |
fIsOpen = true; |
|
return true; |
} |
/tools/src/librlink/RlinkCommandList.cpp
1,6 → 1,6
// $Id: RlinkCommandList.cpp 661 2015-04-03 18:28:41Z mueller $ |
// $Id: RlinkCommandList.cpp 606 2014-11-24 07:08:51Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-02 661 1.3 expect logic: add SetLastExpect methods |
// 2014-11-23 606 1.2 new rlink v4 iface |
// 2014-08-02 576 1.1 rename LastExpect->SetLastExpect |
// 2013-05-06 495 1.0.3 add RlinkContext to Print() args |
25,7 → 24,7
|
/*! |
\file |
\version $Id: RlinkCommandList.cpp 661 2015-04-03 18:28:41Z mueller $ |
\version $Id: RlinkCommandList.cpp 606 2014-11-24 07:08:51Z mueller $ |
\brief Implemenation of class RlinkCommandList. |
*/ |
|
201,81 → 200,13
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
void RlinkCommandList::SetLastExpectStatus(uint8_t stat, uint8_t statmsk) |
{ |
if (fList.empty()) |
throw Rexception("RlinkCommandList::SetLastExpectStatus()", |
"Bad state: list empty"); |
fList.back()->SetExpectStatus(stat, statmsk); |
return; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
void RlinkCommandList::SetLastExpectData(uint16_t data, uint16_t datamsk) |
{ |
if (fList.empty()) |
throw Rexception("RlinkCommandList::SetLastExpectData()", |
"Bad state: list empty"); |
RlinkCommand& cmd = *fList.back(); |
if (!cmd.Expect()) cmd.SetExpect(new RlinkCommandExpect()); |
cmd.Expect()->SetData(data, datamsk); |
return; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
void RlinkCommandList::SetLastExpectDone(uint16_t done) |
{ |
if (fList.empty()) |
throw Rexception("RlinkCommandList::SetLastExpectDone()", |
"Bad state: list empty"); |
RlinkCommand& cmd = *fList.back(); |
if (!cmd.Expect()) cmd.SetExpect(new RlinkCommandExpect()); |
cmd.Expect()->SetDone(done); |
return; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
void RlinkCommandList::SetLastExpectBlock(const std::vector<uint16_t>& block) |
{ |
if (fList.empty()) |
throw Rexception("RlinkCommandList::SetLastExpectBlock()", |
"Bad state: list empty"); |
RlinkCommand& cmd = *fList.back(); |
if (!cmd.Expect()) cmd.SetExpect(new RlinkCommandExpect()); |
cmd.Expect()->SetBlock(block); |
return; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
void RlinkCommandList::SetLastExpectBlock(const std::vector<uint16_t>& block, |
const std::vector<uint16_t>& blockmsk) |
{ |
if (fList.empty()) |
throw Rexception("RlinkCommandList::SetLastExpectBlock()", |
"Bad state: list empty"); |
RlinkCommand& cmd = *fList.back(); |
if (!cmd.Expect()) cmd.SetExpect(new RlinkCommandExpect()); |
cmd.Expect()->SetBlock(block, blockmsk); |
return; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
void RlinkCommandList::SetLastExpect(RlinkCommandExpect* pexp) |
{ |
if (fList.empty()) |
size_t ncmd = fList.size(); |
if (ncmd == 0) |
throw Rexception("RlinkCommandList::SetLastExpect()", |
"Bad state: list empty"); |
fList.back()->SetExpect(pexp); |
fList[ncmd-1]->SetExpect(pexp); |
return; |
} |
|
293,12 → 224,12
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
void RlinkCommandList::Print(std::ostream& os, |
void RlinkCommandList::Print(std::ostream& os, const RlinkContext& cntx, |
const RlinkAddrMap* pamap, size_t abase, |
size_t dbase, size_t sbase) const |
{ |
foreach_ (RlinkCommand* pcmd, fList) { |
pcmd->Print(os, pamap, abase, dbase, sbase); |
pcmd->Print(os, cntx, pamap, abase, dbase, sbase); |
} |
return; |
} |
/tools/src/librlink/RlinkCommandList.hpp
1,6 → 1,6
// $Id: RlinkCommandList.hpp 661 2015-04-03 18:28:41Z mueller $ |
// $Id: RlinkCommandList.hpp 606 2014-11-24 07:08:51Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-02 661 1.3 expect logic: add SetLastExpect methods |
// 2014-11-23 606 1.2 new rlink v4 iface |
// 2014-08-02 576 1.1 rename LastExpect->SetLastExpect |
// 2013-05-06 495 1.0.1 add RlinkContext to Print() args; drop oper<<() |
24,7 → 23,7
|
/*! |
\file |
\version $Id: RlinkCommandList.hpp 661 2015-04-03 18:28:41Z mueller $ |
\version $Id: RlinkCommandList.hpp 606 2014-11-24 07:08:51Z mueller $ |
\brief Declaration of class RlinkCommandList. |
*/ |
|
63,12 → 62,6
size_t AddAttn(); |
size_t AddInit(uint16_t addr, uint16_t data); |
|
void SetLastExpectStatus(uint8_t stat, uint8_t statmsk=0xff); |
void SetLastExpectData(uint16_t data, uint16_t datamsk=0xffff); |
void SetLastExpectDone(uint16_t done); |
void SetLastExpectBlock(const std::vector<uint16_t>& block); |
void SetLastExpectBlock(const std::vector<uint16_t>& block, |
const std::vector<uint16_t>& blockmsk); |
void SetLastExpect(RlinkCommandExpect* exp); |
|
void ClearLaboIndex(); |
79,9 → 72,9
void Clear(); |
size_t Size() const; |
|
void Print(std::ostream& os, const RlinkAddrMap* pamap=0, |
size_t abase=16, size_t dbase=16, |
size_t sbase=16) const; |
void Print(std::ostream& os, const RlinkContext& cntx, |
const RlinkAddrMap* pamap=0, size_t abase=16, |
size_t dbase=16, size_t sbase=16) const; |
void Dump(std::ostream& os, int ind=0, const char* text=0) const; |
|
RlinkCommandList& operator=(const RlinkCommandList& rhs); |
/tools/src/librlink/RlinkCommand.ipp
1,6 → 1,6
// $Id: RlinkCommand.ipp 661 2015-04-03 18:28:41Z mueller $ |
// $Id: RlinkCommand.ipp 600 2014-11-02 22:33:02Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-02 661 1.3 expect logic: add stat check, Print() without cntx |
// 2014-11-02 600 1.2 new rlink v4 iface |
// 2013-05-06 495 1.0.1 add RlinkContext to Print() args; drop oper<<() |
// 2011-03-27 374 1.0 Initial version |
22,7 → 21,7
|
/*! |
\file |
\version $Id: RlinkCommand.ipp 661 2015-04-03 18:28:41Z mueller $ |
\version $Id: RlinkCommand.ipp 600 2014-11-02 22:33:02Z mueller $ |
\brief Implemenation (inline) of class RlinkCommand. |
*/ |
|
140,28 → 139,6
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline void RlinkCommand::SetExpectStatus(uint8_t stat, uint8_t statmsk) |
{ |
fExpectStatusSet = true; |
fExpectStatusVal = stat; |
fExpectStatusMsk = statmsk; |
return; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline void RlinkCommand::SetExpectStatusDefault(uint8_t stat, uint8_t statmsk) |
{ |
fExpectStatusSet = false; |
fExpectStatusVal = stat; |
fExpectStatusMsk = statmsk; |
return; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline uint8_t RlinkCommand::Request() const |
{ |
return fRequest; |
295,45 → 272,5
return fpExpect; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline uint8_t RlinkCommand::ExpectStatusValue() const |
{ |
return fExpectStatusVal; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline uint8_t RlinkCommand::ExpectStatusMask() const |
{ |
return fExpectStatusMsk; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline bool RlinkCommand::ExpectStatusSet() const |
{ |
return fExpectStatusSet; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline bool RlinkCommand::StatusCheck() const |
{ |
return (fStatus & fExpectStatusMsk) == fExpectStatusVal; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline bool RlinkCommand::StatusIsChecked() const |
{ |
return fExpectStatusMsk != 0x0; |
} |
|
} // end namespace Retro |
|
/tools/src/librlink/RlinkPort.ipp
1,6 → 1,6
// $Id: RlinkPort.ipp 666 2015-04-12 21:17:54Z mueller $ |
// $Id: RlinkPort.ipp 513 2013-05-01 14:02:06Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-11 666 1.3 add fXon, XonEnable() |
// 2013-05-01 513 1.2.1 fTraceLevel now uint32_t |
// 2013-02-23 492 1.2 use RparseUrl |
// 2013-02-22 491 1.1 use new RlogFile/RlogMsg interfaces |
23,7 → 22,7
|
/*! |
\file |
\version $Id: RlinkPort.ipp 666 2015-04-12 21:17:54Z mueller $ |
\version $Id: RlinkPort.ipp 513 2013-05-01 14:02:06Z mueller $ |
\brief Implemenation (inline) of RlinkPort. |
*/ |
|
49,14 → 48,6
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline bool RlinkPort::XonEnable() const |
{ |
return fXon; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline int RlinkPort::FdRead() const |
{ |
return fFdRead; |
/tools/src/librlink/ReventLoop.hpp
1,6 → 1,6
// $Id: ReventLoop.hpp 662 2015-04-05 08:02:54Z mueller $ |
// $Id: ReventLoop.hpp 513 2013-05-01 14:02:06Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-04 662 1.2 BUGFIX: fix race in Stop(), add UnStop,StopPending |
// 2013-05-01 513 1.1.1 fTraceLevel now uint32_t |
// 2013-02-22 491 1.1 use new RlogFile/RlogMsg interfaces |
// 2013-01-11 473 1.0 Initial version |
22,7 → 21,7
|
/*! |
\file |
\version $Id: ReventLoop.hpp 662 2015-04-05 08:02:54Z mueller $ |
\version $Id: ReventLoop.hpp 513 2013-05-01 14:02:06Z mueller $ |
\brief Declaration of class \c ReventLoop. |
*/ |
|
61,8 → 60,6
uint32_t TraceLevel() const; |
|
void Stop(); |
void UnStop(); |
bool StopPending(); |
virtual void EventLoop(); |
|
virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; |
82,7 → 79,7
fHandler(hdl),fFd(fd),fEvents(evts) {} |
}; |
|
bool fStopPending; |
bool fLoopActive; |
bool fUpdatePoll; |
boost::mutex fPollDscMutex; |
std::vector<PollDsc> fPollDsc; |
/tools/src/librlink/ReventLoop.ipp
1,6 → 1,6
// $Id: ReventLoop.ipp 662 2015-04-05 08:02:54Z mueller $ |
// $Id: ReventLoop.ipp 513 2013-05-01 14:02:06Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-04 662 1.2 BUGFIX: fix race in Stop(), add UnStop,StopPending |
// 2013-05-01 513 1.1.1 fTraceLevel now uint32_t |
// 2013-02-22 491 1.1 use new RlogFile/RlogMsg interfaces |
// 2013-01-11 473 1.0 Initial version |
21,7 → 20,7
|
/*! |
\file |
\version $Id: ReventLoop.ipp 662 2015-04-05 08:02:54Z mueller $ |
\version $Id: ReventLoop.ipp 513 2013-05-01 14:02:06Z mueller $ |
\brief Implemenation (inline) of class ReventLoop. |
*/ |
|
33,7 → 32,7
|
inline void ReventLoop::Stop() |
{ |
fStopPending = true; |
fLoopActive = false; |
return; |
} |
|
40,23 → 39,6
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline void ReventLoop::UnStop() |
{ |
fStopPending = false; |
return; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline bool ReventLoop::StopPending() |
{ |
return fStopPending; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline void ReventLoop::SetLogFile(const boost::shared_ptr<RlogFile>& splog) |
{ |
fspLog = splog; |
/tools/src/librlink/ReventLoop.cpp
1,6 → 1,6
// $Id: ReventLoop.cpp 662 2015-04-05 08:02:54Z mueller $ |
// $Id: ReventLoop.cpp 511 2013-04-27 13:51:46Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-04 662 1.2 BUGFIX: fix race in Stop(), add UnStop,StopPending |
// 2013-04-27 511 1.1.3 BUGFIX: logic in DoCall() fixed (loop range) |
// 2013-03-05 495 1.1.2 add exception catcher to EventLoop |
// 2013-03-01 493 1.1.1 DoCall(): remove handler on negative return |
23,7 → 22,7
|
/*! |
\file |
\version $Id: ReventLoop.cpp 662 2015-04-05 08:02:54Z mueller $ |
\version $Id: ReventLoop.cpp 511 2013-04-27 13:51:46Z mueller $ |
\brief Implemenation of class ReventLoop. |
*/ |
|
55,7 → 54,7
//! FIXME_docs |
|
ReventLoop::ReventLoop() |
: fStopPending(false), |
: fLoopActive(false), |
fUpdatePoll(false), |
fPollDscMutex(), |
fPollDsc(), |
162,10 → 161,11
|
void ReventLoop::EventLoop() |
{ |
fLoopActive = true; |
fUpdatePoll = true; |
|
try { |
while (!StopPending()) { |
while (fLoopActive) { |
int irc = DoPoll(); |
if (fPollFd.size() == 0) break; |
if (irc>0) DoCall(); |
188,7 → 188,7
{ |
RosFill bl(ind); |
os << bl << (text?text:"--") << "ReventLoop @ " << this << endl; |
os << bl << " fStopPending: " << fStopPending << endl; |
os << bl << " fLoopActive: " << fLoopActive << endl; |
os << bl << " fUpdatePoll: " << fUpdatePoll << endl; |
{ |
boost::lock_guard<boost::mutex> lock(((ReventLoop*)this)->fPollDscMutex); |
/tools/src/librlink/RlinkServerEventLoop.cpp
1,6 → 1,6
// $Id: RlinkServerEventLoop.cpp 662 2015-04-05 08:02:54Z mueller $ |
// $Id: RlinkServerEventLoop.cpp 495 2013-03-06 17:13:48Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-04 662 1.2 BUGFIX: fix race in Stop(), use StopPending() |
// 2013-03-05 495 1.1.1 add exception catcher to EventLoop |
// 2013-02-22 491 1.1 use new RlogFile/RlogMsg interfaces |
// 2013-01-12 474 1.0 Initial Version |
21,7 → 20,7
|
/*! |
\file |
\version $Id: RlinkServerEventLoop.cpp 662 2015-04-05 08:02:54Z mueller $ |
\version $Id: RlinkServerEventLoop.cpp 495 2013-03-06 17:13:48Z mueller $ |
\brief Implemenation of RlinkServerEventLoop. |
*/ |
|
60,12 → 59,13
|
void RlinkServerEventLoop::EventLoop() |
{ |
fLoopActive = true; |
fUpdatePoll = true; |
|
if (fspLog && fTraceLevel>0) fspLog->Write("eloop: starting", 'I'); |
|
try { |
while (!StopPending()) { |
while (fLoopActive) { |
int timeout = (fpServer->AttnPending() || |
fpServer->ActnPending()) ? 0 : -1; |
int irc = DoPoll(timeout); |
/tools/src/librlink/RlinkCommandExpect.cpp
1,6 → 1,6
// $Id: RlinkCommandExpect.cpp 661 2015-04-03 18:28:41Z mueller $ |
// $Id: RlinkCommandExpect.cpp 488 2013-02-16 18:49:47Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-02 661 1.1 expect logic: remove stat from Expect, invert mask |
// 2011-11-28 434 1.0.1 Dump(): use proper cast for lp64 compatibility |
// 2011-03-12 368 1.0 Initial version |
// 2011-01-15 355 0.1 First draft |
21,7 → 20,7
|
/*! |
\file |
\version $Id: RlinkCommandExpect.cpp 661 2015-04-03 18:28:41Z mueller $ |
\version $Id: RlinkCommandExpect.cpp 488 2013-02-16 18:49:47Z mueller $ |
\brief Implemenation of class RlinkCommandExpect. |
*/ |
|
50,8 → 49,10
//! Default constructor |
|
RlinkCommandExpect::RlinkCommandExpect() |
: fDataVal(0), |
fDataMsk(0x0), |
: fStatusVal(0), |
fStatusMsk(0xff), |
fDataVal(0), |
fDataMsk(0xffff), |
fBlockVal(), |
fBlockMsk() |
{} |
59,8 → 60,23
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
RlinkCommandExpect::RlinkCommandExpect(uint16_t data, uint16_t datamsk) |
: fDataVal(data), |
RlinkCommandExpect::RlinkCommandExpect(uint8_t stat, uint8_t statmsk) |
: fStatusVal(stat), |
fStatusMsk(statmsk), |
fDataVal(0), |
fDataMsk(0xffff), |
fBlockVal(), |
fBlockMsk() |
{} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
RlinkCommandExpect::RlinkCommandExpect(uint8_t stat, uint8_t statmsk, |
uint16_t data, uint16_t datamsk) |
: fStatusVal(stat), |
fStatusMsk(statmsk), |
fDataVal(data), |
fDataMsk(datamsk), |
fBlockVal(), |
fBlockMsk() |
69,9 → 85,12
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
RlinkCommandExpect::RlinkCommandExpect(const std::vector<uint16_t>& block) |
: fDataVal(0), |
fDataMsk(0x0), |
RlinkCommandExpect::RlinkCommandExpect(uint8_t stat, uint8_t statmsk, |
const std::vector<uint16_t>& block) |
: fStatusVal(stat), |
fStatusMsk(statmsk), |
fDataVal(0), |
fDataMsk(0xffff), |
fBlockVal(block), |
fBlockMsk() |
{} |
79,10 → 98,13
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
RlinkCommandExpect::RlinkCommandExpect(const std::vector<uint16_t>& block, |
RlinkCommandExpect::RlinkCommandExpect(uint8_t stat, uint8_t statmsk, |
const std::vector<uint16_t>& block, |
const std::vector<uint16_t>& blockmsk) |
: fDataVal(0), |
fDataMsk(0x0), |
: fStatusVal(stat), |
fStatusMsk(statmsk), |
fDataVal(0), |
fDataMsk(0xffff), |
fBlockVal(block), |
fBlockMsk(blockmsk) |
{} |
100,8 → 122,8
{ |
if (ind >= fBlockVal.size()) return true; |
uint16_t eval = fBlockVal[ind]; |
uint16_t emsk = (ind < fBlockMsk.size()) ? fBlockMsk[ind] : 0xffff; |
return (val & emsk) == eval; |
uint16_t emsk = (ind < fBlockMsk.size()) ? fBlockMsk[ind] : 0x0000; |
return (val|emsk) == (eval|emsk); |
} |
|
//------------------------------------------+----------------------------------- |
113,8 → 135,8
for (size_t i=0; i<size; i++) { |
if (i >= fBlockVal.size()) break; |
uint16_t eval = fBlockVal[i]; |
uint16_t emsk = (i < fBlockMsk.size()) ? fBlockMsk[i] : 0xffff; |
if ((pval[i] & emsk) != eval) nerr += 1; |
uint16_t emsk = (i < fBlockMsk.size()) ? fBlockMsk[i] : 0x0000; |
if ((pval[i]|emsk) != (eval|emsk)) nerr += 1; |
} |
|
return nerr; |
127,7 → 149,7
{ |
if (ind >= fBlockVal.size()) return false; |
if (ind >= fBlockMsk.size()) return true; |
return fBlockMsk[ind] != 0x0; |
return fBlockMsk[ind] != 0xffff; |
} |
|
//------------------------------------------+----------------------------------- |
138,6 → 160,8
RosFill bl(ind); |
os << bl << (text?text:"--") << "RlinkCommandExpect @ " << this << endl; |
|
os << bl << " fStatusVal: " << RosPrintBvi(fStatusVal,0) << endl; |
os << bl << " fStatusMsk: " << RosPrintBvi(fStatusMsk,0) << endl; |
os << bl << " fDataVal: " << RosPrintBvi(fDataVal,0) << endl; |
os << bl << " fDataMsk: " << RosPrintBvi(fDataMsk,0) << endl; |
os << bl << " fBlockVal.size: " << RosPrintf(fBlockVal.size(),"d",3) << endl; |
151,7 → 175,7
|
os << RosPrintBvi(fBlockVal[i],16); |
if (fBlockMsk.size()>0) { |
if (i<fBlockMsk.size() && fBlockMsk[i]!=0xffff) { |
if (i<fBlockMsk.size() && fBlockMsk[i]!=0x0000) { |
os << "," << RosPrintBvi(fBlockMsk[i],16); |
} else { |
os << " "; |
/tools/src/librlink/RlinkPortTerm.hpp
1,6 → 1,6
// $Id: RlinkPortTerm.hpp 666 2015-04-12 21:17:54Z mueller $ |
// $Id: RlinkPortTerm.hpp 486 2013-02-10 22:34:43Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-11 666 1.1 drop xon/xoff excaping, now done in RlinkPacketBuf |
// 2011-12-18 440 1.0.2 add kStatNPort stats |
// 2011-12-11 438 1.0.1 Read(),Write(): added for xon handling, tcdrain(); |
// 2011-03-27 374 1.0 Initial version |
22,7 → 21,7
|
/*! |
\file |
\version $Id: RlinkPortTerm.hpp 666 2015-04-12 21:17:54Z mueller $ |
\version $Id: RlinkPortTerm.hpp 486 2013-02-10 22:34:43Z mueller $ |
\brief Declaration of class RlinkPortTerm. |
*/ |
|
44,13 → 43,24
|
virtual bool Open(const std::string& url, RerrMsg& emsg); |
virtual void Close(); |
|
virtual int Read(uint8_t* buf, size_t size, double timeout, |
RerrMsg& emsg); |
virtual int Write(const uint8_t* buf, size_t size, RerrMsg& emsg); |
|
virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; |
|
// some constants (also defined in cpp) |
static const uint8_t kc_xon = 0x11; // XON char -> ^Q = hex 11 |
static const uint8_t kc_xoff = 0x13; // XOFF char -> ^S = hex 13 |
static const uint8_t kc_xesc = 0x1b; // XESC char -> ^[ = ESC = hex 1B |
|
// statistics counter indices |
enum stats { |
kStatNPortTxXesc = RlinkPort::kDimStat, |
kStatNPortRxXesc, |
kDimStat |
}; |
|
protected: |
void DumpTios(std::ostream& os, int ind, const std::string& name, |
const struct termios& tios) const; |
58,6 → 68,10
protected: |
struct termios fTiosOld; |
struct termios fTiosNew; |
bool fUseXon; //!< xon attribute set |
bool fPendXesc; //!< xesc pending |
std::vector<uint8_t> fTxBuf; //!< buffer to handle xesc |
std::vector<uint8_t> fRxBuf; //!< buffer to handle xesc |
}; |
|
} // end namespace Retro |
/tools/src/librlink/RlinkContext.hpp
1,6 → 1,6
// $Id: RlinkContext.hpp 661 2015-04-03 18:28:41Z mueller $ |
// $Id: RlinkContext.hpp 492 2013-02-24 22:14:47Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-03-28 660 1.1 add SetStatus(Value|Mask)() |
// 2013-02-23 492 1.0 Initial version |
// --------------------------------------------------------------------------- |
|
20,7 → 19,7
|
/*! |
\file |
\version $Id: RlinkContext.hpp 661 2015-04-03 18:28:41Z mueller $ |
\version $Id: RlinkContext.hpp 492 2013-02-24 22:14:47Z mueller $ |
\brief Declaration of class RlinkContext. |
*/ |
|
36,11 → 35,8
RlinkContext(); |
~RlinkContext(); |
|
void SetStatus(uint8_t stat, uint8_t statmsk=0xff); |
void SetStatus(uint8_t stat, uint8_t statmsk=0); |
|
void SetStatusValue(uint8_t stat); |
void SetStatusMask(uint8_t statmsk); |
|
uint8_t StatusValue() const; |
uint8_t StatusMask() const; |
|
/tools/src/librlink/RlinkContext.ipp
1,6 → 1,6
// $Id: RlinkContext.ipp 660 2015-03-29 22:10:16Z mueller $ |
// $Id: RlinkContext.ipp 492 2013-02-24 22:14:47Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,13 → 13,12
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-03-28 660 1.1 add SetStatus(Value|Mask)() |
// 2013-02-23 492 1.0 Initial version |
// --------------------------------------------------------------------------- |
|
/*! |
\file |
\version $Id: RlinkContext.ipp 660 2015-03-29 22:10:16Z mueller $ |
\version $Id: RlinkContext.ipp 492 2013-02-24 22:14:47Z mueller $ |
\brief Implemenation (inline) of class RlinkContext. |
*/ |
|
39,24 → 38,6
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline void RlinkContext::SetStatusValue(uint8_t stat) |
{ |
fStatusVal = stat; |
return; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline void RlinkContext::SetStatusMask(uint8_t statmsk) |
{ |
fStatusMsk = statmsk; |
return; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline uint8_t RlinkContext::StatusValue() const |
{ |
return fStatusVal; |
/tools/src/librlinktpp/RtclRlinkConnect.cpp
1,4 → 1,4
// $Id: RtclRlinkConnect.cpp 676 2015-05-09 16:31:54Z mueller $ |
// $Id: RtclRlinkConnect.cpp 631 2015-01-09 21:36:51Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,11 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-05-09 676 1.4.3 M_errcnt: add -increment; M_log: add -bare,-info.. |
// 2015-04-19 668 1.4.2 M_wtlam: allow tout=0 for pending attn cleanup |
// 2015-04-12 666 1.4.1 add M_init |
// 2015-04-03 661 1.4 expect logic: drop estatdef, use LastExpect.. |
// 2015-03-28 660 1.3.3 add stat* getter/setter; M_exec: add -estaterr ect |
// 2015-01-06 631 1.3.2 add M_get, M_set, remove M_config |
// 2014-12-20 616 1.3.1 M_exec: add -edone for BlockDone checking |
// 2014-12-06 609 1.3 new rlink v4 iface |
38,7 → 33,7
|
/*! |
\file |
\version $Id: RtclRlinkConnect.cpp 676 2015-05-09 16:31:54Z mueller $ |
\version $Id: RtclRlinkConnect.cpp 631 2015-01-09 21:36:51Z mueller $ |
\brief Implemenation of class RtclRlinkConnect. |
*/ |
|
81,7 → 76,6
{ |
AddMeth("open", boost::bind(&RtclRlinkConnect::M_open, this, _1)); |
AddMeth("close", boost::bind(&RtclRlinkConnect::M_close, this, _1)); |
AddMeth("init", boost::bind(&RtclRlinkConnect::M_init, this, _1)); |
AddMeth("exec", boost::bind(&RtclRlinkConnect::M_exec, this, _1)); |
AddMeth("amap", boost::bind(&RtclRlinkConnect::M_amap, this, _1)); |
AddMeth("errcnt", boost::bind(&RtclRlinkConnect::M_errcnt, this, _1)); |
100,9 → 94,7
fCmdnameObj[i] = Tcl_NewStringObj(RlinkCommand::CommandName(i), -1); |
} |
|
// attributes of RlinkConnect |
RlinkConnect* pobj = &Obj(); |
|
RlinkConnect* pobj = &Obj(); |
fGets.Add<uint32_t> ("baseaddr", |
boost::bind(&RlinkConnect::LogBaseAddr, pobj)); |
fGets.Add<uint32_t> ("basedata", |
117,9 → 109,6
boost::bind(&RlinkConnect::TraceLevel, pobj)); |
fGets.Add<const string&> ("logfile", |
boost::bind(&RlinkConnect::LogFileName, pobj)); |
|
fGets.Add<uint32_t> ("initdone", |
boost::bind(&RlinkConnect::LinkInitDone, pobj)); |
fGets.Add<uint32_t> ("sysid", |
boost::bind(&RlinkConnect::SysId, pobj)); |
fGets.Add<size_t> ("rbufsize", |
143,20 → 132,6
boost::bind(&RlinkConnect::SetTraceLevel, pobj, _1)); |
fSets.Add<const string&> ("logfile", |
boost::bind(&RlinkConnect::SetLogFileName, pobj, _1)); |
|
// attributes of buildin RlinkContext |
RlinkContext* pcntx = &Obj().Context(); |
fGets.Add<bool> ("statchecked", |
boost::bind(&RlinkContext::StatusIsChecked, pcntx)); |
fGets.Add<uint8_t> ("statvalue", |
boost::bind(&RlinkContext::StatusValue, pcntx)); |
fGets.Add<uint8_t> ("statmask", |
boost::bind(&RlinkContext::StatusMask, pcntx)); |
|
fSets.Add<uint8_t> ("statvalue", |
boost::bind(&RlinkContext::SetStatusValue, pcntx, _1)); |
fSets.Add<uint8_t> ("statmask", |
boost::bind(&RlinkContext::SetStatusMask, pcntx, _1)); |
} |
|
//------------------------------------------+----------------------------------- |
199,24 → 174,10
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
int RtclRlinkConnect::M_init(RtclArgs& args) |
{ |
if (!args.AllDone()) return kERR; |
if (!Obj().IsOpen()) return args.Quit("-E: port not open"); |
if (Obj().LinkInitDone()) return args.Quit("-E: already initialized"); |
RerrMsg emsg; |
if (!Obj().LinkInit(emsg)) return args.Quit(emsg); |
return kOK; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
int RtclRlinkConnect::M_exec(RtclArgs& args) |
{ |
static RtclNameSet optset("-rreg|-rblk|-wreg|-wblk|-labo|-attn|-init|" |
"-edata|-edone|-estat|" |
"-estaterr|-estatnak|-estattout|" |
"-edata|-edone|-estat|-estatdef|" |
"-print|-dump|-rlist"); |
|
Tcl_Interp* interp = args.Interp(); |
231,6 → 192,9
string vardump; |
string varlist; |
|
uint8_t estatdef_val = 0x00; |
uint8_t estatdef_msk = 0xff; |
|
while (args.NextOpt(opt, optset)) { |
|
size_t lsize = clist.Size(); |
281,6 → 245,10
|
} else if (opt == "-edata") { // -edata data ?mask -------------- |
if (!ClistNonEmpty(args, clist)) return kERR; |
if (clist[lsize-1].Expect()==0) { |
clist[lsize-1].SetExpect(new RlinkCommandExpect(estatdef_val, |
estatdef_msk)); |
} |
if (clist[lsize-1].Command() == RlinkCommand::kCmdRblk) { |
vector<uint16_t> data; |
vector<uint16_t> mask; |
287,13 → 255,13
size_t bsize = clist[lsize-1].BlockSize(); |
if (!args.GetArg("data", data, 0, bsize)) return kERR; |
if (!args.GetArg("??mask", mask, 0, bsize)) return kERR; |
clist.SetLastExpectBlock(data, mask); |
clist[lsize-1].Expect()->SetBlock(data, mask); |
} else { |
uint16_t data=0; |
uint16_t mask=0xffff; |
uint16_t mask=0; |
if (!args.GetArg("data", data)) return kERR; |
if (!args.GetArg("??mask", mask)) return kERR; |
clist.SetLastExpectData(data, mask); |
clist[lsize-1].Expect()->SetData(data, mask); |
} |
|
} else if (opt == "-edone") { // -edone done -------------------- |
300,35 → 268,39
if (!ClistNonEmpty(args, clist)) return kERR; |
uint16_t done=0; |
if (!args.GetArg("done", done)) return kERR; |
if (clist[lsize-1].Expect()==0) { |
clist[lsize-1].SetExpect(new RlinkCommandExpect(estatdef_val, |
estatdef_msk)); |
} |
uint8_t cmd = clist[lsize-1].Command(); |
if (cmd == RlinkCommand::kCmdRblk || |
cmd == RlinkCommand::kCmdWblk) { |
clist.SetLastExpectDone(done); |
clist[lsize-1].Expect()->SetDone(done); |
} else { |
return args.Quit("-E: -edone allowed only after -rblk,-wblk"); |
} |
|
} else if (opt == "-estat") { // -estat stat ?mask -------------- |
} else if (opt == "-estat") { // -estat ?stat ?mask ------------- |
if (!ClistNonEmpty(args, clist)) return kERR; |
uint8_t stat=0; |
uint8_t mask=0xff; |
if (!args.GetArg("stat", stat)) return kERR; |
uint8_t mask=0; |
if (!args.GetArg("??stat", stat)) return kERR; |
if (!args.GetArg("??mask", mask)) return kERR; |
clist.SetLastExpectStatus(stat, mask); |
if (args.NOptMiss() == 2) mask = 0xff; |
if (clist[lsize-1].Expect()==0) { |
clist[lsize-1].SetExpect(new RlinkCommandExpect()); |
} |
clist[lsize-1].Expect()->SetStatus(stat, mask); |
|
} else if (opt == "-estaterr" || // -estaterr ---------------------- |
opt == "-estatnak" || // -estatnak ---------------------- |
opt == "-estattout") { // -estattout --------------------- |
if (!ClistNonEmpty(args, clist)) return kERR; |
uint8_t val = 0; |
uint8_t msk = RlinkCommand::kStat_M_RbTout | |
RlinkCommand::kStat_M_RbNak | |
RlinkCommand::kStat_M_RbErr; |
if (opt == "-estaterr") val = RlinkCommand::kStat_M_RbErr; |
if (opt == "-estatnak") val = RlinkCommand::kStat_M_RbNak; |
if (opt == "-estattout") val = RlinkCommand::kStat_M_RbTout; |
clist.SetLastExpectStatus(val, msk); |
|
} else if (opt == "-estatdef") { // -estatdef ?stat ?mask ----------- |
uint8_t stat=0; |
uint8_t mask=0; |
if (!args.GetArg("??stat", stat)) return kERR; |
if (!args.GetArg("??mask", mask)) return kERR; |
if (args.NOptMiss() == 2) mask = 0xff; |
estatdef_val = stat; |
estatdef_msk = mask; |
|
} else if (opt == "-print") { // -print ?varRes ----------------- |
varprint = "-"; |
if (!args.GetArg("??varRes", varprint)) return kERR; |
340,8 → 312,18
if (!args.GetArg("??varRes", varlist)) return kERR; |
} |
|
} // while (args.NextOpt(opt, optset)) |
if (estatdef_msk != 0xff && // estatdef defined |
lsize != clist.Size()) { // and cmd added to clist |
for (size_t i=lsize; i<clist.Size(); i++) { // loop over new cmds |
if (clist[i].Expect()==0) { // if no stat |
clist[i].SetExpect(new RlinkCommandExpect(estatdef_val, |
estatdef_msk)); |
} |
} |
} |
|
} |
|
int nact = 0; |
if (varprint == "-") nact += 1; |
if (vardump == "-") nact += 1; |
385,7 → 367,7
|
if (!varprint.empty()) { |
ostringstream sos; |
clist.Print(sos, &Obj().AddrMap(), Obj().LogBaseAddr(), |
clist.Print(sos, Obj().Context(), &Obj().AddrMap(), Obj().LogBaseAddr(), |
Obj().LogBaseData(), Obj().LogBaseStat()); |
RtclOPtr pobj(Rtcl::NewLinesObj(sos)); |
if (!Rtcl::SetVarOrResult(args.Interp(), varprint, pobj)) return kERR; |
536,20 → 518,17
|
int RtclRlinkConnect::M_errcnt(RtclArgs& args) |
{ |
static RtclNameSet optset("-clear|-increment"); |
static RtclNameSet optset("-clear"); |
string opt; |
bool fclr = false; |
bool finc = false; |
bool fclear = false; |
|
while (args.NextOpt(opt, optset)) { |
if (opt == "-clear") fclr = true; |
if (opt == "-increment") finc = true; |
if (opt == "-clear") fclear = true; |
} |
if (!args.AllDone()) return kERR; |
|
if (finc) Obj().Context().IncErrorCount(); |
args.SetResult(int(Obj().Context().ErrorCount())); |
if (fclr) Obj().Context().ClearErrorCount(); |
if (fclear) Obj().Context().ClearErrorCount(); |
|
return kOK; |
} |
561,7 → 540,7
{ |
double tout; |
string rvn_apat; |
if (!args.GetArg("tout", tout, 0.0)) return kERR; |
if (!args.GetArg("tout", tout, 0.001)) return kERR; |
if (!args.GetArg("??varApat", rvn_apat)) return kERR; |
if (!args.AllDone()) return kERR; |
|
590,14 → 569,9
|
if (Obj().PrintLevel() >= 3) { |
RlogMsg lmsg(Obj().LogFile()); |
lmsg << "-- wtlam apat=" << RosPrintf(apat,"x0",4); |
if (tout == 0.) { |
lmsg << " to=0 harvest only"; |
} else { |
lmsg << " to=" << RosPrintf(tout, "f", 0,3) |
<< " T=" << RosPrintf(twait, "f", 0,3); |
} |
lmsg << " OK" << endl; |
lmsg << "-- wtlam to=" << RosPrintf(tout, "f", 0,3) |
<< " T=" << RosPrintf(twait, "f", 0,3) |
<< " OK" << endl; |
} |
|
args.SetResult(twait); |
687,18 → 661,6
|
int RtclRlinkConnect::M_log(RtclArgs& args) |
{ |
static RtclNameSet optset("-bare|-info|-warn|-error|-fatal"); |
string opt; |
bool fbare = false; |
char tag = 0; |
while (args.NextOpt(opt, optset)) { |
if (opt == "-bare") fbare = true; |
if (opt == "-info") tag = 'I'; |
if (opt == "-warn") tag = 'W'; |
if (opt == "-error") tag = 'E'; |
if (opt == "-fatal") tag = 'F'; |
} |
|
string msg; |
if (!args.GetArg("msg", msg)) return kERR; |
if (!args.AllDone()) return kERR; |
705,11 → 667,7
if (Obj().PrintLevel() != 0 || |
Obj().DumpLevel() != 0 || |
Obj().TraceLevel() != 0) { |
if (tag || fbare) { |
Obj().LogFile().Write(msg, tag); |
} else { |
Obj().LogFile().Write(string("# ") + msg); |
} |
Obj().LogFile().Write(string("# ") + msg); |
} |
return kOK; |
} |
852,6 → 810,7
return true; |
} |
|
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
/tools/src/librlinktpp/RtclRlinkConnect.hpp
1,4 → 1,4
// $Id: RtclRlinkConnect.hpp 666 2015-04-12 21:17:54Z mueller $ |
// $Id: RtclRlinkConnect.hpp 631 2015-01-09 21:36:51Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-12 666 1.0.5 add M_init |
// 2015-01-06 631 1.0.4 add M_get, M_set, remove M_config |
// 2013-02-23 492 1.0.3 use RlogFile.Name(); use Context().ErrorCount() |
// 2013-01-06 473 1.0.2 add M_rawio |
24,7 → 23,7
|
/*! |
\file |
\version $Id: RtclRlinkConnect.hpp 666 2015-04-12 21:17:54Z mueller $ |
\version $Id: RtclRlinkConnect.hpp 631 2015-01-09 21:36:51Z mueller $ |
\brief Declaration of class RtclRlinkConnect. |
*/ |
|
51,7 → 50,6
protected: |
int M_open(RtclArgs& args); |
int M_close(RtclArgs& args); |
int M_init(RtclArgs& args); |
int M_exec(RtclArgs& args); |
int M_amap(RtclArgs& args); |
int M_errcnt(RtclArgs& args); |
/tools/src/librlinktpp/RtclRlinkServer.cpp
1,6 → 1,6
// $Id: RtclRlinkServer.cpp 662 2015-04-05 08:02:54Z mueller $ |
// $Id: RtclRlinkServer.cpp 632 2015-01-11 12:30:03Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-04 662 1.1 add M_get, M_set; remove 'server -trace' |
// 2014-08-22 584 1.0.6 use nullptr |
// 2013-05-01 513 1.0.5 TraceLevel now uint32_t |
// 2013-04-26 510 1.0.4 change M_attn, now -info instead of -show |
25,7 → 24,7
|
/*! |
\file |
\version $Id: RtclRlinkServer.cpp 662 2015-04-05 08:02:54Z mueller $ |
\version $Id: RtclRlinkServer.cpp 632 2015-01-11 12:30:03Z mueller $ |
\brief Implemenation of class RtclRlinkServer. |
*/ |
|
64,9 → 63,7
RtclRlinkServer::RtclRlinkServer(Tcl_Interp* interp, const char* name) |
: RtclProxyOwned<RlinkServer>("RlinkServer", interp, name, |
new RlinkServer()), |
fspConn(), |
fGets(), |
fSets() |
fspConn() |
{ |
AddMeth("server", boost::bind(&RtclRlinkServer::M_server, this, _1)); |
AddMeth("attn", boost::bind(&RtclRlinkServer::M_attn, this, _1)); |
73,31 → 70,7
AddMeth("stats", boost::bind(&RtclRlinkServer::M_stats, this, _1)); |
AddMeth("print", boost::bind(&RtclRlinkServer::M_print, this, _1)); |
AddMeth("dump", boost::bind(&RtclRlinkServer::M_dump, this, _1)); |
AddMeth("get", boost::bind(&RtclRlinkServer::M_get, this, _1)); |
AddMeth("set", boost::bind(&RtclRlinkServer::M_set, this, _1)); |
AddMeth("$default", boost::bind(&RtclRlinkServer::M_default, this, _1)); |
|
// attributes of RlinkConnect |
RlinkServer* pobj = &Obj(); |
fGets.Add<uint32_t> ("tracelevel", |
boost::bind(&RlinkServer::TraceLevel, pobj)); |
|
fSets.Add<uint32_t> ("tracelevel", |
boost::bind(&RlinkServer::SetTraceLevel, pobj, _1)); |
|
// attributes of buildin RlinkContext |
RlinkContext* pcntx = &Obj().Context(); |
fGets.Add<bool> ("statchecked", |
boost::bind(&RlinkContext::StatusIsChecked, pcntx)); |
fGets.Add<uint8_t> ("statvalue", |
boost::bind(&RlinkContext::StatusValue, pcntx)); |
fGets.Add<uint8_t> ("statmask", |
boost::bind(&RlinkContext::StatusMask, pcntx)); |
|
fSets.Add<uint8_t> ("statvalue", |
boost::bind(&RlinkContext::SetStatusValue, pcntx, _1)); |
fSets.Add<uint8_t> ("statmask", |
boost::bind(&RlinkContext::SetStatusMask, pcntx, _1)); |
} |
|
//------------------------------------------+----------------------------------- |
138,7 → 111,7
|
int RtclRlinkServer::M_server(RtclArgs& args) |
{ |
static RtclNameSet optset("-start|-stop|-resume|-test"); |
static RtclNameSet optset("-start|-stop|-resume|-test|-trace"); |
string opt; |
if (args.NextOpt(opt, optset)) { |
if (opt == "-start") { // server -start |
153,6 → 126,14
} else if (opt == "-test") { // server -test |
if (!args.AllDone()) return kERR; |
args.SetResult(Obj().IsActive()); |
} else if (opt == "-trace") { // server -trace ... |
uint32_t level; |
if (!args.GetArg("?level", level)) return kERR; |
if (args.NOptMiss()==0) { // server -trace level |
Obj().SetTraceLevel(level); |
} else { // server -trace |
args.SetResult((int)Obj().TraceLevel()); |
} |
} |
|
} else { // server |
302,26 → 283,6
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
int RtclRlinkServer::M_get(RtclArgs& args) |
{ |
// synchronize with server thread (really needed ??) |
boost::lock_guard<RlinkConnect> lock(Obj().Connect()); |
return fGets.M_get(args); |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
int RtclRlinkServer::M_set(RtclArgs& args) |
{ |
// synchronize with server thread (really needed ??) |
boost::lock_guard<RlinkConnect> lock(Obj().Connect()); |
return fSets.M_set(args); |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
int RtclRlinkServer::M_default(RtclArgs& args) |
{ |
if (!args.AllDone()) return kERR; |
/tools/src/librlinktpp/RtclRlinkServer.hpp
1,6 → 1,6
// $Id: RtclRlinkServer.hpp 662 2015-04-05 08:02:54Z mueller $ |
// $Id: RtclRlinkServer.hpp 486 2013-02-10 22:34:43Z mueller $ |
// |
// Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,7 → 13,6
// |
// Revision History: |
// Date Rev Version Comment |
// 2015-04-04 662 1.1 add M_get, M_set; remove 'server -trace' |
// 2013-02-05 482 1.0.1 add shared_ptr to RlinkConnect object |
// 2013-01-12 474 1.0 Initial version |
// --------------------------------------------------------------------------- |
20,7 → 19,7
|
/*! |
\file |
\version $Id: RtclRlinkServer.hpp 662 2015-04-05 08:02:54Z mueller $ |
\version $Id: RtclRlinkServer.hpp 486 2013-02-10 22:34:43Z mueller $ |
\brief Declaration of class RtclRlinkServer. |
*/ |
|
34,10 → 33,7
|
#include "librtcltools/RtclOPtr.hpp" |
#include "librtcltools/RtclProxyOwned.hpp" |
#include "librtcltools/RtclGetList.hpp" |
#include "librtcltools/RtclSetList.hpp" |
#include "RtclAttnShuttle.hpp" |
|
#include "librlink/RlinkServer.hpp" |
|
namespace Retro { |
57,8 → 53,6
int M_stats(RtclArgs& args); |
int M_print(RtclArgs& args); |
int M_dump(RtclArgs& args); |
int M_get(RtclArgs& args); |
int M_set(RtclArgs& args); |
int M_default(RtclArgs& args); |
|
protected: |
67,8 → 61,6
|
boost::shared_ptr<RlinkConnect> fspConn; |
alist_t fAttnHdl; //<! list of attn handlers |
RtclGetList fGets; |
RtclSetList fSets; |
}; |
|
} // end namespace Retro |
/tools/bin/tbrun_tbwrri
1,23 → 1,14
#!/bin/bash |
# $Id: tbrun_tbwrri 666 2015-04-12 21:17:54Z mueller $ |
# $Id: tbrun_tbwrri 641 2015-02-01 22:12:15Z mueller $ |
# |
# Copyright 2014-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-04-11 666 1.1 add --fusp,--xon |
# 2014-12-27 622 1.0 Initial version |
# |
|
chkval () |
{ |
if [[ $1 =~ --.* || $1 =~ -[a-z]* ]]; then |
echo "tbrun_tbwrri-E: value forgotten prior to '$1'" |
exit 1 |
fi |
} |
|
docmd () |
{ |
echo "$1" |
35,24 → 26,19
optrri="" |
optpcom="" |
optcuff="" |
optfusp="" |
optxon="" |
|
# handle options |
while (( $# > 0 )) ; do |
case $1 in |
-dry|--dry) optdry=$1 ; shift 1 ;; |
-lsuf|--lsuf) optlsuf=$2 ; chkval $2 ; shift 2 ;; |
-stack|--stack) optstack=$2 ; chkval $2 ; shift 2 ;; |
-ghw|--ghw) optghw=$2 ; chkval $2 ; shift 2 ;; |
-tbw|--tbw) opttbw=$2 ; chkval $2 ; shift 2 ;; |
-pack|--pack) optpack=$2 ; chkval $2 ; shift 2 ;; |
-rri|--rri) optrri=$2 ; chkval $2 ; shift 2 ;; |
-cuff|--cuff) optcuff=$1 ; shift 1 ;; |
-fusp|--fusp) optfusp=$1 ; shift 1 ;; |
-xon|--xon) optxon=$1 ; shift 1 ;; |
-pcom|--pcom) optpcom=$1 ; shift 1 ;; |
-\?|-h*|--h*) opthelp=$1 ; shift 1 ;; |
-dry|--dry) optdry=$1 ; shift 1 ;; |
-lsuf|--lsuf) optlsuf=$2 ; shift 2 ;; |
-stack|--stack) optstack=$2 ; shift 2 ;; |
-ghw|--ghw) optghw=$2 ; shift 2 ;; |
-tbw|--tbw) opttbw=$2 ; shift 2 ;; |
-pack|--pack) optpack=$2 ; shift 2 ;; |
-rri|--rri) optrri=$2 ; shift 2 ;; |
-cuff|--cuff) optcuff=$1 ; shift 1 ;; |
-pcom|--pcom) optpcom=$1 ; shift 1 ;; |
-*) echo "tbrun_tbwrri-E: invalid option '$1'"; exit 1 ;; |
*) break;; |
esac |
59,34 → 45,21
done |
|
# complain if no tbench defined |
if [[ -n "$opthelp" || $# -eq 0 ]] ; then |
if (( $# == 0 )) ; then |
echo "Usage: tbrun_tbwrri [opts] testbench rricmds..." |
echo " Options:" |
echo " --dry dry run, print commands, don't execute" |
echo " --lsuf suff use '_<suff>.log' as suffix for log file" |
echo " --stack nnn use <nnn> as ghdl stack size" |
echo " --ghw fname write ghw file with name '<fname>.ghw'" |
echo " --ghw fname write ghw file with name '<fname>.ghw" |
echo " --tbw opts append <opts> to tbw command" |
echo " --pack plist add '--pack=<=plist>' option to ti_rri" |
echo " --rri opts append <opts> to ti_rri command" |
echo " --cuff use cuff and not serport" |
echo " --fusp use 2nd serport" |
echo " --xon use xon with 1st serport" |
echo " --pcom print test comments" |
exit 1 |
fi |
|
# check that only one of --cuff --fusp or --xon given |
ncfxcount=0 |
if [[ -n "$optcuff" ]] ; then ncfxcount=$(($ncfxcount+1)); fi |
if [[ -n "$optfusp" ]] ; then ncfxcount=$(($ncfxcount+1)); fi |
if [[ -n "$optxon" ]] ; then ncfxcount=$(($ncfxcount+1)); fi |
|
if (( $ncfxcount > 1 )) ; then |
echo "tbrun_tbwrri-E: only one of --cuff,-fusp,--xon allowed" |
exit 1 |
fi |
|
tbench=$1 |
shift 1 |
|
119,48 → 92,17
cmd="time ti_rri --run=\"tbw $tbench -fifo" |
if [[ -n "$opttbw" ]] ; then cmd+=" $opttbw"; fi |
if [[ -n "$optstack" ]] ; then cmd+=" --stack-max-size=$optstack"; fi |
if [[ -n "$optghw" ]] ; then |
if [[ "$optghw" != *.ghw ]]; then optghw="$optghw.ghw"; fi |
cmd+=" --wave=$optghw"; |
fi |
if [[ -n "$optghw" ]] ; then cmd+=" --wave=$optghw.ghw"; fi |
cmd+=" 2>&1 | ghdl_assert_filter\"" |
|
# Note: the following ensurs that we always have 'fifo=,<options' with an |
# empty first field (the default fifo name) |
fifoopts="" |
if [[ -n "$optxon" ]] ; then fifoopts+=",xon"; fi |
if (( $ncfxcount > 0 )) ; then fifoopts+=",noinit"; fi |
|
if [[ -n "$fifoopts" ]] ; then |
cmd+=" --fifo=$fifoopts" |
else |
cmd+=" --fifo" |
fi |
|
cmd+=" --logl=3" |
|
cmd+=" --fifo --logl=3" |
if [[ -n "$optpack" ]] ; then cmd+=" --pack=$optpack"; fi |
if [[ -n "$optrri" ]] ; then cmd+=" $optrri"; fi |
|
cmd+=" --" |
|
if [[ -n "$optcuff" ]] ; then |
cmd+=" \"rlc oob -sbdata 8 0x4\"" # portsel = 0100 -> fx2 |
cmd+=" \"rlc oob -sbdata 16 0x4\"" # swi = 0100 -> fx2 |
cmd+=" \"rlc oob -sbdata 8 0x2\" \"rlc oob -sbdata 16 0x4\"" |
fi |
|
if [[ -n "$optfusp" ]] ; then |
cmd+=" \"rlc oob -sbdata 8 0x1\"" # portsel = 0001 -> 2nd ser |
cmd+=" \"rlc oob -sbdata 16 0x1\"" # swi = 0001 -> 2nd ser |
fi |
|
if [[ -n "$optxon" ]] ; then |
cmd+=" \"rlc oob -sbdata 8 0x2\"" # portsel = 0010 -> 1st ser XON |
cmd+=" \"rlc oob -sbdata 16 0x2\"" # swi = 0010 -> 1st ser XON |
fi |
|
if (( $ncfxcount > 0 )) ; then cmd+=" \"rlc init\""; fi |
|
while (( $# > 0 )) ; do |
cmd+=" " |
if [[ $1 =~ " " ]] ; then cmd+="\""; fi |
/tools/bin/ticonv_pdpcp
1,7 → 1,7
#!/usr/bin/perl -w |
# $Id: ticonv_pdpcp 675 2015-05-08 21:05:08Z mueller $ |
# $Id: ticonv_pdpcp 646 2015-02-15 12:04:55Z mueller $ |
# |
# Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
# This program is free software; you may redistribute and/or modify it under |
# the terms of the GNU General Public License as published by the Free |
14,8 → 14,6
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-05-08 675 1.3.1 start/stop/suspend overhaul |
# 2015-04-03 661 1.3 adopt to new stat checking and mask polarity |
# 2014-12-27 622 1.2.1 use wmembe now |
# 2014-12-07 609 1.2 use rlink::anena (for rlink v4) |
# 2014-07-31 576 1.1 add --cmax option (default = 3); support .sdef |
53,16 → 51,11
my $tout = $opts{tout} || 10.; |
my $cmax = $opts{cmax} || 6; |
|
my $ref_sdef = 0x00; # by default check for 'hard' errors |
my $msk_sdef = 0xf0; # ignore the status bits + attn flag |
|
open IFILE, $fnam or die "failed to open '$fnam'"; |
|
print "set old_statvalue [rlc get statvalue]\n"; |
print "set old_statmask [rlc get statmask]\n"; |
print "\n"; |
|
print "rlc set statvalue 0x00\n"; |
print "rlc set statmask \$rlink::STAT_DEFMASK\n"; |
print "\n"; |
|
while (<IFILE>) { |
chomp; |
s/--.*//; # drop all -- style comments |
101,12 → 94,8
# .sdef s=ref[,msk] ------------------------------------------------ |
} elsif ($cmd =~ /^\.sdef\s+s=([01]+),?([01]*)$/) { |
cmdlist_do(); |
my $ref_sdef = oct("0b$1"); |
my $msk_sdef = oct("0b$2"); |
$msk_sdef = 0 unless defined $msk_sdef; # nothing ignored if not defined |
printf "rlc log \".sdef 0x%2.2x,0x%2.2x\"\n", $ref_sdef, $msk_sdef; |
printf "rlc set statvalue 0x%2.2x\n", $ref_sdef; |
printf "rlc set statmask 0x%2.2x\n", (0xff & ~$msk_sdef); |
$ref_sdef = oct("0b$1"); |
$msk_sdef = oct("0b$2"); |
|
# .rlmon,.rbmon ---------------------------------------------------- |
} elsif ($cmd =~ /^\.(r[lb]mon)\s+(\d)$/) { |
182,10 → 171,10
next if $dat =~ m/^#/; |
if ($dat =~ m/d=([0-7]+)/ ) { |
push @data, "0$1"; |
push @mask, "0177777"; |
push @mask, "0"; |
} elsif ($dat =~ m/d=-/) { |
push @data, "0"; |
push @mask, "0"; |
push @mask, "0177777"; |
$domask = 1; |
} else { |
exit 1; |
205,13 → 194,13
push @cmdlist, "-$1 0$2"; |
add_edata($'); |
|
# simple action commands: sta,sto,step,cres,bres ------------------- |
} elsif ($cmd =~ /^(sta|sto|step|cres|bres)$/) { |
# simple action commands: sta,sto,cont,step,rst -------------------- |
} elsif ($cmd =~ /^(sta|sto|cont|step|rst)$/) { |
my %cmdmap = (sta => 'start', |
sto => 'stop', |
cont => 'continue', |
step => 'step', |
cres => 'creset', |
bres => 'breset'); |
rst => 'reset'); |
push @cmdlist, sprintf "-%s", $cmdmap{$1}; |
|
# wtgo -> wtcpu ---------------------------------------------------- |
241,11 → 230,6
} |
|
cmdlist_do(); |
|
print "\n"; |
print "rlc set statvalue \$old_statvalue\n"; |
print "rlc set statmask \$old_statmask\n"; |
|
exit 0; |
|
#------------------------------------------------------------------------------- |
262,7 → 246,7
return unless scalar(@cmdlist); |
|
# printf "$cpu cp \\\n"; |
print "$cpu cp \\\n"; |
printf "$cpu cp -estatdef 0x%2.2x 0x%2.2x \\\n", $ref_sdef, $msk_sdef; |
while (scalar(@cmdlist)) { |
print " "; |
print shift @cmdlist; |
/tools/bin/vbomconv
1,5 → 1,5
#!/usr/bin/perl -w |
# $Id: vbomconv 672 2015-05-02 21:58:28Z mueller $ |
# $Id: vbomconv 646 2015-02-15 12:04:55Z mueller $ |
# |
# Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
383,7 → 383,6
# --xst_prj ---------------------------------------------------------- |
|
if (exists $opts{xst_prj}) { |
## $xst_writevhdl = 0; # needed in case "-use_new_parser yes" used |
foreach (@srcfile_list) { |
if ($xst_writevhdl) { |
print "vhdl work $_\n"; |
/tools/bin/ti_w11
1,5 → 1,5
#!/usr/bin/perl -w |
# $Id: ti_w11 680 2015-05-14 13:29:46Z mueller $ |
# $Id: ti_w11 654 2015-03-01 18:45:38Z mueller $ |
# |
# Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
6,8 → 6,6
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-05-14 680 1.3.1 use now -f1,-f1e,-f2,-f2e (fx now f1e) |
# 2015-04-13 667 1.3 rename -fu->-fc, add -f2,-fx; setup good defaults |
# 2015-01-02 640 1.2.2 BUGFIX: allow 'M' unit in baud rates |
# 2014-12-23 619 1.2.1 use -fifo tbw option for test bench starts |
# 2014-07-13 570 1.2 BUGFIX: split options args into ti_rri opts and cmds |
25,7 → 23,6
|
my $sysbase = "$ENV{RETROBASE}/rtl/sys_gen/w11a"; |
|
my $opt_dry; |
my $opt_b; |
my $opt_io = ''; |
my $opt_f = ''; |
49,11 → 46,7
while (scalar(@ARGV)) { |
my $curarg = $ARGV[0]; |
|
if ($curarg =~ m{^-dry$} ) { # -dry |
$opt_dry = 1; |
shift @ARGV; |
|
} elsif ($curarg =~ m{^-b$} ) { # -b |
if ($curarg =~ m{^-b$} ) { # -b |
$opt_b = 1; |
shift @ARGV; |
|
61,43 → 54,37
$opt_tmu = 1; |
shift @ARGV; |
|
} elsif ($curarg =~ m{^-s3$} ) { # -s3 (use -f2 by default) |
} elsif ($curarg =~ m{^-s3$} ) { # -s3 |
$opt_io = 'f'; |
$opt_f = '2'; |
$val_tb = $val_tb_s3; |
shift @ARGV; |
|
} elsif ($curarg =~ m{^-n2$} ) { # -n2 (use -fc by default) |
} elsif ($curarg =~ m{^-n2$} ) { # -n2 |
$opt_io = 'f'; |
$opt_f = 'c'; |
$val_tb = $val_tb_n2; |
shift @ARGV; |
|
} elsif ($curarg =~ m{^-n3$} ) { # -n3 (use -fc by default) |
} elsif ($curarg =~ m{^-n3$} ) { # -n3 |
$opt_io = 'f'; |
$opt_f = 'c'; |
$val_tb = $val_tb_n3; |
shift @ARGV; |
|
} elsif ($curarg =~ m{^-b3$} ) { # -b3 (use -f1x by default) |
} elsif ($curarg =~ m{^-b4$} ) { # -b3 |
$opt_io = 'f'; |
$opt_f = '1x'; |
$val_tb = $val_tb_b3; |
shift @ARGV; |
|
} elsif ($curarg =~ m{^-n4$} ) { # -n4 (prim serport fine) |
} elsif ($curarg =~ m{^-n4$} ) { # -n4 |
$opt_io = 'f'; |
$opt_f = '1'; |
$val_tb = $val_tb_n4; |
shift @ARGV; |
|
} elsif ($curarg =~ m{^-bn4$} ) { # -bn4 (prim serport fine) |
} elsif ($curarg =~ m{^-bn4$} ) { # -bn4 |
$opt_io = 'f'; |
$opt_f = '1'; |
$val_tb = $val_tb_bn4; |
shift @ARGV; |
|
} elsif ($curarg =~ m{^-f(c|1|1x|2|2x)$} ) { # -f.. |
} elsif ($curarg =~ m{^-f(s\d?|u)$} ) { # -f[su] |
$opt_f = $1; |
shift @ARGV; |
|
165,13 → 152,11
|
# |
# check that either -(s3|n2|n3|n4|bn4) or -t or -u given |
# setup options for either case |
# setup pi_rri options for either case |
# |
|
if ($opt_io eq 'f') { |
my $fifoopts = ",noinit"; # fifo always with deferred init |
$fifoopts .= ",xon" if $opt_f eq 'x'; |
push @arglist, "--fifo=$fifoopts"; |
push @arglist, '--fifo'; |
push @arglist, "--run=$val_tb"; |
} elsif ($opt_io eq 't') { |
push @arglist, "--term=$val_term"; |
178,7 → 163,7
} elsif ($opt_io eq 'u') { |
push @arglist, '--cuff'; |
} else { |
print STDERR "ti_w11-E: neither -(s3|n2|n3|b3|n4|bn4) nor -t,-u specified\n"; |
print STDERR "ti_w11-E: neither -(s3|n2|n3|b3|n4|bn4) nor -t or -u specified\n"; |
print_usage(); |
exit 1; |
} |
202,27 → 187,13
if ($opt_tmu) { |
push @arglist, 'rlc oob -sbcntl 13 1'; |
} |
if ($opt_f eq 'c') { |
push @arglist, 'rlc oob -sbdata 8 0x4'; # portsel = 0100 -> fx2 |
push @arglist, 'rlc oob -sbdata 16 0x4'; # swi = 0100 -> fx2 |
} elsif ($opt_f eq '1x') { |
push @arglist, 'rlc oob -sbdata 8 0x2'; # portsel = 0010 -> 1st ser XON |
push @arglist, 'rlc oob -sbdata 16 0x2'; # swi = 0010 -> 1st ser XON |
} elsif ($opt_f eq '2') { |
push @arglist, 'rlc oob -sbdata 8 0x1'; # portsel = 0001 -> 2nd ser |
push @arglist, 'rlc oob -sbdata 16 0x1'; # swi = 0001 -> 2nd ser |
} elsif ($opt_f eq '2x') { |
push @arglist, 'rlc oob -sbdata 8 0x3'; # portsel = 0011 -> 2nd ser XON |
push @arglist, 'rlc oob -sbdata 16 0x3'; # swi = 0011 -> 2nd ser XON |
if ($opt_f eq 'u') { |
push @arglist, 'rlc oob -sbdata 8 0x2'; |
push @arglist, 'rlc oob -sbdata 16 0x4'; |
} |
} |
|
# |
# --fifo always uses deferred init, so add a rlc init after the oob's |
# |
push @arglist, 'rlc init' if $opt_io eq 'f'; |
|
# |
# initialize w11 cpu system |
# |
push @arglist, 'rw11::setup_sys'; |
256,7 → 227,7
} |
|
# |
# print command line |
# print command file |
# |
if (1) { |
print 'ti_rri ', join (' ', map {(m{\s}) ? "\"$_\"" : $_} @arglist) , "\n"; |
263,10 → 234,6
} |
|
# |
# if dry run, stop here |
# |
exit 0 if $opt_dry; |
# |
# and do it |
# |
exec $tirri, @arglist |
278,18 → 245,14
sub print_usage { |
print "usage: ti_w11 <setup options> <ti_rri opts and cmds>...\n"; |
print " setup options for ghdl simulation runs:\n"; |
print " -b3 start tb_w11a_b3 simulation (default: -f1x)\n"; |
print " -b3 start tb_w11a_b3 simulation\n"; |
print " -n4 start tb_w11a_n4 simulation\n"; |
print " -bn4 start tb_w11a_br_n4 simulation\n"; |
print " -n3 start tb_w11a_n3 simulation (default: -fc)\n"; |
print " -n2 start tb_w11a_n2 simulation (default: -fc)\n"; |
print " -s3 start tb_w11a_s3 simulation (default: -f2)\n"; |
print " -n3 start tb_w11a_n3 simulation\n"; |
print " -n2 start tb_w11a_n2 simulation\n"; |
print " -s3 start tb_w11a_s3 simulation\n"; |
print " -f.. simulation communication options\n"; |
print " -fc use fx2 data path (cuff)\n"; |
print " -f1 use 1st serport\n"; |
print " -f1x use 1st serport with xon\n"; |
print " -f2 use 2nd serport (fusp)\n"; |
print " -f2x use 2nd serport with xon\n"; |
print " -fu use cuff data path\n"; |
print " -tmu activate trace and monitoring unit\n"; |
print " setup options for FPGA connects:\n"; |
print " -u use --cuff connect\n"; |
/tools/bin/asm-11
1,5 → 1,5
#!/usr/bin/perl -w |
# $Id: asm-11 659 2015-03-22 23:15:51Z mueller $ |
# $Id: asm-11 575 2014-07-27 20:55:41Z mueller $ |
# |
# Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
506,7 → 506,7
|
printf "-- parse: '$line'\n" if $opts{tparse} || $opts{ttoken}; |
|
# quit if invalid character found (non 7 bit ascii in asm-11) |
# quit if illegal character found (non 7 bit ascii in asm-11) |
foreach my $c (@{$l{cl}}) { |
if (ord($c) > 127) { |
add_err(\%l, 'I'); |
/tools/bin/create_disk
1,5 → 1,5
#!/usr/bin/perl -w |
# $Id: create_disk 679 2015-05-13 17:38:46Z mueller $ |
# $Id: create_disk 562 2014-06-15 17:23:18Z mueller $ |
# |
# Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
14,7 → 14,6
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-04-06 665 1.1.1 add alias RM03 (for RM02) and RP05 (for RP04) |
# 2014-06-14 562 1.1 BUGFIX: repair --boot; add RM02,RM05,RP04,RP07 |
# 2013-05-20 521 1.0 First draft |
# |
70,10 → 69,6
} |
|
my $typ = uc($opts{typ}); |
|
$typ = "RM02" if defined $typ && $typ eq "RM03"; # RM03 is equivalent to RM02 |
$typ = "RP04" if defined $typ && $typ eq "RP05"; # RM05 is equivalent to RP04 |
|
unless (defined $typ && exists $disktype{$typ}) { |
print STDERR "create_disk-E: no or invalid --typ specification, use --help\n"; |
exit 1; |
218,12 → 213,12
$buf .= "++======================================++\r\n"; |
$buf .= "\r\n"; |
$buf .= "Disk image created with 'create_disk --typ=$typ':\r\n"; |
$buf .= sprintf " number of cylinders: %7d\r\n", $cyl; |
$buf .= sprintf " tracks per cylinder: %7d\r\n", $hd; |
$buf .= sprintf " sectors per track: %7d\r\n", $sec; |
$buf .= sprintf " block size: %7d\r\n", $bps; |
$buf .= sprintf " total number of sectors:%7d\r\n", $nblk; |
$buf .= sprintf " capacity in kByte: %7d\r\n", $cap/1024; |
$buf .= sprintf " number of cylinders: %6d\r\n", $cyl; |
$buf .= sprintf " tracks per cylinder: %6d\r\n", $hd; |
$buf .= sprintf " sectors per track: %6d\r\n", $sec; |
$buf .= sprintf " block size: %6d\r\n", $bps; |
$buf .= sprintf " total number of sectors: %6d\r\n", $nblk; |
$buf .= sprintf " capacity in kByte: %6d\r\n", $cap/1024; |
$buf .= "\r\n"; |
$buf .= "CPU WILL HALT\r\n"; |
$buf .= "\r\n"; |
266,10 → 261,6
} |
|
print "\n"; |
print " RM03 is accepted as an alias for RM02 (same capacity)\n"; |
print " RP05 is accepted as an alias for RP04 (same capacity)\n"; |
|
print "\n"; |
print "currently supported initialization patterns:\n"; |
print " zero all zero (the default anyway if no -ini given)\n"; |
print " ones all ones\n"; |
/tools/bin/tmuconv
1,7 → 1,7
#!/usr/bin/perl -w |
# $Id: tmuconv 676 2015-05-09 16:31:54Z mueller $ |
# $Id: tmuconv 334 2010-10-23 08:24:24Z mueller $ |
# |
# Copyright 2008-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
# This program is free software; you may redistribute and/or modify it under |
# the terms of the GNU General Public License as published by the Free |
55,9 → 55,7
# vm.ibsres.busy:b |
# vm.ibsres.dout:o |
# co.cpugo:b |
# co.cpususp:b |
# co.suspint:b |
# co.suspext:b |
# co.cpuhalt:b |
# sy.emmreq.req:b |
# sy.emmreq.we:b |
# sy.emmreq.be:b |
316,28 → 314,6
177414=> "rk.mr ", |
177416=> "rk.db ", |
177060=> "xor.cs", # XOR Tester |
176700=> "rpa.cs1", |
176702=> "rpa.wc ", |
176704=> "rpa.ba ", |
176706=> "rpa.da ", |
176710=> "rpa.cs2", |
176712=> "rpa.ds ", |
176714=> "rpa.er1", |
176716=> "rpa.as ", |
176720=> "rpa.la ", |
176722=> "rpa.db ", |
176724=> "rpa.mr1", |
176726=> "rpa.dt ", |
176730=> "rpa.sn ", |
176732=> "rpa.of ", |
176734=> "rpa.dc ", |
176736=> "rpa.m13", |
176740=> "rpa.m14", |
176742=> "rpa.m15", |
176744=> "rpa.ec1", |
176746=> "rpa.ec2", |
176750=> "rpa.bae", |
176752=> "rpa.cs3", |
176500=> "ti2.cs", |
176502=> "ti2.bu", |
176504=> "to2.cs", |
821,20 → 797,20
$sign = "-"; |
} |
return sprintf "$name .%s%d.", $sign, abs(2*$off); |
|
|
} elsif ($type eq "sob") { |
my $reg = ($code>>6) & 07; |
my $off = $code & 077; |
return sprintf "$name r%d,.-%d.", $reg, 2*$off; |
|
|
} elsif ($type eq "trap") { |
my $off = $code & 0377; |
return sprintf "$name %3.3o", $off; |
|
|
} elsif ($type eq "spl") { |
my $off = $code & 07; |
return sprintf "$name %d", $off; |
|
|
} elsif ($type eq "ccop") { |
my $cc = $code & 017; |
return "nop" if ($cc == 0); |
847,17 → 823,17
if ($code & 002) { $str .= $del . $name . "v", $del = "+" } |
if ($code & 001) { $str .= $del . $name . "c", $del = "+" } |
return $str; |
|
|
} elsif ($type eq "jsr") { |
my $reg = ($code>>6) & 07; |
my $dst = $code & 077; |
my $dst_str = regmod($dst); |
return "$name r$reg,$dst_str"; |
|
|
} elsif ($type eq "mark") { |
my $off = $code & 077; |
return sprintf "$name %3.3o", $off; |
|
|
} elsif ($type eq "rfpp") { |
my $reg = ($code>>6) & 03; |
my $dst = $code & 077; |
/tools/oskit/rsx11mp-30_rp/.cvsignore
File deleted
/tools/oskit/rsx11mp-30_rp/rsx11mp-30_rp_boot.tcl
File deleted
/tools/oskit/rsx11mp-30_rp/rsx11mp-30_rp_boot.scmd
File deleted
tools/oskit/rsx11mp-30_rp
Property changes :
Deleted: svn:ignore
## -1,38 +0,0 ##
-*.dep_ghdl
-*.dep_isim
-*.dep_xst
-work-obj93.cf
-*.vcd
-*.ghw
-*.sav
-*.tmp
-*.exe
-ise
-xflow.his
-*.ngc
-*.ncd
-*.pcf
-*.bit
-*.msk
-isim
-isim.log
-isim.wdb
-fuse.log
-*_[sft]sim.vhd
-*_tsim.sdf
-*_xst.log
-*_tra.log
-*_twr.log
-*_map.log
-*_par.log
-*_tsi.log
-*_pad.log
-*_bgn.log
-*_svn.log
-*_sum.log
-*_[dsft]sim.log
-*.dat
-*.dsk
-*.log
-*license.txt
-*license.pdf
Index: tools/oskit/211bsd_rp/211bsd_rp_boot.tcl
===================================================================
--- tools/oskit/211bsd_rp/211bsd_rp_boot.tcl (revision 30)
+++ tools/oskit/211bsd_rp/211bsd_rp_boot.tcl (nonexistent)
@@ -1,28 +0,0 @@
-# $Id: 211bsd_rp_boot.tcl 679 2015-05-13 17:38:46Z mueller $
-#
-# Setup file for 211bsd RP06 based system
-#
-# Usage:
-#
-# console_starter -d DL0 &
-# console_starter -d DL1 &
-# ti_w11 -xxx @211bsd_rp_boot.tcl ( -xxx depends on sim or fpga connect)
-#
-
-# setup w11 cpu
-puts [rlw]
-
-# setup tt,lp (211bsd uses parity -> use 7 bit mode)
-rw11::setup_tt "cpu0" {to7bit 1}
-rw11::setup_lp
-
-# mount disks
-cpu0rpa0 set type rp06
-cpu0rpa1 set type rp06
-
-cpu0rpa0 att 211bsd_rp.dsk
-
-# and boot
-rw11::cpumon
-rw11::cpucons
-cpu0 boot rpa0
Index: tools/oskit/211bsd_rp/README_211bsd_rpset.txt
===================================================================
--- tools/oskit/211bsd_rp/README_211bsd_rpset.txt (revision 30)
+++ tools/oskit/211bsd_rp/README_211bsd_rpset.txt (nonexistent)
@@ -1,134 +0,0 @@
-# $Id: README_211bsd_rpset.txt 680 2015-05-14 13:29:46Z mueller $
-
-Notes on oskit: 2.11BSD system on a RP06 volume
-
- Table of content:
-
- 1. General remarks
- 2. Installation
- 3. Usage
-
-1. General remarks ---------------------------------------------------
-
- See notes on
-
- 1. I/O emulation setup
- 2. FPGA Board setup
- 3. Rlink and Backend Server setup
- 4. Legal terms
-
- in $RETROBASE/doc/w11a_os_guide.txt
-
-2. Installation ------------------------------------------------------
-
- - A disk set is available from
- http://www.retro11.de/data/oc_w11/oskits/211bsd_rpset.tgz
- Download, unpack and copy the disk images (*.dsk), e.g.
-
- cd $RETROBASE/tools/oskit/211bsd_rp/
- wget http://www.retro11.de/data/oc_w11/oskits/211bsd_rpset.tgz
- tar -xzf 211bsd_rpset.tgz
-
-3. Usage -------------------------------------------------------------
-
- - Start backend server and boot system (see section 3 in w11a_os_guide.txt)
- boot script: 211bsd_rp_boot.tcl
- example: ti_w11 @211bsd_rp_boot.tcl
- where is the proper option set for the board.
-
- - Hit in the xterm window to connnect to backend server.
- The boot dialog in the console xterm window will look like
- (required input is in {..}, with {} denoting a carriage return:
-
- 70Boot from xp(0,0,0) at 0176700
- : {}
- : xp(0,0,0)unix
- Boot: bootdev=05000 bootcsr=0176700
-
- 2.11 BSD UNIX #9: Wed Dec 10 06:24:37 PST 2008
- root@curly.2bsd.com:/usr/src/sys/RETRONFPNW
-
- attaching lo0
-
- phys mem = 3932160
- avail mem = 3461952
- user mem = 307200
-
- January 3 23:00:35 init: configure system
-
- dz ? csr 160100 vector 310 skipped: No CSR.
- lp 0 csr 177514 vector 200 attached
- rk 0 csr 177400 vector 220 attached
- rl 0 csr 174400 vector 160 attached
- tm ? csr 172520 vector 224 skipped: No CSR.
- xp 0 csr 176700 vector 254 attached
- cn 1 csr 176500 vector 300 attached
- erase, kill ^U, intr ^C
-
- In first '#' prompt the system is in single-user mode. Just enter a ^D
- to continue the system startup to multi-user mode:
-
- #^D
- Fast boot ... skipping disk checks
- checking quotas: done.
- Assuming NETWORKING system ...
- ifconfig: ioctl (SIOCGIFFLAGS): no such interface
- add host curly.2bsd.com: gateway localhost.2bsd.com
- add net default: gateway 206.139.202.1: Network is unreachable
- starting system logger
- checking for core dump...
- preserving editor files
- clearing /tmp
- standard daemons: update cron accounting.
- starting network daemons: inetd printer.
- January 3 23:00:47 lpd[76]: /dev/ttyS5: No such file or directory
- starting local daemons:Sat Jan 3 23:00:47 PST 2009
- January 3 23:00:47 init: kernel security level changed from 0 to 1
- January 3 23:00:49 getty: /dev/tty04: Device not configured
- January 3 23:00:49 getty: /dev/tty03: Device not configured
- January 3 23:00:49 getty: /dev/tty00: Device not configured
- January 3 23:00:49 getty: /dev/tty01: Device not configured
- January 3 23:00:49 getty: /dev/tty02: Device not config
-
- 2.11 BSD UNIX (curly.2bsd.com) (console)
-
- login:
-
- The login prompt is sometimes mangled with the 'Device not configured'
- system messages, if its not visible just hit to get a fresh one.
-
- login: {root}
- erase, kill ^U, intr ^C
-
- Now the system is in multi-user mode, daemons runnng. You can explore
- the system, e.g. with a 'pstat -T' or a 'mount' command. The second
- xterm can be activated too, it will connect to a second emulated DL11.
- At the end is important to shutdown properly with a 'halt':
-
- # {pstat -T}
- 7/186 files
- 40/208 inodes
- 11/150 processes
- 6/ 46 texts active, 31 used
- 2/135 swapmap entries, 420 kB used, 2139 kB free, 2133 kB max
- 34/150 coremap entries, 2906 kB free, 2818 kB max
- 1/ 10 ub_map entries, 10 free, 10 max
- # {mount}
- /dev/xp0a on /
- /dev/xp0c on /usr
- # {halt}
- syncing disks... done
- halting
-
- While the system was running the server process display the
- cpumon>
- prompt. When the w11 has halted after 211bsd shutdown a message like
-
- CPU down attention
- Processor registers and status:
- Processor registers and status:
- PS: 030350 cm,pm=k,u s,p,t=0,7,0 NZVC=1000 rust: 01 HALTed
- R0: 177560 R1: 010330 R2: 056172 R3: 000010
- R4: 005000 R5: 147510 SP: 147466 PC: 000014
-
- will be visible. Now the server process can be stopped with ^D.
Index: tools/oskit/211bsd_rp/211bsd_rp_boot.scmd
===================================================================
--- tools/oskit/211bsd_rp/211bsd_rp_boot.scmd (revision 30)
+++ tools/oskit/211bsd_rp/211bsd_rp_boot.scmd (nonexistent)
@@ -1,24 +0,0 @@
-; $Id: 211bsd_rp_boot.scmd 666 2015-04-12 21:17:54Z mueller $
-;
-; Setup file for 211bsd RP06 based system
-;
-; Usage:
-;
-; pdp11 211bsd_rp_boot.scmd
-;
-do ../../simh/setup_w11a_max.scmd
-set tto 7b
-set dlo0 7b
-;
-set rp0 rp06
-set rp1 rp06
-;
-set rl0 rl02
-set rl1 rl02
-set rl2 rl02
-set rl3 rl02
-;
-att rp0 211bsd_rp.dsk
-att rk6 rk_home.dsk
-;
-boo rp0
Index: tools/oskit/211bsd_rp/.cvsignore
===================================================================
--- tools/oskit/211bsd_rp/.cvsignore (revision 30)
+++ tools/oskit/211bsd_rp/.cvsignore (nonexistent)
@@ -1,5 +0,0 @@
-*.dat
-*.dsk
-*.log
-*license.txt
-*license.pdf
Index: tools/oskit/211bsd_rp
===================================================================
--- tools/oskit/211bsd_rp (revision 30)
+++ tools/oskit/211bsd_rp (nonexistent)
tools/oskit/211bsd_rp
Property changes :
Deleted: svn:ignore
## -1,38 +0,0 ##
-*.dep_ghdl
-*.dep_isim
-*.dep_xst
-work-obj93.cf
-*.vcd
-*.ghw
-*.sav
-*.tmp
-*.exe
-ise
-xflow.his
-*.ngc
-*.ncd
-*.pcf
-*.bit
-*.msk
-isim
-isim.log
-isim.wdb
-fuse.log
-*_[sft]sim.vhd
-*_tsim.sdf
-*_xst.log
-*_tra.log
-*_twr.log
-*_map.log
-*_par.log
-*_tsi.log
-*_pad.log
-*_bgn.log
-*_svn.log
-*_sum.log
-*_[dsft]sim.log
-*.dat
-*.dsk
-*.log
-*license.txt
-*license.pdf
Index: tools/oskit/xxdp_rl/README_xxdp_rlset.txt
===================================================================
--- tools/oskit/xxdp_rl/README_xxdp_rlset.txt (revision 30)
+++ tools/oskit/xxdp_rl/README_xxdp_rlset.txt (revision 29)
@@ -1,4 +1,4 @@
-# $Id: README_xxdp_rlset.txt 680 2015-05-14 13:29:46Z mueller $
+# $Id: README_xxdp_rlset.txt 652 2015-02-28 12:18:08Z mueller $
Notes on oskit: XXDP V2.2 and V2.5 system on RL02 volumes
@@ -38,7 +38,7 @@
or on w11a
ti_w11 @xxdp22_rl_boot.tcl
ti_w11 @xxdp25_rl_boot.tcl
- where is the proper option set for the board.
+ where opt is the proper option set for the board.
- Hit in the xterm window to connect to simh or backend server.
The boot dialog in the console xterm window will look like
/tools/oskit/211bsd_rl/README_211bsd_rlset.txt
1,4 → 1,4
# $Id: README_211bsd_rlset.txt 680 2015-05-14 13:29:46Z mueller $ |
# $Id: README_211bsd_rlset.txt 633 2015-01-11 22:58:48Z mueller $ |
|
Notes on oskit: 2.11BSD system on RL02 volumes |
|
33,8 → 33,7
|
- Start backend server and boot system (see section 3 in w11a_os_guide.txt) |
boot script: 211bsd_rl_boot.tcl |
example: ti_w11 <opt> @211bsd_rl_boot.tcl |
where <opt> is the proper option set for the board. |
example: ti_w11 -u @211bsd_rl_boot.tcl |
|
- Hit <ENTER> in the xterm window to connnect to backend server. |
The boot dialog in the console xterm window will look like |
56,10 → 55,10
|
dz ? csr 160100 vector 310 skipped: No CSR. |
lp 0 csr 177514 vector 200 attached |
rk 0 csr 177400 vector 220 attached |
rk ? csr 177400 vector 220 didn't interrupt. |
rl 0 csr 174400 vector 160 attached |
tm ? csr 172520 vector 224 skipped: No CSR. |
xp 0 csr 176700 vector 254 attached |
xp ? csr 176700 vector 254 skipped: No CSR. |
cn 1 csr 176500 vector 300 attached |
erase, kill ^U, intr ^C |
|
/tools/oskit/rt11-53_rl/README_rt11-53_rlset.txt
29,8 → 29,7
- Start them in simulator |
pdp11 rt11-53_rl_boot.scmd |
or ONLY IF YOU HAVE A VALID LICENSE on w11a |
ti_w11 <opt> @rt11-53_rl_boot.tcl |
where <opt> is the proper option set for the board. |
ti_w11 -u @rt11-53_rl_boot.tcl |
|
- Hit <ENTER> in the xterm window to connect to simh or backend server. |
The boot dialog in the console xterm window will look like |
/tools/oskit/rt11-40_rk/README_rt11-40_rkset.txt
1,4 → 1,4
# $Id: README_rt11-40_rkset.txt 680 2015-05-14 13:29:46Z mueller $ |
# $Id: README_rt11-40_rkset.txt 558 2014-06-01 22:20:51Z mueller $ |
|
Notes on oskit: RT-11 V4.0 system on RK05 volumes |
|
29,8 → 29,7
- Start them in simulator |
pdp11 rt11-40_rk_boot.scmd |
or ONLY IF YOU HAVE A VALID LICENSE on w11a |
ti_w11 <opt> @rt11-40_rk_boot.tcl |
where <opt> is the proper option set for the board. |
ti_w11 -u @rt11-40_rk_boot.tcl |
|
- Hit <ENTER> in the xterm window to connect to simh or backend server. |
The boot dialog in the console xterm window will look like |
/tools/oskit/unix-v5_rk/README_unix_v5_rkset.txt
1,4 → 1,4
# $Id: README_unix_v5_rkset.txt 680 2015-05-14 13:29:46Z mueller $ |
# $Id: README_unix_v5_rkset.txt 558 2014-06-01 22:20:51Z mueller $ |
|
Notes on oskit: Unix V5 system on RK05 volumes |
|
33,8 → 33,7
|
- Start backend server and boot system (see section 3 in w11a_os_guide.txt) |
boot script: uv5_rk_boot.tcl |
example: ti_w11 <opt> @uv5_rk_boot.tcl |
where <opt> is the proper option set for the board. |
example: ti_w11 -u @uv5_rk_boot.tcl |
|
- Hit <ENTER> in the xterm window to connect to backend server. |
The boot dialog in the console xterm window will look like |
/tools/oskit/211bsd_rk/README_211bsd_rkset.txt
1,4 → 1,4
# $Id: README_211bsd_rkset.txt 680 2015-05-14 13:29:46Z mueller $ |
# $Id: README_211bsd_rkset.txt 558 2014-06-01 22:20:51Z mueller $ |
|
Notes on oskit: 2.11BSD system on RK05 volumes |
|
33,8 → 33,7
|
- Start backend server and boot system (see section 3 in w11a_os_guide.txt) |
boot script: 211bsd_rk_boot.tcl |
example: ti_w11 <opt> @211bsd_rk_boot.tcl |
where <opt> is the proper option set for the board. |
example: ti_w11 -u @211bsd_rk_boot.tcl |
|
- Hit <ENTER> in the xterm window to connnect to backend server. |
The boot dialog in the console xterm window will look like |
56,10 → 55,10
|
dz ? csr 160100 vector 310 skipped: No CSR. |
lp 0 csr 177514 vector 200 attached |
rk 0 csr 177400 vector 220 attached |
rl 0 csr 174400 vector 160 attached |
rk ? csr 177400 vector 220 didn't interrupt. |
rl ? csr 174400 vector 160 skipped: No CSR. |
tm ? csr 172520 vector 224 skipped: No CSR. |
xp 0 csr 176700 vector 254 attached |
xp ? csr 176700 vector 254 skipped: No CSR. |
cn 1 csr 176500 vector 300 attached |
erase, kill ^U, intr ^C |
|
/tools/oskit/rsx11m-31_rk/README_rsx11m-31_rkset.txt
1,4 → 1,4
# $Id: README_rsx11m-31_rkset.txt 680 2015-05-14 13:29:46Z mueller $ |
# $Id: README_rsx11m-31_rkset.txt 558 2014-06-01 22:20:51Z mueller $ |
|
Notes on oskit: RSX-11M V3.1 system on RK05 volumes |
|
29,8 → 29,7
- Start them in simulator |
pdp11 rsx11m-31_rk_boot.scmd |
or ONLY IF YOU HAVE A VALID LICENSE on w11a |
ti_w11 <opt> @rsx11m-31_rk_boot.tcl |
where <opt> is the proper option set for the board. |
ti_w11 -u @rsx11m-31_rk_boot.tcl |
|
- Hit <ENTER> in the xterm window to connect to simh or backend server. |
The boot dialog in the console xterm window will look like |
/tools/oskit/rsx11m-40_rk/README_rsx11m-40_rkset.txt
1,4 → 1,4
# $Id: README_rsx11m-40_rkset.txt 680 2015-05-14 13:29:46Z mueller $ |
# $Id: README_rsx11m-40_rkset.txt 580 2014-08-10 15:47:10Z mueller $ |
|
Notes on oskit: RSX-11M V4.0 system on RK05 volumes |
|
29,8 → 29,7
- Start them in simulator |
pdp11 rsx11m-40_rk_boot.scmd |
or ONLY IF YOU HAVE A VALID LICENSE on w11a |
ti_w11 <opt> @rsx11m-40_rk_boot.tcl |
where <opt> is the proper option set for the board. |
ti_w11 -u @rsx11m-40_rk_boot.tcl |
|
- Hit <ENTER> in the xterm window to connect to simh or backend server. |
The boot dialog in the console xterm window will look like |
/tools/dox/w11_vhd_all.Doxyfile
5,7 → 5,7
#--------------------------------------------------------------------------- |
DOXYFILE_ENCODING = UTF-8 |
PROJECT_NAME = "w11 - vhd" |
PROJECT_NUMBER = 0.65 |
PROJECT_NUMBER = 0.64 |
PROJECT_BRIEF = "W11 CPU core and support modules" |
PROJECT_LOGO = |
OUTPUT_DIRECTORY = $(RETRODOXY)/w11/vhd |
/tools/dox/w11_cpp.Doxyfile
5,7 → 5,7
#--------------------------------------------------------------------------- |
DOXYFILE_ENCODING = UTF-8 |
PROJECT_NAME = "w11 - cpp" |
PROJECT_NUMBER = 0.65 |
PROJECT_NUMBER = 0.64 |
PROJECT_BRIEF = "Backend server for Rlink and w11" |
PROJECT_LOGO = |
OUTPUT_DIRECTORY = $(RETRODOXY)/w11/cpp |
/tools/dox/w11_tcl.Doxyfile
5,7 → 5,7
#--------------------------------------------------------------------------- |
DOXYFILE_ENCODING = UTF-8 |
PROJECT_NAME = "w11 - tcl" |
PROJECT_NUMBER = 0.65 |
PROJECT_NUMBER = 0.64 |
PROJECT_BRIEF = "Backend server for Rlink and w11" |
PROJECT_LOGO = |
OUTPUT_DIRECTORY = $(RETRODOXY)/w11/tcl |
/tools/tbench/test_rhrp_basics.tcl
File deleted
/tools/tbench/test_rhrp_func_reg.tcl
File deleted
/tools/tbench/test_rhrp_regs.tcl
File deleted
/tools/tbench/test_rhrp_int.tcl
File deleted
/tools/tbench/rhrp_all.dat
File deleted
/tools/tbench/test_cp_ibrbasics.tcl
1,4 → 1,4
# $Id: test_cp_ibrbasics.tcl 676 2015-05-09 16:31:54Z mueller $ |
# $Id: test_cp_ibrbasics.tcl 621 2014-12-26 21:20:05Z mueller $ |
# |
# Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
13,7 → 13,7
# |
|
# ---------------------------------------------------------------------------- |
rlc log "test_cp_ibrbasics: Test very basic ibus interface gymnastics --------" |
rlc log "test_cp_ibrbasics: Test very basic ibus interface gymnastics" |
|
rlc log " write/read ibus space (MMU SAR SM I regs) via bwm/brm" |
$cpu cp -wal 0172240 \ |
/tools/tbench/test_cp_membasics.tcl
1,4 → 1,4
# $Id: test_cp_membasics.tcl 676 2015-05-09 16:31:54Z mueller $ |
# $Id: test_cp_membasics.tcl 621 2014-12-26 21:20:05Z mueller $ |
# |
# Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
14,7 → 14,7
# |
|
# ---------------------------------------------------------------------------- |
rlc log "test_cp_membasics: Test very basic memory interface gymnastics ------" |
rlc log "test_cp_membasics: Test very basic memory interface gymnastics" |
|
# -------------------------------------------------------------------- |
rlc log " write/read address register" |
/tools/tbench/test_cp_psw.tcl
1,4 → 1,4
# $Id: test_cp_psw.tcl 676 2015-05-09 16:31:54Z mueller $ |
# $Id: test_cp_psw.tcl 621 2014-12-26 21:20:05Z mueller $ |
# |
# Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
18,7 → 18,7
# |
|
# ---------------------------------------------------------------------------- |
rlc log "test_cp_psw: test psw access via all methods ------------------------" |
rlc log "test_cp_psw: test psw access via all methods" |
rlc log " write/read via cp" |
foreach w { 000000 000017 } { |
$cpu cp -wps $w \ |
/tools/tbench/test_cp_gpr.tcl
1,4 → 1,4
# $Id: test_cp_gpr.tcl 676 2015-05-09 16:31:54Z mueller $ |
# $Id: test_cp_gpr.tcl 552 2014-03-02 23:02:00Z mueller $ |
# |
# Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
14,7 → 14,7
# |
|
# ---------------------------------------------------------------------------- |
rlc log "test_cp_gpr: test cp access to general purpose registers ------------" |
rlc log "test_cp_gpr: test cp access to general purpose registers" |
rlc log " write set 0" |
$cpu cp -wps 0000000 |
$cpu cp -wr0 0000001 \ |
/tools/tbench/test_cp_cpubasics.tcl
1,24 → 1,21
# $Id: test_cp_cpubasics.tcl 676 2015-05-09 16:31:54Z mueller $ |
# $Id: test_cp_cpubasics.tcl 552 2014-03-02 23:02:00Z mueller $ |
# |
# Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-05-09 676 1.1 w11a start/stop/suspend overhaul |
# 2013-03-31 502 1.0 Initial version |
# |
# Test very basic cpu interface gymnastics |
# 1. load code via ldasm |
# 2. execute code via -start, -stapc |
# 2. execute code via -start, -stapc, -continue |
# 3. single step code via -step |
# 4. verify -suspend, -resume |
# |
|
# ---------------------------------------------------------------------------- |
rlc log "test_cp_cpubasics: Test very basic cpu interface gymnastics ---------" |
rlc log " A1: start/stop/step basics --------------------------------" |
rlc log " load simple linear code via lsasm" |
rlc log "test_cp_cpubasics: Test very basic cpu interface gymnastics" |
rlc log " load code via lsasm" |
|
# |
$cpu ldasm -lst lst -sym sym { |
30,11 → 27,11
stop: |
} |
|
rlc log " read back and check" |
rlc log " read back and check" |
$cpu cp -wal $sym(start) \ |
-brm 4 -edata {0005202 0005202 0005202 0000000} |
|
rlc log " execute via -start" |
rlc log " execute via -start" |
$cpu cp -wr2 00000 \ |
-wpc $sym(start) \ |
-start |
42,7 → 39,7
$cpu cp -rr2 -edata 00003 \ |
-rpc -edata $sym(stop) |
|
rlc log " execute via -stapc" |
rlc log " execute via -stapc" |
$cpu cp -wr2 00100 \ |
-stapc $sym(start) |
$cpu wtcpu -reset 1.0 |
49,86 → 46,22
$cpu cp -rr2 -edata 00103 \ |
-rpc -edata $sym(stop) |
|
rlc log " execute via -step" |
$cpu cp -wr2 00300 \ |
-wpc $sym(start) |
$cpu cp -step \ |
-rpc -edata [expr {$sym(start)+002}] \ |
-rr2 -edata 00301 \ |
-rstat -edata 000100 |
$cpu cp -step \ |
-rpc -edata [expr {$sym(start)+004}] \ |
-rr2 -edata 00302 \ |
-rstat -edata 000100 |
$cpu cp -step \ |
-rpc -edata [expr {$sym(start)+006}] \ |
-rr2 -edata 00303 \ |
-rstat -edata 000100 |
$cpu cp -step \ |
-rpc -edata [expr {$sym(start)+010}] \ |
-rr2 -edata 00303 \ |
-rstat -edata 000020 |
|
rlc log " A2: suspend/resume basics; cpugo,cpususp flags ------------" |
# define tmpproc for r2 increment checks |
proc tmpproc_checkr2inc {val} { |
set emsg "" |
if {$val == 0} { |
set emsg "FAIL: r2 change zero" |
rlc errcnt -inc |
} |
rlc log -bare ".. r2 increment $val $emsg" |
} |
|
# |
rlc log " load simple loop code via lsasm" |
$cpu ldasm -lst lst -sym sym { |
. = 1000 |
start: inc r2 |
br start |
stop: |
} |
|
set statgo [regbld rw11::STAT cpugo] |
set statgosu [regbld rw11::STAT cpususp cpugo] |
|
rlc log " execute via -stapc, check cpugo and that r2 increments" |
$cpu cp -wr2 00000 \ |
-stapc $sym(start) \ |
-rr2 rr2_1 -estat $statgo \ |
-rr2 rr2_2 -estat $statgo |
tmpproc_checkr2inc $rr2_1 |
tmpproc_checkr2inc [expr {$rr2_2 - $rr2_1}] |
|
rlc log " suspend, check cpususp=1 and that r2 doesn't increment" |
$cpu cp -suspend \ |
-wr2 00000 \ |
-rr2 -edata 0 -estat $statgosu \ |
-rr2 -edata 0 -estat $statgosu |
|
rlc log " resume, check cpususp=0 and that r2 increments again" |
$cpu cp -resume \ |
-rr2 rr2_1 -estat $statgo \ |
-rr2 rr2_2 -estat $statgo |
tmpproc_checkr2inc $rr2_1 |
tmpproc_checkr2inc [expr {$rr2_2 - $rr2_1}] |
|
rlc log " suspend than step, two steps should inc r2 once" |
$cpu cp -suspend \ |
-wr2 00000 \ |
-step \ |
-step \ |
-rr2 -edata 1 \ |
-step \ |
-step \ |
-rr2 -edata 2 |
|
rlc log " stop while suspended, check cpugo=0,cpususp=1,attn=1; harvest attn" |
$cpu cp -stop -estat [regbld rw11::STAT cpususp attn] |
rlc log " execute via -continue" |
$cpu cp -wr2 00200 \ |
-wpc $sym(start) \ |
-continue |
$cpu wtcpu -reset 1.0 |
$cpu cp -rr2 -edata 00203 \ |
-rpc -edata $sym(stop) |
|
rlc log " creset, check cpususp=0" |
# Note: creset still has cpususp stat flag set because it clears with one |
# cycle delay. So do -estat after next command |
$cpu cp -creset \ |
-rr2 -estat 0 |
rlc log " execute via -step" |
$cpu cp -wr2 00300 \ |
-wpc $sym(start) |
$cpu cp -step -rpc -edata [expr {$sym(start)+002}] \ |
-rr2 -edata 00301 -rstat -edata 000100 |
$cpu cp -step -rpc -edata [expr {$sym(start)+004}] \ |
-rr2 -edata 00302 -rstat -edata 000100 |
$cpu cp -step -rpc -edata [expr {$sym(start)+006}] \ |
-rr2 -edata 00303 -rstat -edata 000100 |
$cpu cp -step -rpc -edata [expr {$sym(start)+010}] \ |
-rr2 -edata 00303 -rstat -edata 000030 |
/tools/asm-11/lib/defs_rk.mac
File deleted
/tools/asm-11/lib/kproct.mac
File deleted
/tools/asm-11/lib/defs_bits.mac
File deleted
/tools/asm-11/lib/defs_rp.mac
File deleted
/tools/asm-11/lib/kprfmt.mac
File deleted
/tools/asm-11/lib/kprstr.mac
File deleted
/tools/asm-11/lib/vec_cpucatch.mac
File deleted
/tools/asm-11/lib/kprdec.mac
File deleted
/tools/asm-11/lib/defs_cpu.mac
File deleted
/tools/asm-11/lib/kprchr.mac
File deleted
tools/asm-11/lib
Property changes :
Deleted: svn:ignore
## -1,33 +0,0 ##
-*.dep_ghdl
-*.dep_isim
-*.dep_xst
-work-obj93.cf
-*.vcd
-*.ghw
-*.sav
-*.tmp
-*.exe
-ise
-xflow.his
-*.ngc
-*.ncd
-*.pcf
-*.bit
-*.msk
-isim
-isim.log
-isim.wdb
-fuse.log
-*_[sft]sim.vhd
-*_tsim.sdf
-*_xst.log
-*_tra.log
-*_twr.log
-*_map.log
-*_par.log
-*_tsi.log
-*_pad.log
-*_bgn.log
-*_svn.log
-*_sum.log
-*_[dsft]sim.log
Index: rtl/ibus/ibdr_rhrp.vbom
===================================================================
--- rtl/ibus/ibdr_rhrp.vbom (revision 30)
+++ rtl/ibus/ibdr_rhrp.vbom (nonexistent)
@@ -1,9 +0,0 @@
-# libs
-../vlib/slvtypes.vhd
-../vlib/memlib/memlib.vhd
-iblib.vhd
-# components
-[sim]../vlib/memlib/ram_1swar_gen.vbom
-[xst,vsyn]../vlib/memlib/ram_1swar_gen_unisim.vbom
-# design
-ibdr_rhrp.vhd
Index: rtl/ibus/ibdr_rhrp.vhd
===================================================================
--- rtl/ibus/ibdr_rhrp.vhd (revision 30)
+++ rtl/ibus/ibdr_rhrp.vhd (nonexistent)
@@ -1,1436 +0,0 @@
--- $Id: ibdr_rhrp.vhd 680 2015-05-14 13:29:46Z mueller $
---
--- Copyright 2015- by Walter F.J. Mueller
---
--- This program is free software; you may redistribute and/or modify it under
--- the terms of the GNU General Public License as published by the Free
--- Software Foundation, either version 2, or at your option any later version.
---
--- This program is distributed in the hope that it will be useful, but
--- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
--- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
--- for complete details.
---
-------------------------------------------------------------------------------
--- Module Name: ibdr_rhrp - syn
--- Description: ibus dev(rem): RHRP
---
--- Dependencies: ram_1swar_gen
--- Test bench: -
--- Target Devices: generic
--- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31
---
--- Synthesized (xst):
--- Date Rev ise Target flop lutl lutm slic t peri
--- 2015-05-14 680 14.7 131013 xc6slx16-2 211 408 8 131 s 8.8
--- 2015-04-06 664 14.7 131013 xc6slx16-2 177 331 8 112 s 8.7
---
--- Revision History:
--- Date Rev Version Comment
--- 2015-05-14 680 1.0 Initial version
--- 2015-03-15 658 0.1 First draft
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.slvtypes.all;
-use work.memlib.all;
-use work.iblib.all;
-
--- ----------------------------------------------------------------------------
-entity ibdr_rhrp is -- ibus dev(rem): RH+RP
- -- fixed address: 176700
- port (
- CLK : in slbit; -- clock
- CE_USEC : in slbit; -- usec pulse
- BRESET : in slbit; -- ibus reset
- ITIMER : in slbit; -- instruction timer
- RB_LAM : out slbit; -- remote attention
- IB_MREQ : in ib_mreq_type; -- ibus request
- IB_SRES : out ib_sres_type; -- ibus response
- EI_REQ : out slbit; -- interrupt request
- EI_ACK : in slbit -- interrupt acknowledge
- );
-
- -- by default xst uses a binary encoding for the main fsm.
- -- that give quite sub-optimal results, so force one-hot
- attribute fsm_encoding : string;
- attribute fsm_encoding of ibdr_rhrp : entity is "one-hot";
-
-end entity ibdr_rhrp;
-
-architecture syn of ibdr_rhrp is
-
- constant ibaddr_rhrp : slv16 := slv(to_unsigned(8#176700#,16));
-
- -- nam rw mb rp rm storage
- constant ibaddr_cs1 : slv5 := "00000"; -- cs1 rw 0 rpcs1 rmcs1 m d,6+r
- constant ibaddr_wc : slv5 := "00001"; -- wc rw - rpwc rmwc m 0,7
- constant ibaddr_ba : slv5 := "00010"; -- ba rw - rpba rmba m 1,7
- constant ibaddr_da : slv5 := "00011"; -- da rw 5 rpda rmda m d,0
- constant ibaddr_cs2 : slv5 := "00100"; -- cs2 rw - rpcs2 rmcs2 r cs2*
- constant ibaddr_ds : slv5 := "00101"; -- ds r- 1 rpds rmds r ds*
- constant ibaddr_er1 : slv5 := "00110"; -- er1 rw 2 rper1 rmer1 r er1*
- constant ibaddr_as : slv5 := "00111"; -- as rw 4 rpas rmas r as*
- constant ibaddr_la : slv5 := "01000"; -- la r- 7 rpla rmla r sc
- constant ibaddr_db : slv5 := "01001"; -- db r? - rpdb rmdb m 2,7
- constant ibaddr_mr1 : slv5 := "01010"; -- mr1 rw 3 rpmr1 rmmr1 m d,3
- constant ibaddr_dt : slv5 := "01011"; -- dt r- 6 rpdt rmdt r dt*+map
- constant ibaddr_sn : slv5 := "01100"; -- sn r- 10 rpsn rmsn
/rtl/ibus/ibdr_rk11.vhd
1,6 → 1,6
-- $Id: ibdr_rk11.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: ibdr_rk11.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2008-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
29,7 → 29,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-01 672 1.3 BUGFIX: interrupt after dreset,seek command start |
-- 2011-11-18 427 1.2.2 now numeric_std clean |
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM; |
-- 2010-10-17 333 1.2 use ibus V2 interface |
113,15 → 112,6
constant rkmr_ibf_fdone : integer := 8; -- func done |
subtype rkmr_ibf_sdone is integer range 7 downto 0; -- seek done |
|
constant func_creset : slv3 := "000"; -- func: control reset |
constant func_write : slv3 := "001"; -- func: write |
constant func_read : slv3 := "010"; -- func: read |
constant func_wchk : slv3 := "011"; -- func: write check |
constant func_seek : slv3 := "100"; -- func: seek |
constant func_rchk : slv3 := "101"; -- func: read check |
constant func_dreset : slv3 := "110"; -- func: drive reset |
constant func_wlock : slv3 := "111"; -- func: write lock |
|
type state_type is ( |
s_idle, |
s_init |
350,7 → 340,7
|
if ibw0 = '1' then |
n.ide := IB_MREQ.din(rkcs_ibf_ide); -- mirror ide bit |
if n.ide = '0' then -- if IE set to 0 |
if n.ide = '0' then -- if IE 0 or set to 0 |
n.fireq := '0'; -- cancel all pending |
n.sireq := (others=>'0'); -- interrupt requests |
end if; |
363,23 → 353,21
n.wce := '0'; |
n.fireq := '0'; -- cancel pend. int |
|
if IB_MREQ.din(rkcs_ibf_func)=func_creset then -- control reset? |
if unsigned(IB_MREQ.din(rkcs_ibf_func))=0 then -- control reset? |
n.creset := '1'; -- handle locally |
else |
ilam := '1'; -- issue lam |
end if; |
|
if IB_MREQ.din(rkcs_ibf_func)=func_seek or -- if seek |
IB_MREQ.din(rkcs_ibf_func)=func_dreset then -- or drive reset |
n.sbusy(to_integer(unsigned(r.drsel))) := '1'; -- drive busy |
if n.ide = '1' then -- if enabled |
n.fireq := '1'; -- interrupt ! |
end if; |
if unsigned(IB_MREQ.din(rkcs_ibf_func))=4 or -- if seek |
unsigned(IB_MREQ.din(rkcs_ibf_func))=6 then -- or drive reset |
n.sbusy(to_integer(unsigned(r.drsel))) := '1'; -- set busy |
end if; |
|
end if; |
else -- GO=0 |
if r.ide='0' and n.ide='1' and -- if IDE 0->1 transition |
if r.ide = '0' and -- if ide now 0 |
IB_MREQ.din(rkcs_ibf_ide)='1' and -- and is set to 1 |
r.rdy='1' then -- and controller ready |
n.fireq := '1'; -- issue interrupt |
end if; |
/rtl/ibus/iblib.vhd
1,6 → 1,6
-- $Id: iblib.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: iblib.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2008-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
19,7 → 19,6
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-24 668 2.1 add ibd_ibmon |
-- 2010-10-23 335 2.0.1 add ib_sel; add ib_sres_or_mon |
-- 2010-10-17 333 2.0 ibus V2 interface: use aval,re,we,rmw |
-- 2010-06-11 303 1.1 added racc,cacc signals to ib_mreq_type |
29,7 → 28,6
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
|
135,19 → 133,6
); |
end component; |
|
component ibd_ibmon is -- ibus dev: ibus monitor |
generic ( |
IB_ADDR : slv16 := slv(to_unsigned(8#160000#,16)); |
AWIDTH : natural := 9); |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
IB_MREQ : in ib_mreq_type; -- ibus: request |
IB_SRES : out ib_sres_type; -- ibus: response |
IB_SRES_SUM : in ib_sres_type -- ibus: response (sum for monitor) |
); |
end component; |
|
-- |
-- components for use in test benches (not synthesizable) |
-- |
/rtl/ibus/ibdlib.vhd
1,4 → 1,4
-- $Id: ibdlib.vhd 678 2015-05-10 16:23:02Z mueller $ |
-- $Id: ibdlib.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2008-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
19,8 → 19,6
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-09 676 1.3 start/stop/suspend overhaul |
-- 2015-03-13 658 1.2.1 add rprm declaration (later renaned to rhrp) |
-- 2014-06-08 561 1.2 fix rl11 declaration |
-- 2011-11-18 427 1.1.2 now numeric_std clean |
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM; |
97,7 → 95,7
); |
end component; |
|
component ibd_kw11p is -- ibus dev(loc): KW11-P (prog clock) |
component ibd_kw11p is -- ibus dev(loc): KW11-P (line clock) |
-- fixed address: 172540 |
port ( |
CLK : in slbit; -- clock |
105,7 → 103,6
CE_MSEC : in slbit; -- msec pulse |
RESET : in slbit; -- system reset |
BRESET : in slbit; -- ibus reset |
CPUSUSP : in slbit; -- cpu suspended |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ : out slbit; -- interrupt request |
120,7 → 117,6
CE_MSEC : in slbit; -- msec pulse |
RESET : in slbit; -- system reset |
BRESET : in slbit; -- ibus reset |
CPUSUSP : in slbit; -- cpu suspended |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ : out slbit; -- interrupt request |
128,21 → 124,6
); |
end component; |
|
component ibdr_rhrp is -- ibus dev(rem): RH+RP |
-- fixed address: 174400 |
port ( |
CLK : in slbit; -- clock |
CE_USEC : in slbit; -- usec pulse |
BRESET : in slbit; -- ibus reset |
ITIMER : in slbit; -- instruction timer |
RB_LAM : out slbit; -- remote attention |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ : out slbit; -- interrupt request |
EI_ACK : in slbit -- interrupt acknowledge |
); |
end component; |
|
component ibdr_rl11 is -- ibus dev(rem): RL11 |
-- fixed address: 174400 |
port ( |
284,8 → 265,6
CE_MSEC : in slbit; -- msec pulse |
RESET : in slbit; -- reset |
BRESET : in slbit; -- ibus reset |
ITIMER : in slbit; -- instruction timer |
CPUSUSP : in slbit; -- cpu suspended |
RB_LAM : out slv16_1; -- remote attention vector |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
/rtl/ibus/ibdr_minisys.vhd
1,4 → 1,4
-- $Id: ibdr_minisys.vhd 676 2015-05-09 16:31:54Z mueller $ |
-- $Id: ibdr_minisys.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
142,7 → 142,6
CE_MSEC => CE_MSEC, |
RESET => RESET, |
BRESET => BRESET, |
CPUSUSP => '0', |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_KW11L, |
EI_REQ => EI_REQ_KW11L, |
/rtl/ibus/ibdr_maxisys.vhd
1,4 → 1,4
-- $Id: ibdr_maxisys.vhd 679 2015-05-13 17:38:46Z mueller $ |
-- $Id: ibdr_maxisys.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2009-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
17,7 → 17,6
-- |
-- Dependencies: ibd_iist |
-- ibd_kw11l |
-- ibdr_rhrp |
-- ibdr_rl11 |
-- ibdr_rk11 |
-- ibdr_dl11 |
33,7 → 32,6
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2015-04-06 664 14.7 131013 xc6slx16-2 559 1068 29 410 s 9.1 +RHRP |
-- 2015-01-04 630 14.7 131013 xc6slx16-2 388 761 20 265 s 8.0 +RL11 |
-- 2014-06-08 560 14.7 131013 xc6slx16-2 311 615 8 216 s 7.1 |
-- 2010-10-17 333 12.1 M53d xc3s1000-4 312 1058 16 617 s 10.3 |
41,13 → 39,9
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-10 678 1.3 start/stop/suspend overhaul |
-- 2015-04-06 664 1.2.3 rename RPRM to RHRP |
-- 2015-03-14 658 1.2.2 add RPRM; rearrange intmap (+rhrp,tm11,-kw11-l) |
-- use sys_conf, make most devices configurable |
-- 2015-01-04 630 1.2.1 RL11 back in |
-- 2014-06-27 565 1.2.1 temporarily hide RL11 |
-- 2014-06-08 561 1.2 add RL11 |
-- 2014-06-08 561 1.2 add rl11 |
-- 2011-11-18 427 1.1.2 now numeric_std clean |
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM |
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ |
62,15 → 56,15
-- full system setup |
-- |
-- ibbase vec pri slot attn sror device name |
-- |
-- 172540 104 ?7 17 - 1/1 KW11-P |
-- 177500 260 6 15 16 - 1/2 IIST |
-- 177546 100 6 14 15 - 1/3 KW11-L |
-- |
-- 172540 104 ?7 14 17 - 1/1 KW11-P |
-- 177500 260 6 13 16 - 1/2 IIST |
-- 177546 100 6 12 15 - 1/3 KW11-L |
-- 174510 120 5 14 9 1/4 DEUNA |
-- 176700 254 5 13 13 6 2/1 RHRP |
-- 174400 160 5 12 12 5 2/2 RL11 |
-- 177400 220 5 11 11 4 2/3 RK11 |
-- 172520 224 5 10 10 7 2/4 TM11 |
-- 176700 254 5 13 6 2/1 RH70/RP06 |
-- 174400 160 5 11 12 5 2/2 RL11 |
-- 177400 220 5 10 11 4 2/3 RK11 |
-- 172520 224 5 10 7 2/4 TM11 |
-- 160100 310? 5 9 9 3 3/1 DZ11-RX |
-- 314? 5 8 8 ^ DZ11-TX |
-- 177560 060 4 7 7 1 3/2 DL11-RX 1st |
90,7 → 84,6
use work.slvtypes.all; |
use work.iblib.all; |
use work.ibdlib.all; |
use work.sys_conf.all; |
|
-- ---------------------------------------------------------------------------- |
entity ibdr_maxisys is -- ibus(rem) full system |
100,8 → 93,6
CE_MSEC : in slbit; -- msec pulse |
RESET : in slbit; -- reset |
BRESET : in slbit; -- ibus reset |
ITIMER : in slbit; -- instruction timer |
CPUSUSP : in slbit; -- cpu suspended |
RB_LAM : out slv16_1; -- remote attention vector |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
115,12 → 106,12
architecture syn of ibdr_maxisys is |
|
constant conf_intmap : intmap_array_type := |
((8#260#,6), -- line 15 IIST |
(8#100#,6), -- line 14 KW11-L |
(8#254#,5), -- line 13 RHRP |
(8#160#,5), -- line 12 RL11 |
(8#220#,5), -- line 11 RK11 |
(8#224#,5), -- line 10 TM11 |
(intmap_init, -- line 15 |
(8#104#,6), -- line 14 KW11-P |
(8#260#,6), -- line 13 IIST |
(8#100#,6), -- line 12 KW11-L |
(8#160#,5), -- line 11 RL11 |
(8#220#,5), -- line 10 RK11 |
(8#310#,5), -- line 9 DZ11-RX |
(8#314#,5), -- line 8 DZ11-TX |
(8#060#,4), -- line 7 DL11-RX 1st |
130,11 → 121,11
(8#070#,4), -- line 3 PC11-PTR |
(8#074#,4), -- line 2 PC11-PTP |
(8#200#,4), -- line 1 LP11 |
intmap_init -- line 0 (must be unused!) |
intmap_init -- line 0 |
); |
|
signal RB_LAM_DENUA : slbit := '0'; |
signal RB_LAM_RHRP : slbit := '0'; |
signal RB_LAM_RP06 : slbit := '0'; |
signal RB_LAM_RL11 : slbit := '0'; |
signal RB_LAM_RK11 : slbit := '0'; |
signal RB_LAM_TM11 : slbit := '0'; |
148,7 → 139,7
signal IB_SRES_KW11P : ib_sres_type := ib_sres_init; |
signal IB_SRES_KW11L : ib_sres_type := ib_sres_init; |
signal IB_SRES_DEUNA : ib_sres_type := ib_sres_init; |
signal IB_SRES_RHRP : ib_sres_type := ib_sres_init; |
signal IB_SRES_RP06 : ib_sres_type := ib_sres_init; |
signal IB_SRES_RL11 : ib_sres_type := ib_sres_init; |
signal IB_SRES_RK11 : ib_sres_type := ib_sres_init; |
signal IB_SRES_TM11 : ib_sres_type := ib_sres_init; |
171,7 → 162,7
signal EI_REQ_KW11P : slbit := '0'; |
signal EI_REQ_KW11L : slbit := '0'; |
signal EI_REQ_DEUNA : slbit := '0'; |
signal EI_REQ_RHRP : slbit := '0'; |
signal EI_REQ_RP06 : slbit := '0'; |
signal EI_REQ_RL11 : slbit := '0'; |
signal EI_REQ_RK11 : slbit := '0'; |
signal EI_REQ_TM11 : slbit := '0'; |
189,7 → 180,7
signal EI_ACK_KW11P : slbit := '0'; |
signal EI_ACK_KW11L : slbit := '0'; |
signal EI_ACK_DEUNA : slbit := '0'; |
signal EI_ACK_RHRP : slbit := '0'; |
signal EI_ACK_RP06 : slbit := '0'; |
signal EI_ACK_RL11 : slbit := '0'; |
signal EI_ACK_RK11 : slbit := '0'; |
signal EI_ACK_TM11 : slbit := '0'; |
210,7 → 201,7
|
begin |
|
IIST: if sys_conf_ibd_iist generate |
IIST: if true generate |
begin |
I0 : ibd_iist |
port map ( |
241,7 → 232,6
CE_MSEC => CE_MSEC, |
RESET => RESET, |
BRESET => BRESET, |
CPUSUSP => CPUSUSP, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_KW11L, |
EI_REQ => EI_REQ_KW11L, |
248,24 → 238,8
EI_ACK => EI_ACK_KW11L |
); |
|
RHRP: if sys_conf_ibd_rhrp generate |
RL11: if true generate |
begin |
I0 : ibdr_rhrp |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
BRESET => BRESET, |
ITIMER => ITIMER, |
RB_LAM => RB_LAM_RHRP, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_RHRP, |
EI_REQ => EI_REQ_RHRP, |
EI_ACK => EI_ACK_RHRP |
); |
end generate RHRP; |
|
RL11: if sys_conf_ibd_rl11 generate |
begin |
I0 : ibdr_rl11 |
port map ( |
CLK => CLK, |
279,7 → 253,7
); |
end generate RL11; |
|
RK11: if sys_conf_ibd_rk11 generate |
RK11: if true generate |
begin |
I0 : ibdr_rk11 |
port map ( |
309,7 → 283,7
EI_ACK_TX => EI_ACK_DL11TX_0 |
); |
|
DL11_1: if sys_conf_ibd_dl11_1 generate |
DL11_1: if true generate |
begin |
I0 : ibdr_dl11 |
generic map ( |
329,7 → 303,7
); |
end generate DL11_1; |
|
PC11: if sys_conf_ibd_pc11 generate |
PC11: if true generate |
begin |
I0 : ibdr_pc11 |
port map ( |
346,7 → 320,7
); |
end generate PC11; |
|
LP11: if sys_conf_ibd_lp11 generate |
LP11: if true generate |
begin |
I0 : ibdr_lp11 |
port map ( |
381,7 → 355,7
|
SRES_OR_2 : ib_sres_or_4 |
port map ( |
IB_SRES_1 => IB_SRES_RHRP, |
IB_SRES_1 => IB_SRES_RP06, |
IB_SRES_2 => IB_SRES_RL11, |
IB_SRES_3 => IB_SRES_RK11, |
IB_SRES_4 => IB_SRES_TM11, |
424,12 → 398,11
EI_VECT => EI_VECT |
); |
|
EI_REQ(15) <= EI_REQ_IIST; |
EI_REQ(14) <= EI_REQ_KW11L; |
EI_REQ(13) <= EI_REQ_RHRP; |
EI_REQ(12) <= EI_REQ_RL11; |
EI_REQ(11) <= EI_REQ_RK11; |
EI_REQ(10) <= EI_REQ_TM11; |
EI_REQ(14) <= EI_REQ_KW11P; |
EI_REQ(13) <= EI_REQ_IIST; |
EI_REQ(12) <= EI_REQ_KW11L; |
EI_REQ(11) <= EI_REQ_RL11; |
EI_REQ(10) <= EI_REQ_RK11; |
EI_REQ( 9) <= EI_REQ_DZ11RX; |
EI_REQ( 8) <= EI_REQ_DZ11TX; |
EI_REQ( 7) <= EI_REQ_DL11RX_0; |
440,12 → 413,11
EI_REQ( 2) <= EI_REQ_PC11PTP; |
EI_REQ( 1) <= EI_REQ_LP11; |
|
EI_ACK_IIST <= EI_ACK(15); |
EI_ACK_KW11L <= EI_ACK(14); |
EI_ACK_RHRP <= EI_ACK(13); |
EI_ACK_RL11 <= EI_ACK(12); |
EI_ACK_RK11 <= EI_ACK(11); |
EI_ACK_TM11 <= EI_ACK(10); |
EI_ACK_KW11P <= EI_ACK(14); |
EI_ACK_IIST <= EI_ACK(13); |
EI_ACK_KW11L <= EI_ACK(12); |
EI_ACK_RL11 <= EI_ACK(11); |
EI_ACK_RK11 <= EI_ACK(10); |
EI_ACK_DZ11RX <= EI_ACK( 9); |
EI_ACK_DZ11TX <= EI_ACK( 8); |
EI_ACK_DL11RX_0 <= EI_ACK( 7); |
461,7 → 433,7
RB_LAM( 9) <= RB_LAM_DENUA; |
RB_LAM( 8) <= RB_LAM_LP11; |
RB_LAM( 7) <= RB_LAM_TM11; |
RB_LAM( 6) <= RB_LAM_RHRP; |
RB_LAM( 6) <= RB_LAM_RP06; |
RB_LAM( 5) <= RB_LAM_RL11; |
RB_LAM( 4) <= RB_LAM_RK11; |
RB_LAM( 3) <= RB_LAM_DZ11; |
/rtl/ibus/ibdr_maxisys.vbom
2,11 → 2,9
../vlib/slvtypes.vhd |
iblib.vhd |
ibdlib.vhd |
${sys_conf := sys_conf.vhd} |
# components |
ibd_iist.vbom |
ibd_kw11l.vbom |
ibdr_rhrp.vbom |
ibdr_rl11.vbom |
ibdr_rk11.vbom |
ibdr_dl11.vbom |
/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd
1,4 → 1,4
-- $Id: sys_tst_rlink_b3.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: sys_tst_rlink_b3.vhd 640 2015-02-01 09:56:53Z mueller $ |
-- |
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
34,7 → 34,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-11 666 1.0.1 rearrange XON handling |
-- 2015-01-16 636 1.0 Initial version (derived from sys_tst_rlink_n3) |
------------------------------------------------------------------------------ |
-- Usage of Basys 3 Switches, Buttons, LEDs: |
194,9 → 193,7
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
ENAPIN_RBMON => sbcntl_sbf_rbmon, |
CDWIDTH => 15, |
CDINIT => sys_conf_ser2rri_cdinit, |
RBMON_AWIDTH => 0, |
RBMON_RBADDR => x"ffe8") |
CDINIT => sys_conf_ser2rri_cdinit) |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
204,7 → 201,7
CE_INT => CE_MSEC, |
RESET => RESET, |
ENAXON => SWI(1), |
ESCFILL => '0', |
ENAESC => SWI(1), |
RXSD => RXD, |
TXSD => TXD, |
CTS_N => '0', |
/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd
1,6 → 1,6
-- $Id: sys_tst_rlink_n2.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: sys_tst_rlink_n2.vhd 614 2014-12-20 15:00:45Z mueller $ |
-- |
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2010-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
40,7 → 40,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-11 666 1.4.1 rearrange XON handling |
-- 2014-11-09 603 1.4 use new rlink v4 iface and 4 bit STAT |
-- 2014-08-15 583 1.3 rb_mreq addr now 16 bit |
-- 2011-12-23 444 1.2 remove clksys output hack |
228,9 → 227,7
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
ENAPIN_RBMON => sbcntl_sbf_rbmon, |
CDWIDTH => 15, |
CDINIT => sys_conf_ser2rri_cdinit, |
RBMON_AWIDTH => 0, |
RBMON_RBADDR => x"ffe8") |
CDINIT => sys_conf_ser2rri_cdinit) |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
238,7 → 235,7
CE_INT => CE_MSEC, |
RESET => RESET, |
ENAXON => SWI(1), |
ESCFILL => '0', |
ENAESC => SWI(1), |
RXSD => RXD, |
TXSD => TXD, |
CTS_N => CTS_N, |
/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd
1,6 → 1,6
-- $Id: sys_tst_rlink_n3.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: sys_tst_rlink_n3.vhd 614 2014-12-20 15:00:45Z mueller $ |
-- |
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
37,7 → 37,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-11 666 1.4.1 rearrange XON handling |
-- 2014-11-09 603 1.4 use new rlink v4 iface and 4 bit STAT |
-- 2014-08-15 583 1.3 rb_mreq addr now 16 bit |
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect |
226,9 → 225,7
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
ENAPIN_RBMON => sbcntl_sbf_rbmon, |
CDWIDTH => 15, |
CDINIT => sys_conf_ser2rri_cdinit, |
RBMON_AWIDTH => 0, |
RBMON_RBADDR => x"ffe8") |
CDINIT => sys_conf_ser2rri_cdinit) |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
236,7 → 233,7
CE_INT => CE_MSEC, |
RESET => RESET, |
ENAXON => SWI(1), |
ESCFILL => '0', |
ENAESC => SWI(1), |
RXSD => RXD, |
TXSD => TXD, |
CTS_N => CTS_N, |
/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd
1,4 → 1,4
-- $Id: sys_tst_rlink_n4.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: sys_tst_rlink_n4.vhd 643 2015-02-07 17:41:53Z mueller $ |
-- |
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
34,7 → 34,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-11 666 1.4.1 rearrange XON handling |
-- 2015-02-06 643 1.4 factor out memory |
-- 2015-02-01 641 1.3.1 separate I_BTNRST_N; autobaud on msb of display |
-- 2015-01-31 640 1.3 drop fusp iface; use new sn_hio |
209,9 → 208,7
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
ENAPIN_RBMON => sbcntl_sbf_rbmon, |
CDWIDTH => 15, |
CDINIT => sys_conf_ser2rri_cdinit, |
RBMON_AWIDTH => 0, |
RBMON_RBADDR => x"ffe8") |
CDINIT => sys_conf_ser2rri_cdinit) |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
219,7 → 216,7
CE_INT => CE_MSEC, |
RESET => RESET, |
ENAXON => SWI(1), |
ESCFILL => '0', |
ENAESC => SWI(1), |
RXSD => RXD, |
TXSD => TXD, |
CTS_N => CTS_N, |
/rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd
1,6 → 1,6
-- $Id: sys_tst_rlink_s3.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: sys_tst_rlink_s3.vhd 614 2014-12-20 15:00:45Z mueller $ |
-- |
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
35,7 → 35,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-11 666 1.2.1 rearrange XON handling |
-- 2014-11-09 603 1.2 use new rlink v4 iface and 4 bit STAT |
-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit |
-- 2011-12-22 442 1.0 Initial version (derived from sys_tst_rlink_n2) |
199,9 → 198,7
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
ENAPIN_RBMON => sbcntl_sbf_rbmon, |
CDWIDTH => 15, |
CDINIT => sys_conf_ser2rri_cdinit, |
RBMON_AWIDTH => 0, |
RBMON_RBADDR => x"ffe8") |
CDINIT => sys_conf_ser2rri_cdinit) |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
209,7 → 206,7
CE_INT => CE_MSEC, |
RESET => RESET, |
ENAXON => SWI(1), |
ESCFILL => '0', |
ENAESC => SWI(1), |
RXSD => RXD, |
TXSD => TXD, |
CTS_N => CTS_N, |
/rtl/sys_gen/w11a/basys3/sys_conf.vhd
1,4 → 1,4
-- $Id: sys_conf.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
19,7 → 19,6
-- Tool versions: viv 2014.4; ghdl 0.31 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-03-14 658 1.1 add sys_conf_ibd_* definitions |
-- 2015-02-08 644 1.0 Initial version (derived from _n4 version) |
------------------------------------------------------------------------------ |
|
30,7 → 29,6
|
package sys_conf is |
|
-- configure clocks -------------------------------------------------------- |
constant sys_conf_clksys_vcodivide : positive := 1; |
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz |
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz |
41,19 → 39,13
constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; |
constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; |
|
-- configure rlink and hio interfaces -------------------------------------- |
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud |
|
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers |
|
-- configure memory controller --------------------------------------------- |
constant sys_conf_memctl_mawidth : positive := 4; |
constant sys_conf_memctl_nblock : positive := 11; |
|
-- configure debug and monitoring units ------------------------------------ |
constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs |
constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs |
|
-- configure w11 cpu core -------------------------------------------------- |
-- sys_conf_mem_losize is highest 64 byte MMU block number |
-- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks |
constant sys_conf_mem_losize : integer := 256*sys_conf_memctl_nblock-1; |
60,21 → 52,8
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 |
constant sys_conf_ibd_pc11 : boolean := true; -- PC11 |
constant sys_conf_ibd_lp11 : boolean := true; -- LP11 |
-- derived constants |
|
-- configure mass storage devices |
constant sys_conf_ibd_rk11 : boolean := true; -- RK11 |
constant sys_conf_ibd_rl11 : boolean := true; -- RL11 |
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP |
|
-- configure other devices |
constant sys_conf_ibd_iist : boolean := true; -- IIST |
|
-- derived constants ======================================================= |
constant sys_conf_clksys : integer := |
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / |
sys_conf_clksys_outdivide; |
89,3 → 68,15
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1; |
|
end package sys_conf; |
|
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory |
-- 2 211 111 111 110 000 000 000 |
-- 1 098 765 432 109 876 543 210 |
-- |
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte |
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte |
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte |
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte |
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte |
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte |
-- upper 256 kB excluded for 11/70 UB |
/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd
1,4 → 1,4
-- $Id: sys_conf_sim.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: sys_conf_sim.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
19,7 → 19,6
-- Tool versions: viv 2014.4; ghdl 0.31 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-03-14 658 1.1 add sys_conf_ibd_* definitions |
-- 2015-02-21 649 1.0 Initial version |
------------------------------------------------------------------------------ |
|
30,7 → 29,6
|
package sys_conf is |
|
-- configure clocks -------------------------------------------------------- |
constant sys_conf_clksys_vcodivide : positive := 1; |
constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz |
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz |
41,19 → 39,13
constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; |
constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; |
|
-- configure rlink and hio interfaces -------------------------------------- |
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim |
|
constant sys_conf_hio_debounce : boolean := false; -- no debouncers |
|
-- configure memory controller --------------------------------------------- |
constant sys_conf_memctl_mawidth : positive := 4; |
constant sys_conf_memctl_nblock : positive := 11; |
|
-- configure debug and monitoring units ------------------------------------ |
constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs |
constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs |
|
-- configure w11 cpu core -------------------------------------------------- |
-- sys_conf_mem_losize is highest 64 byte MMU block number |
-- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks |
constant sys_conf_mem_losize : integer := 256*sys_conf_memctl_nblock-1; |
60,21 → 52,8
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 |
constant sys_conf_ibd_pc11 : boolean := true; -- PC11 |
constant sys_conf_ibd_lp11 : boolean := true; -- LP11 |
|
-- configure mass storage devices |
constant sys_conf_ibd_rk11 : boolean := true; -- RK11 |
constant sys_conf_ibd_rl11 : boolean := true; -- RL11 |
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP |
|
-- configure other devices |
constant sys_conf_ibd_iist : boolean := true; -- IIST |
|
-- derived constants ======================================================= |
-- derived constants |
|
constant sys_conf_clksys : integer := |
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / |
sys_conf_clksys_outdivide; |
/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd
1,4 → 1,4
-- $Id: sys_w11a_b3.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: sys_w11a_b3.vhd 652 2015-02-28 12:18:08Z mueller $ |
-- |
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
18,14 → 18,21
-- Dependencies: vlib/xlib/s7_cmt_sfs |
-- vlib/genlib/clkdivce |
-- bplib/bpgen/bp_rs232_2line_iob |
-- bplib/bpgen/sn_humanio_rbus |
-- vlib/rlink/rlink_sp1c |
-- w11a/pdp11_sys70 |
-- vlib/rbus/rb_sres_or_3 |
-- w11a/pdp11_core_rbus |
-- w11a/pdp11_core |
-- w11a/pdp11_cache |
-- w11a/pdp11_mem70 |
-- w11a/pdp11_bram_memctl |
-- ibus/ib_sres_or_2 |
-- ibus/ibdr_maxisys |
-- w11a/pdp11_bram_memctl |
-- vlib/rlink/ioleds_sp1c |
-- w11a/pdp11_hio70 |
-- bplib/bpgen/sn_humanio_rbus |
-- vlib/rbus/rb_sres_or_2 |
-- w11a/pdp11_statleds |
-- w11a/pdp11_ledmux |
-- w11a/pdp11_dspmux |
-- w11a/pdp11_tmu_sb [sim only] |
-- |
-- Test bench: tb/tb_sys_w11a_b3 |
-- |
38,9 → 45,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul |
-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 |
-- 2015-04-11 666 1.1.1 rearrange XON handling |
-- 2015-02-21 649 1.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) |
-- 2015-02-08 644 1.0 Initial version (derived from sys_w11a_n4) |
------------------------------------------------------------------------------ |
126,17 → 130,14
|
signal CLK : slbit := '0'; |
|
signal RESET : slbit := '0'; |
signal CE_USEC : slbit := '0'; |
signal CE_MSEC : slbit := '0'; |
|
signal RXD : slbit := '1'; |
signal TXD : slbit := '0'; |
|
signal RB_MREQ : rb_mreq_type := rb_mreq_init; |
signal RB_SRES : rb_sres_type := rb_sres_init; |
signal RB_SRES_CPU : rb_sres_type := rb_sres_init; |
signal RB_SRES_HIO : rb_sres_type := rb_sres_init; |
signal SWI : slv16 := (others=>'0'); |
signal BTN : slv5 := (others=>'0'); |
signal LED : slv16 := (others=>'0'); |
signal DSP_DAT : slv16 := (others=>'0'); |
signal DSP_DP : slv4 := (others=>'0'); |
|
signal RB_LAM : slv16 := (others=>'0'); |
signal RB_STAT : slv4 := (others=>'0'); |
143,17 → 144,35
|
signal SER_MONI : serport_moni_type := serport_moni_init; |
|
signal GRESET : slbit := '0'; -- general reset (from rbus) |
signal CRESET : slbit := '0'; -- cpu reset (from cp) |
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) |
signal ITIMER : slbit := '0'; |
signal RB_MREQ : rb_mreq_type := rb_mreq_init; |
signal RB_SRES : rb_sres_type := rb_sres_init; |
signal RB_SRES_CPU : rb_sres_type := rb_sres_init; |
signal RB_SRES_IBD : rb_sres_type := rb_sres_init; |
signal RB_SRES_HIO : rb_sres_type := rb_sres_init; |
|
signal RESET : slbit := '0'; |
signal CE_USEC : slbit := '0'; |
signal CE_MSEC : slbit := '0'; |
|
signal CPU_RESET : slbit := '0'; |
signal CP_CNTL : cp_cntl_type := cp_cntl_init; |
signal CP_ADDR : cp_addr_type := cp_addr_init; |
signal CP_DIN : slv16 := (others=>'0'); |
signal CP_STAT : cp_stat_type := cp_stat_init; |
signal CP_DOUT : slv16 := (others=>'0'); |
|
signal EI_PRI : slv3 := (others=>'0'); |
signal EI_VECT : slv9_2 := (others=>'0'); |
signal EI_ACKM : slbit := '0'; |
signal CP_STAT : cp_stat_type := cp_stat_init; |
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; |
|
signal EM_MREQ : em_mreq_type := em_mreq_init; |
signal EM_SRES : em_sres_type := em_sres_init; |
|
signal HM_ENA : slbit := '0'; |
signal MEM70_FMISS : slbit := '0'; |
signal CACHE_FMISS : slbit := '0'; |
signal CACHE_CHIT : slbit := '0'; |
|
signal MEM_REQ : slbit := '0'; |
signal MEM_WE : slbit := '0'; |
signal MEM_BUSY : slbit := '0'; |
165,21 → 184,25
signal MEM_DI : slv32 := (others=>'0'); |
signal MEM_DO : slv32 := (others=>'0'); |
|
signal BRESET : slbit := '0'; |
signal IB_MREQ : ib_mreq_type := ib_mreq_init; |
signal IB_SRES : ib_sres_type := ib_sres_init; |
|
signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init; |
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; |
|
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; |
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; |
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; |
signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; |
|
signal DISPREG : slv16 := (others=>'0'); |
signal STATLEDS : slv8 := (others=>'0'); |
signal ABCLKDIV : slv16 := (others=>'0'); |
|
signal SWI : slv16 := (others=>'0'); |
signal BTN : slv5 := (others=>'0'); |
signal LED : slv16 := (others=>'0'); |
signal DSP_DAT : slv16 := (others=>'0'); |
signal DSP_DP : slv4 := (others=>'0'); |
|
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx |
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx |
constant rbaddr_ibus0 : slv16 := x"4000"; -- 4000/1000: 0100 xxxx xxxx xxxx |
constant rbaddr_core0 : slv16 := x"0000"; -- 0000/0020: 0000 0000 000x xxxx |
|
begin |
|
187,7 → 210,7
report "assert sys_conf_clksys on MHz grid" |
severity failure; |
|
GEN_CLKSYS : s7_cmt_sfs -- clock generator ------------------- |
GEN_CLKSYS : s7_cmt_sfs |
generic map ( |
VCO_DIVIDE => sys_conf_clksys_vcodivide, |
VCO_MULTIPLY => sys_conf_clksys_vcomultiply, |
202,7 → 225,7
LOCKED => open |
); |
|
CLKDIV : clkdivce -- usec/msec clock divider ----------- |
CLKDIV : clkdivce |
generic map ( |
CDUWIDTH => 7, |
USECDIV => sys_conf_clksys_mhz, |
213,7 → 236,7
CE_MSEC => CE_MSEC |
); |
|
IOB_RS232 : bp_rs232_2line_iob -- serport iob ---------------------- |
IOB_RS232 : bp_rs232_2line_iob |
port map ( |
CLK => CLK, |
RXD => RXD, |
222,8 → 245,34
O_TXD => O_TXD |
); |
|
RLINK : rlink_sp1c -- rlink for serport ----------------- |
HIO : sn_humanio_rbus |
generic map ( |
SWIDTH => 16, |
BWIDTH => 5, |
LWIDTH => 16, |
DCWIDTH => 2, |
DEBOUNCE => sys_conf_hio_debounce, |
RB_ADDR => rbaddr_hio) |
port map ( |
CLK => CLK, |
RESET => RESET, |
CE_MSEC => CE_MSEC, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_HIO, |
SWI => SWI, |
BTN => BTN, |
LED => LED, |
DSP_DAT => DSP_DAT, |
DSP_DP => DSP_DP, |
I_SWI => I_SWI, |
I_BTN => I_BTN, |
O_LED => O_LED, |
O_ANO_N => O_ANO_N, |
O_SEG_N => O_SEG_N |
); |
|
RLINK : rlink_sp1c |
generic map ( |
BTOWIDTH => 7, -- 128 cycles access timeout |
RTAWIDTH => 12, |
SYSID => (others=>'0'), |
232,9 → 281,7
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
ENAPIN_RBMON => sbcntl_sbf_rbmon, |
CDWIDTH => 13, |
CDINIT => sys_conf_ser2rri_cdinit, |
RBMON_AWIDTH => sys_conf_rbmon_awidth, |
RBMON_RBADDR => rbaddr_rbmon) |
CDINIT => sys_conf_ser2rri_cdinit) |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
242,7 → 289,7
CE_INT => CE_MSEC, |
RESET => RESET, |
ENAXON => SWI(1), |
ESCFILL => '0', |
ENAESC => SWI(1), |
RXSD => RXD, |
TXSD => TXD, |
CTS_N => '0', |
255,61 → 302,94
SER_MONI => SER_MONI |
); |
|
SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- |
RB_SRES_OR : rb_sres_or_3 |
port map ( |
CLK => CLK, |
RESET => RESET, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_CPU, |
RB_STAT => RB_STAT, |
RB_LAM_CPU => RB_LAM(0), |
GRESET => GRESET, |
CRESET => CRESET, |
BRESET => BRESET, |
CP_STAT => CP_STAT, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
EI_ACKM => EI_ACKM, |
ITIMER => ITIMER, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_IBDR, |
MEM_REQ => MEM_REQ, |
MEM_WE => MEM_WE, |
MEM_BUSY => MEM_BUSY, |
MEM_ACK_R => MEM_ACK_R, |
MEM_ADDR => MEM_ADDR, |
MEM_BE => MEM_BE, |
MEM_DI => MEM_DI, |
MEM_DO => MEM_DO, |
DM_STAT_DP => DM_STAT_DP |
RB_SRES_1 => RB_SRES_CPU, |
RB_SRES_2 => RB_SRES_IBD, |
RB_SRES_3 => RB_SRES_HIO, |
RB_SRES_OR => RB_SRES |
); |
|
RB2CP : pdp11_core_rbus |
generic map ( |
RB_ADDR_CORE => rbaddr_core0, |
RB_ADDR_IBUS => rbaddr_ibus0) |
port map ( |
CLK => CLK, |
RESET => RESET, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_CPU, |
RB_STAT => RB_STAT, |
RB_LAM => RB_LAM(0), |
CPU_RESET => CPU_RESET, |
CP_CNTL => CP_CNTL, |
CP_ADDR => CP_ADDR, |
CP_DIN => CP_DIN, |
CP_STAT => CP_STAT, |
CP_DOUT => CP_DOUT |
); |
|
W11A : pdp11_core |
port map ( |
CLK => CLK, |
RESET => CPU_RESET, |
CP_CNTL => CP_CNTL, |
CP_ADDR => CP_ADDR, |
CP_DIN => CP_DIN, |
CP_STAT => CP_STAT, |
CP_DOUT => CP_DOUT, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
EI_ACKM => EI_ACKM, |
EM_MREQ => EM_MREQ, |
EM_SRES => EM_SRES, |
BRESET => BRESET, |
IB_MREQ_M => IB_MREQ, |
IB_SRES_M => IB_SRES, |
DM_STAT_DP => DM_STAT_DP, |
DM_STAT_VM => DM_STAT_VM, |
DM_STAT_CO => DM_STAT_CO |
); |
|
CACHE: pdp11_cache |
port map ( |
CLK => CLK, |
GRESET => CPU_RESET, |
EM_MREQ => EM_MREQ, |
EM_SRES => EM_SRES, |
FMISS => CACHE_FMISS, |
CHIT => CACHE_CHIT, |
MEM_REQ => MEM_REQ, |
MEM_WE => MEM_WE, |
MEM_BUSY => MEM_BUSY, |
MEM_ACK_R => MEM_ACK_R, |
MEM_ADDR => MEM_ADDR, |
MEM_BE => MEM_BE, |
MEM_DI => MEM_DI, |
MEM_DO => MEM_DO |
); |
|
IBDR_SYS : ibdr_maxisys -- IO system ------------------------- |
MEM70: pdp11_mem70 |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
CE_MSEC => CE_MSEC, |
RESET => GRESET, |
BRESET => BRESET, |
ITIMER => ITIMER, |
CPUSUSP => CP_STAT.cpususp, |
RB_LAM => RB_LAM(15 downto 1), |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_IBDR, |
EI_ACKM => EI_ACKM, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
DISPREG => DISPREG |
CLK => CLK, |
CRESET => BRESET, |
HM_ENA => HM_ENA, |
HM_VAL => CACHE_CHIT, |
CACHE_FMISS => MEM70_FMISS, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_MEM70 |
); |
|
HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; |
CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; |
|
BRAM_CTL: pdp11_bram_memctl -- memory controller ----------------- |
BRAM_CTL: pdp11_bram_memctl |
generic map ( |
MAWIDTH => sys_conf_memctl_mawidth, |
NBLOCK => sys_conf_memctl_nblock) |
port map ( |
CLK => CLK, |
RESET => GRESET, |
RESET => CPU_RESET, |
REQ => MEM_REQ, |
WE => MEM_WE, |
BUSY => MEM_BUSY, |
323,62 → 403,82
DO => MEM_DO |
); |
|
LED_IO : ioleds_sp1c -- hio leds from serport ------------- |
IB_SRES_OR : ib_sres_or_2 |
port map ( |
IB_SRES_1 => IB_SRES_MEM70, |
IB_SRES_2 => IB_SRES_IBDR, |
IB_SRES_OR => IB_SRES |
); |
|
IBDR_SYS : ibdr_maxisys |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
CE_MSEC => CE_MSEC, |
RESET => CPU_RESET, |
BRESET => BRESET, |
RB_LAM => RB_LAM(15 downto 1), |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_IBDR, |
EI_ACKM => EI_ACKM, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
DISPREG => DISPREG |
); |
|
LED_IO : ioleds_sp1c |
port map ( |
SER_MONI => SER_MONI, |
IOLEDS => DSP_DP |
); |
|
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; |
|
HIO70 : pdp11_hio70 -- hio from sys70 -------------------- |
generic map ( |
LWIDTH => LED'length, |
DCWIDTH => 2) |
LED_CPU : pdp11_statleds |
port map ( |
SEL_LED => SWI(3), |
SEL_DSP => SWI(5 downto 4), |
MEM_ACT_R => MEM_ACT_R, |
MEM_ACT_W => MEM_ACT_W, |
CP_STAT => CP_STAT, |
DM_STAT_DP => DM_STAT_DP, |
ABCLKDIV => ABCLKDIV, |
DISPREG => DISPREG, |
LED => LED, |
DSP_DAT => DSP_DAT |
STATLEDS => STATLEDS |
); |
|
HIO : sn_humanio_rbus -- hio manager ----------------------- |
|
LED_MUX : pdp11_ledmux |
generic map ( |
SWIDTH => 16, |
BWIDTH => 5, |
LWIDTH => 16, |
DCWIDTH => 2, |
DEBOUNCE => sys_conf_hio_debounce, |
RB_ADDR => rbaddr_hio) |
LWIDTH => LED'length) |
port map ( |
CLK => CLK, |
RESET => RESET, |
CE_MSEC => CE_MSEC, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_HIO, |
SWI => SWI, |
BTN => BTN, |
LED => LED, |
DSP_DAT => DSP_DAT, |
DSP_DP => DSP_DP, |
I_SWI => I_SWI, |
I_BTN => I_BTN, |
O_LED => O_LED, |
O_ANO_N => O_ANO_N, |
O_SEG_N => O_SEG_N |
SEL => SWI(3), |
STATLEDS => STATLEDS, |
DM_STAT_DP => DM_STAT_DP, |
LED => LED |
); |
|
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; |
|
RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- |
DSP_MUX : pdp11_dspmux |
generic map ( |
DCWIDTH => 2) |
port map ( |
RB_SRES_1 => RB_SRES_CPU, |
RB_SRES_2 => RB_SRES_HIO, |
RB_SRES_OR => RB_SRES |
SEL => SWI(5 downto 4), |
ABCLKDIV => ABCLKDIV, |
DM_STAT_DP => DM_STAT_DP, |
DISPREG => DISPREG, |
DSP_DAT => DSP_DAT |
); |
|
-- synthesis translate_off |
DM_STAT_SY.emmreq <= EM_MREQ; |
DM_STAT_SY.emsres <= EM_SRES; |
DM_STAT_SY.chit <= CACHE_CHIT; |
|
TMU : pdp11_tmu_sb |
generic map ( |
ENAPIN => 13) |
port map ( |
CLK => CLK, |
DM_STAT_DP => DM_STAT_DP, |
DM_STAT_VM => DM_STAT_VM, |
DM_STAT_CO => DM_STAT_CO, |
DM_STAT_SY => DM_STAT_SY |
); |
-- synthesis translate_on |
|
end syn; |
/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom
16,14 → 16,21
[ghdl]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom |
../../../vlib/genlib/clkdivce.vbom |
../../../bplib/bpgen/bp_rs232_2line_iob.vbom |
../../../bplib/bpgen/sn_humanio_rbus.vbom |
../../../vlib/rlink/rlink_sp1c.vbom |
../../../w11a/pdp11_sys70.vbom |
../../../vlib/rbus/rb_sres_or_3.vbom |
../../../w11a/pdp11_core_rbus.vbom |
../../../w11a/pdp11_core.vbom |
../../../w11a/pdp11_cache.vbom |
../../../w11a/pdp11_mem70.vbom |
../../../w11a/pdp11_bram_memctl.vbom |
../../../ibus/ib_sres_or_2.vbom |
../../../ibus/ibdr_maxisys.vbom |
../../../w11a/pdp11_bram_memctl.vbom |
../../../vlib/rlink/ioleds_sp1c.vbom |
../../../w11a/pdp11_hio70.vbom |
../../../bplib/bpgen/sn_humanio_rbus.vbom |
../../../vlib/rbus/rb_sres_or_2.vbom |
../../../w11a/pdp11_statleds.vbom |
../../../w11a/pdp11_ledmux.vbom |
../../../w11a/pdp11_dspmux.vbom |
[sim]../../../w11a/pdp11_tmu_sb.vbom |
# design |
sys_w11a_b3.vhd |
@xdc:../../../bplib/basys3/basys3_pclk.xdc |
/rtl/sys_gen/w11a/nexys2/sys_conf.vhd
1,4 → 1,4
-- $Id: sys_conf.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: sys_conf.vhd 647 2015-02-17 22:35:36Z mueller $ |
-- |
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
19,7 → 19,6
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-03-14 658 1.4 add sys_conf_ibd_* definitions |
-- 2015-02-15 647 1.3 drop bram and minisys options |
-- 2015-01-04 630 1.2.2 use clksys=54 (no closure after rlink r4 + RL11) |
-- 2014-12-22 619 1.2.1 add _rbmon_awidth |
42,47 → 41,30
|
package sys_conf is |
|
-- configure clocks -------------------------------------------------------- |
constant sys_conf_clkfx_divide : positive := 25; |
constant sys_conf_clkfx_multiply : positive := 27; -- ==> 54 MHz |
|
-- configure rlink and hio interfaces -------------------------------------- |
constant sys_conf_memctl_read0delay : positive := 3; |
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; |
constant sys_conf_memctl_writedelay : positive := 4; |
|
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud |
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers |
|
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon |
|
-- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec |
constant sys_conf_fx2_petowidth : positive := 10; |
constant sys_conf_fx2_ccwidth : positive := 5; |
|
-- configure debug and monitoring units ------------------------------------ |
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon |
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon |
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers |
|
-- configure memory controller --------------------------------------------- |
constant sys_conf_memctl_read0delay : positive := 3; |
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; |
constant sys_conf_memctl_writedelay : positive := 4; |
|
-- configure w11 cpu core -------------------------------------------------- |
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte |
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 |
constant sys_conf_ibd_pc11 : boolean := true; -- PC11 |
constant sys_conf_ibd_lp11 : boolean := true; -- LP11 |
-- derived constants |
|
-- configure mass storage devices |
constant sys_conf_ibd_rk11 : boolean := true; -- RK11 |
constant sys_conf_ibd_rl11 : boolean := true; -- RL11 |
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP |
|
-- configure other devices |
constant sys_conf_ibd_iist : boolean := true; -- IIST |
|
-- derived constants ======================================================= |
constant sys_conf_clksys : integer := |
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; |
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; |
91,3 → 73,15
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; |
|
end package sys_conf; |
|
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory |
-- 2 211 111 111 110 000 000 000 |
-- 1 098 765 432 109 876 543 210 |
-- |
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte |
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte |
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte |
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte |
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte |
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte |
-- upper 256 kB excluded for 11/70 UB |
/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd
1,4 → 1,4
-- $Id: sys_conf_sim.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: sys_conf_sim.vhd 647 2015-02-17 22:35:36Z mueller $ |
-- |
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
19,7 → 19,6
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-03-14 658 1.4 add sys_conf_ibd_* definitions |
-- 2015-02-07 643 1.3 drop bram and minisys options |
-- 2014-12-22 619 1.2.1 add _rbmon_awidth |
-- 2013-04-21 509 1.2 add fx2 settings |
35,51 → 34,46
|
package sys_conf is |
|
-- configure clocks -------------------------------------------------------- |
constant sys_conf_clkfx_divide : positive := 1; |
constant sys_conf_clkfx_multiply : positive := 1; -- no dcm in sim... |
-- constant sys_conf_clkfx_divide : positive := 25; |
-- constant sys_conf_clkfx_multiply : positive := 28; -- ==> 56 MHz |
|
-- configure rlink and hio interfaces -------------------------------------- |
constant sys_conf_memctl_read0delay : positive := 3; |
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; |
constant sys_conf_memctl_writedelay : positive := 4; |
|
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim |
constant sys_conf_hio_debounce : boolean := false; -- no debouncers |
|
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon |
|
-- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec |
constant sys_conf_fx2_petowidth : positive := 10; |
constant sys_conf_fx2_ccwidth : positive := 5; |
|
constant sys_conf_hio_debounce : boolean := false; -- no debouncers |
|
-- configure memory controller --------------------------------------------- |
constant sys_conf_memctl_read0delay : positive := 3; |
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; |
constant sys_conf_memctl_writedelay : positive := 4; |
|
-- configure debug and monitoring units ------------------------------------ |
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon |
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon |
|
-- configure w11 cpu core -------------------------------------------------- |
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte |
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 |
constant sys_conf_ibd_pc11 : boolean := true; -- PC11 |
constant sys_conf_ibd_lp11 : boolean := true; -- LP11 |
-- derived constants |
|
-- configure mass storage devices |
constant sys_conf_ibd_rk11 : boolean := true; -- RK11 |
constant sys_conf_ibd_rl11 : boolean := true; -- RL11 |
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP |
|
-- configure other devices |
constant sys_conf_ibd_iist : boolean := true; -- IIST |
|
-- derived constants ======================================================= |
constant sys_conf_clksys : integer := |
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; |
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; |
|
end package sys_conf; |
|
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory |
-- 2 211 111 111 110 000 000 000 |
-- 1 098 765 432 109 876 543 210 |
-- |
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte |
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte |
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte |
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte |
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte |
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte |
-- upper 256 kB excluded for 11/70 UB |
/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd
1,4 → 1,4
-- $Id: sys_w11a_n2.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: sys_w11a_n2.vhd 652 2015-02-28 12:18:08Z mueller $ |
-- |
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
18,14 → 18,22
-- Dependencies: vlib/xlib/dcm_sfs |
-- vlib/genlib/clkdivce |
-- bplib/bpgen/bp_rs232_2l4l_iob |
-- bplib/bpgen/sn_humanio_rbus |
-- bplib/fx2rlink/rlink_sp1c_fx2 |
-- w11a/pdp11_sys70 |
-- vlib/rbus/rb_sres_or_4 |
-- vlib/rbus/rbd_rbmon |
-- w11a/pdp11_core_rbus |
-- w11a/pdp11_core |
-- w11a/pdp11_cache |
-- w11a/pdp11_mem70 |
-- bplib/nxcramlib/nx_cram_memctl_as |
-- ibus/ib_sres_or_2 |
-- ibus/ibdr_maxisys |
-- bplib/nxcramlib/nx_cram_memctl_as |
-- bplib/fx2rlink/ioleds_sp1c_fx2 |
-- w11a/pdp11_hio70 |
-- bplib/bpgen/sn_humanio_rbus |
-- vlib/rbus/rb_sres_or_2 |
-- w11a/pdp11_statleds |
-- w11a/pdp11_ledmux |
-- w11a/pdp11_dspmux |
-- w11a/pdp11_tmu_sb [sim only] |
-- |
-- Test bench: tb/tb_sys_w11a_n2 |
-- |
64,9 → 72,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul |
-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 |
-- 2015-04-11 666 1.7.2 rearrange XON handling |
-- 2015-02-21 649 1.7.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) |
-- 2015-02-15 647 1.7 drop bram and minisys options |
-- 2014-12-24 620 1.6.2 relocate ibus window and hio rbus address |
160,6 → 165,7
use work.genlib.all; |
use work.serportlib.all; |
use work.rblib.all; |
use work.rbdlib.all; |
use work.rlinklib.all; |
use work.fx2lib.all; |
use work.fx2rlinklib.all; |
214,19 → 220,16
|
signal CLK : slbit := '0'; |
|
signal RESET : slbit := '0'; |
signal CE_USEC : slbit := '0'; |
signal CE_MSEC : slbit := '0'; |
|
signal RXD : slbit := '1'; |
signal TXD : slbit := '0'; |
signal RTS_N : slbit := '0'; |
signal CTS_N : slbit := '0'; |
|
signal RB_MREQ : rb_mreq_type := rb_mreq_init; |
signal RB_SRES : rb_sres_type := rb_sres_init; |
signal RB_SRES_CPU : rb_sres_type := rb_sres_init; |
signal RB_SRES_HIO : rb_sres_type := rb_sres_init; |
signal SWI : slv8 := (others=>'0'); |
signal BTN : slv4 := (others=>'0'); |
signal LED : slv8 := (others=>'0'); |
signal DSP_DAT : slv16 := (others=>'0'); |
signal DSP_DP : slv4 := (others=>'0'); |
|
signal RB_LAM : slv16 := (others=>'0'); |
signal RB_STAT : slv4 := (others=>'0'); |
235,23 → 238,35
signal SER_MONI : serport_moni_type := serport_moni_init; |
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; |
|
signal SWI : slv8 := (others=>'0'); |
signal BTN : slv4 := (others=>'0'); |
signal LED : slv8 := (others=>'0'); |
signal DSP_DAT : slv16 := (others=>'0'); |
signal DSP_DP : slv4 := (others=>'0'); |
signal RB_MREQ : rb_mreq_type := rb_mreq_init; |
signal RB_SRES : rb_sres_type := rb_sres_init; |
signal RB_SRES_CPU : rb_sres_type := rb_sres_init; |
signal RB_SRES_IBD : rb_sres_type := rb_sres_init; |
signal RB_SRES_HIO : rb_sres_type := rb_sres_init; |
signal RB_SRES_RBMON : rb_sres_type := rb_sres_init; |
|
signal GRESET : slbit := '0'; -- general reset (from rbus) |
signal CRESET : slbit := '0'; -- cpu reset (from cp) |
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) |
signal ITIMER : slbit := '0'; |
signal RESET : slbit := '0'; |
signal CE_USEC : slbit := '0'; |
signal CE_MSEC : slbit := '0'; |
|
signal CPU_RESET : slbit := '0'; |
signal CP_CNTL : cp_cntl_type := cp_cntl_init; |
signal CP_ADDR : cp_addr_type := cp_addr_init; |
signal CP_DIN : slv16 := (others=>'0'); |
signal CP_STAT : cp_stat_type := cp_stat_init; |
signal CP_DOUT : slv16 := (others=>'0'); |
|
signal EI_PRI : slv3 := (others=>'0'); |
signal EI_VECT : slv9_2 := (others=>'0'); |
signal EI_ACKM : slbit := '0'; |
|
signal CP_STAT : cp_stat_type := cp_stat_init; |
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; |
signal EM_MREQ : em_mreq_type := em_mreq_init; |
signal EM_SRES : em_sres_type := em_sres_init; |
|
signal HM_ENA : slbit := '0'; |
signal MEM70_FMISS : slbit := '0'; |
signal CACHE_FMISS : slbit := '0'; |
signal CACHE_CHIT : slbit := '0'; |
|
signal MEM_REQ : slbit := '0'; |
signal MEM_WE : slbit := '0'; |
266,9 → 281,18
|
signal MEM_ADDR_EXT : slv22 := (others=>'0'); |
|
signal BRESET : slbit := '0'; |
signal IB_MREQ : ib_mreq_type := ib_mreq_init; |
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; |
signal IB_SRES : ib_sres_type := ib_sres_init; |
|
signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init; |
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; |
|
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; |
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; |
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; |
signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; |
|
signal DISPREG : slv16 := (others=>'0'); |
signal STATLEDS : slv8 := (others=>'0'); |
signal ABCLKDIV : slv16 := (others=>'0'); |
275,6 → 299,8
|
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx |
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx |
constant rbaddr_ibus0 : slv16 := x"4000"; -- 4000/1000: 0100 xxxx xxxx xxxx |
constant rbaddr_core0 : slv16 := x"0000"; -- 0000/0020: 0000 0000 000x xxxx |
|
begin |
|
282,7 → 308,7
report "assert sys_conf_clksys on MHz grid" |
severity failure; |
|
DCM : dcm_sfs -- clock generator ------------------- |
DCM : dcm_sfs |
generic map ( |
CLKFX_DIVIDE => sys_conf_clkfx_divide, |
CLKFX_MULTIPLY => sys_conf_clkfx_multiply, |
293,7 → 319,7
LOCKED => open |
); |
|
CLKDIV : clkdivce -- usec/msec clock divider ----------- |
CLKDIV : clkdivce |
generic map ( |
CDUWIDTH => 6, |
USECDIV => sys_conf_clksys_mhz, |
304,7 → 330,7
CE_MSEC => CE_MSEC |
); |
|
IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ---------------- |
IOB_RS232 : bp_rs232_2l4l_iob |
port map ( |
CLK => CLK, |
RESET => '0', |
321,8 → 347,30
O_RTS1_N => O_FUSP_RTS_N |
); |
|
RLINK : rlink_sp1c_fx2 -- rlink for serport + fx2 ----------- |
HIO : sn_humanio_rbus |
generic map ( |
DEBOUNCE => sys_conf_hio_debounce, |
RB_ADDR => rbaddr_hio) |
port map ( |
CLK => CLK, |
RESET => RESET, |
CE_MSEC => CE_MSEC, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_HIO, |
SWI => SWI, |
BTN => BTN, |
LED => LED, |
DSP_DAT => DSP_DAT, |
DSP_DP => DSP_DP, |
I_SWI => I_SWI, |
I_BTN => I_BTN, |
O_LED => O_LED, |
O_ANO_N => O_ANO_N, |
O_SEG_N => O_SEG_N |
); |
|
RLINK : rlink_sp1c_fx2 |
generic map ( |
BTOWIDTH => 7, -- 128 cycles access timeout |
RTAWIDTH => 12, |
SYSID => (others=>'0'), |
333,9 → 381,7
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
ENAPIN_RBMON => sbcntl_sbf_rbmon, |
CDWIDTH => 13, |
CDINIT => sys_conf_ser2rri_cdinit, |
RBMON_AWIDTH => sys_conf_rbmon_awidth, |
RBMON_RBADDR => rbaddr_rbmon) |
CDINIT => sys_conf_ser2rri_cdinit) |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
343,6 → 389,7
CE_INT => CE_MSEC, |
RESET => RESET, |
ENAXON => SWI(1), |
ENAESC => SWI(1), |
ENAFX2 => SWI(2), |
RXSD => RXD, |
TXSD => TXD, |
366,56 → 413,106
IO_FX2_DATA => IO_FX2_DATA |
); |
|
SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- |
RB_SRES_OR : rb_sres_or_4 |
port map ( |
CLK => CLK, |
RESET => RESET, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_CPU, |
RB_STAT => RB_STAT, |
RB_LAM_CPU => RB_LAM(0), |
GRESET => GRESET, |
CRESET => CRESET, |
BRESET => BRESET, |
CP_STAT => CP_STAT, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
EI_ACKM => EI_ACKM, |
ITIMER => ITIMER, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_IBDR, |
MEM_REQ => MEM_REQ, |
MEM_WE => MEM_WE, |
MEM_BUSY => MEM_BUSY, |
MEM_ACK_R => MEM_ACK_R, |
MEM_ADDR => MEM_ADDR, |
MEM_BE => MEM_BE, |
MEM_DI => MEM_DI, |
MEM_DO => MEM_DO, |
DM_STAT_DP => DM_STAT_DP |
RB_SRES_1 => RB_SRES_CPU, |
RB_SRES_2 => RB_SRES_IBD, |
RB_SRES_3 => RB_SRES_HIO, |
RB_SRES_4 => RB_SRES_RBMON, |
RB_SRES_OR => RB_SRES |
); |
|
RBMON : if sys_conf_rbmon_awidth > 0 generate |
begin |
RBMON : rbd_rbmon |
generic map ( |
RB_ADDR => rbaddr_rbmon, |
AWIDTH => sys_conf_rbmon_awidth) |
port map ( |
CLK => CLK, |
RESET => RESET, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_RBMON, |
RB_SRES_SUM => RB_SRES |
); |
end generate RBMON; |
|
RB2CP : pdp11_core_rbus |
generic map ( |
RB_ADDR_CORE => rbaddr_core0, |
RB_ADDR_IBUS => rbaddr_ibus0) |
port map ( |
CLK => CLK, |
RESET => RESET, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_CPU, |
RB_STAT => RB_STAT, |
RB_LAM => RB_LAM(0), |
CPU_RESET => CPU_RESET, |
CP_CNTL => CP_CNTL, |
CP_ADDR => CP_ADDR, |
CP_DIN => CP_DIN, |
CP_STAT => CP_STAT, |
CP_DOUT => CP_DOUT |
); |
|
IBDR_SYS : ibdr_maxisys -- IO system ------------------------- |
W11A : pdp11_core |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
CE_MSEC => CE_MSEC, |
RESET => GRESET, |
BRESET => BRESET, |
ITIMER => ITIMER, |
CPUSUSP => CP_STAT.cpususp, |
RB_LAM => RB_LAM(15 downto 1), |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_IBDR, |
EI_ACKM => EI_ACKM, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
DISPREG => DISPREG |
CLK => CLK, |
RESET => CPU_RESET, |
CP_CNTL => CP_CNTL, |
CP_ADDR => CP_ADDR, |
CP_DIN => CP_DIN, |
CP_STAT => CP_STAT, |
CP_DOUT => CP_DOUT, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
EI_ACKM => EI_ACKM, |
EM_MREQ => EM_MREQ, |
EM_SRES => EM_SRES, |
BRESET => BRESET, |
IB_MREQ_M => IB_MREQ, |
IB_SRES_M => IB_SRES, |
DM_STAT_DP => DM_STAT_DP, |
DM_STAT_VM => DM_STAT_VM, |
DM_STAT_CO => DM_STAT_CO |
); |
|
CACHE: pdp11_cache |
port map ( |
CLK => CLK, |
GRESET => CPU_RESET, |
EM_MREQ => EM_MREQ, |
EM_SRES => EM_SRES, |
FMISS => CACHE_FMISS, |
CHIT => CACHE_CHIT, |
MEM_REQ => MEM_REQ, |
MEM_WE => MEM_WE, |
MEM_BUSY => MEM_BUSY, |
MEM_ACK_R => MEM_ACK_R, |
MEM_ADDR => MEM_ADDR, |
MEM_BE => MEM_BE, |
MEM_DI => MEM_DI, |
MEM_DO => MEM_DO |
); |
|
|
MEM70: pdp11_mem70 |
port map ( |
CLK => CLK, |
CRESET => BRESET, |
HM_ENA => HM_ENA, |
HM_VAL => CACHE_CHIT, |
CACHE_FMISS => MEM70_FMISS, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_MEM70 |
); |
|
HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; |
CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; |
|
MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) |
|
SRAM_CTL: nx_cram_memctl_as -- memory controller ----------------- |
SRAM_CTL: nx_cram_memctl_as |
generic map ( |
READ0DELAY => sys_conf_memctl_read0delay, |
READ1DELAY => sys_conf_memctl_read1delay, |
422,7 → 519,7
WRITEDELAY => sys_conf_memctl_writedelay) |
port map ( |
CLK => CLK, |
RESET => GRESET, |
RESET => CPU_RESET, |
REQ => MEM_REQ, |
WE => MEM_WE, |
BUSY => MEM_BUSY, |
448,11 → 545,34
|
O_FLA_CE_N <= '1'; -- keep Flash memory disabled |
|
LED_IO : ioleds_sp1c_fx2 -- hio leds from serport or fx2 ------ |
IB_SRES_OR : ib_sres_or_2 |
port map ( |
IB_SRES_1 => IB_SRES_MEM70, |
IB_SRES_2 => IB_SRES_IBDR, |
IB_SRES_OR => IB_SRES |
); |
|
IBDR_SYS : ibdr_maxisys |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
RESET => GRESET, |
CE_MSEC => CE_MSEC, |
RESET => CPU_RESET, |
BRESET => BRESET, |
RB_LAM => RB_LAM(15 downto 1), |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_IBDR, |
EI_ACKM => EI_ACKM, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
DISPREG => DISPREG |
); |
|
LED_IO : ioleds_sp1c_fx2 |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
RESET => CPU_RESET, |
ENAFX2 => SWI(2), |
RB_SRES => RB_SRES, |
RLB_MONI => RLB_MONI, |
460,52 → 580,53
IOLEDS => DSP_DP |
); |
|
LED_CPU : pdp11_statleds |
port map ( |
MEM_ACT_R => MEM_ACT_R, |
MEM_ACT_W => MEM_ACT_W, |
CP_STAT => CP_STAT, |
DM_STAT_DP => DM_STAT_DP, |
STATLEDS => STATLEDS |
); |
|
LED_MUX : pdp11_ledmux |
generic map ( |
LWIDTH => LED'length) |
port map ( |
SEL => SWI(3), |
STATLEDS => STATLEDS, |
DM_STAT_DP => DM_STAT_DP, |
LED => LED |
); |
|
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; |
|
HIO70 : pdp11_hio70 -- hio from sys70 -------------------- |
DSP_MUX : pdp11_dspmux |
generic map ( |
LWIDTH => LED'length, |
DCWIDTH => 2) |
port map ( |
SEL_LED => SWI(3), |
SEL_DSP => SWI(5 downto 4), |
MEM_ACT_R => MEM_ACT_R, |
MEM_ACT_W => MEM_ACT_W, |
CP_STAT => CP_STAT, |
SEL => SWI(5 downto 4), |
ABCLKDIV => ABCLKDIV, |
DM_STAT_DP => DM_STAT_DP, |
ABCLKDIV => ABCLKDIV, |
DISPREG => DISPREG, |
LED => LED, |
DSP_DAT => DSP_DAT |
); |
|
HIO : sn_humanio_rbus -- hio manager ----------------------- |
|
-- synthesis translate_off |
DM_STAT_SY.emmreq <= EM_MREQ; |
DM_STAT_SY.emsres <= EM_SRES; |
DM_STAT_SY.chit <= CACHE_CHIT; |
|
TMU : pdp11_tmu_sb |
generic map ( |
DEBOUNCE => sys_conf_hio_debounce, |
RB_ADDR => rbaddr_hio) |
ENAPIN => 13) |
port map ( |
CLK => CLK, |
RESET => RESET, |
CE_MSEC => CE_MSEC, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_HIO, |
SWI => SWI, |
BTN => BTN, |
LED => LED, |
DSP_DAT => DSP_DAT, |
DSP_DP => DSP_DP, |
I_SWI => I_SWI, |
I_BTN => I_BTN, |
O_LED => O_LED, |
O_ANO_N => O_ANO_N, |
O_SEG_N => O_SEG_N |
CLK => CLK, |
DM_STAT_DP => DM_STAT_DP, |
DM_STAT_VM => DM_STAT_VM, |
DM_STAT_CO => DM_STAT_CO, |
DM_STAT_SY => DM_STAT_SY |
); |
|
RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- |
port map ( |
RB_SRES_1 => RB_SRES_CPU, |
RB_SRES_2 => RB_SRES_HIO, |
RB_SRES_OR => RB_SRES |
); |
|
-- synthesis translate_on |
|
end syn; |
/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom
4,6 → 4,7
../../../vlib/genlib/genlib.vhd |
../../../vlib/serport/serportlib.vbom |
../../../vlib/rbus/rblib.vhd |
../../../vlib/rbus/rbdlib.vhd |
../../../vlib/rlink/rlinklib.vbom |
../../../bplib/fx2lib/fx2lib.vhd |
../../../bplib/fx2rlink/fx2rlinklib.vbom |
19,14 → 20,22
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom |
../../../vlib/genlib/clkdivce.vbom |
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom |
../../../bplib/bpgen/sn_humanio_rbus.vbom |
../../../bplib/fx2rlink/rlink_sp1c_fx2.vbom |
../../../w11a/pdp11_sys70.vbom |
../../../vlib/rbus/rb_sres_or_4.vbom |
../../../vlib/rbus/rbd_rbmon.vbom |
../../../w11a/pdp11_core_rbus.vbom |
../../../w11a/pdp11_core.vbom |
../../../w11a/pdp11_cache.vbom |
../../../w11a/pdp11_mem70.vbom |
../../../bplib/nxcramlib/nx_cram_memctl_as.vbom |
../../../ibus/ib_sres_or_2.vbom |
../../../ibus/ibdr_maxisys.vbom |
../../../bplib/nxcramlib/nx_cram_memctl_as.vbom |
../../../bplib/fx2rlink/ioleds_sp1c_fx2.vbom |
../../../w11a/pdp11_hio70.vbom |
../../../bplib/bpgen/sn_humanio_rbus.vbom |
../../../vlib/rbus/rb_sres_or_2.vbom |
../../../w11a/pdp11_statleds.vbom |
../../../w11a/pdp11_ledmux.vbom |
../../../w11a/pdp11_dspmux.vbom |
[sim]../../../w11a/pdp11_tmu_sb.vbom |
# design |
sys_w11a_n2.vhd |
@ucf_cpp: sys_w11a_n2.ucf |
/rtl/sys_gen/w11a/nexys3/sys_conf.vhd
1,4 → 1,4
-- $Id: sys_conf.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: sys_conf.vhd 647 2015-02-17 22:35:36Z mueller $ |
-- |
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
19,7 → 19,6
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-03-14 658 1.4 add sys_conf_ibd_* definitions |
-- 2015-02-15 647 1.3 drop bram and minisys options |
-- 2014-12-26 621 1.2.2 use 68 MHz, get occasional problems with 72 MHz |
-- 2014-12-22 619 1.2.1 add _rbmon_awidth |
46,50 → 45,32
|
package sys_conf is |
|
-- configure clocks -------------------------------------------------------- |
constant sys_conf_clksys_vcodivide : positive := 25; |
constant sys_conf_clksys_vcomultiply : positive := 17; -- dcm 68 MHz |
constant sys_conf_clksys_outdivide : positive := 1; -- sys 68 MHz |
constant sys_conf_clksys_gentype : string := "DCM"; |
|
-- configure rlink and hio interfaces -------------------------------------- |
constant sys_conf_memctl_read0delay : positive := 4; |
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; |
constant sys_conf_memctl_writedelay : positive := 5; |
|
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud |
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers |
|
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon |
|
-- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec |
constant sys_conf_fx2_petowidth : positive := 10; |
constant sys_conf_fx2_ccwidth : positive := 5; |
|
-- configure memory controller --------------------------------------------- |
constant sys_conf_memctl_read0delay : positive := 4; |
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; |
constant sys_conf_memctl_writedelay : positive := 5; |
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers |
|
-- configure debug and monitoring units ------------------------------------ |
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon |
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon |
|
-- configure w11 cpu core -------------------------------------------------- |
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte |
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
-- configure character and communication devices |
constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 |
constant sys_conf_ibd_pc11 : boolean := true; -- PC11 |
constant sys_conf_ibd_lp11 : boolean := true; -- LP11 |
-- derived constants |
|
-- configure mass storage devices |
constant sys_conf_ibd_rk11 : boolean := true; -- RK11 |
constant sys_conf_ibd_rl11 : boolean := true; -- RL11 |
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP |
|
-- configure other devices |
constant sys_conf_ibd_iist : boolean := true; -- IIST |
|
-- derived constants ======================================================= |
constant sys_conf_clksys : integer := |
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / |
sys_conf_clksys_outdivide; |
99,3 → 80,15
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; |
|
end package sys_conf; |
|
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory |
-- 2 211 111 111 110 000 000 000 |
-- 1 098 765 432 109 876 543 210 |
-- |
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte |
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte |
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte |
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte |
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte |
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte |
-- upper 256 kB excluded for 11/70 UB |
/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd
1,4 → 1,4
-- $Id: sys_conf_sim.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: sys_conf_sim.vhd 647 2015-02-17 22:35:36Z mueller $ |
-- |
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
19,7 → 19,6
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-03-14 658 1.5 add sys_conf_ibd_* definitions |
-- 2015-02-15 647 1.4 drop bram and minisys options |
-- 2014-12-22 619 1.3.1 add _rbmon_awidth |
-- 2013-10-06 538 1.3 pll support, use clksys_vcodivide ect |
34,50 → 33,32
|
package sys_conf is |
|
-- configure clocks -------------------------------------------------------- |
constant sys_conf_clksys_vcodivide : positive := 25; |
constant sys_conf_clksys_vcomultiply : positive := 18; -- dcm 72 MHz |
constant sys_conf_clksys_outdivide : positive := 1; -- sys 72 MHz |
constant sys_conf_clksys_gentype : string := "DCM"; |
|
-- configure rlink and hio interfaces -------------------------------------- |
constant sys_conf_memctl_read0delay : positive := 4; -- for <75 MHz |
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; |
constant sys_conf_memctl_writedelay : positive := 5; |
|
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim |
constant sys_conf_hio_debounce : boolean := false; -- no debouncers |
|
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon |
|
-- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec |
constant sys_conf_fx2_petowidth : positive := 10; |
constant sys_conf_fx2_ccwidth : positive := 5; |
|
constant sys_conf_hio_debounce : boolean := false; -- no debouncers |
|
-- configure memory controller --------------------------------------------- |
constant sys_conf_memctl_read0delay : positive := 4; -- for <75 MHz |
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; |
constant sys_conf_memctl_writedelay : positive := 5; |
|
-- configure debug and monitoring units ------------------------------------ |
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon |
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable rbmon |
|
-- configure w11 cpu core -------------------------------------------------- |
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte |
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 |
constant sys_conf_ibd_pc11 : boolean := true; -- PC11 |
constant sys_conf_ibd_lp11 : boolean := true; -- LP11 |
-- derived constants |
|
-- configure mass storage devices |
constant sys_conf_ibd_rk11 : boolean := true; -- RK11 |
constant sys_conf_ibd_rl11 : boolean := true; -- RL11 |
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP |
|
-- configure other devices |
constant sys_conf_ibd_iist : boolean := true; -- IIST |
|
-- derived constants ======================================================= |
|
constant sys_conf_clksys : integer := |
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / |
sys_conf_clksys_outdivide; |
84,3 → 65,15
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; |
|
end package sys_conf; |
|
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory |
-- 2 211 111 111 110 000 000 000 |
-- 1 098 765 432 109 876 543 210 |
-- |
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte |
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte |
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte |
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte |
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte |
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte |
-- upper 256 kB excluded for 11/70 UB |
/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd
1,4 → 1,4
-- $Id: sys_w11a_n3.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: sys_w11a_n3.vhd 652 2015-02-28 12:18:08Z mueller $ |
-- |
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
18,14 → 18,22
-- Dependencies: vlib/xlib/s6_cmt_sfs |
-- vlib/genlib/clkdivce |
-- bplib/bpgen/bp_rs232_2l4l_iob |
-- bplib/bpgen/sn_humanio_rbus |
-- bplib/fx2rlink/rlink_sp1c_fx2 |
-- w11a/pdp11_sys70 |
-- vlib/rbus/rb_sres_or_4 |
-- vlib/rbus/rbd_rbmon |
-- w11a/pdp11_core_rbus |
-- w11a/pdp11_core |
-- w11a/pdp11_cache |
-- w11a/pdp11_mem70 |
-- bplib/nxcramlib/nx_cram_memctl_as |
-- ibus/ib_sres_or_2 |
-- ibus/ibdr_maxisys |
-- bplib/nxcramlib/nx_cram_memctl_as |
-- bplib/fx2rlink/ioleds_sp1c_fx2 |
-- w11a/pdp11_hio70 |
-- bplib/bpgen/sn_humanio_rbus |
-- vlib/rbus/rb_sres_or_2 |
-- w11a/pdp11_statleds |
-- w11a/pdp11_ledmux |
-- w11a/pdp11_dspmux |
-- w11a/pdp11_tmu_sb [sim only] |
-- |
-- Test bench: tb/tb_sys_w11a_n3 |
-- |
34,9 → 42,7
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2015-04-25 668 14.7 131013 xc6slx16-2 2101 4420 167 1520 ok: +ibmon 66% |
-- 2015-04-06 664 14.7 131013 xc6slx16-2 1991 4350 167 1489 ok: +RHRP 65% |
-- 2015-02-21 649 14.7 131013 xc6slx16-2 1819 3905 160 1380 ok: +RL11 |
-- 2014-02-21 649 14.7 131013 xc6slx16-2 1819 3905 160 1380 ok: +RL11 |
-- 2014-12-22 619 14.7 131013 xc6slx16-2 1742 3767 150 1350 ok: +rbmon |
-- 2014-12-20 614 14.7 131013 xc6slx16-2 1640 3692 150 1297 ok: -RL11,rlv4 |
-- 2014-06-08 561 14.7 131013 xc6slx16-2 1531 3500 142 1165 ok: +RL11 |
47,10 → 53,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul |
-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 |
-- 2015-04-24 668 1.8.3 added ibd_ibmon |
-- 2015-04-11 666 1.8.2 rearrange XON handling |
-- 2015-02-21 649 1.8.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) |
-- 2015-02-15 647 1.8 drop bram and minisys options |
-- 2014-12-24 620 1.7.2 relocate ibus window and hio rbus address |
125,6 → 127,7
use work.genlib.all; |
use work.serportlib.all; |
use work.rblib.all; |
use work.rbdlib.all; |
use work.rlinklib.all; |
use work.fx2lib.all; |
use work.fx2rlinklib.all; |
180,38 → 183,53
|
signal CLK : slbit := '0'; |
|
signal RESET : slbit := '0'; |
signal CE_USEC : slbit := '0'; |
signal CE_MSEC : slbit := '0'; |
|
signal RXD : slbit := '1'; |
signal TXD : slbit := '0'; |
signal RTS_N : slbit := '0'; |
signal CTS_N : slbit := '0'; |
|
signal RB_MREQ : rb_mreq_type := rb_mreq_init; |
signal RB_SRES : rb_sres_type := rb_sres_init; |
signal RB_SRES_CPU : rb_sres_type := rb_sres_init; |
signal RB_SRES_HIO : rb_sres_type := rb_sres_init; |
signal SWI : slv8 := (others=>'0'); |
signal BTN : slv5 := (others=>'0'); |
signal LED : slv8 := (others=>'0'); |
signal DSP_DAT : slv16 := (others=>'0'); |
signal DSP_DP : slv4 := (others=>'0'); |
|
signal RB_LAM : slv16 := (others=>'0'); |
signal RB_STAT : slv4 := (others=>'0'); |
|
|
signal RLB_MONI : rlb_moni_type := rlb_moni_init; |
signal SER_MONI : serport_moni_type := serport_moni_init; |
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; |
|
signal GRESET : slbit := '0'; -- general reset (from rbus) |
signal CRESET : slbit := '0'; -- cpu reset (from cp) |
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) |
signal ITIMER : slbit := '0'; |
signal RB_MREQ : rb_mreq_type := rb_mreq_init; |
signal RB_SRES : rb_sres_type := rb_sres_init; |
signal RB_SRES_CPU : rb_sres_type := rb_sres_init; |
signal RB_SRES_IBD : rb_sres_type := rb_sres_init; |
signal RB_SRES_HIO : rb_sres_type := rb_sres_init; |
signal RB_SRES_RBMON : rb_sres_type := rb_sres_init; |
|
signal RESET : slbit := '0'; |
signal CE_USEC : slbit := '0'; |
signal CE_MSEC : slbit := '0'; |
|
signal CPU_RESET : slbit := '0'; |
signal CP_CNTL : cp_cntl_type := cp_cntl_init; |
signal CP_ADDR : cp_addr_type := cp_addr_init; |
signal CP_DIN : slv16 := (others=>'0'); |
signal CP_STAT : cp_stat_type := cp_stat_init; |
signal CP_DOUT : slv16 := (others=>'0'); |
|
signal EI_PRI : slv3 := (others=>'0'); |
signal EI_VECT : slv9_2 := (others=>'0'); |
signal EI_ACKM : slbit := '0'; |
|
signal CP_STAT : cp_stat_type := cp_stat_init; |
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; |
signal EM_MREQ : em_mreq_type := em_mreq_init; |
signal EM_SRES : em_sres_type := em_sres_init; |
|
signal HM_ENA : slbit := '0'; |
signal MEM70_FMISS : slbit := '0'; |
signal CACHE_FMISS : slbit := '0'; |
signal CACHE_CHIT : slbit := '0'; |
|
signal MEM_REQ : slbit := '0'; |
signal MEM_WE : slbit := '0'; |
226,21 → 244,26
|
signal MEM_ADDR_EXT : slv22 := (others=>'0'); |
|
signal BRESET : slbit := '0'; |
signal IB_MREQ : ib_mreq_type := ib_mreq_init; |
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; |
signal IB_SRES : ib_sres_type := ib_sres_init; |
|
signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init; |
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; |
|
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; |
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; |
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; |
signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; |
|
signal DISPREG : slv16 := (others=>'0'); |
signal STATLEDS : slv8 := (others=>'0'); |
signal ABCLKDIV : slv16 := (others=>'0'); |
|
signal SWI : slv8 := (others=>'0'); |
signal BTN : slv5 := (others=>'0'); |
signal LED : slv8 := (others=>'0'); |
signal DSP_DAT : slv16 := (others=>'0'); |
signal DSP_DP : slv4 := (others=>'0'); |
|
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx |
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx |
constant rbaddr_ibus0 : slv16 := x"4000"; -- 4000/1000: 0100 xxxx xxxx xxxx |
constant rbaddr_core0 : slv16 := x"0000"; -- 0000/0020: 0000 0000 000x xxxx |
|
begin |
|
248,7 → 271,7
report "assert sys_conf_clksys on MHz grid" |
severity failure; |
|
GEN_CLKSYS : s6_cmt_sfs -- clock generator ------------------- |
GEN_CLKSYS : s6_cmt_sfs |
generic map ( |
VCO_DIVIDE => sys_conf_clksys_vcodivide, |
VCO_MULTIPLY => sys_conf_clksys_vcomultiply, |
263,7 → 286,7
LOCKED => open |
); |
|
CLKDIV : clkdivce -- usec/msec clock divider ----------- |
CLKDIV : clkdivce |
generic map ( |
CDUWIDTH => 7, |
USECDIV => sys_conf_clksys_mhz, |
274,7 → 297,7
CE_MSEC => CE_MSEC |
); |
|
IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ---------------- |
IOB_RS232 : bp_rs232_2l4l_iob |
port map ( |
CLK => CLK, |
RESET => '0', |
291,8 → 314,31
O_RTS1_N => O_FUSP_RTS_N |
); |
|
RLINK : rlink_sp1c_fx2 -- rlink for serport + fx2 ----------- |
HIO : sn_humanio_rbus |
generic map ( |
BWIDTH => 5, |
DEBOUNCE => sys_conf_hio_debounce, |
RB_ADDR => rbaddr_hio) |
port map ( |
CLK => CLK, |
RESET => RESET, |
CE_MSEC => CE_MSEC, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_HIO, |
SWI => SWI, |
BTN => BTN, |
LED => LED, |
DSP_DAT => DSP_DAT, |
DSP_DP => DSP_DP, |
I_SWI => I_SWI, |
I_BTN => I_BTN, |
O_LED => O_LED, |
O_ANO_N => O_ANO_N, |
O_SEG_N => O_SEG_N |
); |
|
RLINK : rlink_sp1c_fx2 |
generic map ( |
BTOWIDTH => 7, -- 128 cycles access timeout |
RTAWIDTH => 12, |
SYSID => (others=>'0'), |
303,9 → 349,7
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
ENAPIN_RBMON => sbcntl_sbf_rbmon, |
CDWIDTH => 13, |
CDINIT => sys_conf_ser2rri_cdinit, |
RBMON_AWIDTH => sys_conf_rbmon_awidth, |
RBMON_RBADDR => rbaddr_rbmon) |
CDINIT => sys_conf_ser2rri_cdinit) |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
313,6 → 357,7
CE_INT => CE_MSEC, |
RESET => RESET, |
ENAXON => SWI(1), |
ENAESC => SWI(1), |
ENAFX2 => SWI(2), |
RXSD => RXD, |
TXSD => TXD, |
336,56 → 381,106
IO_FX2_DATA => IO_FX2_DATA |
); |
|
SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- |
RB_SRES_OR : rb_sres_or_4 |
port map ( |
CLK => CLK, |
RESET => RESET, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_CPU, |
RB_STAT => RB_STAT, |
RB_LAM_CPU => RB_LAM(0), |
GRESET => GRESET, |
CRESET => CRESET, |
BRESET => BRESET, |
CP_STAT => CP_STAT, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
EI_ACKM => EI_ACKM, |
ITIMER => ITIMER, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_IBDR, |
MEM_REQ => MEM_REQ, |
MEM_WE => MEM_WE, |
MEM_BUSY => MEM_BUSY, |
MEM_ACK_R => MEM_ACK_R, |
MEM_ADDR => MEM_ADDR, |
MEM_BE => MEM_BE, |
MEM_DI => MEM_DI, |
MEM_DO => MEM_DO, |
DM_STAT_DP => DM_STAT_DP |
RB_SRES_1 => RB_SRES_CPU, |
RB_SRES_2 => RB_SRES_IBD, |
RB_SRES_3 => RB_SRES_HIO, |
RB_SRES_4 => RB_SRES_RBMON, |
RB_SRES_OR => RB_SRES |
); |
|
RBMON : if sys_conf_rbmon_awidth > 0 generate |
begin |
RBMON : rbd_rbmon |
generic map ( |
RB_ADDR => rbaddr_rbmon, |
AWIDTH => sys_conf_rbmon_awidth) |
port map ( |
CLK => CLK, |
RESET => RESET, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_RBMON, |
RB_SRES_SUM => RB_SRES |
); |
end generate RBMON; |
|
IBDR_SYS : ibdr_maxisys -- IO system ------------------------- |
RB2CP : pdp11_core_rbus |
generic map ( |
RB_ADDR_CORE => rbaddr_core0, |
RB_ADDR_IBUS => rbaddr_ibus0) |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
CE_MSEC => CE_MSEC, |
RESET => GRESET, |
BRESET => BRESET, |
ITIMER => ITIMER, |
CPUSUSP => CP_STAT.cpususp, |
RB_LAM => RB_LAM(15 downto 1), |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_IBDR, |
EI_ACKM => EI_ACKM, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
DISPREG => DISPREG |
CLK => CLK, |
RESET => RESET, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_CPU, |
RB_STAT => RB_STAT, |
RB_LAM => RB_LAM(0), |
CPU_RESET => CPU_RESET, |
CP_CNTL => CP_CNTL, |
CP_ADDR => CP_ADDR, |
CP_DIN => CP_DIN, |
CP_STAT => CP_STAT, |
CP_DOUT => CP_DOUT |
); |
|
|
W11A : pdp11_core |
port map ( |
CLK => CLK, |
RESET => CPU_RESET, |
CP_CNTL => CP_CNTL, |
CP_ADDR => CP_ADDR, |
CP_DIN => CP_DIN, |
CP_STAT => CP_STAT, |
CP_DOUT => CP_DOUT, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
EI_ACKM => EI_ACKM, |
EM_MREQ => EM_MREQ, |
EM_SRES => EM_SRES, |
BRESET => BRESET, |
IB_MREQ_M => IB_MREQ, |
IB_SRES_M => IB_SRES, |
DM_STAT_DP => DM_STAT_DP, |
DM_STAT_VM => DM_STAT_VM, |
DM_STAT_CO => DM_STAT_CO |
); |
|
CACHE: pdp11_cache |
port map ( |
CLK => CLK, |
GRESET => CPU_RESET, |
EM_MREQ => EM_MREQ, |
EM_SRES => EM_SRES, |
FMISS => CACHE_FMISS, |
CHIT => CACHE_CHIT, |
MEM_REQ => MEM_REQ, |
MEM_WE => MEM_WE, |
MEM_BUSY => MEM_BUSY, |
MEM_ACK_R => MEM_ACK_R, |
MEM_ADDR => MEM_ADDR, |
MEM_BE => MEM_BE, |
MEM_DI => MEM_DI, |
MEM_DO => MEM_DO |
); |
|
MEM70: pdp11_mem70 |
port map ( |
CLK => CLK, |
CRESET => BRESET, |
HM_ENA => HM_ENA, |
HM_VAL => CACHE_CHIT, |
CACHE_FMISS => MEM70_FMISS, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_MEM70 |
); |
|
HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; |
CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; |
|
MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) |
|
SRAM_CTL: nx_cram_memctl_as -- memory controller ----------------- |
SRAM_CTL: nx_cram_memctl_as |
generic map ( |
READ0DELAY => sys_conf_memctl_read0delay, |
READ1DELAY => sys_conf_memctl_read1delay, |
392,7 → 487,7
WRITEDELAY => sys_conf_memctl_writedelay) |
port map ( |
CLK => CLK, |
RESET => GRESET, |
RESET => CPU_RESET, |
REQ => MEM_REQ, |
WE => MEM_WE, |
BUSY => MEM_BUSY, |
418,12 → 513,35
|
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled |
O_PPCM_RST_N <= '1'; -- |
|
IB_SRES_OR : ib_sres_or_2 |
port map ( |
IB_SRES_1 => IB_SRES_MEM70, |
IB_SRES_2 => IB_SRES_IBDR, |
IB_SRES_OR => IB_SRES |
); |
|
LED_IO : ioleds_sp1c_fx2 -- hio leds from serport or fx2 ------ |
IBDR_SYS : ibdr_maxisys |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
RESET => GRESET, |
CE_MSEC => CE_MSEC, |
RESET => CPU_RESET, |
BRESET => BRESET, |
RB_LAM => RB_LAM(15 downto 1), |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_IBDR, |
EI_ACKM => EI_ACKM, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
DISPREG => DISPREG |
); |
|
LED_IO : ioleds_sp1c_fx2 |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
RESET => CPU_RESET, |
ENAFX2 => SWI(2), |
RB_SRES => RB_SRES, |
RLB_MONI => RLB_MONI, |
431,53 → 549,53
IOLEDS => DSP_DP |
); |
|
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; |
|
HIO70 : pdp11_hio70 -- hio from sys70 -------------------- |
generic map ( |
LWIDTH => LED'length, |
DCWIDTH => 2) |
LED_CPU : pdp11_statleds |
port map ( |
SEL_LED => SWI(3), |
SEL_DSP => SWI(5 downto 4), |
MEM_ACT_R => MEM_ACT_R, |
MEM_ACT_W => MEM_ACT_W, |
CP_STAT => CP_STAT, |
DM_STAT_DP => DM_STAT_DP, |
ABCLKDIV => ABCLKDIV, |
DISPREG => DISPREG, |
LED => LED, |
DSP_DAT => DSP_DAT |
STATLEDS => STATLEDS |
); |
|
HIO : sn_humanio_rbus -- hio manager ----------------------- |
|
LED_MUX : pdp11_ledmux |
generic map ( |
BWIDTH => 5, |
DEBOUNCE => sys_conf_hio_debounce, |
RB_ADDR => rbaddr_hio) |
LWIDTH => LED'length) |
port map ( |
CLK => CLK, |
RESET => RESET, |
CE_MSEC => CE_MSEC, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_HIO, |
SWI => SWI, |
BTN => BTN, |
LED => LED, |
DSP_DAT => DSP_DAT, |
DSP_DP => DSP_DP, |
I_SWI => I_SWI, |
I_BTN => I_BTN, |
O_LED => O_LED, |
O_ANO_N => O_ANO_N, |
O_SEG_N => O_SEG_N |
SEL => SWI(3), |
STATLEDS => STATLEDS, |
DM_STAT_DP => DM_STAT_DP, |
LED => LED |
); |
|
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; |
|
RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- |
DSP_MUX : pdp11_dspmux |
generic map ( |
DCWIDTH => 2) |
port map ( |
RB_SRES_1 => RB_SRES_CPU, |
RB_SRES_2 => RB_SRES_HIO, |
RB_SRES_OR => RB_SRES |
SEL => SWI(5 downto 4), |
ABCLKDIV => ABCLKDIV, |
DM_STAT_DP => DM_STAT_DP, |
DISPREG => DISPREG, |
DSP_DAT => DSP_DAT |
); |
|
-- synthesis translate_off |
DM_STAT_SY.emmreq <= EM_MREQ; |
DM_STAT_SY.emsres <= EM_SRES; |
DM_STAT_SY.chit <= CACHE_CHIT; |
|
TMU : pdp11_tmu_sb |
generic map ( |
ENAPIN => 13) |
port map ( |
CLK => CLK, |
DM_STAT_DP => DM_STAT_DP, |
DM_STAT_VM => DM_STAT_VM, |
DM_STAT_CO => DM_STAT_CO, |
DM_STAT_SY => DM_STAT_SY |
); |
-- synthesis translate_on |
|
end syn; |
/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom
4,6 → 4,7
../../../vlib/genlib/genlib.vhd |
../../../vlib/serport/serportlib.vbom |
../../../vlib/rbus/rblib.vhd |
../../../vlib/rbus/rbdlib.vhd |
../../../vlib/rlink/rlinklib.vbom |
../../../bplib/fx2lib/fx2lib.vhd |
../../../bplib/fx2rlink/fx2rlinklib.vbom |
19,14 → 20,22
[ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom |
../../../vlib/genlib/clkdivce.vbom |
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom |
../../../bplib/bpgen/sn_humanio_rbus.vbom |
../../../bplib/fx2rlink/rlink_sp1c_fx2.vbom |
../../../w11a/pdp11_sys70.vbom |
../../../vlib/rbus/rb_sres_or_4.vbom |
../../../vlib/rbus/rbd_rbmon.vbom |
../../../w11a/pdp11_core_rbus.vbom |
../../../w11a/pdp11_core.vbom |
../../../w11a/pdp11_cache.vbom |
../../../w11a/pdp11_mem70.vbom |
../../../bplib/nxcramlib/nx_cram_memctl_as.vbom |
../../../ibus/ib_sres_or_2.vbom |
../../../ibus/ibdr_maxisys.vbom |
../../../bplib/nxcramlib/nx_cram_memctl_as.vbom |
../../../bplib/fx2rlink/ioleds_sp1c_fx2.vbom |
../../../w11a/pdp11_hio70.vbom |
../../../bplib/bpgen/sn_humanio_rbus.vbom |
../../../vlib/rbus/rb_sres_or_2.vbom |
../../../w11a/pdp11_statleds.vbom |
../../../w11a/pdp11_ledmux.vbom |
../../../w11a/pdp11_dspmux.vbom |
[sim]../../../w11a/pdp11_tmu_sb.vbom |
# design |
sys_w11a_n3.vhd |
@ucf_cpp: sys_w11a_n3.ucf |
/rtl/sys_gen/w11a/nexys4/sys_conf.vhd
1,4 → 1,4
-- $Id: sys_conf.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: sys_conf.vhd 643 2015-02-07 17:41:53Z mueller $ |
-- |
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
19,7 → 19,6
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions |
-- 2015-02-07 643 1.1 drop bram and minisys options |
-- 2013-09-22 534 1.0 Initial version (derived from _n3 version) |
------------------------------------------------------------------------------ |
40,7 → 39,6
|
package sys_conf is |
|
-- configure clocks -------------------------------------------------------- |
constant sys_conf_clksys_vcodivide : positive := 1; |
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz |
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz |
51,39 → 49,21
constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; |
constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; |
|
-- configure rlink and hio interfaces -------------------------------------- |
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud |
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers |
|
-- configure memory controller --------------------------------------------- |
constant sys_conf_memctl_read0delay : positive := 5; |
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; |
constant sys_conf_memctl_writedelay : positive := 5; |
|
-- configure debug and monitoring units ------------------------------------ |
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon |
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon |
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud |
|
-- configure w11 cpu core -------------------------------------------------- |
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers |
|
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte |
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 |
constant sys_conf_ibd_pc11 : boolean := true; -- PC11 |
constant sys_conf_ibd_lp11 : boolean := true; -- LP11 |
-- derived constants |
|
-- configure mass storage devices |
constant sys_conf_ibd_rk11 : boolean := true; -- RK11 |
constant sys_conf_ibd_rl11 : boolean := true; -- RL11 |
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP |
|
-- configure other devices |
constant sys_conf_ibd_iist : boolean := true; -- IIST |
|
-- derived constants ======================================================= |
constant sys_conf_clksys : integer := |
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / |
sys_conf_clksys_outdivide; |
98,3 → 78,15
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1; |
|
end package sys_conf; |
|
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory |
-- 2 211 111 111 110 000 000 000 |
-- 1 098 765 432 109 876 543 210 |
-- |
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte |
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte |
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte |
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte |
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte |
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte |
-- upper 256 kB excluded for 11/70 UB |
/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd
1,4 → 1,4
-- $Id: sys_conf_sim.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: sys_conf_sim.vhd 647 2015-02-17 22:35:36Z mueller $ |
-- |
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
19,7 → 19,6
-- Tool versions: xst 14.5-14.7; ghdl 0.29-0.31 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions |
-- 2015-02-07 643 1.1 drop bram and minisys options |
-- 2013-09-34 534 1.0 Initial version (cloned from _n3) |
------------------------------------------------------------------------------ |
31,7 → 30,6
|
package sys_conf is |
|
-- configure clocks -------------------------------------------------------- |
constant sys_conf_clksys_vcodivide : positive := 1; |
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz |
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz |
42,39 → 40,21
constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; |
constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; |
|
-- configure rlink and hio interfaces -------------------------------------- |
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim |
constant sys_conf_hio_debounce : boolean := false; -- no debouncers |
|
-- configure memory controller --------------------------------------------- |
constant sys_conf_memctl_read0delay : positive := 6; -- for 100 MHz |
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; |
constant sys_conf_memctl_writedelay : positive := 7; |
|
-- configure debug and monitoring units ------------------------------------ |
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon |
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon |
|
-- configure w11 cpu core -------------------------------------------------- |
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim |
|
constant sys_conf_hio_debounce : boolean := false; -- no debouncers |
|
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte |
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 |
constant sys_conf_ibd_pc11 : boolean := true; -- PC11 |
constant sys_conf_ibd_lp11 : boolean := true; -- LP11 |
-- derived constants |
|
-- configure mass storage devices |
constant sys_conf_ibd_rk11 : boolean := true; -- RK11 |
constant sys_conf_ibd_rl11 : boolean := true; -- RL11 |
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP |
|
-- configure other devices |
constant sys_conf_ibd_iist : boolean := true; -- IIST |
|
-- derived constants ======================================================= |
constant sys_conf_clksys : integer := |
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / |
sys_conf_clksys_outdivide; |
86,3 → 66,15
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; |
|
end package sys_conf; |
|
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory |
-- 2 211 111 111 110 000 000 000 |
-- 1 098 765 432 109 876 543 210 |
-- |
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte |
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte |
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte |
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte |
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte |
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte |
-- upper 256 kB excluded for 11/70 UB |
/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd
1,4 → 1,4
-- $Id: sys_w11a_n4.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: sys_w11a_n4.vhd 650 2015-02-22 21:39:47Z mueller $ |
-- |
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
18,14 → 18,21
-- Dependencies: vlib/xlib/s7_cmt_sfs |
-- vlib/genlib/clkdivce |
-- bplib/bpgen/bp_rs232_4line_iob |
-- bplib/bpgen/sn_humanio_rbus |
-- vlib/rlink/rlink_sp1c |
-- w11a/pdp11_sys70 |
-- vlib/rbus/rb_sres_or_3 |
-- w11a/pdp11_core_rbus |
-- w11a/pdp11_core |
-- w11a/pdp11_cache |
-- w11a/pdp11_mem70 |
-- bplib/nxcramlib/nx_cram_memctl_as |
-- ibus/ib_sres_or_2 |
-- ibus/ibdr_maxisys |
-- bplib/nxcramlib/nx_cram_memctl_as |
-- bplib/fx2rlink/ioleds_sp1c |
-- w11a/pdp11_hio70 |
-- bplib/bpgen/sn_humanio_rbus |
-- vlib/rbus/rb_sres_or_2 |
-- vlib/rlink/ioleds_sp1c |
-- w11a/pdp11_statleds |
-- w11a/pdp11_ledmux |
-- w11a/pdp11_dspmux |
-- w11a/pdp11_tmu_sb [sim only] |
-- |
-- Test bench: tb/tb_sys_w11a_n4 |
-- |
39,9 → 46,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; ; reset overhaul |
-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 |
-- 2015-04-11 666 1.4.2 rearrange XON handling |
-- 2015-02-21 649 1.4.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) |
-- 2015-02-07 643 1.4 new DSP+LED layout, use pdp11_dr; drop bram and |
-- minisys options; |
152,19 → 156,16
|
signal CLK : slbit := '0'; |
|
signal RESET : slbit := '0'; |
signal CE_USEC : slbit := '0'; |
signal CE_MSEC : slbit := '0'; |
|
signal RXD : slbit := '1'; |
signal TXD : slbit := '0'; |
signal RTS_N : slbit := '0'; |
signal CTS_N : slbit := '0'; |
|
signal RB_MREQ : rb_mreq_type := rb_mreq_init; |
signal RB_SRES : rb_sres_type := rb_sres_init; |
signal RB_SRES_CPU : rb_sres_type := rb_sres_init; |
signal RB_SRES_HIO : rb_sres_type := rb_sres_init; |
signal SWI : slv16 := (others=>'0'); |
signal BTN : slv5 := (others=>'0'); |
signal LED : slv16 := (others=>'0'); |
signal DSP_DAT : slv32 := (others=>'0'); |
signal DSP_DP : slv8 := (others=>'0'); |
|
signal RB_LAM : slv16 := (others=>'0'); |
signal RB_STAT : slv4 := (others=>'0'); |
171,18 → 172,35
|
signal SER_MONI : serport_moni_type := serport_moni_init; |
|
signal GRESET : slbit := '0'; -- general reset (from rbus) |
signal CRESET : slbit := '0'; -- cpu reset (from cp) |
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) |
signal ITIMER : slbit := '0'; |
|
signal RB_MREQ : rb_mreq_type := rb_mreq_init; |
signal RB_SRES : rb_sres_type := rb_sres_init; |
signal RB_SRES_CPU : rb_sres_type := rb_sres_init; |
signal RB_SRES_IBD : rb_sres_type := rb_sres_init; |
signal RB_SRES_HIO : rb_sres_type := rb_sres_init; |
|
signal RESET : slbit := '0'; |
signal CE_USEC : slbit := '0'; |
signal CE_MSEC : slbit := '0'; |
|
signal CPU_RESET : slbit := '0'; |
signal CP_CNTL : cp_cntl_type := cp_cntl_init; |
signal CP_ADDR : cp_addr_type := cp_addr_init; |
signal CP_DIN : slv16 := (others=>'0'); |
signal CP_STAT : cp_stat_type := cp_stat_init; |
signal CP_DOUT : slv16 := (others=>'0'); |
|
signal EI_PRI : slv3 := (others=>'0'); |
signal EI_VECT : slv9_2 := (others=>'0'); |
signal EI_ACKM : slbit := '0'; |
|
signal EM_MREQ : em_mreq_type := em_mreq_init; |
signal EM_SRES : em_sres_type := em_sres_init; |
|
signal HM_ENA : slbit := '0'; |
signal MEM70_FMISS : slbit := '0'; |
signal CACHE_FMISS : slbit := '0'; |
signal CACHE_CHIT : slbit := '0'; |
|
signal CP_STAT : cp_stat_type := cp_stat_init; |
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; |
|
signal MEM_REQ : slbit := '0'; |
signal MEM_WE : slbit := '0'; |
signal MEM_BUSY : slbit := '0'; |
196,21 → 214,25
|
signal MEM_ADDR_EXT : slv22 := (others=>'0'); |
|
signal BRESET : slbit := '0'; |
signal IB_MREQ : ib_mreq_type := ib_mreq_init; |
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; |
signal IB_SRES : ib_sres_type := ib_sres_init; |
|
signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init; |
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; |
|
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; |
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; |
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; |
signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; |
|
signal DISPREG : slv16 := (others=>'0'); |
signal STATLEDS : slv8 := (others=>'0'); |
signal ABCLKDIV : slv16 := (others=>'0'); |
|
signal SWI : slv16 := (others=>'0'); |
signal BTN : slv5 := (others=>'0'); |
signal LED : slv16 := (others=>'0'); |
signal DSP_DAT : slv32 := (others=>'0'); |
signal DSP_DP : slv8 := (others=>'0'); |
|
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx |
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx |
constant rbaddr_ibus0 : slv16 := x"4000"; -- 4000/1000: 0100 xxxx xxxx xxxx |
constant rbaddr_core0 : slv16 := x"0000"; -- 0000/0020: 0000 0000 000x xxxx |
|
begin |
|
218,7 → 240,7
report "assert sys_conf_clksys on MHz grid" |
severity failure; |
|
GEN_CLKSYS : s7_cmt_sfs -- clock generator ------------------- |
GEN_CLKSYS : s7_cmt_sfs |
generic map ( |
VCO_DIVIDE => sys_conf_clksys_vcodivide, |
VCO_MULTIPLY => sys_conf_clksys_vcomultiply, |
233,7 → 255,7
LOCKED => open |
); |
|
CLKDIV : clkdivce -- usec/msec clock divider ----------- |
CLKDIV : clkdivce |
generic map ( |
CDUWIDTH => 7, |
USECDIV => sys_conf_clksys_mhz, |
244,7 → 266,7
CE_MSEC => CE_MSEC |
); |
|
IOB_RS232 : bp_rs232_4line_iob -- serport iob ---------------------- |
IOB_RS232 : bp_rs232_4line_iob |
port map ( |
CLK => CLK, |
RXD => RXD, |
257,8 → 279,34
O_RTS_N => O_RTS_N |
); |
|
RLINK : rlink_sp1c -- rlink for serport ----------------- |
HIO : sn_humanio_rbus |
generic map ( |
SWIDTH => 16, |
BWIDTH => 5, |
LWIDTH => 16, |
DCWIDTH => 3, |
DEBOUNCE => sys_conf_hio_debounce, |
RB_ADDR => rbaddr_hio) |
port map ( |
CLK => CLK, |
RESET => RESET, |
CE_MSEC => CE_MSEC, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_HIO, |
SWI => SWI, |
BTN => BTN, |
LED => LED, |
DSP_DAT => DSP_DAT, |
DSP_DP => DSP_DP, |
I_SWI => I_SWI, |
I_BTN => I_BTN, |
O_LED => O_LED, |
O_ANO_N => O_ANO_N, |
O_SEG_N => O_SEG_N |
); |
|
RLINK : rlink_sp1c |
generic map ( |
BTOWIDTH => 7, -- 128 cycles access timeout |
RTAWIDTH => 12, |
SYSID => (others=>'0'), |
267,9 → 315,7
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
ENAPIN_RBMON => sbcntl_sbf_rbmon, |
CDWIDTH => 13, |
CDINIT => sys_conf_ser2rri_cdinit, |
RBMON_AWIDTH => sys_conf_rbmon_awidth, |
RBMON_RBADDR => rbaddr_rbmon) |
CDINIT => sys_conf_ser2rri_cdinit) |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
277,7 → 323,7
CE_INT => CE_MSEC, |
RESET => RESET, |
ENAXON => SWI(1), |
ESCFILL => '0', |
ENAESC => SWI(1), |
RXSD => RXD, |
TXSD => TXD, |
CTS_N => CTS_N, |
290,56 → 336,90
SER_MONI => SER_MONI |
); |
|
SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- |
RB_SRES_OR : rb_sres_or_3 |
port map ( |
CLK => CLK, |
RESET => RESET, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_CPU, |
RB_STAT => RB_STAT, |
RB_LAM_CPU => RB_LAM(0), |
GRESET => GRESET, |
CRESET => CRESET, |
BRESET => BRESET, |
CP_STAT => CP_STAT, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
EI_ACKM => EI_ACKM, |
ITIMER => ITIMER, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_IBDR, |
MEM_REQ => MEM_REQ, |
MEM_WE => MEM_WE, |
MEM_BUSY => MEM_BUSY, |
MEM_ACK_R => MEM_ACK_R, |
MEM_ADDR => MEM_ADDR, |
MEM_BE => MEM_BE, |
MEM_DI => MEM_DI, |
MEM_DO => MEM_DO, |
DM_STAT_DP => DM_STAT_DP |
RB_SRES_1 => RB_SRES_CPU, |
RB_SRES_2 => RB_SRES_IBD, |
RB_SRES_3 => RB_SRES_HIO, |
RB_SRES_OR => RB_SRES |
); |
|
RB2CP : pdp11_core_rbus |
generic map ( |
RB_ADDR_CORE => rbaddr_core0, |
RB_ADDR_IBUS => rbaddr_ibus0) |
port map ( |
CLK => CLK, |
RESET => RESET, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_CPU, |
RB_STAT => RB_STAT, |
RB_LAM => RB_LAM(0), |
CPU_RESET => CPU_RESET, |
CP_CNTL => CP_CNTL, |
CP_ADDR => CP_ADDR, |
CP_DIN => CP_DIN, |
CP_STAT => CP_STAT, |
CP_DOUT => CP_DOUT |
); |
|
IBDR_SYS : ibdr_maxisys -- IO system ------------------------- |
W11A : pdp11_core |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
CE_MSEC => CE_MSEC, |
RESET => GRESET, |
BRESET => BRESET, |
ITIMER => ITIMER, |
CPUSUSP => CP_STAT.cpususp, |
RB_LAM => RB_LAM(15 downto 1), |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_IBDR, |
EI_ACKM => EI_ACKM, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
DISPREG => DISPREG |
CLK => CLK, |
RESET => CPU_RESET, |
CP_CNTL => CP_CNTL, |
CP_ADDR => CP_ADDR, |
CP_DIN => CP_DIN, |
CP_STAT => CP_STAT, |
CP_DOUT => CP_DOUT, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
EI_ACKM => EI_ACKM, |
EM_MREQ => EM_MREQ, |
EM_SRES => EM_SRES, |
BRESET => BRESET, |
IB_MREQ_M => IB_MREQ, |
IB_SRES_M => IB_SRES, |
DM_STAT_DP => DM_STAT_DP, |
DM_STAT_VM => DM_STAT_VM, |
DM_STAT_CO => DM_STAT_CO |
); |
|
CACHE: pdp11_cache |
port map ( |
CLK => CLK, |
GRESET => CPU_RESET, |
EM_MREQ => EM_MREQ, |
EM_SRES => EM_SRES, |
FMISS => CACHE_FMISS, |
CHIT => CACHE_CHIT, |
MEM_REQ => MEM_REQ, |
MEM_WE => MEM_WE, |
MEM_BUSY => MEM_BUSY, |
MEM_ACK_R => MEM_ACK_R, |
MEM_ADDR => MEM_ADDR, |
MEM_BE => MEM_BE, |
MEM_DI => MEM_DI, |
MEM_DO => MEM_DO |
); |
|
|
MEM70: pdp11_mem70 |
port map ( |
CLK => CLK, |
CRESET => BRESET, |
HM_ENA => HM_ENA, |
HM_VAL => CACHE_CHIT, |
CACHE_FMISS => MEM70_FMISS, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_MEM70 |
); |
|
HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; |
CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; |
|
MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) |
|
CRAM_CTL: nx_cram_memctl_as -- memory controller ----------------- |
CRAM_CTL: nx_cram_memctl_as |
generic map ( |
READ0DELAY => sys_conf_memctl_read0delay, |
READ1DELAY => sys_conf_memctl_read1delay, |
346,7 → 426,7
WRITEDELAY => sys_conf_memctl_writedelay) |
port map ( |
CLK => CLK, |
RESET => GRESET, |
RESET => CPU_RESET, |
REQ => MEM_REQ, |
WE => MEM_WE, |
BUSY => MEM_BUSY, |
370,66 → 450,87
IO_MEM_DATA => IO_MEM_DATA |
); |
|
LED_IO : ioleds_sp1c -- hio leds from serport ------------- |
IB_SRES_OR : ib_sres_or_2 |
port map ( |
IB_SRES_1 => IB_SRES_MEM70, |
IB_SRES_2 => IB_SRES_IBDR, |
IB_SRES_OR => IB_SRES |
); |
|
IBDR_SYS : ibdr_maxisys |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
CE_MSEC => CE_MSEC, |
RESET => CPU_RESET, |
BRESET => BRESET, |
RB_LAM => RB_LAM(15 downto 1), |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_IBDR, |
EI_ACKM => EI_ACKM, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
DISPREG => DISPREG |
); |
|
LED_IO : ioleds_sp1c |
port map ( |
SER_MONI => SER_MONI, |
IOLEDS => DSP_DP(3 downto 0) |
); |
DSP_DP(7 downto 4) <= "0010"; |
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; |
|
HIO70 : pdp11_hio70 -- hio from sys70 -------------------- |
generic map ( |
LWIDTH => LED'length, |
DCWIDTH => 3) |
|
LED_CPU : pdp11_statleds |
port map ( |
SEL_LED => SWI(3), |
SEL_DSP => SWI(5 downto 4), |
MEM_ACT_R => MEM_ACT_R, |
MEM_ACT_W => MEM_ACT_W, |
CP_STAT => CP_STAT, |
DM_STAT_DP => DM_STAT_DP, |
ABCLKDIV => ABCLKDIV, |
DISPREG => DISPREG, |
LED => LED, |
DSP_DAT => DSP_DAT |
STATLEDS => STATLEDS |
); |
|
HIO : sn_humanio_rbus -- hio manager ----------------------- |
|
LED_MUX : pdp11_ledmux |
generic map ( |
SWIDTH => 16, |
BWIDTH => 5, |
LWIDTH => 16, |
DCWIDTH => 3, |
DEBOUNCE => sys_conf_hio_debounce, |
RB_ADDR => rbaddr_hio) |
LWIDTH => LED'length) |
port map ( |
CLK => CLK, |
RESET => RESET, |
CE_MSEC => CE_MSEC, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_HIO, |
SWI => SWI, |
BTN => BTN, |
LED => LED, |
DSP_DAT => DSP_DAT, |
DSP_DP => DSP_DP, |
I_SWI => I_SWI, |
I_BTN => I_BTN, |
O_LED => O_LED, |
O_ANO_N => O_ANO_N, |
O_SEG_N => O_SEG_N |
SEL => SWI(3), |
STATLEDS => STATLEDS, |
DM_STAT_DP => DM_STAT_DP, |
LED => LED |
); |
|
RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- |
|
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; |
|
DSP_MUX : pdp11_dspmux |
generic map ( |
DCWIDTH => 3) |
port map ( |
RB_SRES_1 => RB_SRES_CPU, |
RB_SRES_2 => RB_SRES_HIO, |
RB_SRES_OR => RB_SRES |
SEL => SWI(5 downto 4), |
ABCLKDIV => ABCLKDIV, |
DM_STAT_DP => DM_STAT_DP, |
DISPREG => DISPREG, |
DSP_DAT => DSP_DAT |
); |
|
-- setup unused outputs in nexys4 |
O_RGBLED0 <= (others=>'0'); |
O_RGBLED1 <= (others=>not I_BTNRST_N); |
|
-- synthesis translate_off |
DM_STAT_SY.emmreq <= EM_MREQ; |
DM_STAT_SY.emsres <= EM_SRES; |
DM_STAT_SY.chit <= CACHE_CHIT; |
|
TMU : pdp11_tmu_sb |
generic map ( |
ENAPIN => 13) |
port map ( |
CLK => CLK, |
DM_STAT_DP => DM_STAT_DP, |
DM_STAT_VM => DM_STAT_VM, |
DM_STAT_CO => DM_STAT_CO, |
DM_STAT_SY => DM_STAT_SY |
); |
-- synthesis translate_on |
|
end syn; |
/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom
17,14 → 17,21
[ghdl]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom |
../../../vlib/genlib/clkdivce.vbom |
../../../bplib/bpgen/bp_rs232_4line_iob.vbom |
../../../bplib/bpgen/sn_humanio_rbus.vbom |
../../../vlib/rlink/rlink_sp1c.vbom |
../../../w11a/pdp11_sys70.vbom |
../../../vlib/rbus/rb_sres_or_3.vbom |
../../../w11a/pdp11_core_rbus.vbom |
../../../w11a/pdp11_core.vbom |
../../../w11a/pdp11_cache.vbom |
../../../w11a/pdp11_mem70.vbom |
../../../bplib/nxcramlib/nx_cram_memctl_as.vbom |
../../../ibus/ib_sres_or_2.vbom |
../../../ibus/ibdr_maxisys.vbom |
../../../bplib/nxcramlib/nx_cram_memctl_as.vbom |
../../../vlib/rlink/ioleds_sp1c.vbom |
../../../w11a/pdp11_hio70.vbom |
../../../bplib/bpgen/sn_humanio_rbus.vbom |
../../../ibus/ib_sres_or_2.vbom |
../../../w11a/pdp11_statleds.vbom |
../../../w11a/pdp11_ledmux.vbom |
../../../w11a/pdp11_dspmux.vbom |
[sim]../../../w11a/pdp11_tmu_sb.vbom |
# design |
sys_w11a_n4.vhd |
# constraints |
/rtl/sys_gen/w11a/s3board/tb/sys_conf_sim.vhd
1,6 → 1,6
-- $Id: sys_conf_sim.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: sys_conf_sim.vhd 619 2014-12-23 13:17:41Z mueller $ |
-- |
-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
19,7 → 19,6
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions |
-- 2014-12-22 619 1.1.2 add _rbmon_awidth |
-- 2010-05-05 288 1.1.1 add sys_conf_hio_debounce |
-- 2008-02-23 118 1.1 add memory config |
33,15 → 32,10
|
package sys_conf is |
|
-- configure rlink and hio interfaces -------------------------------------- |
constant sys_conf_hio_debounce : boolean := false; -- no debouncers |
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim |
constant sys_conf_hio_debounce : boolean := false; -- no debouncers |
|
-- configure debug and monitoring units ------------------------------------ |
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon |
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon |
|
-- configure w11 cpu core -------------------------------------------------- |
constant sys_conf_bram : integer := 0; -- no bram, use cache |
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB) |
constant sys_conf_mem_losize : integer := 8#037777#; -- 1 MByte |
53,19 → 47,16
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 |
constant sys_conf_ibd_pc11 : boolean := true; -- PC11 |
constant sys_conf_ibd_lp11 : boolean := true; -- LP11 |
|
-- configure mass storage devices |
constant sys_conf_ibd_rk11 : boolean := true; -- RK11 |
constant sys_conf_ibd_rl11 : boolean := true; -- RL11 |
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP |
|
-- configure other devices |
constant sys_conf_ibd_iist : boolean := true; -- IIST |
|
end package sys_conf; |
|
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory |
-- 2 211 111 111 110 000 000 000 |
-- 1 098 765 432 109 876 543 210 |
-- |
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte |
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte |
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte |
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte |
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte |
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte |
-- upper 256 kB excluded for 11/70 UB |
/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd
1,4 → 1,4
-- $Id: sys_w11a_s3.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: sys_w11a_s3.vhd 652 2015-02-28 12:18:08Z mueller $ |
-- |
-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
17,14 → 17,25
-- |
-- Dependencies: vlib/genlib/clkdivce |
-- bplib/bpgen/bp_rs232_2l4l_iob |
-- bplib/bpgen/sn_humanio |
-- vlib/rlink/rlink_sp1c |
-- w11a/pdp11_sys70 |
-- vlib/rbus/rb_sres_or_3 |
-- vlib/rbus/rbd_rbmon |
-- w11a/pdp11_core_rbus |
-- w11a/pdp11_core |
-- w11a/pdp11_bram |
-- vlib/s3board/s3_sram_dummy |
-- w11a/pdp11_cache |
-- w11a/pdp11_mem70 |
-- bplib/s3board/s3_sram_memctl |
-- ibus/ib_sres_or_2 |
-- ibus/ibdr_minisys |
-- ibus/ibdr_maxisys |
-- bplib/s3board/s3_sram_memctl |
-- vlib/rlink/ioleds_sp1c |
-- w11a/pdp11_hio70 |
-- bplib/bpgen/sn_humanio_rbus |
-- vlib/rbus/rb_sres_or_2 |
-- w11a/pdp11_statleds |
-- w11a/pdp11_ledmux |
-- w11a/pdp11_dspmux |
-- w11a/pdp11_tmu_sb [sim only] |
-- |
-- Test bench: tb/tb_sys_w11a_s3 |
-- |
33,7 → 44,6
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2015-05-02 673 14.7 131013 xc3s1000-4 2054 6196 350 3858 OK: +RHRP 50% |
-- 2015-02-21 649 14.7 131013 xc3s1000-4 1643 5124 318 3176 OK: +RL11 |
-- 2014-12-22 619 14.7 131013 xc3s1000-4 1569 4768 302 2994 OK: +rbmon |
-- 2014-12-20 614 14.7 131013 xc3s1000-4 1455 4523 302 2807 OK: -RL11,rlv4 |
73,9 → 83,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul |
-- 2015-05-02 673 2.0 use pdp11_sys70 and pdp11_hio70; now in std form |
-- 2015-04-11 666 1.7.1 rearrange XON handling |
-- 2015-02-21 649 1.7 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) |
-- 2014-12-24 620 1.6.2 relocate ibus window and hio rbus address |
-- 2014-12-22 619 1.6.1 add rbus monitor rbd_rbmon |
179,9 → 186,9
use work.genlib.all; |
use work.serportlib.all; |
use work.rblib.all; |
use work.rbdlib.all; |
use work.rlinklib.all; |
use work.bpgenlib.all; |
use work.bpgenrbuslib.all; |
use work.s3boardlib.all; |
use work.iblib.all; |
use work.ibdlib.all; |
218,19 → 225,16
|
signal CLK : slbit := '0'; |
|
signal RESET : slbit := '0'; |
signal CE_USEC : slbit := '0'; |
signal CE_MSEC : slbit := '0'; |
|
signal RXD : slbit := '1'; |
signal TXD : slbit := '0'; |
signal RTS_N : slbit := '0'; |
signal CTS_N : slbit := '0'; |
|
signal RB_MREQ : rb_mreq_type := rb_mreq_init; |
signal RB_SRES : rb_sres_type := rb_sres_init; |
signal RB_SRES_CPU : rb_sres_type := rb_sres_init; |
signal RB_SRES_HIO : rb_sres_type := rb_sres_init; |
signal SWI : slv8 := (others=>'0'); |
signal BTN : slv4 := (others=>'0'); |
signal LED : slv8 := (others=>'0'); |
signal DSP_DAT : slv16 := (others=>'0'); |
signal DSP_DP : slv4 := (others=>'0'); |
|
signal RB_LAM : slv16 := (others=>'0'); |
signal RB_STAT : slv4 := (others=>'0'); |
237,24 → 241,35
|
signal SER_MONI : serport_moni_type := serport_moni_init; |
|
signal SWI : slv8 := (others=>'0'); |
signal BTN : slv4 := (others=>'0'); |
signal LED : slv8 := (others=>'0'); |
signal DSP_DAT : slv16 := (others=>'0'); |
signal DSP_DP : slv4 := (others=>'0'); |
signal RB_MREQ : rb_mreq_type := rb_mreq_init; |
signal RB_SRES : rb_sres_type := rb_sres_init; |
signal RB_SRES_CPU : rb_sres_type := rb_sres_init; |
signal RB_SRES_IBD : rb_sres_type := rb_sres_init; |
signal RB_SRES_RBMON : rb_sres_type := rb_sres_init; |
|
signal GRESET : slbit := '0'; -- general reset (from rbus) |
signal CRESET : slbit := '0'; -- cpu reset (from cp) |
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) |
signal ITIMER : slbit := '0'; |
signal RESET : slbit := '0'; |
signal CE_USEC : slbit := '0'; |
signal CE_MSEC : slbit := '0'; |
|
signal CPU_RESET : slbit := '0'; |
signal CP_CNTL : cp_cntl_type := cp_cntl_init; |
signal CP_ADDR : cp_addr_type := cp_addr_init; |
signal CP_DIN : slv16 := (others=>'0'); |
signal CP_STAT : cp_stat_type := cp_stat_init; |
signal CP_DOUT : slv16 := (others=>'0'); |
|
signal EI_PRI : slv3 := (others=>'0'); |
signal EI_VECT : slv9_2 := (others=>'0'); |
signal EI_ACKM : slbit := '0'; |
|
signal EM_MREQ : em_mreq_type := em_mreq_init; |
signal EM_SRES : em_sres_type := em_sres_init; |
|
signal HM_ENA : slbit := '0'; |
signal MEM70_FMISS : slbit := '0'; |
signal CACHE_FMISS : slbit := '0'; |
signal CACHE_CHIT : slbit := '0'; |
|
signal CP_STAT : cp_stat_type := cp_stat_init; |
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; |
|
signal MEM_REQ : slbit := '0'; |
signal MEM_WE : slbit := '0'; |
signal MEM_BUSY : slbit := '0'; |
266,9 → 281,18
signal MEM_DI : slv32 := (others=>'0'); |
signal MEM_DO : slv32 := (others=>'0'); |
|
signal BRESET : slbit := '0'; |
signal IB_MREQ : ib_mreq_type := ib_mreq_init; |
signal IB_SRES : ib_sres_type := ib_sres_init; |
|
signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init; |
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; |
|
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; |
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; |
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; |
signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; |
|
signal DISPREG : slv16 := (others=>'0'); |
signal STATLEDS : slv8 := (others=>'0'); |
signal ABCLKDIV : slv16 := (others=>'0'); |
275,12 → 299,14
|
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx |
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx |
constant rbaddr_ibus0 : slv16 := x"4000"; -- 4000/1000: 0100 xxxx xxxx xxxx |
constant rbaddr_core0 : slv16 := x"0000"; -- 0000/0020: 0000 0000 000x xxxx |
|
begin |
|
CLK <= I_CLK50; -- use 50MHz as system clock |
|
CLKDIV : clkdivce -- usec/msec clock divider ----------- |
CLKDIV : clkdivce |
generic map ( |
CDUWIDTH => 6, |
USECDIV => 50, |
291,7 → 317,7
CE_MSEC => CE_MSEC |
); |
|
IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ---------------- |
IOB_RS232 : bp_rs232_2l4l_iob |
port map ( |
CLK => CLK, |
RESET => '0', |
308,8 → 334,27
O_RTS1_N => O_FUSP_RTS_N |
); |
|
RLINK : rlink_sp1c -- rlink for serport ----------------- |
HIO : sn_humanio |
generic map ( |
DEBOUNCE => sys_conf_hio_debounce) |
port map ( |
CLK => CLK, |
RESET => RESET, |
CE_MSEC => CE_MSEC, |
SWI => SWI, |
BTN => BTN, |
LED => LED, |
DSP_DAT => DSP_DAT, |
DSP_DP => DSP_DP, |
I_SWI => I_SWI, |
I_BTN => I_BTN, |
O_LED => O_LED, |
O_ANO_N => O_ANO_N, |
O_SEG_N => O_SEG_N |
); |
|
RLINK : rlink_sp1c |
generic map ( |
BTOWIDTH => 6, -- 64 cycles access timeout |
RTAWIDTH => 12, |
SYSID => (others=>'0'), |
318,9 → 363,7
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
ENAPIN_RBMON => sbcntl_sbf_rbmon, |
CDWIDTH => 13, |
CDINIT => sys_conf_ser2rri_cdinit, |
RBMON_AWIDTH => sys_conf_rbmon_awidth, |
RBMON_RBADDR => rbaddr_rbmon) |
CDINIT => sys_conf_ser2rri_cdinit) |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
328,7 → 371,7
CE_INT => CE_MSEC, |
RESET => RESET, |
ENAXON => SWI(1), |
ESCFILL => '0', |
ENAESC => SWI(1), |
RXSD => RXD, |
TXSD => TXD, |
CTS_N => CTS_N, |
341,127 → 384,263
SER_MONI => SER_MONI |
); |
|
SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- |
RB_SRES_OR : rb_sres_or_3 |
port map ( |
CLK => CLK, |
RESET => RESET, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_CPU, |
RB_STAT => RB_STAT, |
RB_LAM_CPU => RB_LAM(0), |
GRESET => GRESET, |
CRESET => CRESET, |
BRESET => BRESET, |
CP_STAT => CP_STAT, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
EI_ACKM => EI_ACKM, |
ITIMER => ITIMER, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_IBDR, |
MEM_REQ => MEM_REQ, |
MEM_WE => MEM_WE, |
MEM_BUSY => MEM_BUSY, |
MEM_ACK_R => MEM_ACK_R, |
MEM_ADDR => MEM_ADDR, |
MEM_BE => MEM_BE, |
MEM_DI => MEM_DI, |
MEM_DO => MEM_DO, |
DM_STAT_DP => DM_STAT_DP |
RB_SRES_1 => RB_SRES_CPU, |
RB_SRES_2 => RB_SRES_IBD, |
RB_SRES_3 => RB_SRES_RBMON, |
RB_SRES_OR => RB_SRES |
); |
|
IBDR_SYS : ibdr_maxisys -- IO system ------------------------- |
|
RBMON : if sys_conf_rbmon_awidth > 0 generate |
begin |
RBMON : rbd_rbmon |
generic map ( |
RB_ADDR => rbaddr_rbmon, |
AWIDTH => sys_conf_rbmon_awidth) |
port map ( |
CLK => CLK, |
RESET => RESET, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_RBMON, |
RB_SRES_SUM => RB_SRES |
); |
end generate RBMON; |
|
RP2CP : pdp11_core_rbus |
generic map ( |
RB_ADDR_CORE => rbaddr_core0, |
RB_ADDR_IBUS => rbaddr_ibus0) |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
CE_MSEC => CE_MSEC, |
RESET => GRESET, |
BRESET => BRESET, |
ITIMER => ITIMER, |
CPUSUSP => CP_STAT.cpususp, |
RB_LAM => RB_LAM(15 downto 1), |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_IBDR, |
EI_ACKM => EI_ACKM, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
DISPREG => DISPREG); |
CLK => CLK, |
RESET => RESET, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_CPU, |
RB_STAT => RB_STAT, |
RB_LAM => RB_LAM(0), |
CPU_RESET => CPU_RESET, |
CP_CNTL => CP_CNTL, |
CP_ADDR => CP_ADDR, |
CP_DIN => CP_DIN, |
CP_STAT => CP_STAT, |
CP_DOUT => CP_DOUT |
); |
|
SRAM_CTL: s3_sram_memctl -- memory controller ----------------- |
W11A : pdp11_core |
port map ( |
CLK => CLK, |
RESET => GRESET, |
REQ => MEM_REQ, |
WE => MEM_WE, |
BUSY => MEM_BUSY, |
ACK_R => MEM_ACK_R, |
ACK_W => open, |
ACT_R => MEM_ACT_R, |
ACT_W => MEM_ACT_W, |
ADDR => MEM_ADDR(17 downto 0), |
BE => MEM_BE, |
DI => MEM_DI, |
DO => MEM_DO, |
O_MEM_CE_N => O_MEM_CE_N, |
O_MEM_BE_N => O_MEM_BE_N, |
O_MEM_WE_N => O_MEM_WE_N, |
O_MEM_OE_N => O_MEM_OE_N, |
O_MEM_ADDR => O_MEM_ADDR, |
IO_MEM_DATA => IO_MEM_DATA |
); |
CLK => CLK, |
RESET => CPU_RESET, |
CP_CNTL => CP_CNTL, |
CP_ADDR => CP_ADDR, |
CP_DIN => CP_DIN, |
CP_STAT => CP_STAT, |
CP_DOUT => CP_DOUT, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
EI_ACKM => EI_ACKM, |
EM_MREQ => EM_MREQ, |
EM_SRES => EM_SRES, |
BRESET => BRESET, |
IB_MREQ_M => IB_MREQ, |
IB_SRES_M => IB_SRES, |
DM_STAT_DP => DM_STAT_DP, |
DM_STAT_VM => DM_STAT_VM, |
DM_STAT_CO => DM_STAT_CO |
); |
|
MEM_BRAM: if sys_conf_bram > 0 generate |
signal HM_VAL_BRAM : slbit := '0'; |
begin |
|
MEM : pdp11_bram |
generic map ( |
AWIDTH => sys_conf_bram_awidth) |
port map ( |
CLK => CLK, |
GRESET => CPU_RESET, |
EM_MREQ => EM_MREQ, |
EM_SRES => EM_SRES |
); |
|
HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write |
|
MEM70: pdp11_mem70 |
port map ( |
CLK => CLK, |
CRESET => BRESET, |
HM_ENA => EM_MREQ.req, |
HM_VAL => HM_VAL_BRAM, |
CACHE_FMISS => MEM70_FMISS, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_MEM70 |
); |
|
SRAM_PROT : s3_sram_dummy -- connect SRAM to protection dummy |
port map ( |
O_MEM_CE_N => O_MEM_CE_N, |
O_MEM_BE_N => O_MEM_BE_N, |
O_MEM_WE_N => O_MEM_WE_N, |
O_MEM_OE_N => O_MEM_OE_N, |
O_MEM_ADDR => O_MEM_ADDR, |
IO_MEM_DATA => IO_MEM_DATA |
); |
|
end generate MEM_BRAM; |
|
MEM_SRAM: if sys_conf_bram = 0 generate |
|
CACHE: pdp11_cache |
port map ( |
CLK => CLK, |
GRESET => CPU_RESET, |
EM_MREQ => EM_MREQ, |
EM_SRES => EM_SRES, |
FMISS => CACHE_FMISS, |
CHIT => CACHE_CHIT, |
MEM_REQ => MEM_REQ, |
MEM_WE => MEM_WE, |
MEM_BUSY => MEM_BUSY, |
MEM_ACK_R => MEM_ACK_R, |
MEM_ADDR => MEM_ADDR, |
MEM_BE => MEM_BE, |
MEM_DI => MEM_DI, |
MEM_DO => MEM_DO |
); |
|
MEM70: pdp11_mem70 |
port map ( |
CLK => CLK, |
CRESET => BRESET, |
HM_ENA => HM_ENA, |
HM_VAL => CACHE_CHIT, |
CACHE_FMISS => MEM70_FMISS, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_MEM70 |
); |
|
HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; |
CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; |
|
SRAM_CTL: s3_sram_memctl |
port map ( |
CLK => CLK, |
RESET => CPU_RESET, |
REQ => MEM_REQ, |
WE => MEM_WE, |
BUSY => MEM_BUSY, |
ACK_R => MEM_ACK_R, |
ACK_W => open, |
ACT_R => MEM_ACT_R, |
ACT_W => MEM_ACT_W, |
ADDR => MEM_ADDR(17 downto 0), |
BE => MEM_BE, |
DI => MEM_DI, |
DO => MEM_DO, |
O_MEM_CE_N => O_MEM_CE_N, |
O_MEM_BE_N => O_MEM_BE_N, |
O_MEM_WE_N => O_MEM_WE_N, |
O_MEM_OE_N => O_MEM_OE_N, |
O_MEM_ADDR => O_MEM_ADDR, |
IO_MEM_DATA => IO_MEM_DATA |
); |
|
end generate MEM_SRAM; |
|
LED_IO : ioleds_sp1c -- hio leds from serport ------------- |
IB_SRES_OR : ib_sres_or_2 |
port map ( |
IB_SRES_1 => IB_SRES_MEM70, |
IB_SRES_2 => IB_SRES_IBDR, |
IB_SRES_OR => IB_SRES); |
|
IBD_MINI : if false generate |
begin |
IBDR_SYS : ibdr_minisys |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
CE_MSEC => CE_MSEC, |
RESET => CPU_RESET, |
BRESET => BRESET, |
RB_LAM => RB_LAM(15 downto 1), |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_IBDR, |
EI_ACKM => EI_ACKM, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
DISPREG => DISPREG); |
end generate IBD_MINI; |
|
IBD_MAXI : if true generate |
begin |
IBDR_SYS : ibdr_maxisys |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
CE_MSEC => CE_MSEC, |
RESET => CPU_RESET, |
BRESET => BRESET, |
RB_LAM => RB_LAM(15 downto 1), |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_IBDR, |
EI_ACKM => EI_ACKM, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
DISPREG => DISPREG); |
end generate IBD_MAXI; |
|
LED_IO : ioleds_sp1c |
port map ( |
SER_MONI => SER_MONI, |
IOLEDS => DSP_DP |
); |
|
LED_CPU : pdp11_statleds |
port map ( |
MEM_ACT_R => MEM_ACT_R, |
MEM_ACT_W => MEM_ACT_W, |
CP_STAT => CP_STAT, |
DM_STAT_DP => DM_STAT_DP, |
STATLEDS => STATLEDS |
); |
|
LED_MUX : pdp11_ledmux |
generic map ( |
LWIDTH => LED'length) |
port map ( |
SEL => SWI(3), |
STATLEDS => STATLEDS, |
DM_STAT_DP => DM_STAT_DP, |
LED => LED |
); |
|
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; |
|
HIO70 : pdp11_hio70 -- hio from sys70 -------------------- |
DSP_MUX : pdp11_dspmux |
generic map ( |
LWIDTH => LED'length, |
DCWIDTH => 2) |
port map ( |
SEL_LED => SWI(3), |
SEL_DSP => SWI(5 downto 4), |
MEM_ACT_R => MEM_ACT_R, |
MEM_ACT_W => MEM_ACT_W, |
CP_STAT => CP_STAT, |
SEL => SWI(5 downto 4), |
ABCLKDIV => ABCLKDIV, |
DM_STAT_DP => DM_STAT_DP, |
ABCLKDIV => ABCLKDIV, |
DISPREG => DISPREG, |
LED => LED, |
DSP_DAT => DSP_DAT |
); |
|
HIO : sn_humanio_rbus -- hio manager ----------------------- |
|
-- synthesis translate_off |
DM_STAT_SY.emmreq <= EM_MREQ; |
DM_STAT_SY.emsres <= EM_SRES; |
DM_STAT_SY.chit <= CACHE_CHIT; |
|
TMU : pdp11_tmu_sb |
generic map ( |
DEBOUNCE => sys_conf_hio_debounce, |
RB_ADDR => rbaddr_hio) |
ENAPIN => 13) |
port map ( |
CLK => CLK, |
RESET => RESET, |
CE_MSEC => CE_MSEC, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_HIO, |
SWI => SWI, |
BTN => BTN, |
LED => LED, |
DSP_DAT => DSP_DAT, |
DSP_DP => DSP_DP, |
I_SWI => I_SWI, |
I_BTN => I_BTN, |
O_LED => O_LED, |
O_ANO_N => O_ANO_N, |
O_SEG_N => O_SEG_N |
CLK => CLK, |
DM_STAT_DP => DM_STAT_DP, |
DM_STAT_VM => DM_STAT_VM, |
DM_STAT_CO => DM_STAT_CO, |
DM_STAT_SY => DM_STAT_SY |
); |
|
RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- |
port map ( |
RB_SRES_1 => RB_SRES_CPU, |
RB_SRES_2 => RB_SRES_HIO, |
RB_SRES_OR => RB_SRES |
); |
|
-- synthesis translate_on |
|
end syn; |
/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom
3,9 → 3,9
../../../vlib/genlib/genlib.vhd |
../../../vlib/serport/serportlib.vbom |
../../../vlib/rbus/rblib.vhd |
../../../vlib/rbus/rbdlib.vhd |
../../../vlib/rlink/rlinklib.vbom |
../../../bplib/bpgen/bpgenlib.vbom |
../../../bplib/bpgen/bpgenrbuslib.vbom |
../../../bplib/s3board/s3boardlib.vbom |
../../../ibus/iblib.vhd |
../../../ibus/ibdlib.vhd |
14,14 → 14,25
# components |
../../../vlib/genlib/clkdivce.vbom |
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom |
../../../bplib/bpgen/sn_humanio.vbom |
../../../vlib/rlink/rlink_sp1c.vbom |
../../../w11a/pdp11_sys70.vbom |
../../../vlib/rbus/rb_sres_or_3.vbom |
../../../vlib/rbus/rbd_rbmon.vbom |
../../../w11a/pdp11_core_rbus.vbom |
../../../w11a/pdp11_core.vbom |
../../../w11a/pdp11_bram.vbom |
../../../bplib/s3board/s3_sram_dummy.vbom |
../../../w11a/pdp11_cache.vbom |
../../../w11a/pdp11_mem70.vbom |
../../../bplib/s3board/s3_sram_memctl.vbom |
../../../ibus/ib_sres_or_2.vbom |
../../../ibus/ibdr_minisys.vbom |
../../../ibus/ibdr_maxisys.vbom |
../../../bplib/s3board/s3_sram_memctl.vbom |
../../../vlib/rlink/ioleds_sp1c.vbom |
../../../w11a/pdp11_hio70.vbom |
../../../bplib/bpgen/sn_humanio_rbus.vbom |
../../../vlib/rbus/rb_sres_or_2.vbom |
../../../w11a/pdp11_statleds.vbom |
../../../w11a/pdp11_ledmux.vbom |
../../../w11a/pdp11_dspmux.vbom |
[sim]../../../w11a/pdp11_tmu_sb.vbom |
# design |
sys_w11a_s3.vhd |
@ucf_cpp: sys_w11a_s3.ucf |
/rtl/sys_gen/w11a/s3board/sys_conf.vhd
1,6 → 1,6
-- $Id: sys_conf.vhd 673 2015-05-03 08:34:52Z mueller $ |
-- $Id: sys_conf.vhd 619 2014-12-23 13:17:41Z mueller $ |
-- |
-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
19,7 → 19,6
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions |
-- 2014-12-22 619 1.1.2 add _rbmon_awidth |
-- 2010-05-05 288 1.1.1 add sys_conf_hio_debounce |
-- 2008-02-23 118 1.1 add memory config |
33,31 → 32,31
|
package sys_conf is |
|
-- configure rlink and hio interfaces -------------------------------------- |
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers |
constant sys_conf_ser2rri_cdinit : integer := 434-1; -- 50000000/115200 |
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers |
|
-- configure debug and monitoring units ------------------------------------ |
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon |
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon |
|
-- configure w11 cpu core -------------------------------------------------- |
constant sys_conf_bram : integer := 0; -- no bram, use cache |
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB) |
constant sys_conf_mem_losize : integer := 8#037777#; -- 1 MByte |
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) |
|
-- constant sys_conf_bram : integer := 1; -- bram only |
-- constant sys_conf_bram_awidth : integer := 15; -- bram size (32 kB) |
-- constant sys_conf_mem_losize : integer := 8#000777#; -- 32 kByte |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 |
constant sys_conf_ibd_pc11 : boolean := true; -- PC11 |
constant sys_conf_ibd_lp11 : boolean := true; -- LP11 |
end package sys_conf; |
|
-- configure mass storage devices |
constant sys_conf_ibd_rk11 : boolean := true; -- RK11 |
constant sys_conf_ibd_rl11 : boolean := true; -- RL11 |
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP |
|
-- configure other devices |
constant sys_conf_ibd_iist : boolean := true; -- IIST |
|
end package sys_conf; |
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory |
-- 2 211 111 111 110 000 000 000 |
-- 1 098 765 432 109 876 543 210 |
-- |
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte |
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte |
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte |
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte |
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte |
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte |
-- upper 256 kB excluded for 11/70 UB |
/rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vhd
1,6 → 1,6
-- $Id: tst_rlink_cuff.vhd 666 2015-04-12 21:17:54Z mueller $ |
-- $Id: tst_rlink_cuff.vhd 593 2014-09-14 22:21:33Z mueller $ |
-- |
-- Copyright 2012-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2012-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
29,7 → 29,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-11 666 1.2 rearrange XON handling |
-- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT |
-- 2013-01-02 467 1.0.1 use 64 usec led pulse width |
-- 2012-12-29 466 1.0 Initial version |
128,8 → 127,6
CLK => CLK, |
CE_INT => CE_MSEC, |
RESET => RESET, |
ESCXON => SWI(1), |
ESCFILL => '0', |
RLB_DI => RLB_DI, |
RLB_ENA => RLB_ENA, |
RLB_BUSY => RLB_BUSY, |
177,7 → 174,7
CE_MSEC => CE_MSEC, |
RESET => RESET, |
ENAXON => SWI(1), |
ENAESC => '0', -- escaping now in rlink_core8 |
ENAESC => SWI(1), |
RXDATA => SER_RXDATA, |
RXVAL => SER_RXVAL, |
RXHOLD => SER_RXHOLD, |
/rtl/bplib/fx2rlink/rlink_sp1c_fx2.vhd
1,6 → 1,6
-- $Id: rlink_sp1c_fx2.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: rlink_sp1c_fx2.vhd 610 2014-12-09 22:44:43Z mueller $ |
-- |
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
19,23 → 19,18
-- serport/serport_1clock |
-- rlinklib/rlink_rlbmux |
-- fx2lib/fx2_2fifoctl_ic |
-- rbus/rbd_rbmon |
-- rbus/rb_sres_or_2 |
-- |
-- Test bench: - |
-- |
-- Target Devices: generic |
-- Tool versions: xst 13.1-14.7; viv 2014.4; ghdl 0.29-0.31 |
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa |
-- 2015-05-02 672 14.7 131013 xc6slx16-2 618 875 90 340 s 7.2 - - |
-- 2013-04-20 509 13.3 O76d xc3s1200e-4 441 903 128 637 s 8.7 - - |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-02 672 1.3 add rbd_rbmon (optional via generics) |
-- 2015-04-11 666 1.2 drop ENAESC, rearrange XON handling |
-- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT |
-- 2013-04-20 509 1.0 Initial version (derived from rlink_sp1c) |
------------------------------------------------------------------------------ |
46,7 → 41,6
|
use work.slvtypes.all; |
use work.rblib.all; |
use work.rbdlib.all; |
use work.rlinklib.all; |
use work.serportlib.all; |
use work.fx2lib.all; |
64,9 → 58,7
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none) |
ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none) |
CDWIDTH : positive := 13; -- clk divider width |
CDINIT : natural := 15; -- clk divider initial/reset setting |
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none) |
RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr |
CDINIT : natural := 15); -- clk divider initial/reset setting |
port ( |
CLK : in slbit; -- clock |
CE_USEC : in slbit; -- 1 usec clock enable |
74,6 → 66,7
CE_INT : in slbit := '0'; -- rri ato time unit clock enable |
RESET : in slbit; -- reset |
ENAXON : in slbit; -- enable xon/xoff handling |
ENAESC : in slbit; -- enable xon/xoff escaping |
ENAFX2 : in slbit; -- enable fx2 usage |
RXSD : in slbit; -- receive serial data (board view) |
TXSD : out slbit; -- transmit serial data (board view) |
124,13 → 117,9
signal FX2_TXBUSY : slbit := '0'; |
signal FX2_TXAFULL : slbit := '0'; |
|
signal RB_MREQ_M : rb_mreq_type := rb_mreq_init; |
signal RB_SRES_M : rb_sres_type := rb_sres_init; |
signal RB_SRES_RBMON : rb_sres_type := rb_sres_init; |
|
begin |
|
CORE : rlink_core8 -- rlink master ---------------------- |
CORE : rlink_core8 |
generic map ( |
BTOWIDTH => BTOWIDTH, |
RTAWIDTH => RTAWIDTH, |
142,8 → 131,6
CLK => CLK, |
CE_INT => CE_INT, |
RESET => RESET, |
ESCXON => ENAXON, |
ESCFILL => '0', -- not used in FX2 enabled boards |
RLB_DI => RLB_DI, |
RLB_ENA => RLB_ENA, |
RLB_BUSY => RLB_BUSY, |
151,13 → 138,13
RLB_VAL => RLB_VAL, |
RLB_HOLD => RLB_HOLD, |
RL_MONI => RL_MONI, |
RB_MREQ => RB_MREQ_M, |
RB_SRES => RB_SRES_M, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES, |
RB_LAM => RB_LAM, |
RB_STAT => RB_STAT |
); |
|
SERPORT : serport_1clock -- serport interface ----------------- |
SERPORT : serport_1clock |
generic map ( |
CDWIDTH => CDWIDTH, |
CDINIT => CDINIT, |
168,7 → 155,7
CE_MSEC => CE_MSEC, |
RESET => RESET, |
ENAXON => ENAXON, |
ENAESC => '0', -- escaping now in rlink_core8 |
ENAESC => ENAESC, |
RXDATA => SER_RXDATA, |
RXVAL => SER_RXVAL, |
RXHOLD => SER_RXHOLD, |
182,7 → 169,7
TXCTS_N => CTS_N |
); |
|
RLBMUX : rlink_rlbmux -- rlink control mux ----------------- |
RLBMUX : rlink_rlbmux |
port map ( |
SEL => ENAFX2, |
RLB_DI => RLB_DI, |
205,12 → 192,7
P1_TXBUSY => FX2_TXBUSY |
); |
|
RLB_MONI.rxval <= RLB_VAL; |
RLB_MONI.rxhold <= RLB_HOLD; |
RLB_MONI.txena <= RLB_ENA; |
RLB_MONI.txbusy <= RLB_BUSY; |
|
FX2CNTL : fx2_2fifoctl_ic -- FX2 interface --------------------- |
FX2CNTL : fx2_2fifoctl_ic |
generic map ( |
RXFAWIDTH => 5, |
TXFAWIDTH => 5, |
240,28 → 222,9
IO_FX2_DATA => IO_FX2_DATA |
); |
|
RBMON : if RBMON_AWIDTH > 0 generate -- rbus monitor -------------- |
begin |
I0 : rbd_rbmon |
generic map ( |
RB_ADDR => RBMON_RBADDR, |
AWIDTH => RBMON_AWIDTH) |
port map ( |
CLK => CLK, |
RESET => RESET, |
RB_MREQ => RB_MREQ_M, |
RB_SRES => RB_SRES_RBMON, |
RB_SRES_SUM => RB_SRES_M |
); |
end generate RBMON; |
|
RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- |
port map ( |
RB_SRES_1 => RB_SRES, |
RB_SRES_2 => RB_SRES_RBMON, |
RB_SRES_OR => RB_SRES_M |
); |
|
RB_MREQ <= RB_MREQ_M; -- setup output signals |
RLB_MONI.rxval <= RLB_VAL; |
RLB_MONI.rxhold <= RLB_HOLD; |
RLB_MONI.txena <= RLB_ENA; |
RLB_MONI.txbusy <= RLB_BUSY; |
|
end syn; |
/rtl/bplib/fx2rlink/fx2rlinklib.vhd
1,6 → 1,6
-- $Id: fx2rlinklib.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: fx2rlinklib.vhd 610 2014-12-09 22:44:43Z mueller $ |
-- |
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
20,7 → 20,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-11 666 1.2 rlink_sp1c_fx2: drop ENAESC |
-- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT |
-- 2013-04-20 509 1.0 Initial version |
------------------------------------------------------------------------------ |
54,9 → 53,7
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none) |
ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none) |
CDWIDTH : positive := 13; -- clk divider width |
CDINIT : natural := 15; -- clk divider initial/reset setting |
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size (0=none) |
RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr |
CDINIT : natural := 15); -- clk divider initial/reset setting |
port ( |
CLK : in slbit; -- clock |
CE_USEC : in slbit; -- 1 usec clock enable |
64,6 → 61,7
CE_INT : in slbit := '0'; -- rri ato time unit clock enable |
RESET : in slbit; -- reset |
ENAXON : in slbit; -- enable xon/xoff handling |
ENAESC : in slbit; -- enable xon/xoff escaping |
ENAFX2 : in slbit; -- enable fx2 usage |
RXSD : in slbit; -- receive serial data (board view) |
TXSD : out slbit; -- transmit serial data (board view) |
/rtl/bplib/fx2rlink/rlink_sp1c_fx2.vbom
1,12 → 1,9
# libs |
../../vlib/slvtypes.vhd |
../../vlib/rbus/rblib.vhd |
../../vlib/rbus/rbdlib.vhd |
../../vlib/rlink/rlinklib.vbom |
../../vlib/serport/serportlib.vbom |
../fx2lib/fx2lib.vhd |
../../vlib/rbus/rbd_rbmon.vbom |
../../vlib/rbus/rb_sres_or_2.vbom |
# components |
../../vlib/rlink/rlink_core8.vbom |
../../vlib/serport/serport_1clock.vbom |
/rtl/bplib/basys3/tb/tb_basys3.vhd
1,4 → 1,4
-- $Id: tb_basys3.vhd 666 2015-04-12 21:17:54Z mueller $ |
-- $Id: tb_basys3.vhd 648 2015-02-20 20:16:21Z mueller $ |
-- |
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
20,7 → 20,7
-- rlink/tb/tbcore_rlink |
-- xlib/s7_cmt_sfs |
-- tb_basys3_core |
-- serport/serport_master |
-- serport/serport_uart_rxtx |
-- basys3_aif [UUT] |
-- |
-- To test: generic, any basys3_aif target |
30,7 → 30,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-12 666 1.1 use serport_master instead of serport_uart_rxtx |
-- 2015-02-18 648 1.0 Initial version (derived from tb_nexys4) |
------------------------------------------------------------------------------ |
|
79,10 → 78,6
signal O_ANO_N : slv4 := (others=>'0'); |
signal O_SEG_N : slv8 := (others=>'0'); |
|
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff |
|
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); |
|
constant clock_period : time := 10 ns; |
constant clock_offset : time := 200 ns; |
|
143,26 → 138,22
O_SEG_N => O_SEG_N |
); |
|
SERMSTR : serport_master |
UART : serport_uart_rxtx |
generic map ( |
CDWIDTH => CLKDIV'length) |
port map ( |
CLK => CLKCOM, |
RESET => RESET, |
CLKDIV => CLKDIV, |
ENAXON => R_PORTSEL_XON, |
ENAESC => '0', |
RXDATA => RXDATA, |
RXVAL => RXVAL, |
RXERR => RXERR, |
RXOK => '1', |
TXDATA => TXDATA, |
TXENA => TXENA, |
TXBUSY => TXBUSY, |
RXSD => O_TXD, |
TXSD => I_RXD, |
RXRTS_N => open, |
TXCTS_N => '0' |
CLK => CLKCOM, |
RESET => RESET, |
CLKDIV => CLKDIV, |
RXSD => O_TXD, |
RXDATA => RXDATA, |
RXVAL => RXVAL, |
RXERR => RXERR, |
RXACT => RXACT, |
TXSD => I_RXD, |
TXDATA => TXDATA, |
TXENA => TXENA, |
TXBUSY => TXBUSY |
); |
|
proc_moni: process |
181,13 → 172,4
|
end process proc_moni; |
|
proc_simbus: process (SB_VAL) |
begin |
if SB_VAL'event and to_x01(SB_VAL)='1' then |
if SB_ADDR = sbaddr_portsel then |
R_PORTSEL_XON <= to_x01(SB_DATA(1)); |
end if; |
end if; |
end process proc_simbus; |
|
end sim; |
/rtl/bplib/basys3/tb/tb_basys3.vbom
18,7 → 18,7
../../../vlib/rlink/tb/tbcore_rlink.vbom |
../../../vlib/xlib/s7_cmt_sfs_gsim.vbom |
tb_basys3_core.vbom |
../../../vlib/serport/serport_master.vbom |
../../../vlib/serport/serport_uart_rxtx.vbom |
${basys3_aif := basys3_dummy.vbom} |
# design |
tb_basys3.vhd |
/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
1,6 → 1,6
-- $Id: tb_nexys2_fusp.vhd 666 2015-04-12 21:17:54Z mueller $ |
-- $Id: tb_nexys2_fusp.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
20,7 → 20,7
-- xlib/dcm_sfs |
-- rlink/tb/tbcore_rlink |
-- tb_nexys2_core |
-- serport/serport_master |
-- serport/serport_uart_rxtx |
-- nexys2_fusp_aif [UUT] |
-- |
-- To test: generic, any nexys2_fusp_aif target |
30,7 → 30,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-12 666 3.3 use serport_master instead of serport_uart_rxtx |
-- 2011-12-23 444 3.2 new system clock scheme, new tbcore_rlink iface |
-- 2011-11-26 433 3.1.1 remove O_FLA_CE_N from tb_nexys2_core |
-- 2011-11-21 432 3.1 update O_FLA_CE_N usage |
111,8 → 110,7
signal CTS_N : slbit := '0'; |
signal RTS_N : slbit := '0'; |
|
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport |
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff |
signal R_PORTSEL : slbit := '0'; |
|
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); |
|
199,33 → 197,29
O_FUSP_TXD => O_FUSP_TXD |
); |
|
SERMSTR : serport_master |
UART : serport_uart_rxtx |
generic map ( |
CDWIDTH => CLKDIV'length) |
port map ( |
CLK => CLKCOM, |
RESET => UART_RESET, |
CLKDIV => CLKDIV, |
ENAXON => R_PORTSEL_XON, |
ENAESC => '0', |
RXDATA => RXDATA, |
RXVAL => RXVAL, |
RXERR => RXERR, |
RXOK => '1', |
TXDATA => TXDATA, |
TXENA => TXENA, |
TXBUSY => TXBUSY, |
RXSD => UART_RXD, |
TXSD => UART_TXD, |
RXRTS_N => RTS_N, |
TXCTS_N => CTS_N |
CLK => CLKCOM, |
RESET => UART_RESET, |
CLKDIV => CLKDIV, |
RXSD => UART_RXD, |
RXDATA => RXDATA, |
RXVAL => RXVAL, |
RXERR => RXERR, |
RXACT => RXACT, |
TXSD => UART_TXD, |
TXDATA => TXDATA, |
TXENA => TXENA, |
TXBUSY => TXBUSY |
); |
|
proc_port_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N, |
proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N, |
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N) |
begin |
|
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl |
if R_PORTSEL = '0' then -- use main board rs232, no flow cntl |
I_RXD <= UART_TXD; -- write port 0 inputs |
UART_RXD <= O_TXD; -- get port 0 outputs |
RTS_N <= '0'; |
261,8 → 255,7
begin |
if SB_VAL'event and to_x01(SB_VAL)='1' then |
if SB_ADDR = sbaddr_portsel then |
R_PORTSEL_SER <= to_x01(SB_DATA(0)); |
R_PORTSEL_XON <= to_x01(SB_DATA(1)); |
R_PORTSEL <= to_x01(SB_DATA(0)); |
end if; |
end if; |
end process proc_simbus; |
/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd
1,6 → 1,6
-- $Id: tb_nexys2_fusp_cuff.vhd 666 2015-04-12 21:17:54Z mueller $ |
-- $Id: tb_nexys2_fusp_cuff.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
20,7 → 20,7
-- xlib/dcm_sfs |
-- rlink/tb/tbcore_rlink_dcm |
-- tb_nexys2_core |
-- serport/serport_master |
-- serport/serport_uart_rxtx |
-- fx2lib/tb/fx2_2fifo_core |
-- nexys2_fusp_cuff_aif [UUT] |
-- |
31,7 → 31,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx |
-- 2013-01-03 469 1.1 add fx2 model and data path |
-- 2013-01-01 467 1.0 Initial version (derived from tb_nexys2_fusp) |
------------------------------------------------------------------------------ |
127,7 → 126,6
signal RTS_N : slbit := '0'; |
|
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport |
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff |
signal R_PORTSEL_FX2 : slbit := '0'; -- if 1 use fx2 |
|
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); |
223,26 → 221,22
IO_FX2_DATA => IO_FX2_DATA |
); |
|
SERMSTR : serport_master |
UART : serport_uart_rxtx |
generic map ( |
CDWIDTH => CLKDIV'length) |
port map ( |
CLK => CLKCOM, |
RESET => UART_RESET, |
CLKDIV => CLKDIV, |
ENAXON => R_PORTSEL_XON, |
ENAESC => '0', |
RXDATA => UART_RXDATA, |
RXVAL => UART_RXVAL, |
RXERR => UART_RXERR, |
RXOK => '1', |
TXDATA => UART_TXDATA, |
TXENA => UART_TXENA, |
TXBUSY => UART_TXBUSY, |
RXSD => UART_RXD, |
TXSD => UART_TXD, |
RXRTS_N => RTS_N, |
TXCTS_N => CTS_N |
CLK => CLKCOM, |
RESET => UART_RESET, |
CLKDIV => CLKDIV, |
RXSD => UART_RXD, |
RXDATA => UART_RXDATA, |
RXVAL => UART_RXVAL, |
RXERR => UART_RXERR, |
RXACT => UART_RXACT, |
TXSD => UART_TXD, |
TXDATA => UART_TXDATA, |
TXENA => UART_TXENA, |
TXBUSY => UART_TXBUSY |
); |
|
FX2 : entity work.fx2_2fifo_core |
327,8 → 321,7
if SB_VAL'event and to_x01(SB_VAL)='1' then |
if SB_ADDR = sbaddr_portsel then |
R_PORTSEL_SER <= to_x01(SB_DATA(0)); |
R_PORTSEL_XON <= to_x01(SB_DATA(1)); |
R_PORTSEL_FX2 <= to_x01(SB_DATA(2)); |
R_PORTSEL_FX2 <= to_x01(SB_DATA(1)); |
end if; |
end if; |
end process proc_simbus; |
/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom
18,7 → 18,7
../../../vlib/rlink/tb/tbcore_rlink.vbom |
../../../vlib/xlib/dcm_sfs_gsim.vbom |
tb_nexys2_core.vbom |
../../../vlib/serport/serport_master.vbom |
../../../vlib/serport/serport_uart_rxtx.vbom |
../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom |
${nexys2_fusp_cuff_aif := nexys2_fusp_cuff_dummy.vbom} |
# design |
/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom
18,7 → 18,7
../../../vlib/rlink/tb/tbcore_rlink.vbom |
../../../vlib/xlib/dcm_sfs_gsim.vbom |
tb_nexys2_core.vbom |
../../../vlib/serport/serport_master.vbom |
../../../vlib/serport/serport_uart_rxtx.vbom |
${nexys2_fusp_aif := nexys2_fusp_dummy.vbom} |
# design |
tb_nexys2_fusp.vhd |
/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd
1,6 → 1,6
-- $Id: tb_nexys3_fusp.vhd 666 2015-04-12 21:17:54Z mueller $ |
-- $Id: tb_nexys3_fusp.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
20,7 → 20,7
-- xlib/s6_cmt_sfs |
-- rlink/tb/tbcore_rlink |
-- tb_nexys3_core |
-- serport/serport_master |
-- serport/serport_uart_rxtx |
-- nexys3_fusp_aif [UUT] |
-- |
-- To test: generic, any nexys3_fusp_aif target |
30,7 → 30,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx |
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect |
-- 2011-12-23 444 1.1 new system clock scheme, new tbcore_rlink iface |
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_fusp) |
107,8 → 106,7
signal CTS_N : slbit := '0'; |
signal RTS_N : slbit := '0'; |
|
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport |
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff |
signal R_PORTSEL : slbit := '0'; |
|
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); |
|
200,33 → 198,29
O_FUSP_TXD => O_FUSP_TXD |
); |
|
SERMSTR : serport_master |
UART : serport_uart_rxtx |
generic map ( |
CDWIDTH => CLKDIV'length) |
port map ( |
CLK => CLKCOM, |
RESET => UART_RESET, |
CLKDIV => CLKDIV, |
ENAXON => R_PORTSEL_XON, |
ENAESC => '0', |
RXDATA => RXDATA, |
RXVAL => RXVAL, |
RXERR => RXERR, |
RXOK => '1', |
TXDATA => TXDATA, |
TXENA => TXENA, |
TXBUSY => TXBUSY, |
RXSD => UART_RXD, |
TXSD => UART_TXD, |
RXRTS_N => RTS_N, |
TXCTS_N => CTS_N |
CLK => CLKCOM, |
RESET => UART_RESET, |
CLKDIV => CLKDIV, |
RXSD => UART_RXD, |
RXDATA => RXDATA, |
RXVAL => RXVAL, |
RXERR => RXERR, |
RXACT => RXACT, |
TXSD => UART_TXD, |
TXDATA => TXDATA, |
TXENA => TXENA, |
TXBUSY => TXBUSY |
); |
|
proc_port_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N, |
proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N, |
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N) |
begin |
|
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl |
if R_PORTSEL = '0' then -- use main board rs232, no flow cntl |
I_RXD <= UART_TXD; -- write port 0 inputs |
UART_RXD <= O_TXD; -- get port 0 outputs |
RTS_N <= '0'; |
262,8 → 256,7
begin |
if SB_VAL'event and to_x01(SB_VAL)='1' then |
if SB_ADDR = sbaddr_portsel then |
R_PORTSEL_SER <= to_x01(SB_DATA(0)); |
R_PORTSEL_XON <= to_x01(SB_DATA(1)); |
R_PORTSEL <= to_x01(SB_DATA(0)); |
end if; |
end if; |
end process proc_simbus; |
/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd
1,6 → 1,6
-- $Id: tb_nexys3_fusp_cuff.vhd 666 2015-04-12 21:17:54Z mueller $ |
-- $Id: tb_nexys3_fusp_cuff.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
20,7 → 20,7
-- xlib/s6_cmt_sfs |
-- rlink/tb/tbcore_rlink |
-- tb_nexys3_core |
-- serport/serport_master |
-- serport/serport_uart_rxtx |
-- fx2lib/tb/fx2_2fifo_core |
-- nexys3_fusp_cuff_aif [UUT] |
-- |
31,7 → 31,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx |
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect |
-- 2013-04-21 509 1.0 Initial version (derived from tb_nexys3_fusp and |
-- tb_nexys2_fusp_cuff) |
76,6 → 75,7
signal UART_RXDATA : slv8 := (others=>'0'); |
signal UART_RXVAL : slbit := '0'; |
signal UART_RXERR : slbit := '0'; |
signal UART_RXACT : slbit := '0'; |
signal UART_TXDATA : slv8 := (others=>'0'); |
signal UART_TXENA : slbit := '0'; |
signal UART_TXBUSY : slbit := '0'; |
128,7 → 128,6
signal RTS_N : slbit := '0'; |
|
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport |
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff |
signal R_PORTSEL_FX2 : slbit := '0'; -- if 1 use fx2 |
|
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); |
229,26 → 228,22
IO_FX2_DATA => IO_FX2_DATA |
); |
|
SERMSTR : serport_master |
UART : serport_uart_rxtx |
generic map ( |
CDWIDTH => CLKDIV'length) |
port map ( |
CLK => CLKCOM, |
RESET => UART_RESET, |
CLKDIV => CLKDIV, |
ENAXON => R_PORTSEL_XON, |
ENAESC => '0', |
RXDATA => UART_RXDATA, |
RXVAL => UART_RXVAL, |
RXERR => UART_RXERR, |
RXOK => '1', |
TXDATA => UART_TXDATA, |
TXENA => UART_TXENA, |
TXBUSY => UART_TXBUSY, |
RXSD => UART_RXD, |
TXSD => UART_TXD, |
RXRTS_N => RTS_N, |
TXCTS_N => CTS_N |
CLK => CLKCOM, |
RESET => UART_RESET, |
CLKDIV => CLKDIV, |
RXSD => UART_RXD, |
RXDATA => UART_RXDATA, |
RXVAL => UART_RXVAL, |
RXERR => UART_RXERR, |
RXACT => UART_RXACT, |
TXSD => UART_TXD, |
TXDATA => UART_TXDATA, |
TXENA => UART_TXENA, |
TXBUSY => UART_TXBUSY |
); |
|
FX2 : entity work.fx2_2fifo_core |
333,8 → 328,7
if SB_VAL'event and to_x01(SB_VAL)='1' then |
if SB_ADDR = sbaddr_portsel then |
R_PORTSEL_SER <= to_x01(SB_DATA(0)); |
R_PORTSEL_XON <= to_x01(SB_DATA(1)); |
R_PORTSEL_FX2 <= to_x01(SB_DATA(2)); |
R_PORTSEL_FX2 <= to_x01(SB_DATA(1)); |
end if; |
end if; |
end process proc_simbus; |
/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom
18,7 → 18,7
../../../vlib/rlink/tb/tbcore_rlink.vbom |
../../../vlib/xlib/s6_cmt_sfs_gsim.vbom |
tb_nexys3_core.vbom |
../../../vlib/serport/serport_master.vbom |
../../../vlib/serport/serport_uart_rxtx.vbom |
../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom |
${nexys3_fusp_cuff_aif := nexys3_fusp_cuff_dummy.vbom} |
# design |
/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom
18,7 → 18,7
../../../vlib/rlink/tb/tbcore_rlink.vbom |
../../../vlib/xlib/s6_cmt_sfs_gsim.vbom |
tb_nexys3_core.vbom |
../../../vlib/serport/serport_master.vbom |
../../../vlib/serport/serport_uart_rxtx.vbom |
${nexys3_fusp_aif := nexys3_fusp_dummy.vbom} |
# design |
tb_nexys3_fusp.vhd |
/rtl/bplib/nexys4/tb/tb_nexys4.vhd
1,4 → 1,4
-- $Id: tb_nexys4.vhd 666 2015-04-12 21:17:54Z mueller $ |
-- $Id: tb_nexys4.vhd 643 2015-02-07 17:41:53Z mueller $ |
-- |
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
20,7 → 20,7
-- rlink/tb/tbcore_rlink |
-- xlib/s7_cmt_sfs |
-- tb_nexys4_core |
-- serport/serport_master |
-- serport/serport_uart_rxtx |
-- nexys4_aif [UUT] |
-- |
-- To test: generic, any nexys4_aif target |
30,7 → 30,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx |
-- 2015-02-06 643 1.2 factor out memory |
-- 2015-02-01 641 1.1 separate I_BTNRST_N |
-- 2013-09-28 535 1.0.1 use proper clock manager |
87,10 → 86,6
signal O_ANO_N : slv8 := (others=>'0'); |
signal O_SEG_N : slv8 := (others=>'0'); |
|
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff |
|
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); |
|
constant clock_period : time := 10 ns; |
constant clock_offset : time := 200 ns; |
|
157,26 → 152,22
O_SEG_N => O_SEG_N |
); |
|
SERMSTR : serport_master |
UART : serport_uart_rxtx |
generic map ( |
CDWIDTH => CLKDIV'length) |
port map ( |
CLK => CLKCOM, |
RESET => RESET, |
CLKDIV => CLKDIV, |
ENAXON => R_PORTSEL_XON, |
ENAESC => '0', |
RXDATA => RXDATA, |
RXVAL => RXVAL, |
RXERR => RXERR, |
RXOK => '1', |
TXDATA => TXDATA, |
TXENA => TXENA, |
TXBUSY => TXBUSY, |
RXSD => O_TXD, |
TXSD => I_RXD, |
RXRTS_N => I_CTS_N, |
TXCTS_N => O_RTS_N |
CLK => CLKCOM, |
RESET => RESET, |
CLKDIV => CLKDIV, |
RXSD => O_TXD, |
RXDATA => RXDATA, |
RXVAL => RXVAL, |
RXERR => RXERR, |
RXACT => RXACT, |
TXSD => I_RXD, |
TXDATA => TXDATA, |
TXENA => TXENA, |
TXBUSY => TXBUSY |
); |
|
proc_moni: process |
195,13 → 186,4
|
end process proc_moni; |
|
proc_simbus: process (SB_VAL) |
begin |
if SB_VAL'event and to_x01(SB_VAL)='1' then |
if SB_ADDR = sbaddr_portsel then |
R_PORTSEL_XON <= to_x01(SB_DATA(1)); |
end if; |
end if; |
end process proc_simbus; |
|
end sim; |
/rtl/bplib/nexys4/tb/tb_nexys4.vbom
18,7 → 18,7
../../../vlib/rlink/tb/tbcore_rlink.vbom |
../../../vlib/xlib/s7_cmt_sfs_gsim.vbom |
tb_nexys4_core.vbom |
../../../vlib/serport/serport_master.vbom |
../../../vlib/serport/serport_uart_rxtx.vbom |
${nexys4_aif := nexys4_dummy.vbom} |
# design |
tb_nexys4.vhd |
/rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd
1,4 → 1,4
-- $Id: tb_nexys4_cram.vhd 666 2015-04-12 21:17:54Z mueller $ |
-- $Id: tb_nexys4_cram.vhd 643 2015-02-07 17:41:53Z mueller $ |
-- |
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
20,7 → 20,7
-- rlink/tb/tbcore_rlink |
-- xlib/s7_cmt_sfs |
-- tb_nexys4_core |
-- serport/serport_master |
-- serport/serport_uart_rxtx |
-- nexys4_cram_aif [UUT] |
-- vlib/parts/micron/mt45w8mw16b |
-- |
31,7 → 31,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx |
-- 2015-02-01 641 1.1 separate I_BTNRST_N |
-- 2013-09-28 535 1.0.1 use proper clock manager |
-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3) |
97,10 → 96,6
signal O_MEM_ADDR : slv23 := (others=>'Z'); |
signal IO_MEM_DATA : slv16 := (others=>'0'); |
|
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff |
|
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); |
|
constant clock_period : time := 10 ns; |
constant clock_offset : time := 200 ns; |
|
192,26 → 187,22
DATA => IO_MEM_DATA |
); |
|
SERMSTR : serport_master |
UART : serport_uart_rxtx |
generic map ( |
CDWIDTH => CLKDIV'length) |
port map ( |
CLK => CLKCOM, |
RESET => RESET, |
CLKDIV => CLKDIV, |
ENAXON => R_PORTSEL_XON, |
ENAESC => '0', |
RXDATA => RXDATA, |
RXVAL => RXVAL, |
RXERR => RXERR, |
RXOK => '1', |
TXDATA => TXDATA, |
TXENA => TXENA, |
TXBUSY => TXBUSY, |
RXSD => O_TXD, |
TXSD => I_RXD, |
RXRTS_N => I_CTS_N, |
TXCTS_N => O_RTS_N |
CLK => CLKCOM, |
RESET => RESET, |
CLKDIV => CLKDIV, |
RXSD => O_TXD, |
RXDATA => RXDATA, |
RXVAL => RXVAL, |
RXERR => RXERR, |
RXACT => RXACT, |
TXSD => I_RXD, |
TXDATA => TXDATA, |
TXENA => TXENA, |
TXBUSY => TXBUSY |
); |
|
proc_moni: process |
/rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom
19,7 → 19,7
../../../vlib/xlib/s7_cmt_sfs_gsim.vbom |
tb_nexys4_core.vbom |
../../micron/mt45w8mw16b.vbom |
../../../vlib/serport/serport_master.vbom |
../../../vlib/serport/serport_uart_rxtx.vbom |
${nexys4_cram_aif := nexys4_cram_dummy.vbom} |
# design |
tb_nexys4_cram.vhd |
/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd
1,6 → 1,6
-- $Id: tb_s3board_fusp.vhd 666 2015-04-12 21:17:54Z mueller $ |
-- $Id: tb_s3board_fusp.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
20,7 → 20,7
-- rlink/tb/tbcore_rlink |
-- tb_s3board_core |
-- s3board_fusp_aif [UUT] |
-- serport/serport_master |
-- serport/serport_uart_rxtx |
-- |
-- To test: generic, any s3board_fusp_aif target |
-- |
28,7 → 28,6
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx |
-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface |
-- 2011-11-19 427 3.0.1 now numeric_std clean |
-- 2010-12-30 351 3.0 use rlink/tb now |
101,8 → 100,7
signal CTS_N : slbit := '0'; |
signal RTS_N : slbit := '0'; |
|
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport |
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff |
signal R_PORTSEL : slbit := '0'; |
|
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); |
|
169,33 → 167,29
O_FUSP_TXD => O_FUSP_TXD |
); |
|
SERMSTR : serport_master |
UART : serport_uart_rxtx |
generic map ( |
CDWIDTH => CLKDIV'length) |
port map ( |
CLK => CLK, |
RESET => UART_RESET, |
CLKDIV => CLKDIV, |
ENAXON => R_PORTSEL_XON, |
ENAESC => '0', |
RXDATA => RXDATA, |
RXVAL => RXVAL, |
RXERR => RXERR, |
RXOK => '1', |
TXDATA => TXDATA, |
TXENA => TXENA, |
TXBUSY => TXBUSY, |
RXSD => UART_RXD, |
TXSD => UART_TXD, |
RXRTS_N => RTS_N, |
TXCTS_N => CTS_N |
CLK => CLK, |
RESET => UART_RESET, |
CLKDIV => CLKDIV, |
RXSD => UART_RXD, |
RXDATA => RXDATA, |
RXVAL => RXVAL, |
RXERR => RXERR, |
RXACT => RXACT, |
TXSD => UART_TXD, |
TXDATA => TXDATA, |
TXENA => TXENA, |
TXBUSY => TXBUSY |
); |
|
proc_port_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N, |
proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N, |
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N) |
begin |
|
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl |
if R_PORTSEL = '0' then -- use main board rs232, no flow cntl |
I_RXD <= UART_TXD; -- write port 0 inputs |
UART_RXD <= O_TXD; -- get port 0 outputs |
RTS_N <= '0'; |
231,8 → 225,7
begin |
if SB_VAL'event and to_x01(SB_VAL)='1' then |
if SB_ADDR = sbaddr_portsel then |
R_PORTSEL_SER <= to_x01(SB_DATA(0)); |
R_PORTSEL_XON <= to_x01(SB_DATA(1)); |
R_PORTSEL <= to_x01(SB_DATA(0)); |
end if; |
end if; |
end process proc_simbus; |
/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom
15,7 → 15,7
../../../vlib/simlib/simclkcnt.vbom |
../../../vlib/rlink/tb/tbcore_rlink.vbom |
tb_s3board_core.vbom |
../../../vlib/serport/serport_master.vbom |
../../../vlib/serport/serport_uart_rxtx.vbom |
${s3board_fusp_aif := s3board_fusp_dummy.vbom} |
# design |
tb_s3board_fusp.vhd |
/rtl/w11a/pdp11_reg70.vhd
File deleted
/rtl/w11a/pdp11_reg70.vbom
File deleted
/rtl/w11a/pdp11_hio70.vbom
File deleted
/rtl/w11a/pdp11_hio70.vhd
File deleted
/rtl/w11a/pdp11_irq.vhd
1,4 → 1,4
-- $Id: pdp11_irq.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: pdp11_irq.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
48,7 → 48,7
entity pdp11_irq is -- interrupt requester |
port ( |
CLK : in slbit; -- clock |
BRESET : in slbit; -- bus reset |
BRESET : in slbit; -- ibus reset |
INT_ACK : in slbit; -- interrupt acknowledge from CPU |
EI_PRI : in slv3; -- external interrupt priority |
EI_VECT : in slv9_2; -- external interrupt vector |
/rtl/w11a/pdp11_ledmux.vhd
1,4 → 1,4
-- $Id: pdp11_ledmux.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: pdp11_ledmux.vhd 652 2015-02-28 12:18:08Z mueller $ |
-- |
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
41,7 → 41,7
port ( |
SEL : in slbit; -- select (0=stat;1=dr) |
STATLEDS : in slv8; -- 8 bit CPU status |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status |
LED : out slv(LWIDTH-1 downto 0) -- hio leds |
); |
end pdp11_ledmux; |
/rtl/w11a/pdp11_dpath.vhd
1,4 → 1,4
-- $Id: pdp11_dpath.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: pdp11_dpath.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2006-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
59,7 → 59,7
entity pdp11_dpath is -- CPU datapath |
port ( |
CLK : in slbit; -- clock |
CRESET : in slbit; -- cpu reset |
CRESET : in slbit; -- console reset |
CNTL : in dpath_cntl_type; -- control interface |
STAT : out dpath_stat_type; -- status interface |
CP_DIN : in slv16; -- console port data in |
/rtl/w11a/pdp11_cache.vhd
1,4 → 1,4
-- $Id: pdp11_cache.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: pdp11_cache.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
40,7 → 40,7
entity pdp11_cache is -- cache |
port ( |
CLK : in slbit; -- clock |
GRESET : in slbit; -- general reset |
GRESET : in slbit; -- global reset |
EM_MREQ : in em_mreq_type; -- em request |
EM_SRES : out em_sres_type; -- em response |
FMISS : in slbit; -- force miss |
/rtl/w11a/pdp11_dspmux.vhd
1,4 → 1,4
-- $Id: pdp11_dspmux.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: pdp11_dspmux.vhd 652 2015-02-28 12:18:08Z mueller $ |
-- |
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
56,7 → 56,7
port ( |
SEL : in slv2; -- select |
ABCLKDIV : in slv16; -- serport clock divider |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status |
DISPREG : in slv16; -- display register |
DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data |
); |
/rtl/w11a/tb/tbd_pdp11core.vhd
1,6 → 1,6
-- $Id: tbd_pdp11core.vhd 674 2015-05-04 16:17:40Z mueller $ |
-- $Id: tbd_pdp11core.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
41,7 → 41,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-03 674 1.6 start/stop/suspend overhaul |
-- 2011-11-18 427 1.5.1 now numeric_std clean |
-- 2010-12-30 351 1.5 rename tbd_pdp11_core -> tbd_pdp11core |
-- 2010-10-23 335 1.4.2 rename RRI_LAM->RB_LAM; |
92,12 → 91,9
CP_STAT_cmderr : out slbit; -- console status port |
CP_STAT_cmdmerr : out slbit; -- console status port |
CP_STAT_cpugo : out slbit; -- console status port |
CP_STAT_cpuhalt : out slbit; -- console status port |
CP_STAT_cpustep : out slbit; -- console status port |
CP_STAT_cpuwait : out slbit; -- console status port |
CP_STAT_cpususp : out slbit; -- console status port |
CP_STAT_cpurust : out slv4; -- console status port |
CP_STAT_suspint : out slbit; -- console status port |
CP_STAT_suspext : out slbit; -- console status port |
CP_DOUT : out slv16 -- console data out |
); |
end tbd_pdp11core; |
144,12 → 140,9
CP_STAT_cmderr <= CP_STAT.cmderr; |
CP_STAT_cmdmerr <= CP_STAT.cmdmerr; |
CP_STAT_cpugo <= CP_STAT.cpugo; |
CP_STAT_cpuhalt <= CP_STAT.cpuhalt; |
CP_STAT_cpustep <= CP_STAT.cpustep; |
CP_STAT_cpuwait <= CP_STAT.cpuwait; |
CP_STAT_cpususp <= CP_STAT.cpususp; |
CP_STAT_cpurust <= CP_STAT.cpurust; |
CP_STAT_suspint <= CP_STAT.suspint; |
CP_STAT_suspext <= CP_STAT.suspext; |
|
CLKDIV : clkdivce |
generic map ( |
171,11 → 164,6
CP_DIN => CP_DIN, |
CP_STAT => CP_STAT, |
CP_DOUT => CP_DOUT, |
ESUSP_O => open, -- not tested |
ESUSP_I => '0', -- dito |
ITIMER => open, -- dito |
EBREAK => '0', -- dito |
DBREAK => '0', -- dito |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
EI_ACKM => EI_ACKM, |
/rtl/w11a/tb/tb_pdp11core.vhd
1,6 → 1,6
-- $Id: tb_pdp11core.vhd 675 2015-05-08 21:05:08Z mueller $ |
-- $Id: tb_pdp11core.vhd 621 2014-12-26 21:20:05Z mueller $ |
-- |
-- Copyright 2006-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2006-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
47,7 → 47,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-08 675 1.5 start/stop/suspend overhaul |
-- 2014-12-26 621 1.4.1 adopt wmembe,ribr,wibr emulation to new 4k window |
-- 2011-12-23 444 1.4 use new simclk/simclkcnt |
-- 2011-11-18 427 1.3.2 now numeric_std clean |
115,11 → 114,8
signal CP_STAT_cmdmerr : slbit := '0'; |
signal CP_STAT_cpugo : slbit := '0'; |
signal CP_STAT_cpustep : slbit := '0'; |
signal CP_STAT_cpuwait : slbit := '0'; |
signal CP_STAT_cpususp : slbit := '0'; |
signal CP_STAT_cpuhalt : slbit := '0'; |
signal CP_STAT_cpurust : slv4 := (others=>'0'); |
signal CP_STAT_suspint : slbit := '0'; |
signal CP_STAT_suspext : slbit := '0'; |
signal CP_DOUT : slv16 := (others=>'0'); |
|
signal CLK_STOP : slbit := '0'; |
168,11 → 164,8
CP_STAT_cmdmerr => CP_STAT_cmdmerr, |
CP_STAT_cpugo => CP_STAT_cpugo, |
CP_STAT_cpustep => CP_STAT_cpustep, |
CP_STAT_cpuwait => CP_STAT_cpuwait, |
CP_STAT_cpususp => CP_STAT_cpususp, |
CP_STAT_cpuhalt => CP_STAT_cpuhalt, |
CP_STAT_cpurust => CP_STAT_cpurust, |
CP_STAT_suspint => CP_STAT_suspint, |
CP_STAT_suspext => CP_STAT_suspext, |
CP_DOUT => CP_DOUT |
); |
|
334,7 → 327,7
end if; |
|
when others => -- bad directive |
write(oline, string'("-E: unknown directive: ")); |
write(oline, string'("?? unknown directive: ")); |
write(oline, dname); |
writeline(output, oline); |
report "aborting" severity failure; |
445,20 → 438,16
idosta := '1'; -- request 'sta' to be done next |
|
when "sta " => -- sta |
ifunc := c_cpfunc_start; |
ifunc := c_cpfunc_sta; |
when "sto " => -- sto |
ifunc := c_cpfunc_stop; |
ifunc := c_cpfunc_sto; |
when "cont " => -- cont |
ifunc := c_cpfunc_cont; |
when "step " => -- step |
ifunc := c_cpfunc_step; |
iwtstp := true; |
when "cres " => -- cres |
ifunc := c_cpfunc_creset; |
when "bres " => -- bres |
ifunc := c_cpfunc_breset; |
when "susp " => -- susp |
ifunc := c_cpfunc_suspend; |
when "resu " => -- resu |
ifunc := c_cpfunc_resume; |
when "rst " => -- rst |
ifunc := c_cpfunc_rst; |
|
when "wtgo " => -- wtgo |
iwtgo := true; |
469,7 → 458,7
next file_loop; |
|
when others => -- bad directive |
write(oline, string'("-E: unknown directive: ")); |
write(oline, string'("?? unknown directive: ")); |
write(oline, dname); |
writeline(output, oline); |
report "aborting" severity failure; |
564,13 → 553,11
else |
write(oline, string'("wmem")); |
end if; |
when c_cpfunc_start => write(oline, string'("sta ")); |
when c_cpfunc_stop => write(oline, string'("sto ")); |
when c_cpfunc_step => write(oline, string'("step")); |
when c_cpfunc_creset => write(oline, string'("cres")); |
when c_cpfunc_breset => write(oline, string'("bres")); |
when c_cpfunc_suspend => write(oline, string'("susp")); |
when c_cpfunc_resume => write(oline, string'("resu")); |
when c_cpfunc_sta => write(oline, string'("sta ")); |
when c_cpfunc_sto => write(oline, string'("sto ")); |
when c_cpfunc_cont => write(oline, string'("cont")); |
when c_cpfunc_step => write(oline, string'("step")); |
when c_cpfunc_rst => write(oline, string'("rst ")); |
when others => |
write(oline, string'("?")); |
writeoct(oline, ifunc, right, 2); |
588,11 → 575,8
write(oline, R_CP_STAT.cmdmerr, right, 2); |
writeoct(oline, R_CP_DOUT, right, 8); |
write(oline, R_CP_STAT.cpugo, right, 3); |
write(oline, R_CP_STAT.cpustep, right, 1); |
write(oline, R_CP_STAT.cpuwait, right, 1); |
write(oline, R_CP_STAT.cpususp, right, 1); |
write(oline, R_CP_STAT.suspint, right, 1); |
write(oline, R_CP_STAT.suspext, right, 1); |
write(oline, R_CP_STAT.cpustep, right, 2); |
write(oline, R_CP_STAT.cpuhalt, right, 2); |
writeoct(oline, R_CP_STAT.cpurust, right, 3); |
|
if R_WAITOK = '1' then |
683,11 → 667,8
R_CP_STAT.cmdmerr <= CP_STAT_cmdmerr; |
R_CP_STAT.cpugo <= CP_STAT_cpugo; |
R_CP_STAT.cpustep <= CP_STAT_cpustep; |
R_CP_STAT.cpuwait <= CP_STAT_cpuwait; |
R_CP_STAT.cpususp <= CP_STAT_cpususp; |
R_CP_STAT.cpuhalt <= CP_STAT_cpuhalt; |
R_CP_STAT.cpurust <= CP_STAT_cpurust; |
R_CP_STAT.suspint <= CP_STAT_suspint; |
R_CP_STAT.suspext <= CP_STAT_suspext; |
R_CP_DOUT <= CP_DOUT; |
|
end loop; |
/rtl/w11a/tb/tb_pdp11core_stim.dat
1,8 → 1,7
# $Id: tb_pdp11core_stim.dat 675 2015-05-08 21:05:08Z mueller $ |
# $Id: tb_pdp11core_stim.dat 621 2014-12-26 21:20:05Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-05-08 675 2.6 start/stop/suspend overhaul |
# 2014-12-26 621 2.5 adopt wmembe,ribr,wibr emulation to new 4k window |
# 2014-12-20 614 2.4 adopted to rlink v4 |
# 2014-07-13 569 2.3 after ECO-026: correct test 31.1 wrong V=1 cases |
250,10 → 249,9
.merr 0 |
.sdef s=00000000,01110000 |
# |
C test access error handling to IB space (use 00160016) |
C (is above ibd_ibmon decoded range, and below other debug stuff) |
C test access error handling to IB space (use 00160000) |
C with wm/rm |
wal 160016 |
wal 160000 |
.merr 1 |
.sdef s=01000001 |
wm 000000 |
262,7 → 260,7
.sdef s=00000000,01110000 |
C with bwm/brm |
# |
wal 160016 |
wal 160000 |
.merr 1 |
.sdef s=01000001 |
bwm 2 |
271,7 → 269,7
.merr 0 |
.sdef s=00000000,01110000 |
# |
wal 160016 |
wal 160000 |
.merr 1 |
.sdef s=01000001 |
brm 2 |
360,12 → 358,12
077002 -- sob r0,-2 |
000000 -- halt |
# |
C Exec code 1 (very basics: start; 'simple' instructions) |
C Exec code 1 (very basics: cont,start; 'simple' instructions) |
C Exec test 1.1 (sec+clc+halt) |
# |
wpc 002100 -- pc=2100 |
wps 000010 -- psw: set N flag |
sta -- start @ 2100 |
cont -- cont @ 2100 |
wtgo |
rpc d=002106 -- ! pc |
rps d=000001 -- ! N cleared, C set now |
373,7 → 371,6
C Exec test 1.2 (4 *inc R2, starting from -2) |
# |
wr2 177776 -- r2=-2 |
cres |
stapc 002120 -- start @ 2120 |
wtgo |
rr2 d=000002 -- ! r2=2 |
382,7 → 379,6
C Exec test 1.3 (dec r3; bne -2; halt) |
# |
wr3 000002 -- r3=2 |
cres |
stapc 002140 -- start @ 2140 |
wtgo |
rr3 d=000000 -- ! r3=0 |
392,7 → 388,6
# |
wr0 000002 -- r0=2 |
wr1 000000 -- r1=0 |
cres |
stapc 002160 -- start @ 2160 |
wtgo |
rr0 d=000000 -- ! r0=0 |
411,7 → 406,6
C Exec code 2 (bpt against trap catcher @14) |
# |
wsp 001400 -- sp=1400 |
cres |
stapc 002200 -- start @ 2200 |
wtgo |
rsp d=001374 -- ! sp |
444,7 → 438,6
wr0 000000 -- r0=0 |
wr1 000000 -- r1=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 002300 -- start @ 2300 |
wtgo |
rr0 d=000001 -- ! r0 |
470,7 → 463,6
bwm 2 |
002402 -- start address |
000020 -- set T flag in PSW |
cres |
stapc 002400 -- start @ 2400 -> rtt -> 2402 from stack |
wtgo |
rr0 d=000002 -- ! r0 |
478,7 → 470,7
rsp d=001400 -- ! sp |
rpc d=002410 -- ! pc |
# |
cres -- console reset (to clear T flag) |
rst -- console reset (to clear T flag) |
wal 000014 -- vector: 14 -> trap catcher again |
bwm 2 |
000016 -- PC:16 |
513,7 → 505,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 002500 -- start @ 2500 |
wtgo |
rr0 d=002544 -- ! r0 |
551,7 → 542,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 002600 -- start @ 2600 |
wtgo |
rr0 d=002540 -- ! r0 |
603,7 → 593,6
wr4 002774 -- r4=2774 |
wr5 000666 -- r5=666 |
wsp 001400 -- sp=1400 |
cres |
stapc 002700 -- start @ 2700 |
wtgo |
rr0 d=002750 -- ! r0 |
665,7 → 654,6
wr3 003060 -- r3=3060 |
wr4 003074 -- r4=3074 |
wsp 001400 -- sp=1400 |
cres |
stapc 003000 -- start @ 3000 |
wtgo |
rr0 d=003050 -- ! r0 |
749,7 → 737,6
wr4 003144 -- r4=3144 |
wr5 003160 -- r5=3160 |
wsp 001400 -- sp=1400 |
cres |
stapc 003100 -- start @ 3100 |
wtgo |
rr0 d=003210 -- ! r0=3210 |
808,7 → 795,6
wr1 177777 -- r1=177777 |
wr5 003400 -- r5=3400 |
wsp 001400 -- sp=1400 |
cres |
stapc 003300 -- start @ 3300 |
wtgo |
rr5 d=003424 -- ! r5=3424 |
850,7 → 836,6
# |
C Exec code 13.1a (run WAIT) |
# |
cres |
stapc 003500 -- start @ 3500 |
.wait 20 -- let it go |
rpc d=003502 -- ! should hang here ... |
875,7 → 860,6
# |
C Exec code 13.2 (test bwm/brm while CPU busy looping) |
wr0 000000 -- r0=0 |
cres |
stapc 003520 -- start @ 3520 |
# |
wal 003560 -- write data while CPU active |
905,7 → 889,6
# |
C Exec code 13.3 (test bwm/brm while CPU on WAIT) |
# |
cres |
stapc 003540 -- start @ 3540 |
# |
wal 003560 -- write data while CPU active |
984,7 → 967,6
wr3 000044 -- r3=44 |
wr5 003700 -- r5=3700 |
wsp 001400 -- sp=140 |
cres |
stapc 003600 -- start @ 3600 |
wtgo |
rr5 d=003720 -- ! r5=3720 |
1095,7 → 1077,6
C Exec test 16.1 (check CRESET of PSW, SSR0, SSR3 after start) |
# |
wps 000000 -- psw: set pri=0 |
cres |
stapc 004030 -- start @ 4030 (just HALT, testing console reset) |
wtgo |
rpc d=004032 -- ! pc=4032 |
1204,7 → 1185,6
bwm 2 |
004100 -- start address (code 17 @ 4100) |
000020 -- set T flag in PSW |
cres |
stapc 004274 -- start @ 4274 -> rtt -> 4100 from stack |
wtgo |
rr1 d=004711 -- ! r1=4711 |
1281,7 → 1261,7
d=000020 -- ! mem(4572)=0000; xor r1,(r4)+ (#4711, #070707) |
d=000024 -- ! mem(4574)=0Z00; sxt (r4)+ (#111111 with N=0) |
# |
cres -- console reset (to clear T flag) |
rst -- console reset (to clear T flag) |
wal 000014 -- vector: 14 -> trap catcher again |
bwm 2 |
000016 -- PC:16 |
1313,7 → 1293,7
#---------- |
C Exec code 20 (check CPUERR and error handling) |
C Exec test 20.1 (odd address abort) |
cres -- console reset |
rst -- console reset |
wps 000000 -- psw: clear |
wal 001374 -- clean stack |
bwm 2 |
1951,7 → 1931,7
wr5 005260 -- r5=5260 |
wsp 001400 -- sp=1400 |
wpc 005000 -- pc=5000 |
sta -- start @ 5000 |
cont -- cont @ 5000 |
wtgo |
rsp d=001372 -- ! sp |
rpc d=005030 -- ! pc (halt in TRAP handler) |
2151,7 → 2131,6
wr2 177776 -- r2=177776 (PS address) |
wr5 006300 -- r5=6300 (output data) |
wsp 001400 -- sp=1400 |
cres |
stapc 005700 -- start @ 5700 |
wtgo |
rr0 d=006212 -- ! r0 |
2179,7 → 2158,6
wr2 177776 -- r2=177776 (PS address) |
wr5 006330 -- sp=6330 (output data) |
wsp 001400 -- sp=1400 |
cres |
stapc 005720 -- start @ 5720 |
wtgo |
rr0 d=006226 -- ! r0 |
2203,7 → 2181,6
wr2 177776 -- r2=177776 (PS address) |
wr5 006344 -- sp=6344 (output data) |
wsp 001400 -- sp=1400 |
cres |
stapc 005740 -- start @ 5740 |
wtgo |
rr0 d=006264 -- ! r0 |
2272,7 → 2249,6
wr0 006470 -- r0=6470 |
wr5 123456 -- r5=123456 |
wsp 001400 -- sp=1400 |
cres |
stapc 006400 -- start @ 6400 |
wtgo |
rr0 d=006476 -- ! r0=6476 (3 words written) |
2362,7 → 2338,6
bwm 2 |
006500 -- start address (code 25 @ 6500) |
000020 -- set T flag in PSW |
cres |
stapc 006564 -- start @ 6564 -> rtt -> 6500 from stack |
wtgo |
rr1 d=000123 -- ! r1=123 |
2419,7 → 2394,7
d=000020 -- ! mem(6674)=0000; aslb (r4)+ (#020) |
d=000023 -- ! mem(6676)=00VC; aslb (r4)+ (#220) |
# |
cres -- console reset (to clear T flag) |
rst -- console reset (to clear T flag) |
wal 000014 -- vector: 14 -> trap catcher again |
bwm 2 |
000016 -- PC:16 |
2520,7 → 2495,6
wr0 007060 -- r0=7060 (input data for (r0)+...) |
wr1 007100 -- r1=7100 (input data for -(r1)...) |
wsp 001400 -- sp=1400 |
cres |
stapc 006700 -- start @ 6700 |
wtgo |
rr0 d=007070 -- ! r0 |
2541,7 → 2515,6
C Exec test 26.2 (test indexed mode with pc (mode 67)): |
# |
wsp 001400 -- sp=1400 |
cres |
stapc 006720 -- start @ 6720 |
wtgo |
rpc d=006736 -- ! pc |
2555,7 → 2528,6
# |
wr0 000111 -- r0=0111 |
wsp 001400 -- sp=1400 |
cres |
stapc 006750 -- start @ 6750 |
wtgo |
rr0 d=000112 -- ! r0 |
2577,7 → 2549,6
wr2 000120 -- r2=0120 |
wr3 000130 -- r3=0130 |
wsp 001400 -- sp=1400 |
cres |
stapc 007000 -- start @ 7000 |
wtgo |
rr0 d=000101 -- ! r0 |
2594,7 → 2565,6
# |
wr1 000000 -- r1=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 007020 -- start @ 7020 |
wtgo |
rr1 d=000002 -- ! r1 |
2718,7 → 2688,6
wr2 000014 -- r2=14 (test count) |
wr3 177776 -- r3=177776 (#PSW) |
wsp 001400 -- sp=1400 |
cres |
stapc 007100 -- start @ 7100 |
wtgo |
rr0 d=007260 -- ! r0 |
2758,7 → 2727,6
wr2 000012 -- r2=12 (test count) |
wr3 177776 -- r3=177776 (#PSW) |
wsp 001400 -- sp=1400 |
cres |
stapc 007120 -- start @ 7120 |
wtgo |
rr0 d=007374 -- ! r0 |
2804,7 → 2772,6
wr2 000003 -- r2=3 (test count) |
wr3 177776 -- r3=177776 (#PSW) |
wsp 001400 -- sp=1400 |
cres |
stapc 007150 -- start @ 7150 |
wtgo |
rr0 d=007454 -- ! r0 |
2879,7 → 2846,6
wr2 000010 -- r2=10 (test count) |
wr3 177776 -- r3=177776 (#PSW) |
wsp 001400 -- sp=1400 |
cres |
stapc 010200 -- start @ 10200 |
wtgo |
rr0 d=010300 -- ! r0 |
2920,7 → 2886,6
wr3 000000 -- r3=0 |
wr4 000000 -- r4=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 010220 -- start @ 10220 |
wtgo |
rr0 d=010300 -- ! r0 |
3088,10 → 3053,10
wr2 000025 -- r2=25 (test count) |
wr3 177776 -- r3=177776 (#PSW) |
wsp 001400 -- sp=1400 |
cres -- console reset ; do reset; cont to start with |
rst -- console reset ; do reset; cont to start with |
wps 000000 -- clear psw ; psw cc code dump below |
wpc 010400 -- pc=10400 |
sta -- start @ 10400 |
cont -- cont @ 10400 |
wtgo |
rr0 d=010676 -- ! r0 |
rr1 d=011076 -- ! r1 |
3173,7 → 3138,6
wr1 010700 -- r1=10700 (output data from DIV) |
wr5 000016 -- r5=16 (test count) |
wsp 001400 -- sp=1400 |
cres |
stapc 010420 -- start @ 10420 |
wtgo |
rr0 d=010624 -- ! r0 |
3253,7 → 3217,6
wr4 177776 -- r4=177776 (#PSW) |
wr5 011220 -- r1=11220 (output data) |
wsp 001400 -- sp=1400 |
cres |
stapc 011100 -- start @ 11100 |
wtgo |
rr5 d=011300 -- ! r5 |
3376,7 → 3339,6
wr0 011300 -- r0=11300 |
wr1 000003 -- r1=3 |
wsp 001400 -- sp=1400 |
cres |
stapc 011200 -- start @ 11200 |
wtgo |
rr0 d=011322 -- ! r0=11322 |
3398,7 → 3360,6
wr0 011324 -- r0=11324 |
wr1 000003 -- r1=3 |
wsp 001400 -- sp=1400 |
cres |
stapc 011220 -- start @ 11220 |
wtgo |
rr0 d=011346 -- ! r0=11346 |
3420,7 → 3381,6
wr0 011350 -- r0=11350 |
wr1 000003 -- r1=3 |
wsp 001400 -- sp=1400 |
cres |
stapc 011240 -- start @ 11240 |
wtgo |
rr0 d=011364 -- ! r0=11364 |
3439,7 → 3399,6
wr0 011364 -- r0=11364 |
wr1 000003 -- r1=3 |
wsp 001400 -- sp=1400 |
cres |
stapc 011260 -- start @ 11260 |
wtgo |
rr0 d=011400 -- ! r0=11400 |
3529,7 → 3488,6
# |
C Exec code 34 (11/34 self test code) |
# D RE RQ FU DAT |
cres |
stapc 011400 -- start @ 11400 |
wtgo |
rr0 d=000000 -- ! r0 |
3678,7 → 3636,6
# |
C Exec code 35 (11/70 self test code) |
# D RE RQ FU DAT |
cres |
stapc 011600 -- start @ 11600 |
wtgo |
rpc d=012152 -- ! pc |
3739,7 → 3696,6
wr4 036000 -- r4=36000 -> input area |
wr5 037000 -- r5=37000 -> output area |
wsp 001400 -- sp=1400 |
cres |
stapc 012200 -- start @ 12200 |
wtgo |
rpc d=012216 -- ! pc |
3847,7 → 3803,6
wr4 036000 -- r4=36000 -> input area |
wr5 037000 -- r5=37000 -> output area |
wsp 001400 -- sp=1400 |
cres |
stapc 012300 -- start @ 12300 |
wtgo |
rpc d=012322 -- ! pc |
3979,7 → 3934,6
wr4 036000 -- r4=36000 -> input area |
wr5 037000 -- r5=37000 -> output area |
wsp 001400 -- sp=1400 |
cres |
stapc 012300 -- start @ 12300 |
wtgo |
rpc d=012322 -- ! pc |
4231,7 → 4185,6
wr4 036000 -- r4=36000 -> input area |
wr5 037000 -- r5=37000 -> output area |
wsp 001400 -- sp=1400 |
cres |
stapc 012400 -- start @ 12400 |
wtgo |
rpc d=012436 -- ! pc |
4593,7 → 4546,6
wr4 036000 -- r4=36000 |
wr5 037000 -- r5=37000 |
wsp 001400 -- sp=1400 |
cres |
stapc 012500 -- start @ 12500 |
wtgo |
rpc d=012546 -- ! pc |
4966,7 → 4918,6
wr4 036000 -- r4=36000 -> input area |
wr5 037000 -- r5=37000 -> output area |
wsp 001400 -- sp=1400 |
cres |
stapc 012600 -- start @ 12600 |
wtgo |
rpc d=012636 -- ! pc |
5144,7 → 5095,6
C Exec test 43.1 (basics) |
# D RE RQ FU DAT |
wsp 001400 -- sp=1400 |
cres |
stapc 012700 -- start @ 12700 |
wtgo |
rpc d=012734 -- ! pc |
5161,7 → 5111,6
C Exec test 43.2 (MARK with max. # of args) |
# D RE RQ FU DAT |
wsp 001400 -- sp=1400 |
cres |
stapc 012740 -- start @ 12740 |
wtgo |
rpc d=012764 -- ! pc |
5206,7 → 5155,7
C Exec code 44 (Implementation variations) |
C test 44.1: OPR R,(R)+ : incremented before {J11} or after {70} use as source |
# |
cres -- console reset |
rst -- console reset |
wps 000000 -- clear psw |
wr4 001600 -- r4=1600 |
wsp 001400 -- sp=1400 |
5293,7 → 5242,7
000020 -- set T flag in PSW |
wsp 001374 -- sp=1374 |
wpc 013020 -- pc=13020 |
sta -- start (rtt) |
cont -- cont (rtt) |
wtgo |
rpc d=000020 -- ! pc=20 ; T-trap executed |
rsp d=001374 -- ! sp=1374 |
5301,7 → 5250,7
brm 2 |
d=013072 -- trap address: address after noop expected for 11/70 |
d=000020 -- PSW |
cres -- console reset (to clear T flag) |
rst -- console reset (to clear T flag) |
# |
C test 44.11: If RTI sets T bit, T trap occurs immediately {70,J11} |
# |
5311,7 → 5260,7
000020 -- set T flag in PSW |
wsp 001374 -- sp=1374 |
wpc 013024 -- pc=13024 |
sta -- start (rti) |
cont -- cont (rti) |
wtgo |
rpc d=000020 -- ! pc=20 ; T-trap executed |
rsp d=001374 -- ! sp=1374 |
5319,7 → 5268,7
brm 2 |
d=013070 -- trap address: address of noop expected for 11/70 |
d=000020 -- PSW |
cres -- console reset (to clear T flag) |
rst -- console reset (to clear T flag) |
# |
C test 44.14: Direct access to PSW can {05..20} / cannot {others} set T bit |
# |
5342,7 → 5291,7
brm 2 |
d=013034 -- ! PC of abort [[s:0]] |
d=000000 -- ! PS of abort (currently gets lost...) |
cres -- console reset (to clear CPUERR reg) |
rst -- console reset (to clear CPUERR reg) |
wal 000000 -- clean tainted memory |
bwm 2 |
000000 -- |
5359,13 → 5308,12
# |
C test 44.28: If PC->bad memory, PC incremented {others} / not inc'ed {35,40} |
# |
cres |
wal 177572 -- SSR0 |
wmi 000001 -- set enable bit |
wr4 100000 -- r4=100000 |
wsp 001400 -- sp=1400 |
wpc 013034 -- pc=13034 |
sta -- start (jmp (r4)) |
cont -- cont (jmp (r4)) |
wtgo |
rpc d=000254 -- ! pc=254 ; trap 240 ; Note: halt is executed, was cont ! |
rsp d=001374 -- ! sp=1374 |
5373,7 → 5321,7
brm 2 |
d=100002 -- trap address: PC inc'ed expected for 11/70 [[s:100000]] |
d=000340 -- PSW |
cres -- console reset (to clear CPUERR reg) |
rst -- console reset (to clear CPUERR reg) |
# |
# simh notes: |
# 1. simh reads instruction, later increments PC. Thus PC not inc'ed in simh. |
5394,7 → 5342,7
brm 2 |
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]] |
d=000021 -- ! SSR1: ra=1,2 |
cres -- console reset (to clear CPUERR reg) |
rst -- console reset (to clear CPUERR reg) |
# |
C test 44.29/30b: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44} |
C test for srcr chain (mov (r1)+,r0) |
5412,7 → 5360,7
brm 2 |
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]] |
d=000021 -- ! SSR1: ra=1,2 |
cres -- console reset (to clear CPUERR reg) |
rst -- console reset (to clear CPUERR reg) |
# |
C test 44.29/30c: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44} |
C test for dstr chain (inc (r1)+) |
5430,7 → 5378,7
brm 2 |
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]] |
d=000021 -- ! SSR1: ra=1,2 |
cres -- console reset (to clear CPUERR reg) |
rst -- console reset (to clear CPUERR reg) |
C test 44.29/30d: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44} |
C test for dsta chain (mtpd (r1)+) |
# |
5449,7 → 5397,7
brm 2 |
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]] |
d=010426 -- ! SSR1: rb=1,2; ra=6,2 |
cres -- console reset (to clear CPUERR reg) |
rst -- console reset (to clear CPUERR reg) |
# |
# simh notes: |
# 1. simh first pops, than writes to destination, reversing ra,rb in SSR1 |
5480,7 → 5428,7
brm 2 |
d=013044 -- ! PC after failed instruction [[s:013042]] |
d=100000 -- ! PS |
cres -- console reset (to clear CPUERR reg, PSW) |
rst -- console reset (to clear CPUERR reg, PSW) |
# |
# simh notes: |
# 1. simh saves PC of failed instruction on stack, not PC after instruction |
5501,7 → 5449,7
d=170000 -- ! PS |
wal 177766 -- check CPUERR |
rm d=000200 -- ! CPUERR: (illhalt=1) |
cres -- console reset (to clear CPUERR reg, PSW) |
rst -- console reset (to clear CPUERR reg, PSW) |
# |
C test 44.44: PDR bit<0> implemented {70} or not {others} |
# |
5540,7 → 5488,7
bwm 2 |
077406 -- slf=127; ed=0(up); acf=6(w/r) |
077406 -- slf=127; ed=0(up); acf=6(w/r) |
cres -- console reset (to clear CPUERR reg) |
rst -- console reset (to clear CPUERR reg) |
# |
C test 44.46: Full PAR implemented {44,70,J11} or not {others} |
# |
5599,7 → 5547,7
d=000001 -- ! SSR0: (ena=1) |
d=000000 -- ! SSR1: ra=none |
d=000016 -- ! SSR2: PC of halt |
cres -- console reset (to clear CPUERR reg, PSW) |
rst -- console reset (to clear CPUERR reg, PSW) |
# |
# simh notes: |
# 1. when simh steps over a BPT,IOT,..., the PC is pointing after the |
5640,7 → 5588,7
rsp d=001376 -- ! sp=1376 |
wal 001376 -- check stack |
rmi d=013046 -- ! it returns PC like 11/70 unpredictable [[s:0]] |
cres -- console reset (to clear CPUERR reg) |
rst -- console reset (to clear CPUERR reg) |
# |
# simh note: |
# 1. simh returns 0 here, just unpredictable in a different way ... |
5677,7 → 5625,7
rsp d=110601 -- ! usp [[usp]] |
# --> all preset values intact; -> mtpd thus noop --> like 11/70 unpredictable |
# |
cres -- console reset (to clear CPUERR reg) |
rst -- console reset (to clear CPUERR reg) |
# |
# simh notes on MMR0: |
# 1. simh doesn't freeze MMR0 bit 7, the instr.compl. bit is set again after |
5698,7 → 5646,6
C Exec code 45 (mmr1 and instructions with implicit stack push/pop) |
C test 45.1: mtpd (r1)+ |
# |
cres |
wal 177572 -- SSR0 |
wmi 000001 -- set enable bit |
wal 001376 -- setup stack with value for mtpd |
5717,7 → 5664,7
d=013100 -- ! SSR2: PC of mtpd |
wal 030000 -- check target memory |
rm d=123456 -- ! |
cres -- console reset |
rst -- console reset |
# |
C test 45.2: mfpd (r1)+ |
# |
5739,7 → 5686,7
rmi d=123456 -- ! |
wal 030000 -- clear tainted target memory |
wm 000000 -- |
cres -- console reset |
rst -- console reset |
# |
C test 45.3: jsr pc,(r1)+ and rts pc |
# |
5767,7 → 5714,7
d=000001 -- ! SSR0: (seg=0,ena=1) |
d=000026 -- ! SSR1: ra=6,2 [[s:0]] |
d=013110 -- ! SSR2: PC of rts |
cres -- console reset |
rst -- console reset |
# |
# simh notes: |
# 1. simh reads stack and incremets sp later. In case of an MMU abort on |
5852,7 → 5799,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
5883,7 → 5829,6
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
cres |
stapc 013220 -- start @ 13220 (1op mem) |
wtgo |
rpc d=013240 -- ! pc=halt |
5914,7 → 5859,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
5945,7 → 5889,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
5976,7 → 5919,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
6007,7 → 5949,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
6038,7 → 5979,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
6069,7 → 6009,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
6100,7 → 6039,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
6131,7 → 6069,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
6162,7 → 6099,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
6193,7 → 6129,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
6224,7 → 6159,6
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
cres |
stapc 013220 -- start @ 13220 (1op mem) |
wtgo |
rpc d=013240 -- ! pc=halt |
6264,7 → 6198,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
6299,7 → 6232,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
6334,7 → 6266,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
6369,7 → 6300,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
6404,7 → 6334,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
6439,7 → 6368,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
6474,7 → 6402,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
6509,7 → 6436,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
6552,7 → 6478,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
6579,7 → 6504,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
6606,7 → 6530,6
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
cres |
stapc 013270 -- start @ 13270 (2op mem) |
wtgo |
rpc d=013312 -- ! pc=halt |
6647,7 → 6570,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
6680,7 → 6602,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
6713,7 → 6634,6
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
cres |
stapc 013270 -- start @ 13270 (2op mem) |
wtgo |
rpc d=013312 -- ! pc=halt |
6746,7 → 6666,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
6779,7 → 6698,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
6812,7 → 6730,6
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
cres |
stapc 013270 -- start @ 13270 (2op mem) |
wtgo |
rpc d=013312 -- ! pc=halt |
6845,7 → 6762,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
6878,7 → 6794,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
6911,7 → 6826,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
6944,7 → 6858,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
7017,7 → 6930,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
7076,7 → 6988,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
7135,7 → 7046,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
7205,7 → 7115,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7252,7 → 7161,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7283,7 → 7191,6
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
cres |
stapc 013220 -- start @ 13220 (1op mem) |
wtgo |
rpc d=013240 -- ! pc=halt |
7314,7 → 7221,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7345,7 → 7251,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7376,7 → 7281,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7407,7 → 7311,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7438,7 → 7341,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7469,7 → 7371,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7500,7 → 7401,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7531,7 → 7431,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7562,7 → 7461,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7593,7 → 7491,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7624,7 → 7521,6
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
cres |
stapc 013220 -- start @ 13220 (1op mem) |
wtgo |
rpc d=013240 -- ! pc=halt |
7664,7 → 7560,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7699,7 → 7594,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7734,7 → 7628,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7769,7 → 7662,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7804,7 → 7696,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7839,7 → 7730,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7874,7 → 7764,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7909,7 → 7798,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
7952,7 → 7840,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
7979,7 → 7866,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
8006,7 → 7892,6
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
cres |
stapc 013270 -- start @ 13270 (2op mem) |
wtgo |
rpc d=013312 -- ! pc=halt |
8047,7 → 7932,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
8080,7 → 7964,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
8113,7 → 7996,6
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
cres |
stapc 013270 -- start @ 13270 (2op mem) |
wtgo |
rpc d=013312 -- ! pc=halt |
8146,7 → 8028,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
8179,7 → 8060,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
8212,7 → 8092,6
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
cres |
stapc 013270 -- start @ 13270 (2op mem) |
wtgo |
rpc d=013312 -- ! pc=halt |
8245,7 → 8124,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
8278,7 → 8156,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
8351,7 → 8228,6
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
cres |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
8445,7 → 8321,6
wr2 000000 -- r2=0 |
wr3 005201 -- r3= inc r1 |
wr4 005202 -- r4= inc r2 |
cres |
stapc 013402 -- start @ 13402 |
wtgo |
rpc d=013434 -- ! pc |
8477,7 → 8352,6
C Exec test 47.1 (pipeline tester adapted from KDJ11A.MAC, test 121, p. 70) |
# |
wr1 013474 -- r1=13474 (alternate halt) |
cres |
stapc 013440 -- start @ 13440 |
wtgo |
rpc d=013472 -- ! pc |
8525,7 → 8399,7
C Exec code 50 (check that all reserved instructions trap to 10) |
C Test odd address abort |
# |
cres -- console reset |
rst -- console reset |
wps 000000 -- clear psw |
wal 001374 -- clean stack |
bwm 2 |
/rtl/w11a/pdp11_bram.vhd
1,4 → 1,4
-- $Id: pdp11_bram.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: pdp11_bram.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
40,7 → 40,7
AWIDTH : positive := 14); -- address width |
port ( |
CLK : in slbit; -- clock |
GRESET : in slbit; -- general reset |
GRESET : in slbit; -- global reset |
EM_MREQ : in em_mreq_type; -- em request |
EM_SRES : out em_sres_type -- em response |
); |
/rtl/w11a/pdp11_core_rbus.vhd
1,6 → 1,6
-- $Id: pdp11_core_rbus.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: pdp11_core_rbus.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
27,7 → 27,6
-- |
-- Revision History: - |
-- Date Rev Version Comment |
-- 2015-05-09 677 1.5 start/stop/suspend overhaul; reset overhaul |
-- 2014-12-26 621 1.4 use full size 4k word ibus window |
-- 2014-12-21 617 1.3.1 use separate RB_STAT bits for cmderr and cmdmerr |
-- 2014-09-05 591 1.3 use new rlink v4 iface and 4 bit STAT |
66,16 → 65,12
-- 0000: noop |
-- 0001: start |
-- 0010: stop |
-- 0011: step |
-- 0100: creset |
-- 0101: breset |
-- 0110: suspend |
-- 0111: resume |
-- 0011: continue |
-- 0100: step |
-- 1111: reset (soft) |
-- 00010 stat r/-/- cpu status |
-- 9 suspext r/-/- cp_stat: statext |
-- 8 suspint r/-/- cp_stat: statint |
-- 7:04 cpurust r/-/- cp_stat: cpurust |
-- 3 cpususp r/-/- cp_stat: cpususp |
-- 3 cpuhalt r/-/- cp_stat: cpuhalt |
-- 2 cpugo r/-/- cp_stat: cpugo |
-- 1 cmdmerr r/-/- cp_stat: cmdmerr |
-- 0 cmderr r/-/- cp_stat: cmderr |
114,7 → 109,7
RB_SRES : out rb_sres_type; -- rbus: response |
RB_STAT : out slv4; -- rbus: status flags |
RB_LAM : out slbit; -- remote attention |
GRESET : out slbit; -- general reset |
CPU_RESET : out slbit; -- cpu master reset |
CP_CNTL : out cp_cntl_type; -- console control port |
CP_ADDR : out cp_addr_type; -- console address port |
CP_DIN : out slv16; -- console data in |
136,7 → 131,6
state : state_type; -- state |
rbselc : slbit; -- rbus select for core |
rbseli : slbit; -- rbus select for ibus |
rbinit : slbit; -- rbus init seen (1 cycle pulse) |
cpreq : slbit; -- cp request flag |
cpfunc : slv5; -- cp function |
cpugo_1 : slbit; -- prev cycle cpugo |
152,7 → 146,6
constant regs_init : regs_type := ( |
s_idle, -- state |
'0','0', -- rbselc,rbseli |
'0', -- rbinit |
'0', -- cpreq |
(others=>'0'), -- cpfunc |
'0', -- cpugo_1 |
193,6 → 186,7
variable irbena : slbit := '0'; |
|
variable icpreq : slbit := '0'; |
variable icpureset : slbit := '0'; |
variable icpaddr : cp_addr_type := cp_addr_init; |
|
begin |
209,12 → 203,11
irbena := RB_MREQ.re or RB_MREQ.we; |
|
icpreq := '0'; |
icpureset := '0'; |
|
-- generate single cycle pulse in case init against rbus base address seen |
-- is used to generate some state machine resets via GRESET |
n.rbinit := '0'; |
-- look for init's against the rbus base address, generate subsystem resets |
if RB_MREQ.init='1' and RB_MREQ.addr=RB_ADDR_CORE then |
n.rbinit := RB_MREQ.din(0); |
icpureset := RB_MREQ.din(0); |
end if; |
|
-- rbus address decoder |
266,13 → 259,11
end if; |
|
when c_rbaddr_stat => -- stat ------------------ |
irb_dout(c_stat_rbf_suspext) := CP_STAT.suspext; |
irb_dout(c_stat_rbf_suspint) := CP_STAT.suspint; |
irb_dout(c_stat_rbf_cmderr) := CP_STAT.cmderr; |
irb_dout(c_stat_rbf_cmdmerr) := CP_STAT.cmdmerr; |
irb_dout(c_stat_rbf_cpugo) := CP_STAT.cpugo; |
irb_dout(c_stat_rbf_cpuhalt) := CP_STAT.cpuhalt; |
irb_dout(c_stat_rbf_cpurust) := CP_STAT.cpurust; |
irb_dout(c_stat_rbf_cpususp) := CP_STAT.cpususp; |
irb_dout(c_stat_rbf_cpugo) := CP_STAT.cpugo; |
irb_dout(c_stat_rbf_cmdmerr) := CP_STAT.cmdmerr; |
irb_dout(c_stat_rbf_cmderr) := CP_STAT.cmderr; |
|
when c_rbaddr_psw => -- psw ------------------- |
if irbena = '1' then |
421,12 → 412,12
|
RB_STAT(3) <= CP_STAT.cmderr; |
RB_STAT(2) <= CP_STAT.cmdmerr; |
RB_STAT(1) <= CP_STAT.cpususp; |
RB_STAT(1) <= CP_STAT.cpuhalt or CP_STAT.cpurust(CP_STAT.cpurust'left); |
RB_STAT(0) <= CP_STAT.cpugo; |
|
RB_LAM <= irb_lam; |
|
GRESET <= R_REGS.rbinit; |
CPU_RESET <= icpureset; |
|
CP_CNTL.req <= r.cpreq; |
CP_CNTL.func <= r.cpfunc; |
/rtl/w11a/pdp11_mem70.vhd
1,4 → 1,4
-- $Id: pdp11_mem70.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: pdp11_mem70.vhd 644 2015-02-08 22:56:54Z mueller $ |
-- |
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
43,7 → 43,7
entity pdp11_mem70 is -- 11/70 memory system registers |
port ( |
CLK : in slbit; -- clock |
CRESET : in slbit; -- cpu reset |
CRESET : in slbit; -- console reset |
HM_ENA : in slbit; -- hit/miss enable |
HM_VAL : in slbit; -- hit/miss value |
CACHE_FMISS : out slbit; -- cache force miss |
/rtl/w11a/pdp11_core.vhd
1,6 → 1,6
-- $Id: pdp11_core.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: pdp11_core.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2006-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
20,7 → 20,7
-- pdp11_decode |
-- pdp11_sequencer |
-- pdp11_irq |
-- pdp11_reg70 |
-- pdp11_sys70 |
-- ibus/ib_sres_or_4 |
-- |
-- Test bench: tb/tb_pdp11core |
30,8 → 30,6
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-09 679 1.4 start/stop/suspend overhaul; reset overhaul |
-- 2015-04-30 670 1.3.2 rename pdp11_sys70 -> pdp11_reg70 |
-- 2011-11-18 427 1.3.1 now numeric_std clean |
-- 2010-06-13 305 1.3 add CP_ADDR in port; drop R_CPDIN, R_CPOUT; _vmbox |
-- CP_ADDR now from in port; dpath CP_DIN now from in |
71,20 → 69,14
CP_DIN : in slv16; -- console data in |
CP_STAT : out cp_stat_type; -- console status port |
CP_DOUT : out slv16; -- console data out |
ESUSP_O : out slbit; -- external suspend output |
ESUSP_I : in slbit; -- external suspend input |
ITIMER : out slbit; -- instruction timer |
EBREAK : in slbit; -- execution break |
DBREAK : in slbit; -- data break |
EI_PRI : in slv3; -- external interrupt priority |
EI_VECT : in slv9_2; -- external interrupt vector |
EI_ACKM : out slbit; -- external interrupt acknowledge |
EM_MREQ : out em_mreq_type; -- external memory: request |
EM_SRES : in em_sres_type; -- external memory: response |
CRESET : out slbit; -- cpu reset |
BRESET : out slbit; -- bus reset |
IB_MREQ_M : out ib_mreq_type; -- ibus master request (master) |
IB_SRES_M : in ib_sres_type; -- ibus slave response (master) |
BRESET : out slbit; -- ibus reset |
IB_MREQ_M : out ib_mreq_type; -- inbus master request (master) |
IB_SRES_M : in ib_sres_type; -- inbus slave response (master) |
DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath |
DM_STAT_VM : out dm_stat_vm_type; -- debug and monitor status - vmbox |
DM_STAT_CO : out dm_stat_co_type -- debug and monitor status - core |
94,8 → 86,10
architecture syn of pdp11_core is |
|
signal GRESET : slbit := '0'; |
signal CRESET_L : slbit := '0'; |
signal CRESET : slbit := '0'; |
signal BRESET_L : slbit := '0'; |
signal SEQ_CRESET : slbit := '0'; |
signal SEQ_BRESET : slbit := '0'; |
signal VM_CNTL : vm_cntl_type := vm_cntl_init; |
signal VM_STAT : vm_stat_type := vm_stat_init; |
signal MMU_MONI : mmu_moni_type := mmu_moni_init; |
124,12 → 118,14
begin |
|
GRESET <= RESET; |
CRESET <= RESET or SEQ_CRESET; |
BRESET_L <= RESET or SEQ_CRESET or SEQ_BRESET; |
|
VMBOX : pdp11_vmbox |
port map ( |
CLK => CLK, |
GRESET => GRESET, |
CRESET => CRESET_L, |
CRESET => CRESET, |
BRESET => BRESET_L, |
CP_ADDR => CP_ADDR, |
VM_CNTL => VM_CNTL, |
149,7 → 145,7
DPATH : pdp11_dpath |
port map ( |
CLK => CLK, |
CRESET => CRESET_L, |
CRESET => CRESET, |
CNTL => DP_CNTL, |
STAT => DP_STAT, |
CP_DIN => CP_DIN, |
184,18 → 180,13
VM_STAT => VM_STAT, |
INT_PRI => INT_PRI, |
INT_VECT => INT_VECT, |
INT_ACK => INT_ACK, |
CRESET => CRESET_L, |
BRESET => BRESET_L, |
CRESET => SEQ_CRESET, |
BRESET => SEQ_BRESET, |
MMU_MONI => MMU_MONI, |
DP_CNTL => DP_CNTL, |
VM_CNTL => VM_CNTL, |
CP_STAT => CP_STAT_L, |
ESUSP_O => ESUSP_O, |
ESUSP_I => ESUSP_I, |
ITIMER => ITIMER, |
EBREAK => EBREAK, |
DBREAK => DBREAK, |
INT_ACK => INT_ACK, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_SEQ |
); |
214,10 → 205,10
IB_SRES => IB_SRES_IRQ |
); |
|
REG70 : pdp11_reg70 |
SYS70 : pdp11_sys70 |
port map ( |
CLK => CLK, |
CRESET => CRESET_L, |
CRESET => CRESET, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_SYS |
); |
235,13 → 226,10
|
CP_STAT <= CP_STAT_L; |
|
CRESET <= CRESET_L; |
BRESET <= BRESET_L; |
|
DM_STAT_CO.cpugo <= CP_STAT_L.cpugo; |
DM_STAT_CO.cpususp <= CP_STAT_L.cpususp; |
DM_STAT_CO.suspint <= CP_STAT_L.suspint; |
DM_STAT_CO.suspext <= CP_STAT_L.suspext; |
DM_STAT_CO.cpugo <= CP_STAT_L.cpugo; |
DM_STAT_CO.cpuhalt <= CP_STAT_L.cpuhalt; |
|
end syn; |
|
/rtl/w11a/pdp11_mmu_ssr12.vhd
1,4 → 1,4
-- $Id: pdp11_mmu_ssr12.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: pdp11_mmu_ssr12.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
47,7 → 47,7
entity pdp11_mmu_ssr12 is -- mmu register ssr1 and ssr2 |
port ( |
CLK : in slbit; -- clock |
CRESET : in slbit; -- cpu reset |
CRESET : in slbit; -- console reset |
TRACE : in slbit; -- trace enable |
MONI : in mmu_moni_type; -- MMU monitor port data |
IB_MREQ : in ib_mreq_type; -- ibus request |
/rtl/w11a/pdp11_tmu_sb.vhd
1,4 → 1,4
-- $Id: pdp11_tmu_sb.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: pdp11_tmu_sb.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2009- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
36,10 → 36,10
ENAPIN : integer := 13); -- SB_CNTL signal to use for enable |
port ( |
CLK : in slbit; -- clock |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath |
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox |
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core |
DM_STAT_SY : in dm_stat_sy_type -- debug and monitor status - system |
DM_STAT_DP : in dm_stat_dp_type; -- DM dpath |
DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox |
DM_STAT_CO : in dm_stat_co_type; -- DM core |
DM_STAT_SY : in dm_stat_sy_type -- DM system |
); |
end pdp11_tmu_sb; |
|
/rtl/w11a/pdp11_sequencer.vhd
1,4 → 1,4
-- $Id: pdp11_sequencer.vhd 679 2015-05-13 17:38:46Z mueller $ |
-- $Id: pdp11_sequencer.vhd 643 2015-02-07 17:41:53Z mueller $ |
-- |
-- Copyright 2006-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
18,11 → 18,10
-- Dependencies: ib_sel |
-- Test bench: tb/tb_pdp11_core (implicit) |
-- Target Devices: generic |
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 |
-- Tool versions: ise 8.2-14.7; viv 2014.1; ghdl 0.18-0.31 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-10 678 1.6 start/stop/suspend overhaul; reset overhaul |
-- 2015-02-07 643 1.5.2 s_op_wait: load R0 in DSRC for DR emulation |
-- 2014-07-12 569 1.5.1 rename s_opg_div_zero -> s_opg_div_quit; |
-- use DP_STAT.div_quit; set munit_s_div_sr; |
77,7 → 76,7
entity pdp11_sequencer is -- CPU sequencer |
port ( |
CLK : in slbit; -- clock |
GRESET : in slbit; -- general reset |
GRESET : in slbit; -- global reset |
PSW : in psw_type; -- processor status |
PC : in slv16; -- program counter |
IREG : in slv16; -- IREG |
87,18 → 86,13
VM_STAT : in vm_stat_type; -- virtual memory status port |
INT_PRI : in slv3; -- interrupt priority |
INT_VECT : in slv9_2; -- interrupt vector |
INT_ACK : out slbit; -- interrupt acknowledge |
CRESET : out slbit; -- cpu reset |
BRESET : out slbit; -- bus reset |
CRESET : out slbit; -- console reset |
BRESET : out slbit; -- ibus reset |
MMU_MONI : out mmu_moni_type; -- mmu monitor port |
DP_CNTL : out dpath_cntl_type; -- data path control |
VM_CNTL : out vm_cntl_type; -- virtual memory control port |
CP_STAT : out cp_stat_type; -- console port status |
ESUSP_O : out slbit; -- external suspend output |
ESUSP_I : in slbit; -- external suspend input |
ITIMER : out slbit; -- instruction timer |
EBREAK : in slbit; -- execution break |
DBREAK : in slbit; -- data break |
INT_ACK : out slbit; -- interrupt acknowledge |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type -- ibus response |
); |
317,12 → 311,16
proc_next: process (R_STATE, R_STATUS, PSW, PC, CP_CNTL, |
ID_STAT, R_IDSTAT, IREG, VM_STAT, DP_STAT, |
R_CPUERR, R_VMSTAT, IB_MREQ, IBSEL_CPUERR, |
INT_PRI, INT_VECT, ESUSP_I, EBREAK, DBREAK) |
INT_PRI, INT_VECT) |
|
variable nstate : state_type; |
variable nstatus : cpustat_type := cpustat_init; |
variable ncpuerr : cpuerr_type := cpuerr_init; |
|
variable ncreset : slbit := '0'; |
variable nbreset : slbit := '0'; |
variable nintack : slbit := '0'; |
|
variable ndpcntl : dpath_cntl_type := dpath_cntl_init; |
variable nvmcntl : vm_cntl_type := vm_cntl_init; |
variable nidstat : decode_stat_type := decode_stat_init; |
500,12 → 498,10
R_STATUS.trap_ysv='1' or nstatus.trap_ysv='1' or |
PSW.tflag='1' then |
nstate := s_trap_disp; |
elsif R_STATUS.cpugo='1' and -- running |
R_STATUS.cpususp='0' and -- and not suspended |
not R_STATUS.cmdbusy='1' then -- and no cmd pending |
nstate := s_ifetch; -- fetch next |
elsif R_STATUS.cpugo='1' and not R_STATUS.cmdbusy='1' then |
nstate := s_ifetch; |
else |
nstate := s_idle; -- otherwise idle |
nstate := s_idle; |
end if; |
end procedure do_fork_next; |
|
524,15 → 520,13
R_STATUS.trap_ysv='1' or nstatus.trap_ysv='1' or |
PSW.tflag='1' then |
nstate := s_trap_disp; |
elsif R_STATUS.cpugo='1' and -- running |
R_STATUS.cpususp='0' and -- and not suspended |
not R_STATUS.cmdbusy='1' then -- and no cmd pending |
nvmcntl.req := '1'; -- read next instruction |
ndpcntl.gpr_pcinc := '1'; -- inc PC |
nmmumoni.istart := '1'; -- signal istart to MMU |
nstate := s_ifetch_w; -- next: wait for fetched instruction |
elsif R_STATUS.cpugo='1' and not R_STATUS.cmdbusy='1' then |
nvmcntl.req := '1'; |
ndpcntl.gpr_pcinc := '1'; |
nmmumoni.istart := '1'; |
nstate := s_ifetch_w; |
else |
nstate := s_idle; -- otherwise idle |
nstate := s_idle; |
end if; |
end procedure do_fork_next_pref; |
|
558,20 → 552,10
ncpuerr := R_CPUERR; |
|
nstatus.cpuwait := '0'; -- wait flag 0 unless set in s_op_wait |
|
-- itimer pulse logic: |
-- if neither running nor suspended --> free run, set itimer = 1 |
-- otherwise clear to ensure single cycle pulses generated by |
-- s_idecode or s_op_wait |
if R_STATUS.cpugo='0' and R_STATUS.cpususp='0' then |
nstatus.itimer := '1'; |
else |
nstatus.itimer := '0'; |
end if; |
|
nstatus.creset := '0'; -- ensure single cycle pulse |
nstatus.breset := '0'; -- dito |
nstatus.intack := '0'; -- dito |
ncreset := '0'; |
nbreset := '0'; |
nintack := '0'; |
|
nidstat := R_IDSTAT; |
|
685,22 → 669,20
if R_STATUS.cmdbusy = '1' then |
case R_STATUS.cpfunc is |
|
when c_cpfunc_noop => -- noop : no operation ------- |
when c_cpfunc_noop => -- noop : no operation -------- |
nstatus.cmdack := '1'; |
nstate := s_idle; |
|
when c_cpfunc_start => -- start : cpu start --------- |
when c_cpfunc_sta => -- sta : cpu start ----------- |
ncreset := '1'; |
nstatus.cmdack := '1'; |
if R_STATUS.cpugo = '1' then -- if already running |
nstatus.cmderr := '1'; -- reject |
else -- if not running |
nstatus.cpugo := '1'; -- start cpu |
nstatus.cpurust := c_cpurust_runs; |
nstatus.waitsusp := '0'; |
end if; |
nstatus.cpugo := '1'; |
nstatus.cpuhalt := '0'; |
nstatus.cpurust := c_cpurust_runs; |
nstatus.waitsusp := '0'; |
nstate := s_idle; |
|
when c_cpfunc_stop => -- stop : cpu stop ----------- |
when c_cpfunc_sto => -- sto : cpu stop ------------ |
nstatus.cmdack := '1'; |
nstatus.cpugo := '0'; |
nstatus.cpurust := c_cpurust_stop; |
707,13 → 689,22
nstatus.waitsusp := '0'; |
nstate := s_idle; |
|
when c_cpfunc_step => -- step : cpu step ----------- |
when c_cpfunc_cont => -- cont : cpu continue -------- |
nstatus.cmdack := '1'; |
nstatus.cpugo := '1'; |
nstatus.cpuhalt := '0'; |
nstatus.cpurust := c_cpurust_runs; |
nstatus.waitsusp := '0'; |
nstate := s_idle; |
|
when c_cpfunc_step => -- step : cpu step ------------ |
nstatus.cmdack := '1'; |
nstatus.cpustep := '1'; |
nstatus.cpuhalt := '0'; |
nstatus.cpurust := c_cpurust_step; |
nstatus.waitsusp := '0'; |
if int_pending = '1' then |
nstatus.intack := '1'; |
nintack := '1'; |
nstatus.intvect := INT_VECT; |
nstate := s_int_ext; |
else |
720,43 → 711,15
nstate := s_ifetch; |
end if; |
|
when c_cpfunc_creset => -- creset : cpu reset -------- |
when c_cpfunc_rst => -- rst : cpu reset (soft) ---- |
ncreset := '1'; |
nstatus.cmdack := '1'; |
if R_STATUS.cpugo = '1' then -- if already running |
nstatus.cmderr := '1'; -- reject |
else -- if not running |
nstatus.creset := '1'; -- do cpu reset |
nstatus.breset := '1'; -- and bus reset ! |
nstatus.suspint := '0'; -- clear suspend |
nstatus.cpurust := c_cpurust_init; |
end if; |
nstatus.cpugo := '0'; |
nstatus.cpuhalt := '0'; |
nstatus.cpurust := c_cpurust_reset; |
nstatus.waitsusp := '0'; |
nstate := s_idle; |
|
when c_cpfunc_breset => -- breset : bus reset -------- |
nstatus.cmdack := '1'; |
if R_STATUS.cpugo = '1' then -- if already running |
nstatus.cmderr := '1'; -- reject |
else -- if not running |
nstatus.breset := '1'; -- do bus reset only |
end if; |
nstate := s_idle; |
|
when c_cpfunc_suspend => -- suspend : cpu suspend ----- |
nstatus.cmdack := '1'; |
nstatus.suspint := '1'; |
nstatus.cpurust := c_cpurust_susp; |
nstate := s_idle; |
|
when c_cpfunc_resume => -- resume : cpu resume ------- |
nstatus.cmdack := '1'; |
nstatus.suspint := '0'; |
if R_STATUS.cpugo = '1' then |
nstatus.cpurust := c_cpurust_runs; |
else |
nstatus.cpurust := c_cpurust_stop; |
end if; |
nstate := s_idle; |
|
when c_cpfunc_rreg => -- rreg : read register ------ |
ndpcntl.gpr_adst := R_STATUS.cprnum; |
ndpcntl.ddst_sel := c_dpath_ddst_dst; |
805,14 → 768,13
nstatus.waitsusp := '0'; |
nstate := s_op_wait; |
|
elsif R_STATUS.cpugo = '1' and -- running |
R_STATUS.cpususp='0' then -- and not suspended |
if int_pending = '1' then -- interrupt pending |
nstatus.intack := '1'; -- acknowledle it |
nstatus.intvect := INT_VECT; -- latch vector address |
nstate := s_int_ext; -- and handle |
elsif R_STATUS.cpugo = '1' then |
if int_pending = '1' then |
nintack := '1'; |
nstatus.intvect := INT_VECT; |
nstate := s_int_ext; |
else |
nstate := s_ifetch; -- otherwise fetch intruction |
nstate := s_ifetch; |
end if; |
|
end if; |
867,7 → 829,6
end if; |
|
when s_idecode => |
nstatus.itimer := '1'; -- signal instruction started |
nidstat := ID_STAT; -- register decode status |
if ID_STAT.force_srcsp = '1' then |
ndpcntl.gpr_asrc := c_gpr_sp; |
881,8 → 842,7
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC |
|
if ID_STAT.do_pref_dec='1' and PSW.tflag='0' and int_pending='0' and |
R_STATUS.cpugo='1' and R_STATUS.cpususp='0' and |
not R_STATUS.cmdbusy='1' |
R_STATUS.cpugo='1' and not R_STATUS.cmdbusy='1' |
then |
nvmcntl.req := '1'; |
ndpcntl.gpr_pcinc := '1'; -- (pc)++ |
1513,6 → 1473,7
if is_kmode = '1' then -- if in kernel mode execute |
nmmumoni.idone := '1'; |
nstatus.cpugo := '0'; |
nstatus.cpuhalt := '1'; |
nstatus.cpurust := c_cpurust_halt; |
nstate := s_idle; |
else -- otherwise trap |
1524,7 → 1485,7
ndpcntl.gpr_asrc := "000"; -- load R0 in DSRC for DR emulation |
ndpcntl.dsrc_sel := c_dpath_dsrc_src; |
ndpcntl.dsrc_we := '1'; |
|
|
nstate := s_op_wait; -- spin here |
if is_kmode = '0' then -- but act as nop if not in kernel |
nstate := s_idle; |
1536,8 → 1497,7
nstate := s_idle; |
else |
nstatus.cpuwait := '1'; -- if spinning here, signal with cpuwait |
nstatus.itimer := '1'; -- itimer will stay 1 during a WAIT |
end if; |
end if; |
|
when s_op_trap => -- traps |
lvector := "0000" & R_IDSTAT.trap_vec; -- vector |
1545,7 → 1505,7
|
when s_op_reset => -- RESET |
if is_kmode = '1' then -- if in kernel mode execute |
nstatus.breset := '1'; -- issue bus reset |
nbreset := '1'; |
end if; |
nstate := s_idle; |
|
2295,18 → 2255,6
|
end case; |
|
if DBREAK = '1' then -- handle BREAK |
nstatus.suspint :='1'; |
end if; |
nstatus.suspext := ESUSP_I; |
|
-- handle cpususp transitions |
if nstatus.suspint='1' or nstatus.suspext='1' then |
nstatus.cpususp := '1'; |
elsif R_STATUS.suspint='0' and R_STATUS.suspext='0' then |
nstatus.cpususp := '0'; |
end if; |
|
if nstatus.cmdack = '1' then -- cmdack in next cycle ? Yes we test |
-- nstatus here !! |
nstatus.cmdbusy := '0'; |
2318,11 → 2266,9
N_CPUERR <= ncpuerr; |
N_IDSTAT <= nidstat; |
|
INT_ACK <= R_STATUS.intack; |
CRESET <= R_STATUS.creset; |
BRESET <= R_STATUS.breset; |
ESUSP_O <= R_STATUS.suspint; -- FIXME_code: handle masking later |
ITIMER <= R_STATUS.itimer; |
CRESET <= ncreset; |
BRESET <= nbreset; |
INT_ACK <= nintack; |
|
DP_CNTL <= ndpcntl; |
VM_CNTL <= nvmcntl; |
2342,11 → 2288,9
CP_STAT.cmdmerr <= R_STATUS.cmdmerr; |
CP_STAT.cpugo <= R_STATUS.cpugo; |
CP_STAT.cpustep <= R_STATUS.cpustep; |
CP_STAT.cpuhalt <= R_STATUS.cpuhalt; |
CP_STAT.cpuwait <= R_STATUS.cpuwait; |
CP_STAT.cpususp <= R_STATUS.cpususp; |
CP_STAT.cpurust <= R_STATUS.cpurust; |
CP_STAT.suspint <= R_STATUS.suspint; |
CP_STAT.suspext <= R_STATUS.suspext; |
end process proc_cpstat; |
|
end syn; |
/rtl/w11a/pdp11_vmbox.vhd
1,6 → 1,6
-- $Id: pdp11_vmbox.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: pdp11_vmbox.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2006-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
27,7 → 27,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-04 662 1.6.4 atowidth now 6 (was 5) to support ibdr_rprm reset |
-- 2011-11-18 427 1.6.3 now numeric_std clean |
-- 2010-10-23 335 1.6.2 add r.paddr_iopage, use ib_sel |
-- 2010-10-22 334 1.6.1 deassert ibus be's at end-cycle; fix rmw logic |
75,9 → 74,9
entity pdp11_vmbox is -- virtual memory |
port ( |
CLK : in slbit; -- clock |
GRESET : in slbit; -- general reset |
CRESET : in slbit; -- cpu reset |
BRESET : in slbit; -- bus reset |
GRESET : in slbit; -- global reset |
CRESET : in slbit; -- console reset |
BRESET : in slbit; -- ibus reset |
CP_ADDR : in cp_addr_type; -- console port address |
VM_CNTL : in vm_cntl_type; -- vm control port |
VM_ADDR : in slv16; -- vm address |
97,7 → 96,7
architecture syn of pdp11_vmbox is |
|
constant ibaddr_slim : slv16 := slv(to_unsigned(8#177774#,16)); |
constant atowidth : natural := 6; -- size of access timeout counter |
constant atowidth : natural := 5; -- size of access timeout counter |
|
type state_type is ( |
s_idle, -- s_idle: wait for vm_cntl request |
/rtl/w11a/pdp11_mmu.vhd
1,4 → 1,4
-- $Id: pdp11_mmu.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: pdp11_mmu.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
61,8 → 61,8
entity pdp11_mmu is -- mmu - memory management unit |
port ( |
CLK : in slbit; -- clock |
CRESET : in slbit; -- cpu reset |
BRESET : in slbit; -- bus reset |
CRESET : in slbit; -- console reset |
BRESET : in slbit; -- ibus reset |
CNTL : in mmu_cntl_type; -- control port |
VADDR : in slv16; -- virtual address |
MONI : in mmu_moni_type; -- monitor port |
/rtl/w11a/pdp11_psr.vhd
1,4 → 1,4
-- $Id: pdp11_psr.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: pdp11_psr.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
47,7 → 47,7
entity pdp11_psr is -- processor status word register |
port ( |
CLK : in slbit; -- clock |
CRESET : in slbit; -- cpu reset |
CRESET : in slbit; -- console reset |
DIN : in slv16; -- input data |
CCIN : in slv4; -- cc input |
CCWE : in slbit; -- enable update cc |
/rtl/w11a/pdp11_tmu.vhd
1,6 → 1,6
-- $Id: pdp11_tmu.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: pdp11_tmu.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2008-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
23,7 → 23,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-03 674 1.2 start/stop/suspend overhaul |
-- 2011-12-23 444 1.1 use local clkcycle count instead of simbus global |
-- 2011-11-18 427 1.0.7 now numeric_std clean |
-- 2010-10-17 333 1.0.6 use ibus V2 interface |
52,10 → 51,10
port ( |
CLK : in slbit; -- clock |
ENA : in slbit := '0'; -- enable trace output |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath |
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox |
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core |
DM_STAT_SY : in dm_stat_sy_type -- debug and monitor status - system |
DM_STAT_DP : in dm_stat_dp_type; -- DM dpath |
DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox |
DM_STAT_CO : in dm_stat_co_type; -- DM core |
DM_STAT_SY : in dm_stat_sy_type -- DM system |
); |
end pdp11_tmu; |
|
117,9 → 116,7
write(oline, string'(" vm.ibsres.dout:o")); |
|
write(oline, string'(" co.cpugo:b")); |
write(oline, string'(" co.cpususp:b")); |
write(oline, string'(" co.suspint:b")); |
write(oline, string'(" co.suspext:b")); |
write(oline, string'(" co.cpuhalt:b")); |
|
write(oline, string'(" sy.emmreq.req:b")); |
write(oline, string'(" sy.emmreq.we:b")); |
205,9 → 202,7
writeoct(oline, DM_STAT_VM.ibsres.dout, right, 7); |
|
write(oline, DM_STAT_CO.cpugo, right, 2); |
write(oline, DM_STAT_CO.cpususp, right, 2); |
write(oline, DM_STAT_CO.suspint, right, 2); |
write(oline, DM_STAT_CO.suspext, right, 2); |
write(oline, DM_STAT_CO.cpuhalt, right, 2); |
|
write(oline, DM_STAT_SY.emmreq.req, right, 2); |
write(oline, DM_STAT_SY.emmreq.we, right, 2); |
/rtl/w11a/sys_conf.vhd
1,6 → 1,6
-- $Id: sys_conf.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
13,13 → 13,12
-- |
------------------------------------------------------------------------------ |
-- Package Name: sys_conf |
-- Description: Default definitions |
-- Description: Default definitions for pdp11core (for simple test benches) |
-- |
-- Dependencies: - |
-- Tool versions: xst 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 |
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-01 672 1.1 adopt to pdp11_sys70 |
-- 2008-02-23 118 1.0 Initial version |
------------------------------------------------------------------------------ |
|
30,12 → 29,19
|
package sys_conf is |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
|
constant sys_conf_bram_awidth : integer := 15; -- 32 kB BRAM |
constant sys_conf_mem_losize : integer := 8#000777#;-- 32 kByte |
-- constant sys_conf_bram_awidth : integer := 14; -- 16 kB BRAM |
-- constant sys_conf_mem_losize : integer := 8#000377#;-- 16 kByte |
|
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon |
|
end package sys_conf; |
|
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory |
-- 2 211 111 111 110 000 000 000 |
-- 1 098 765 432 109 876 543 210 |
-- |
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte |
-- 0 000 000 011 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte |
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte |
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte |
-- upper 256 kB excluded for 11/70 UB |
/rtl/w11a/pdp11.vhd
1,6 → 1,6
-- $Id: pdp11.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: pdp11.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2006-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2006-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
20,9 → 20,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-09 677 1.6 start/stop/suspend overhaul; reset overhaul |
-- 2015-05-01 672 1.5.5 add pdp11_sys70, sys_hio70 |
-- 2015-04-30 670 1.5.4 rename pdp11_sys70 -> pdp11_reg70 |
-- 2015-02-20 649 1.5.3 add pdp11_statleds |
-- 2015-02-08 644 1.5.2 add pdp11_bram_memctl |
-- 2014-08-28 588 1.5.1 use new rlink v4 iface and 4 bit STAT |
346,18 → 343,12
cmdmerr : slbit; -- command memory access error |
cpugo : slbit; -- CPU go state |
cpustep : slbit; -- CPU step flag |
cpususp : slbit; -- CPU susp flag |
cpuhalt : slbit; -- CPU halt flag |
cpuwait : slbit; -- CPU wait flag |
cpurust : slv4; -- CPU run status |
suspint : slbit; -- internal suspend flag |
suspext : slbit; -- external suspend flag |
cpfunc : slv5; -- current control port function |
cprnum : slv3; -- current control port register number |
waitsusp : slbit; -- WAIT instruction suspended |
itimer : slbit; -- ITIMER pulse |
creset : slbit; -- CRESET pulse |
breset : slbit; -- BRESET pulse |
intack : slbit; -- INT_ACK pulse |
intvect : slv9_2; -- current interrupt vector |
trap_mmu : slbit; -- mmu trace trap pending |
trap_ysv : slbit; -- ysv trap pending |
367,13 → 358,11
end record cpustat_type; |
|
constant cpustat_init : cpustat_type := ( |
'0','0','0','0', -- cmdbusy,cmdack,cmderr,cmdmerr |
'0','0','0','0', -- cpugo,cpustep,cpususp,cpuwait |
'0','0','0','0', -- cmd.. |
'0','0','0','0', -- cpu.. |
c_cpurust_init, -- cpurust |
'0','0', -- suspint,suspext |
"00000","000", -- cpfunc, cprnum |
'0', -- waitsusp |
'0','0','0','0', -- itimer,creset,breset,intack |
(others=>'0'), -- intvect |
'0','0','0', -- trap_(mmu|ysv), prefdone |
'0','0' -- do_gprwe, do_intrsv |
540,22 → 529,19
rnum : slv3; -- register number |
end record cp_cntl_type; |
|
constant c_cpfunc_noop : slv5 := "00000"; -- noop : no operation |
constant c_cpfunc_start : slv5 := "00001"; -- sta : cpu start |
constant c_cpfunc_stop : slv5 := "00010"; -- sto : cpu stop |
constant c_cpfunc_step : slv5 := "00011"; -- cont : cpu step |
constant c_cpfunc_creset : slv5 := "00100"; -- step : cpu cpu reset |
constant c_cpfunc_breset : slv5 := "00101"; -- rst : cpu bus reset |
constant c_cpfunc_suspend : slv5 := "00110"; -- rst : cpu suspend |
constant c_cpfunc_resume : slv5 := "00111"; -- rst : cpu resume |
constant c_cpfunc_noop : slv5 := "00000"; -- noop : no operation |
constant c_cpfunc_sta : slv5 := "00001"; -- sta : cpu start |
constant c_cpfunc_sto : slv5 := "00010"; -- sto : cpu stop |
constant c_cpfunc_cont : slv5 := "00011"; -- cont : cpu continue |
constant c_cpfunc_step : slv5 := "00100"; -- step : cpu step |
constant c_cpfunc_rst : slv5 := "01111"; -- rst : cpu reset (soft) |
constant c_cpfunc_rreg : slv5 := "10000"; -- rreg : read register |
constant c_cpfunc_wreg : slv5 := "10001"; -- wreg : write register |
constant c_cpfunc_rpsw : slv5 := "10010"; -- rpsw : read psw |
constant c_cpfunc_wpsw : slv5 := "10011"; -- wpsw : write psw |
constant c_cpfunc_rmem : slv5 := "10100"; -- rmem : read memory |
constant c_cpfunc_wmem : slv5 := "10101"; -- wmem : write memory |
|
constant c_cpfunc_rreg : slv5 := "10000"; -- rreg : read register |
constant c_cpfunc_wreg : slv5 := "10001"; -- wreg : write register |
constant c_cpfunc_rpsw : slv5 := "10010"; -- rpsw : read psw |
constant c_cpfunc_wpsw : slv5 := "10011"; -- wpsw : write psw |
constant c_cpfunc_rmem : slv5 := "10100"; -- rmem : read memory |
constant c_cpfunc_wmem : slv5 := "10101"; -- wmem : write memory |
|
constant cp_cntl_init : cp_cntl_type := ('0',c_cpfunc_noop,"000"); |
|
type cp_stat_type is record -- control port status |
565,18 → 551,15
cmdmerr : slbit; -- command memory access error |
cpugo : slbit; -- CPU go state |
cpustep : slbit; -- CPU step flag |
cpuhalt : slbit; -- CPU halt flag |
cpuwait : slbit; -- CPU wait flag |
cpususp : slbit; -- CPU susp flag |
cpurust : slv4; -- CPU run status |
suspint : slbit; -- internal suspend |
suspext : slbit; -- external suspend |
end record cp_stat_type; |
|
constant cp_stat_init : cp_stat_type := ( |
'0','0','0','0', -- cmd... |
'0','0','0','0', -- cpu... |
(others=>'0'), -- cpurust |
'0','0' -- susp... |
(others=>'0') -- cpurust |
); |
|
type cp_addr_type is record -- control port address |
636,15 → 619,10
|
type dm_stat_co_type is record -- debug and monitor status - core |
cpugo : slbit; -- cpugo state flag |
cpususp : slbit; -- cpususp state flag |
suspint : slbit; -- suspint state flag |
suspext : slbit; -- suspext state flag |
cpuhalt : slbit; -- cpuhalt state flag |
end record dm_stat_co_type; |
|
constant dm_stat_co_init : dm_stat_co_type := ( |
'0','0', -- cpu... |
'0','0' -- susp... |
); |
constant dm_stat_co_init : dm_stat_co_type := ('0','0'); |
|
type dm_stat_sy_type is record -- debug and monitor status - system |
emmreq : em_mreq_type; -- external memory: request |
652,11 → 630,7
chit : slbit; -- cache hit |
end record dm_stat_sy_type; |
|
constant dm_stat_sy_init : dm_stat_sy_type := ( |
em_mreq_init, -- emmreq |
em_sres_init, -- emsres |
'0' -- chit |
); |
constant dm_stat_sy_init : dm_stat_sy_type := (em_mreq_init,em_sres_init,'0'); |
|
-- rbus interface definitions ------------------------------------------------ |
|
685,13 → 659,11
constant c_ah_rbf_ena_22bit: integer := 6; -- ah: 22bit |
subtype c_ah_rbf_addr is integer range 5 downto 0; -- ah: address |
|
constant c_stat_rbf_suspext: integer := 9; -- stat field: suspext |
constant c_stat_rbf_suspint: integer := 8; -- stat field: suspint |
constant c_stat_rbf_cmderr: integer := 0; -- stat field: cmderr |
constant c_stat_rbf_cmdmerr: integer := 1; -- stat field: cmdmerr |
constant c_stat_rbf_cpugo: integer := 2; -- stat field: cpugo |
constant c_stat_rbf_cpuhalt: integer := 3; -- stat field: cpuhalt |
subtype c_stat_rbf_cpurust is integer range 7 downto 4; -- cpurust |
constant c_stat_rbf_cpususp: integer := 3; -- stat field: cpususp |
constant c_stat_rbf_cpugo: integer := 2; -- stat field: cpugo |
constant c_stat_rbf_cmdmerr: integer := 1; -- stat field: cmdmerr |
constant c_stat_rbf_cmderr: integer := 0; -- stat field: cmderr |
|
subtype c_membe_rbf_be is integer range 1 downto 0; -- membe: be's |
constant c_membe_rbf_stick: integer := 2; -- membe: sticky flag |
722,7 → 694,7
component pdp11_psr is -- processor status word register |
port ( |
CLK : in slbit; -- clock |
CRESET : in slbit; -- cpu reset |
CRESET : in slbit; -- console reset |
DIN : in slv16; -- input data |
CCIN : in slv4; -- cc input |
CCWE : in slbit; -- enable update cc |
871,7 → 843,7
component pdp11_mmu_ssr12 is -- mmu register ssr1 and ssr2 |
port ( |
CLK : in slbit; -- clock |
CRESET : in slbit; -- cpu reset |
CRESET : in slbit; -- console reset |
TRACE : in slbit; -- trace enable |
MONI : in mmu_moni_type; -- MMU monitor port data |
IB_MREQ : in ib_mreq_type; -- ibus request |
882,8 → 854,8
component pdp11_mmu is -- mmu - memory management unit |
port ( |
CLK : in slbit; -- clock |
CRESET : in slbit; -- cpu reset |
BRESET : in slbit; -- bus reset |
CRESET : in slbit; -- console reset |
BRESET : in slbit; -- ibus reset |
CNTL : in mmu_cntl_type; -- control port |
VADDR : in slv16; -- virtual address |
MONI : in mmu_moni_type; -- monitor port |
897,9 → 869,9
component pdp11_vmbox is -- virtual memory |
port ( |
CLK : in slbit; -- clock |
GRESET : in slbit; -- general reset |
CRESET : in slbit; -- cpu reset |
BRESET : in slbit; -- bus reset |
GRESET : in slbit; -- global reset |
CRESET : in slbit; -- console reset |
BRESET : in slbit; -- ibus reset |
CP_ADDR : in cp_addr_type; -- console port address |
VM_CNTL : in vm_cntl_type; -- vm control port |
VM_ADDR : in slv16; -- vm address |
919,7 → 891,7
component pdp11_dpath is -- CPU datapath |
port ( |
CLK : in slbit; -- clock |
CRESET : in slbit; -- cpu reset |
CRESET : in slbit; -- console reset |
CNTL : in dpath_cntl_type; -- control interface |
STAT : out dpath_stat_type; -- status interface |
CP_DIN : in slv16; -- console port data in |
932,7 → 904,7
VM_DIN : out slv16; -- virt. memory data in |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status - dpath |
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status |
); |
end component; |
|
946,7 → 918,7
component pdp11_sequencer is -- cpu sequencer |
port ( |
CLK : in slbit; -- clock |
GRESET : in slbit; -- general reset |
GRESET : in slbit; -- global reset |
PSW : in psw_type; -- processor status |
PC : in slv16; -- program counter |
IREG : in slv16; -- IREG |
956,18 → 928,13
VM_STAT : in vm_stat_type; -- virtual memory status port |
INT_PRI : in slv3; -- interrupt priority |
INT_VECT : in slv9_2; -- interrupt vector |
INT_ACK : out slbit; -- interrupt acknowledge |
CRESET : out slbit; -- cpu reset |
BRESET : out slbit; -- bus reset |
CRESET : out slbit; -- console reset |
BRESET : out slbit; -- ibus reset |
MMU_MONI : out mmu_moni_type; -- mmu monitor port |
DP_CNTL : out dpath_cntl_type; -- data path control |
VM_CNTL : out vm_cntl_type; -- virtual memory control port |
CP_STAT : out cp_stat_type; -- console port status |
ESUSP_O : out slbit; -- external suspend output |
ESUSP_I : in slbit; -- external suspend input |
ITIMER : out slbit; -- instruction timer |
EBREAK : in slbit; -- execution break |
DBREAK : in slbit; -- data break |
INT_ACK : out slbit; -- interrupt acknowledge |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type -- ibus response |
); |
976,7 → 943,7
component pdp11_irq is -- interrupt requester |
port ( |
CLK : in slbit; -- clock |
BRESET : in slbit; -- bus reset |
BRESET : in slbit; -- ibus reset |
INT_ACK : in slbit; -- interrupt acknowledge from CPU |
EI_PRI : in slv3; -- external interrupt priority |
EI_VECT : in slv9_2; -- external interrupt vector |
999,10 → 966,10
); |
end component; |
|
component pdp11_reg70 is -- 11/70 memory system registers |
component pdp11_sys70 is -- 11/70 memory system registers |
port ( |
CLK : in slbit; -- clock |
CRESET : in slbit; -- cpu reset |
CRESET : in slbit; -- console reset |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type -- ibus response |
); |
1011,7 → 978,7
component pdp11_mem70 is -- 11/70 memory system registers |
port ( |
CLK : in slbit; -- clock |
CRESET : in slbit; -- cpu reset |
CRESET : in slbit; -- console reset |
HM_ENA : in slbit; -- hit/miss enable |
HM_VAL : in slbit; -- hit/miss value |
CACHE_FMISS : out slbit; -- cache force miss |
1023,7 → 990,7
component pdp11_cache is -- cache |
port ( |
CLK : in slbit; -- clock |
GRESET : in slbit; -- general reset |
GRESET : in slbit; -- global reset |
EM_MREQ : in em_mreq_type; -- em request |
EM_SRES : out em_sres_type; -- em response |
FMISS : in slbit; -- force miss |
1048,18 → 1015,12
CP_DIN : in slv16; -- console data in |
CP_STAT : out cp_stat_type; -- console status port |
CP_DOUT : out slv16; -- console data out |
ESUSP_O : out slbit; -- external suspend output |
ESUSP_I : in slbit; -- external suspend input |
ITIMER : out slbit; -- instruction timer |
EBREAK : in slbit; -- execution break |
DBREAK : in slbit; -- data break |
EI_PRI : in slv3; -- external interrupt priority |
EI_VECT : in slv9_2; -- external interrupt vector |
EI_ACKM : out slbit; -- external interrupt acknowledge |
EM_MREQ : out em_mreq_type; -- external memory: request |
EM_SRES : in em_sres_type; -- external memory: response |
CRESET : out slbit; -- cpu reset |
BRESET : out slbit; -- bus reset |
BRESET : out slbit; -- ibus reset |
IB_MREQ_M : out ib_mreq_type; -- ibus master request (master) |
IB_SRES_M : in ib_sres_type; -- ibus slave response (master) |
DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath |
1072,10 → 1033,10
port ( |
CLK : in slbit; -- clock |
ENA : in slbit := '0'; -- enable trace output |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath |
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox |
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core |
DM_STAT_SY : in dm_stat_sy_type -- debug and monitor status - system |
DM_STAT_DP : in dm_stat_dp_type; -- DM dpath |
DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox |
DM_STAT_CO : in dm_stat_co_type; -- DM core |
DM_STAT_SY : in dm_stat_sy_type -- DM system |
); |
end component; |
|
1084,10 → 1045,10
ENAPIN : integer := 13); -- SB_CNTL signal to use for enable |
port ( |
CLK : in slbit; -- clock |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath |
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox |
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core |
DM_STAT_SY : in dm_stat_sy_type -- debug and monitor status - system |
DM_STAT_DP : in dm_stat_dp_type; -- DM dpath |
DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox |
DM_STAT_CO : in dm_stat_co_type; -- DM core |
DM_STAT_SY : in dm_stat_sy_type -- DM system |
); |
end component; |
|
1096,7 → 1057,7
CDWIDTH : positive := 3); -- clock divider width |
port ( |
CLK : in slbit; -- clock |
GRESET : in slbit; -- general reset |
GRESET : in slbit; -- global reset |
ROW0 : in slv22; -- led row 0 (22 leds, top) |
ROW1 : in slv16; -- led row 1 (16 leds) |
ROW2 : in slv16; -- led row 2 (16 leds) |
1115,7 → 1076,7
AWIDTH : positive := 14); -- address width |
port ( |
CLK : in slbit; -- clock |
GRESET : in slbit; -- general reset |
GRESET : in slbit; -- global reset |
EM_MREQ : in em_mreq_type; -- em request |
EM_SRES : out em_sres_type -- em response |
); |
1147,7 → 1108,7
MEM_ACT_R : in slbit; -- memory active read |
MEM_ACT_W : in slbit; -- memory active write |
CP_STAT : in cp_stat_type; -- console port status |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status |
STATLEDS : out slv8 -- 8 bit CPU status |
); |
end component; |
1158,7 → 1119,7
port ( |
SEL : in slbit; -- select (0=stat;1=dr) |
STATLEDS : in slv8; -- 8 bit CPU status |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status |
LED : out slv(LWIDTH-1 downto 0) -- hio leds |
); |
end component; |
1169,7 → 1130,7
port ( |
SEL : in slv2; -- select |
ABCLKDIV : in slv16; -- serport clock divider |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status |
DISPREG : in slv16; -- display register |
DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data |
); |
1186,7 → 1147,7
RB_SRES : out rb_sres_type; -- rbus: response |
RB_STAT : out slv4; -- rbus: status flags |
RB_LAM : out slbit; -- remote attention |
GRESET : out slbit; -- general reset |
CPU_RESET : out slbit; -- cpu master reset |
CP_CNTL : out cp_cntl_type; -- console control port |
CP_ADDR : out cp_addr_type; -- console address port |
CP_DIN : out slv16; -- console data in |
1195,54 → 1156,6
); |
end component; |
|
component pdp11_sys70 is -- 11/70 system 1 core +rbus,debug,cache |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
RB_MREQ : in rb_mreq_type; -- rbus request (slave) |
RB_SRES : out rb_sres_type; -- rbus response |
RB_STAT : out slv4; -- rbus status flags |
RB_LAM_CPU : out slbit; -- rbus lam (cpu) |
GRESET : out slbit; -- general reset (from rbus) |
CRESET : out slbit; -- cpu reset (from cp) |
BRESET : out slbit; -- bus reset (from cp or cpu) |
CP_STAT : out cp_stat_type; -- console port status |
EI_PRI : in slv3; -- external interrupt priority |
EI_VECT : in slv9_2; -- external interrupt vector |
EI_ACKM : out slbit; -- external interrupt acknowledge |
ITIMER : out slbit; -- instruction timer |
IB_MREQ : out ib_mreq_type; -- ibus request (master) |
IB_SRES : in ib_sres_type; -- ibus response (from IO system) |
MEM_REQ : out slbit; -- memory: request |
MEM_WE : out slbit; -- memory: write enable |
MEM_BUSY : in slbit; -- memory: controller busy |
MEM_ACK_R : in slbit; -- memory: acknowledge read |
MEM_ADDR : out slv20; -- memory: address |
MEM_BE : out slv4; -- memory: byte enable |
MEM_DI : out slv32; -- memory: data in (memory view) |
MEM_DO : in slv32; -- memory: data out (memory view) |
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status - dpath |
); |
end component; |
|
component pdp11_hio70 is -- hio led and dsp for sys70 |
generic ( |
LWIDTH : positive := 8; -- led width |
DCWIDTH : positive := 2); -- digit counter width (2 or 3) |
port ( |
SEL_LED : in slbit; -- led select (0=stat;1=dr) |
SEL_DSP : in slv2; -- dsp select |
MEM_ACT_R : in slbit; -- memory active read |
MEM_ACT_W : in slbit; -- memory active write |
CP_STAT : in cp_stat_type; -- console port status |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status |
ABCLKDIV : in slv16; -- serport clock divider |
DISPREG : in slv16; -- display register |
LED : out slv(LWIDTH-1 downto 0); -- hio leds |
DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data |
); |
end component; |
|
-- ----- move later to pdp11_conf -------------------------------------------- |
|
constant conf_vect_pirq : integer := 8#240#; |
/rtl/w11a/pdp11_statleds.vhd
1,4 → 1,4
-- $Id: pdp11_statleds.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: pdp11_statleds.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
51,7 → 51,7
MEM_ACT_R : in slbit; -- memory active read |
MEM_ACT_W : in slbit; -- memory active write |
CP_STAT : in cp_stat_type; -- console port status |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status |
STATLEDS : out slv8 -- 8 bit CPU status |
); |
end pdp11_statleds; |
/rtl/w11a/pdp11_sys70.vhd
1,6 → 1,6
-- $Id: pdp11_sys70.vhd 677 2015-05-09 21:52:32Z mueller $ |
-- $Id: pdp11_sys70.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
13,24 → 13,19
-- |
------------------------------------------------------------------------------ |
-- Module Name: pdp11_sys70 - syn |
-- Description: pdp11: 11/70 system - single core +rbus,debug,cache |
-- Description: pdp11: 11/70 system registers |
-- |
-- Dependencies: w11a/pdp11_core_rbus |
-- w11a/pdp11_core |
-- w11a/pdp11_cache |
-- w11a/pdp11_mem70 |
-- ibus/ibd_ibmon |
-- ibus/ib_sres_or_3 |
-- w11a/pdp11_tmu_sb [sim only] |
-- |
-- Dependencies: - |
-- Test bench: tb/tb_pdp11_core (implicit) |
-- Target Devices: generic |
-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 |
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-09 677 1.1 start/stop/suspend overhaul; reset overhaul |
-- 2015-05-01 672 1.0 Initial version (extracted from sys_w11a_*) |
-- 2011-11-18 427 1.1.1 now numeric_std clean |
-- 2010-10-17 333 1.1 use ibus V2 interface |
-- 2008-08-22 161 1.0.1 use iblib |
-- 2008-04-20 137 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
38,7 → 33,6
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.rblib.all; |
use work.pdp11.all; |
use work.iblib.all; |
use work.sys_conf.all; |
45,198 → 39,92
|
-- ---------------------------------------------------------------------------- |
|
entity pdp11_sys70 is -- 11/70 system 1 core +rbus,debug,cache |
entity pdp11_sys70 is -- 11/70 memory system registers |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
RB_MREQ : in rb_mreq_type; -- rbus request (slave) |
RB_SRES : out rb_sres_type; -- rbus response |
RB_STAT : out slv4; -- rbus status flags |
RB_LAM_CPU : out slbit; -- rbus lam (cpu) |
GRESET : out slbit; -- general reset (from rbus) |
CRESET : out slbit; -- cpu reset (from cp) |
BRESET : out slbit; -- bus reset (from cp or cpu) |
CP_STAT : out cp_stat_type; -- console port status |
EI_PRI : in slv3; -- external interrupt priority |
EI_VECT : in slv9_2; -- external interrupt vector |
EI_ACKM : out slbit; -- external interrupt acknowledge |
ITIMER : out slbit; -- instruction timer |
IB_MREQ : out ib_mreq_type; -- ibus request (master) |
IB_SRES : in ib_sres_type; -- ibus response |
MEM_REQ : out slbit; -- memory: request |
MEM_WE : out slbit; -- memory: write enable |
MEM_BUSY : in slbit; -- memory: controller busy |
MEM_ACK_R : in slbit; -- memory: acknowledge read |
MEM_ADDR : out slv20; -- memory: address |
MEM_BE : out slv4; -- memory: byte enable |
MEM_DI : out slv32; -- memory: data in (memory view) |
MEM_DO : in slv32; -- memory: data out (memory view) |
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status - dpath |
CRESET : in slbit; -- console reset |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type -- ibus response |
); |
end pdp11_sys70; |
|
architecture syn of pdp11_sys70 is |
|
signal RB_SRES_CPU : rb_sres_type := rb_sres_init; |
constant ibaddr_mbrk : slv16 := slv(to_unsigned(8#177770#,16)); |
constant ibaddr_sysid : slv16 := slv(to_unsigned(8#177764#,16)); |
|
signal CP_CNTL : cp_cntl_type := cp_cntl_init; |
signal CP_ADDR : cp_addr_type := cp_addr_init; |
signal CP_DIN : slv16 := (others=>'0'); |
signal CP_STAT_L : cp_stat_type := cp_stat_init; |
signal CP_DOUT : slv16 := (others=>'0'); |
type regs_type is record -- state registers |
ibsel_mbrk : slbit; -- ibus select mbrk |
ibsel_sysid : slbit; -- ibus select sysid |
mbrk : slv8; -- status of mbrk register |
end record regs_type; |
|
signal EM_MREQ : em_mreq_type := em_mreq_init; |
signal EM_SRES : em_sres_type := em_sres_init; |
|
signal GRESET_L : slbit := '0'; |
signal CRESET_L : slbit := '0'; |
signal BRESET_L : slbit := '0'; |
constant regs_init : regs_type := ( |
'0','0', -- ibsel_* |
mbrk=>(others=>'0') -- mbrk |
); |
|
signal HM_ENA : slbit := '0'; |
signal MEM70_FMISS : slbit := '0'; |
signal CACHE_FMISS : slbit := '0'; |
signal CACHE_CHIT : slbit := '0'; |
signal R_REGS : regs_type := regs_init; |
signal N_REGS : regs_type := regs_init; |
|
signal DM_STAT_DP_L : dm_stat_dp_type := dm_stat_dp_init; |
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; |
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; |
signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; |
begin |
|
signal IB_MREQ_M : ib_mreq_type := ib_mreq_init; |
signal IB_SRES_M : ib_sres_type := ib_sres_init; |
signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init; |
signal IB_SRES_IBMON : ib_sres_type := ib_sres_init; |
proc_regs: process (CLK) |
begin |
if rising_edge(CLK) then |
if CRESET = '1' then |
R_REGS <= regs_init; |
else |
R_REGS <= N_REGS; |
end if; |
end if; |
end process proc_regs; |
|
constant rbaddr_ibus0 : slv16 := x"4000"; -- 4000/1000: 0100 xxxx xxxx xxxx |
constant rbaddr_core0 : slv16 := x"0000"; -- 0000/0020: 0000 0000 000x xxxx |
proc_next: process (R_REGS, IB_MREQ) |
variable r : regs_type := regs_init; |
variable n : regs_type := regs_init; |
variable idout : slv16 := (others=>'0'); |
variable ibreq : slbit := '0'; |
variable ibw0 : slbit := '0'; |
begin |
|
r := R_REGS; |
n := R_REGS; |
|
begin |
idout := (others=>'0'); |
ibreq := IB_MREQ.re or IB_MREQ.we; |
ibw0 := IB_MREQ.we and IB_MREQ.be0; |
|
RB2CP : pdp11_core_rbus |
generic map ( |
RB_ADDR_CORE => rbaddr_core0, |
RB_ADDR_IBUS => rbaddr_ibus0) |
port map ( |
CLK => CLK, |
RESET => RESET, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_CPU, |
RB_STAT => RB_STAT, |
RB_LAM => RB_LAM_CPU, |
GRESET => GRESET_L, |
CP_CNTL => CP_CNTL, |
CP_ADDR => CP_ADDR, |
CP_DIN => CP_DIN, |
CP_STAT => CP_STAT_L, |
CP_DOUT => CP_DOUT |
); |
-- ibus address decoder |
n.ibsel_mbrk := '0'; |
n.ibsel_sysid := '0'; |
if IB_MREQ.aval = '1' then |
if IB_MREQ.addr = ibaddr_mbrk(12 downto 1) then |
n.ibsel_mbrk := '1'; |
end if; |
if IB_MREQ.addr = ibaddr_sysid(12 downto 1) then |
n.ibsel_sysid := '1'; |
end if; |
end if; |
|
-- ibus transactions |
if r.ibsel_mbrk = '1' then |
idout(r.mbrk'range) := r.mbrk; |
end if; |
if r.ibsel_sysid = '1' then |
idout := slv(to_unsigned(8#123456#,16)); |
end if; |
|
W11A : pdp11_core |
port map ( |
CLK => CLK, |
RESET => GRESET_L, |
CP_CNTL => CP_CNTL, |
CP_ADDR => CP_ADDR, |
CP_DIN => CP_DIN, |
CP_STAT => CP_STAT_L, |
CP_DOUT => CP_DOUT, |
ESUSP_O => open, |
ESUSP_I => '0', |
ITIMER => ITIMER, |
EBREAK => '0', |
DBREAK => '0', |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
EI_ACKM => EI_ACKM, |
EM_MREQ => EM_MREQ, |
EM_SRES => EM_SRES, |
CRESET => CRESET_L, |
BRESET => BRESET_L, |
IB_MREQ_M => IB_MREQ_M, |
IB_SRES_M => IB_SRES_M, |
DM_STAT_DP => DM_STAT_DP_L, |
DM_STAT_VM => DM_STAT_VM, |
DM_STAT_CO => DM_STAT_CO |
); |
if r.ibsel_mbrk='1' and ibw0='1' then |
n.mbrk := IB_MREQ.din(n.mbrk'range); |
end if; |
|
CACHE: pdp11_cache |
port map ( |
CLK => CLK, |
GRESET => GRESET_L, |
EM_MREQ => EM_MREQ, |
EM_SRES => EM_SRES, |
FMISS => CACHE_FMISS, |
CHIT => CACHE_CHIT, |
MEM_REQ => MEM_REQ, |
MEM_WE => MEM_WE, |
MEM_BUSY => MEM_BUSY, |
MEM_ACK_R => MEM_ACK_R, |
MEM_ADDR => MEM_ADDR, |
MEM_BE => MEM_BE, |
MEM_DI => MEM_DI, |
MEM_DO => MEM_DO |
); |
N_REGS <= n; |
|
MEM70: pdp11_mem70 |
port map ( |
CLK => CLK, |
CRESET => BRESET_L, |
HM_ENA => HM_ENA, |
HM_VAL => CACHE_CHIT, |
CACHE_FMISS => MEM70_FMISS, |
IB_MREQ => IB_MREQ_M, |
IB_SRES => IB_SRES_MEM70 |
); |
IB_SRES.dout <= idout; |
IB_SRES.ack <= (r.ibsel_mbrk or r.ibsel_sysid) and ibreq; |
IB_SRES.busy <= '0'; |
|
HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; |
CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; |
|
IBMON : if sys_conf_ibmon_awidth > 0 generate |
begin |
I0 : ibd_ibmon |
generic map ( |
IB_ADDR => slv(to_unsigned(8#160000#,16)), |
AWIDTH => sys_conf_ibmon_awidth) |
port map ( |
CLK => CLK, |
RESET => RESET, |
IB_MREQ => IB_MREQ_M, |
IB_SRES => IB_SRES_IBMON, |
IB_SRES_SUM => DM_STAT_VM.ibsres |
); |
end generate IBMON; |
|
IB_SRES_OR : ib_sres_or_3 |
port map ( |
IB_SRES_1 => IB_SRES_MEM70, |
IB_SRES_2 => IB_SRES, |
IB_SRES_3 => IB_SRES_IBMON, |
IB_SRES_OR => IB_SRES_M |
); |
|
RB_SRES <= RB_SRES_CPU; -- currently single rbus device |
IB_MREQ <= IB_MREQ_M; -- setup output signals |
GRESET <= GRESET_L; |
CRESET <= CRESET_L; |
BRESET <= BRESET_L; |
CP_STAT <= CP_STAT_L; |
DM_STAT_DP <= DM_STAT_DP_L; |
|
-- synthesis translate_off |
DM_STAT_SY.emmreq <= EM_MREQ; |
DM_STAT_SY.emsres <= EM_SRES; |
DM_STAT_SY.chit <= CACHE_CHIT; |
|
TMU : pdp11_tmu_sb |
generic map ( |
ENAPIN => 13) |
port map ( |
CLK => CLK, |
DM_STAT_DP => DM_STAT_DP_L, |
DM_STAT_VM => DM_STAT_VM, |
DM_STAT_CO => DM_STAT_CO, |
DM_STAT_SY => DM_STAT_SY |
); |
-- synthesis translate_on |
|
end process proc_next; |
|
end syn; |
/rtl/w11a/pdp11_sys70.vbom
1,16 → 1,8
# libs |
../vlib/slvtypes.vhd |
../vlib/rbus/rblib.vhd |
../ibus/iblib.vhd |
pdp11.vbom |
${sys_conf := sys_conf.vhd} |
# components |
pdp11_core_rbus.vbom |
pdp11_core.vbom |
pdp11_cache.vbom |
pdp11_mem70.vbom |
../ibus/ibd_ibmon.vbom |
../ibus/ib_sres_or_3.vbom |
[sim]pdp11_tmu_sb.vbom |
# design |
pdp11_sys70.vhd |
/rtl/w11a/pdp11_core.vbom
8,7 → 8,7
pdp11_decode.vbom |
pdp11_sequencer.vbom |
pdp11_irq.vbom |
pdp11_reg70.vbom |
pdp11_sys70.vbom |
../ibus/ib_sres_or_4.vbom |
# design |
pdp11_core.vhd |
/rtl/vlib/rlink/rlink_sp1c.vhd
1,6 → 1,6
-- $Id: rlink_sp1c.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: rlink_sp1c.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
17,8 → 17,6
-- |
-- Dependencies: rlink_core8 |
-- serport/serport_1clock |
-- rbus/rbd_rbmon |
-- rbus/rb_sres_or_2 |
-- |
-- Test bench: - |
-- |
27,13 → 25,10
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa |
-- 2015-05-02 672 14.7 131013 xc6slx16-2 495 671 56 255 s 8.8 - - |
-- 2011-12-09 437 13.1 O40d xc3s1000-4 337 733 64 469 s 9.8 - - |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-02 672 4.2 add rbd_rbmon (optional via generics) |
-- 2015-04-11 666 4.1 rename ENAESC->ESCFILL, rearrange XON handling |
-- 2014-08-28 588 4.0 use rlink v4 iface, 4 bit STAT |
-- 2011-12-09 437 1.0 Initial version |
------------------------------------------------------------------------------ |
44,7 → 39,6
|
use work.slvtypes.all; |
use work.rblib.all; |
use work.rbdlib.all; |
use work.rlinklib.all; |
use work.serportlib.all; |
|
59,9 → 53,7
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none) |
ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none) |
CDWIDTH : positive := 13; -- clk divider width |
CDINIT : natural := 15; -- clk divider initial/reset setting |
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none) |
RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr |
CDINIT : natural := 15); -- clk divider initial/reset setting |
port ( |
CLK : in slbit; -- clock |
CE_USEC : in slbit; -- 1 usec clock enable |
69,7 → 61,7
CE_INT : in slbit := '0'; -- rri ato time unit clock enable |
RESET : in slbit; -- reset |
ENAXON : in slbit; -- enable xon/xoff handling |
ESCFILL : in slbit; -- enable fill escaping |
ENAESC : in slbit; -- enable xon/xoff escaping |
RXSD : in slbit; -- receive serial data (board view) |
TXSD : out slbit; -- transmit serial data (board view) |
CTS_N : in slbit := '0'; -- clear to send (act.low, board view) |
93,13 → 85,9
signal RLB_VAL : slbit := '0'; |
signal RLB_HOLD : slbit := '0'; |
|
signal RB_MREQ_M : rb_mreq_type := rb_mreq_init; |
signal RB_SRES_M : rb_sres_type := rb_sres_init; |
signal RB_SRES_RBMON : rb_sres_type := rb_sres_init; |
|
begin |
|
CORE : rlink_core8 -- rlink master ---------------------- |
CORE : rlink_core8 |
generic map ( |
BTOWIDTH => BTOWIDTH, |
RTAWIDTH => RTAWIDTH, |
111,8 → 99,6
CLK => CLK, |
CE_INT => CE_INT, |
RESET => RESET, |
ESCXON => ENAXON, |
ESCFILL => ESCFILL, |
RLB_DI => RLB_DI, |
RLB_ENA => RLB_ENA, |
RLB_BUSY => RLB_BUSY, |
120,13 → 106,13
RLB_VAL => RLB_VAL, |
RLB_HOLD => RLB_HOLD, |
RL_MONI => RL_MONI, |
RB_MREQ => RB_MREQ_M, |
RB_SRES => RB_SRES_M, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES, |
RB_LAM => RB_LAM, |
RB_STAT => RB_STAT |
); |
|
SERPORT : serport_1clock -- serport interface ----------------- |
SERPORT : serport_1clock |
generic map ( |
CDWIDTH => CDWIDTH, |
CDINIT => CDINIT, |
137,7 → 123,7
CE_MSEC => CE_MSEC, |
RESET => RESET, |
ENAXON => ENAXON, |
ENAESC => '0', -- escaping now in rlink_core8 |
ENAESC => ENAESC, |
RXDATA => RLB_DI, |
RXVAL => RLB_ENA, |
RXHOLD => RLB_BUSY, |
151,28 → 137,4
TXCTS_N => CTS_N |
); |
|
RBMON : if RBMON_AWIDTH > 0 generate -- rbus monitor -------------- |
begin |
I0 : rbd_rbmon |
generic map ( |
RB_ADDR => RBMON_RBADDR, |
AWIDTH => RBMON_AWIDTH) |
port map ( |
CLK => CLK, |
RESET => RESET, |
RB_MREQ => RB_MREQ_M, |
RB_SRES => RB_SRES_RBMON, |
RB_SRES_SUM => RB_SRES_M |
); |
end generate RBMON; |
|
RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- |
port map ( |
RB_SRES_1 => RB_SRES, |
RB_SRES_2 => RB_SRES_RBMON, |
RB_SRES_OR => RB_SRES_M |
); |
|
RB_MREQ <= RB_MREQ_M; -- setup output signals |
|
end syn; |
/rtl/vlib/rlink/rlinklib.vhd
1,4 → 1,4
-- $Id: rlinklib.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: rlinklib.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
20,10 → 20,7
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- |
-- 2015-04-11 666 4.1.2 rlink_core8: add ESC(XON|FILL); |
-- rlink_sp1c: rename ENAESC->ESCFILL |
-- 2015-02-21 649 4.1.1 add ioleds_sp1c |
-- 2014-02-21 649 4.1.1 add ioleds_sp1c |
-- 2014-12-21 617 4.1 use stat(2) to signal rbus timeout |
-- 2014-10-12 596 4.0 now rlink v4.0 iface, 4 bit STAT |
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit |
174,8 → 171,6
CLK : in slbit; -- clock |
CE_INT : in slbit := '0'; -- rlink ato time unit clock enable |
RESET : in slbit; -- reset |
ESCXON : in slbit := '0'; -- enable xon/xoff escaping |
ESCFILL : in slbit := '0'; -- enable fill escaping |
RLB_DI : in slv8; -- rlink 8b: data in |
RLB_ENA : in slbit; -- rlink 8b: data enable |
RLB_BUSY : out slbit; -- rlink 8b: data busy |
229,9 → 224,7
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none) |
ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none) |
CDWIDTH : positive := 13; -- clk divider width |
CDINIT : natural := 15; -- clk divider initial/reset setting |
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none) |
RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr |
CDINIT : natural := 15); -- clk divider initial/reset setting |
port ( |
CLK : in slbit; -- clock |
CE_USEC : in slbit; -- 1 usec clock enable |
238,8 → 231,8
CE_MSEC : in slbit; -- 1 msec clock enable |
CE_INT : in slbit := '0'; -- rri ato time unit clock enable |
RESET : in slbit; -- reset |
ENAXON : in slbit := '0'; -- enable xon/xoff handling |
ESCFILL : in slbit := '0'; -- enable fill escaping |
ENAXON : in slbit; -- enable xon/xoff handling |
ENAESC : in slbit; -- enable xon/xoff escaping |
RXSD : in slbit; -- receive serial data (board view) |
TXSD : out slbit; -- transmit serial data (board view) |
CTS_N : in slbit := '0'; -- clear to send (act.low, board view) |
/rtl/vlib/rlink/rlink_core8.vhd
1,4 → 1,4
-- $Id: rlink_core8.vhd 666 2015-04-12 21:17:54Z mueller $ |
-- $Id: rlink_core8.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
32,7 → 32,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-11 666 4.1 add ESCXON,ESCFILL in signals, for cdata2byte |
-- 2014-10-12 596 4.0 now rlink v4 iface, 4 bit STAT |
-- 2011-12-09 437 1.0 Initial version |
------------------------------------------------------------------------------ |
58,8 → 57,6
CLK : in slbit; -- clock |
CE_INT : in slbit := '0'; -- rlink ato time unit clock enable |
RESET : in slbit; -- reset |
ESCXON : in slbit; -- enable xon/xoff escaping |
ESCFILL : in slbit; -- enable fill escaping |
RLB_DI : in slv8; -- rlink 8b: data in |
RLB_ENA : in slbit; -- rlink 8b: data enable |
RLB_BUSY : out slbit; -- rlink 8b: data busy |
132,8 → 129,8
port map ( |
CLK => CLK, |
RESET => RESET, |
ESCXON => ESCXON, |
ESCFILL => ESCFILL, |
ESCXON => '0', |
ESCFILL => '0', |
DI => RL_DO, |
ENA => RL_VAL, |
BUSY => RL_HOLD, |
/rtl/vlib/rlink/tb/tbu_rlink_sp1c.vhd
1,6 → 1,6
-- $Id: tbu_rlink_sp1c.vhd 666 2015-04-12 21:17:54Z mueller $ |
-- $Id: tbu_rlink_sp1c.vhd 593 2014-09-14 22:21:33Z mueller $ |
-- |
-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
36,7 → 36,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-11 666 4.1 rename ENAESC->ESCFILL |
-- 2014-08-31 590 4.0 now full rlink v4 iface, 4 bit STAT |
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit |
-- 2011-12-22 442 3.2 renamed and retargeted to test rlink_sp1c |
139,7 → 138,7
CE_INT => CE_INT, |
RESET => RESET, |
ENAXON => '0', |
ESCFILL => '0', |
ENAESC => '0', |
RXSD => RXSD, |
TXSD => TXSD, |
CTS_N => CTS_N, |
/rtl/vlib/rlink/rlink_sp1c.vbom
1,13 → 1,10
# libs |
../slvtypes.vhd |
../rbus/rblib.vhd |
../rbus/rbdlib.vhd |
rlinklib.vbom |
../serport/serportlib.vbom |
# components |
rlink_core8.vbom |
../serport/serport_1clock.vbom |
../rbus/rbd_rbmon.vbom |
../rbus/rb_sres_or_2.vbom |
# design |
rlink_sp1c.vhd |
/rtl/vlib/rbus/rbd_rbmon.vhd
1,6 → 1,6
-- $Id: rbd_rbmon.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: rbd_rbmon.vhd 620 2014-12-25 10:48:35Z mueller $ |
-- |
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2010-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
30,7 → 30,6
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-02 672 5.0.1 use natural for AWIDTH to work around a ghdl issue |
-- 2014-12-22 619 5.0 reorganized, supports now 16 bit addresses |
-- 2014-09-13 593 4.1 change default address -> ffe8 |
-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit (but only 8 bit recorded) |
46,10 → 45,9
-- 01 stop r/w/f writing 1 stops moni |
-- 00 start r/w/f writing 1 starts moni and clears addr |
-- 001 stat r/w/- Status register |
-- 15:13 bsize r/-/- buffer size (AWIDTH-9) |
-- 00 wrap r/-/- line address wrapped (cleared on go) |
-- 010 hilim r/w/- upper address limit, inclusive (def: 0xfffb) |
-- 011 lolim r/w/- lower address limit, inclusive (def: 0x0000) |
-- 010 hilim r/w/- upper address limit (def: 0xfffb) |
-- 011 lolim r/w/- lower address limit (def: 0x0000) |
-- 100 addr r/w/- Address register |
-- *:02 laddr r/w/- line address |
-- 01:00 waddr r/w/- word address |
80,14 → 78,10
use work.memlib.all; |
use work.rblib.all; |
|
-- Note: AWIDTH has type natural to allow AWIDTH=0 can be used in if generates |
-- to control the instantiation. ghdl checks even for not instantiated |
-- entities the validity of generics, that's why natural needed here .... |
|
entity rbd_rbmon is -- rbus dev: rbus monitor |
generic ( |
RB_ADDR : slv16 := slv(to_unsigned(16#ffe8#,16)); |
AWIDTH : natural := 9); |
AWIDTH : positive := 9); |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
/rtl/vlib/rbus/rbdlib.vhd
1,4 → 1,4
-- $Id: rbdlib.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: rbdlib.vhd 620 2014-12-25 10:48:35Z mueller $ |
-- |
-- Copyright 2010-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
63,7 → 63,7
component rbd_rbmon is -- rbus dev: rbus monitor |
generic ( |
RB_ADDR : slv16 := rbaddr_rbmon; |
AWIDTH : natural := 9); |
AWIDTH : positive := 9); |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
/rtl/vlib/serport/serport_master.vhd
File deleted
/rtl/vlib/serport/serport_master.vbom
File deleted
/rtl/vlib/serport/serport_uart_rxtx_ab.vhd
1,4 → 1,4
-- $Id: serport_uart_rxtx_ab.vhd 666 2015-04-12 21:17:54Z mueller $ |
-- $Id: serport_uart_rxtx_ab.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
23,7 → 23,6
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2015-04-12 666 14.7 131013 xc6slx16-2 100 142 0 48 s 6.2 |
-- 2010-12-25 348 12.1 M53d xc3s1000-4 99 197 - 124 s 9.8 |
-- |
-- Revision History: |
/rtl/vlib/serport/serportlib.vhd
1,4 → 1,4
-- $Id: serportlib.vhd 666 2015-04-12 21:17:54Z mueller $ |
-- $Id: serportlib.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
20,11 → 20,10
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-11 666 1.3.1 add serport_master |
-- 2015-02-01 641 1.3 add CLKDIV_F for autobaud |
-- 2015-02-01 641 1.3 add CLKDIV_F for autobaud; |
-- 2013-01-26 476 1.2.6 renamed package to serportlib |
-- 2011-12-09 437 1.2.5 rename stat->moni port |
-- 2011-10-23 419 1.2.4 remove serport_clkdiv_ consts |
-- 2011-10-23 419 1.2.4 remove serport_clkdiv_ consts; |
-- 2011-10-22 417 1.2.3 add serport_xon(rx|tx) defs |
-- 2011-10-14 416 1.2.2 add c_serport defs |
-- 2010-12-26 348 1.2.1 add ABCLKDIV to serport_uart_rxtx_ab |
240,27 → 239,4
); |
end component; |
|
component serport_master is -- serial port module, master side |
generic ( |
CDWIDTH : positive := 13); -- clk divider width |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting |
ENAXON : in slbit := '0'; -- enable xon/xoff handling |
ENAESC : in slbit := '0'; -- enable xon/xoff escaping |
RXDATA : out slv8; -- receiver data out |
RXVAL : out slbit; -- receiver data valid |
RXERR : out slbit; -- receiver data error (frame error) |
RXOK : in slbit := '1'; -- rx channel ok |
TXDATA : in slv8; -- transmit data in |
TXENA : in slbit; -- transmit data enable |
TXBUSY : out slbit; -- transmit busy |
RXSD : in slbit; -- receive serial data (uart view) |
TXSD : out slbit; -- transmit serial data (uart view) |
RXRTS_N : out slbit; -- receive rts (uart view, act.low) |
TXCTS_N : in slbit :='0' -- transmit cts (uart view, act.low) |
); |
end component; |
|
end package serportlib; |
/rtl/vlib/serport/serport_1clock.vhd
1,4 → 1,4
-- $Id: serport_1clock.vhd 666 2015-04-12 21:17:54Z mueller $ |
-- $Id: serport_1clock.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
25,12 → 25,10
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2015-04-12 666 14.7 131013 xc6slx16-2 171 239 32 94 s 6.3 |
-- 2011-11-13 424 13.1 O40d xc3s1000-4 157 337 64 232 s 9.9 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-11 666 1.1.1 add sim assertions for RXOVR and RXERR |
-- 2015-02-01 641 1.1 add CLKDIV_F for autobaud; |
-- 2011-12-10 438 1.0.2 internal reset on abact |
-- 2011-12-09 437 1.0.1 rename stat->moni port |
253,22 → 251,4
MONI.abclkdiv_f <= ABCLKDIV_F; |
end process proc_abclkdiv; |
|
-- synthesis translate_off |
|
proc_check: process (CLK) |
begin |
if rising_edge(CLK) then |
assert RXOVR = '0' |
report "serport_1clock-W: RXOVR = " & slbit'image(RXOVR) & |
"; data loss in receive fifo" |
severity warning; |
assert RXERR = '0' |
report "serport_1clock-W: RXERR = " & slbit'image(RXERR) & |
"; spurious receive error" |
severity warning; |
end if; |
end process proc_check; |
|
-- synthesis translate_on |
|
end syn; |
/rtl/vlib/serport/serport_2clock.vhd
1,4 → 1,4
-- $Id: serport_2clock.vhd 666 2015-04-12 21:17:54Z mueller $ |
-- $Id: serport_2clock.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
26,12 → 26,10
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2015-04-12 666 14.7 131013 xc6slx16-2 285 283 32 138 s 6.2/5.9 |
-- 2011-11-13 424 13.1 O40d xc3s1000-4 224 362 64 295 s 8.6/10.1 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-04-11 666 1.1.1 add sim assertions for RXOVR and RXERR |
-- 2015-02-01 641 1.1 add CLKDIV_F for autobaud; |
-- 2011-12-10 438 1.0.2 internal reset on abact |
-- 2011-12-09 437 1.0.1 rename stat->moni port |
384,19 → 382,5
MONI.abclkdiv <= (others=>'0'); |
MONI.abclkdiv(R_SYNU.abclkdiv_s'range) <= R_SYNU.abclkdiv_s; |
end process proc_abclkdiv; |
|
-- synthesis translate_off |
|
proc_check: process (CLKS) |
begin |
assert RXOVR = '0' |
report "serport_2clock-W: RXOVR = '1'; data loss in receive fifo" |
severity warning; |
assert RXERR = '0' |
report "serport_2clock-W: RXERR = '1'; spurious receive error" |
severity warning; |
end process proc_check; |
|
-- synthesis translate_on |
|
end syn; |
/rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd
1,4 → 1,4
-- $Id: s7_cmt_sfs_gsim.vhd 675 2015-05-08 21:05:08Z mueller $ |
-- $Id: s7_cmt_sfs_gsim.vhd 554 2014-04-21 14:01:51Z mueller $ |
-- |
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
19,7 → 19,7
-- Dependencies: - |
-- Test bench: - |
-- Target Devices: generic Series-7 |
-- Tool versions: xst 14.5; viv 2014.4; ghdl 0.29 |
-- Tool versions: xst 14.5; viv 2014.1; ghdl 0.29 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
/rtl/make_ise/generic_xflow.mk
1,4 → 1,4
# $Id: generic_xflow.mk 672 2015-05-02 21:58:28Z mueller $ |
# $Id: generic_xflow.mk 646 2015-02-15 12:04:55Z mueller $ |
# |
# Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
5,7 → 5,6
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-05-02 672 1.11 ucf_cpp handling: remove -C (gcc 4.8 stdc-predef.h) |
# 2015-02-06 643 1.10 use make_ise; rename xise_msg_filter <- isemsg_filter |
# drop --ise_path from vbomconv; |
# 2013-10-12 539 1.9 use xtwi; support trce tsi file; use -C for cpp |
301,12 → 300,12
# generate cpp'ed ucf files from ucf_cpp |
# |
%.ucf : %.ucf_cpp |
cpp -I${RETROBASE}/rtl $*.ucf_cpp $*.ucf |
cpp -C -I${RETROBASE}/rtl $*.ucf_cpp $*.ucf |
# |
# generate nested dependency rules for cpp'ed ucf files from ucf_cpp |
# |
%.dep_ucf_cpp : %.ucf_cpp |
cpp -I${RETROBASE}/rtl -MM $*.ucf_cpp |\ |
cpp -C -I${RETROBASE}/rtl -MM $*.ucf_cpp |\ |
sed 's/\.o:/\.ucf:/' > $*.dep_ucf_cpp |
# |
# Cleanup |
/rtl/make_ise/syn_s3_speed.opt
1,6 → 1,6
FLOWTYPE = FPGA_SYNTHESIS; |
# |
# $Id: syn_s3_speed.opt 672 2015-05-02 21:58:28Z mueller $ |
# $Id: syn_s3_speed.opt 540 2013-10-13 18:42:50Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
33,13 → 33,8
"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED |
"-opt_level 2"; # Optimization Effort Criteria: 2=High |
## "-shreg_min_size 3"; # not available for Spartan-3 !! |
"-shreg_extract NO"; # --> switch shreg extraction off instead |
"-shreg_extract NO"; # --> switch shreg extrtaction off instead |
"-uc <design>.xcf"; # Constraint File name |
## Note: |
## "-use_new_parser yes"; |
## solves some nasty 'INTERNAL_ERROR:Xst:cmain.c:3464:1.56' problems, but |
## leads to other problems later on (un-routable designs ect). |
## Therefore currently not used. |
# |
# The following are HDL Options |
# |
/doc/README_known_issues.txt
File deleted
/doc/FILES.txt
46,7 → 46,6
rtl/w11a - w11a core |
tools helper programs |
tools/asm-11 - pdp-11 assembler code |
tools/asm-11/lib - definitions and macros for asm-11 |
tools/asm-11/tests - test bench for asm-11 |
tools/asm-11/tests-err - test bench for asm-11 (error check part) |
tools/bin - scripts and binaries |
/doc/w11a_tb_guide.txt
1,4 → 1,4
# $Id: w11a_tb_guide.txt 660 2015-03-29 22:10:16Z mueller $ |
# $Id: w11a_tb_guide.txt 654 2015-03-01 18:45:38Z mueller $ |
|
Note: Only ISE based test benches are currently documented ! |
The Vivado test environemnt is still in it's infancy ! |
258,7 → 258,7
- sys_w11a_n2 test bench |
|
cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb |
tbrun_tbwrri --lsuf tbench_dsim --pack rw11 --cuff tb_w11a_n2 \ |
tbrun_tbwrri --lsuf tbench_dsim --pack rw11 --cuff tb_w11a_n2 \ |
"rw11::setup_cpu" "rw11::tbench @w11a_all.dat" |
-> 2638820.0 ns 131930: DONE |
-> real 0m24.890s user 0m25.286s sys 0m0.439s |
/doc/w11a_os_guide.txt
1,4 → 1,4
# $Id: w11a_os_guide.txt 680 2015-05-14 13:29:46Z mueller $ |
# $Id: w11a_os_guide.txt 654 2015-03-01 18:45:38Z mueller $ |
|
Guide to run operating system images on w11a systems |
|
202,14 → 202,12
|
can be freely distributed and used for non-commercial purposes. |
|
Several oskits are provided: |
Two oskits are currently provided: |
|
- unix-v5_rk: Unix V5 System on RK05 |
- 211bsd_rk: 2.11BSD system on RK05 |
- 211bsd_rl: 2.11BSD system on RL02 |
|
- 211bsd_rk: 2.11BSD system on RK05 (very elementary subset) |
- 211bsd_rl: 2.11BSD system on RL02 (small subset) |
- 211bsd_rp: 2.11BSD system on RP06 (full system) |
|
For further details consult the README_<oskit-name>set.txt file in the |
oskit directory. |
|
242,17 → 240,13
out the W11A and let the author know whether is works as it should. |
For convenience the boot scripts are also included ( <kit>.tcl ). |
|
Several oskits are provided: |
Several osskits are currently provided |
|
- rsx11m-31_rk: RSX-11M V3.1 on RK05 |
- rsx11m-40_rk: RSX-11M V4.0 on RK05 |
- rsx11m-31_rk: RSX-11M V3.1 on RK05 |
- rsx11m-40_rk: RSX-11M V4.0 on RK05 |
- rt11-40_rk: RT-11 V4.0 on RK05 |
- rt11-53_rl: RT-11 V5.3 on RL02 |
- xxdp_rl: XXDP 22 and 25 on RL02 |
|
- rsx11mp-30_rp: RSX-11M+ V3.0 on RP06 |
|
- rt11-40_rk: RT-11 V4.0 on RK05 |
- rt11-53_rl: RT-11 V5.3 on RL02 |
|
- xxdp_rl: XXDP 22 and 25 on RL02 |
|
For further details consult the README_<oskit-name>set.txt file in the |
oskit directory. |
/doc/man/man1/ti_rri.1
1,11 → 1,11
.\" -*- nroff -*- |
.\" $Id: ti_rri.1 666 2015-04-12 21:17:54Z mueller $ |
.\" $Id: ti_rri.1 653 2015-03-01 12:53:01Z mueller $ |
.\" |
.\" Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
.\" |
.\" ------------------------------------------------------------------ |
. |
.TH TI_RRI 1 2015-04-12 "Retro Project" "Retro Project Manual" |
.TH TI_RRI 1 2015-01-28 "Retro Project" "Retro Project Manual" |
.\" ------------------------------------------------------------------ |
.SH NAME |
ti_rri \- \fBRlink\fP Backend Server |
76,15 → 76,12
Two fifo's are generated, one with a '_tx' and one with a '_tx' appended |
to the name prefix. |
.IP \fBopts\fP |
comma separated list of further fifo port options: |
comma separated list of further options for the fifo port: |
.RS |
.PD 0 |
.IP \fBkeep\fP |
.TP |
.B keep |
fifo is kept open on exit |
.IP \fBxon\fP |
software flow control (xon/xoff) |
.IP \fBnoinit\fP |
defer link initialization (debug or test benches) |
.PD |
.RE |
.RE |
113,7 → 110,7
.PD |
.RE |
.IP \fBopts\fP |
comma separated list of further term port options: |
comma separated list of further options for the serial port connection: |
.RS |
.PD 0 |
.IP \fBbreak\fP |
122,8 → 119,6
hardware flow control (cts/rts) |
.IP \fBxon\fP |
software flow control (xon/xoff) |
.IP \fBnoinit\fP |
defer link initialization (debug or test benches) |
.PD |
.RE |
.RE |
136,13 → 131,11
USB path, default derived from environment variables RETRO_FX2_VID and |
RETRO_FX2_PID. |
.IP \fBopts\fP |
comma separated list of further cuff port options: |
comma separated list of further options for the fifo port: |
.RS |
.PD 0 |
.IP \fBtrace\fP |
trace USB activities |
.IP \fBnoinit\fP |
defer link initialization (debug or test benches) |
.PD |
.RE |
.RE |
/doc/man/man1/ti_w11.1
1,11 → 1,11
.\" -*- nroff -*- |
.\" $Id: ti_w11.1 680 2015-05-14 13:29:46Z mueller $ |
.\" $Id: ti_w11.1 654 2015-03-01 18:45:38Z mueller $ |
.\" |
.\" Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
.\" |
.\" ------------------------------------------------------------------ |
. |
.TH TI_W11 1 2015-04-12 "Retro Project" "Retro Project Manual" |
.TH TI_W11 1 2015-02-22 "Retro Project" "Retro Project Manual" |
.\" ------------------------------------------------------------------ |
.SH NAME |
ti_w11 \- Quick starter for \fBti_rri\fP with \fBw11\fP CPU designs |
51,36 → 51,16
.SS "setup options for ghdl simulation runs" |
.PD 0 |
.IP \fB-b3\fP |
start \fItb_w11a_b3\fP simulation (w11a on Basys3, default \fB-f1x\fP) |
start \fItb_w11a_b3\fP simulation (w11a on Basys3 board) |
.IP \fB-n4\fP |
start \fItb_w11a_n4\fP simulation (w11a on Nexys4) |
start \fItb_w11a_n4\fP simulation (w11a on Nexys4 board) |
.IP \fB-n3\fP |
start \fItb_w11a_n3\fP simulation (w11a on Nexys3, default \fB-fc\fP) |
start \fItb_w11a_n3\fP simulation (w11a on Nexys3 board) |
.IP \fB-n2\fP |
start \fItb_w11a_n2\fP simulation (w11a on Nexys2, default \fB-fc\fP) |
start \fItb_w11a_n2\fP simulation (w11a on Nexys2 board) |
.IP \fB-s3\fP |
start \fItb_w11a_s3\fP simulation (w11a on S3board, default \fB-f2\fP) |
start \fItb_w11a_s3\fP simulation (w11a on S3board) |
.PD |
.IP \fB-f\fIm\fR |
select communication mode for simulation. The \fB-f\fIm\fR can be used after |
the \fB-b3\fP,...,\fB-s3\fP options to overwrite the default. Valid values |
for mode \fIm\fP are |
.RS |
.PD 0 |
.IP \fBc\fP 4 |
use Cypress FX2 data path (cuff, only for -n2 and -n3) |
.IP \fB1\fP 4 |
use 1st serport |
.IP \fB1x\fP 4 |
use 1st serport with xon |
.IP \fB2\fP 4 |
use 2nd serport (fusp, only for -s3,-n2,-n3) |
.IP \fB2x\fP 4 |
use 2nd serport with xon |
.PD |
.RE |
.IP \fB-tmu\fP |
activate trace and monitoring unit |
. |
.SS "common options" |
.IP \fB-e "\fR=\fIfile"\fR |
/doc/README.txt
1,4 → 1,4
$Id: README.txt 680 2015-05-14 13:29:46Z mueller $ |
$Id: README.txt 655 2015-03-04 20:35:21Z mueller $ |
|
Release notes for w11a |
|
13,7 → 13,6
in the doc directory, specifically |
|
* README.txt: release notes |
* README_known_issues.txt: known issues |
* INSTALL.txt: installation and building test benches and systems |
* FILES.txt: short description of the directory layout, what is where ? |
* w11a_tb_guide.txt: running test benches |
22,127 → 21,6
|
2. Change Log ---------------------------------------------------------------- |
|
- trunk (2015-05-14: svn rev 30(oc) 681(wfjm); untagged w11a_V0.65) +++++++++ |
- Preface |
|
- With small RK05 or RL02 sized disks only quite reduced OS setups could |
be booted, full featured systems were beyond reach. Now finally large |
disks are available, with a RH70 + RP/RM disk controller emulation. It |
supports up to four disks and allows now to run full featured 211bsd |
or rsx-11mplus systems. |
|
- to track down issues with ibus devices a 'ibus monitor' was added, it can |
record in the default setup up to 511 ibus transactions. An address filter |
allows to select accesses of one device. The ibd_ibmon tcl package |
contains the appropriate support scripts. |
|
- several cleanups |
- factor out common blocks on sys_w11a_* systems: the core+rbus+cache |
logic of single cpu systems now contained in pdp11_sys70, and the |
human I/O for digilent boards now in pdp11_hio70. |
- cpu start/stop logic cleanup: new command set with simple commands. |
Add also a new suspend/resume mechanism, which allows to hold the cpu |
without leaving the 'run state'. While suspended all timers are frozen. |
Very helpful when debugging, will be the basis for a hardware break |
point logic in a later release. |
- xon/xoff consolidation: escaping now done in cdata2byte/byte2cdata in |
FPGA and in RlinkPacketBufSnd/RlinkPacketBufRcv in backend. The extra |
escaping level in serport_xonrx/serport_xontx isn't used anymore, the |
special code in RlinkPortTerm has been removed. This allows to use |
xon/xoff flow control also in simulation links via RlinkPortFifo. |
- status check cleanup: it is very helpful to have a default status check |
and an easy way to modify it cases where some error flags are expected |
(e.g. on device polls). In the old logic status and data checks were |
done via RlinkCommandExpect. The new logic reflects that status checks |
are the normal case, and store the status check pattern in RlinkCommand. |
The meaning of expect masks for status and data is inverted, now a '1' |
means that the bit is checked (before it meant the bit is ignored). |
The default status check pattern is still in RlinkContext, but will be |
copied to RlinkCommand when the list is processed. RlinkCommandExpect |
handles now only data checks. |
|
- and bug fixes |
- rk11 cleanup: since the first days 211bsd autoconfig printed |
rk ? csr 177400 vector 220 didn't interrupt |
for boots from a RK11 it didn't have consequences, but when booted from |
a RL,RP, or RM disk this prevents that the RK11 disks are configured. |
Was caused by a missing interrupt after device reset. Now fixed. |
|
- Summary |
- added RH70/RP/RM big disk support |
- many cleanups |
|
- New features |
- new directory trees for |
- tools/asm-11/lib - definitions and macros for asm-11 |
- new modules |
- rtl/vlib/serport |
- serport_master - serial port module, master side |
- rtl/ibus/ibd_ibmon - ibus monitor |
- rtl/w11a/pdp11_sys70 - 11/70 system - single core +rbus,debug,cache |
- rtl/w11a/pdp11_hio70 - hio led and dsp for sys70 |
- tools/src/librw11 |
- Rw11(Cntl|Unit)RHRP - Controller/Unit for RHRP |
- tools/tbench |
- test_rhrp_* - test tbench for RHRP |
- new oskits |
- tools/oskit/211bsd_rp - new oskit for 2.11BSD on RP06 |
- tools/oskit/rsx11mp-30_rp - new oskit for RSX-11Mplus V3.0 on RP06 |
|
- Changes |
- renames |
- rtl/w11a/pdp11_sys70 -> pdp11_reg70 (_sys70 now different function) |
- functional changes |
- rtl/bplib/*/tb/tb_* - use serport_master instead of |
serport_uart_rxtx, allow xon/xoff |
- rtl/bplib/fx2rlink |
- rlink_sp1c_fx2 - add rbd_rbmon (optional via generics) |
- rtl/vlib/rlink/rlink_sp1c - add rbd_rbmon (optional via generics) |
- rtl/ibus/ibd_kw11l - freeze timer when cpu suspended |
- tools/bin/tbrun_tbwrri - add --fusp,--xon |
- tools/bin/ti_w11 - rename -fu->-fc, add -f2,-fx; setup defaults |
- tools/bin/librlink |
- RlinkCommandList - add SetLastExpect() methods |
- RlinkPort - add XonEnable() |
- RlinkPortCuff - add noinit attribute |
- RlinkPort(Fifo|Term) - add xon,noinit attributes |
- tools/src/librw11 |
- Rw11Cpu - add AddRbibr(), AddWbibr(), RAddrMap() |
- tools/bin/librlinktpp |
- RtclRlinkConnect - errcnt: add -increment |
log: add -bare,-info.. |
wtlam: allow tout=0 for attn cleanup |
init: new command |
exec: drop -estatdef |
- RtclRlinkServer - get/set interface added |
- tools/src/librwxxtpp |
- RtclRw11Cntl - start: new command |
- RtclRw11Cpu - cp: add -rbibr, wbibr, -rreg,...,-init |
- cp: add -estat(err|nak|tout), drop estatdef |
- rename amap->imap; add rmap |
|
- Bug fixes |
- rtl/ibus |
- ibdr_rk11 - interrupt after dreset and seek command start |
- tools/src/librlink |
- RlinkConnect - WaitAttn(): return 0. (not -1.) if poll |
- RlinkServer - Stop(): fix race in (could hang) |
|
- Known issues |
- all issues: see README_known_issues.txt |
- resolved issues: -- none -- |
- new issues: |
- V0.65-1: ti_rri sometimes crashes in normal rundown (exit or ^D) when |
a cuff: type rlink is active. One gets |
terminate called after throwing an instance of 'Retro::Rexception' |
what(): RlinkPortCuff::Cleanup(): driver thread failed to stop |
doesn't affect normal operation, will be fixed in upcoming release. |
- V0.65-2: some exotic RH70/RP/RM features and conditions not implemented |
- last block transfered flag (in DS) |
- CS2.BAI currently ignored and not handled |
- read or write 'with header' gives currently ILF |
All this isn't used by any OS, so in practice not relevant. |
|
- trunk (2015-03-01: svn rev 29(oc) 655(wfjm); untagged w11a_V0.64) +++++++++ |
|
- Preface |