OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

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    /w11/trunk
    from Rev 15 to Rev 16
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Rev 15 → Rev 16

/tools/tcl/rbemon/test_regs.tcl
1,4 → 1,4
# $Id: test_regs.tcl 375 2011-04-02 07:56:47Z mueller $
# $Id: test_regs.tcl 440 2011-12-18 20:08:09Z mueller $
#
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
13,6 → 13,7
#
# Revision History:
# Date Rev Version Comment
# 2011-12-18 440 1.0.1 increase npoll in "CNTL.clr->0" test
# 2011-04-02 375 1.0 Initial version
#
 
82,7 → 83,7
#
#-------------------------------------------------------------------------
rlc log " test 4: verify that CNTL.clr returns to 0"
set npoll 32
set npoll 48
set edat {}
set emsk {}
for {set i 0} {$i < $npoll} {incr i} { lappend edat 0x0000 }
/tools/tcl/setup_packages
11,4 → 11,5
pkg_mkIndex -verbose rbs3hio *.tcl
pkg_mkIndex -verbose rbemon *.tcl
#
#
pkg_mkIndex -verbose tst_rlink *.tcl
/tools/src/librlink/RlinkPortTerm.cpp
1,4 → 1,4
// $Id: RlinkPortTerm.cpp 435 2011-12-04 20:15:25Z mueller $
// $Id: RlinkPortTerm.cpp 440 2011-12-18 20:08:09Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
13,6 → 13,10
//
// Revision History:
// Date Rev Version Comment
// 2011-12-18 440 1.0.4 add kStatNPort stats; Open(): autoadd /dev/tty,
// BUGFIX: Open(): set VSTART, VSTOP
// 2011-12-11 438 1.0.3 Read(),Write(): added for xon handling, tcdrain();
// Open(): add more baud rates, support xon attribute
// 2011-12-04 435 1.0.2 Open(): add cts attr, hw flow control now optional
// 2011-07-04 388 1.0.1 add termios readback and verification
// 2011-03-27 374 1.0 Initial version
20,7 → 24,7
 
/*!
\file
\version $Id: RlinkPortTerm.cpp 435 2011-12-04 20:15:25Z mueller $
\version $Id: RlinkPortTerm.cpp 440 2011-12-18 20:08:09Z mueller $
\brief Implemenation of RlinkPortTerm.
*/
 
45,11 → 49,20
*/
 
//------------------------------------------+-----------------------------------
// constants definitions
const uint8_t RlinkPortTerm::kc_xon;
const uint8_t RlinkPortTerm::kc_xoff;
const uint8_t RlinkPortTerm::kc_xesc;
 
//------------------------------------------+-----------------------------------
//! Default constructor
 
RlinkPortTerm::RlinkPortTerm()
: RlinkPort()
{}
{
fStats.Define(kStatNPortTxXesc, "NPortTxXesc", "Tx XESC escapes");
fStats.Define(kStatNPortRxXesc, "NPortRxXesc", "Rx XESC escapes");
}
 
//------------------------------------------+-----------------------------------
//! Destructor
66,12 → 79,21
{
if (IsOpen()) Close();
 
if (!ParseUrl(url, "|baud=|break|cts|", emsg)) return false;
if (!ParseUrl(url, "|baud=|break|cts|xon", emsg)) return false;
 
// if path doesn't start with a '/' prepend a '/dev/tty'
if (fPath.substr(0,1) != "/") {
string dev = fPath;
fPath = "/dev/tty";
fPath += dev;
}
 
speed_t speed = B115200;
string baud;
if (UrlFindOpt("baud", baud)) {
speed = B0;
if (baud=="2400") speed = B2400;
if (baud=="4800") speed = B4800;
if (baud=="9600") speed = B9600;
if (baud=="19200" || baud=="19k") speed = B19200;
if (baud=="38400" || baud=="38k") speed = B38400;
81,9 → 103,14
if (baud=="460800" || baud=="460k") speed = B460800;
if (baud=="500000" || baud=="500k") speed = B500000;
if (baud=="921600" || baud=="921k") speed = B921600;
if (baud=="1000000" || baud=="1M") speed = B1000000;
if (baud=="2000000" || baud=="2M") speed = B2000000;
if (baud=="3000000" || baud=="3M") speed = B3000000;
if (baud=="1000000" || baud=="1000k" || baud=="1M") speed = B1000000;
if (baud=="1152000" || baud=="1152k") speed = B1152000;
if (baud=="1500000" || baud=="1500k") speed = B1500000;
if (baud=="2000000" || baud=="2000k" || baud=="2M") speed = B2000000;
if (baud=="2500000" || baud=="2500k") speed = B2500000;
if (baud=="3000000" || baud=="3000k" || baud=="3M") speed = B3000000;
if (baud=="3500000" || baud=="3500k") speed = B3500000;
if (baud=="4000000" || baud=="4000k" || baud=="4M") speed = B4000000;
if (speed == B0) {
emsg.Init("RlinkPortTerm::Open()",
string("invalid baud rate \"") + baud + string("\" specified"));
117,10 → 144,19
return false;
}
 
bool use_cts = UrlFindOpt("cts");
bool use_xon = UrlFindOpt("xon");
fUseXon = use_xon;
fPendXesc = false;
 
fTiosNew = fTiosOld;
 
fTiosNew.c_iflag = IGNBRK | // ignore breaks on input
IGNPAR; // ignore parity errors
if (use_xon) {
fTiosNew.c_iflag |= IXON| // XON/XOFF flow control output
IXOFF; // XON/XOFF flow control input
}
 
fTiosNew.c_oflag = 0;
 
128,7 → 164,7
CSTOPB | // 2 stop bits
CREAD | // enable receiver
CLOCAL; // ignore modem control
if (UrlFindOpt("cts")) {
if (use_cts) {
fTiosNew.c_cflag |= CRTSCTS; // enable hardware flow control
}
 
153,6 → 189,10
fTiosNew.c_cc[VSTOP] = 0; // undef
fTiosNew.c_cc[VMIN] = 1; // wait for 1 char
fTiosNew.c_cc[VTIME] = 0; //
if (use_xon) {
fTiosNew.c_cc[VSTART] = kc_xon; // setup XON -> ^Q
fTiosNew.c_cc[VSTOP] = kc_xoff; // setup XOFF -> ^S
}
 
if (tcsetattr(fd, TCSANOW, &fTiosNew) != 0) {
emsg.InitErrno("RlinkPortTerm::Open()",
234,6 → 274,78
}
//------------------------------------------+-----------------------------------
//! FIXME_docs
 
int RlinkPortTerm::Read(uint8_t* buf, size_t size, double timeout,
RerrMsg& emsg)
{
int irc;
if (fUseXon) {
uint8_t* po = buf;
if (fRxBuf.size() < size) fRxBuf.resize(size);
 
// repeat read untill at least one byte returned (or an error occurs)
// this avoids that the Read() returns with 0 in case only one byte is
// seen and this is a kc_xesc. At most two iterations possible because
// in 2nd iteration fPendXesc must be set and thus po pushed.
while (po == buf) {
irc = RlinkPort::Read(fRxBuf.data(), size, timeout, emsg);
if (irc <= 0) break;
uint8_t* pi = fRxBuf.data();
for (int i=0; i<irc; i++) {
uint8_t c = *pi++;
if (fPendXesc) {
*po++ = ~c;
fPendXesc = false;
} else if (c == kc_xesc) {
fStats.Inc(kStatNPortRxXesc);
fPendXesc = true;
} else {
*po++ = c;
}
}
irc = po - buf; // set irc to # of unescaped bytes
}
 
} else {
irc = RlinkPort::Read(buf, size, timeout, emsg);
}
 
return irc;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_docs
 
int RlinkPortTerm::Write(const uint8_t* buf, size_t size, RerrMsg& emsg)
{
int irc = 0;
if (fUseXon) {
fTxBuf.clear();
const uint8_t* pc = buf;
for (size_t i=0; i<size; i++) {
uint8_t c = *pc++;
if (c==kc_xon || c==kc_xoff || c==kc_xesc) {
fStats.Inc(kStatNPortTxXesc);
fTxBuf.push_back(kc_xesc);
fTxBuf.push_back(~c);
} else {
fTxBuf.push_back(c);
}
}
int irce = RlinkPort::Write(fTxBuf.data(), fTxBuf.size(), emsg);
if (irce == (int)fTxBuf.size()) irc = size;
} else {
irc = RlinkPort::Write(buf, size, emsg);
}
 
/* tcdrain(fFdWrite);*/
return irc;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
void RlinkPortTerm::Dump(std::ostream& os, int ind, const char* text) const
286,6 → 398,8
if (tios.c_cflag & PARODD) os << " PARODD";
speed_t speed = cfgetispeed(&tios);
int baud = 0;
if (speed == B2400) baud = 2400;
if (speed == B4800) baud = 4800;
if (speed == B9600) baud = 9600;
if (speed == B19200) baud = 19200;
if (speed == B38400) baud = 38400;
296,8 → 410,13
if (speed == B500000) baud = 500000;
if (speed == B921600) baud = 921600;
if (speed == B1000000) baud = 1000000;
if (speed == B1152000) baud = 1152000;
if (speed == B1500000) baud = 1500000;
if (speed == B2000000) baud = 2000000;
if (speed == B2500000) baud = 2500000;
if (speed == B3000000) baud = 3000000;
if (speed == B3500000) baud = 3500000;
if (speed == B4000000) baud = 4000000;
os << " speed: " << RosPrintf(baud, "d", 7);
os << endl;
 
/tools/src/librlink/RlinkPortTerm.hpp
1,4 → 1,4
// $Id: RlinkPortTerm.hpp 375 2011-04-02 07:56:47Z mueller $
// $Id: RlinkPortTerm.hpp 440 2011-12-18 20:08:09Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
13,6 → 13,8
//
// Revision History:
// Date Rev Version Comment
// 2011-12-18 440 1.0.2 add kStatNPort stats
// 2011-12-11 438 1.0.1 Read(),Write(): added for xon handling, tcdrain();
// 2011-03-27 374 1.0 Initial version
// ---------------------------------------------------------------------------
 
19,7 → 21,7
 
/*!
\file
\version $Id: RlinkPortTerm.hpp 375 2011-04-02 07:56:47Z mueller $
\version $Id: RlinkPortTerm.hpp 440 2011-12-18 20:08:09Z mueller $
\brief Declaration of class RlinkPortTerm.
*/
 
26,6 → 28,7
#ifndef included_Retro_RlinkPortTerm
#define included_Retro_RlinkPortTerm 1
 
#include <vector>
#include <termios.h>
 
#include "RlinkPort.hpp"
40,9 → 43,24
 
virtual bool Open(const std::string& url, RerrMsg& emsg);
virtual void Close();
virtual int Read(uint8_t* buf, size_t size, double timeout,
RerrMsg& emsg);
virtual int Write(const uint8_t* buf, size_t size, RerrMsg& emsg);
 
virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const;
 
// some constants
static const uint8_t kc_xon = 0x11; // XON char -> ^Q = hex 11
static const uint8_t kc_xoff = 0x13; // XOFF char -> ^S = hex 13
static const uint8_t kc_xesc = 0x1b; // XESC char -> ^[ = ESC = hex 1B
 
// statistics counter indices
enum stats {
kStatNPortTxXesc = RlinkPort::kDimStat,
kStatNPortRxXesc,
kDimStat
};
 
protected:
void DumpTios(std::ostream& os, int ind, const std::string& name,
const struct termios& tios) const;
50,6 → 68,10
protected:
struct termios fTiosOld;
struct termios fTiosNew;
bool fUseXon; //!< xon attribute set
bool fPendXesc; //!< xesc pending
std::vector<uint8_t> fTxBuf; //!< buffer to handle xesc
std::vector<uint8_t> fRxBuf; //!< buffer to handle xesc
};
} // end namespace Retro
/tools/src/Makefile
5,7 → 5,6
#
# Revision History:
# Date Rev Version Comment
# 2011-07-31 401 1.2 rename realclean->distclean; add librusbtpp
# 2011-03-20 372 1.1.1 renamed ..tcl -> ..tpp
# 2011-03-14 370 1.1.0 rename librtoolstcl -> librtcltools
# 2011-02-13 361 1.1 add realclean rule; add dirs and dependencies
/tools/bin/pi_rri
1,5 → 1,5
#!/usr/bin/perl -w
# $Id: pi_rri 435 2011-12-04 20:15:25Z mueller $
# $Id: pi_rri 440 2011-12-18 20:08:09Z mueller $
#
# Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
14,6 → 14,7
#
# Revision History:
# Date Rev Version Comment
# 2011-12-18 440 1.6.6 add xon/xoff flow control support
# 2011-12-04 435 1.6.5 add control over flow control (cts or none)
# 2011-09-17 410 1.6.4 use for crc8 now a6 polynomial
# 2010-12-29 351 1.6.3 rename rriext->cext and cpmon->rlmon
168,6 → 169,10
use constant D9NAK => 0x103;
use constant D9ATTN => 0x104;
 
use constant KC_XON => 0x11; # XON char -> ^Q = hex 11
use constant KC_XOFF => 0x13; # XOFF char -> ^S = hex 13
use constant KC_XESC => 0x1b; # XESC char -> ^[ = ESC = hex 1B
 
use constant PDPCP_ADDR_CONF => 000;
use constant PDPCP_ADDR_CNTL => 001;
use constant PDPCP_ADDR_STAT => 002;
443,6 → 448,9
my $raw_timeout = 1.;
my $cmax = 16;
 
my $xesc_enable = 0; # enables xon/xoff/xesc escaping
my $xesc_pending = 0; # xesc pending on receive
 
my $cmd_line;
my $cmd_rest;
my $cmd_bad;
6342,10 → 6350,14
&{$chan_tab{$curchan}{write}}(); # flush write queue before read
 
&{$chan_tab{$curchan}{read}}($timeout) unless @que_rcv;
if ($xesc_enable) {
&{$chan_tab{$curchan}{read}}($timeout) unless @que_rcv;
}
 
$dat = shift @que_rcv;
 
if (exists $opts{tio8} and defined $dat) {
print $fh_log conv_etime(\$tlast_tio8),
print $fh_log conv_etime(\$tlast_tio8),
"[$curchan] rcv8 ", conv_dat8($dat),"\n";
}
$stat_tab{ibyte} += 1;
6456,6 → 6468,9
print_fatal("flow attribute must be 0(none),1(cts), or 2(xon)")
unless ($flow>=0 && $flow<=2);
 
$xesc_enable = ($flow == 2); # enable/disable xesc escaping
$xesc_pending = 0;
 
## term_tios_print($term_oldtios);
 
my $newtios = new POSIX::Termios;
6462,7 → 6477,13
$newtios->getattr($fd) || die "getattr failed: $!"; ## hack for cygwin !!
 
my $c_iflag = &POSIX::BRKINT; # ignore parity errors (??? WRONG??)
if ($flow == 2) {
$c_iflag |= &POSIX::IXON | # XON/XOFF flow control output
&POSIX::IXOFF; # XON/XOFF flow control input
}
 
my $c_oflag = 0;
 
my $c_cflag = &POSIX::CS8 | # 8 bit chars
&POSIX::CSTOPB | # 2 stop bits
&POSIX::CREAD | # enable receiver
6470,9 → 6491,10
if ($flow == 1) { # if cts/rts flow control
$c_cflag |= LINUX_CRTSCTS; # enable hardware flow control
}
 
my $c_lflag = 0;
 
my $speed = 0;
 
$speed = &POSIX::B9600 if $baud == 9600;
$speed = &POSIX::B19200 if $baud == 19200;
$speed = &POSIX::B38400 if $baud == 38400;
6506,6 → 6528,11
$newtios->setcc(&POSIX::VMIN, 1); # wait for 1 char
$newtios->setcc(&POSIX::VTIME, 0); #
 
if ($flow == 2) {
$newtios->setcc(&POSIX::VSTART, KC_XON); # setup XON -> ^Q
$newtios->setcc(&POSIX::VSTOP, KC_XOFF); # setup XOFF -> ^S
}
 
## term_tios_print($newtios);
 
$newtios->setattr($fd) || die "setattr failed: $!";
6634,15 → 6661,30
 
if (exists $opts{tiob}) {
printf $fh_log "%s[$curchan] read %3d bytes in %8.6f sec\n",
conv_etime(\$tlast_tiob), $rc, get_time()-$tstart;
conv_etime(\$tlast_tiob), $rc, get_time()-$tstart;
}
if ($rc) {
push @que_rcv, unpack("C*", $buf);
if ($xesc_enable) {
my @que_rcv_xesc = unpack("C*", $buf);
foreach my $char (@que_rcv_xesc) {
if ($xesc_pending) {
push @que_rcv, (~$char) & 0xff;
$xesc_pending = 0;
} elsif ($char == KC_XESC) {
$xesc_pending = 1;
} else {
push @que_rcv, $char;
}
}
 
} else {
push @que_rcv, unpack("C*", $buf);
}
}
}
### if (defined $rc) {
### printf "+++1 _read $timeout rc=%d\n", $rc;
### } else {
### } else {
### printf "+++1 _read $timeout rc=undef\n";
### }
return $rc;
6654,7 → 6696,24
## printf "+++2 _write q=%d\n", scalar @que_snd;
if (scalar @que_snd) {
 
my $buf = pack("C*", @que_snd);
my $buf;
 
if ($xesc_enable) { # handle xon,xoff,xesc escaping
my @que_snd_xesc;
foreach my $char (@que_snd) {
if ($char==KC_XON || $char==KC_XOFF || $char==KC_XESC) {
push @que_snd_xesc, KC_XESC;
push @que_snd_xesc, (~$char) & 0xff;
} else {
push @que_snd_xesc, $char;
}
}
$buf = pack("C*", @que_snd_xesc);
 
} else {
$buf = pack("C*", @que_snd);
}
 
while (length($buf)) {
while(1) { # read rcv fifo before writing
my $rc = genio_read(0.); # to avoid blocking under cygwin
/tools/bin/ti_rri
1,6 → 1,6
#! /usr/bin/env tclsh
# -*- tcl -*-
# $Id: ti_rri 435 2011-12-04 20:15:25Z mueller $
# $Id: ti_rri 440 2011-12-18 20:08:09Z mueller $
#
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
15,6 → 15,7
#
# Revision History:
# Date Rev Version Comment
# 2011-12-19 440 1.0.3 re-organize option handling for --term and --fifo
# 2011-12-04 435 1.0.2 add flow attribute to --term
# 2011-04-22 379 1.0.1 check for RETROBASE; proper exit handling; help text
# 2011-04-17 376 1.0 Initial version
21,8 → 22,8
# 2011-03-19 371 0.1 First draft
#
#
# --fifo[=name,keep]
# --term[=name,baud,break,flow]
# --fifo[=name,opts,...]
# --term[=name,baud,opts,...]
# --run=command
# --log=filename ; default "-"
# --logl=n ; default 2
108,24 → 109,25
puts { --fifo[=ARGS] open fifo type rlink port. Optional arguments are:}
puts { --fifo=[NAME[,KEEP]]}
puts { NAME fifo name prefix, default 'rlink_cext_fifo'}
puts { KEEP if non-empty the fifo is kept open on exit}
puts { OPTS further options (comma separated list):}
puts { keep fifo is kept open on exit}
puts { --term[=ARGS] open term type rlink port. Optional arguments are:}
puts { --term=[NAME[,BAUD[,BREAK[,FLOW]]]]}
puts { --term=[NAME[,BAUD[,OPTS]]]}
puts { NAME tty device name, default 'USB0'}
puts { if not starting with '/' the name is}
puts { prefixed with '/dev/tty'}
puts { BAUD serial port baud rate, default '115k'}
puts { allowed baud rate settings are:}
puts { 9600, 19200, 19k, 38400, 38k, 57600, 57k}
puts { 115200, 115k, 230400, 230k, 460800, 460k}
puts { 500000, 500k, 921600, 921k, 1000000, 1M}
puts { 2000000, 2M, 3000000, 3M}
puts { BREAK controls whether a break will be send:}
puts { 0 no break (default)}
puts { 1 send break, do autobaud}
puts { FLOW controls flow control regime:}
puts { 0 no flow control (default)}
puts { 1 cts/rts hardware flow control}
puts { 2400, 4800, 9600, 19200, 19k, 38400, 38k}
puts { 57600, 57k, 115200, 115k, 230400, 230k}
puts { 460800, 460k, 500000, 500k, 921600, 921k}
puts { 1000000, 1000k, 1M, 1500000, 1500k}
puts { 2000000, 2000k, 2M, 2500000, 2500k}
puts { 3000000, 3000k, 3M, 4000000, 4000k, 4M}
puts { OPTS further options (comma separated list):}
puts { break send a break, do autobaud}
puts { cts hardware flow control (cts/rts)}
puts { xon software flow control (xon/xoff)}
puts { --log=FILE set log file name. Default is to write to stdout.}
puts { --logl=LVL set log level, default is '2' allowed values:}
puts { 0 no logging}
191,10 → 193,14
if { $opts(fifo) } {
set nlist [split $opts(fifo_) ","]
set path [lindex $nlist 0]
set keep [lindex $nlist 1]
if {$path eq ""} {set path "rlink_cext_fifo"}
set url "fifo:$path"
if {$keep ne ""} {append url "?keep"}
set delim "?"
foreach opt [lrange $nlist 1 end] {
if {$opt ne ""} {append url "$delim$opt"}
set delim ";"
}
# puts "-I: $url"
rlc open $url
}
 
203,18 → 209,12
set nlist [split $opts(term_) ","]
set dev [lindex $nlist 0]
set baud [lindex $nlist 1]
set brk [lindex $nlist 2]
set flow [lindex $nlist 3]
if {$dev eq ""} {set dev "USB0"}
if {$baud eq ""} {set baud "115k"}
if {$brk eq ""} {set brk 0}
if {$flow eq ""} {set flow 0}
if {! [regexp -- {^/} $dev]} {
set dev "/dev/tty$dev"
set url "term:$dev?baud=$baud"
foreach opt [lrange $nlist 2 end] {
if {$opt ne ""} {append url ";$opt"}
}
set url "term:$dev?baud=$baud"
if {$brk eq 1} {append url ";break"}
if {$flow eq 1} {append url ";cts"}
# puts "-I: $url"
rlc open $url
}
/rtl/sys_gen/tst_rlink/tst_rlink.vbom File deleted
/rtl/sys_gen/tst_rlink/tst_rlink.vhd File deleted
/rtl/sys_gen/tst_rlink/rbd_tst_rlink.vhd
0,0 → 1,191
-- $Id: rbd_tst_rlink.vhd 438 2011-12-11 23:40:52Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rbd_tst_rlink - syn
-- Description: rbus device for tst_rlink
--
-- Dependencies: rbus/rbd_tester
-- rbus/rbd_bram
-- rbus/rbd_rbmon
-- rbus/rbd_eyemon
-- rbus/rbd_timer
-- rbus/rb_sres_or_3
-- rbus/rb_sres_or_4
--
-- Test bench: nexys3/tb/tb_tst_rlink_n3
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-11 351 1.0 Initial version (derived from tst_rlink)
------------------------------------------------------------------------------
-- Usage of STAT signal:
-- STAT(0): timer 0 busy
-- STAT(1): timer 1 busy
-- STAT(2:7): unused
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.rblib.all;
use work.rbdlib.all;
 
-- ----------------------------------------------------------------------------
 
entity rbd_tst_rlink is -- rbus device for tst_rlink
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_USEC : in slbit; -- usec pulse
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv3; -- rbus: status flags
RB_SRES_TOP : in rb_sres_type; -- top-level rb_sres, for rbd_mon
RXSD : in slbit; -- serport rxsd, for rbd_emon
RXACT : in slbit; -- serport rxact, for rbd_emon
STAT : out slv8 -- status flags
 
);
end rbd_tst_rlink;
 
architecture syn of rbd_tst_rlink is
 
signal RB_SRES_TEST : rb_sres_type := rb_sres_init;
signal RB_SRES_BRAM : rb_sres_type := rb_sres_init;
signal RB_SRES_MON : rb_sres_type := rb_sres_init;
signal RB_SRES_EMON : rb_sres_type := rb_sres_init;
signal RB_SRES_TIM0 : rb_sres_type := rb_sres_init;
signal RB_SRES_TIM1 : rb_sres_type := rb_sres_init;
signal RB_SRES_SUM1 : rb_sres_type := rb_sres_init;
 
signal RB_LAM_TEST : slv16 := (others=>'0');
 
signal TIM0_DONE : slbit := '0';
signal TIM0_BUSY : slbit := '0';
signal TIM1_DONE : slbit := '0';
signal TIM1_BUSY : slbit := '0';
 
constant rbaddr_mon : slv8 := "11111100"; -- 111111xx
constant rbaddr_emon : slv8 := "11111000"; -- 111110xx
constant rbaddr_bram : slv8 := "11110100"; -- 111101xx
constant rbaddr_test : slv8 := "11110000"; -- 111100xx
constant rbaddr_tim1 : slv8 := "11100001"; -- 11100001
constant rbaddr_tim0 : slv8 := "11100000"; -- 11100000
begin
 
TEST : rbd_tester
generic map (
RB_ADDR => rbaddr_test)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TEST,
RB_LAM => RB_LAM_TEST,
RB_STAT => RB_STAT
);
BRAM : rbd_bram
generic map (
RB_ADDR => rbaddr_bram)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_BRAM
);
MON : rbd_rbmon
generic map (
RB_ADDR => rbaddr_mon,
AWIDTH => 9)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_MON,
RB_SRES_SUM => RB_SRES_TOP
);
 
EMON : rbd_eyemon
generic map (
RB_ADDR => rbaddr_emon,
RDIV => slv(to_unsigned(0,8)))
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_EMON,
RXSD => RXSD,
RXACT => RXACT
);
 
TIM0 : rbd_timer
generic map (
RB_ADDR => rbaddr_tim0)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TIM0,
DONE => TIM0_DONE,
BUSY => TIM0_BUSY
);
 
TIM1 : rbd_timer
generic map (
RB_ADDR => rbaddr_tim1)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TIM1,
DONE => TIM1_DONE,
BUSY => TIM1_BUSY
);
 
RB_SRES_OR1 : rb_sres_or_3
port map (
RB_SRES_1 => RB_SRES_TEST,
RB_SRES_2 => RB_SRES_BRAM,
RB_SRES_3 => RB_SRES_MON,
RB_SRES_OR => RB_SRES_SUM1
);
 
RB_SRES_OR : rb_sres_or_4
port map (
RB_SRES_1 => RB_SRES_SUM1,
RB_SRES_2 => RB_SRES_EMON,
RB_SRES_3 => RB_SRES_TIM0,
RB_SRES_4 => RB_SRES_TIM1,
RB_SRES_OR => RB_SRES
);
 
RB_LAM(15 downto 2) <= RB_LAM_TEST(15 downto 2);
RB_LAM(1) <= TIM1_DONE;
RB_LAM(0) <= TIM0_DONE;
STAT(0) <= TIM0_BUSY;
STAT(1) <= TIM1_BUSY;
STAT(7 downto 2) <= (others=>'0');
end syn;
/rtl/sys_gen/tst_rlink/rbd_tst_rlink.vbom
0,0 → 1,14
# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
../../vlib/rbus/rbdlib.vhd
# components
../../vlib/rbus/rbd_tester.vbom
../../vlib/rbus/rbd_bram.vbom
../../vlib/rbus/rbd_rbmon.vbom
../../vlib/rbus/rbd_eyemon.vbom
../../vlib/rbus/rbd_timer.vbom
../../vlib/rbus/rb_sres_or_3.vbom
../../vlib/rbus/rb_sres_or_4.vbom
# design
rbd_tst_rlink.vhd
/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.mfset
1,4 → 1,4
# $Id: sys_tst_rlink_n2.mfset 427 2011-11-19 21:04:11Z mueller $
# $Id: sys_tst_rlink_n2.mfset 440 2011-12-18 20:08:09Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
9,29 → 9,26
Node <HIO/R_REGS.btneff_[0-5]> of sequential type is unconnected
Node <HIO/R_REGS.btn_[0-5]> of sequential type is unconnected
 
Unconnected output port 'SIZE' of component 'fifo_1c_dram'
Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'OFIFO_SIZE' of component 'rlink_base'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen'
Unconnected output port 'RL_MONI' of component 'rlink_sp1c'
 
Input <I_MEM_WAIT> is never used
Input <RB_MREQ.din<\d+:\d+>> is never used
Input <RB_MREQ.init> is never used
Input <RB_MREQ.aval> is never used
Input <RB_MREQ.re> is never used
Input <CE_USEC> is never used
 
Signal <L_DO<17:16>> is assigned but never used
Signal <FIFO_SIZE> is assigned but never used
Signal <SIZE<1:0>> is assigned but never used
ignal <RL_MONI.lamp> is assigned but never used
Signal <RL_MONI.eop> is assigned but never used
Signal <RL_MONI.attn> is assigned but never used
Signal <RXFIFO_SIZE<2:0>> is assigned but never used
Signal <RB_LAM_TEST<1:0>> is assigned but never used
Signal <SWI<7:1>> is assigned but never used
Signal <SWI<7:2>> is assigned but never used
Signal <SER_MONI.rxovr> is assigned but never used
Signal <SER_MONI.rxerr> is assigned but never used
Signal <SER_MONI.abdone> is assigned but never used
Signal <STAT<7:2>> is assigned but never used
Signal <RL_SER_MONI.rxerr> is assigned but never used
Signal <RL_SER_MONI.rxdrop> is assigned but never used
Signal <RL_SER_MONI.abdone> is assigned but never used
Signal <BTN> is assigned but never used
 
FF/Latch <R_REGS.ledin_2> in Unit <sn_humanio_rbus> is equivalent
/rtl/sys_gen/tst_rlink/nexys2/tb/tb_tst_rlink_n2.vhd
1,4 → 1,4
-- $Id: tb_tst_rlink_n2.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: tb_tst_rlink_n2.vhd 437 2011-12-09 19:38:07Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
12,7 → 12,7
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_rlink
-- Module Name: tb_tst_rlink_n2
-- Description: Configuration for tb_tst_rlink_n2 for tb_nexys2_fusp
--
-- Dependencies: sys_tst_rlink_n2
/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd
1,4 → 1,4
-- $Id: sys_tst_rlink_n2.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: sys_tst_rlink_n2.vhd 442 2011-12-23 10:03:28Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
19,7 → 19,9
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- tst_rlink
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- vlib/rbus/rb_sres_or_2
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: tb/tb_tst_rlink_n2
29,6 → 31,7
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-18 440 13.1 O40d xc3s1200e-4 754 1605 96 1057 t 16.8
-- 2011-06-26 385 12.1 M53d xc3s1200e-4 688 1500 68 993 t 16.2
-- 2011-04-02 375 12.1 M53d xc3s1200e-4 688 1572 68 994 t 13.8
-- 2010-12-29 351 12.1 M53d xc3s1200e-4 604 1298 68 851 t 14.7
35,6 → 38,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-18 440 1.1.6 use now rbd_tst_rlink and rlink_sp1c
-- 2011-11-26 433 1.1.5 use nx_cram_dummy now
-- 2011-11-23 432 1.1.4 update O_FLA_CE_N usage
-- 2011-11-17 426 1.1.3 use dcm_sfs now
45,20 → 49,21
------------------------------------------------------------------------------
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
-- (1:7): no function (only connected to s3_humanio_rbus)
--
-- LED(7): SER_MONI.abact
-- LED(6:2): no function (only connected to sn_humanio_rbus)
-- LED(0): timer 0 busy
-- LED(1): timer 1 busy
-- LED(2:6): no function (only connected to s3_humanio_rbus)
-- LED(7): RL_SER_MONI.abact
--
-- DSP: RL_SER_MONI.clkdiv (from auto bauder)
-- DP(0): RL_SER_MONI.rxact
-- DP(1): RTS_N (shows rx back preasure)
-- DP(2): RL_SER_MONI.txact
-- DP(3): CTS_N (shows tx back preasure)
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back preasure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
 
library ieee;
67,6 → 72,7
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serport.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
124,9 → 130,15
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
 
signal RB_MREQ_TOP : rb_mreq_type := rb_mreq_init;
signal RB_SRES_TOP : rb_sres_type := rb_sres_init;
signal RL_SER_MONI : rl_ser_moni_type := rl_ser_moni_init;
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
 
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
 
constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
188,8 → 200,8
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ_TOP,
RB_SRES => RB_SRES_TOP,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
202,24 → 214,59
O_SEG_N => O_SEG_N
);
 
RLTEST : entity work.tst_rlink
RLINK : rlink_sp1c
generic map (
CDINIT => sys_conf_ser2rri_cdinit)
ATOWIDTH => 6,
ITOWIDTH => 6,
CPREF => c_rlink_cpref,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 15,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
 
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ_TOP => RB_MREQ_TOP,
RB_SRES_TOP => RB_SRES_TOP,
RL_SER_MONI => RL_SER_MONI,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
 
RB_SRES_OR1 : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_HIO,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_OR => RB_SRES
);
 
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
236,13 → 283,14
 
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
 
DSP_DAT <= RL_SER_MONI.clkdiv;
DSP_DP(0) <= RL_SER_MONI.rxact;
DSP_DP(1) <= RTS_N;
DSP_DP(2) <= RL_SER_MONI.txact;
DSP_DP(3) <= CTS_N;
DSP_DAT <= SER_MONI.abclkdiv;
 
LED(7) <= RL_SER_MONI.abact;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
 
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom
2,6 → 2,7
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../vlib/serport/serport.vhd
../../../vlib/rbus/rblib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
13,7 → 14,9
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio_rbus.vbom
../tst_rlink.vbom
../../../vlib/rlink/rlink_sp1c.vbom
../rbd_tst_rlink.vbom
../../../vlib/rbus/rb_sres_or_2.vbom
../../../bplib/nxcramlib/nx_cram_dummy.vbom
# design
sys_tst_rlink_n2.vhd
/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd
1,4 → 1,4
-- $Id: sys_tst_rlink_n3.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: sys_tst_rlink_n3.vhd 442 2011-12-23 10:03:28Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
19,7 → 19,9
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- tst_rlink
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- vlib/rbus/rb_sres_or_2
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: tb/tb_tst_rlink_n3
29,28 → 31,32
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-18 440 13.1 O40d xc6slx16-2 752 1258 48 439 t 7.9
-- 2011-11-26 433 13.1 O40d xc6slx16-2 722 1199 36 423 t 9.7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-18 440 1.1.1 use [rt]xok for DSP_DP
-- 2011-12-11 438 1.1 use now rbd_tst_rlink and rlink_sp1c
-- 2011-11-26 433 1.0 Initial version (derived from sys_tst_rlink_n2)
------------------------------------------------------------------------------
-- Usage of Nexys 3 Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
-- (1:7): no function (only connected to s3_humanio_rbus)
--
-- LED(7): SER_MONI.abact
-- LED(6:2): no function (only connected to sn_humanio_rbus)
-- LED(0): timer 0 busy
-- LED(1): timer 1 busy
-- LED(2:6): no function (only connected to s3_humanio_rbus)
-- LED(7): RL_SER_MONI.abact
--
-- DSP: RL_SER_MONI.clkdiv (from auto bauder)
-- DP(0): RL_SER_MONI.rxact
-- DP(1): RTS_N (shows rx back preasure)
-- DP(2): RL_SER_MONI.txact
-- DP(3): CTS_N (shows tx back preasure)
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back preasure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
 
library ieee;
59,6 → 65,7
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serport.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
116,9 → 123,15
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
 
signal RB_MREQ_TOP : rb_mreq_type := rb_mreq_init;
signal RB_SRES_TOP : rb_sres_type := rb_sres_init;
signal RL_SER_MONI : rl_ser_moni_type := rl_ser_moni_init;
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
 
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
 
constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
179,8 → 192,8
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ_TOP,
RB_SRES => RB_SRES_TOP,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
193,24 → 206,59
O_SEG_N => O_SEG_N
);
 
RLTEST : entity work.tst_rlink
RLINK : rlink_sp1c
generic map (
CDINIT => sys_conf_ser2rri_cdinit)
ATOWIDTH => 6,
ITOWIDTH => 6,
CPREF => c_rlink_cpref,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 15,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
 
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ_TOP => RB_MREQ_TOP,
RB_SRES_TOP => RB_SRES_TOP,
RL_SER_MONI => RL_SER_MONI,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
 
RB_SRES_OR1 : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_HIO,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_OR => RB_SRES
);
 
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
228,13 → 276,14
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
 
DSP_DAT <= RL_SER_MONI.clkdiv;
DSP_DP(0) <= RL_SER_MONI.rxact;
DSP_DP(1) <= RTS_N;
DSP_DP(2) <= RL_SER_MONI.txact;
DSP_DP(3) <= CTS_N;
DSP_DAT <= SER_MONI.abclkdiv;
 
LED(7) <= RL_SER_MONI.abact;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
 
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vbom
2,6 → 2,7
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../vlib/serport/serport.vhd
../../../vlib/rbus/rblib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
13,7 → 14,9
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio_rbus.vbom
../tst_rlink.vbom
../../../vlib/rlink/rlink_sp1c.vbom
../rbd_tst_rlink.vbom
../../../vlib/rbus/rb_sres_or_2.vbom
../../../bplib/nxcramlib/nx_cram_dummy.vbom
# design
sys_tst_rlink_n3.vhd
/rtl/sys_gen/tst_rlink/s3board/sys_conf.vhd
0,0 → 1,44
-- $Id: sys_conf.vhd 442 2011-12-23 10:03:28Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_s3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-22 442 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package sys_conf is
 
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
 
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
 
-- derived constants
 
constant sys_conf_clksys : integer := 50000000;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
 
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
/rtl/sys_gen/tst_rlink/s3board/tb/tbw.dat
0,0 → 1,6
# $Id: tbw.dat 442 2011-12-23 10:03:28Z mueller $
#
[tb_tst_rlink_s3]
rlink_cext_fifo_rx = <fifo>
rlink_cext_fifo_tx = <fifo>
rlink_cext_conf = <null>
/rtl/sys_gen/tst_rlink/s3board/tb/tb_tst_rlink_s3.vhd
0,0 → 1,39
-- $Id: tb_tst_rlink_s3.vhd 442 2011-12-23 10:03:28Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_rlink_s3
-- Description: Configuration for tb_tst_rlink_s3 for tb_s3board_fusp
--
-- Dependencies: sys_tst_rlink_s3
--
-- To test: sys_tst_rlink_s3
--
-- Verified:
-- Date Rev Code ghdl ise Target Comment
-- 2011-12-22 442 - 0.29 13.1 O40d xc3s1000 u:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-22 442 1.0 Initial version
------------------------------------------------------------------------------
 
configuration tb_tst_rlink_s3 of tb_s3board_fusp is
 
for sim
for all : s3board_fusp_aif
use entity work.sys_tst_rlink_s3;
end for;
end for;
 
end tb_tst_rlink_s3;
/rtl/sys_gen/tst_rlink/s3board/tb/tb_tst_rlink_s3.vbom
0,0 → 1,7
# configure tb_s3board_fusp with sys_tst_rlink_s3 target;
# use vhdl configure file (tb_tst_rlink_s3.vhd) to allow
# that all configurations will co-exist in work library
s3board_aif : ../sys_tst_rlink_s3.vbom
sys_conf = sys_conf_sim.vhd
../../../../bplib/s3board/tb/tb_s3board_fusp.vbom
tb_tst_rlink_s3.vhd
/rtl/sys_gen/tst_rlink/s3board/tb/sys_tst_rlink_s3.ucf_cpp
0,0 → 1,7
link ../sys_tst_rlink_s3.ucf_cpp
rtl/sys_gen/tst_rlink/s3board/tb/sys_tst_rlink_s3.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: rtl/sys_gen/tst_rlink/s3board/tb/sys_conf_sim.vhd =================================================================== --- rtl/sys_gen/tst_rlink/s3board/tb/sys_conf_sim.vhd (nonexistent) +++ rtl/sys_gen/tst_rlink/s3board/tb/sys_conf_sim.vhd (revision 16) @@ -0,0 +1,41 @@ +-- $Id: sys_conf_sim.vhd 442 2011-12-23 10:03:28Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_s3 (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-22 442 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- derived constants + + constant sys_conf_clksys : integer := 50000000; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + +end package sys_conf; Index: rtl/sys_gen/tst_rlink/s3board/tb/Makefile =================================================================== --- rtl/sys_gen/tst_rlink/s3board/tb/Makefile (nonexistent) +++ rtl/sys_gen/tst_rlink/s3board/tb/Makefile (revision 16) @@ -0,0 +1,30 @@ +# $Id: Makefile 442 2011-12-23 10:03:28Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-12-22 442 1.0 Initial version +# +EXE_all = tb_tst_rlink_s3 +# +ISE_PATH = xc3s1000-ft256-4 +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean + rm -f sys_tst_rlink_s3.ucf +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +# Index: rtl/sys_gen/tst_rlink/s3board/tb/.cvsignore =================================================================== --- rtl/sys_gen/tst_rlink/s3board/tb/.cvsignore (nonexistent) +++ rtl/sys_gen/tst_rlink/s3board/tb/.cvsignore (revision 16) @@ -0,0 +1,7 @@ +tb_tst_rlink_s3 +tb_tst_rlink_s3_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +sys_tst_rlink_s3.ucf +*.dep_ucf_cpp Index: rtl/sys_gen/tst_rlink/s3board/tb =================================================================== --- rtl/sys_gen/tst_rlink/s3board/tb (nonexistent) +++ rtl/sys_gen/tst_rlink/s3board/tb (revision 16)
rtl/sys_gen/tst_rlink/s3board/tb Property changes : Added: svn:ignore ## -0,0 +1,39 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_tst_rlink_s3 +tb_tst_rlink_s3_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +sys_tst_rlink_s3.ucf +*.dep_ucf_cpp Index: rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.ucf_cpp =================================================================== --- rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.ucf_cpp (nonexistent) +++ rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.ucf_cpp (revision 16) @@ -0,0 +1,19 @@ +## $Id: sys_tst_rlink_s3.ucf_cpp 442 2011-12-23 10:03:28Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-12-22 442 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +## std board +## +#include "bplib/s3board/s3board_pins.ucf" +## +## Pmod1-RS232 on A2 connector +## +#include "bplib/s3board/s3board_a2_pm1_rs232.ucf" Index: rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd =================================================================== --- rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd (nonexistent) +++ rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd (revision 16) @@ -0,0 +1,262 @@ +-- $Id: sys_tst_rlink_s3.vhd 442 2011-12-23 10:03:28Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_rlink_s3 - syn +-- Description: rlink tester design for s3board +-- +-- Dependencies: vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2l4l_iob +-- bplib/bpgen/sn_humanio_rbus +-- vlib/rlink/rlink_sp1c +-- rbd_tst_rlink +-- vlib/rbus/rb_sres_or_2 +-- bplib/s3board/s3_sram_dummy +-- +-- Test bench: tb/tb_tst_rlink_s3 +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-12-22 442 13.1 O40d xc3s1000e-4 765 1672 96 1088 t 12.6 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-22 442 1.0 Initial version (derived from sys_tst_rlink_n2) +------------------------------------------------------------------------------ +-- Usage of S3board switches, Buttons, LEDs: +-- +-- SWI(7:2): no function (only connected to sn_humanio_rbus) +-- SWI(1): 1 enable XON +-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob +-- 1 -> Pmod B/top RS232 port / +-- +-- LED(7): SER_MONI.abact +-- LED(6:2): no function (only connected to sn_humanio_rbus) +-- LED(0): timer 0 busy +-- LED(1): timer 1 busy +-- +-- DSP: SER_MONI.clkdiv (from auto bauder) +-- DP(3): not SER_MONI.txok (shows tx back preasure) +-- DP(2): SER_MONI.txact (shows tx activity) +-- DP(1): not SER_MONI.rxok (shows rx back preasure) +-- DP(0): SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.serport.all; +use work.rblib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.s3boardlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_rlink_s3 is -- top level + -- implements s3board_fusp_aif + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- s3 switches + I_BTN : in slv4; -- s3 buttons + O_LED : out slv8; -- s3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32; -- sram: data lines + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end sys_tst_rlink_s3; + +architecture syn of sys_tst_rlink_s3 is + + signal CLK : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv3 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + signal STAT : slv8 := (others=>'0'); + + constant rbaddr_hio : slv8 := "11000000"; -- 110000xx + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + RESET <= '0'; -- so far not used + CLK <= I_CLK50; + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + HIO : sn_humanio_rbus + generic map ( + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RLINK : rlink_sp1c + generic map ( + ATOWIDTH => 6, + ITOWIDTH => 6, + CPREF => c_rlink_cpref, + IFAWIDTH => 5, + OFAWIDTH => 5, + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 15, + CDINIT => sys_conf_ser2rri_cdinit) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ENAESC => SWI(1), + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + RBDTST : entity work.rbd_tst_rlink + port map ( + CLK => CLK, + RESET => RESET, + CE_USEC => CE_USEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TST, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RB_SRES_TOP => RB_SRES, + RXSD => RXD, + RXACT => SER_MONI.rxact, + STAT => STAT + ); + + RB_SRES_OR1 : rb_sres_or_2 + port map ( + RB_SRES_1 => RB_SRES_HIO, + RB_SRES_2 => RB_SRES_TST, + RB_SRES_OR => RB_SRES + ); + + SRAM : s3_sram_dummy -- connect SRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + DSP_DAT <= SER_MONI.abclkdiv; + + DSP_DP(3) <= not SER_MONI.txok; + DSP_DP(2) <= SER_MONI.txact; + DSP_DP(1) <= not SER_MONI.rxok; + DSP_DP(0) <= SER_MONI.rxact; + + LED(7) <= SER_MONI.abact; + LED(6 downto 2) <= (others=>'0'); + LED(1) <= STAT(1); + LED(0) <= STAT(0); + +end syn; Index: rtl/sys_gen/tst_rlink/s3board/.cvsignore =================================================================== --- rtl/sys_gen/tst_rlink/s3board/.cvsignore (nonexistent) +++ rtl/sys_gen/tst_rlink/s3board/.cvsignore (revision 16) @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_rlink_s3.ucf +*.dep_ucf_cpp +*.svf Index: rtl/sys_gen/tst_rlink/s3board/Makefile =================================================================== --- rtl/sys_gen/tst_rlink/s3board/Makefile (nonexistent) +++ rtl/sys_gen/tst_rlink/s3board/Makefile (revision 16) @@ -0,0 +1,27 @@ +# $Id: Makefile 442 2011-12-23 10:03:28Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-12-22 442 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +ISE_BOARD = s3board +ISE_PATH = xc3s1000-ft256-4 +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f sys_tst_rlink_s3.ucf +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +# Index: rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vbom =================================================================== --- rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vbom (nonexistent) +++ rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vbom (revision 16) @@ -0,0 +1,20 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serport.vhd +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/s3board/s3boardlib.vbom +sys_conf : sys_conf.vhd +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../vlib/rlink/rlink_sp1c.vbom +../rbd_tst_rlink.vbom +../../../vlib/rbus/rb_sres_or_2.vbom +../../../bplib/s3board/s3_sram_dummy.vbom +# design +sys_tst_rlink_s3.vhd +@ucf_cpp: sys_tst_rlink_s3.ucf Index: rtl/sys_gen/tst_rlink/s3board =================================================================== --- rtl/sys_gen/tst_rlink/s3board (nonexistent) +++ rtl/sys_gen/tst_rlink/s3board (revision 16)
rtl/sys_gen/tst_rlink/s3board Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_rlink_s3.ucf +*.dep_ucf_cpp +*.svf Index: rtl/sys_gen/tst_rlink/Makefile =================================================================== --- rtl/sys_gen/tst_rlink/Makefile (nonexistent) +++ rtl/sys_gen/tst_rlink/Makefile (revision 16) @@ -0,0 +1,24 @@ +# $Id: Makefile 438 2011-12-11 23:40:52Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-12-11 438 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +ISE_PATH = xc3s1000-ft256-4 +# +.PHONY : all clean realclean +# +all : $(NGC_all) +# +clean : ise_clean +# +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +include $(VBOM_all:.vbom=.dep_xst) +# Index: rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd =================================================================== --- rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd (revision 15) +++ rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd (revision 16) @@ -1,4 +1,4 @@ --- $Id: sys_w11a_n2.vhd 433 2011-11-27 22:04:39Z mueller $ +-- $Id: sys_w11a_n2.vhd 440 2011-12-18 20:08:09Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_2l4l_iob -- bplib/bpgen/sn_humanio_rbus --- vlib/rlink/rlink_base_serport +-- vlib/rlink/rlink_sp1c -- vlib/rri/rb_sres_or_3 -- w11a/pdp11_core_rbus -- w11a/pdp11_core @@ -40,6 +40,7 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-12-18 440 13.1 O40d xc3s1200e-4 1450 4439 270 2740 ok: LP+PC+DL+II -- 2011-11-18 427 13.1 O40d xc3s1200e-4 1433 4374 242 2680 ok: LP+PC+DL+II -- 2010-12-30 351 12.1 M53d xc3s1200e-4 1389 4368 242 2674 ok: LP+PC+DL+II -- 2010-11-06 336 12.1 M53d xc3s1200e-4 1357 4304* 242 2618 ok: LP+PC+DL+II @@ -63,6 +64,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-12-18 440 1.2.7 use rlink_sp1c -- 2011-11-26 433 1.2.6 use nx_cram_(dummy|memctl_as) now -- 2011-11-23 432 1.2.5 update O_FLA_CE_N usage -- 2011-11-19 427 1.2.4 now numeric_std clean @@ -93,26 +95,29 @@ -- -- Usage of Nexys 2 Switches, Buttons, LEDs: -- +-- SWI(7:2): no function (only connected to sn_humanio_rbus) +-- SWI(1): 1 enable XON -- SWI(0): 0 -> main board RS232 port -- 1 -> Pmod B/top RS232 port -- --- LED(0:4): if cpugo=1 show cpu mode activity +-- LED(7) MEM_ACT_W +-- (6) MEM_ACT_R +-- (5) cmdbusy (all rlink access, mostly rdma) +-- (4:0): if cpugo=1 show cpu mode activity +-- (4) kernel mode, pri>0 +-- (3) kernel mode, pri=0 +-- (2) kernel mode, wait +-- (1) supervisor mode -- (0) user mode --- (1) supervisor mode --- (2) kernel mode, wait --- (3) kernel mode, pri=0 --- (4) kernel mode, pri>0 -- if cpugo=0 shows cpurust -- (3:0) cpurust code -- (4) '1' --- (5) cmdbusy (all rlink access, mostly rdma) --- (6) MEM_ACT_R --- (7) MEM_ACT_W -- --- DP(0): RXSD (inverted to signal activity) --- DP(1): RTS_N (shows rx back preasure) --- DP(2): TXSD (inverted to signal activity) --- DP(3): CTS_N (shows tx back preasure) +-- DP(3): not SER_MONI.txok (shows tx back preasure) +-- DP(2): SER_MONI.txact (shows tx activity) +-- DP(1): not SER_MONI.rxok (shows rx back preasure) +-- DP(0): SER_MONI.rxact (shows rx activity) +-- library ieee; use ieee.std_logic_1164.all; @@ -121,6 +126,7 @@ use work.slvtypes.all; use work.xlib.all; use work.genlib.all; +use work.serport.all; use work.rblib.all; use work.rlinklib.all; use work.bpgenlib.all; @@ -180,6 +186,8 @@ signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv3 := (others=>'0'); + signal SER_MONI : serport_moni_type := serport_moni_init; + signal RB_MREQ : rb_mreq_type := rb_mreq_init; signal RB_SRES : rb_sres_type := rb_sres_init; signal RB_SRES_CPU : rb_sres_type := rb_sres_init; @@ -309,14 +317,17 @@ O_SEG_N => O_SEG_N ); - RLINK : rlink_base_serport + RLINK : rlink_sp1c generic map ( - ATOWIDTH => 6, -- 64 cycles access timeout - ITOWIDTH => 6, -- 64 periods max idle timeout - IFAWIDTH => 5, -- 32 word input fifo - OFAWIDTH => 0, -- no output fifo - CDWIDTH => 13, - CDINIT => sys_conf_ser2rri_cdinit) + ATOWIDTH => 6, -- 64 cycles access timeout + ITOWIDTH => 6, -- 64 periods max idle timeout + CPREF => c_rlink_cpref, + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 13, + CDINIT => sys_conf_ser2rri_cdinit) port map ( CLK => CLK, CE_USEC => CE_USEC, @@ -323,6 +334,8 @@ CE_MSEC => CE_MSEC, CE_INT => CE_MSEC, RESET => RESET, + ENAXON => SWI(1), + ENAESC => SWI(1), RXSD => RXD, TXSD => TXD, CTS_N => CTS_N, @@ -332,7 +345,7 @@ RB_LAM => RB_LAM, RB_STAT => RB_STAT, RL_MONI => open, - RL_SER_MONI => open + SER_MONI => SER_MONI ); RB_SRES_OR : rb_sres_or_3 @@ -546,11 +559,12 @@ end generate IBD_MAXI; DSP_DAT(15 downto 0) <= DISPREG; - DSP_DP(0) <= not RXD; - DSP_DP(1) <= RTS_N; - DSP_DP(2) <= not TXD; - DSP_DP(3) <= CTS_N; + DSP_DP(3) <= not SER_MONI.txok; + DSP_DP(2) <= SER_MONI.txact; + DSP_DP(1) <= not SER_MONI.rxok; + DSP_DP(0) <= SER_MONI.rxact; + proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw) variable iled : slv8 := (others=>'0'); begin
/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom
2,6 → 2,7
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../vlib/serport/serport.vhd
../../../vlib/rbus/rblib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
16,7 → 17,7
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio_rbus.vbom
../../../vlib/rlink/rlink_base_serport.vbom
../../../vlib/rlink/rlink_sp1c.vbom
../../../vlib/rbus/rb_sres_or_3.vbom
../../../w11a/pdp11_core_rbus.vbom
../../../w11a/pdp11_core.vbom
/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.mfset
1,4 → 1,4
# $Id: sys_w11a_n3.mfset 433 2011-11-27 22:04:39Z mueller $
# $Id: sys_w11a_n3.mfset 440 2011-12-18 20:08:09Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
7,7 → 7,6
 
sys_w11a_n3\..*Output port <LOCKED> of the instance <DCM> is unconnected
sys_w11a_n3\..*Output port <BTN> of the instance <HIO> is unconnected
sys_w11a_n3\..*Output port <RL_SER_MONI_.*> of the instance <RLINK> is unconnected
sys_w11a_n3\..*Output port <RL_MONI_.*> of the instance <RLINK> is unconnected
sys_w11a_n3\..*Output port <DM_STAT_.*> of the instance <CORE> is unconnected
#
/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd
1,4 → 1,4
-- $Id: sys_w11a_n3.vhd 435 2011-12-04 20:15:25Z mueller $
-- $Id: sys_w11a_n3.vhd 440 2011-12-18 20:08:09Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
19,7 → 19,7
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_base_serport
-- vlib/rlink/rlink_sp1c
-- vlib/rri/rb_sres_or_3
-- w11a/pdp11_core_rbus
-- w11a/pdp11_core
40,10 → 40,12
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-18 440 13.1 O40d xc6slx16-2 1441 3161 96 1084 ok: LP+PC+DL+II
-- 2011-11-20 430 13.1 O40d xc6slx16-2 1412 3206 84 1063 ok: LP+PC+DL+II
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-18 440 1.0.4 use rlink_sp1c
-- 2011-12-04 435 1.0.3 increase ATOWIDTH 6->7 (saw i/o timeouts on wblks)
-- 2011-11-26 433 1.0.2 use nx_cram_(dummy|memctl_as) now
-- 2011-11-23 432 1.0.1 fixup PPCM handling
55,26 → 57,29
--
-- Usage of Nexys 3 Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port
-- 1 -> Pmod B/top RS232 port
--
-- LED(0:4): if cpugo=1 show cpu mode activity
-- LED(7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0): if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- (1) supervisor mode
-- (2) kernel mode, wait
-- (3) kernel mode, pri=0
-- (4) kernel mode, pri>0
-- if cpugo=0 shows cpurust
-- (3:0) cpurust code
-- (4) '1'
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (6) MEM_ACT_R
-- (7) MEM_ACT_W
--
-- DP(0): RXSD (inverted to signal activity)
-- DP(1): RTS_N (shows rx back preasure)
-- DP(2): TXSD (inverted to signal activity)
-- DP(3): CTS_N (shows tx back preasure)
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back preasure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
 
library ieee;
use ieee.std_logic_1164.all;
83,6 → 88,7
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serport.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
141,6 → 147,8
 
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
 
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
270,14 → 278,17
O_SEG_N => O_SEG_N
);
 
RLINK : rlink_base_serport
RLINK : rlink_sp1c
generic map (
ATOWIDTH => 7, -- 128 cycles access timeout
ITOWIDTH => 6, -- 64 periods max idle timeout
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 0, -- no output fifo
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit)
ATOWIDTH => 7, -- 128 cycles access timeout
ITOWIDTH => 6, -- 64 periods max idle timeout
CPREF => c_rlink_cpref,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
284,6 → 295,8
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
293,7 → 306,7
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
RL_SER_MONI => open
SER_MONI => SER_MONI
);
 
RB_SRES_OR : rb_sres_or_3
509,11 → 522,12
end generate IBD_MAXI;
DSP_DAT(15 downto 0) <= DISPREG;
DSP_DP(0) <= not RXD;
DSP_DP(1) <= RTS_N;
DSP_DP(2) <= not TXD;
DSP_DP(3) <= CTS_N;
 
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
 
proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
variable iled : slv8 := (others=>'0');
begin
/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom
2,6 → 2,7
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../vlib/serport/serport.vhd
../../../vlib/rbus/rblib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
16,7 → 17,7
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio_rbus.vbom
../../../vlib/rlink/rlink_base_serport.vbom
../../../vlib/rlink/rlink_sp1c.vbom
../../../vlib/rbus/rb_sres_or_3.vbom
../../../w11a/pdp11_core_rbus.vbom
../../../w11a/pdp11_core.vbom
/rtl/sys_gen/w11a/s3board/sys_w11a_s3.mfset
1,4 → 1,4
# $Id: sys_w11a_s3.mfset 406 2011-08-14 21:06:44Z mueller $
# $Id: sys_w11a_s3.mfset 442 2011-12-23 10:03:28Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
7,16 → 7,10
Node <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.req_boot> of sequential type is unconnected
Node <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.req_lock> of sequential type is unconnected
Node <CORE/VMBOX/R_REGS.ibcacc> of sequential type is unconnected
Node <CORE/SEQ/R_STATUS.cpuwait> of sequential type is unconnected
 
Unconnected output port 'RL_MONI' of component 'rlink_base_serport'
Unconnected output port 'RL_SER_MONI' of component 'rlink_base_serport'
Unconnected output port 'OFIFO_SIZE' of component 'rlink_base'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen'
Unconnected output port 'ACK_W' of component 's3_sram_memctl'
Unconnected output port 'ACT_R' of component 's3_sram_memctl'
Unconnected output port 'ACT_W' of component 's3_sram_memctl'
 
Input <CP_STAT.cpuwait> is never used
Input <CP_STAT.cmdbusy> is never used
37,9 → 31,6
Input <MONI.idone> is never used
Input <MONI.trace_prev> is never used
Input <DIN<\d*:\d*>> is never used
Input <RB_MREQ.din<\d*:\d*>> is never used
Input <RB_MREQ.aval> is never used
Input <RB_MREQ.re> is never used
Input <CNTL.trap_done> is never used
Input <VADDR<\d*:\d*>> is never used
 
84,8 → 75,6
Signal <DM_STAT_DP.dsrc> is assigned but never used
Signal <DM_STAT_DP.dres> is assigned but never used
Signal <DM_STAT_DP.ddst> is assigned but never used
Signal <DM_STAT_DP.psw.pri> is assigned but never used
Signal <DM_STAT_DP.psw.cmode> is assigned but never used
Signal <DM_STAT_CO.cpuhalt> is assigned but never used
Signal <DM_STAT_CO.cpugo> is assigned but never used
 
98,7 → 87,6
Signal <EI_ACK_DZ11RX> is assigned but never used
Signal <EI_ACK<\d*>> is assigned but never used
 
Signal <SIZE<\d*:\d*>> is assigned but never used
Signal <MEM_ADDR<\d*:\d*>> is assigned but never used
 
FF/Latch <R_REGS.dcf_brk_1> in Unit <ibd_iist> is equivalent
109,7 → 97,6
FF/Latch <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.dcf_brk_\d*> in Unit <sys_w11a_s3> is equivalent
 
FF/Latch <R_SSR0.inst_compl> has a constant value of 0
FF/Latch <RLINK/BASE/RL/R_REGS.attn_\d*> has a constant value
FF/Latch <CORE/SEQ/R_STATUS.intvect_8> has a constant value of 0
FF/Latch <CORE/SEQ/R_IDSTAT.res_sel_2> has a constant value of 0
 
/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd
1,4 → 1,4
-- $Id: sys_w11a_s3.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: sys_w11a_s3.vhd 442 2011-12-23 10:03:28Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
18,7 → 18,7
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio
-- vlib/rlink/rlink_base_serport
-- vlib/rlink/rlink_sp1c
-- vlib/rbus/rb_sres_or_2
-- w11a/pdp11_core_rbus
-- w11a/pdp11_core
39,6 → 39,7
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-21 442 13.1 O40d xc3s1000-4 1301 4307 270 2613 OK: LP+PC+DL+II
-- 2011-11-19 427 13.1 O40d xc3s1000-4 1322 4298 242 2616 OK: LP+PC+DL+II
-- 2010-12-30 351 12.1 M53d xc3s1000-4 1316 4291 242 2609 OK: LP+PC+DL+II
-- 2010-11-06 336 12.1 M53d xc3s1000-4 1284 4253* 242 2575 OK: LP+PC+DL+II
72,6 → 73,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-21 442 1.4.4 use rlink_sp1c; hio led usage now a for n2/n3
-- 2011-11-19 427 1.4.3 now numeric_std clean
-- 2011-07-09 391 1.4.2 use now bp_rs232_2l4l_iob
-- 2011-07-08 390 1.4.1 use now sn_humanio
122,12 → 124,30
-- w11a + rlink + serport
--
-- Usage of S3BOARD Switches, Buttons, LEDs:
-- LED(7..0):last RXDATA
--
-- DP(0): RXSD (inverted to signal activity)
-- DP(1): RTS_N (shows rx back preasure)
-- DP(2): TXSD (inverted to signal activity)
-- DP(3): CTS_N (shows tx back preasure)
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port
-- 1 -> Pmod B/top RS232 port
--
-- LED(7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0): if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (3:0) cpurust code
-- (4) '1'
--
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back preasure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
 
library ieee;
use ieee.std_logic_1164.all;
135,6 → 155,7
 
use work.slvtypes.all;
use work.genlib.all;
use work.serport.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
188,6 → 209,8
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
 
signal SER_MONI : serport_moni_type := serport_moni_init;
 
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
220,6 → 243,8
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
294,14 → 319,17
O_SEG_N => O_SEG_N
);
 
RLINK : rlink_base_serport
RLINK : rlink_sp1c
generic map (
ATOWIDTH => 6, -- 64 cycles access timeout
ITOWIDTH => 6, -- 64 periods max idle timeout
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 0, -- no output fifo
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit)
ATOWIDTH => 6, -- 64 cycles access timeout
ITOWIDTH => 6, -- 64 periods max idle timeout
CPREF => c_rlink_cpref,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
308,6 → 336,8
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
317,9 → 347,9
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
RL_SER_MONI => open
SER_MONI => SER_MONI
);
 
RB_SRES_OR : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_CPU,
450,8 → 480,8
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => open,
ACT_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR(17 downto 0),
BE => MEM_BE,
DI => MEM_DI,
509,17 → 539,41
end generate IBD_MAXI;
DSP_DAT(15 downto 0) <= DISPREG;
DSP_DP(0) <= not RXD;
DSP_DP(1) <= RTS_N;
DSP_DP(2) <= not TXD;
DSP_DP(3) <= CTS_N;
 
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
LED(0) <= CP_STAT.cpugo;
LED(1) <= CP_STAT.cpuhalt;
LED(5 downto 2) <= CP_STAT.cpurust;
LED(6) <= SWI(0) or SWI(1) or SWI(2) or SWI(3) or
SWI(4) or SWI(5) or SWI(6) or SWI(7);
LED(7) <= BTN(0) or BTN(1) or BTN(2) or BTN(3);
proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
variable iled : slv8 := (others=>'0');
begin
iled := (others=>'0');
iled(7) := MEM_ACT_W;
iled(6) := MEM_ACT_R;
iled(5) := CP_STAT.cmdbusy;
if CP_STAT.cpugo = '1' then
case DM_STAT_DP.psw.cmode is
when c_psw_kmode =>
if CP_STAT.cpuwait = '1' then
iled(2) := '1';
elsif unsigned(DM_STAT_DP.psw.pri) = 0 then
iled(3) := '1';
else
iled(4) := '1';
end if;
when c_psw_smode =>
iled(1) := '1';
when c_psw_umode =>
iled(0) := '1';
when others => null;
end case;
else
iled(4) := '1';
iled(3 downto 0) := CP_STAT.cpurust;
end if;
LED <= iled;
end process;
-- synthesis translate_off
DM_STAT_SY.emmreq <= EM_MREQ;
536,6 → 590,6
DM_STAT_CO => DM_STAT_CO,
DM_STAT_SY => DM_STAT_SY
);
 
-- synthesis translate_on
end syn;
/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom
1,6 → 1,7
# libs
../../../vlib/slvtypes.vhd
../../../vlib/genlib/genlib.vhd
../../../vlib/serport/serport.vhd
../../../vlib/rbus/rblib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
13,7 → 14,7
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio.vbom
../../../vlib/rlink/rlink_base_serport.vbom
../../../vlib/rlink/rlink_sp1c.vbom
../../../vlib/rbus/rb_sres_or_2.vbom
../../../w11a/pdp11_core_rbus.vbom
../../../w11a/pdp11_core.vbom
/rtl/sys_gen/tst_snhumanio/nexys3/.cvsignore
1,4 → 1,5
_impactbatch.log
sys_tst_snhumanio_n3.ucf
*.dep_ucf_cpp
_impact*
*.svf
/rtl/sys_gen/tst_snhumanio/nexys3
rtl/sys_gen/tst_snhumanio/nexys3 Property changes : Modified: svn:ignore ## -33,4 +33,5 ## _impactbatch.log sys_tst_snhumanio_n3.ucf *.dep_ucf_cpp +_impact* *.svf Index: rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vhd =================================================================== --- rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vhd (revision 15) +++ rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vhd (revision 16) @@ -1,4 +1,4 @@ --- $Id: sys_tst_snhumanio_atlys.vhd 414 2011-10-11 19:38:12Z mueller $ +-- $Id: sys_tst_snhumanio_atlys.vhd 439 2011-12-16 21:56:04Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -46,7 +46,7 @@ -- ---------------------------------------------------------------------------- entity sys_tst_snhumanio_atlys is -- top level - -- implements xxx_aif + -- implements atlys_aif port ( I_CLK100 : in slbit; -- 100 MHz clock -- O_CLKSYS : out slbit; -- DCM derived system clock
/rtl/sys_gen/tst_serloop/tst_serloop.vbom
0,0 → 1,7
# libs
../../vlib/slvtypes.vhd
../../vlib/serport/serport.vhd
tst_serlooplib.vhd
# components
# design
tst_serloop.vhd
/rtl/sys_gen/tst_serloop/tst_serlooplib.vhd
0,0 → 1,111
-- $Id: tst_serlooplib.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: tst_serlooplib
-- Description: Definitions for tst_serloop records and helpers
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-10 438 1.0.2 add rxui(cnt|dat) fields in hio_stat_type
-- 2011-12-09 437 1.0.1 rename serport stat->moni port
-- 2011-10-14 416 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.serport.all;
 
package tst_serlooplib is
 
constant c_mode_idle : slv2 := "00"; -- mode: idle (no tx activity)
constant c_mode_rxblast : slv2 := "01"; -- mode: rxblast (check rx activity)
constant c_mode_txblast : slv2 := "10"; -- mode: txblast (saturate tx)
constant c_mode_loop : slv2 := "11"; -- mode: loop (rx->tx loop-back)
 
type hio_cntl_type is record -- humanio controls
mode : slv2; -- mode (idle,(tx|tx)blast,loop)
enaxon : slbit; -- enable xon/xoff handling
enaesc : slbit; -- enable xon/xoff escaping
enathrottle : slbit; -- enable 1 msec tx throttling
enaftdi : slbit; -- enable ftdi flush handling
end record hio_cntl_type;
 
constant hio_cntl_init : hio_cntl_type := (
c_mode_idle, -- mode
'0','0','0','0' -- enaxon,enaesc,enathrottle,enaftdi
);
 
type hio_stat_type is record -- humanio status
rxfecnt : slv16; -- rx frame error counter
rxoecnt : slv16; -- rx overrun error counter
rxsecnt : slv16; -- rx sequence error counter
rxcnt : slv32; -- rx char counter
txcnt : slv32; -- tx char counter
rxuicnt : slv8; -- rx unsolicited input counter
rxuidat : slv8; -- rx unsolicited input data
rxokcnt : slv16; -- rxok 1->0 transition counter
txokcnt : slv16; -- txok 1->0 transition counter
end record hio_stat_type;
 
constant hio_stat_init : hio_stat_type := (
(others=>'0'), -- rxfecnt
(others=>'0'), -- rxoecnt
(others=>'0'), -- rxsecnt
(others=>'0'), -- rxcnt
(others=>'0'), -- txcnt
(others=>'0'), -- rxuicnt
(others=>'0'), -- rxuidat
(others=>'0'), -- rxokcnt
(others=>'0') -- txokcnt
);
 
-- -------------------------------------
component tst_serloop is -- tester for serport components
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
HIO_CNTL : in hio_cntl_type; -- humanio controls
HIO_STAT : out hio_stat_type; -- humanio status
SER_MONI : in serport_moni_type; -- serport monitor
RXDATA : in slv8; -- receiver data out
RXVAL : in slbit; -- receiver data valid
RXHOLD : out slbit; -- receiver data hold
TXDATA : out slv8; -- transmit data in
TXENA : out slbit; -- transmit data enable
TXBUSY : in slbit -- transmit busy
);
end component;
 
component tst_serloop_hiomap is -- default human I/O mapper
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
HIO_CNTL : out hio_cntl_type; -- tester controls from hio
HIO_STAT : in hio_stat_type; -- tester status to display by hio
SER_MONI : in serport_moni_type; -- serport monitor to display by hio
SWI : in slv8; -- switch settings
BTN : in slv4; -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end component;
 
end package tst_serlooplib;
/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vhd
0,0 → 1,565
-- $Id: tb_tst_serloop.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop - sim
-- Description: Generic test bench for sys_tst_serloop_xx
--
-- Dependencies: vlib/serport/serport_uart_rxtx
-- vlib/serport/serport_xontx
--
-- To test: sys_tst_serloop_xx
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 425 1.0 Initial version
-- 2011-11-06 420 0.5 First draft
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.simlib.all;
use work.serport.all;
 
entity tb_tst_serloop is
port (
CLKS : in slbit; -- clock for serport
CLKH : in slbit; -- clock for humanio
CLK_STOP : out slbit; -- clock stop
P0_RXD : out slbit; -- port 0 receive data (board view)
P0_TXD : in slbit; -- port 0 transmit data (board view)
P0_RTS_N : in slbit; -- port 0 rts_n
P0_CTS_N : out slbit; -- port 0 cts_n
P1_RXD : out slbit; -- port 1 receive data (board view)
P1_TXD : in slbit; -- port 1 transmit data (board view)
P1_RTS_N : in slbit; -- port 1 rts_n
P1_CTS_N : out slbit; -- port 1 cts_n
SWI : out slv8; -- hio switches
BTN : out slv4 -- hio buttons
);
end tb_tst_serloop;
 
architecture sim of tb_tst_serloop is
signal CLK_STOP_L : slbit := '0';
signal CLK_CYCLE : slv31 := (others=>'0');
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
 
signal CLKDIV : slv13 := (others=>'0');
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
 
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal ACTPORT : slbit := '0';
signal BREAK : slbit := '0';
signal CTS_CYCLE : integer := 0;
signal CTS_FRACT : integer := 0;
signal XON_CYCLE : integer := 0;
signal XON_FRACT : integer := 0;
 
signal S2M_ACTIVE : slbit := '0';
signal S2M_SIZE : integer := 0;
signal S2M_ENAESC : slbit := '0';
signal S2M_ENAXON : slbit := '0';
signal M2S_XONSEEN : slbit := '0';
signal M2S_XOFFSEEN : slbit := '0';
 
signal R_XONRXOK : slbit := '1';
signal R_XONTXOK : slbit := '1';
 
begin
 
proc_cycle: process (CLKS)
begin
if rising_edge(CLKS) then
CLK_CYCLE <= slv(unsigned(CLK_CYCLE) + 1);
end if;
end process proc_cycle;
 
UART : serport_uart_rxtx
generic map (
CDWIDTH => 13)
port map (
CLK => CLKS,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY
);
 
XONTX : serport_xontx
port map (
CLK => CLKS,
RESET => UART_RESET,
ENAXON => S2M_ENAXON,
ENAESC => S2M_ENAESC,
UART_TXDATA => UART_TXDATA,
UART_TXENA => UART_TXENA,
UART_TXBUSY => UART_TXBUSY,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXOK => R_XONRXOK,
TXOK => R_XONTXOK
);
proc_port_mux: process (ACTPORT, BREAK, UART_TXD, CTS_N,
P0_TXD, P0_RTS_N, P1_TXD, P1_RTS_N)
variable eff_txd : slbit := '0';
begin
 
if BREAK = '0' then -- if no break active
eff_txd := UART_TXD; -- send uart
else -- otherwise
eff_txd := '0'; -- force '0'
end if;
if ACTPORT = '0' then -- use port 0
P0_RXD <= eff_txd; -- write port 0 inputs
P0_CTS_N <= CTS_N;
UART_RXD <= P0_TXD; -- get port 0 outputs
RTS_N <= P0_RTS_N;
P1_RXD <= '1'; -- port 1 inputs to idle state
P1_CTS_N <= '0';
else -- use port 1
P1_RXD <= eff_txd; -- write port 1 inputs
P1_CTS_N <= CTS_N;
UART_RXD <= P1_TXD; -- get port 1 outputs
RTS_N <= P1_RTS_N;
P0_RXD <= '1'; -- port 0 inputs to idle state
P0_CTS_N <= '0';
end if;
end process proc_port_mux;
 
proc_cts: process(CLKS)
variable cts_timer : integer := 0;
begin
if rising_edge(CLKS) then
if CTS_CYCLE = 0 then -- if cts throttle off
CTS_N <= '0'; -- cts permanently asserted
 
else -- otherwise determine throttling
 
if cts_timer>0 and cts_timer<CTS_CYCLE then -- unless beyond ends
cts_timer := cts_timer - 1; -- decrement
else
cts_timer := CTS_CYCLE-1; -- otherwise reload
end if;
 
if cts_timer < cts_fract then -- if in lower 'fract' counts
CTS_N <= '1'; -- throttle: deassert CTS
else -- otherwise
CTS_N <= '0'; -- let go: assert CTS
end if;
 
end if;
end if;
 
end process proc_cts;
proc_xonrxok: process(CLKS)
variable xon_timer : integer := 0;
begin
if rising_edge(CLKS) then
if XON_CYCLE = 0 then -- if xon throttle off
R_XONRXOK <= '1'; -- xonrxok permanently asserted
 
else -- otherwise determine throttling
 
if xon_timer>0 and xon_timer<XON_CYCLE then -- unless beyond ends
xon_timer := xon_timer - 1; -- decrement
else
xon_timer := XON_CYCLE-1; -- otherwise reload
end if;
 
if xon_timer < xon_fract then -- if in lower 'fract' counts
R_XONRXOK <= '0'; -- throttle: deassert xonrxok
else -- otherwise
R_XONRXOK <= '1'; -- let go: assert xonrxok
end if;
 
end if;
end if;
end process proc_xonrxok;
proc_xontxok: process(CLKS)
begin
if rising_edge(CLKS) then
if M2S_XONSEEN = '1' then
R_XONTXOK <= '1';
elsif M2S_XOFFSEEN = '1' then
R_XONTXOK <= '0';
end if;
end if;
end process proc_xontxok;
proc_stim: process
file fstim : text open read_mode is "tb_tst_serloop_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable iactport : slbit := '0';
variable iswi : slv8 := (others=>'0');
variable btn_num : integer := 0;
variable i_cycle : integer := 0;
variable i_fract : integer := 0;
variable nbyte : integer := 0;
variable enaesc : slbit := '0';
variable enaxon : slbit := '0';
variable bcnt : integer := 0;
variable itxdata : slv8 := (others=>'0');
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
 
procedure waitclk(ncyc : in integer) is
begin
for i in 1 to ncyc loop
wait until rising_edge(CLKS);
end loop; -- i
end procedure waitclk;
 
begin
 
-- initialize some top level out signals
SWI <= (others=>'0');
BTN <= (others=>'0');
wait until rising_edge(CLKS);
 
file_loop: while not endfile(fstim) loop
 
readline (fstim, iline);
 
readcomment(iline, ok);
next file_loop when ok;
 
readword(iline, dname, ok);
if ok then
case dname is
when "wait " => -- wait
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": wait ");
write(oline, idelta, right, 5);
writeline(output, oline);
waitclk(idelta);
 
when "port " => -- switch rs232 port
read_ea(iline, iactport);
ACTPORT <= iactport;
writetimestamp(oline, CLK_CYCLE, ": port ");
write(oline, iactport, right, 5);
writeline(output, oline);
when "cts " => -- setup cts throttling
read_ea(iline, i_cycle);
read_ea(iline, i_fract);
CTS_CYCLE <= i_cycle;
CTS_FRACT <= i_fract;
writetimestamp(oline, CLK_CYCLE, ": cts ");
write(oline, i_cycle, right, 5);
write(oline, i_fract, right, 5);
writeline(output, oline);
when "xon " => -- setup xon throttling
read_ea(iline, i_cycle);
read_ea(iline, i_fract);
XON_CYCLE <= i_cycle;
XON_FRACT <= i_fract;
writetimestamp(oline, CLK_CYCLE, ": cts ");
write(oline, i_cycle, right, 5);
write(oline, i_fract, right, 5);
writeline(output, oline);
when "swi " => -- new SWI settings
read_ea(iline, iswi);
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": swi ");
write(oline, iswi, right, 10);
write(oline, idelta, right, 5);
writeline(output, oline);
wait until rising_edge(CLKH);
SWI <= iswi;
wait until rising_edge(CLKS);
waitclk(idelta);
when "btn " => -- BTN push (3 cyc down + 3 cyc wait)
read_ea(iline, btn_num);
read_ea(iline, idelta);
if btn_num>=0 and btn_num<=3 then
writetimestamp(oline, CLK_CYCLE, ": btn ");
write(oline, btn_num, right, 5);
write(oline, idelta, right, 5);
writeline(output, oline);
wait until rising_edge(CLKH);
BTN(btn_num) <= '1'; -- 3 cycle BTN pulse
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
BTN(btn_num) <= '0';
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKS);
waitclk(idelta);
else
write(oline, string'("!! btn: btn number out of range"));
writeline(output, oline);
end if;
when "expect" => -- expect n bytes data
read_ea(iline, nbyte);
read_ea(iline, enaesc);
read_ea(iline, enaxon);
writetimestamp(oline, CLK_CYCLE, ": expect");
write(oline, nbyte, right, 5);
write(oline, enaesc, right, 3);
write(oline, enaxon, right, 3);
writeline(output, oline);
 
if nbyte > 0 then
S2M_ACTIVE <= '1';
S2M_SIZE <= nbyte;
else
S2M_ACTIVE <= '0';
end if;
S2M_ENAESC <= enaesc;
S2M_ENAXON <= enaxon;
wait until rising_edge(CLKS);
 
when "send " => -- send n bytes data
read_ea(iline, nbyte);
read_ea(iline, enaesc);
read_ea(iline, enaxon);
writetimestamp(oline, CLK_CYCLE, ": send ");
write(oline, nbyte, right, 5);
write(oline, enaesc, right, 3);
write(oline, enaxon, right, 3);
writeline(output, oline);
bcnt := 0;
itxdata := (others=>'0');
wait until falling_edge(CLKS);
while bcnt < nbyte loop
while TXBUSY='1' or RTS_N='1' loop
wait until falling_edge(CLKS);
end loop;
 
TXDATA <= itxdata;
itxdata := slv(unsigned(itxdata) + 1);
bcnt := bcnt + 1;
TXENA <= '1';
wait until falling_edge(CLKS);
TXENA <= '0';
wait until falling_edge(CLKS);
end loop;
while TXBUSY='1' or RTS_N='1' loop -- wait till last char send...
wait until falling_edge(CLKS);
end loop;
wait until rising_edge(CLKS);
when "break " => -- send a break for n cycles
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": break ");
write(oline, idelta, right, 5);
writeline(output, oline);
-- send break for n cycles
BREAK <= '1';
waitclk(idelta);
BREAK <= '0';
-- wait for 3 bit cell width
waitclk(3*to_integer(unsigned(CLKDIV)+1));
-- send 'sync' character
wait until falling_edge(CLKS);
TXDATA <= "10000000";
TXENA <= '1';
wait until falling_edge(CLKS);
TXENA <= '0';
wait until rising_edge(CLKS);
when "clkdiv" => -- set new clock divider
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": clkdiv");
write(oline, idelta, right, 5);
writeline(output, oline);
CLKDIV <= slv(to_unsigned(idelta, CLKDIV'length));
UART_RESET <= '1';
wait until rising_edge(CLKS);
UART_RESET <= '0';
 
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
 
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop
 
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
 
-- extra wait for at least two character times (20 bit times)
-- to allow tx and rx of the last character
waitclk(20*(to_integer(unsigned(CLKDIV))+1));
 
CLK_STOP_L <= '1';
 
wait for 500 ns; -- allows dcm's to stop
 
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
 
end process proc_stim;
 
CLK_STOP <= CLK_STOP_L;
proc_moni: process
variable oline : line;
variable dclk : integer := 0;
variable active_1 : slbit := '0';
variable irxdata : slv8 := (others=>'0');
variable irxeff : slv8 := (others=>'0');
variable irxval : slbit := '0';
variable doesc : slbit := '0';
variable bcnt : integer := 0;
variable xseen : slbit := '0';
begin
 
loop
wait until falling_edge(CLKS);
 
M2S_XONSEEN <= '0';
M2S_XOFFSEEN <= '0';
 
if S2M_ACTIVE='1' and active_1='0' then -- start expect message
irxdata := (others=>'0');
bcnt := 0;
end if;
 
if S2M_ACTIVE='0' and active_1='1' then -- end expect message
if bcnt = S2M_SIZE then
writetimestamp(oline, CLK_CYCLE, ": OK: message seen");
else
writetimestamp(oline, CLK_CYCLE, ": FAIL: missing chars, seen=");
write(oline, bcnt, right, 5);
write(oline, string'(" expect="));
write(oline, S2M_SIZE, right, 5);
end if;
writeline(output, oline);
end if;
 
active_1 := S2M_ACTIVE;
if RXVAL = '1' then
writetimestamp(oline, CLK_CYCLE, ": char: ");
write(oline, RXDATA, right, 10);
write(oline, string'(" ("));
writeoct(oline, RXDATA, right, 3);
write(oline, string'(") dt="));
write(oline, dclk, right, 4);
 
irxeff := RXDATA;
irxval := '1';
if doesc = '1' then
irxeff := not RXDATA;
irxval := '1';
doesc := '0';
write(oline, string'(" eff="));
write(oline, irxeff, right, 10);
write(oline, string'(" ("));
writeoct(oline, irxeff, right, 3);
write(oline, string'(")"));
elsif S2M_ENAESC='1' and RXDATA=c_serport_xesc then
doesc := '1';
irxval := '0';
write(oline, string'(" XESC seen"));
end if;
 
xseen := '0';
if S2M_ENAXON = '1' then
if RXDATA = c_serport_xon then
write(oline, string'(" XON seen"));
M2S_XONSEEN <= '1';
xseen := '1';
elsif RXDATA = c_serport_xoff then
write(oline, string'(" XOFF seen"));
M2S_XOFFSEEN <= '1';
xseen := '1';
end if;
end if;
if S2M_ACTIVE='1' and irxval='1' and xseen='0' then
if irxeff = irxdata then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL: expect="));
write(oline, irxdata, right, 10);
end if;
irxdata := slv(unsigned(irxdata) + 1);
bcnt := bcnt + 1;
end if;
writeline(output, oline);
dclk := 0;
 
end if;
 
if RXERR = '1' then
writetimestamp(oline, CLK_CYCLE, ": FAIL: RXERR='1'");
writeline(output, oline);
end if;
dclk := dclk + 1;
end loop;
end process proc_moni;
 
end sim;
/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vbom
0,0 → 1,9
# libs
../../../vlib/slvtypes.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/serport/serport.vhd
# components
../../../vlib/serport/serport_uart_rxtx.vbom
../../../vlib/serport/serport_xontx.vbom
# design
tb_tst_serloop.vhd
/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop_stim.dat
0,0 → 1,124
# $Id: tb_tst_serloop_stim.dat 441 2011-12-20 17:01:16Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-11-06 420 1.0 Initial version
#
C ------------------------------------------------
C try SWI settings
# only the 4 LBS (disp and enable control)
# don't touch the 2 mode settings here !!
#
wait 10
#
swi 10000000 2
swi 01000000 2
swi 00100000 2
swi 00010000 2
swi 00000000 2
wait 2
#
C ------------------------------------------------
C loop-back message with 16 bytes on port 0
#
port 0
swi 00000000 2
btn 0 10
#
# mode=11(loop);
swi 00000110 2
btn 1 10
#
expect 16 0 0
send 16 0 0
wait 100
expect 0 0 0
C ------------------------------------------------
C loop-back message with 16 bytes on port 1
#
port 1
swi 00000001 2
btn 0 10
#
# mode=11(loop);port=1
swi 00000111 2
btn 1 10
#
expect 16 0 0
send 16 0 0
wait 100
expect 0 0 0
#
C ------------------------------------------------
C loop-back message with 32 bytes escaped on port 0
#
port 0
swi 00000000 2
btn 0 10
#
# enaesc=1; mode=11(loop)
swi 00100110 2
btn 1 10
#
expect 32 1 0
send 32 1 0
wait 100
expect 0 0 0
#
C ------------------------------------------------
C loop-back message with 256 bytes escaped on port 1; cts throttle
#
port 1
swi 00000001 2
btn 0 10
#
# enaesc=1; mode=11(loop); port=1
swi 00100111 2
btn 1 10
#
cts 200 100
expect 256 1 0
send 256 1 0
wait 1500
expect 0 0 0
cts 0 0
#
C ------------------------------------------------
C loop-back message with 256 bytes escaped on port 0; xon throttle
#
port 0
swi 00000000 2
btn 0 10
#
# enaesc=1;enaxon=1; mode=11(loop); port=0
swi 00110110 2
btn 1 10
#
xon 200 100
expect 256 1 1
send 256 1 1
wait 1500
expect 0 0 0
xon 0 0
C ------------------------------------------------
C loop-back message with 256 bytes escaped on port 1; xon throttle
#
port 1
swi 00000001 2
btn 0 10
#
# enaesc=1;enaxon=1; mode=11(loop); port=1
swi 00110111 2
btn 1 10
#
xon 200 100
expect 256 1 1
send 256 1 1
wait 1500
expect 0 0 0
xon 0 0
#
C ------------------------------------------------
C cool down
wait 200
 
/rtl/sys_gen/tst_serloop/tb
rtl/sys_gen/tst_serloop/tb Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: rtl/sys_gen/tst_serloop/tst_serlooplib.vbom =================================================================== --- rtl/sys_gen/tst_serloop/tst_serlooplib.vbom (nonexistent) +++ rtl/sys_gen/tst_serloop/tst_serlooplib.vbom (revision 16) @@ -0,0 +1,3 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/serport/serport.vhd Index: rtl/sys_gen/tst_serloop/nexys2/sys_conf1.vhd =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/sys_conf1.vhd (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/sys_conf1.vhd (revision 16) @@ -0,0 +1,37 @@ +-- $Id: sys_conf1.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop1_n2 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-16 439 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkdiv_usecdiv : integer := 50; -- default usec + constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + constant sys_conf_uart_cdinit : integer := 434-1; -- 50000000/115200 + +end package sys_conf; Index: rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vhd =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vhd (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vhd (revision 16) @@ -0,0 +1,140 @@ +-- $Id: tb_tst_serloop1_n2.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_serloop1_n2 - sim +-- Description: Test bench for sys_tst_serloop1_n2 +-- +-- Dependencies: simlib/simclk +-- sys_tst_serloop2_n2 [UUT] +-- tb/tb_tst_serloop +-- +-- To test: sys_tst_serloop1_n2 +-- +-- Target Devices: generic +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-16 439 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.simlib.all; + +entity tb_tst_serloop1_n2 is +end tb_tst_serloop1_n2; + +architecture sim of tb_tst_serloop1_n2 is + + signal CLK50 : slbit := '0'; + signal CLK_STOP : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv8 := (others=>'0'); + signal I_BTN : slv4 := (others=>'0'); + + signal O_FUSP_RTS_N : slbit := '0'; + signal I_FUSP_CTS_N : slbit := '0'; + signal I_FUSP_RXD : slbit := '1'; + signal O_FUSP_TXD : slbit := '1'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '1'; + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + + signal FUSP_RTS_N : slbit := '0'; + signal FUSP_CTS_N : slbit := '0'; + signal FUSP_RXD : slbit := '1'; + signal FUSP_TXD : slbit := '1'; + + constant clock_period : time := 20 ns; + constant clock_offset : time := 200 ns; + constant delay_time : time := 2 ns; + +begin + + SYSCLK : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK50, + CLK_CYCLE => open, + CLK_STOP => CLK_STOP + ); + + UUT : entity work.sys_tst_serloop1_n2 + port map ( + I_CLK50 => CLK50, + O_CLKSYS => open, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => open, + O_ANO_N => open, + O_SEG_N => open, + O_MEM_CE_N => open, + O_MEM_BE_N => open, + O_MEM_WE_N => open, + O_MEM_OE_N => open, + O_MEM_ADV_N => open, + O_MEM_CLK => open, + O_MEM_CRE => open, + I_MEM_WAIT => '0', + O_MEM_ADDR => open, + IO_MEM_DATA => open, + O_FLA_CE_N => open, + O_FUSP_RTS_N => O_FUSP_RTS_N, + I_FUSP_CTS_N => I_FUSP_CTS_N, + I_FUSP_RXD => I_FUSP_RXD, + O_FUSP_TXD => O_FUSP_TXD + ); + + GENTB : entity work.tb_tst_serloop + port map ( + CLKS => CLK50, + CLKH => CLK50, + CLK_STOP => CLK_STOP, + P0_RXD => RXD, + P0_TXD => TXD, + P0_RTS_N => '0', + P0_CTS_N => open, + P1_RXD => FUSP_RXD, + P1_TXD => FUSP_TXD, + P1_RTS_N => FUSP_RTS_N, + P1_CTS_N => FUSP_CTS_N, + SWI => SWI, + BTN => BTN + ); + + I_RXD <= RXD after delay_time; + TXD <= O_TXD after delay_time; + FUSP_RTS_N <= O_FUSP_RTS_N after delay_time; + I_FUSP_CTS_N <= FUSP_CTS_N after delay_time; + I_FUSP_RXD <= FUSP_RXD after delay_time; + FUSP_TXD <= O_FUSP_TXD after delay_time; + + I_SWI <= SWI after delay_time; + I_BTN <= BTN after delay_time; + +end sim; Index: rtl/sys_gen/tst_serloop/nexys2/tb/tbw.dat =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/tb/tbw.dat (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/tb/tbw.dat (revision 16) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 441 2011-12-20 17:01:16Z mueller $ +# +[tb_tst_serloop1_n2] +tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat +[tb_tst_serloop2_n2] +tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat Index: rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vhd =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vhd (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vhd (revision 16) @@ -0,0 +1,168 @@ +-- $Id: tb_tst_serloop2_n2.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_serloop2_n2 - sim +-- Description: Test bench for sys_tst_serloop2_n2 +-- +-- Dependencies: simlib/simclk +-- vlib/xlib/dcm_sfs +-- sys_tst_serloop2_n2 [UUT] +-- tb/tb_tst_serloop +-- +-- To test: sys_tst_serloop2_n2 +-- +-- Target Devices: generic +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage +-- 2011-11-17 426 1.0.1 use dcm_sfs now +-- 2011-11-13 424 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.simlib.all; + +entity tb_tst_serloop2_n2 is +end tb_tst_serloop2_n2; + +architecture sim of tb_tst_serloop2_n2 is + + signal CLK50 : slbit := '0'; + signal CLK_STOP : slbit := '0'; + + signal CLKS : slbit := '0'; + signal CLKH : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv8 := (others=>'0'); + signal I_BTN : slv4 := (others=>'0'); + + signal O_FUSP_RTS_N : slbit := '0'; + signal I_FUSP_CTS_N : slbit := '0'; + signal I_FUSP_RXD : slbit := '1'; + signal O_FUSP_TXD : slbit := '1'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '1'; + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + + signal FUSP_RTS_N : slbit := '0'; + signal FUSP_CTS_N : slbit := '0'; + signal FUSP_RXD : slbit := '1'; + signal FUSP_TXD : slbit := '1'; + + constant clock_period : time := 20 ns; + constant clock_offset : time := 200 ns; + constant delay_time : time := 2 ns; + +begin + + SYSCLK : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK50, + CLK_CYCLE => open, + CLK_STOP => CLK_STOP + ); + + DCM_S : dcm_sfs + generic map ( + CLKFX_DIVIDE => 5, + CLKFX_MULTIPLY => 6, + CLKIN_PERIOD => 20.0) + port map ( + CLKIN => CLK50, + CLKFX => CLKS, + LOCKED => open + ); + + DCM_H : dcm_sfs + generic map ( + CLKFX_DIVIDE => 2, + CLKFX_MULTIPLY => 4, + CLKIN_PERIOD => 20.0) + port map ( + CLKIN => CLK50, + CLKFX => CLKH, + LOCKED => open + ); + + UUT : entity work.sys_tst_serloop2_n2 + port map ( + I_CLK50 => CLK50, + O_CLKSYS => open, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => open, + O_ANO_N => open, + O_SEG_N => open, + O_MEM_CE_N => open, + O_MEM_BE_N => open, + O_MEM_WE_N => open, + O_MEM_OE_N => open, + O_MEM_ADV_N => open, + O_MEM_CLK => open, + O_MEM_CRE => open, + I_MEM_WAIT => '0', + O_MEM_ADDR => open, + IO_MEM_DATA => open, + O_FLA_CE_N => open, + O_FUSP_RTS_N => O_FUSP_RTS_N, + I_FUSP_CTS_N => I_FUSP_CTS_N, + I_FUSP_RXD => I_FUSP_RXD, + O_FUSP_TXD => O_FUSP_TXD + ); + + GENTB : entity work.tb_tst_serloop + port map ( + CLKS => CLKS, + CLKH => CLKH, + CLK_STOP => CLK_STOP, + P0_RXD => RXD, + P0_TXD => TXD, + P0_RTS_N => '0', + P0_CTS_N => open, + P1_RXD => FUSP_RXD, + P1_TXD => FUSP_TXD, + P1_RTS_N => FUSP_RTS_N, + P1_CTS_N => FUSP_CTS_N, + SWI => SWI, + BTN => BTN + ); + + I_RXD <= RXD after delay_time; + TXD <= O_TXD after delay_time; + FUSP_RTS_N <= O_FUSP_RTS_N after delay_time; + I_FUSP_CTS_N <= FUSP_CTS_N after delay_time; + I_FUSP_RXD <= FUSP_RXD after delay_time; + FUSP_TXD <= O_FUSP_TXD after delay_time; + + I_SWI <= SWI after delay_time; + I_BTN <= BTN after delay_time; + +end sim; Index: rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vbom =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vbom (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vbom (revision 16) @@ -0,0 +1,11 @@ +# conf +sys_conf = sys_conf1_sim.vhd +# libs +../../../../vlib/slvtypes.vhd +../../../../vlib/simlib/simlib.vhd +# components +../../../../vlib/simlib/simclk.vbom +../sys_tst_serloop1_n2.vbom +../../tb/tb_tst_serloop.vbom +# design +tb_tst_serloop1_n2.vhd Index: rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vbom =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vbom (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vbom (revision 16) @@ -0,0 +1,13 @@ +# conf +sys_conf = sys_conf2_sim.vhd +# libs +../../../../vlib/slvtypes.vhd +../../../../vlib/xlib/xlib.vhd +../../../../vlib/simlib/simlib.vhd +# components +../../../../vlib/simlib/simclk.vbom +../../../../vlib/xlib/dcm_sfs_gsim.vbom +../sys_tst_serloop2_n2.vbom +../../tb/tb_tst_serloop.vbom +# design +tb_tst_serloop2_n2.vhd Index: rtl/sys_gen/tst_serloop/nexys2/tb/sys_tst_serloop1_n2.ucf_cpp =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/tb/sys_tst_serloop1_n2.ucf_cpp (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/tb/sys_tst_serloop1_n2.ucf_cpp (revision 16) @@ -0,0 +1 @@ +link ../sys_tst_serloop1_n2.ucf_cpp \ No newline at end of file
rtl/sys_gen/tst_serloop/nexys2/tb/sys_tst_serloop1_n2.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: rtl/sys_gen/tst_serloop/nexys2/tb/sys_tst_serloop2_n2.ucf_cpp =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/tb/sys_tst_serloop2_n2.ucf_cpp (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/tb/sys_tst_serloop2_n2.ucf_cpp (revision 16) @@ -0,0 +1 @@ +link ../sys_tst_serloop2_n2.ucf_cpp \ No newline at end of file
rtl/sys_gen/tst_serloop/nexys2/tb/sys_tst_serloop2_n2.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: rtl/sys_gen/tst_serloop/nexys2/tb/sys_conf1_sim.vhd =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/tb/sys_conf1_sim.vhd (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/tb/sys_conf1_sim.vhd (revision 16) @@ -0,0 +1,43 @@ +-- $Id: sys_conf1_sim.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop1_n2 (for test bench) +-- +-- Dependencies: - +-- Tool versions: xst 11.4; ghdl 0.26 +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-16 439 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- in simulation a usec is shortened to 10 cycles (0.2 usec) and a msec + -- to 50 cycles (1 usec). This affects the pulse generators (usec) and + -- mainly the autobauder. A break will be detected after 128 msec periods, + -- this in simulation after 128 usec or 6400 cycles. This is compatible with + -- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles) + + constant sys_conf_clkdiv_usecdiv : integer := 10; -- default usec + constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened ! + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim + +end package sys_conf; Index: rtl/sys_gen/tst_serloop/nexys2/tb/sys_conf2_sim.vhd =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/tb/sys_conf2_sim.vhd (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/tb/sys_conf2_sim.vhd (revision 16) @@ -0,0 +1,44 @@ +-- $Id: sys_conf2_sim.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop2_n2 (for test bench) +-- +-- Dependencies: - +-- Tool versions: xst 11.4; ghdl 0.26 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-13 424 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- in simulation a usec is shortened to 12 cycles (0.2 usec) and a msec + -- to 60 cycles (1 usec). This affects the pulse generators (usec) and + -- mainly the autobauder. A break will be detected after 128 msec periods, + -- this in simulation after 128 usec or 6400 cycles. This is compatible with + -- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles) + + constant sys_conf_clkudiv_usecdiv : integer := 20; -- default usec + constant sys_conf_clksdiv_usecdiv : integer := 12; -- default usec + constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened ! + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim + +end package sys_conf; Index: rtl/sys_gen/tst_serloop/nexys2/tb/.cvsignore =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/tb/.cvsignore (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/tb/.cvsignore (revision 16) @@ -0,0 +1,10 @@ +tb_tst_serloop1_n2 +tb_tst_serloop1_n2_[sft]sim +tb_tst_serloop1_n2_ISim +tb_tst_serloop1_n2_ISim_[sft]sim +tb_tst_serloop2_n2 +tb_tst_serloop2_n2_[sft]sim +tb_tst_serloop2_n2_ISim +tb_tst_serloop2_n2_ISim_[sft]sim +tb_tst_serloop_stim +*.dep_ucf_cpp Index: rtl/sys_gen/tst_serloop/nexys2/tb/Makefile =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/tb/Makefile (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/tb/Makefile (revision 16) @@ -0,0 +1,29 @@ +# $Id: Makefile 441 2011-12-20 17:01:16Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-13 424 1.0 Initial version +# +EXE_all = tb_tst_serloop1_n2 tb_tst_serloop2_n2 +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean isim_clean +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_isim.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_isim) +include $(wildcard *.o.dep_ghdl) +# Index: rtl/sys_gen/tst_serloop/nexys2/tb =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/tb (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/tb (revision 16)
rtl/sys_gen/tst_serloop/nexys2/tb Property changes : Added: svn:ignore ## -0,0 +1,42 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_tst_serloop1_n2 +tb_tst_serloop1_n2_[sft]sim +tb_tst_serloop1_n2_ISim +tb_tst_serloop1_n2_ISim_[sft]sim +tb_tst_serloop2_n2 +tb_tst_serloop2_n2_[sft]sim +tb_tst_serloop2_n2_ISim +tb_tst_serloop2_n2_ISim_[sft]sim +tb_tst_serloop_stim +*.dep_ucf_cpp Index: rtl/sys_gen/tst_serloop/nexys2/sys_conf2.vhd =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/sys_conf2.vhd (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/sys_conf2.vhd (revision 16) @@ -0,0 +1,39 @@ +-- $Id: sys_conf2.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop2_n2 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-13 424 1.0 Initial version +-- 2011-10-25 419 0.5 First draft +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkudiv_usecdiv : integer := 100; -- default usec + constant sys_conf_clksdiv_usecdiv : integer := 60; -- default usec + constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + constant sys_conf_uart_cdinit : integer := 521-1; -- 60000000/115200 + +end package sys_conf; Index: rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.ucf_cpp =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.ucf_cpp (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.ucf_cpp (revision 16) @@ -0,0 +1,19 @@ +## $Id: sys_tst_serloop1_n2.ucf_cpp 441 2011-12-20 17:01:16Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-12-16 439 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +## std board +## +#include "bplib/nexys2/nexys2_pins.ucf" +## +## Pmod B0 - RS232 +## +#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf" Index: rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.ucf_cpp =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.ucf_cpp (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.ucf_cpp (revision 16) @@ -0,0 +1,32 @@ +## $Id: sys_tst_serloop2_n2.ucf_cpp 441 2011-12-20 17:01:16Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-12-16 439 1.0.1 set maxdelay clk-clks to 12 ns +## 2011-09-17 410 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +## rules to prevent default 'cross clock' constraints for the dcm generated +## clocks CLK(100 MHz) and CLKS(60 MHz). All essential domain crossing done +## via fifo's or dedicated capture/synch flops. + +NET "CLK" TNM_NET = "CLK"; +NET "CLKS" TNM_NET = "CLKS"; +TIMESPEC "TS_CDC_CLK_CLKS" = FROM "CLK" TO "CLKS" 12 ns; +TIMESPEC "TS_CDC_CLKS_CLK" = FROM "CLKS" TO "CLK" 12 ns; + +## rule to allow that two DCMs are driven by one clock pin. +NET "I_CLK50" CLOCK_DEDICATED_ROUTE = FALSE; + +## std board +## +#include "bplib/nexys2/nexys2_pins.ucf" +## +## Pmod B0 - RS232 +## +#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf" Index: rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vhd =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vhd (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vhd (revision 16) @@ -0,0 +1,242 @@ +-- $Id: sys_tst_serloop1_n2.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_serloop1_n2 - syn +-- Description: Tester serial link for nexys2 +-- +-- Dependencies: genlib/clkdivce +-- bpgen/bp_rs232_2l4l_iob +-- bpgen/sn_humanio +-- tst_serloop_hiomap +-- vlib/serport/serport_1clock +-- tst_serloop +-- vlib/nxcramlib/nx_cram_dummy +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-12-16 439 13.1 O40d xc3s1200e-4 433 634 64 490 t 13.1 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-16 439 0.5 Initial version +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.tst_serlooplib.all; +use work.serport.all; +use work.nxcramlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_serloop1_n2 is -- top level + -- implements nexys2_fusp_aif + port ( + I_CLK50 : in slbit; -- 50 MHz clock + O_CLKSYS : out slbit; -- DCM derived system clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end sys_tst_serloop1_n2; + +architecture syn of sys_tst_serloop1_n2 is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RXD : slbit := '0'; + signal TXD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal HIO_CNTL : hio_cntl_type := hio_cntl_init; + signal HIO_STAT : hio_stat_type := hio_stat_init; + + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXHOLD : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal SER_MONI : serport_moni_type := serport_moni_init; + +begin + + CLK <= I_CLK50; + O_CLKSYS <= CLK; + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20 + MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5 + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio + generic map ( + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => '0', + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RESET <= BTN(0); -- BTN(0) will reset tester !! + + HIOMAP : tst_serloop_hiomap + port map ( + CLK => CLK, + RESET => RESET, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), -- port selection + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + SERPORT : serport_1clock + generic map ( + CDWIDTH => 15, + CDINIT => sys_conf_uart_cdinit, + RXFAWIDTH => 5, + TXFAWIDTH => 5) + port map ( + CLK => CLK, + CE_MSEC => CE_MSEC, + RESET => RESET, + ENAXON => HIO_CNTL.enaxon, + ENAESC => HIO_CNTL.enaesc, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + MONI => SER_MONI, + RXSD => RXD, + TXSD => TXD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N + ); + + TESTER : tst_serloop + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_FLA_CE_N <= '1'; -- keep Flash memory disabled + +end syn; Index: rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vhd =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vhd (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vhd (revision 16) @@ -0,0 +1,286 @@ +-- $Id: sys_tst_serloop2_n2.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_serloop2_n2 - syn +-- Description: Tester serial link for nexys2 +-- +-- Dependencies: vlib/xlib/dcm_sfs +-- genlib/clkdivce +-- bpgen/bp_rs232_2l4l_iob +-- bpgen/sn_humanio +-- tst_serloop_hiomap +-- vlib/serport/serport_2clock +-- tst_serloop +-- vlib/nxcramlib/nx_cram_dummy +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-12-16 439 13.1 O40d xc3s1200e-4 516 696 64 575 t xx.x +-- 2011-11-16 426 13.1 O40d xc3s1200e-4 494 661 64 547 t xx.x +-- 2011-11-13 425 13.1 O40d xc3s1200e-4 487 645 64 532 t xx.x +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-09 437 1.0.4 rename serport stat->moni port +-- 2011-11-26 433 1.0.3 use nx_cram_dummy now +-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage +-- 2011-11-17 426 1.0.1 use dcm_sfs now +-- 2011-11-12 423 1.0 Initial version +-- 2011-11-09 422 0.5 First draft +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.tst_serlooplib.all; +use work.serport.all; +use work.nxcramlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_serloop2_n2 is -- top level + -- implements nexys2_fusp_aif + port ( + I_CLK50 : in slbit; -- 50 MHz clock + O_CLKSYS : out slbit; -- DCM derived system clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end sys_tst_serloop2_n2; + +architecture syn of sys_tst_serloop2_n2 is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal CLKS : slbit := '0'; + signal CES_MSEC : slbit := '0'; + + signal RXD : slbit := '0'; + signal TXD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal HIO_CNTL : hio_cntl_type := hio_cntl_init; + signal HIO_STAT : hio_stat_type := hio_stat_init; + + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXHOLD : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal SER_MONI : serport_moni_type := serport_moni_init; + +begin + + DCM_U : dcm_sfs + generic map ( + CLKFX_DIVIDE => 2, + CLKFX_MULTIPLY => 4, + CLKIN_PERIOD => 20.0) + port map ( + CLKIN => I_CLK50, + CLKFX => CLK, + LOCKED => open + ); + + O_CLKSYS <= '0'; + + CLKDIV_U : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clkudiv_usecdiv, -- syn: 100 sim: 20 + MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5 + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + DCM_S : dcm_sfs + generic map ( + CLKFX_DIVIDE => 5, + CLKFX_MULTIPLY => 6, + CLKIN_PERIOD => 20.0) + port map ( + CLKIN => I_CLK50, + CLKFX => CLKS, + LOCKED => open + ); + + CLKDIV_S : clkdivce + generic map ( + CDUWIDTH => 6, + USECDIV => sys_conf_clksdiv_usecdiv, -- syn: 60 sim: 12 + MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5 + port map ( + CLK => CLKS, + CE_USEC => open, + CE_MSEC => CES_MSEC + ); + + HIO : sn_humanio + generic map ( + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => '0', + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RESET <= BTN(0); -- BTN(0) will reset tester !! + + HIOMAP : tst_serloop_hiomap + port map ( + CLK => CLK, + RESET => RESET, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLKS, + RESET => '0', + SEL => SWI(0), -- port selection + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + SERPORT : serport_2clock + generic map ( + CDWIDTH => 15, + CDINIT => sys_conf_uart_cdinit, + RXFAWIDTH => 5, + TXFAWIDTH => 5) + port map ( + CLKU => CLK, + RESET => RESET, + CLKS => CLKS, + CES_MSEC => CES_MSEC, + ENAXON => HIO_CNTL.enaxon, + ENAESC => HIO_CNTL.enaesc, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + MONI => SER_MONI, + RXSD => RXD, + TXSD => TXD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N + ); + + TESTER : tst_serloop + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_FLA_CE_N <= '1'; -- keep Flash memory disabled + +end syn; Index: rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vbom =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vbom (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vbom (revision 16) @@ -0,0 +1,19 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../tst_serlooplib.vbom +../../../vlib/serport/serport.vhd +../../../bplib/nxcramlib/nxcramlib.vhd +sys_conf : sys_conf1.vhd +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_serloop_hiomap.vbom +../../../vlib/serport/serport_1clock.vbom +../tst_serloop.vbom +../../../bplib/nxcramlib/nx_cram_dummy.vbom +# design +sys_tst_serloop1_n2.vhd +@ucf_cpp: sys_tst_serloop1_n2.ucf Index: rtl/sys_gen/tst_serloop/nexys2/Makefile =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/Makefile (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/Makefile (revision 16) @@ -0,0 +1,28 @@ +# $Id: Makefile 441 2011-12-20 17:01:16Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-09 422 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +ISE_BOARD = nexys2 +ISE_PATH = xc3s1200e-fg320-4 +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f sys_tst_serloop1_n2.ucf + rm -f sys_tst_serloop2_n2.ucf +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +# Index: rtl/sys_gen/tst_serloop/nexys2/.cvsignore =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/.cvsignore (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/.cvsignore (revision 16) @@ -0,0 +1,5 @@ +_impactbatch.log +sys_tst_serloop1_n2.ucf +sys_tst_serloop2_n2.ucf +*.dep_ucf_cpp +*.svf Index: rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vbom =================================================================== --- rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vbom (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vbom (revision 16) @@ -0,0 +1,22 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../tst_serlooplib.vbom +../../../vlib/serport/serport.vhd +../../../bplib/nxcramlib/nxcramlib.vhd +sys_conf : sys_conf2.vhd +# components +[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_serloop_hiomap.vbom +../../../vlib/serport/serport_2clock.vbom +../tst_serloop.vbom +../../../bplib/nxcramlib/nx_cram_dummy.vbom +# design +sys_tst_serloop2_n2.vhd +@ucf_cpp: sys_tst_serloop2_n2.ucf Index: rtl/sys_gen/tst_serloop/nexys2 =================================================================== --- rtl/sys_gen/tst_serloop/nexys2 (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys2 (revision 16)
rtl/sys_gen/tst_serloop/nexys2 Property changes : Added: svn:ignore ## -0,0 +1,37 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_serloop1_n2.ucf +sys_tst_serloop2_n2.ucf +*.dep_ucf_cpp +*.svf Index: rtl/sys_gen/tst_serloop/nexys3/sys_conf1.vhd =================================================================== --- rtl/sys_gen/tst_serloop/nexys3/sys_conf1.vhd (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys3/sys_conf1.vhd (revision 16) @@ -0,0 +1,37 @@ +-- $Id: sys_conf1.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop1_n3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-09 438 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkdiv_usecdiv : integer := 100; -- default usec + constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + constant sys_conf_uart_cdinit : integer := 868-1; -- 100000000/115200 + +end package sys_conf; Index: rtl/sys_gen/tst_serloop/nexys3/tb/tbw.dat =================================================================== --- rtl/sys_gen/tst_serloop/nexys3/tb/tbw.dat (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys3/tb/tbw.dat (revision 16) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 441 2011-12-20 17:01:16Z mueller $ +# +[tb_tst_serloop1_n3] +tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat +[tb_tst_serloop2_n3] +tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat Index: rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vhd =================================================================== --- rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vhd (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vhd (revision 16) @@ -0,0 +1,139 @@ +-- $Id: tb_tst_serloop1_n3.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_serloop1_n3 - sim +-- Description: Test bench for sys_tst_serloop1_n3 +-- +-- Dependencies: simlib/simclk +-- sys_tst_serloop1_n3 [UUT] +-- tb/tb_tst_serloop +-- +-- To test: sys_tst_serloop1_n3 +-- +-- Target Devices: generic +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-11 438 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.simlib.all; + +entity tb_tst_serloop1_n3 is +end tb_tst_serloop1_n3; + +architecture sim of tb_tst_serloop1_n3 is + + signal CLK100 : slbit := '0'; + signal CLK_STOP : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv8 := (others=>'0'); + signal I_BTN : slv5 := (others=>'0'); + + signal O_FUSP_RTS_N : slbit := '0'; + signal I_FUSP_CTS_N : slbit := '0'; + signal I_FUSP_RXD : slbit := '1'; + signal O_FUSP_TXD : slbit := '1'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '1'; + signal SWI : slv8 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + + signal FUSP_RTS_N : slbit := '0'; + signal FUSP_CTS_N : slbit := '0'; + signal FUSP_RXD : slbit := '1'; + signal FUSP_TXD : slbit := '1'; + + constant clock_period : time := 10 ns; + constant clock_offset : time := 200 ns; + constant delay_time : time := 2 ns; + +begin + + SYSCLK : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK100, + CLK_CYCLE => open, + CLK_STOP => CLK_STOP + ); + + UUT : entity work.sys_tst_serloop1_n3 + port map ( + I_CLK100 => CLK100, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => open, + O_ANO_N => open, + O_SEG_N => open, + O_MEM_CE_N => open, + O_MEM_BE_N => open, + O_MEM_WE_N => open, + O_MEM_OE_N => open, + O_MEM_ADV_N => open, + O_MEM_CLK => open, + O_MEM_CRE => open, + I_MEM_WAIT => '0', + O_MEM_ADDR => open, + IO_MEM_DATA => open, + O_PPCM_CE_N => open, + O_PPCM_RST_N => open, + O_FUSP_RTS_N => O_FUSP_RTS_N, + I_FUSP_CTS_N => I_FUSP_CTS_N, + I_FUSP_RXD => I_FUSP_RXD, + O_FUSP_TXD => O_FUSP_TXD + ); + + GENTB : entity work.tb_tst_serloop + port map ( + CLKS => CLK100, + CLKH => CLK100, + CLK_STOP => CLK_STOP, + P0_RXD => RXD, + P0_TXD => TXD, + P0_RTS_N => '0', + P0_CTS_N => open, + P1_RXD => FUSP_RXD, + P1_TXD => FUSP_TXD, + P1_RTS_N => FUSP_RTS_N, + P1_CTS_N => FUSP_CTS_N, + SWI => SWI, + BTN => BTN(3 downto 0) + ); + + I_RXD <= RXD after delay_time; + TXD <= O_TXD after delay_time; + FUSP_RTS_N <= O_FUSP_RTS_N after delay_time; + I_FUSP_CTS_N <= FUSP_CTS_N after delay_time; + I_FUSP_RXD <= FUSP_RXD after delay_time; + FUSP_TXD <= O_FUSP_TXD after delay_time; + + I_SWI <= SWI after delay_time; + I_BTN <= BTN after delay_time; + +end sim; Index: rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vbom =================================================================== --- rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vbom (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vbom (revision 16) @@ -0,0 +1,11 @@ +# conf +sys_conf = sys_conf1_sim.vhd +# libs +../../../../vlib/slvtypes.vhd +../../../../vlib/simlib/simlib.vhd +# components +../../../../vlib/simlib/simclk.vbom +../sys_tst_serloop1_n3.vbom +../../tb/tb_tst_serloop.vbom +# design +tb_tst_serloop1_n3.vhd Index: rtl/sys_gen/tst_serloop/nexys3/tb/sys_tst_serloop1_n3.ucf_cpp =================================================================== --- rtl/sys_gen/tst_serloop/nexys3/tb/sys_tst_serloop1_n3.ucf_cpp (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys3/tb/sys_tst_serloop1_n3.ucf_cpp (revision 16) @@ -0,0 +1 @@ +link ../sys_tst_serloop1_n3.ucf_cpp \ No newline at end of file
rtl/sys_gen/tst_serloop/nexys3/tb/sys_tst_serloop1_n3.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: rtl/sys_gen/tst_serloop/nexys3/tb/sys_conf1_sim.vhd =================================================================== --- rtl/sys_gen/tst_serloop/nexys3/tb/sys_conf1_sim.vhd (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys3/tb/sys_conf1_sim.vhd (revision 16) @@ -0,0 +1,43 @@ +-- $Id: sys_conf1_sim.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop1_n3 (for test bench) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-11 438 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- in simulation a usec is shortened to 20 cycles (0.2 usec) and a msec + -- to 100 cycles (1 usec). This affects the pulse generators (usec) and + -- mainly the autobauder. A break will be detected after 128 msec periods, + -- this in simulation after 128 usec or 6400 cycles. This is compatible with + -- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles) + + constant sys_conf_clkdiv_usecdiv : integer := 20; -- default usec + constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened ! + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim + +end package sys_conf; Index: rtl/sys_gen/tst_serloop/nexys3/tb/Makefile =================================================================== --- rtl/sys_gen/tst_serloop/nexys3/tb/Makefile (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys3/tb/Makefile (revision 16) @@ -0,0 +1,30 @@ +# $Id: Makefile 442 2011-12-23 10:03:28Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-12-11 438 1.0.1 added tb_tst_serloop1_n3 +# 2011-11-27 433 1.0 Initial version +# +EXE_all = tb_tst_serloop1_n3 +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean isim_clean +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_isim.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_isim) +include $(wildcard *.o.dep_ghdl) +# Index: rtl/sys_gen/tst_serloop/nexys3/tb/.cvsignore =================================================================== --- rtl/sys_gen/tst_serloop/nexys3/tb/.cvsignore (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys3/tb/.cvsignore (revision 16) @@ -0,0 +1,10 @@ +tb_tst_serloop1_n3 +tb_tst_serloop1_n3_[sft]sim +tb_tst_serloop1_n3_ISim +tb_tst_serloop1_n3_ISim_[sft]sim +tb_tst_serloop2_n3 +tb_tst_serloop2_n3_[sft]sim +tb_tst_serloop2_n3_ISim +tb_tst_serloop2_n3_ISim_[sft]sim +tb_tst_serloop_stim +*.dep_ucf_cpp Index: rtl/sys_gen/tst_serloop/nexys3/tb =================================================================== --- rtl/sys_gen/tst_serloop/nexys3/tb (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys3/tb (revision 16)
rtl/sys_gen/tst_serloop/nexys3/tb Property changes : Added: svn:ignore ## -0,0 +1,42 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_tst_serloop1_n3 +tb_tst_serloop1_n3_[sft]sim +tb_tst_serloop1_n3_ISim +tb_tst_serloop1_n3_ISim_[sft]sim +tb_tst_serloop2_n3 +tb_tst_serloop2_n3_[sft]sim +tb_tst_serloop2_n3_ISim +tb_tst_serloop2_n3_ISim_[sft]sim +tb_tst_serloop_stim +*.dep_ucf_cpp Index: rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.ucf_cpp =================================================================== --- rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.ucf_cpp (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.ucf_cpp (revision 16) @@ -0,0 +1,19 @@ +## $Id: sys_tst_serloop1_n3.ucf_cpp 441 2011-12-20 17:01:16Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-12-09 438 1.0 Initial version +## + +NET "I_CLK100" TNM_NET = "I_CLK100"; +TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK100"; +OFFSET = OUT 20 ns AFTER "I_CLK100"; + +## std board +## +#include "bplib/nexys3/nexys3_pins.ucf" +## +## Pmod B0 - RS232 +## +#include "bplib/nexys3/nexys3_pins_pmb0_rs232.ucf" Index: rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vhd =================================================================== --- rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vhd (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vhd (revision 16) @@ -0,0 +1,243 @@ +-- $Id: sys_tst_serloop1_n3.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_serloop1_n3 - syn +-- Description: Tester serial link for nexys3 (serport_1clock case) +-- +-- Dependencies: genlib/clkdivce +-- bpgen/bp_rs232_2l4l_iob +-- bpgen/sn_humanio +-- tst_serloop_hiomap +-- vlib/serport/serport_1clock +-- tst_serloop +-- vlib/nxcramlib/nx_cram_dummy +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-12-11 438 13.1 O40d xc6slx16-2 419 650 32 221 t 7.7 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-11 438 1.0 Initial version (derived from sys_tst_serloop_n3) +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.tst_serlooplib.all; +use work.serport.all; +use work.nxcramlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_serloop1_n3 is -- top level + -- implements nexys3_fusp_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n3 switches + I_BTN : in slv5; -- n3 buttons + O_LED : out slv8; -- n3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_PPCM_CE_N : out slbit; -- ppcm: ... + O_PPCM_RST_N : out slbit; -- ppcm: ... + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end sys_tst_serloop1_n3; + +architecture syn of sys_tst_serloop1_n3 is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RXD : slbit := '0'; + signal TXD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal HIO_CNTL : hio_cntl_type := hio_cntl_init; + signal HIO_STAT : hio_stat_type := hio_stat_init; + + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXHOLD : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal SER_MONI : serport_moni_type := serport_moni_init; + +begin + + CLK <= I_CLK100; + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 8, + USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20 + MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5 + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio + generic map ( + BWIDTH => 5, + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => '0', + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RESET <= BTN(0); -- BTN(0) will reset tester !! + + HIOMAP : tst_serloop_hiomap + port map ( + CLK => CLK, + RESET => RESET, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + SWI => SWI, + BTN => BTN(3 downto 0), + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), -- port selection + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + SERPORT : serport_1clock + generic map ( + CDWIDTH => 15, + CDINIT => sys_conf_uart_cdinit, + RXFAWIDTH => 5, + TXFAWIDTH => 5) + port map ( + CLK => CLK, + CE_MSEC => CE_MSEC, + RESET => RESET, + ENAXON => HIO_CNTL.enaxon, + ENAESC => HIO_CNTL.enaesc, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + MONI => SER_MONI, + RXSD => RXD, + TXSD => TXD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N + ); + + TESTER : tst_serloop + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled + O_PPCM_RST_N <= '1'; -- + +end syn; Index: rtl/sys_gen/tst_serloop/nexys3/.cvsignore =================================================================== --- rtl/sys_gen/tst_serloop/nexys3/.cvsignore (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys3/.cvsignore (revision 16) @@ -0,0 +1,5 @@ +_impactbatch.log +sys_tst_serloop1_n3.ucf +sys_tst_serloop2_n3.ucf +*.dep_ucf_cpp +*.svf Index: rtl/sys_gen/tst_serloop/nexys3/Makefile =================================================================== --- rtl/sys_gen/tst_serloop/nexys3/Makefile (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys3/Makefile (revision 16) @@ -0,0 +1,31 @@ +# $Id: Makefile 441 2011-12-20 17:01:16Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-27 433 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +ISE_BOARD = nexys3 +ISE_PATH = xc6slx16-csg324-2 +# +XFLOWOPT_SYN = syn_s6_speed.opt +XFLOWOPT_IMP = imp_s6_speed.opt +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f sys_tst_serloop1_n3.ucf + rm -f sys_tst_serloop2_n3.ucf +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +# Index: rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vbom =================================================================== --- rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vbom (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vbom (revision 16) @@ -0,0 +1,20 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../tst_serlooplib.vbom +../../../vlib/serport/serport.vhd +../../../bplib/nxcramlib/nxcramlib.vhd +sys_conf : sys_conf1.vhd +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_serloop_hiomap.vbom +../../../vlib/serport/serport_1clock.vbom +../tst_serloop.vbom +../../../bplib/nxcramlib/nx_cram_dummy.vbom +# design +sys_tst_serloop1_n3.vhd +@ucf_cpp: sys_tst_serloop1_n3.ucf Index: rtl/sys_gen/tst_serloop/nexys3 =================================================================== --- rtl/sys_gen/tst_serloop/nexys3 (nonexistent) +++ rtl/sys_gen/tst_serloop/nexys3 (revision 16)
rtl/sys_gen/tst_serloop/nexys3 Property changes : Added: svn:ignore ## -0,0 +1,37 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_serloop1_n3.ucf +sys_tst_serloop2_n3.ucf +*.dep_ucf_cpp +*.svf Index: rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vhd =================================================================== --- rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vhd (nonexistent) +++ rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vhd (revision 16) @@ -0,0 +1,219 @@ +-- $Id: tst_serloop_hiomap.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tst_serloop_hiomap - syn +-- Description: default human I/O mapper +-- +-- Dependencies: - +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-09 437 1.0.2 rename serport stat->moni port +-- 2011-11-16 426 1.0.1 setup leds and dps +-- 2011-11-05 420 1.0 Initial version +------------------------------------------------------------------------------ +-- +-- Usage of Switches, Buttons, LEDs: +-- +-- BTN(3): -- unused -- +-- (2): -- unused -- +-- (1): load enables from SWI(7:4) +-- SWI(7) -> ENAFTDI +-- SWI(6) -> ENATHROTTLE +-- SWI(5) -> ENAESC +-- SWI(4) -> ENAXON +-- (0): reset state [!! decoded by top level design !!] +-- +-- SWI(7:4) select display or enable pattern (when BTN(1) pressed) +-- (3) -- unused -- +-- (2:1): mode 00 idle +-- 01 rxblast +-- 10 txblast +-- 11 loop +-- SWI(0) 0 -> main board RS232 port +-- 1 -> Pmod1 RS232 port +-- +-- LED(7) enaesc +-- (6) enaxon +-- (5) rxfecnt > 0 (frame error) +-- (4) rxoecnt > 0 (overrun error) +-- (3) rxsecnt > 0 (sequence error) +-- (2) abact (shows ab activity) +-- (1) (not rxok) or (not txok) (shows back preasure) +-- (0) rxact or txact (shows activity) +-- +-- DSP data as selected by SWI(7:4) +-- 0000 -> rxfecnt +-- 0001 -> rxoecnt +-- 0010 -> rxsecnt +-- 0100 -> rxcnt.l +-- 0101 -> rxcnt.h +-- 0110 -> txcnt.l +-- 0111 -> txcnt.h +-- 1000 -> rxokcnt +-- 1001 -> txokcnt +-- 1010 -> rxuicnt,rxuidat +-- 1111 -> abclkdiv +-- +-- DP(3): not SER_MONI.txok (shows tx back preasure) +-- (2): SER_MONI.txact (shows tx activity) +-- (1): not SER_MONI.rxok (shows rx back preasure) +-- (0): SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.serport.all; +use work.tst_serlooplib.all; + +-- ---------------------------------------------------------------------------- + +entity tst_serloop_hiomap is -- default human I/O mapper + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + HIO_CNTL : out hio_cntl_type; -- tester controls from hio + HIO_STAT : in hio_stat_type; -- tester status to diaplay by hio + SER_MONI : in serport_moni_type; -- serport monitor to display by hio + SWI : in slv8; -- switch settings + BTN : in slv4; -- button settings + LED : out slv8; -- led data + DSP_DAT : out slv16; -- display data + DSP_DP : out slv4 -- display decimal points + ); +end tst_serloop_hiomap; + +architecture syn of tst_serloop_hiomap is + + type regs_type is record + enaxon : slbit; -- enable xon/xoff handling + enaesc : slbit; -- enable xon/xoff escaping + enathrottle : slbit; -- enable 1 msec tx throttling + enaftdi : slbit; -- enable ftdi flush handling + dspdat : slv16; -- display data + end record regs_type; + + constant regs_init : regs_type := ( + '0','0','0','0', -- enaxon,enaesc,enathrottle,enaftdi + (others=>'0') -- dspdat + + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + +begin + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, HIO_STAT, SER_MONI, SWI, BTN) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable icntl : hio_cntl_type := hio_cntl_init; + variable iled : slv8 := (others=>'0'); + variable idat : slv16 := (others=>'0'); + variable idp : slv4 := (others=>'0'); + + begin + + r := R_REGS; + n := R_REGS; + + icntl := hio_cntl_init; + iled := (others=>'0'); + idat := (others=>'0'); + idp := (others=>'0'); + + -- handle BTN(1) "load enables" press + + if BTN(1) = '1' then + n.enaxon := SWI(4); + n.enaesc := SWI(5); + n.enathrottle := SWI(6); + n.enaftdi := SWI(7); + end if; + + -- setup tester controls + + icntl.mode := SWI(2 downto 1); + icntl.enaxon := r.enaxon; + icntl.enaesc := r.enaesc; + icntl.enathrottle := r.enathrottle; + icntl.enaftdi := r.enaftdi; + + -- setup leds + iled(7) := icntl.enaesc; + iled(6) := icntl.enaxon; + if unsigned(HIO_STAT.rxfecnt) > 0 then iled(5) := '1'; end if; + if unsigned(HIO_STAT.rxoecnt) > 0 then iled(4) := '1'; end if; + if unsigned(HIO_STAT.rxsecnt) > 0 then iled(3) := '1'; end if; + iled(2) := SER_MONI.abact; + iled(1) := (not SER_MONI.rxok) or (not SER_MONI.txok); + iled(0) := SER_MONI.rxact or SER_MONI.txact; + + -- setup display data + + case SWI(7 downto 4) is + when "0000" => idat := HIO_STAT.rxfecnt; + when "0001" => idat := HIO_STAT.rxoecnt; + when "0010" => idat := HIO_STAT.rxsecnt; + when "0100" => idat := HIO_STAT.rxcnt(15 downto 0); + when "0101" => idat := HIO_STAT.rxcnt(31 downto 16); + when "0110" => idat := HIO_STAT.txcnt(15 downto 0); + when "0111" => idat := HIO_STAT.txcnt(31 downto 16); + when "1000" => idat := HIO_STAT.rxokcnt; + when "1001" => idat := HIO_STAT.txokcnt; + when "1010" => idat := HIO_STAT.rxuicnt & HIO_STAT.rxuidat; + when "1111" => idat := SER_MONI.abclkdiv; + when others => null; + end case; + n.dspdat := idat; + + -- setup display decimal points + + idp(3) := not SER_MONI.txok; -- tx back preasure + idp(2) := SER_MONI.txact; -- tx activity + idp(1) := not SER_MONI.rxok; -- rx back preasure + idp(0) := SER_MONI.rxact; -- rx activity + + N_REGS <= n; + + HIO_CNTL <= icntl; + LED <= iled; + DSP_DAT <= r.dspdat; + DSP_DP <= idp; + + end process proc_next; + +end syn; Index: rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vbom =================================================================== --- rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vbom (nonexistent) +++ rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vbom (revision 16) @@ -0,0 +1,7 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/serport/serport.vhd +tst_serlooplib.vbom +# components +# design +tst_serloop_hiomap.vhd Index: rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vhd =================================================================== --- rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vhd (nonexistent) +++ rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vhd (revision 16) @@ -0,0 +1,243 @@ +-- $Id: sys_tst_serloop_s3.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_serloop_s3 - syn +-- Description: Tester serial link for s3board +-- +-- Dependencies: vlib/xlib/dcm_sfs +-- genlib/clkdivce +-- bpgen/bp_rs232_2l4l_iob +-- bpgen/sn_humanio +-- tst_serloop_hiomap +-- vlib/serport/serport_1clock +-- tst_serloop +-- s3board/s3_sram_dummy +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-11-16 426 13.1 O40d xc3s1000-4 424 602 64 476 t 13.6 +-- 2011-11-13 425 13.1 O40d xc3s1000-4 421 586 64 466 t 13.6 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-09 437 1.0.2 rename serport stat->moni port +-- 2011-11-17 426 1.0.1 use dcm_sfs now +-- 2011-11-12 423 1.0 Initial version +-- 2011-10-25 419 0.5 First draft +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.tst_serlooplib.all; +use work.serport.all; +use work.s3boardlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_serloop_s3 is -- top level + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- s3 switches + I_BTN : in slv4; -- s3 buttons + O_LED : out slv8; -- s3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32; -- sram: data lines + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end sys_tst_serloop_s3; + +architecture syn of sys_tst_serloop_s3 is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RXD : slbit := '0'; + signal TXD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal HIO_CNTL : hio_cntl_type := hio_cntl_init; + signal HIO_STAT : hio_stat_type := hio_stat_init; + + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXHOLD : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal SER_MONI : serport_moni_type := serport_moni_init; + +begin + + DCM : dcm_sfs + generic map ( + CLKFX_DIVIDE => 5, + CLKFX_MULTIPLY => 6, + CLKIN_PERIOD => 20.0) + port map ( + CLKIN => I_CLK50, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 6, + USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 60 sim: 12 + MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5 + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio + generic map ( + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => '0', + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RESET <= BTN(0); -- BTN(0) will reset tester !! + + HIOMAP : tst_serloop_hiomap + port map ( + CLK => CLK, + RESET => RESET, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), -- port selection + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + SERPORT : serport_1clock + generic map ( + CDWIDTH => 15, + CDINIT => sys_conf_uart_cdinit, + RXFAWIDTH => 5, + TXFAWIDTH => 5) + port map ( + CLK => CLK, + CE_MSEC => CE_MSEC, + RESET => RESET, + ENAXON => HIO_CNTL.enaxon, + ENAESC => HIO_CNTL.enaesc, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + MONI => SER_MONI, + RXSD => RXD, + TXSD => TXD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N + ); + + TESTER : tst_serloop + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + SRAM : s3_sram_dummy -- connect SRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + +end syn; + Index: rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vbom =================================================================== --- rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vbom (nonexistent) +++ rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vbom (revision 16) @@ -0,0 +1,22 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../tst_serlooplib.vbom +../../../vlib/serport/serport.vhd +../../../bplib/s3board/s3boardlib.vbom +sys_conf : sys_conf.vhd +# components +[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3.vbom +[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_serloop_hiomap.vbom +../../../vlib/serport/serport_1clock.vbom +../tst_serloop.vbom +../../../bplib/s3board/s3_sram_dummy.vbom +# design +sys_tst_serloop_s3.vhd +@ucf_cpp: sys_tst_serloop_s3.ucf Index: rtl/sys_gen/tst_serloop/s3board/sys_conf.vhd =================================================================== --- rtl/sys_gen/tst_serloop/s3board/sys_conf.vhd (nonexistent) +++ rtl/sys_gen/tst_serloop/s3board/sys_conf.vhd (revision 16) @@ -0,0 +1,38 @@ +-- $Id: sys_conf.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop_s3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-13 424 1.0 Initial version +-- 2011-10-25 419 0.5 First draft +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkdiv_usecdiv : integer := 60; -- default usec + constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + constant sys_conf_uart_cdinit : integer := 521-1; -- 60000000/115200 + +end package sys_conf; Index: rtl/sys_gen/tst_serloop/s3board/tb/tbw.dat =================================================================== --- rtl/sys_gen/tst_serloop/s3board/tb/tbw.dat (nonexistent) +++ rtl/sys_gen/tst_serloop/s3board/tb/tbw.dat (revision 16) @@ -0,0 +1,4 @@ +# $Id: tbw.dat 441 2011-12-20 17:01:16Z mueller $ +# +[tb_tst_serloop_s3] +tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat Index: rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vhd =================================================================== --- rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vhd (nonexistent) +++ rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vhd (revision 16) @@ -0,0 +1,149 @@ +-- $Id: tb_tst_serloop_s3.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_serloop_s3 - sim +-- Description: Test bench for sys_tst_serloop_s3 +-- +-- Dependencies: simlib/simclk +-- vlib/xlib/dcm_sfs +-- sys_tst_serloop_s3 [UUT] +-- tb/tb_tst_serloop +-- +-- To test: sys_tst_serloop_s3 +-- +-- Target Devices: generic +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-17 426 1.0.1 use dcm_sfs now +-- 2011-11-06 420 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.simlib.all; + +entity tb_tst_serloop_s3 is +end tb_tst_serloop_s3; + +architecture sim of tb_tst_serloop_s3 is + + signal CLK50 : slbit := '0'; + signal CLK_STOP : slbit := '0'; + + signal CLKS : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv8 := (others=>'0'); + signal I_BTN : slv4 := (others=>'0'); + + signal O_FUSP_RTS_N : slbit := '0'; + signal I_FUSP_CTS_N : slbit := '0'; + signal I_FUSP_RXD : slbit := '1'; + signal O_FUSP_TXD : slbit := '1'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '1'; + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + + signal FUSP_RTS_N : slbit := '0'; + signal FUSP_CTS_N : slbit := '0'; + signal FUSP_RXD : slbit := '1'; + signal FUSP_TXD : slbit := '1'; + + constant clock_period : time := 20 ns; + constant clock_offset : time := 200 ns; + constant delay_time : time := 2 ns; + +begin + + SYSCLK : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK50, + CLK_CYCLE => open, + CLK_STOP => CLK_STOP + ); + + DCM_S : dcm_sfs + generic map ( + CLKFX_DIVIDE => 5, + CLKFX_MULTIPLY => 6, + CLKIN_PERIOD => 20.0) + port map ( + CLKIN => CLK50, + CLKFX => CLKS, + LOCKED => open + ); + + UUT : entity work.sys_tst_serloop_s3 + port map ( + I_CLK50 => CLK50, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => open, + O_ANO_N => open, + O_SEG_N => open, + O_MEM_CE_N => open, + O_MEM_BE_N => open, + O_MEM_WE_N => open, + O_MEM_OE_N => open, + O_MEM_ADDR => open, + IO_MEM_DATA => open, + O_FUSP_RTS_N => O_FUSP_RTS_N, + I_FUSP_CTS_N => I_FUSP_CTS_N, + I_FUSP_RXD => I_FUSP_RXD, + O_FUSP_TXD => O_FUSP_TXD + ); + + GENTB : entity work.tb_tst_serloop + port map ( + CLKS => CLKS, + CLKH => CLKS, + CLK_STOP => CLK_STOP, + P0_RXD => RXD, + P0_TXD => TXD, + P0_RTS_N => '0', + P0_CTS_N => open, + P1_RXD => FUSP_RXD, + P1_TXD => FUSP_TXD, + P1_RTS_N => FUSP_RTS_N, + P1_CTS_N => FUSP_CTS_N, + SWI => SWI, + BTN => BTN + ); + + I_RXD <= RXD after delay_time; + TXD <= O_TXD after delay_time; + FUSP_RTS_N <= O_FUSP_RTS_N after delay_time; + I_FUSP_CTS_N <= FUSP_CTS_N after delay_time; + I_FUSP_RXD <= FUSP_RXD after delay_time; + FUSP_TXD <= O_FUSP_TXD after delay_time; + + I_SWI <= SWI after delay_time; + I_BTN <= BTN after delay_time; + +end sim; Index: rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vbom =================================================================== --- rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vbom (nonexistent) +++ rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vbom (revision 16) @@ -0,0 +1,13 @@ +# conf +sys_conf = sys_conf_sim.vhd +# libs +../../../../vlib/slvtypes.vhd +../../../../vlib/xlib/xlib.vhd +../../../../vlib/simlib/simlib.vhd +# components +../../../../vlib/simlib/simclk.vbom +../../../../vlib/xlib/dcm_sfs_gsim.vbom +../sys_tst_serloop_s3.vbom +../../tb/tb_tst_serloop.vbom +# design +tb_tst_serloop_s3.vhd Index: rtl/sys_gen/tst_serloop/s3board/tb/sys_conf_sim.vhd =================================================================== --- rtl/sys_gen/tst_serloop/s3board/tb/sys_conf_sim.vhd (nonexistent) +++ rtl/sys_gen/tst_serloop/s3board/tb/sys_conf_sim.vhd (revision 16) @@ -0,0 +1,43 @@ +-- $Id: sys_conf_sim.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop_s3 (for test bench) +-- +-- Dependencies: - +-- Tool versions: xst 11.4; ghdl 0.26 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-05 420 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- in simulation a usec is shortened to 12 cycles (0.2 usec) and a msec + -- to 60 cycles (1 usec). This affects the pulse generators (usec) and + -- mainly the autobauder. A break will be detected after 128 msec periods, + -- this in simulation after 128 usec or 6400 cycles. This is compatible with + -- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles) + + constant sys_conf_clkdiv_usecdiv : integer := 12; -- shortened ! + constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened ! + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim + +end package sys_conf; Index: rtl/sys_gen/tst_serloop/s3board/tb/.cvsignore =================================================================== --- rtl/sys_gen/tst_serloop/s3board/tb/.cvsignore (nonexistent) +++ rtl/sys_gen/tst_serloop/s3board/tb/.cvsignore (revision 16) @@ -0,0 +1,6 @@ +tb_tst_serloop_s3 +tb_tst_serloop_s3_[sft]sim +tb_tst_serloop_s3_ISim +tb_tst_serloop_s3_ISim_[sft]sim +tb_tst_serloop_stim +*.dep_ucf_cpp Index: rtl/sys_gen/tst_serloop/s3board/tb/Makefile =================================================================== --- rtl/sys_gen/tst_serloop/s3board/tb/Makefile (nonexistent) +++ rtl/sys_gen/tst_serloop/s3board/tb/Makefile (revision 16) @@ -0,0 +1,29 @@ +# $Id: Makefile 441 2011-12-20 17:01:16Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-05 420 1.0 Initial version +# +EXE_all = tb_tst_serloop_s3 +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean isim_clean +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_isim.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_isim) +include $(wildcard *.o.dep_ghdl) +# Index: rtl/sys_gen/tst_serloop/s3board/tb/sys_tst_serloop_s3.ucf_cpp =================================================================== --- rtl/sys_gen/tst_serloop/s3board/tb/sys_tst_serloop_s3.ucf_cpp (nonexistent) +++ rtl/sys_gen/tst_serloop/s3board/tb/sys_tst_serloop_s3.ucf_cpp (revision 16) @@ -0,0 +1 @@ +link ../sys_tst_serloop_s3.ucf_cpp \ No newline at end of file
rtl/sys_gen/tst_serloop/s3board/tb/sys_tst_serloop_s3.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: rtl/sys_gen/tst_serloop/s3board/tb =================================================================== --- rtl/sys_gen/tst_serloop/s3board/tb (nonexistent) +++ rtl/sys_gen/tst_serloop/s3board/tb (revision 16)
rtl/sys_gen/tst_serloop/s3board/tb Property changes : Added: svn:ignore ## -0,0 +1,38 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_tst_serloop_s3 +tb_tst_serloop_s3_[sft]sim +tb_tst_serloop_s3_ISim +tb_tst_serloop_s3_ISim_[sft]sim +tb_tst_serloop_stim +*.dep_ucf_cpp Index: rtl/sys_gen/tst_serloop/s3board/Makefile =================================================================== --- rtl/sys_gen/tst_serloop/s3board/Makefile (nonexistent) +++ rtl/sys_gen/tst_serloop/s3board/Makefile (revision 16) @@ -0,0 +1,27 @@ +# $Id: Makefile 441 2011-12-20 17:01:16Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-10-14 416 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +ISE_BOARD = s3board +ISE_PATH = xc3s1000-ft256-4 +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f sys_tst_serloop_s3.ucf +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +# Index: rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.mfset =================================================================== --- rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.mfset (nonexistent) +++ rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.mfset (revision 16) @@ -0,0 +1,34 @@ +# $Id: sys_tst_serloop_s3.mfset 441 2011-12-20 17:01:16Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Mux is complete : default of case is discarded + +Unconnected output port 'LOCKED' of component 'dcm_sfs' +Unconnected output port 'SIZE' of component 'fifo_1c_dram' +Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' + +Input > is never used +Input > is never used +Input > is never used +Input > is never used + +Signal > is assigned but never used +Signal is assigned but never used + +# +# ---------------------------------------------------------------------------- +[tra] + +# +# ---------------------------------------------------------------------------- +[map] +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] + +# +# ---------------------------------------------------------------------------- +[bgn] Index: rtl/sys_gen/tst_serloop/s3board/.cvsignore =================================================================== --- rtl/sys_gen/tst_serloop/s3board/.cvsignore (nonexistent) +++ rtl/sys_gen/tst_serloop/s3board/.cvsignore (revision 16) @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_serloop_s3.ucf +*.dep_ucf_cpp +*.svf Index: rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.ucf_cpp =================================================================== --- rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.ucf_cpp (nonexistent) +++ rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.ucf_cpp (revision 16) @@ -0,0 +1,19 @@ +## $Id: sys_tst_serloop_s3.ucf_cpp 441 2011-12-20 17:01:16Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-10-25 419 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +## std board +## +#include "bplib/s3board/s3board_pins.ucf" +## +## Pmod1-RS232 on A2 connector +## +#include "bplib/s3board/s3board_a2_pm1_rs232.ucf" Index: rtl/sys_gen/tst_serloop/s3board =================================================================== --- rtl/sys_gen/tst_serloop/s3board (nonexistent) +++ rtl/sys_gen/tst_serloop/s3board (revision 16)
rtl/sys_gen/tst_serloop/s3board Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_serloop_s3.ucf +*.dep_ucf_cpp +*.svf Index: rtl/sys_gen/tst_serloop/tst_serloop.vhd =================================================================== --- rtl/sys_gen/tst_serloop/tst_serloop.vhd (nonexistent) +++ rtl/sys_gen/tst_serloop/tst_serloop.vhd (revision 16) @@ -0,0 +1,241 @@ +-- $Id: tst_serloop.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tst_serloop - syn +-- Description: simple stand-alone tester for serport components +-- +-- Dependencies: - +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-10 438 1.0.2 clr fecnt when abact; add rxui(cnt|dat) regs +-- 2011-12-09 437 1.0.1 rename serport stat->moni port +-- 2011-11-06 420 1.0 Initial version +-- 2011-10-14 416 0.5 First draft +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.serport.all; +use work.tst_serlooplib.all; + +-- ---------------------------------------------------------------------------- + +entity tst_serloop is -- tester for serport components + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CE_MSEC : in slbit; -- msec pulse + HIO_CNTL : in hio_cntl_type; -- humanio controls + HIO_STAT : out hio_stat_type; -- humanio status + SER_MONI : in serport_moni_type; -- serport monitor + RXDATA : in slv8; -- receiver data out + RXVAL : in slbit; -- receiver data valid + RXHOLD : out slbit; -- receiver data hold + TXDATA : out slv8; -- transmit data in + TXENA : out slbit; -- transmit data enable + TXBUSY : in slbit -- transmit busy + ); +end tst_serloop; + +architecture syn of tst_serloop is + + type regs_type is record + rxdata : slv8; -- next rx char + txdata : slv8; -- next tx char + rxfecnt : slv16; -- rx frame error counter + rxoecnt : slv16; -- rx overrun error counter + rxsecnt : slv16; -- rx sequence error counter + rxcnt : slv32; -- rx char counter + txcnt : slv32; -- tx char counter + rxuicnt : slv8; -- rx unsolicited input counter + rxuidat : slv8; -- rx unsolicited input data + rxokcnt : slv16; -- rxok 1->0 transition counter + txokcnt : slv16; -- txok 1->0 transition counter + rxok_1 : slbit; -- rxok last cycle + txok_1 : slbit; -- txok last cycle + rxthrottle : slbit; -- rx throttle flag + end record regs_type; + + constant regs_init : regs_type := ( + (others=>'0'), -- rxdata + (others=>'0'), -- txdata + (others=>'0'), -- rxfecnt + (others=>'0'), -- rxoecnt + (others=>'0'), -- rxsecnt + (others=>'0'), -- rxcnt + (others=>'0'), -- txcnt + (others=>'0'), -- rxuicnt + (others=>'0'), -- rxuidat + (others=>'0'), -- rxokcnt + (others=>'0'), -- txokcnt + '0','0', -- rxok_1,txok_1 + '0' -- rxthrottle + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + +begin + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, SER_MONI, + RXDATA, RXVAL, TXBUSY) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable irxhold : slbit := '1'; + variable itxena : slbit := '0'; + variable itxdata : slv8 := (others=>'0'); + variable skipxon : slbit := '0'; + + function nextchar(skipxon: in slbit; data: in slv8) return slv8 is + variable inc : slv8 := (others=>'0'); + begin + inc := "00000001"; + if skipxon='1' and (data=c_serport_xon or data=c_serport_xoff) then + inc := "00000010"; + end if; + return slv(unsigned(data)+unsigned(inc)); + end function nextchar; + + begin + r := R_REGS; + n := R_REGS; + + irxhold := '1'; + itxena := '0'; + + itxdata := RXDATA; + if HIO_CNTL.mode = c_mode_txblast then + itxdata := r.txdata; + end if; + + skipxon := '0'; + if HIO_CNTL.enaxon='1' and HIO_CNTL.enaesc='0' then + skipxon := '1'; + end if; + + if HIO_CNTL.enathrottle = '1' then + if CE_MSEC = '1' then + n.rxthrottle := not r.rxthrottle; + end if; + else + n.rxthrottle := '0'; + end if; + + + case HIO_CNTL.mode is + when c_mode_idle => + null; + + when c_mode_rxblast => + if RXVAL='1' and r.rxthrottle='0' then + irxhold := '0'; + if RXDATA /= r.rxdata then + n.rxsecnt := slv(unsigned(r.rxsecnt) + 1); + end if; + n.rxdata := nextchar(skipxon, RXDATA); + end if; + + when c_mode_txblast => + if TXBUSY = '0' then + itxena := '1'; + n.txdata := nextchar(skipxon, r.txdata); + end if; + irxhold := '0'; + if RXVAL = '1' then + n.rxuicnt := slv(unsigned(r.rxuicnt) + 1); + n.rxuidat := RXDATA; + end if; + + when c_mode_loop => + if RXVAL='1' and r.rxthrottle='0' and TXBUSY = '0' then + irxhold := '0'; + itxena := '1'; + end if; + + when others => null; + end case; + + + if SER_MONI.abact = '1' then -- if auto bauder active + n.rxfecnt := (others=>'0'); -- reset frame error counter + else -- otherwise + if SER_MONI.rxerr = '1' then -- count rx frame errors + n.rxfecnt := slv(unsigned(r.rxfecnt) + 1); + end if; + end if; + + if SER_MONI.rxovr = '1' then + n.rxoecnt := slv(unsigned(r.rxoecnt) + 1); + end if; + + if RXVAL='1' and irxhold='0' then + n.rxcnt := slv(unsigned(r.rxcnt) + 1); + end if; + + if itxena = '1' then + n.txcnt := slv(unsigned(r.txcnt) + 1); + end if; + + n.rxok_1 := SER_MONI.rxok; + n.txok_1 := SER_MONI.txok; + + if SER_MONI.rxok='0' and r.rxok_1='1' then + n.rxokcnt := slv(unsigned(r.rxokcnt) + 1); + end if; + if SER_MONI.txok='0' and r.txok_1='1' then + n.txokcnt := slv(unsigned(r.txokcnt) + 1); + end if; + + N_REGS <= n; + + RXHOLD <= irxhold; + TXENA <= itxena; + TXDATA <= itxdata; + + HIO_STAT.rxfecnt <= r.rxfecnt; + HIO_STAT.rxoecnt <= r.rxoecnt; + HIO_STAT.rxsecnt <= r.rxsecnt; + HIO_STAT.rxcnt <= r.rxcnt; + HIO_STAT.txcnt <= r.txcnt; + HIO_STAT.rxuicnt <= r.rxuicnt; + HIO_STAT.rxuidat <= r.rxuidat; + HIO_STAT.rxokcnt <= r.rxokcnt; + HIO_STAT.txokcnt <= r.txokcnt; + + end process proc_next; + +end syn; Index: rtl/sys_gen/tst_serloop/Makefile =================================================================== --- rtl/sys_gen/tst_serloop/Makefile (nonexistent) +++ rtl/sys_gen/tst_serloop/Makefile (revision 16) @@ -0,0 +1,26 @@ +# $Id: Makefile 441 2011-12-20 17:01:16Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-10-14 416 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +ISE_PATH = xc3s1000-ft256-4 +# +.PHONY : all clean realclean +# +all : tst_serloop +# +clean : ise_clean +# +realclean : + rm -f tst_serloop +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +include $(VBOM_all:.vbom=.dep_xst) +# Index: rtl/sys_gen/tst_serloop/.cvsignore =================================================================== --- rtl/sys_gen/tst_serloop/.cvsignore (nonexistent) +++ rtl/sys_gen/tst_serloop/.cvsignore (revision 16) @@ -0,0 +1 @@ +tst_serloop Index: rtl/sys_gen/tst_serloop =================================================================== --- rtl/sys_gen/tst_serloop (nonexistent) +++ rtl/sys_gen/tst_serloop (revision 16)
rtl/sys_gen/tst_serloop Property changes : Added: svn:ignore ## -0,0 +1,33 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tst_serloop Index: rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vbom =================================================================== --- rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vbom (nonexistent) +++ rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vbom (revision 16) @@ -0,0 +1,14 @@ +# Not meant for direct top level usage. Used with +# tb_nx_cram_memctl_(....)[_ssim].vbom and config +# lines to generate the different cases. +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/simlib/simlib.vhd +# components +../../../vlib/simlib/simclk.vbom +../../micron/mt45w8mw16b.vbom +uut : tbd_nx_cram_memctl_as.vbom +# design +tb_nx_cram_memctl.vhd +@top:tb_nx_cram_memctl Index: rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl_as.vhd =================================================================== --- rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl_as.vhd (nonexistent) +++ rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl_as.vhd (revision 16) @@ -0,0 +1,39 @@ +-- $Id: tb_nx_cram_memctl_as.vhd 433 2011-11-27 22:04:39Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_nx_cram_memctl_as +-- Description: Configuration tb_nx_cram_memctl_as for tb_nx_cram_memctl +-- +-- Dependencies: tbd_nx_cram_memctl_as +-- To test: nx_cram_memctl_as +-- +-- Verified (with tb_nx_cram_memctl_stim.dat): +-- Date Rev Code ghdl ise Target Comment +-- 2010-05-30 297 - 0.26 11.4 L68 xc3s1200e ok +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-26 433 1.1 renamed from tb_n2_cram_memctl_as +-- 2010-05-30 297 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_nx_cram_memctl_as of tb_nx_cram_memctl is + + for sim + for all :tbd_nx_cram_memctl + use entity work.tbd_nx_cram_memctl_as; + end for; + end for; + +end tb_nx_cram_memctl_as; Index: rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl_stim.dat =================================================================== --- rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl_stim.dat (nonexistent) +++ rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl_stim.dat (revision 16) @@ -0,0 +1,212 @@ +# $Id: tb_nx_cram_memctl_stim.dat 433 2011-11-27 22:04:39Z mueller $ +# +.memon 0 +# +C write full word 16 cells +# +write 000000 1111 30201000 +write 000001 1111 31211101 +write 000002 1111 32221202 +write 000003 1111 33231303 +write 000004 1111 34241404 +write 000005 1111 35251505 +write 000006 1111 36261606 +write 000007 1111 37271707 +write 000008 1111 38281808 +write 000009 1111 39291909 +write 00000a 1111 3a2a1a0a +write 00000b 1111 3b2b1b0b +write 00000c 1111 3c2c1c0c +write 00000d 1111 3d2d1d0d +write 00000e 1111 3e2e1e0e +write 00000f 1111 3f2f1f0f +# +C read 16 cells +# +read 000000 30201000 +read 000001 31211101 +read 000002 32221202 +read 000003 33231303 +read 000004 34241404 +read 000005 35251505 +read 000006 36261606 +read 000007 37271707 +read 000008 38281808 +read 000009 39291909 +read 00000a 3a2a1a0a +read 00000b 3b2b1b0b +read 00000c 3c2c1c0c +read 00000d 3d2d1d0d +read 00000e 3e2e1e0e +read 00000f 3f2f1f0f +# +C write selected bytes in first 16 cells +# +write 000000 0000 70605040 +write 000001 0001 71615141 +write 000002 0010 72625242 +write 000003 0011 73635343 +write 000004 0100 74645444 +write 000005 0101 75655545 +write 000006 0110 76665646 +write 000007 0111 77675747 +write 000008 1000 78685848 +write 000009 1001 79695949 +write 00000a 1010 7a6a5a4a +write 00000b 1011 7b6b5b4b +write 00000c 1100 7c6c5c4c +write 00000d 1101 7d6d5d4d +write 00000e 1110 7e6e5e4e +write 00000f 1111 7f6f5f4f +# +C read back +# +read 000000 30201000 +read 000001 31211141 +read 000002 32225202 +read 000003 33235343 +read 000004 34641404 +read 000005 35651545 +read 000006 36665606 +read 000007 37675747 +read 000008 78281808 +read 000009 79291949 +read 00000a 7a2a5a0a +read 00000b 7b2b5b4b +read 00000c 7c6c1c0c +read 00000d 7d6d1d4d +read 00000e 7e6e5e0e +read 00000f 7f6f5f4f +# +C read and write with waits +# +.wait 12 +write 000010 1111 30201000 +.wait 11 +write 000011 1111 31211101 +.wait 10 +write 000012 1111 32221202 +.wait 9 +write 000013 1111 33231303 +.wait 8 +write 000014 1111 34241404 +.wait 7 +write 000015 1111 35251505 +.wait 6 +write 000016 1111 36261606 +.wait 5 +write 000017 1111 37271707 +.wait 4 +write 000018 1111 38281808 +.wait 3 +write 000019 1111 39291909 +.wait 2 +write 00001a 1111 3a2a1a0a +.wait 1 +write 00001b 1111 3b2b1b0b +write 00001c 1111 3b2b1b0b +# +.wait 12 +read 000010 30201000 +.wait 11 +read 000011 31211101 +.wait 10 +read 000012 32221202 +.wait 9 +read 000013 33231303 +.wait 8 +read 000014 34241404 +.wait 7 +read 000015 35251505 +.wait 6 +read 000016 36261606 +.wait 5 +read 000017 37271707 +.wait 4 +read 000018 38281808 +.wait 3 +read 000019 39291909 +.wait 2 +read 00001a 3a2a1a0a +.wait 1 +read 00000e 7e6e5e0e +read 00000f 7f6f5f4f +# +C read and write mixed, with waits +# +.wait 2 +write 000014 1111 34241404 +.wait 2 +read 000012 32221202 +.wait 2 +write 000015 1111 35251505 +.wait 2 +read 000013 33231303 +# +.wait 1 +write 000016 1111 36261606 +.wait 1 +read 000014 34241404 +.wait 1 +write 000017 1111 37271707 +.wait 1 +read 000015 35251505 +# +write 000018 1111 38281808 +read 000016 36261606 +write 000019 1111 39291909 +read 000017 37271707 +# +.wait 2 +write 00001a 1111 3a2a1a0a +write 00001b 1111 3b2b1b0b +.wait 2 +read 000018 38281808 +read 000019 39291909 +.wait 2 +write 00001c 1111 3c2c1c0c +write 00001d 1111 3d2d1d0d +.wait 2 +read 00001a 3a2a1a0a +read 00001b 3b2b1b0b +# +.wait 1 +write 00001e 1111 3e2e1e0e +write 00001f 1111 3f2f1f0f +.wait 1 +read 00001c 3c2c1c0c +read 00001d 3d2d1d0d +.wait 1 +write 000014 0100 74645444 +write 000015 0101 75655545 +.wait 1 +read 00001e 3e2e1e0e +read 00001f 3f2f1f0f +# +write 000016 0110 76665646 +write 000017 0111 77675747 +read 000010 30201000 +read 000011 31211101 +write 000018 1000 78685848 +write 000019 1001 79695949 +read 000012 32221202 +read 000013 33231303 +# +write 00001a 1010 7a6a5a4a +write 00001b 1011 7b6b5b4b +write 00001c 1100 7c6c5c4c +read 000014 34641404 +read 000015 35651545 +read 000016 36665606 +write 00001d 1101 7d6d5d4d +write 00001e 1110 7e6e5e4e +write 00001f 1111 7f6f5f4f +read 000017 37675747 +read 000018 78281808 +read 000019 79291949 +read 00001a 7a2a5a0a +read 00001b 7b2b5b4b +read 00001c 7c6c1c0c +read 00001d 7d6d1d4d +read 00001e 7e6e5e0e +read 00001f 7f6f5f4f Index: rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl_as.vbom =================================================================== --- rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl_as.vbom (nonexistent) +++ rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl_as.vbom (revision 16) @@ -0,0 +1,6 @@ +# configure tb_nx_cram_memctl with tbd_nx_cram_memctl_as target; +# use vhdl configure file (tb_nx_cram_memctl_as.vhd) to allow +# that all configurations will co-exist in work library +uut = tbd_nx_cram_memctl_as.vbom +tb_nx_cram_memctl.vbom +tb_nx_cram_memctl_as.vhd Index: rtl/bplib/nxcramlib/tb/tbw.dat =================================================================== --- rtl/bplib/nxcramlib/tb/tbw.dat (nonexistent) +++ rtl/bplib/nxcramlib/tb/tbw.dat (revision 16) @@ -0,0 +1,4 @@ +# $Id: tbw.dat 433 2011-11-27 22:04:39Z mueller $ +# +[tb_nx_cram_memctl_as] +tb_nx_cram_memctl_stim = tb_nx_cram_memctl_stim.dat Index: rtl/bplib/nxcramlib/tb/tbd_nx_cram_memctl_as.vhd =================================================================== --- rtl/bplib/nxcramlib/tb/tbd_nx_cram_memctl_as.vhd (nonexistent) +++ rtl/bplib/nxcramlib/tb/tbd_nx_cram_memctl_as.vhd (revision 16) @@ -0,0 +1,121 @@ +-- $Id: tbd_nx_cram_memctl_as.vhd 433 2011-11-27 22:04:39Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tbd_nx_cram_memctl_as - syn +-- Description: Wrapper for nx_cram_memctl_as to avoid records & generics. +-- It has a port interface which will not be modified by xst +-- synthesis (no records, no generic port). +-- +-- Dependencies: nx_cram_memctl_as +-- To test: nx_cram_memctl_as +-- +-- Target Devices: generic +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 122 0 107 t 11.4 +-- 2010-05-30 297 11.4 L68 xc3s1200e-4 91 99 0 95 t 13.1 +-- +-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-26 433 1.2 renamed from tbd_n2_cram_memctl_as +-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_memctl +-- 2010-06-03 298 1.0.1 add hack to force IOB'FFs to O_MEM_ADDR +-- 2010-05-30 297 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.nxcramlib.all; + +entity tbd_nx_cram_memctl_as is -- CRAM driver (async mode) [tb design] + -- generic: READ0=2;READ1=2;WRITE=3 + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + REQ : in slbit; -- request + WE : in slbit; -- write enable + BUSY : out slbit; -- controller busy + ACK_R : out slbit; -- acknowledge read + ACK_W : out slbit; -- acknowledge write + ACT_R : out slbit; -- signal active read + ACT_W : out slbit; -- signal active write + ADDR : in slv22; -- address (32 bit word address) + BE : in slv4; -- byte enable + DI : in slv32; -- data in (memory view) + DO : out slv32; -- data out (memory view) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16 -- cram: data lines + ); +end tbd_nx_cram_memctl_as; + + +architecture syn of tbd_nx_cram_memctl_as is + + signal ADDR_X : slv22 := (others=>'0'); + +begin + + -- Note: This is a HACk to ensure that the IOB flops are on the O_MEM_ADDR + -- pins. Without par might choose to use IFF's on ADDR, causing varying + -- routing delays to O_MEM_ADDR. Didn't find a better way, setting + -- iob "false" attributes in ADDR didn't help. + -- This logic doesn't hurt, and prevents that IFFs for ADDR compete with + -- OFF's for O_MEM_ADDR. + + ADDR_X <= ADDR when RESET='0' else (others=>'0'); + + MEMCTL : nx_cram_memctl_as + generic map ( + READ0DELAY => 2, + READ1DELAY => 2, + WRITEDELAY => 3) + port map ( + CLK => CLK, + RESET => RESET, + REQ => REQ, + WE => WE, + BUSY => BUSY, + ACK_R => ACK_R, + ACK_W => ACK_W, + ACT_R => ACT_R, + ACT_W => ACT_W, + ADDR => ADDR_X, + BE => BE, + DI => DI, + DO => DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + +end syn; Index: rtl/bplib/nxcramlib/tb/tbd_nx_cram_memctl_as.vbom =================================================================== --- rtl/bplib/nxcramlib/tb/tbd_nx_cram_memctl_as.vbom (nonexistent) +++ rtl/bplib/nxcramlib/tb/tbd_nx_cram_memctl_as.vbom (revision 16) @@ -0,0 +1,7 @@ +# libs +../../../vlib/slvtypes.vhd +../nxcramlib.vhd +# components +../nx_cram_memctl_as.vbom +# design +tbd_nx_cram_memctl_as.vhd Index: rtl/bplib/nxcramlib/tb/Makefile =================================================================== --- rtl/bplib/nxcramlib/tb/Makefile (nonexistent) +++ rtl/bplib/nxcramlib/tb/Makefile (revision 16) @@ -0,0 +1,31 @@ +# $Id: Makefile 433 2011-11-27 22:04:39Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-26 433 1.0 Initial version (cloned) +# +EXE_all = tb_nx_cram_memctl_as +# +ISE_PATH = xc3s1200e-fg320-4 +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean isim_clean +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_isim.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_isim) +include $(wildcard *.o.dep_ghdl) +# Index: rtl/bplib/nxcramlib/tb/.cvsignore =================================================================== --- rtl/bplib/nxcramlib/tb/.cvsignore (nonexistent) +++ rtl/bplib/nxcramlib/tb/.cvsignore (revision 16) @@ -0,0 +1,5 @@ +tb_nx_cram_memctl_as +tb_nx_cram_memctl_as_[sft]sim +tb_nx_cram_memctl_as_ISim +tb_nx_cram_memctl_as_ISim_[sft]sim +tb_nx_cram_memctl_stim Index: rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vhd =================================================================== --- rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vhd (nonexistent) +++ rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vhd (revision 16) @@ -0,0 +1,373 @@ +-- $Id: tb_nx_cram_memctl.vhd 433 2011-11-27 22:04:39Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_nx_cram_memctl - sim +-- Description: Test bench for nx_cram_memctl +-- +-- Dependencies: vlib/simlib/simclk +-- bplib/micron/mt45w8mw16b +-- tbd_nx_cram_memctl [UUT, abstact] +-- +-- To test: nx_cram_memctl_as (via tbd_nx_cram_memctl_as) +-- +-- Target Devices: generic +-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-26 433 1.3 renamed from tb_n2_cram_memctl +-- 2011-11-21 432 1.2 now numeric_std clean; update O_FLA_CE_N usage +-- 2010-05-30 297 1.1 use abstact uut tbd_nx_cram_memctl +-- 2010-05-23 293 1.0 Initial version (derived from tb_s3_sram_memctl) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.simlib.all; + +entity tb_nx_cram_memctl is +end tb_nx_cram_memctl; + +architecture sim of tb_nx_cram_memctl is + +component tbd_nx_cram_memctl is -- CRAM driver (abstract) [tb design] + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + REQ : in slbit; -- request + WE : in slbit; -- write enable + BUSY : out slbit; -- controller busy + ACK_R : out slbit; -- acknowledge read + ACK_W : out slbit; -- acknowledge write + ACT_R : out slbit; -- signal active read + ACT_W : out slbit; -- signal active write + ADDR : in slv22; -- address (32 bit word address) + BE : in slv4; -- byte enable + DI : in slv32; -- data in (memory view) + DO : out slv32; -- data out (memory view) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16 -- cram: data lines + ); +end component; + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + signal REQ : slbit := '0'; + signal WE : slbit := '0'; + signal BUSY : slbit := '0'; + signal ACK_R : slbit := '0'; + signal ACK_W : slbit := '0'; + signal ACT_R : slbit := '0'; + signal ACT_W : slbit := '0'; + signal ADDR : slv22 := (others=>'0'); + signal BE : slv4 := (others=>'0'); + signal DI : slv32 := (others=>'0'); + signal DO : slv32 := (others=>'0'); + signal O_MEM_CE_N : slbit := '0'; + signal O_MEM_BE_N : slv2 := (others=>'0'); + signal O_MEM_WE_N : slbit := '0'; + signal O_MEM_OE_N : slbit := '0'; + signal O_MEM_ADV_N : slbit := '0'; + signal O_MEM_CLK : slbit := '0'; + signal O_MEM_CRE : slbit := '0'; + signal I_MEM_WAIT : slbit := '0'; + signal O_MEM_ADDR : slv23 := (others=>'0'); + signal IO_MEM_DATA : slv16 := (others=>'0'); + + signal R_MEMON : slbit := '0'; + signal N_CHK_DATA : slbit := '0'; + signal N_REF_DATA : slv32 := (others=>'0'); + signal N_REF_ADDR : slv22 := (others=>'0'); + signal R_CHK_DATA_AL : slbit := '0'; + signal R_REF_DATA_AL : slv32 := (others=>'0'); + signal R_REF_ADDR_AL : slv22 := (others=>'0'); + signal R_CHK_DATA_DL : slbit := '0'; + signal R_REF_DATA_DL : slv32 := (others=>'0'); + signal R_REF_ADDR_DL : slv22 := (others=>'0'); + + signal CLK_STOP : slbit := '0'; + signal CLK_CYCLE : slv31 := (others=>'0'); + + constant clock_period : time := 20 ns; + constant clock_offset : time := 200 ns; + constant setup_time : time := 7.5 ns; -- compatible ucf for + constant c2out_time : time := 12.0 ns; -- tbd_nx_cram_memctl_as + +begin + + SYSCLK : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK, + CLK_CYCLE => CLK_CYCLE, + CLK_STOP => CLK_STOP + ); + + MEM : entity work.mt45w8mw16b + port map ( + CLK => O_MEM_CLK, + CE_N => O_MEM_CE_N, + OE_N => O_MEM_OE_N, + WE_N => O_MEM_WE_N, + UB_N => O_MEM_BE_N(1), + LB_N => O_MEM_BE_N(0), + ADV_N => O_MEM_ADV_N, + CRE => O_MEM_CRE, + MWAIT => I_MEM_WAIT, + ADDR => O_MEM_ADDR, + DATA => IO_MEM_DATA + ); + + UUT : tbd_nx_cram_memctl + port map ( + CLK => CLK, + RESET => RESET, + REQ => REQ, + WE => WE, + BUSY => BUSY, + ACK_R => ACK_R, + ACK_W => ACK_W, + ACT_R => ACT_R, + ACT_W => ACT_W, + ADDR => ADDR, + BE => BE, + DI => DI, + DO => DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + proc_stim: process + file fstim : text open read_mode is "tb_nx_cram_memctl_stim"; + variable iline : line; + variable oline : line; + variable ok : boolean; + variable dname : string(1 to 6) := (others=>' '); + variable idelta : integer := 0; + variable iaddr : slv22 := (others=>'0'); + variable idata : slv32 := (others=>'0'); + variable ibe : slv4 := (others=>'0'); + variable ival : slbit := '0'; + variable nbusy : integer := 0; + + begin + + wait for clock_offset - setup_time; + + file_loop: while not endfile(fstim) loop + + readline (fstim, iline); + + readcomment(iline, ok); + next file_loop when ok; + + readword(iline, dname, ok); + if ok then + case dname is + when ".memon" => -- .memon + read_ea(iline, ival); + R_MEMON <= ival; + wait for 2*clock_period; + + when ".reset" => -- .reset + write(oline, string'(".reset")); + writeline(output, oline); + RESET <= '1'; + wait for clock_period; + RESET <= '0'; + wait for 9*clock_period; + + when ".wait " => -- .wait + read_ea(iline, idelta); + wait for idelta*clock_period; + + when "read " => -- read + readgen_ea(iline, iaddr, 16); + readgen_ea(iline, idata, 16); + ADDR <= iaddr; + REQ <= '1'; + WE <= '0'; + + writetimestamp(oline, CLK_CYCLE, ": stim read "); + writegen(oline, iaddr, right, 7, 16); + write(oline, string'(" ")); + writegen(oline, idata, right, 9, 16); + + nbusy := 0; + while BUSY='1' loop + nbusy := nbusy + 1; + wait for clock_period; + end loop; + + write(oline, string'(" nbusy=")); + write(oline, nbusy, right, 2); + writeline(output, oline); + + N_CHK_DATA <= '1', '0' after clock_period; + N_REF_DATA <= idata; + N_REF_ADDR <= iaddr; + + wait for clock_period; + REQ <= '0'; + + when "write " => -- write + readgen_ea(iline, iaddr, 16); + read_ea(iline, ibe); + readgen_ea(iline, idata, 16); + ADDR <= iaddr; + BE <= ibe; + DI <= idata; + REQ <= '1'; + WE <= '1'; + + writetimestamp(oline, CLK_CYCLE, ": stim write"); + writegen(oline, iaddr, right, 7, 16); + writegen(oline, ibe , right, 5, 2); + writegen(oline, idata, right, 9, 16); + + nbusy := 0; + while BUSY = '1' loop + nbusy := nbusy + 1; + wait for clock_period; + end loop; + + write(oline, string'(" nbusy=")); + write(oline, nbusy, right, 2); + writeline(output, oline); + + wait for clock_period; + REQ <= '0'; + + when others => -- bad directive + write(oline, string'("?? unknown directive: ")); + write(oline, dname); + writeline(output, oline); + report "aborting" severity failure; + end case; + else + report "failed to find command" severity failure; + + end if; + + testempty_ea(iline); + + end loop; -- file fstim + + wait for 10*clock_period; + + writetimestamp(oline, CLK_CYCLE, ": DONE "); + writeline(output, oline); + + CLK_STOP <= '1'; + + wait; -- suspend proc_stim forever + -- clock is stopped, sim will end + + end process proc_stim; + + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLK); + + if ACK_R = '1' then + writetimestamp(oline, CLK_CYCLE, ": moni "); + writegen(oline, DO, right, 9, 16); + if R_CHK_DATA_DL = '1' then + write(oline, string'(" CHECK")); + if R_REF_DATA_DL = DO then + write(oline, string'(" OK")); + else + write(oline, string'(" FAIL, exp=")); + writegen(oline, R_REF_DATA_DL, right, 9, 16); + write(oline, string'(" for a=")); + writegen(oline, R_REF_ADDR_DL, right, 5, 16); + end if; + R_CHK_DATA_DL <= '0'; + end if; + writeline(output, oline); + end if; + + if R_CHK_DATA_AL = '1' then + R_CHK_DATA_DL <= R_CHK_DATA_AL; + R_REF_DATA_DL <= R_REF_DATA_AL; + R_REF_ADDR_DL <= R_REF_ADDR_AL; + R_CHK_DATA_AL <= '0'; + end if; + if N_CHK_DATA = '1' then + R_CHK_DATA_AL <= N_CHK_DATA; + R_REF_DATA_AL <= N_REF_DATA; + R_REF_ADDR_AL <= N_REF_ADDR; + end if; + + end loop; + + end process proc_moni; + + + proc_memon: process + variable oline : line; + begin + + loop + wait until rising_edge(CLK); + + if R_MEMON = '1' then + writetimestamp(oline, CLK_CYCLE, ": mem "); + write(oline, string'(" ce=")); + write(oline, not O_MEM_CE_N, right, 2); + write(oline, string'(" be=")); + write(oline, not O_MEM_BE_N, right, 4); + write(oline, string'(" we=")); + write(oline, not O_MEM_WE_N, right); + write(oline, string'(" oe=")); + write(oline, not O_MEM_OE_N, right); + write(oline, string'(" a=")); + writegen(oline, O_MEM_ADDR, right, 6, 16); + write(oline, string'(" d=")); + writegen(oline, IO_MEM_DATA, right, 4, 16); + writeline(output, oline); + end if; + + end loop; + + end process proc_memon; + + +end sim; Index: rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl_as_ssim.vbom =================================================================== --- rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl_as_ssim.vbom (nonexistent) +++ rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl_as_ssim.vbom (revision 16) @@ -0,0 +1,5 @@ +# configure for _*sim case +# +uut = tbd_nx_cram_memctl_as_ssim.vhd +tb_nx_cram_memctl_as.vbom +@top:tb_nx_cram_memctl_as Index: rtl/bplib/nxcramlib/tb =================================================================== --- rtl/bplib/nxcramlib/tb (nonexistent) +++ rtl/bplib/nxcramlib/tb (revision 16)
rtl/bplib/nxcramlib/tb Property changes : Added: svn:ignore ## -0,0 +1,37 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_nx_cram_memctl_as +tb_nx_cram_memctl_as_[sft]sim +tb_nx_cram_memctl_as_ISim +tb_nx_cram_memctl_as_ISim_[sft]sim +tb_nx_cram_memctl_stim Index: rtl/bplib/s3board/tb/tb_s3_sram_memctl.vbom =================================================================== --- rtl/bplib/s3board/tb/tb_s3_sram_memctl.vbom (nonexistent) +++ rtl/bplib/s3board/tb/tb_s3_sram_memctl.vbom (revision 16) @@ -0,0 +1,10 @@ +# libs +../../../vlib/slvtypes.vhd +../s3boardlib.vbom +../../../vlib/simlib/simlib.vhd +# components +../../../vlib/simlib/simclk.vbom +../../issi/is61lv25616al.vbom +uut : ../s3_sram_memctl.vbom +# design +tb_s3_sram_memctl.vhd Index: rtl/bplib/s3board/tb/tb_s3_sram_memctl_stim.dat =================================================================== --- rtl/bplib/s3board/tb/tb_s3_sram_memctl_stim.dat (nonexistent) +++ rtl/bplib/s3board/tb/tb_s3_sram_memctl_stim.dat (revision 16) @@ -0,0 +1,176 @@ +# $Id: tb_s3_sram_memctl_stim.dat 290 2010-05-16 08:44:36Z mueller $ +# +.memon 0 +# +C write full word 16 cells +# +write 00000 1111 30201000 +write 00001 1111 31211101 +write 00002 1111 32221202 +write 00003 1111 33231303 +write 00004 1111 34241404 +write 00005 1111 35251505 +write 00006 1111 36261606 +write 00007 1111 37271707 +write 00008 1111 38281808 +write 00009 1111 39291909 +write 0000a 1111 3a2a1a0a +write 0000b 1111 3b2b1b0b +write 0000c 1111 3c2c1c0c +write 0000d 1111 3d2d1d0d +write 0000e 1111 3e2e1e0e +write 0000f 1111 3f2f1f0f +# +C read 16 cells +# +read 00000 30201000 +read 00001 31211101 +read 00002 32221202 +read 00003 33231303 +read 00004 34241404 +read 00005 35251505 +read 00006 36261606 +read 00007 37271707 +read 00008 38281808 +read 00009 39291909 +read 0000a 3a2a1a0a +read 0000b 3b2b1b0b +read 0000c 3c2c1c0c +read 0000d 3d2d1d0d +read 0000e 3e2e1e0e +read 0000f 3f2f1f0f +# +C write selected bytes in first 16 cells +# +write 00000 0000 70605040 +write 00001 0001 71615141 +write 00002 0010 72625242 +write 00003 0011 73635343 +write 00004 0100 74645444 +write 00005 0101 75655545 +write 00006 0110 76665646 +write 00007 0111 77675747 +write 00008 1000 78685848 +write 00009 1001 79695949 +write 0000a 1010 7a6a5a4a +write 0000b 1011 7b6b5b4b +write 0000c 1100 7c6c5c4c +write 0000d 1101 7d6d5d4d +write 0000e 1110 7e6e5e4e +write 0000f 1111 7f6f5f4f +# +C read back +# +read 00000 30201000 +read 00001 31211141 +read 00002 32225202 +read 00003 33235343 +read 00004 34641404 +read 00005 35651545 +read 00006 36665606 +read 00007 37675747 +read 00008 78281808 +read 00009 79291949 +read 0000a 7a2a5a0a +read 0000b 7b2b5b4b +read 0000c 7c6c1c0c +read 0000d 7d6d1d4d +read 0000e 7e6e5e0e +read 0000f 7f6f5f4f +# +C read and write with waits +# +.wait 3 +write 00010 1111 30201000 +.wait 2 +write 00011 1111 31211101 +.wait 1 +write 00012 1111 32221202 +write 00013 1111 33231303 +# +.wait 3 +read 00010 30201000 +.wait 2 +read 00011 31211101 +.wait 1 +read 0000e 7e6e5e0e +read 0000f 7f6f5f4f +# +C read and write mixed, with waits +# +.wait 2 +write 00014 1111 34241404 +.wait 2 +read 00012 32221202 +.wait 2 +write 00015 1111 35251505 +.wait 2 +read 00013 33231303 +# +.wait 1 +write 00016 1111 36261606 +.wait 1 +read 00014 34241404 +.wait 1 +write 00017 1111 37271707 +.wait 1 +read 00015 35251505 +# +write 00018 1111 38281808 +read 00016 36261606 +write 00019 1111 39291909 +read 00017 37271707 +# +.wait 2 +write 0001a 1111 3a2a1a0a +write 0001b 1111 3b2b1b0b +.wait 2 +read 00018 38281808 +read 00019 39291909 +.wait 2 +write 0001c 1111 3c2c1c0c +write 0001d 1111 3d2d1d0d +.wait 2 +read 0001a 3a2a1a0a +read 0001b 3b2b1b0b +# +.wait 1 +write 0001e 1111 3e2e1e0e +write 0001f 1111 3f2f1f0f +.wait 1 +read 0001c 3c2c1c0c +read 0001d 3d2d1d0d +.wait 1 +write 00014 0100 74645444 +write 00015 0101 75655545 +.wait 1 +read 0001e 3e2e1e0e +read 0001f 3f2f1f0f +# +write 00016 0110 76665646 +write 00017 0111 77675747 +read 00010 30201000 +read 00011 31211101 +write 00018 1000 78685848 +write 00019 1001 79695949 +read 00012 32221202 +read 00013 33231303 +# +write 0001a 1010 7a6a5a4a +write 0001b 1011 7b6b5b4b +write 0001c 1100 7c6c5c4c +read 00014 34641404 +read 00015 35651545 +read 00016 36665606 +write 0001d 1101 7d6d5d4d +write 0001e 1110 7e6e5e4e +write 0001f 1111 7f6f5f4f +read 00017 37675747 +read 00018 78281808 +read 00019 79291949 +read 0001a 7a2a5a0a +read 0001b 7b2b5b4b +read 0001c 7c6c1c0c +read 0001d 7d6d1d4d +read 0001e 7e6e5e0e +read 0001f 7f6f5f4f Index: rtl/bplib/s3board/tb/s3board_fusp_dummy.vhd =================================================================== --- rtl/bplib/s3board/tb/s3board_fusp_dummy.vhd (nonexistent) +++ rtl/bplib/s3board/tb/s3board_fusp_dummy.vhd (revision 16) @@ -0,0 +1,78 @@ +-- $Id: s3board_fusp_dummy.vhd 336 2010-11-06 18:28:27Z mueller $ +-- +-- Copyright 2010- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: s3board_fusp_dummy - syn +-- Description: s3board minimal target (base+fusp; serport loopback) +-- +-- Dependencies: - +-- To test: tb_s3board_fusp +-- Target Devices: generic +-- Tool versions: xst 11.4; ghdl 0.26 +-- Revision History: +-- Date Rev Version Comment +-- 2010-11-06 336 1.0.3 rename input pin CLK -> I_CLK50 +-- 2010-05-21 292 1.0.2 rename _PM1_ -> _FUSP_ +-- 2010-05-16 291 1.0.1 rename s3board_usp_dummy->s3board_fusp_dummy +-- 2010-05-01 286 1.0 Initial version (derived from s3board_dummy) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.s3boardlib.all; + +entity s3board_fusp_dummy is -- S3BOARD dummy (base+fusp; loopback) + -- implements s3board_fusp_aif + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- s3 switches + I_BTN : in slv4; -- s3 buttons + O_LED : out slv8; -- s3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32; -- sram: data lines + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end s3board_fusp_dummy; + +architecture syn of s3board_fusp_dummy is + +begin + + O_TXD <= I_RXD; + O_FUSP_TXD <= I_FUSP_RXD; + O_FUSP_RTS_N <= I_FUSP_CTS_N; + + SRAM : s3_sram_dummy -- connect SRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + +end syn; Index: rtl/bplib/s3board/tb/s3board_fusp_dummy.vbom =================================================================== --- rtl/bplib/s3board/tb/s3board_fusp_dummy.vbom (nonexistent) +++ rtl/bplib/s3board/tb/s3board_fusp_dummy.vbom (revision 16) @@ -0,0 +1,7 @@ +# libs +../../../vlib/slvtypes.vhd +../s3boardlib.vbom +# components +../s3_sram_dummy.vbom +# design +s3board_fusp_dummy.vhd Index: rtl/bplib/s3board/tb/tb_s3_sram_memctl_ssim.vbom =================================================================== --- rtl/bplib/s3board/tb/tb_s3_sram_memctl_ssim.vbom (nonexistent) +++ rtl/bplib/s3board/tb/tb_s3_sram_memctl_ssim.vbom (revision 16) @@ -0,0 +1,4 @@ +# configure for _*sim case +uut = s3_sram_memctl_ssim.vhd +tb_s3_sram_memctl.vbom +@top:tb_s3_sram_memctl Index: rtl/bplib/s3board/tb/tb_s3_sram_memctl.vhd =================================================================== --- rtl/bplib/s3board/tb/tb_s3_sram_memctl.vhd (nonexistent) +++ rtl/bplib/s3board/tb/tb_s3_sram_memctl.vhd (revision 16) @@ -0,0 +1,353 @@ +-- $Id: tb_s3_sram_memctl.vhd 432 2011-11-25 20:16:28Z mueller $ +-- +-- Copyright 2007-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_s3_sram_memctl - sim +-- Description: Test bench for s3_sram_memctl +-- +-- Dependencies: vlib/simlib/simclk +-- bplib/issi/is61lv25616al +-- s3_sram_memctl [UUT] +-- +-- To test: s3_sram_memctl +-- +-- Verified (with tb_s3_sram_memctl_stim.dat): +-- Date Rev Code ghdl ise Target Comment +-- 2007-12-16 101 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok +-- 2007-12-16 101 - 0.26 - - c:ok +-- +-- Target Devices: generic +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-21 432 1.0.6 now numeric_std clean +-- 2010-05-23 293 1.0.5 output # busy cycles; change CHK pipeline logic +-- 2010-05-16 291 1.0.4 rename tb_memctl_s3sram->tb_s3_sram_memctl +-- 2008-03-24 129 1.0.3 CLK_CYCLE now 31 bits +-- 2008-02-17 117 1.0.2 use req,we rather req_r,req_w interface +-- 2008-01-20 113 1.0.1 rename memdrv -> memctl_s3sram +-- 2007-12-15 101 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.s3boardlib.all; +use work.simlib.all; + +entity tb_s3_sram_memctl is +end tb_s3_sram_memctl; + +architecture sim of tb_s3_sram_memctl is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + signal REQ : slbit := '0'; + signal WE : slbit := '0'; + signal BUSY : slbit := '0'; + signal ACK_R : slbit := '0'; + signal ACK_W : slbit := '0'; + signal ACT_R : slbit := '0'; + signal ACT_W : slbit := '0'; + signal ADDR : slv18 := (others=>'0'); + signal BE : slv4 := (others=>'0'); + signal DI : slv32 := (others=>'0'); + signal DO : slv32 := (others=>'0'); + signal O_MEM_CE_N : slv2 := (others=>'0'); + signal O_MEM_BE_N : slv4 := (others=>'0'); + signal O_MEM_WE_N : slbit := '0'; + signal O_MEM_OE_N : slbit := '0'; + signal O_MEM_ADDR : slv18 := (others=>'0'); + signal IO_MEM_DATA : slv32 := (others=>'0'); + + signal R_MEMON : slbit := '0'; + signal N_CHK_DATA : slbit := '0'; + signal N_REF_DATA : slv32 := (others=>'0'); + signal N_REF_ADDR : slv18 := (others=>'0'); + signal R_CHK_DATA_AL : slbit := '0'; + signal R_REF_DATA_AL : slv32 := (others=>'0'); + signal R_REF_ADDR_AL : slv18 := (others=>'0'); + signal R_CHK_DATA_DL : slbit := '0'; + signal R_REF_DATA_DL : slv32 := (others=>'0'); + signal R_REF_ADDR_DL : slv18 := (others=>'0'); + + signal CLK_STOP : slbit := '0'; + signal CLK_CYCLE : slv31 := (others=>'0'); + + constant clock_period : time := 20 ns; + constant clock_offset : time := 200 ns; + constant setup_time : time := 5 ns; + constant c2out_time : time := 10 ns; + +begin + + SYSCLK : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK, + CLK_CYCLE => CLK_CYCLE, + CLK_STOP => CLK_STOP + ); + + MEM_L : entity work.is61lv25616al + port map ( + CE_N => O_MEM_CE_N(0), + OE_N => O_MEM_OE_N, + WE_N => O_MEM_WE_N, + UB_N => O_MEM_BE_N(1), + LB_N => O_MEM_BE_N(0), + ADDR => O_MEM_ADDR, + DATA => IO_MEM_DATA(15 downto 0) + ); + + MEM_U : entity work.is61lv25616al + port map ( + CE_N => O_MEM_CE_N(1), + OE_N => O_MEM_OE_N, + WE_N => O_MEM_WE_N, + UB_N => O_MEM_BE_N(3), + LB_N => O_MEM_BE_N(2), + ADDR => O_MEM_ADDR, + DATA => IO_MEM_DATA(31 downto 16) + ); + + UUT : s3_sram_memctl + port map ( + CLK => CLK, + RESET => RESET, + REQ => REQ, + WE => WE, + BUSY => BUSY, + ACK_R => ACK_R, + ACK_W => ACK_W, + ACT_R => ACT_R, + ACT_W => ACT_W, + ADDR => ADDR, + BE => BE, + DI => DI, + DO => DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + proc_stim: process + file fstim : text open read_mode is "tb_s3_sram_memctl_stim"; + variable iline : line; + variable oline : line; + variable ok : boolean; + variable dname : string(1 to 6) := (others=>' '); + variable idelta : integer := 0; + variable iaddr : slv18 := (others=>'0'); + variable idata : slv32 := (others=>'0'); + variable ibe : slv4 := (others=>'0'); + variable ival : slbit := '0'; + variable nbusy : integer := 0; + + begin + + wait for clock_offset - setup_time; + + file_loop: while not endfile(fstim) loop + + readline (fstim, iline); + + readcomment(iline, ok); + next file_loop when ok; + + readword(iline, dname, ok); + if ok then + case dname is + when ".memon" => -- .memon + read_ea(iline, ival); + R_MEMON <= ival; + wait for 2*clock_period; + + when ".reset" => -- .reset + write(oline, string'(".reset")); + writeline(output, oline); + RESET <= '1'; + wait for clock_period; + RESET <= '0'; + wait for 9*clock_period; + + when ".wait " => -- .wait + read_ea(iline, idelta); + wait for idelta*clock_period; + + when "read " => -- read + readgen_ea(iline, iaddr, 16); + readgen_ea(iline, idata, 16); + ADDR <= iaddr; + REQ <= '1'; + WE <= '0'; + + writetimestamp(oline, CLK_CYCLE, ": stim read "); + writegen(oline, iaddr, right, 6, 16); + write(oline, string'(" ")); + writegen(oline, idata, right, 9, 16); + + nbusy := 0; + while BUSY = '1' loop + nbusy := nbusy + 1; + wait for clock_period; + end loop; + + write(oline, string'(" nbusy=")); + write(oline, nbusy, right, 2); + writeline(output, oline); + + N_CHK_DATA <= '1', '0' after clock_period; + N_REF_DATA <= idata; + N_REF_ADDR <= iaddr; + + wait for clock_period; + REQ <= '0'; + + when "write " => -- write + readgen_ea(iline, iaddr, 16); + read_ea(iline, ibe); + readgen_ea(iline, idata, 16); + ADDR <= iaddr; + BE <= ibe; + DI <= idata; + REQ <= '1'; + WE <= '1'; + + writetimestamp(oline, CLK_CYCLE, ": stim write"); + writegen(oline, iaddr, right, 6, 16); + writegen(oline, ibe , right, 5, 2); + writegen(oline, idata, right, 9, 16); + + nbusy := 0; + while BUSY = '1' loop + nbusy := nbusy + 1; + wait for clock_period; + end loop; + + write(oline, string'(" nbusy=")); + write(oline, nbusy, right, 2); + writeline(output, oline); + + wait for clock_period; + REQ <= '0'; + + when others => -- bad directive + write(oline, string'("?? unknown directive: ")); + write(oline, dname); + writeline(output, oline); + report "aborting" severity failure; + end case; + else + report "failed to find command" severity failure; + + end if; + + testempty_ea(iline); + + end loop; -- file fstim + + wait for 10*clock_period; + + writetimestamp(oline, CLK_CYCLE, ": DONE "); + writeline(output, oline); + + CLK_STOP <= '1'; + + wait; -- suspend proc_stim forever + -- clock is stopped, sim will end + + end process proc_stim; + + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLK); + + if ACK_R = '1' then + writetimestamp(oline, CLK_CYCLE, ": moni "); + writegen(oline, DO, right, 9, 16); + if R_CHK_DATA_DL = '1' then + write(oline, string'(" CHECK")); + if R_REF_DATA_DL = DO then + write(oline, string'(" OK")); + else + write(oline, string'(" FAIL, exp=")); + writegen(oline, R_REF_DATA_DL, right, 9, 16); + write(oline, string'(" for a=")); + writegen(oline, R_REF_ADDR_DL, right, 5, 16); + end if; + R_CHK_DATA_DL <= '0'; + end if; + writeline(output, oline); + end if; + + if R_CHK_DATA_AL = '1' then + R_CHK_DATA_DL <= R_CHK_DATA_AL; + R_REF_DATA_DL <= R_REF_DATA_AL; + R_REF_ADDR_DL <= R_REF_ADDR_AL; + R_CHK_DATA_AL <= '0'; + end if; + if N_CHK_DATA = '1' then + R_CHK_DATA_AL <= N_CHK_DATA; + R_REF_DATA_AL <= N_REF_DATA; + R_REF_ADDR_AL <= N_REF_ADDR; + end if; + + end loop; + + end process proc_moni; + + + proc_memon: process + variable oline : line; + begin + + loop + wait until rising_edge(CLK); + + if R_MEMON = '1' then + writetimestamp(oline, CLK_CYCLE, ": mem "); + write(oline, string'(" ce=")); + write(oline, not O_MEM_CE_N, right, 2); + write(oline, string'(" be=")); + write(oline, not O_MEM_BE_N, right, 4); + write(oline, string'(" we=")); + write(oline, not O_MEM_WE_N, right); + write(oline, string'(" oe=")); + write(oline, not O_MEM_OE_N, right); + write(oline, string'(" a=")); + writegen(oline, O_MEM_ADDR, right, 5, 16); + write(oline, string'(" d=")); + writegen(oline, IO_MEM_DATA, right, 8, 16); + writeline(output, oline); + end if; + + end loop; + + end process proc_memon; + + +end sim; Index: rtl/w11a/tb/Makefile =================================================================== --- rtl/w11a/tb/Makefile (revision 15) +++ rtl/w11a/tb/Makefile (revision 16) @@ -1,4 +1,4 @@ -# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $ +# $Id: Makefile 442 2011-12-23 10:03:28Z mueller $ # # Revision History: # Date Rev Version Comment @@ -9,7 +9,7 @@ # 2007-07-06 64 1.1 use vbom's # 2007-06-17 58 1.0 Initial version # -EXE_all = tb_pdp11core tb_rlink_tba_pdp11core +EXE_all = tb_pdp11core # # .PHONY : all all_ssim all_tsim clean Index: rtl/vlib/rlink/rlink_serport.vhd =================================================================== --- rtl/vlib/rlink/rlink_serport.vhd (revision 15) +++ rtl/vlib/rlink/rlink_serport.vhd (nonexistent) @@ -1,242 +0,0 @@ --- $Id: rlink_serport.vhd 427 2011-11-19 21:04:11Z mueller $ --- --- Copyright 2007-2011 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: rlink_serport - syn --- Description: rlink: serport adapter (serial to rlink_base) --- --- Dependencies: serport/serport_uart_rxtx_ab --- --- Test bench: tb/tb_rlink_serport --- --- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29 --- --- Synthesized (xst): --- Date Rev ise Target flop lutl lutm slic t peri --- 2010-12-26 348 12.1 M53d xc3s1000-4 122 227 - 152 s 9.8 --- --- Revision History: --- Date Rev Version Comment --- 2011-11-19 427 3.1.2 now numeric_std clean --- 2011-08-14 406 3.1.1 cleaner code for RL_SER_MONI.clkdiv assignment --- 2010-12-25 348 3.1 re-written, is now a serial to rlink_base adapter --- 2010-12-24 347 3.0.1 rename: CP_*->RL->* --- 2010-12-04 343 3.0 renamed rri_ -> rlink_ --- 2010-06-06 301 2.3 use NCOMM=4 (new eop,nak commas) --- 2010-06-03 300 2.2.1 use FAWIDTH=5 --- 2010-05-02 287 2.2 drop RTSFLUSH generic --- 2010-04-18 279 2.1 rewrite flow control, drop RTSFBUF generic --- 2010-04-03 274 2.0 flow control interfaces: RTSFLUSH, CTS_N, RTS_N --- 2007-06-24 60 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; -use work.serport.all; -use work.rblib.all; -use work.rlinklib.all; - -entity rlink_serport is -- rlink serport adapter - generic ( - RB_ADDR : slv8 := slv(to_unsigned(2#11111110#,8)); - CDWIDTH : positive := 13; -- clk divider width - CDINIT : natural := 15); -- clk divider initial/reset setting - port ( - CLK : in slbit; -- clock - CE_USEC : in slbit; -- 1 usec clock enable - CE_MSEC : in slbit; -- 1 msec clock enable - RESET : in slbit; -- reset - RXSD : in slbit; -- receive serial data (board view) - TXSD : out slbit; -- transmit serial data (board view) - CTS_N : in slbit := '0'; -- clear to send (act.low, board view) - RTS_N : out slbit; -- request to send (act.low, board view) - RLB_DI : out slv8; -- rlink 8b: data in - RLB_ENA : out slbit; -- rlink 8b: data enable - RLB_BUSY : in slbit; -- rlink 8b: data busy - RLB_DO : in slv8; -- rlink 8b: data out - RLB_VAL : in slbit; -- rlink 8b: data valid - RLB_HOLD : out slbit; -- rlink 8b: data hold - RB_MREQ : in rb_mreq_type; -- rbus: request (for inits only) - IFIFO_SIZE : in slv4; -- rlink_rlb2rb: input fifo size - RL_MONI : in rl_moni_type; -- rlink_core: monitor port - RL_SER_MONI : out rl_ser_moni_type -- rlink_serport: monitor port - ); -end rlink_serport; - - -architecture syn of rlink_serport is - - type regs_type is record - flpend : slbit; -- flush pending - fldbusy : slbit; -- flush delay busy - fldcnt : slv3; -- flush delay counter - flpbusy : slbit; -- flush pulse busy - flpcnt : slv3; -- flush pulse counter - ffblock : slbit; -- fifo block - fena : slbit; -- flush enable - fwidth : slv3; -- flush pulse width - fdelay : slv3; -- flush pulse delay - rtsoff : slv3; -- rts off level (fifo high water) - rtson : slv3; -- rts on level (fifo low water) - end record regs_type; - - constant regs_init : regs_type := ( - '0','0',"000", -- flpend,fldbusy,fldcnt - '0',"000", -- flpbusy,flpcnt - '0', -- ffblock - '0', -- fena - "000","000", -- fwidth,fdelay - "111","110" -- rtsoff,rtson - ); - - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs - - signal RXVAL : slbit := '0'; - signal RXERR : slbit := '0'; - signal RXACT : slbit := '0'; - signal TXBUSY : slbit := '0'; - signal ABACT : slbit := '0'; - signal ABDONE : slbit := '0'; - signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0'); - -begin - - assert CDWIDTH<=16 - report "assert(CDWIDTH<=16): max width of UART clock divider" - severity failure; - - UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo - generic map ( - CDWIDTH => CDWIDTH, - CDINIT => CDINIT) - port map ( - CLK => CLK, - CE_MSEC => CE_MSEC, - RESET => RESET, - RXSD => RXSD, - RXDATA => RLB_DI, - RXVAL => RXVAL, - RXERR => RXERR, - RXACT => RXACT, - TXSD => TXSD, - TXDATA => RLB_DO, - TXENA => RLB_VAL, - TXBUSY => TXBUSY, - ABACT => ABACT, - ABDONE => ABDONE, - ABCLKDIV => ABCLKDIV(CDWIDTH-1 downto 0) - ); - - proc_regs: process (CLK) - begin - - if rising_edge(CLK) then - if RESET = '1' then - R_REGS <= regs_init; - else - R_REGS <= N_REGS; - end if; - end if; - - end process proc_regs; - - proc_next: process (R_REGS, RB_MREQ, IFIFO_SIZE, RL_MONI, TXBUSY, CE_USEC) - - variable r : regs_type := regs_init; - variable n : regs_type := regs_init; - - begin - - r := R_REGS; - n := R_REGS; - - -- handle init - if RB_MREQ.init='1' and RB_MREQ.we='0' and RB_MREQ.addr=RB_ADDR then - n.fena := RB_MREQ.din(c_rlink_serport_rbf_fena); - n.fwidth := RB_MREQ.din(c_rlink_serport_rbf_fwidth); - n.fdelay := RB_MREQ.din(c_rlink_serport_rbf_fdelay); - n.rtsoff := RB_MREQ.din(c_rlink_serport_rbf_rtsoff); - n.rtson := RB_MREQ.din(c_rlink_serport_rbf_rtson); - end if; - - -- fifo back preasure - if IFIFO_SIZE(3)='1' or - unsigned(IFIFO_SIZE(2 downto 0))>unsigned(r.rtsoff) then - n.ffblock := '1'; - elsif unsigned(IFIFO_SIZE(2 downto 0)) <= unsigned(r.rtson) then - n.ffblock := '0'; - end if; - - -- send flush pulse if - -- eop send unless a pending attn - -- or an attn was send - - if (RL_MONI.eop='1' and RL_MONI.lamp='0') or RL_MONI.attn='1' then - n.flpend := r.fena; - end if; - - -- flush pulse logic - -- start delay when flpend is set - -- re-start delay when TXBUSY=1 - -- when timer expires, clear flpend, start pulse - - if r.flpend='1' and (r.fldbusy='0' or TXBUSY='1') then - n.fldbusy := '1'; - n.fldcnt := r.fdelay; - elsif CE_USEC='1' and r.fldbusy='1' then - if unsigned(r.fldcnt) = 0 then - n.flpend := '0'; - n.fldbusy := '0'; - n.flpbusy := '1'; - n.flpcnt := r.fwidth; - else - n.fldcnt := slv(unsigned(r.fldcnt) - 1); - end if; - end if; - - if CE_USEC='1' and r.flpbusy='1' then - if unsigned(r.flpcnt) = 0 then - n.flpbusy := '0'; - else - n.flpcnt := slv(unsigned(r.flpcnt) - 1); - end if; - end if; - - N_REGS <= n; - - end process proc_next; - - RTS_N <= R_REGS.ffblock or R_REGS.flpbusy; - - RLB_ENA <= RXVAL; - RLB_HOLD <= TXBUSY or CTS_N; - - RL_SER_MONI.rxerr <= RXERR; - RL_SER_MONI.rxdrop <= RXVAL and RLB_BUSY; - RL_SER_MONI.rxact <= RXACT; - RL_SER_MONI.txact <= TXBUSY; - RL_SER_MONI.abact <= ABACT; - RL_SER_MONI.abdone <= ABDONE; - - proc_clkdiv: process (ABCLKDIV) - begin - RL_SER_MONI.clkdiv <= (others=>'0'); - RL_SER_MONI.clkdiv(ABCLKDIV'range) <= ABCLKDIV; - end process proc_clkdiv; - -end syn; Index: rtl/vlib/rlink/rlink_rlb2rl.vhd =================================================================== --- rtl/vlib/rlink/rlink_rlb2rl.vhd (revision 15) +++ rtl/vlib/rlink/rlink_rlb2rl.vhd (nonexistent) @@ -1,208 +0,0 @@ --- $Id: rlink_rlb2rl.vhd 427 2011-11-19 21:04:11Z mueller $ --- --- Copyright 2010- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: rlink_rlb2rl - syn --- Description: rlink 8 bit(rlb) to 9 bit(rl) adapter --- --- Dependencies: comlib/byte2cdata --- comlib/cdata2byte --- memlib/fifo_1c_dram --- --- Test bench: tb/rb_rlink_serport --- --- Target Devices: generic --- Tool versions: xst 12.1; ghdl 0.29 --- --- Synthesized (xst): --- Date Rev ise Target flop lutl lutm slic t peri ifa ofa --- 2010-12-25 348 12.1 M53d xc3s1000-4 61 121 72 114 s 8.3 5 5 --- 2010-12-25 348 12.1 M53d xc3s1000-4 41 84 36 73 s 8.3 5 0 --- 2010-12-25 348 12.1 M53d xc3s1000-4 22 50 - 30 s 4.5 0 0 --- --- Revision History: --- Date Rev Version Comment --- 2010-12-24 348 1.0 Initial version ------------------------------------------------------------------------------- --- --- byte2cdata fifo_1c_dram --- +--------------+ +--------------+ --- | | | | --- RLB_DI ->| DI DO |--->| DI DO |-> RL_DI --- | | | | --- RLB_ENA ->| ENA VAL |--->| ENA VAL |-> RL_ENA --- | | | | --- RLB_BUSY <-| BUSY HOLD |<---| BUSY HOLD |<- RL_BUSY --- | | | | --- +--------------+ | | --- | | --- +---+ | | --- IFIFO_FILL <------------|map|<---| SIZE | --- +---+ +--------------+ --- --- --- cdata2byte fifo_1c_dram --- +--------------+ +--------------+ --- | | | | --- RLB_DO <-| DO DI |<---| DO DI |<- RL_DO --- | | | | --- RLB_VAL <-| VAL ENA |<---| VAL ENA |<- RL_VAL --- | | | | --- RLB_HOLD ->| HOLD BUSY |--->| HOLD BUSY |-> RL_HOLD --- | | | | --- +--------------+ | | --- | | --- +---+ | | --- OFIFO_FILL <------------|map|<---| SIZE | --- +---+ +--------------+ --- - - -library ieee; -use ieee.std_logic_1164.all; - -use work.slvtypes.all; -use work.comlib.all; -use work.memlib.all; -use work.rlinklib.all; - -entity rlink_rlb2rl is -- rlink 8 bit(rlb) to 9 bit(rl) adapter - generic ( - CPREF : slv4 := "1000"; -- comma prefix - IFAWIDTH : natural := 5; -- input fifo address width (0=none) - OFAWIDTH : natural := 5); -- output fifo address width (0=none) - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - RLB_DI : in slv8; -- rlink 8bit: data in - RLB_ENA : in slbit; -- rlink 8bit: data enable - RLB_BUSY : out slbit; -- rlink 8bit: data busy - RLB_DO : out slv8; -- rlink 8bit: data out - RLB_VAL : out slbit; -- rlink 8bit: data valid - RLB_HOLD : in slbit; -- rlink 8bit: data hold - IFIFO_SIZE : out slv4; -- input fifo size (4 msb's) - OFIFO_SIZE : out slv4; -- output fifo fill (4 msb's) - RL_DI : out slv9; -- rlink 9bit: data in - RL_ENA : out slbit; -- rlink 9bit: data enable - RL_BUSY : in slbit; -- rlink 9bit: data busy - RL_DO : in slv9; -- rlink 9bit: data out - RL_VAL : in slbit; -- rlink 9bit: data valid - RL_HOLD : out slbit -- rlink 9bit: data hold - ); -end rlink_rlb2rl; - -architecture syn of rlink_rlb2rl is - - signal RLB_BUSY_L : slbit := '0'; - signal IFIFO_DI : slv9 := (others=>'0'); - signal IFIFO_ENA : slbit := '0'; - signal IFIFO_BUSY : slbit := '0'; - signal OFIFO_DO : slv9 := (others=>'0'); - signal OFIFO_VAL : slbit := '0'; - signal OFIFO_HOLD : slbit := '0'; - -begin - --- RLB -> RL converter (DI handling) ------------- - - B2CD : byte2cdata -- byte stream -> 9bit comma,data - generic map ( - CPREF => CPREF, - NCOMM => c_rlink_ncomm) - port map ( - CLK => CLK, - RESET => RESET, - DI => RLB_DI, - ENA => RLB_ENA, - BUSY => RLB_BUSY_L, - DO => IFIFO_DI, - VAL => IFIFO_ENA, - HOLD => IFIFO_BUSY - ); - - DOIFIFO: if IFAWIDTH > 0 generate - signal SIZE: slv(IFAWIDTH downto 0) := (others=>'0'); - begin - IFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based - generic map ( - AWIDTH => IFAWIDTH, - DWIDTH => 9) - port map ( - CLK => CLK, - RESET => RESET, - DI => IFIFO_DI, - ENA => IFIFO_ENA, - BUSY => IFIFO_BUSY, - DO => RL_DI, - VAL => RL_ENA, - HOLD => RL_BUSY, - SIZE => SIZE - ); - IFIFO_SIZE <= SIZE(IFAWIDTH downto IFAWIDTH-3); - end generate DOIFIFO; - - NOIFIFO: if IFAWIDTH = 0 generate - RL_DI <= IFIFO_DI; - RL_ENA <= IFIFO_ENA; - IFIFO_BUSY <= RL_BUSY; - IFIFO_SIZE <= RLB_BUSY_L & "000"; - end generate NOIFIFO; - - RLB_BUSY <= RLB_BUSY_L; - --- RL -> RLB converter (DO handling) ------------- - - CD2B : cdata2byte -- 9bit comma,data -> byte stream - generic map ( - CPREF => CPREF, - NCOMM => c_rlink_ncomm) - port map ( - CLK => CLK, - RESET => RESET, - DI => OFIFO_DO, - ENA => OFIFO_VAL, - BUSY => OFIFO_HOLD, - DO => RLB_DO, - VAL => RLB_VAL, - HOLD => RLB_HOLD - ); - - DOOFIFO: if OFAWIDTH > 0 generate - signal SIZE : slv(OFAWIDTH downto 0) := (others=>'0'); - begin - OFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based - generic map ( - AWIDTH => OFAWIDTH, - DWIDTH => 9) - port map ( - CLK => CLK, - RESET => RESET, - DI => RL_DO, - ENA => RL_VAL, - BUSY => RL_HOLD, - DO => OFIFO_DO, - VAL => OFIFO_VAL, - HOLD => OFIFO_HOLD, - SIZE => SIZE - ); - OFIFO_SIZE <= SIZE(OFAWIDTH downto OFAWIDTH-3); - end generate DOOFIFO; - - NOOFIFO: if OFAWIDTH = 0 generate - OFIFO_DO <= RL_DO; - OFIFO_VAL <= RL_VAL; - RL_HOLD <= OFIFO_HOLD; - OFIFO_SIZE <= OFIFO_HOLD & "000"; - end generate NOOFIFO; - -end syn; Index: rtl/vlib/rlink/rlink_base_serport.vbom =================================================================== --- rtl/vlib/rlink/rlink_base_serport.vbom (revision 15) +++ rtl/vlib/rlink/rlink_base_serport.vbom (nonexistent) @@ -1,9 +0,0 @@ -# libs -../slvtypes.vhd -../rbus/rblib.vhd -rlinklib.vbom -# components -rlink_base.vbom -rlink_serport.vbom -# design -rlink_base_serport.vhd Index: rtl/vlib/rlink/rlink_base.vbom =================================================================== --- rtl/vlib/rlink/rlink_base.vbom (revision 15) +++ rtl/vlib/rlink/rlink_base.vbom (nonexistent) @@ -1,11 +0,0 @@ -# libs -../slvtypes.vhd -../rbus/rblib.vhd -rlinklib.vbom -# components -rlink_core.vbom -rlink_rlb2rl.vbom -[ghdl,isim]rlink_mon_sb.vbom -[ghdl,isim]../rbus/rb_mon_sb.vbom -# design -rlink_base.vhd Index: rtl/vlib/rlink/rlink_rlb2rl.vbom =================================================================== --- rtl/vlib/rlink/rlink_rlb2rl.vbom (revision 15) +++ rtl/vlib/rlink/rlink_rlb2rl.vbom (nonexistent) @@ -1,11 +0,0 @@ -# libs -../slvtypes.vhd -../comlib/comlib.vhd -../memlib/memlib.vhd -rlinklib.vbom -# components -../comlib/byte2cdata.vbom -../comlib/cdata2byte.vbom -../memlib/fifo_1c_dram.vbom -# design -rlink_rlb2rl.vhd Index: rtl/vlib/rlink/rlink_base_serport.vhd =================================================================== --- rtl/vlib/rlink/rlink_base_serport.vhd (revision 15) +++ rtl/vlib/rlink/rlink_base_serport.vhd (nonexistent) @@ -1,159 +0,0 @@ --- $Id: rlink_base_serport.vhd 427 2011-11-19 21:04:11Z mueller $ --- --- Copyright 2010-2011 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: rlink_base_serport - syn --- Description: rlink base + serport combo --- --- Dependencies: rlink_base --- rlink_serport --- --- Test bench: - --- --- Target Devices: generic --- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29 --- --- Synthesized (xst): --- Date Rev ise Target flop lutl lutm slic t peri ifa ofa --- 2010-12-26 348 12.1 M53d xc3s1000-4 332 687 72 463 s 10.2 5 5 --- 2010-12-26 348 12.1 M53d xc3s1000-4 320 651 36 425 s 10.2 5 0 --- 2010-12-26 301 12.1 M53d xc3s1000-4 289 619 36 394 s 9.9 - - --- 2010-04-03 275 11.4 L68 xc3s1000-4 280 600 18 375 s 8.9 - - --- --- Revision History: --- Date Rev Version Comment --- 2011-11-19 427 3.1.1 now numeric_std clean --- 2010-12-26 348 3.1 rename from rlink_core_serport, use now rlink_base --- 2010-12-24 347 3.0.1 rename: CP_*->RL->* --- 2010-12-04 343 3.0 renamed rri_ -> rlink_ --- 2010-06-05 301 1.2.2 renamed _rpmon -> _rbmon --- 2010-06-03 300 1.2.1 use FAWIDTH=5 --- 2010-05-02 287 1.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM --- drop RP_IINT from interfaces; drop RTSFLUSH generic --- 2010-04-18 279 1.1 drop RTSFBUF generic --- 2010-04-10 275 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; -use work.rblib.all; -use work.rlinklib.all; - -entity rlink_base_serport is -- rlink base+serport combo - generic ( - ATOWIDTH : positive := 5; -- access timeout counter width - ITOWIDTH : positive := 6; -- idle timeout counter width - CPREF : slv4 := c_rlink_cpref; -- comma prefix - IFAWIDTH : natural := 5; -- input fifo address width (0=none) - OFAWIDTH : natural := 5; -- output fifo address width (0=none) - ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none) - ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none) - RB_ADDR : slv8 := slv(to_unsigned(2#11111110#,8)); - CDWIDTH : positive := 13; -- clk divider width - CDINIT : natural := 15); -- clk divider initial/reset setting - port ( - CLK : in slbit; -- clock - CE_USEC : in slbit; -- 1 usec clock enable - CE_MSEC : in slbit; -- 1 msec clock enable - CE_INT : in slbit := '0'; -- rlink ito time unit clock enable - RESET : in slbit; -- reset - RXSD : in slbit; -- receive serial data (board view) - TXSD : out slbit; -- transmit serial data (board view) - CTS_N : in slbit := '0'; -- clear to send (act.low, board view) - RTS_N : out slbit; -- request to send (act.low, board view) - RB_MREQ : out rb_mreq_type; -- rbus: request - RB_SRES : in rb_sres_type; -- rbus: response - RB_LAM : in slv16; -- rbus: look at me - RB_STAT : in slv3; -- rbus: status flags - RL_MONI : out rl_moni_type; -- rlink_core: monitor port - RL_SER_MONI : out rl_ser_moni_type -- rlink_serport: monitor port - ); -end entity rlink_base_serport; - - -architecture syn of rlink_base_serport is - - signal RLB_DI : slv8 := (others=>'0'); - signal RLB_ENA : slbit := '0'; - signal RLB_BUSY : slbit := '0'; - signal RLB_DO : slv8 := (others=>'0'); - signal RLB_VAL : slbit := '0'; - signal RLB_HOLD : slbit := '0'; - signal IFIFO_SIZE : slv4 := (others=>'0'); - - signal RL_MONI_L : rl_moni_type := rl_moni_init; -- local, readable RL_MONI - signal RB_MREQ_L : rb_mreq_type := rb_mreq_init; -- local, readable RB_MREQ - -begin - - BASE : rlink_base - generic map ( - ATOWIDTH => ATOWIDTH, - ITOWIDTH => ITOWIDTH, - CPREF => CPREF, - IFAWIDTH => IFAWIDTH, - OFAWIDTH => OFAWIDTH, - ENAPIN_RLMON => ENAPIN_RLMON, - ENAPIN_RBMON => ENAPIN_RBMON) - port map ( - CLK => CLK, - CE_INT => CE_INT, - RESET => RESET, - RLB_DI => RLB_DI, - RLB_ENA => RLB_ENA, - RLB_BUSY => RLB_BUSY, - RLB_DO => RLB_DO, - RLB_VAL => RLB_VAL, - RLB_HOLD => RLB_HOLD, - IFIFO_SIZE => IFIFO_SIZE, - OFIFO_SIZE => open, - RL_MONI => RL_MONI_L, - RB_MREQ => RB_MREQ_L, - RB_SRES => RB_SRES, - RB_LAM => RB_LAM, - RB_STAT => RB_STAT - ); - - RL_MONI <= RL_MONI_L; - RB_MREQ <= RB_MREQ_L; - - SERPORT : rlink_serport - generic map ( - RB_ADDR => RB_ADDR, - CDWIDTH => CDWIDTH, - CDINIT => CDINIT) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC, - RESET => RESET, - RXSD => RXSD, - TXSD => TXSD, - CTS_N => CTS_N, - RTS_N => RTS_N, - RLB_DI => RLB_DI, - RLB_ENA => RLB_ENA, - RLB_BUSY => RLB_BUSY, - RLB_DO => RLB_DO, - RLB_VAL => RLB_VAL, - RLB_HOLD => RLB_HOLD, - RB_MREQ => RB_MREQ_L, - IFIFO_SIZE => IFIFO_SIZE, - RL_MONI => RL_MONI_L, - RL_SER_MONI=> RL_SER_MONI - ); - -end syn; Index: rtl/vlib/rlink/rlink_base.vhd =================================================================== --- rtl/vlib/rlink/rlink_base.vhd (revision 15) +++ rtl/vlib/rlink/rlink_base.vhd (nonexistent) @@ -1,175 +0,0 @@ --- $Id: rlink_base.vhd 427 2011-11-19 21:04:11Z mueller $ --- --- Copyright 2010-2011 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: rlink_base - syn --- Description: rlink base: core+rl2rlb+rlmon+rbmon - w/ buffered 8bit iface --- --- Dependencies: rlink_core --- rlink_rlb2rl --- rlink_mon_sb [sim only] --- rbus/rb_mon_sb [sim only] --- --- Test bench: tb/tb_rlink_serport --- tb/tb_rlink_tba_ttcombo --- --- Target Devices: generic --- Tool versions: xst 12.1, 13.1; ghdl 0.29 --- --- Synthesized (xst): --- Date Rev ise Target flop lutl lutm slic t peri ifa ofa --- 2010-12-25 348 12.1 M53d xc3s1000-4 206 451 72 304 s 10.5 5 5 --- 2010-12-25 348 12.1 M53d xc3s1000-4 194 407 36 262 s 10.4 5 0 --- --- Revision History: --- Date Rev Version Comment --- 2011-11-19 427 1.0.1 now numeric_std clean --- 2010-12-25 348 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; -use work.rblib.all; -use work.rlinklib.all; - -entity rlink_base is -- rlink base: core+rlb2rl+rlmon+rbmon - -- with buffered 8bit interface - generic ( - ATOWIDTH : positive := 5; -- access timeout counter width - ITOWIDTH : positive := 6; -- idle timeout counter width - CPREF : slv4 := c_rlink_cpref; -- comma prefix - IFAWIDTH : natural := 5; -- input fifo address width (0=none) - OFAWIDTH : natural := 5; -- output fifo address width (0=none) - ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none) - ENAPIN_RBMON : integer := sbcntl_sbf_rbmon); -- SB_CNTL for rbmon (-1=none) - port ( - CLK : in slbit; -- clock - CE_INT : in slbit := '0'; -- rlink ito time unit clock enable - RESET : in slbit; -- reset - RLB_DI : in slv8; -- rlink 8b: data in - RLB_ENA : in slbit; -- rlink 8b: data enable - RLB_BUSY : out slbit; -- rlink 8b: data busy - RLB_DO : out slv8; -- rlink 8b: data out - RLB_VAL : out slbit; -- rlink 8b: data valid - RLB_HOLD : in slbit; -- rlink 8b: data hold - IFIFO_SIZE : out slv4; -- input fifo size (4 msb's) - OFIFO_SIZE : out slv4; -- output fifo fill (4 msb's) - RL_MONI : out rl_moni_type; -- rlink: monitor port - RB_MREQ : out rb_mreq_type; -- rbus: request - RB_SRES : in rb_sres_type; -- rbus: response - RB_LAM : in slv16; -- rbus: look at me - RB_STAT : in slv3 -- rbus: status flags - ); -end entity rlink_base; - - -architecture syn of rlink_base is - - signal RL_DI : slv9 := (others=>'0'); - signal RL_ENA : slbit := '0'; - signal RL_BUSY : slbit := '0'; - signal RL_DO : slv9 := (others=>'0'); - signal RL_VAL : slbit := '0'; - signal RL_HOLD : slbit := '0'; - signal RB_MREQ_L : rb_mreq_type := rb_mreq_init; -- local, readable RB_MREQ - -begin - - RL : rlink_core - generic map ( - ATOWIDTH => ATOWIDTH, - ITOWIDTH => ITOWIDTH) - port map ( - CLK => CLK, - CE_INT => CE_INT, - RESET => RESET, - RL_DI => RL_DI, - RL_ENA => RL_ENA, - RL_BUSY => RL_BUSY, - RL_DO => RL_DO, - RL_VAL => RL_VAL, - RL_HOLD => RL_HOLD, - RL_MONI => RL_MONI, - RB_MREQ => RB_MREQ_L, - RB_SRES => RB_SRES, - RB_LAM => RB_LAM, - RB_STAT => RB_STAT - ); - -- vhdl'93 unfortunately doesn't allow to read a signal bound to an out port - -- because RB_MREQ is read by the monitors, an extra internal - -- signal must be used. This will not be needed with vhdl'2000 anymore - - RB_MREQ <= RB_MREQ_L; - - RLB2RL : rlink_rlb2rl - generic map ( - CPREF => CPREF, - IFAWIDTH => IFAWIDTH, - OFAWIDTH => OFAWIDTH) - port map ( - CLK => CLK, - RESET => RESET, - RLB_DI => RLB_DI, - RLB_ENA => RLB_ENA, - RLB_BUSY => RLB_BUSY, - RLB_DO => RLB_DO, - RLB_VAL => RLB_VAL, - RLB_HOLD => RLB_HOLD, - IFIFO_SIZE => IFIFO_SIZE, - OFIFO_SIZE => OFIFO_SIZE, - RL_DI => RL_DI, - RL_ENA => RL_ENA, - RL_BUSY => RL_BUSY, - RL_DO => RL_DO, - RL_VAL => RL_VAL, - RL_HOLD => RL_HOLD - ); - --- synthesis translate_off - - RLMON: if ENAPIN_RLMON >= 0 generate - MON : rlink_mon_sb - generic map ( - DWIDTH => RL_DI'length, - ENAPIN => ENAPIN_RLMON) - port map ( - CLK => CLK, - RL_DI => RL_DI, - RL_ENA => RL_ENA, - RL_BUSY => RL_BUSY, - RL_DO => RL_DO, - RL_VAL => RL_VAL, - RL_HOLD => RL_HOLD - ); - end generate RLMON; - - RBMON: if ENAPIN_RBMON >= 0 generate - MON : rb_mon_sb - generic map ( - DBASE => 8, - ENAPIN => ENAPIN_RBMON) - port map ( - CLK => CLK, - RB_MREQ => RB_MREQ_L, - RB_SRES => RB_SRES, - RB_LAM => RB_LAM, - RB_STAT => RB_STAT - ); - end generate RBMON; - --- synthesis translate_on - -end syn; Index: rtl/vlib/rlink/rlink_serport.vbom =================================================================== --- rtl/vlib/rlink/rlink_serport.vbom (revision 15) +++ rtl/vlib/rlink/rlink_serport.vbom (nonexistent) @@ -1,9 +0,0 @@ -# libs -../slvtypes.vhd -../serport/serport.vhd -../rbus/rblib.vhd -rlinklib.vbom -# components -../serport/serport_uart_rxtx_ab.vbom -# design -rlink_serport.vhd Index: rtl/vlib/rlink/rlink_core8.vhd =================================================================== --- rtl/vlib/rlink/rlink_core8.vhd (nonexistent) +++ rtl/vlib/rlink/rlink_core8.vhd (revision 16) @@ -0,0 +1,174 @@ +-- $Id: rlink_core8.vhd 440 2011-12-18 20:08:09Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rlink_core8 - syn +-- Description: rlink core with 8bit interface (core+b2c/c2b+rlmon+rbmon) +-- +-- Dependencies: rlink_core +-- comlib/byte2cdata +-- comlib/cdata2byte +-- rlink_mon_sb [sim only] +-- rbus/rb_mon_sb [sim only] +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-12-09 437 13.1 O40d xc3s1000-4 184 403 0 244 s 9.1 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-09 437 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.comlib.all; +use work.rblib.all; +use work.rlinklib.all; + +entity rlink_core8 is -- rlink core with 8bit interface + generic ( + ATOWIDTH : positive := 5; -- access timeout counter width + ITOWIDTH : positive := 6; -- idle timeout counter width + CPREF : slv4 := c_rlink_cpref; -- comma prefix + ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none) + ENAPIN_RBMON : integer := sbcntl_sbf_rbmon); -- SB_CNTL for rbmon (-1=none) + port ( + CLK : in slbit; -- clock + CE_INT : in slbit := '0'; -- rlink ito time unit clock enable + RESET : in slbit; -- reset + RLB_DI : in slv8; -- rlink 8b: data in + RLB_ENA : in slbit; -- rlink 8b: data enable + RLB_BUSY : out slbit; -- rlink 8b: data busy + RLB_DO : out slv8; -- rlink 8b: data out + RLB_VAL : out slbit; -- rlink 8b: data valid + RLB_HOLD : in slbit; -- rlink 8b: data hold + RL_MONI : out rl_moni_type; -- rlink: monitor port + RB_MREQ : out rb_mreq_type; -- rbus: request + RB_SRES : in rb_sres_type; -- rbus: response + RB_LAM : in slv16; -- rbus: look at me + RB_STAT : in slv3 -- rbus: status flags + ); +end entity rlink_core8; + + +architecture syn of rlink_core8 is + + signal RL_DI : slv9 := (others=>'0'); + signal RL_ENA : slbit := '0'; + signal RL_BUSY : slbit := '0'; + signal RL_DO : slv9 := (others=>'0'); + signal RL_VAL : slbit := '0'; + signal RL_HOLD : slbit := '0'; + signal RB_MREQ_L : rb_mreq_type := rb_mreq_init; -- local, readable RB_MREQ + +begin + + RL : rlink_core + generic map ( + ATOWIDTH => ATOWIDTH, + ITOWIDTH => ITOWIDTH) + port map ( + CLK => CLK, + CE_INT => CE_INT, + RESET => RESET, + RL_DI => RL_DI, + RL_ENA => RL_ENA, + RL_BUSY => RL_BUSY, + RL_DO => RL_DO, + RL_VAL => RL_VAL, + RL_HOLD => RL_HOLD, + RL_MONI => RL_MONI, + RB_MREQ => RB_MREQ_L, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT + ); + + RB_MREQ <= RB_MREQ_L; + +-- RLB -> RL converter (DI handling) ------------- + B2CD : byte2cdata -- byte stream -> 9bit comma,data + generic map ( + CPREF => CPREF, + NCOMM => c_rlink_ncomm) + port map ( + CLK => CLK, + RESET => RESET, + DI => RLB_DI, + ENA => RLB_ENA, + BUSY => RLB_BUSY, + DO => RL_DI, + VAL => RL_ENA, + HOLD => RL_BUSY + ); + +-- RL -> RLB converter (DO handling) ------------- + CD2B : cdata2byte -- 9bit comma,data -> byte stream + generic map ( + CPREF => CPREF, + NCOMM => c_rlink_ncomm) + port map ( + CLK => CLK, + RESET => RESET, + DI => RL_DO, + ENA => RL_VAL, + BUSY => RL_HOLD, + DO => RLB_DO, + VAL => RLB_VAL, + HOLD => RLB_HOLD + ); + +-- synthesis translate_off + + RLMON: if ENAPIN_RLMON >= 0 generate + MON : rlink_mon_sb + generic map ( + DWIDTH => RL_DI'length, + ENAPIN => ENAPIN_RLMON) + port map ( + CLK => CLK, + RL_DI => RL_DI, + RL_ENA => RL_ENA, + RL_BUSY => RL_BUSY, + RL_DO => RL_DO, + RL_VAL => RL_VAL, + RL_HOLD => RL_HOLD + ); + end generate RLMON; + + RBMON: if ENAPIN_RBMON >= 0 generate + MON : rb_mon_sb + generic map ( + DBASE => 8, + ENAPIN => ENAPIN_RBMON) + port map ( + CLK => CLK, + RB_MREQ => RB_MREQ_L, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT + ); + end generate RBMON; + +-- synthesis translate_on + +end syn; Index: rtl/vlib/rlink/rlink_core8.vbom =================================================================== --- rtl/vlib/rlink/rlink_core8.vbom (nonexistent) +++ rtl/vlib/rlink/rlink_core8.vbom (revision 16) @@ -0,0 +1,13 @@ +# libs +../slvtypes.vhd +../comlib/comlib.vhd +../rbus/rblib.vhd +rlinklib.vbom +# components +rlink_core.vbom +../comlib/byte2cdata.vbom +../comlib/cdata2byte.vbom +[ghdl,isim]rlink_mon_sb.vbom +[ghdl,isim]../rbus/rb_mon_sb.vbom +# design +rlink_core8.vhd Index: rtl/vlib/rlink/rlink_sp1c.vhd =================================================================== --- rtl/vlib/rlink/rlink_sp1c.vhd (nonexistent) +++ rtl/vlib/rlink/rlink_sp1c.vhd (revision 16) @@ -0,0 +1,137 @@ +-- $Id: rlink_sp1c.vhd 437 2011-12-09 19:38:07Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rlink_sp1c - syn +-- Description: rlink_core8 + serport_1clock combo +-- +-- Dependencies: rlink_core8 +-- serport/serport_1clock +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa +-- 2011-12-09 437 13.1 O40d xc3s1000-4 337 733 64 469 s 9.8 - - +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-09 437 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.rblib.all; +use work.rlinklib.all; +use work.serport.all; + +entity rlink_sp1c is -- rlink_core8+serport_1clock combo + generic ( + ATOWIDTH : positive := 5; -- access timeout counter width + ITOWIDTH : positive := 6; -- idle timeout counter width + CPREF : slv4 := c_rlink_cpref; -- comma prefix + IFAWIDTH : natural := 5; -- input fifo address width (0=none) + OFAWIDTH : natural := 5; -- output fifo address width (0=none) + ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none) + ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none) + CDWIDTH : positive := 13; -- clk divider width + CDINIT : natural := 15); -- clk divider initial/reset setting + port ( + CLK : in slbit; -- clock + CE_USEC : in slbit; -- 1 usec clock enable + CE_MSEC : in slbit; -- 1 msec clock enable + CE_INT : in slbit := '0'; -- rri ito time unit clock enable + RESET : in slbit; -- reset + ENAXON : in slbit; -- enable xon/xoff handling + ENAESC : in slbit; -- enable xon/xoff escaping + RXSD : in slbit; -- receive serial data (board view) + TXSD : out slbit; -- transmit serial data (board view) + CTS_N : in slbit := '0'; -- clear to send (act.low, board view) + RTS_N : out slbit; -- request to send (act.low, board view) + RB_MREQ : out rb_mreq_type; -- rbus: request + RB_SRES : in rb_sres_type; -- rbus: response + RB_LAM : in slv16; -- rbus: look at me + RB_STAT : in slv3; -- rbus: status flags + RL_MONI : out rl_moni_type; -- rlink_core: monitor port + SER_MONI : out serport_moni_type -- serport: monitor port + ); +end entity rlink_sp1c; + + +architecture syn of rlink_sp1c is + + signal RLB_DI : slv8 := (others=>'0'); + signal RLB_ENA : slbit := '0'; + signal RLB_BUSY : slbit := '0'; + signal RLB_DO : slv8 := (others=>'0'); + signal RLB_VAL : slbit := '0'; + signal RLB_HOLD : slbit := '0'; + +begin + + CORE : rlink_core8 + generic map ( + ATOWIDTH => ATOWIDTH, + ITOWIDTH => ITOWIDTH, + CPREF => CPREF, + ENAPIN_RLMON => ENAPIN_RLMON, + ENAPIN_RBMON => ENAPIN_RBMON) + port map ( + CLK => CLK, + CE_INT => CE_INT, + RESET => RESET, + RLB_DI => RLB_DI, + RLB_ENA => RLB_ENA, + RLB_BUSY => RLB_BUSY, + RLB_DO => RLB_DO, + RLB_VAL => RLB_VAL, + RLB_HOLD => RLB_HOLD, + RL_MONI => RL_MONI, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT + ); + + SERPORT : serport_1clock + generic map ( + CDWIDTH => CDWIDTH, + CDINIT => CDINIT, + RXFAWIDTH => IFAWIDTH, + TXFAWIDTH => OFAWIDTH) + port map ( + CLK => CLK, + CE_MSEC => CE_MSEC, + RESET => RESET, + ENAXON => ENAXON, + ENAESC => ENAESC, + RXDATA => RLB_DI, + RXVAL => RLB_ENA, + RXHOLD => RLB_BUSY, + TXDATA => RLB_DO, + TXENA => RLB_VAL, + TXBUSY => RLB_HOLD, + MONI => SER_MONI, + RXSD => RXSD, + TXSD => TXSD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N + ); + +end syn; Index: rtl/vlib/rlink/tb/tb_rlink_serport.vhd =================================================================== --- rtl/vlib/rlink/tb/tb_rlink_serport.vhd (revision 15) +++ rtl/vlib/rlink/tb/tb_rlink_serport.vhd (nonexistent) @@ -1,45 +0,0 @@ --- $Id: tb_rlink_serport.vhd 343 2010-12-05 21:24:38Z mueller $ --- --- Copyright 2007-2010 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: tb_rlink_serport --- Description: Configuration for tb_rlink_serport for tb_rlink. --- --- Dependencies: tbd_rlink_gen --- --- To test: rlink_serport --- rlink_core --- --- Target Devices: generic --- --- Verified (with tb_rlink_stim.dat): --- Date Rev Code ghdl ise Target Comment --- 2007-10-12 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (Test 15 fails) --- 2007-10-12 88 - 0.26 - - c:ok (Test 15 fails) --- --- Revision History: --- Date Rev Version Comment --- 2010-12-05 343 3.0 rri->rlink renames --- 2007-11-25 98 1.0.1 use entity rather arch name to switch core/serport --- 2007-07-08 65 1.0 Initial version ------------------------------------------------------------------------------- - -configuration tb_rlink_serport of tb_rlink is - - for sim - for all : tbd_rlink_gen - use entity work.tbd_rlink_serport; - end for; - end for; - -end tb_rlink_serport; Index: rtl/vlib/rlink/tb/tbd_rlink_serport.vbom =================================================================== --- rtl/vlib/rlink/tb/tbd_rlink_serport.vbom (revision 15) +++ rtl/vlib/rlink/tb/tbd_rlink_serport.vbom (nonexistent) @@ -1,16 +0,0 @@ -# libs -../../slvtypes.vhd -../../comlib/comlib.vhd -../../serport/serport.vhd -../../rbus/rblib.vhd -../rlinklib.vbom -../../simlib/simlib.vhd -../../simlib/simbus.vhd -# components -tbu_rlink_serport : tbu_rlink_serport.vbom -../../serport/serport_uart_tx.vbom -../../serport/serport_uart_rx.vbom -../../comlib/byte2cdata.vbom -../../comlib/cdata2byte.vbom -# design -tbd_rlink_serport.vhd Index: rtl/vlib/rlink/tb/tb_rlink_serport_stim.dat =================================================================== --- rtl/vlib/rlink/tb/tb_rlink_serport_stim.dat (revision 15) +++ rtl/vlib/rlink/tb/tb_rlink_serport_stim.dat (nonexistent) @@ -1,312 +0,0 @@ -# $Id: tb_rlink_serport_stim.dat 351 2010-12-30 21:50:54Z mueller $ -# -# Revision History: -# Date Rev Version Comment -# 2010-12-29 351 1.0.1 use new rbd_tester addr 111100xx (from 111101xx) -# 2010-12-26 348 1.0 Initial version (Test 3 from tb_rlink_stim.dat) -# -#--------------------------------------- -# rbus address mapping -# 11110000 rbd_tester cntl -# 11110001 rbd_tester data -# 11110010 rbd_tester fifo -# 11110011 rbd_tester attn -# -.rlmon 0 -.rbmon 1 -# -C ----------------------------------------------------------------------------- -C Test 1: wreg(data) -C data := 0011001111001100 -C ==> shows that rlink can write a register -C -C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop -C rx: sop - cmd(010) stat crc - eop -# -rxsop -rxcs 00001010 00000000 -rxeop -# -txsop -txcad 00001010 11110001 0011001111001100 -txeop -# -.iowt 10 -# -C ----------------------------------------------------------------------------- -C Test 2: rreg(data) -C data -> 0011001111001100 -C ==> shows that rlink can read back a register -C -C rreg: tx: sop - cmd(00001,000) addr(0001) ccrc - eop -C rx: sop - cmd(000) dl dh stat crc - eop -# -rxsop -rxcds 00001000 0011001111001100 00000000 -rxeop -# -txsop -txca 00001000 11110001 -txeop -# -.iowt 10 -# -C ----------------------------------------------------------------------------- -C Test 3: Test comma escapes -C Assumes CPREF=1000, covers 11111111:10000111 and 10001101:10010000 -C -C data := 1000000011111111 ,... -C data -> 1000000011111111 -C data := 1000001010000001 , -C data -> 1000001010000001 -C data := 1000010010000011 , -C data -> 1000010010000011 -C data := 1000011010000101 6,5 -C data -> 1000011010000101 -C data := 1000100010000111 8,7 -C data -> 1000100010000111 -C data := 1000111010001101 14,13 -C data -> 1000111010001101 -C data := 1001000010001111 .., -C data -> 1001000010001111 -C -C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc -C rreg: tx: - cmd(00010,000) addr(0001) ccrc -C wreg: tx: - cmd(00011,010) addr(0001) dl dh ccrc -C rreg: tx: - cmd(00100,000) addr(0001) ccrc -C wreg: tx: - cmd(00101,010) addr(0001) dl dh ccrc -C rreg: tx: - cmd(00110,000) addr(0001) ccrc -C wreg: tx: - cmd(00111,010) addr(0001) dl dh ccrc -C rreg: tx: - cmd(01000,000) addr(0001) ccrc -C wreg: tx: - cmd(01001,010) addr(0001) dl dh ccrc -C rreg: tx: - cmd(01010,000) addr(0001) ccrc -C wreg: tx: - cmd(01011,010) addr(0001) dl dh ccrc -C rreg: tx: - cmd(01100,000) addr(0001) ccrc -C wreg: tx: - cmd(01101,010) addr(0001) dl dh ccrc -C rreg: tx: - cmd(01110,000) addr(0001) ccrc -C tx: - eop -C rx: sop - cmd(010) stat crc -C rx: - cmd(000) dl dh stat crc -C rx: - cmd(010) stat crc -C rx: - cmd(000) dl dh stat crc -C rx: - cmd(010) stat crc -C rx: - cmd(000) dl dh stat crc -C rx: - cmd(010) stat crc -C rx: - cmd(000) dl dh stat crc -C rx: - cmd(010) stat crc -C rx: - cmd(000) dl dh stat crc -C rx: - cmd(010) stat crc -C rx: - cmd(000) dl dh stat crc -C rx: - cmd(010) stat crc -C rx: - cmd(000) dl dh stat crc -C rx: - eop -# -rxsop -rxcs 00001010 00000000 -rxcds 00010000 1000000011111111 00000000 -rxcs 00011010 00000000 -rxcds 00100000 1000001010000001 00000000 -rxcs 00101010 00000000 -rxcds 00110000 1000010010000011 00000000 -rxcs 00111010 00000000 -rxcds 01000000 1000011010000101 00000000 -rxcs 01001010 00000000 -rxcds 01010000 1000100010000111 00000000 -rxcs 01011010 00000000 -rxcds 01100000 1000111010001101 00000000 -rxcs 01101010 00000000 -rxcds 01110000 1001000010001111 00000000 -rxeop -# -txsop -txcad 00001010 11110001 1000000011111111 -txca 00010000 11110001 -txcad 00011010 11110001 1000001010000001 -txca 00100000 11110001 -txcad 00101010 11110001 1000010010000011 -txca 00110000 11110001 -txcad 00111010 11110001 1000011010000101 -txca 01000000 11110001 -txcad 01001010 11110001 1000100010000111 -txca 01010000 11110001 -txcad 01011010 11110001 1000111010001101 -txca 01100000 11110001 -txcad 01101010 11110001 1001000010001111 -txca 01110000 11110001 -txeop -# -.iowt 10 -# -C ----------------------------------------------------------------------------- -C Test 4: Test RTS throttling via wreg/rreg -C Note: RTS_N response is *not* selfchecking, look into log and check -C for 'RTS_N' lines. -C -C init (11111110:0000000000001000) fena(0),fwth(0),fdly(0),rtsoff(1),rtson(0) -C fifo := 1000000010000000 -C fifo := 1000000010000001 -C fifo := 1000000010000010 -C fifo := 1000000010000011 -C fifo := 1000000110000000 -C fifo := 1000000110000001 -C fifo := 1000000110000010 -C fifo := 1000000110000011 -C fifo -> 8 read (will produce escapes for dl and dh, thus slow down a bit) -C -C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc -C wreg: tx: - cmd(00001,010) addr(0010) dl dh ccrc -C wreg: .... -C wreg: tx: - cmd(01000,010) addr(0010) dl dh ccrc -C rreg: tx: - cmd(10001,000) addr(0010) ccrc -C .... -C rreg: tx: - cmd(11000,000) addr(0010) ccrc -C tx: - eop -C rx: sop - cmd(110) stat crc -C rx: - cmd(010) stat crc -C ... -C rx: - cmd(010) stat crc -C rx: - cmd(000) dl dh stat crc -C ... -C rx: - cmd(000) dl dh stat crc -C rx: - eop -C -# -rxsop -rxcs 11110110 00000000 -rxcs 00001010 00000000 -rxcs 00010010 00000000 -rxcs 00011010 00000000 -rxcs 00100010 00000000 -rxcs 00101010 00000000 -rxcs 00110010 00000000 -rxcs 00111010 00000000 -rxcs 01000010 00000000 -rxcds 10001000 1000000010000000 00000000 -rxcds 10010000 1000000010000001 00000000 -rxcds 10011000 1000000010000010 00000000 -rxcds 10100000 1000000010000011 00000000 -rxcds 10101000 1000000110000000 00000000 -rxcds 10110000 1000000110000001 00000000 -rxcds 10111000 1000000110000010 00000000 -rxcds 11000000 1000000110000011 00000000 -rxeop -# -txsop -txcad 11110110 11111110 0000000000001000 -txcad 00001010 11110010 1000000010000000 -txcad 00010010 11110010 1000000010000001 -txcad 00011010 11110010 1000000010000010 -txcad 00100010 11110010 1000000010000011 -txcad 00101010 11110010 1000000110000000 -txcad 00110010 11110010 1000000110000001 -txcad 00111010 11110010 1000000110000010 -txcad 01000010 11110010 1000000110000011 -txca 10001000 11110010 -txca 10010000 11110010 -txca 10011000 11110010 -txca 10100000 11110010 -txca 10101000 11110010 -txca 10110000 11110010 -txca 10111000 11110010 -txca 11000000 11110010 -txeop -# -.iowt 10 -# -C ----------------------------------------------------------------------------- -C Test 5: Test RTS flush pulse -C Note: RTS_N response is *not* selfchecking, look into log and check -C for 'RTS_N' lines. -C -C 1a. setup width=1, delay=1 -C -C init (11111110:0001001001111110) fena(1),fwth(1),fdly(1),rtsoff(7),rtson(6) -C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc - eop -# -rxsop -rxcs 11110110 00000000 -rxeop -txsop -txcad 11110110 11111110 0001001001111110 -txeop -.iowt 10 -.wait 50 -C -C 1b. test with wreg sequence -C data := 0000000000000001 -C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop -C rx: sop - cmd(010) stat crc - eop -C -# -rxsop -rxcs 00001010 00000000 -rxeop -txsop -txcad 00001010 11110001 0000000000000001 -txeop -.iowt 10 -.wait 50 -C -C 2a. setup width=3, delay=1 -C -C init (11111110:0001011001111110) fena(1),fwth(3),fdly(1),rtsoff(7),rtson(6) -C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc - eop -# -rxsop -rxcs 11110110 00000000 -rxeop -txsop -txcad 11110110 11111110 0001011001111110 -txeop -.iowt 10 -.wait 50 -C -C 2b. test with wreg sequence -C data := 0000000000000001 -C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop -C rx: sop - cmd(010) stat crc - eop -# -rxsop -rxcs 00001010 00000000 -rxeop -txsop -txcad 00001010 11110001 0000000000000001 -txeop -.iowt 10 -.wait 50 -# -C -C 3a. setup width=7, delay=7 -C -C init (11111110:0001111111111110) fena(1),fwth(7),fdly(7),rtsoff(7),rtson(6) -C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc - eop -# -rxsop -rxcs 11110110 00000000 -rxeop -txsop -txcad 11110110 11111110 0001111111111110 -txeop -.iowt 10 -.wait 50 -C -C 3b. test with wreg sequence -C data := 0000000000000001 -C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop -C rx: sop - cmd(010) stat crc - eop -# -rxsop -rxcs 00001010 00000000 -rxeop -txsop -txcad 00001010 11110001 0000000000000001 -txeop -.iowt 10 -.wait 50 -# -#============================================================================== -# -C ----------------------------------------------------------------------------- -C Run down and Finish -.iowt 10 -.wait 100 Index: rtl/vlib/rlink/tb/tb_rlink_serport.vbom =================================================================== --- rtl/vlib/rlink/tb/tb_rlink_serport.vbom (revision 15) +++ rtl/vlib/rlink/tb/tb_rlink_serport.vbom (nonexistent) @@ -1,6 +0,0 @@ -# configure tb_rlink with tbd_rlink_serport wrapper; -# use vhdl configure file (tb_rlink_serport.vhd) to allow -# that all configurations will co-exist in work library -tbd_rlink_gen = tbd_rlink_serport.vbom -tb_rlink.vbom -tb_rlink_serport.vhd Index: rtl/vlib/rlink/tb/tbd_rlink_serport.vhd =================================================================== --- rtl/vlib/rlink/tb/tbd_rlink_serport.vhd (revision 15) +++ rtl/vlib/rlink/tb/tbd_rlink_serport.vhd (nonexistent) @@ -1,249 +0,0 @@ --- $Id: tbd_rlink_serport.vhd 427 2011-11-19 21:04:11Z mueller $ --- --- Copyright 2007-2011 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: tbd_rlink_serport - syn --- Description: Wrapper for rlink_core plus rlink_serport with an interface --- compatible to the rlink_core only module. --- NOTE: this implementation is a hack, should be redone --- using configurations. --- --- Dependencies: tbu_rlink_serport [UUT] --- serport_uart_tx --- serport_uart_rx --- byte2cdata --- cdata2byte --- --- To test: rlink_serport --- --- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 --- --- Revision History: --- Date Rev Version Comment --- 2011-11-19 427 3.0.5 now numeric_std clean --- 2010-12-28 350 3.0.4 use CLKDIV/CDINIT=0; --- 2010-12-26 348 3.0.3 add RTS/CTS ports for tbu_; --- 2010-12-24 347 3.0.2 rename: CP_*->RL->* --- 2010-12-22 346 3.0.1 removed proc_moni, use .rlmon cmd in test bench --- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol; --- 2010-06-06 301 2.3 use NCOMM=4 (new eop,nak commas) --- 2010-05-02 287 2.2.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM --- drop RP_IINT signal from interfaces --- 2010-04-24 281 2.2.1 use serport_uart_[tr]x directly again --- 2010-04-03 274 2.2 add CE_USEC --- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage --- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface --- 2007-11-25 98 1.1 added RP_IINT support; use entity rather arch --- name to switch core/serport; --- use serport_uart_[tr]x_tb to allow that UUT is a --- [sft]sim model compiled with keep hierarchy --- 2007-07-02 63 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use ieee.std_logic_textio.all; -use std.textio.all; - -use work.slvtypes.all; -use work.rlinklib.all; -use work.comlib.all; -use work.serport.all; -use work.simlib.all; -use work.simbus.all; - -entity tbd_rlink_serport is -- rlink_core+rlink_serport tb design - -- implements tbd_rlink_gen - port ( - CLK : in slbit; -- clock - CE_INT : in slbit; -- rlink ito time unit clock enable - CE_USEC : in slbit; -- 1 usec clock enable - RESET : in slbit; -- reset - RL_DI : in slv9; -- rlink: data in - RL_ENA : in slbit; -- rlink: data enable - RL_BUSY : out slbit; -- rlink: data busy - RL_DO : out slv9; -- rlink: data out - RL_VAL : out slbit; -- rlink: data valid - RL_HOLD : in slbit; -- rlink: data hold - RB_MREQ_aval : out slbit; -- rbus: request - aval - RB_MREQ_re : out slbit; -- rbus: request - re - RB_MREQ_we : out slbit; -- rbus: request - we - RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll - RB_MREQ_addr : out slv8; -- rbus: request - addr - RB_MREQ_din : out slv16; -- rbus: request - din - RB_SRES_ack : in slbit; -- rbus: response - ack - RB_SRES_busy : in slbit; -- rbus: response - busy - RB_SRES_err : in slbit; -- rbus: response - err - RB_SRES_dout : in slv16; -- rbus: response - dout - RB_LAM : in slv16; -- rbus: look at me - RB_STAT : in slv3; -- rbus: status flags - TXRXACT : out slbit -- txrx active flag - ); -end entity tbd_rlink_serport; - - -architecture syn of tbd_rlink_serport is - - constant CDWIDTH : positive := 13; - constant c_cdinit : natural := 0; -- NOTE: change in tbu_rlink_serport !! - - signal RRI_RXSD : slbit := '0'; - signal RRI_TXSD : slbit := '0'; - signal RTS_N : slbit := '0'; - signal RXDATA : slv8 := (others=>'0'); - signal RXVAL : slbit := '0'; - signal RXACT : slbit := '0'; - signal TXDATA : slv8 := (others=>'0'); - signal TXENA : slbit := '0'; - signal TXBUSY : slbit := '0'; - signal CLKDIV : slv13 := slv(to_unsigned(c_cdinit,CDWIDTH)); - -component tbu_rlink_serport is -- rlink core+serport combo - port ( - CLK : in slbit; -- clock - CE_INT : in slbit; -- rlink ito time unit clock enable - CE_USEC : in slbit; -- 1 usec clock enable - CE_MSEC : in slbit; -- 1 msec clock enable - RESET : in slbit; -- reset - RXSD : in slbit; -- receive serial data (board view) - TXSD : out slbit; -- transmit serial data (board view) - CTS_N : in slbit; -- clear to send (act.low, board view) - RTS_N : out slbit; -- request to send (act.low, board view) - RB_MREQ_aval : out slbit; -- rbus: request - aval - RB_MREQ_re : out slbit; -- rbus: request - re - RB_MREQ_we : out slbit; -- rbus: request - we - RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll - RB_MREQ_addr : out slv8; -- rbus: request - addr - RB_MREQ_din : out slv16; -- rbus: request - din - RB_SRES_ack : in slbit; -- rbus: response - ack - RB_SRES_busy : in slbit; -- rbus: response - busy - RB_SRES_err : in slbit; -- rbus: response - err - RB_SRES_dout : in slv16; -- rbus: response - dout - RB_LAM : in slv16; -- rbus: look at me - RB_STAT : in slv3 -- rbus: status flags - ); -end component; - -begin - - UUT : tbu_rlink_serport - port map ( - CLK => CLK, - CE_INT => CE_INT, - CE_USEC => CE_USEC, - CE_MSEC => '1', - RESET => RESET, - RXSD => RRI_RXSD, - TXSD => RRI_TXSD, - CTS_N => '0', - RTS_N => RTS_N, - RB_MREQ_aval => RB_MREQ_aval, - RB_MREQ_re => RB_MREQ_re, - RB_MREQ_we => RB_MREQ_we, - RB_MREQ_initt=> RB_MREQ_initt, - RB_MREQ_addr => RB_MREQ_addr, - RB_MREQ_din => RB_MREQ_din, - RB_SRES_ack => RB_SRES_ack, - RB_SRES_busy => RB_SRES_busy, - RB_SRES_err => RB_SRES_err, - RB_SRES_dout => RB_SRES_dout, - RB_LAM => RB_LAM, - RB_STAT => RB_STAT - ); - - UARTRX : serport_uart_rx - generic map ( - CDWIDTH => CDWIDTH) - port map ( - CLK => CLK, - RESET => RESET, - CLKDIV => CLKDIV, - RXSD => RRI_TXSD, - RXDATA => RXDATA, - RXVAL => RXVAL, - RXERR => open, - RXACT => RXACT - ); - - UARTTX : serport_uart_tx - generic map ( - CDWIDTH => CDWIDTH) - port map ( - CLK => CLK, - RESET => RESET, - CLKDIV => CLKDIV, - TXSD => RRI_RXSD, - TXDATA => TXDATA, - TXENA => TXENA, - TXBUSY => TXBUSY - ); - - TXRXACT <= RXACT or TXBUSY; - - B2CD : byte2cdata -- byte stream -> 9bit comma,data - generic map ( - CPREF => c_rlink_cpref, - NCOMM => c_rlink_ncomm) - port map ( - CLK => CLK, - RESET => RESET, - DI => RXDATA, - ENA => RXVAL, - BUSY => open, - DO => RL_DO, - VAL => RL_VAL, - HOLD => RL_HOLD - ); - - CD2B : cdata2byte -- 9bit comma,data -> byte stream - generic map ( - CPREF => c_rlink_cpref, - NCOMM => c_rlink_ncomm) - port map ( - CLK => CLK, - RESET => RESET, - DI => RL_DI, - ENA => RL_ENA, - BUSY => RL_BUSY, - DO => TXDATA, - VAL => TXENA, - HOLD => TXBUSY - ); - - proc_moni: process - variable oline : line; - variable rts_last : slbit := '0'; - variable ncycle : integer := 0; - begin - loop - wait until rising_edge(CLK); -- check at end of clock cycle - if RTS_N /= rts_last then - writetimestamp(oline, SB_CLKCYCLE, ": rts "); - write(oline, string'(" RTS_N ")); - write(oline, rts_last, right, 1); - write(oline, string'(" -> ")); - write(oline, RTS_N, right, 1); - write(oline, string'(" after ")); - write(oline, ncycle, right, 5); - write(oline, string'(" cycles")); - writeline(output, oline); - rts_last := RTS_N; - ncycle := 0; - end if; - ncycle := ncycle + 1; - end loop; - end process proc_moni; - -end syn; Index: rtl/vlib/rlink/tb/tbu_rlink_serport.vbom =================================================================== --- rtl/vlib/rlink/tb/tbu_rlink_serport.vbom (revision 15) +++ rtl/vlib/rlink/tb/tbu_rlink_serport.vbom (nonexistent) @@ -1,9 +0,0 @@ -# libs -../../slvtypes.vhd -../../rbus/rblib.vhd -../rlinklib.vbom -# components -../rlink_base.vbom -../rlink_serport.vbom -# design -tbu_rlink_serport.vhd Index: rtl/vlib/rlink/tb/tbu_rlink_serport.vhd =================================================================== --- rtl/vlib/rlink/tb/tbu_rlink_serport.vhd (revision 15) +++ rtl/vlib/rlink/tb/tbu_rlink_serport.vhd (nonexistent) @@ -1,175 +0,0 @@ --- $Id: tbu_rlink_serport.vhd 427 2011-11-19 21:04:11Z mueller $ --- --- Copyright 2007-2011 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: tbu_rlink_serport - syn --- Description: Wrapper for rlink_base plus rlink_serport to avoid records. --- It has a port interface which will not be modified by xst --- synthesis (no records, no generic port). --- --- Dependencies: rlink_base --- rlink_serport --- --- To test: rlink_serport --- --- Target Devices: generic --- --- Synthesized (xst): --- Date Rev ise Target flop lutl lutm slic t peri --- 2010-04-03 274 11.4 L68 xc3s1000-4 278 588 18 366 s 9.83 --- 2007-10-27 92 9.2.02 J39 xc3s1000-4 273 547 18 - t 9.65 --- 2007-10-27 92 9.1 J30 xc3s1000-4 273 545 18 - t 9.65 --- 2007-10-27 92 8.2.03 I34 xc3s1000-4 283 594 18 323 s 10.3 --- 2007-10-27 92 8.1.03 I27 xc3s1000-4 285 596 18 - s 9.32 --- --- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29 --- --- Revision History: --- Date Rev Version Comment --- 2011-11-19 427 3.1.2 now numeric_std clean --- 2010-12-28 350 3.1.1 use CLKDIV/CDINIT=0; --- 2010-12-26 348 3.1 use rlink_base now; add RTS/CTS ports --- 2010-12-24 347 3.0.1 rename: CP_*->RL->* --- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol; --- 2010-06-03 300 2.2.3 use default FAWIDTH for rri_core_serport --- 2010-05-02 287 2.2.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM --- drop RP_IINT from interfaces; drop RTSFLUSH generic --- 2010-04-18 279 2.2.1 drop RTSFBUF generic for rri_serport --- 2010-04-03 274 2.2 add CP_FLUSH, add rri_serport handshake logic --- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage --- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface --- 2007-11-24 98 1.1 added RP_IINT support --- 2007-07-02 63 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; -use work.rblib.all; -use work.rlinklib.all; - -entity tbu_rlink_serport is -- rlink core+serport combo - port ( - CLK : in slbit; -- clock - CE_INT : in slbit; -- rlink ito time unit clock enable - CE_USEC : in slbit; -- 1 usec clock enable - CE_MSEC : in slbit; -- 1 msec clock enable - RESET : in slbit; -- reset - RXSD : in slbit; -- receive serial data (board view) - TXSD : out slbit; -- transmit serial data (board view) - CTS_N : in slbit; -- clear to send (act.low, board view) - RTS_N : out slbit; -- request to send (act.low, board view) - RB_MREQ_aval : out slbit; -- rbus: request - aval - RB_MREQ_re : out slbit; -- rbus: request - re - RB_MREQ_we : out slbit; -- rbus: request - we - RB_MREQ_initt: out slbit; -- rbus: request - init; avoid name coll - RB_MREQ_addr : out slv8; -- rbus: request - addr - RB_MREQ_din : out slv16; -- rbus: request - din - RB_SRES_ack : in slbit; -- rbus: response - ack - RB_SRES_busy : in slbit; -- rbus: response - busy - RB_SRES_err : in slbit; -- rbus: response - err - RB_SRES_dout : in slv16; -- rbus: response - dout - RB_LAM : in slv16; -- rbus: look at me - RB_STAT : in slv3 -- rbus: status flags - ); -end entity tbu_rlink_serport; - - -architecture syn of tbu_rlink_serport is - - constant CDWIDTH : positive := 13; - constant c_cdinit : natural := 0; -- NOTE: change in tbd_rlink_serport !! - - signal RB_MREQ : rb_mreq_type := rb_mreq_init; - signal RB_SRES : rb_sres_type := rb_sres_init; - - signal RLB_DI : slv8 := (others=>'0'); - signal RLB_ENA : slbit := '0'; - signal RLB_BUSY : slbit := '0'; - signal RLB_DO : slv8 := (others=>'0'); - signal RLB_VAL : slbit := '0'; - signal RLB_HOLD : slbit := '0'; - signal IFIFO_SIZE : slv4 := (others=>'0'); - signal RL_MONI : rl_moni_type := rl_moni_init; - -begin - - RB_MREQ_aval <= RB_MREQ.aval; - RB_MREQ_re <= RB_MREQ.re; - RB_MREQ_we <= RB_MREQ.we; - RB_MREQ_initt<= RB_MREQ.init; - RB_MREQ_addr <= RB_MREQ.addr; - RB_MREQ_din <= RB_MREQ.din; - - RB_SRES.ack <= RB_SRES_ack; - RB_SRES.busy <= RB_SRES_busy; - RB_SRES.err <= RB_SRES_err; - RB_SRES.dout <= RB_SRES_dout; - - BASE : rlink_base - generic map ( - ATOWIDTH => 5, - ITOWIDTH => 6, - CPREF => c_rlink_cpref, - IFAWIDTH => 5, - OFAWIDTH => 0, -- no output fifo - ENAPIN_RLMON => -1, -- no monitors (both are instantiated in - ENAPIN_RBMON => -1) -- tbd_rlink_serport for ssim avail.) - port map ( - CLK => CLK, - CE_INT => CE_INT, - RESET => RESET, - RLB_DI => RLB_DI, - RLB_ENA => RLB_ENA, - RLB_BUSY => RLB_BUSY, - RLB_DO => RLB_DO, - RLB_VAL => RLB_VAL, - RLB_HOLD => RLB_HOLD, - IFIFO_SIZE => IFIFO_SIZE, - OFIFO_SIZE => open, - RL_MONI => RL_MONI, - RB_MREQ => RB_MREQ, - RB_SRES => RB_SRES, - RB_LAM => RB_LAM, - RB_STAT => RB_STAT - ); - - SERPORT : rlink_serport - generic map ( - RB_ADDR => slv(to_unsigned(2#11111110#,8)), - CDWIDTH => CDWIDTH, - CDINIT => c_cdinit) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC, - RESET => RESET, - RXSD => RXSD, - TXSD => TXSD, - CTS_N => CTS_N, - RTS_N => RTS_N, - RLB_DI => RLB_DI, - RLB_ENA => RLB_ENA, - RLB_BUSY => RLB_BUSY, - RLB_DO => RLB_DO, - RLB_VAL => RLB_VAL, - RLB_HOLD => RLB_HOLD, - RB_MREQ => RB_MREQ, - IFIFO_SIZE => IFIFO_SIZE, - RL_MONI => RL_MONI, - RL_SER_MONI=> open - ); - -end syn; Index: rtl/vlib/rlink/tb/tb_rlink_serport_ssim.vbom =================================================================== --- rtl/vlib/rlink/tb/tb_rlink_serport_ssim.vbom (revision 15) +++ rtl/vlib/rlink/tb/tb_rlink_serport_ssim.vbom (nonexistent) @@ -1,5 +0,0 @@ -# configure tb_rlink with tbd_rlink_serport wrapper; _*sim case -tbd_rlink_gen = tbd_rlink_serport.vbom -tbu_rlink_serport = tbu_rlink_serport_ssim.vhd -tb_rlink_serport.vbom -@top:tb_rlink_serport Index: rtl/vlib/rlink/tb/tbu_rlink_sp1c.vbom =================================================================== --- rtl/vlib/rlink/tb/tbu_rlink_sp1c.vbom (nonexistent) +++ rtl/vlib/rlink/tb/tbu_rlink_sp1c.vbom (revision 16) @@ -0,0 +1,8 @@ +# libs +../../slvtypes.vhd +../../rbus/rblib.vhd +../rlinklib.vbom +# components +../rlink_sp1c.vbom +# design +tbu_rlink_sp1c.vhd Index: rtl/vlib/rlink/tb/tb_rlink_sp1c_ssim.vbom =================================================================== --- rtl/vlib/rlink/tb/tb_rlink_sp1c_ssim.vbom (nonexistent) +++ rtl/vlib/rlink/tb/tb_rlink_sp1c_ssim.vbom (revision 16) @@ -0,0 +1,5 @@ +# configure tb_rlink with tbd_rlink_sp1c wrapper; _*sim case +tbd_rlink_gen = tbd_rlink_sp1c.vbom +tbu_rlink_sp1c = tbu_rlink_sp1c_ssim.vhd +tb_rlink_sp1c.vbom +@top:tb_rlink_sp1c Index: rtl/vlib/rlink/tb/tb_rlink_sp1c.vbom =================================================================== --- rtl/vlib/rlink/tb/tb_rlink_sp1c.vbom (nonexistent) +++ rtl/vlib/rlink/tb/tb_rlink_sp1c.vbom (revision 16) @@ -0,0 +1,6 @@ +# configure tb_rlink with tbd_rlink_sp1c wrapper; +# use vhdl configure file (tb_rlink_sp1c.vhd) to allow +# that all configurations will co-exist in work library +tbd_rlink_gen = tbd_rlink_sp1c.vbom +tb_rlink.vbom +tb_rlink_sp1c.vhd Index: rtl/vlib/rlink/tb/tb_rlink_sp1c_stim.dat =================================================================== --- rtl/vlib/rlink/tb/tb_rlink_sp1c_stim.dat (nonexistent) +++ rtl/vlib/rlink/tb/tb_rlink_sp1c_stim.dat (revision 16) @@ -0,0 +1,146 @@ +# $Id: tb_rlink_sp1c_stim.dat 442 2011-12-23 10:03:28Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-12-22 442 1.1 remove RTS tests (now obsolete) +# 2010-12-29 351 1.0.1 use new rbd_tester addr 111100xx (from 111101xx) +# 2010-12-26 348 1.0 Initial version (Test 3 from tb_rlink_stim.dat) +# +#--------------------------------------- +# rbus address mapping +# 11110000 rbd_tester cntl +# 11110001 rbd_tester data +# 11110010 rbd_tester fifo +# 11110011 rbd_tester attn +# +.rlmon 0 +.rbmon 1 +# +C ----------------------------------------------------------------------------- +C Test 1: wreg(data) +C data := 0011001111001100 +C ==> shows that rlink can write a register +C +C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop +C rx: sop - cmd(010) stat crc - eop +# +rxsop +rxcs 00001010 00000000 +rxeop +# +txsop +txcad 00001010 11110001 0011001111001100 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 2: rreg(data) +C data -> 0011001111001100 +C ==> shows that rlink can read back a register +C +C rreg: tx: sop - cmd(00001,000) addr(0001) ccrc - eop +C rx: sop - cmd(000) dl dh stat crc - eop +# +rxsop +rxcds 00001000 0011001111001100 00000000 +rxeop +# +txsop +txca 00001000 11110001 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 3: Test comma escapes +C Assumes CPREF=1000, covers 11111111:10000111 and 10001101:10010000 +C +C data := 1000000011111111 ,... +C data -> 1000000011111111 +C data := 1000001010000001 , +C data -> 1000001010000001 +C data := 1000010010000011 , +C data -> 1000010010000011 +C data := 1000011010000101 6,5 +C data -> 1000011010000101 +C data := 1000100010000111 8,7 +C data -> 1000100010000111 +C data := 1000111010001101 14,13 +C data -> 1000111010001101 +C data := 1001000010001111 .., +C data -> 1001000010001111 +C +C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(00010,000) addr(0001) ccrc +C wreg: tx: - cmd(00011,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(00100,000) addr(0001) ccrc +C wreg: tx: - cmd(00101,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(00110,000) addr(0001) ccrc +C wreg: tx: - cmd(00111,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(01000,000) addr(0001) ccrc +C wreg: tx: - cmd(01001,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(01010,000) addr(0001) ccrc +C wreg: tx: - cmd(01011,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(01100,000) addr(0001) ccrc +C wreg: tx: - cmd(01101,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(01110,000) addr(0001) ccrc +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - eop +# +rxsop +rxcs 00001010 00000000 +rxcds 00010000 1000000011111111 00000000 +rxcs 00011010 00000000 +rxcds 00100000 1000001010000001 00000000 +rxcs 00101010 00000000 +rxcds 00110000 1000010010000011 00000000 +rxcs 00111010 00000000 +rxcds 01000000 1000011010000101 00000000 +rxcs 01001010 00000000 +rxcds 01010000 1000100010000111 00000000 +rxcs 01011010 00000000 +rxcds 01100000 1000111010001101 00000000 +rxcs 01101010 00000000 +rxcds 01110000 1001000010001111 00000000 +rxeop +# +txsop +txcad 00001010 11110001 1000000011111111 +txca 00010000 11110001 +txcad 00011010 11110001 1000001010000001 +txca 00100000 11110001 +txcad 00101010 11110001 1000010010000011 +txca 00110000 11110001 +txcad 00111010 11110001 1000011010000101 +txca 01000000 11110001 +txcad 01001010 11110001 1000100010000111 +txca 01010000 11110001 +txcad 01011010 11110001 1000111010001101 +txca 01100000 11110001 +txcad 01101010 11110001 1001000010001111 +txca 01110000 11110001 +txeop +# +.iowt 10 +# +#============================================================================== +# +C ----------------------------------------------------------------------------- +C Run down and Finish +.iowt 10 +.wait 100 Index: rtl/vlib/rlink/tb/tbu_rlink_sp1c.vhd =================================================================== --- rtl/vlib/rlink/tb/tbu_rlink_sp1c.vhd (nonexistent) +++ rtl/vlib/rlink/tb/tbu_rlink_sp1c.vhd (revision 16) @@ -0,0 +1,151 @@ +-- $Id: tbu_rlink_sp1c.vhd 442 2011-12-23 10:03:28Z mueller $ +-- +-- Copyright 2007-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tbu_rlink_sp1c - syn +-- Description: Wrapper for rlink_sp1c to avoid records. +-- It has a port interface which will not be modified by xst +-- synthesis (no records, no generic port). +-- +-- Dependencies: rlink_sp1c +-- +-- To test: rlink_sp1c +-- +-- Target Devices: generic +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-12-22 442 13.1 O40d xc3s1000-4 348 704 64 473 s 9.08 +-- 2010-04-03 274 11.4 L68 xc3s1000-4 278 588 18 366 s 9.83 +-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 273 547 18 - t 9.65 +-- 2007-10-27 92 9.1 J30 xc3s1000-4 273 545 18 - t 9.65 +-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 283 594 18 323 s 10.3 +-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 285 596 18 - s 9.32 +-- +-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-22 442 3.2 renamed and retargeted to test rlink_sp1c +-- 2011-11-19 427 3.1.2 now numeric_std clean +-- 2010-12-28 350 3.1.1 use CLKDIV/CDINIT=0; +-- 2010-12-26 348 3.1 use rlink_base now; add RTS/CTS ports +-- 2010-12-24 347 3.0.1 rename: CP_*->RL->* +-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol; +-- 2010-06-03 300 2.2.3 use default FAWIDTH for rri_core_serport +-- 2010-05-02 287 2.2.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM +-- drop RP_IINT from interfaces; drop RTSFLUSH generic +-- 2010-04-18 279 2.2.1 drop RTSFBUF generic for rri_serport +-- 2010-04-03 274 2.2 add CP_FLUSH, add rri_serport handshake logic +-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage +-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface +-- 2007-11-24 98 1.1 added RP_IINT support +-- 2007-07-02 63 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.rblib.all; +use work.rlinklib.all; + +entity tbu_rlink_sp1c is -- rlink core+serport combo + port ( + CLK : in slbit; -- clock + CE_INT : in slbit; -- rlink ito time unit clock enable + CE_USEC : in slbit; -- 1 usec clock enable + CE_MSEC : in slbit; -- 1 msec clock enable + RESET : in slbit; -- reset + RXSD : in slbit; -- receive serial data (board view) + TXSD : out slbit; -- transmit serial data (board view) + CTS_N : in slbit; -- clear to send (act.low, board view) + RTS_N : out slbit; -- request to send (act.low, board view) + RB_MREQ_aval : out slbit; -- rbus: request - aval + RB_MREQ_re : out slbit; -- rbus: request - re + RB_MREQ_we : out slbit; -- rbus: request - we + RB_MREQ_initt: out slbit; -- rbus: request - init; avoid name coll + RB_MREQ_addr : out slv8; -- rbus: request - addr + RB_MREQ_din : out slv16; -- rbus: request - din + RB_SRES_ack : in slbit; -- rbus: response - ack + RB_SRES_busy : in slbit; -- rbus: response - busy + RB_SRES_err : in slbit; -- rbus: response - err + RB_SRES_dout : in slv16; -- rbus: response - dout + RB_LAM : in slv16; -- rbus: look at me + RB_STAT : in slv3 -- rbus: status flags + ); +end entity tbu_rlink_sp1c; + + +architecture syn of tbu_rlink_sp1c is + + constant CDWIDTH : positive := 13; + constant c_cdinit : natural := 0; -- NOTE: change in tbd_rlink_sp1c !! + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + + signal RLB_DI : slv8 := (others=>'0'); + signal RLB_ENA : slbit := '0'; + signal RLB_BUSY : slbit := '0'; + signal RLB_DO : slv8 := (others=>'0'); + signal RLB_VAL : slbit := '0'; + signal RLB_HOLD : slbit := '0'; + +begin + + RB_MREQ_aval <= RB_MREQ.aval; + RB_MREQ_re <= RB_MREQ.re; + RB_MREQ_we <= RB_MREQ.we; + RB_MREQ_initt<= RB_MREQ.init; + RB_MREQ_addr <= RB_MREQ.addr; + RB_MREQ_din <= RB_MREQ.din; + + RB_SRES.ack <= RB_SRES_ack; + RB_SRES.busy <= RB_SRES_busy; + RB_SRES.err <= RB_SRES_err; + RB_SRES.dout <= RB_SRES_dout; + + RLINK : rlink_sp1c + generic map ( + ATOWIDTH => 5, + ITOWIDTH => 6, + CPREF => c_rlink_cpref, + IFAWIDTH => 5, + OFAWIDTH => 5, + ENAPIN_RLMON => -1, -- no monitors (both are instantiated in + ENAPIN_RBMON => -1, -- tbd_rlink_sp1c for ssim avail.) + CDWIDTH => 15, + CDINIT => c_cdinit) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_INT, + RESET => RESET, + ENAXON => '0', + ENAESC => '0', + RXSD => RXSD, + TXSD => TXSD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open + -- SER_MONI => open -- ISE 13.1 err's when a second record is mapped open + ); + +end syn; Index: rtl/vlib/rlink/tb/tbd_rlink_sp1c.vbom =================================================================== --- rtl/vlib/rlink/tb/tbd_rlink_sp1c.vbom (nonexistent) +++ rtl/vlib/rlink/tb/tbd_rlink_sp1c.vbom (revision 16) @@ -0,0 +1,16 @@ +# libs +../../slvtypes.vhd +../../comlib/comlib.vhd +../../serport/serport.vhd +../../rbus/rblib.vhd +../rlinklib.vbom +../../simlib/simlib.vhd +../../simlib/simbus.vhd +# components +tbu_rlink_sp1c : tbu_rlink_sp1c.vbom +../../serport/serport_uart_tx.vbom +../../serport/serport_uart_rx.vbom +../../comlib/byte2cdata.vbom +../../comlib/cdata2byte.vbom +# design +tbd_rlink_sp1c.vhd Index: rtl/vlib/rlink/tb/tbw.dat =================================================================== --- rtl/vlib/rlink/tb/tbw.dat (revision 15) +++ rtl/vlib/rlink/tb/tbw.dat (revision 16) @@ -1,8 +1,8 @@ -# $Id: tbw.dat 349 2010-12-28 14:02:13Z mueller $ +# $Id: tbw.dat 442 2011-12-23 10:03:28Z mueller $ # [tb_rlink_direct] tb_rlink_stim = tb_rlink_stim.dat -[tb_rlink_serport] +[tb_rlink_sp1c] tb_rlink_stim = tb_rlink_stim.dat [tb_rlink_tba_ttcombo] tb_rlink_tba_stim = tb_rlink_tba_ttcombo_stim.dat Index: rtl/vlib/rlink/tb/tb_rlink_stim.dat =================================================================== --- rtl/vlib/rlink/tb/tb_rlink_stim.dat (revision 15) +++ rtl/vlib/rlink/tb/tb_rlink_stim.dat (revision 16) @@ -1,7 +1,8 @@ -# $Id: tb_rlink_stim.dat 351 2010-12-30 21:50:54Z mueller $ +# $Id: tb_rlink_stim.dat 442 2011-12-23 10:03:28Z mueller $ # # Revision History: # Date Rev Version Comment +# 2011-12-22 442 3.0.7 adapt for rlink_sp1c (some .iowt 10->20) # 2010-12-29 351 3.0.6 use new rbd_tester addr 111100xx (from 111101xx) # 2010-12-28 350 3.3.2 adapt for cdinit=0 in tbd/tbu(some .iowt 10->20) # 2010-12-25 348 3.3.1 Test 3b moved to tb_rlink_serport_stim.dat @@ -444,7 +445,7 @@ txcad 00011010 11110001 0011001100110011 txeop # -.iowt 10 +.iowt 20 # C C now check that stat reflects first successfull wreg; re-read cerr=1 sticks ! @@ -512,7 +513,7 @@ txcrc txeop # -.iowt 10 +.iowt 20 # C C rblk: tx: sop - cmd(00010,001) addr(0010) cnt(2->001) *BAD CCRC* - eop @@ -592,7 +593,7 @@ txca 00010000 11110001 txeop # -.iowt 10 +.iowt 20 # C C now check that stat reflects bad dcrc: re-read derr=1 sticks ! @@ -1397,7 +1398,7 @@ txsop txc 00001101 txeop -.iowt 10 +.iowt 10 C C .attn 1000000000000000 C attn: tx: sop - cmd(00010,101) ccrc @@ -1949,7 +1950,7 @@ rxeop txeop # -.iowt 10 +.iowt 20 rxsop rxeop txsop @@ -2014,7 +2015,7 @@ tx8 00000111 txca 00010000 11110001 txeop -.iowt 10 +.iowt 20 # C ----------------------------------------------------------------------------- C Test 21a: eop aborts of wreg @@ -2052,7 +2053,7 @@ txsop tx8 00100010 txeop -.iowt 10 +.iowt 20 C C 1b. check stat C stat: stat(000),attn(0),cerr(1),derr(0),rbnak(0),rberr(0) -> 00001000 @@ -2081,7 +2082,7 @@ tx8 00001010 tx8 11110001 txeop -.iowt 10 +.iowt 20 C C 2b. check stat (stat as for 1a.) C @@ -2108,7 +2109,7 @@ tx8 11110001 tx8 00000011 txeop -.iowt 10 +.iowt 20 C C 3b. check stat (stat as for 1a.) C @@ -2136,7 +2137,7 @@ tx8 00000011 tx8 11000000 txeop -.iowt 10 +.iowt 20 C C 4b. check stat (stat as for 1a.) C @@ -2193,7 +2194,7 @@ txsop tx8 00001000 txeop -.iowt 10 +.iowt 20 C C 1b. check stat (cerr=1, last successfull command in Test 21a/5a) C @@ -2220,7 +2221,7 @@ tx8 00001000 tx8 11110001 txeop -.iowt 10 +.iowt 20 C C 2b. check stat (cerr=1) C @@ -2275,7 +2276,7 @@ txsop tx8 00001011 txeop -.iowt 10 +.iowt 20 C C 1b. check stat (cerr=1) C stat: stat(000),attn(0),cerr(1),derr(0),rbnak(0),rberr(0) -> 00001000 @@ -2302,7 +2303,7 @@ tx8 00001011 tx8 11110010 txeop -.iowt 10 +.iowt 20 C C 2b. check stat (cerr=1) C @@ -2329,7 +2330,7 @@ tx8 11110010 tx8 00000001 txeop -.iowt 10 +.iowt 20 C C 3b. check stat (cerr=1) C @@ -2389,7 +2390,7 @@ txcrc tx8 00000001 txeop -.iowt 10 +.iowt 20 C C 5b. check stat (ccmd is wblk now; cerr=0,derr=1) C @@ -2420,7 +2421,7 @@ tx8 00000001 tx8 00011011 txeop -.iowt 10 +.iowt 20 C C 6b. check stat (ccmd is wblk now; cerr=0,derr=1) C @@ -2452,7 +2453,7 @@ tx8 00100011 tx8 00000010 txeop -.iowt 10 +.iowt 20 C C 7b. check stat (ccmd is wblk now; cerr=0,derr=1) C @@ -2485,7 +2486,7 @@ tx8 00000010 tx8 00101011 txeop -.iowt 10 +.iowt 20 C C 8b. check stat (ccmd is wblk now; cerr=0,derr=1) C @@ -2588,7 +2589,7 @@ txsop tx8 00010001 txeop -.iowt 10 +.iowt 20 # C C 2b. check stat (cerr=1) @@ -2615,7 +2616,7 @@ tx8 00011001 tx8 11110010 txeop -.iowt 10 +.iowt 20 # C C 3b. check stat (cerr=1) @@ -2642,7 +2643,7 @@ tx8 11110010 tx8 00000001 txeop -.iowt 10 +.iowt 20 # C C 4b. check stat (cerr=1) @@ -2704,7 +2705,7 @@ txsop tx8 00001100 txeop -.iowt 10 +.iowt 20 # C C 2. normal stat, finally @@ -2747,7 +2748,7 @@ txsop tx8 00001101 txeop -.iowt 10 +.iowt 20 C C 1b. check stat C stat: stat(000),attn(1),cerr(1),derr(0),rbnak(0),rberr(0) -> 00011000 @@ -2805,7 +2806,7 @@ txsop tx8 00010110 txeop -.iowt 10 +.iowt 20 C C 1b. check stat C stat: stat(000),attn(0),cerr(1),derr(0),rbnak(0),rberr(0) -> 00001000 @@ -2831,7 +2832,7 @@ tx8 00010110 tx8 11110000 txeop -.iowt 10 +.iowt 20 C C 2b. check stat C @@ -2857,7 +2858,7 @@ tx8 11110000 tx8 00000010 txeop -.iowt 10 +.iowt 20 C C 3b. check stat C @@ -2884,7 +2885,7 @@ tx8 00000010 tx8 00000000 txeop -.iowt 10 +.iowt 20 C C 4b. check stat C Index: rtl/vlib/rlink/tb/tb_rlink_sp1c.vhd =================================================================== --- rtl/vlib/rlink/tb/tb_rlink_sp1c.vhd (nonexistent) +++ rtl/vlib/rlink/tb/tb_rlink_sp1c.vhd (revision 16) @@ -0,0 +1,45 @@ +-- $Id: tb_rlink_sp1c.vhd 442 2011-12-23 10:03:28Z mueller $ +-- +-- Copyright 2007-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_rlink_sp1c +-- Description: Configuration for tb_rlink_sp1c for tb_rlink. +-- +-- Dependencies: tbd_rlink_gen +-- +-- To test: rlink_sp1c +-- +-- Target Devices: generic +-- +-- Verified (with tb_rlink_stim.dat): +-- Date Rev Code ghdl ise Target Comment +-- 2007-10-12 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (Test 15 fails) +-- 2007-10-12 88 - 0.26 - - c:ok (Test 15 fails) +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-22 442 3.2 renamed and retargeted to tbd_rlink_sp1c +-- 2010-12-05 343 3.0 rri->rlink renames +-- 2007-11-25 98 1.0.1 use entity rather arch name to switch core/serport +-- 2007-07-08 65 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_rlink_sp1c of tb_rlink is + + for sim + for all : tbd_rlink_gen + use entity work.tbd_rlink_sp1c; + end for; + end for; + +end tb_rlink_sp1c; Index: rtl/vlib/rlink/tb/Makefile =================================================================== --- rtl/vlib/rlink/tb/Makefile (revision 15) +++ rtl/vlib/rlink/tb/Makefile (revision 16) @@ -1,9 +1,8 @@ -# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $ +# $Id: Makefile 442 2011-12-23 10:03:28Z mueller $ # # Revision History: # Date Rev Version Comment # 2011-08-13 405 1.4 use includes from rtl/make -# 2010-12-28 349 1.3.1 add tb_rlink_tba_eyemon # 2010-12-05 343 1.3 rri->rlink renames # 2009-11-21 252 1.2 add ISim support # 2007-11-03 95 1.1.2 use .log rather .dat output in check_dsim @@ -11,8 +10,8 @@ # 2007-06-29 61 1.1 add clean and all # 2007-06-10 51 1.0 Initial version # -EXE_all = tb_rlink_direct tb_rlink_serport \ - tb_rlink_tba_ttcombo tb_rlink_tba_eyemon +EXE_all = tb_rlink_direct +EXE_all += tb_rlink_sp1c # # .PHONY : all all_ssim all_tsim clean Index: rtl/vlib/rlink/tb/.cvsignore =================================================================== --- rtl/vlib/rlink/tb/.cvsignore (revision 15) +++ rtl/vlib/rlink/tb/.cvsignore (revision 16) @@ -3,10 +3,10 @@ tb_rlink_direct_[sft]sim tb_rlink_direct_ISim tb_rlink_direct_ISim_[sft]sim -tb_rlink_serport -tb_rlink_serport_[sft]sim -tb_rlink_serport_ISim -tb_rlink_serport_ISim_[sft]sim +tb_rlink_sp1c +tb_rlink_sp1c_[sft]sim +tb_rlink_sp1c_ISim +tb_rlink_sp1c_ISim_[sft]sim tb_rlink_tba_stim tb_rlink_tba_ttcombo tb_rlink_tba_ttcombo_[sft]sim Index: rtl/vlib/rlink/tb/tbd_rlink_sp1c.vhd =================================================================== --- rtl/vlib/rlink/tb/tbd_rlink_sp1c.vhd (nonexistent) +++ rtl/vlib/rlink/tb/tbd_rlink_sp1c.vhd (revision 16) @@ -0,0 +1,250 @@ +-- $Id: tbd_rlink_sp1c.vhd 442 2011-12-23 10:03:28Z mueller $ +-- +-- Copyright 2007-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tbd_rlink_sp1c - syn +-- Description: Wrapper for rlink_core plus rlink_serport with an interface +-- compatible to the rlink_core only module. +-- NOTE: this implementation is a hack, should be redone +-- using configurations. +-- +-- Dependencies: tbu_rlink_sp1c [UUT] +-- serport_uart_tx +-- serport_uart_rx +-- byte2cdata +-- cdata2byte +-- +-- To test: rlink_sp1c +-- +-- Target Devices: generic +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-22 442 3.1 renamed and retargeted to tbu_rlink_sp1c +-- 2011-11-19 427 3.0.5 now numeric_std clean +-- 2010-12-28 350 3.0.4 use CLKDIV/CDINIT=0; +-- 2010-12-26 348 3.0.3 add RTS/CTS ports for tbu_; +-- 2010-12-24 347 3.0.2 rename: CP_*->RL->* +-- 2010-12-22 346 3.0.1 removed proc_moni, use .rlmon cmd in test bench +-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol; +-- 2010-06-06 301 2.3 use NCOMM=4 (new eop,nak commas) +-- 2010-05-02 287 2.2.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM +-- drop RP_IINT signal from interfaces +-- 2010-04-24 281 2.2.1 use serport_uart_[tr]x directly again +-- 2010-04-03 274 2.2 add CE_USEC +-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage +-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface +-- 2007-11-25 98 1.1 added RP_IINT support; use entity rather arch +-- name to switch core/serport; +-- use serport_uart_[tr]x_tb to allow that UUT is a +-- [sft]sim model compiled with keep hierarchy +-- 2007-07-02 63 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.rlinklib.all; +use work.comlib.all; +use work.serport.all; +use work.simlib.all; +use work.simbus.all; + +entity tbd_rlink_sp1c is -- rlink_sp1c tb design + -- implements tbd_rlink_gen + port ( + CLK : in slbit; -- clock + CE_INT : in slbit; -- rlink ito time unit clock enable + CE_USEC : in slbit; -- 1 usec clock enable + RESET : in slbit; -- reset + RL_DI : in slv9; -- rlink: data in + RL_ENA : in slbit; -- rlink: data enable + RL_BUSY : out slbit; -- rlink: data busy + RL_DO : out slv9; -- rlink: data out + RL_VAL : out slbit; -- rlink: data valid + RL_HOLD : in slbit; -- rlink: data hold + RB_MREQ_aval : out slbit; -- rbus: request - aval + RB_MREQ_re : out slbit; -- rbus: request - re + RB_MREQ_we : out slbit; -- rbus: request - we + RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll + RB_MREQ_addr : out slv8; -- rbus: request - addr + RB_MREQ_din : out slv16; -- rbus: request - din + RB_SRES_ack : in slbit; -- rbus: response - ack + RB_SRES_busy : in slbit; -- rbus: response - busy + RB_SRES_err : in slbit; -- rbus: response - err + RB_SRES_dout : in slv16; -- rbus: response - dout + RB_LAM : in slv16; -- rbus: look at me + RB_STAT : in slv3; -- rbus: status flags + TXRXACT : out slbit -- txrx active flag + ); +end entity tbd_rlink_sp1c; + + +architecture syn of tbd_rlink_sp1c is + + constant CDWIDTH : positive := 13; + constant c_cdinit : natural := 0; -- NOTE: change in tbu_rlink_sp1c !! + + signal RRI_RXSD : slbit := '0'; + signal RRI_TXSD : slbit := '0'; + signal RTS_N : slbit := '0'; + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXACT : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + signal CLKDIV : slv13 := slv(to_unsigned(c_cdinit,CDWIDTH)); + +component tbu_rlink_sp1c is -- rlink core+serport combo + port ( + CLK : in slbit; -- clock + CE_INT : in slbit; -- rlink ito time unit clock enable + CE_USEC : in slbit; -- 1 usec clock enable + CE_MSEC : in slbit; -- 1 msec clock enable + RESET : in slbit; -- reset + RXSD : in slbit; -- receive serial data (board view) + TXSD : out slbit; -- transmit serial data (board view) + CTS_N : in slbit; -- clear to send (act.low, board view) + RTS_N : out slbit; -- request to send (act.low, board view) + RB_MREQ_aval : out slbit; -- rbus: request - aval + RB_MREQ_re : out slbit; -- rbus: request - re + RB_MREQ_we : out slbit; -- rbus: request - we + RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll + RB_MREQ_addr : out slv8; -- rbus: request - addr + RB_MREQ_din : out slv16; -- rbus: request - din + RB_SRES_ack : in slbit; -- rbus: response - ack + RB_SRES_busy : in slbit; -- rbus: response - busy + RB_SRES_err : in slbit; -- rbus: response - err + RB_SRES_dout : in slv16; -- rbus: response - dout + RB_LAM : in slv16; -- rbus: look at me + RB_STAT : in slv3 -- rbus: status flags + ); +end component; + +begin + + UUT : tbu_rlink_sp1c + port map ( + CLK => CLK, + CE_INT => CE_INT, + CE_USEC => CE_USEC, + CE_MSEC => '1', + RESET => RESET, + RXSD => RRI_RXSD, + TXSD => RRI_TXSD, + CTS_N => '0', + RTS_N => RTS_N, + RB_MREQ_aval => RB_MREQ_aval, + RB_MREQ_re => RB_MREQ_re, + RB_MREQ_we => RB_MREQ_we, + RB_MREQ_initt=> RB_MREQ_initt, + RB_MREQ_addr => RB_MREQ_addr, + RB_MREQ_din => RB_MREQ_din, + RB_SRES_ack => RB_SRES_ack, + RB_SRES_busy => RB_SRES_busy, + RB_SRES_err => RB_SRES_err, + RB_SRES_dout => RB_SRES_dout, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT + ); + + UARTRX : serport_uart_rx + generic map ( + CDWIDTH => CDWIDTH) + port map ( + CLK => CLK, + RESET => RESET, + CLKDIV => CLKDIV, + RXSD => RRI_TXSD, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => open, + RXACT => RXACT + ); + + UARTTX : serport_uart_tx + generic map ( + CDWIDTH => CDWIDTH) + port map ( + CLK => CLK, + RESET => RESET, + CLKDIV => CLKDIV, + TXSD => RRI_RXSD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + TXRXACT <= RXACT or TXBUSY; + + B2CD : byte2cdata -- byte stream -> 9bit comma,data + generic map ( + CPREF => c_rlink_cpref, + NCOMM => c_rlink_ncomm) + port map ( + CLK => CLK, + RESET => RESET, + DI => RXDATA, + ENA => RXVAL, + BUSY => open, + DO => RL_DO, + VAL => RL_VAL, + HOLD => RL_HOLD + ); + + CD2B : cdata2byte -- 9bit comma,data -> byte stream + generic map ( + CPREF => c_rlink_cpref, + NCOMM => c_rlink_ncomm) + port map ( + CLK => CLK, + RESET => RESET, + DI => RL_DI, + ENA => RL_ENA, + BUSY => RL_BUSY, + DO => TXDATA, + VAL => TXENA, + HOLD => TXBUSY + ); + + proc_moni: process + variable oline : line; + variable rts_last : slbit := '0'; + variable ncycle : integer := 0; + begin + loop + wait until rising_edge(CLK); -- check at end of clock cycle + if RTS_N /= rts_last then + writetimestamp(oline, SB_CLKCYCLE, ": rts "); + write(oline, string'(" RTS_N ")); + write(oline, rts_last, right, 1); + write(oline, string'(" -> ")); + write(oline, RTS_N, right, 1); + write(oline, string'(" after ")); + write(oline, ncycle, right, 5); + write(oline, string'(" cycles")); + writeline(output, oline); + rts_last := RTS_N; + ncycle := 0; + end if; + ncycle := ncycle + 1; + end loop; + end process proc_moni; + +end syn; Index: rtl/vlib/rlink/tb =================================================================== --- rtl/vlib/rlink/tb (revision 15) +++ rtl/vlib/rlink/tb (revision 16)
rtl/vlib/rlink/tb Property changes : Modified: svn:ignore ## -35,10 +35,10 ## tb_rlink_direct_[sft]sim tb_rlink_direct_ISim tb_rlink_direct_ISim_[sft]sim -tb_rlink_serport -tb_rlink_serport_[sft]sim -tb_rlink_serport_ISim -tb_rlink_serport_ISim_[sft]sim +tb_rlink_sp1c +tb_rlink_sp1c_[sft]sim +tb_rlink_sp1c_ISim +tb_rlink_sp1c_ISim_[sft]sim tb_rlink_tba_stim tb_rlink_tba_ttcombo tb_rlink_tba_ttcombo_[sft]sim Index: rtl/vlib/rlink/rlinklib.vhd =================================================================== --- rtl/vlib/rlink/rlinklib.vhd (revision 15) +++ rtl/vlib/rlink/rlinklib.vhd (revision 16) @@ -1,4 +1,4 @@ --- $Id: rlinklib.vhd 427 2011-11-19 21:04:11Z mueller $ +-- $Id: rlinklib.vhd 442 2011-12-23 10:03:28Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -20,6 +20,8 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-12-21 442 3.2.1 retire old, deprecated interfaces +-- 2011-12-09 437 3.2 add rlink_core8 -- 2011-11-18 427 3.1.3 now numeric_std clean -- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core; -- new rlink_serport interface; @@ -52,6 +54,7 @@ use work.slvtypes.all; use work.rblib.all; +use work.serport.all; package rlinklib is @@ -100,6 +103,11 @@ -- As workaround the ibus default addresses are defined here as constant. constant rbaddr_rlink_serport : slv8 := slv(to_unsigned(2#11111110#,8)); +-- this definition logically belongs into the 'for test benches' section' +-- must be here because it is needed as generic default in rlink_core8 +-- simbus sb_cntl field usage for rlink +constant sbcntl_sbf_rlmon : integer := 15; + component rlink_core is -- rlink core with 9bit iface generic ( ATOWIDTH : positive := 5; -- access timeout counter width @@ -136,44 +144,11 @@ ); end component; -component rlink_rlb2rl is -- rlink 8 bit(rlb) to 9 bit(rl) adapter +component rlink_core8 is -- rlink core with 8bit iface generic ( - CPREF : slv4 := c_rlink_cpref; -- comma prefix - IFAWIDTH : natural := 5; -- input fifo address width (0=none) - OFAWIDTH : natural := 5); -- output fifo address width (0=none) - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - RLB_DI : in slv8; -- rlink 8b: data in - RLB_ENA : in slbit; -- rlink 8b: data enable - RLB_BUSY : out slbit; -- rlink 8b: data busy - RLB_DO : out slv8; -- rlink 8b: data out - RLB_VAL : out slbit; -- rlink 8b: data valid - RLB_HOLD : in slbit; -- rlink 8b: data hold - IFIFO_SIZE : out slv4; -- input fifo size (4 msb's) - OFIFO_SIZE : out slv4; -- output fifo fill (4 msb's) - RL_DI : out slv9; -- rlink 9b: data in - RL_ENA : out slbit; -- rlink 9b: data enable - RL_BUSY : in slbit; -- rlink 9b: data busy - RL_DO : in slv9; -- rlink 9b: data out - RL_VAL : in slbit; -- rlink 9b: data valid - RL_HOLD : out slbit -- rlink 9b: data hold - ); -end component; - --- this definition logically belongs into the 'for test benches' section' --- must be here because it is needed as generic default in rlink_base --- simbus sb_cntl field usage for rlink - constant sbcntl_sbf_rlmon : integer := 15; - -component rlink_base is -- rlink base: core+rl2rlb+rlmon+rbmon - -- with buffered 8bit interface - generic ( ATOWIDTH : positive := 5; -- access timeout counter width ITOWIDTH : positive := 6; -- idle timeout counter width CPREF : slv4 := c_rlink_cpref; -- comma prefix - IFAWIDTH : natural := 5; -- input fifo address width (0=none) - OFAWIDTH : natural := 5; -- output fifo address width (0=none) ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none) ENAPIN_RBMON : integer := sbcntl_sbf_rbmon); -- SB_CNTL for rbmon (-1=none) port ( @@ -186,8 +161,6 @@ RLB_DO : out slv8; -- rlink 8b: data out RLB_VAL : out slbit; -- rlink 8b: data valid RLB_HOLD : in slbit; -- rlink 8b: data hold - IFIFO_SIZE : out slv4; -- input fifo size (4 msb's) - OFIFO_SIZE : out slv4; -- output fifo fill (4 msb's) RL_MONI : out rl_moni_type; -- rlink: monitor port RB_MREQ : out rb_mreq_type; -- rbus: request RB_SRES : in rb_sres_type; -- rbus: response @@ -196,57 +169,12 @@ ); end component; -type rl_ser_moni_type is record -- rlink_serport monitor port - rxerr : slbit; -- rx err - rxdrop : slbit; -- rx drop - rxact : slbit; -- rx active - txact : slbit; -- tx active - abact : slbit; -- ab active - abdone : slbit; -- ab done - clkdiv : slv16; -- clock divider -end record rl_ser_moni_type; +-- +-- core + concrete_interface combo's +-- -constant rl_ser_moni_init : rl_ser_moni_type := - ('0','0', -- rxerr,rxdrop - '0','0', -- rxact,txact - '0','0', -- abact,abdone - (others=>'0')); -- clkdiv - -constant c_rlink_serport_rbf_fena: integer := 12; -- -subtype c_rlink_serport_rbf_fwidth is integer range 11 downto 9; -- -subtype c_rlink_serport_rbf_fdelay is integer range 8 downto 6; -- -subtype c_rlink_serport_rbf_rtsoff is integer range 5 downto 3; -- -subtype c_rlink_serport_rbf_rtson is integer range 2 downto 0; -- - -component rlink_serport is -- rlink serport adapter +component rlink_sp1c is -- rlink_core8+serport_1clock combo generic ( - RB_ADDR : slv8 := rbaddr_rlink_serport; - CDWIDTH : positive := 13; -- clk divider width - CDINIT : natural := 15); -- clk divider initial/reset setting - port ( - CLK : in slbit; -- clock - CE_USEC : in slbit; -- 1 usec clock enable - CE_MSEC : in slbit; -- 1 msec clock enable - RESET : in slbit; -- reset - RXSD : in slbit; -- receive serial data (board view) - TXSD : out slbit; -- transmit serial data (board view) - CTS_N : in slbit := '0'; -- clear to send (act.low, board view) - RTS_N : out slbit; -- request to send (act.low, board view) - RLB_DI : out slv8; -- rlink 8b: data in - RLB_ENA : out slbit; -- rlink 8b: data enable - RLB_BUSY : in slbit; -- rlink 8b: data busy - RLB_DO : in slv8; -- rlink 8b: data out - RLB_VAL : in slbit; -- rlink 8b: data valid - RLB_HOLD : out slbit; -- rlink 8b: data hold - RB_MREQ : in rb_mreq_type; -- rbus: request (for inits only) - IFIFO_SIZE : in slv4; -- rlink_rlb2rb: input fifo size - RL_MONI : in rl_moni_type; -- rlink_core: monitor port - RL_SER_MONI : out rl_ser_moni_type -- rlink_serport: monitor port - ); -end component; - -component rlink_base_serport is -- rlink base+serport combo - generic ( ATOWIDTH : positive := 5; -- access timeout counter width ITOWIDTH : positive := 6; -- idle timeout counter width CPREF : slv4 := c_rlink_cpref; -- comma prefix @@ -254,7 +182,6 @@ OFAWIDTH : natural := 5; -- output fifo address width (0=none) ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none) ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none) - RB_ADDR : slv8 := rbaddr_rlink_serport; CDWIDTH : positive := 13; -- clk divider width CDINIT : natural := 15); -- clk divider initial/reset setting port ( @@ -263,6 +190,8 @@ CE_MSEC : in slbit; -- 1 msec clock enable CE_INT : in slbit := '0'; -- rri ito time unit clock enable RESET : in slbit; -- reset + ENAXON : in slbit; -- enable xon/xoff handling + ENAESC : in slbit; -- enable xon/xoff escaping RXSD : in slbit; -- receive serial data (board view) TXSD : out slbit; -- transmit serial data (board view) CTS_N : in slbit := '0'; -- clear to send (act.low, board view) @@ -272,7 +201,7 @@ RB_LAM : in slv16; -- rbus: look at me RB_STAT : in slv3; -- rbus: status flags RL_MONI : out rl_moni_type; -- rlink_core: monitor port - RL_SER_MONI : out rl_ser_moni_type -- rlink_serport: monitor port + SER_MONI : out serport_moni_type -- serport: monitor port ); end component;
/rtl/vlib/rlink/rlink_sp1c.vbom
0,0 → 1,10
# libs
../slvtypes.vhd
../rbus/rblib.vhd
rlinklib.vbom
../serport/serport.vhd
# components
rlink_core8.vbom
../serport/serport_1clock.vbom
# design
rlink_sp1c.vhd
/rtl/vlib/rlink/rlinklib.vbom
1,4 → 1,5
# libs
../slvtypes.vhd
../rbus/rblib.vhd
../serport/serport.vhd
rlinklib.vhd
/rtl/vlib/genlib/gray_cnt_gen.vhd
0,0 → 1,90
-- $Id: gray_cnt_gen.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_gen - syn
-- Description: Generic width Gray code counter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.genlib.all;
 
entity gray_cnt_gen is -- gray code counter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end entity gray_cnt_gen;
 
 
architecture syn of gray_cnt_gen is
 
begin
assert DWIDTH>=4
report "assert(DWIDTH>=4): only 4 or more bit width supported"
severity failure;
 
 
GRAY_4: if DWIDTH=4 generate
begin
CNT : gray_cnt_4
port map (
CLK => CLK,
RESET => RESET,
CE => CE,
DATA => DATA
);
end generate GRAY_4;
 
GRAY_5: if DWIDTH=5 generate
begin
CNT : gray_cnt_5
port map (
CLK => CLK,
RESET => RESET,
CE => CE,
DATA => DATA
);
end generate GRAY_5;
 
GRAY_N: if DWIDTH>5 generate
begin
CNT : gray_cnt_n
generic map (
DWIDTH => DWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CE => CE,
DATA => DATA
);
end generate GRAY_N;
 
end syn;
 
/rtl/vlib/genlib/gray_cnt_gen.vbom
0,0 → 1,9
# libs
../slvtypes.vhd
genlib.vhd
# components
gray_cnt_4.vhd
gray_cnt_5.vhd
gray_cnt_n.vhd
# design
gray_cnt_gen.vhd
/rtl/vlib/genlib/cdc_pulse.vhd
0,0 → 1,117
-- $Id: cdc_pulse.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: cdc_pulse - syn
-- Description: clock domain cross for pulse
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-09 422 1.0 Initial version
--
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
entity cdc_pulse is -- clock domain cross for pulse
generic (
POUT_SINGLE : boolean := false; -- if true: single cycle pout
BUSY_WACK : boolean := false); -- if true: busy waits for ack
port (
CLKM : in slbit; -- clock master
RESET : in slbit := '0'; -- M|reset
CLKS : in slbit; -- clock slave
PIN : in slbit; -- M|pulse in
BUSY : out slbit; -- M|busy
POUT : out slbit -- S|pulse out
);
end entity cdc_pulse;
 
 
architecture syn of cdc_pulse is
 
signal R_REQ : slbit := '0';
signal R_REQ_C : slbit := '0';
signal R_ACK : slbit := '0';
signal R_ACK_C : slbit := '0';
signal R_ACK_S : slbit := '0';
 
begin
 
proc_master: process (CLKM)
begin
if rising_edge(CLKM) then
if RESET = '1' then
R_REQ <= '0';
else
if PIN = '1' then
R_REQ <= '1';
elsif R_ACK_S = '1' then
R_REQ <= '0';
end if;
end if;
R_ACK_C <= R_ACK;
R_ACK_S <= R_ACK_C;
end if;
end process proc_master;
 
proc_slave: process (CLKS)
begin
if rising_edge(CLKS) then
R_REQ_C <= R_REQ;
R_ACK <= R_REQ_C;
end if;
end process proc_slave;
 
SINGLE1: if POUT_SINGLE = true generate
signal R_ACK_1 : slbit := '0';
signal R_POUT : slbit := '0';
begin
proc_pout: process (CLKS)
begin
if rising_edge(CLKS) then
R_ACK_1 <= R_ACK;
if R_ACK='1' and R_ACK_1='0' then
R_POUT <= '1';
else
R_POUT <= '0';
end if;
end if;
end process proc_pout;
POUT <= R_POUT;
end generate SINGLE1;
 
SINGLE0: if POUT_SINGLE = false generate
begin
POUT <= R_ACK;
end generate SINGLE0;
BUSY1: if BUSY_WACK = true generate
begin
BUSY <= R_REQ or R_ACK_S;
end generate BUSY1;
 
BUSY0: if BUSY_WACK = false generate
begin
BUSY <= R_REQ;
end generate BUSY0;
end syn;
 
/rtl/vlib/genlib/gray_cnt_n.vhd
0,0 → 1,112
-- $Id: gray_cnt_n.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_n - syn
-- Description: Genric width Gray code counter
--
-- Dependencies: -
-- Test bench: tb/tb_debounce_gen
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- DWIDTH LUT Flop clock(xst est.)
-- 4 6 5 305MHz/ 3.28ns
-- 5 8 6 286MHz/ 2.85ns
-- 8 13 9 234MHz/ 4.26ns
-- 16 56 17 149MHz/ 6.67ns
-- 32 95 33 161MHz/ 6.19ns
-- 64 188 68 126MHz/ 7.90ns
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.genlib.all;
 
entity gray_cnt_n is -- n bit gray code counter
generic (
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end entity gray_cnt_n;
 
 
architecture syn of gray_cnt_n is
 
signal R_AUX : slbit := '1';
signal R_DATA : slv(DWIDTH-1 downto 0) := (others=>'0');
signal N_DATA : slv(DWIDTH-1 downto 0) := (others=>'0');
 
begin
assert DWIDTH>=3
report "assert(DWIDTH>=3): only 3 bit or larger supported"
severity failure;
 
proc_regs: process (CLK)
begin
 
if rising_edge(CLK) then
if RESET = '1' then
R_AUX <= '1';
R_DATA <= (others=>'0');
elsif CE = '1' then
R_AUX <= not R_AUX;
R_DATA <= N_DATA;
end if;
end if;
end process proc_regs;
proc_next: process (R_AUX, R_DATA)
variable r : slv(DWIDTH-1 downto 0) := (others=>'0');
variable n : slv(DWIDTH-1 downto 0) := (others=>'0');
variable s : slbit := '0';
begin
 
r := R_DATA;
n := R_DATA;
s := '1';
if R_AUX = '1' then
n(0) := not r(0);
else
for i in 1 to DWIDTH-2 loop
if s='1' and r(i-1)='1' then
n(i) := not r(i);
end if;
s := s and not r(i-1);
end loop;
if s = '1' then
n(DWIDTH-1) := r(DWIDTH-2);
end if;
end if;
 
N_DATA <= n;
end process proc_next;
 
DATA <= R_DATA;
 
end syn;
 
/rtl/vlib/genlib/cdc_pulse.vbom
0,0 → 1,4
# libs
../slvtypes.vhd
# design
cdc_pulse.vhd
/rtl/vlib/genlib/gray2bin_gen.vhd
0,0 → 1,64
-- $Id: gray2bin_gen.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gray2bin_gen - syn
-- Description: Gray code to binary converter
--
-- Dependencies: -
-- Test bench: tb/tb_debounce_gen
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
entity gray2bin_gen is -- gray->bin converter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
DI : in slv(DWIDTH-1 downto 0); -- gray code input
DO : out slv(DWIDTH-1 downto 0) -- binary code output
);
end entity gray2bin_gen;
 
 
architecture syn of gray2bin_gen is
 
begin
 
proc_comb: process (DI)
 
variable ido : slv(DWIDTH-1 downto 0);
 
begin
 
ido := (others=>'0');
 
ido(DWIDTH-1) := DI(DWIDTH-1);
for i in DWIDTH-2 downto 0 loop
ido(i) := ido(i+1) xor DI(i);
end loop;
 
DO <= ido;
 
end process proc_comb;
 
end syn;
 
/rtl/vlib/genlib/gray2bin_gen.vbom
0,0 → 1,4
# libs
../slvtypes.vhd
# design
gray2bin_gen.vhd
/rtl/vlib/genlib/gray_cnt_4.vhd
0,0 → 1,103
-- $Id: gray_cnt_4.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_4 - syn
-- Description: 4 bit Gray code counter (ROM based)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- LUT Flop clock(xst est.)
-- 4 4 365MHz/ 2.76ns
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
entity gray_cnt_4 is -- 4 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv4 -- data out
);
end entity gray_cnt_4;
 
 
architecture syn of gray_cnt_4 is
 
signal R_DATA : slv4 := (others=>'0');
signal N_DATA : slv4 := (others=>'0');
-- Note: in xst 8.2.03 fsm_extract="no" is needed. Otherwise an fsm is
-- inferred. For 4 bit the coding was 'Gray', but see remarks in
-- gray_cnt_5. To be save, disallow fsm inferal, enforce reg+rom.
 
attribute fsm_extract : string;
attribute fsm_extract of R_DATA : signal is "no";
attribute rom_style : string;
attribute rom_style of N_DATA : signal is "distributed";
 
begin
 
proc_regs: process (CLK)
begin
 
if rising_edge(CLK) then
if RESET = '1' then
R_DATA <= (others=>'0');
elsif CE = '1' then
R_DATA <= N_DATA;
end if;
end if;
end process proc_regs;
proc_next: process (R_DATA)
begin
 
N_DATA <= (others=>'0');
case R_DATA is
when "0000" => N_DATA <= "0001"; -- 0
when "0001" => N_DATA <= "0011"; -- 1
when "0011" => N_DATA <= "0010"; -- 2
when "0010" => N_DATA <= "0110"; -- 3
when "0110" => N_DATA <= "0111"; -- 4
when "0111" => N_DATA <= "0101"; -- 5
when "0101" => N_DATA <= "0100"; -- 6
when "0100" => N_DATA <= "1100"; -- 7
when "1100" => N_DATA <= "1101"; -- 8
when "1101" => N_DATA <= "1111"; -- 9
when "1111" => N_DATA <= "1110"; -- 10
when "1110" => N_DATA <= "1010"; -- 11
when "1010" => N_DATA <= "1011"; -- 12
when "1011" => N_DATA <= "1001"; -- 13
when "1001" => N_DATA <= "1000"; -- 14
when "1000" => N_DATA <= "0000"; -- 15
when others => null;
end case;
end process proc_next;
 
DATA <= R_DATA;
 
end syn;
 
/rtl/vlib/genlib/gray_cnt_5.vhd
0,0 → 1,121
-- $Id: gray_cnt_5.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_5 - syn
-- Description: 5 bit Gray code counter (ROM based)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- LUT Flop clock(xst est.)
-- 9 5 302MHz/ 3.31ns
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
entity gray_cnt_5 is -- 5 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv5 -- data out
);
end entity gray_cnt_5;
 
 
architecture syn of gray_cnt_5 is
 
signal R_DATA : slv5 := (others=>'0');
signal N_DATA : slv5 := (others=>'0');
 
-- Note: in xst 8.2.03 fsm_extract="no" is needed. Otherwise an fsm
-- is inferred, using 'Johnson' encoding. DATA will be deduced
-- in a combinatorial logic, and will thus have very likely some
-- glitches at the clock transitions, rendering the whole Gray
-- coding useless.
attribute fsm_extract : string;
attribute fsm_extract of R_DATA : signal is "no";
attribute rom_style : string;
attribute rom_style of N_DATA : signal is "distributed";
 
begin
 
proc_regs: process (CLK)
begin
 
if rising_edge(CLK) then
if RESET = '1' then
R_DATA <= (others=>'0');
elsif CE = '1' then
R_DATA <= N_DATA;
end if;
end if;
end process proc_regs;
proc_next: process (R_DATA)
begin
 
N_DATA <= (others=>'0');
case R_DATA is
when "00000" => N_DATA <= "00001"; -- 0
when "00001" => N_DATA <= "00011"; -- 1
when "00011" => N_DATA <= "00010"; -- 2
when "00010" => N_DATA <= "00110"; -- 3
when "00110" => N_DATA <= "00111"; -- 4
when "00111" => N_DATA <= "00101"; -- 5
when "00101" => N_DATA <= "00100"; -- 6
when "00100" => N_DATA <= "01100"; -- 7
when "01100" => N_DATA <= "01101"; -- 8
when "01101" => N_DATA <= "01111"; -- 9
when "01111" => N_DATA <= "01110"; -- 10
when "01110" => N_DATA <= "01010"; -- 11
when "01010" => N_DATA <= "01011"; -- 12
when "01011" => N_DATA <= "01001"; -- 13
when "01001" => N_DATA <= "01000"; -- 14
when "01000" => N_DATA <= "11000"; -- 15
when "11000" => N_DATA <= "11001"; -- 16
when "11001" => N_DATA <= "11011"; -- 17
when "11011" => N_DATA <= "11010"; -- 18
when "11010" => N_DATA <= "11110"; -- 19
when "11110" => N_DATA <= "11111"; -- 20
when "11111" => N_DATA <= "11101"; -- 21
when "11101" => N_DATA <= "11100"; -- 22
when "11100" => N_DATA <= "10100"; -- 23
when "10100" => N_DATA <= "10101"; -- 24
when "10101" => N_DATA <= "10111"; -- 25
when "10111" => N_DATA <= "10110"; -- 26
when "10110" => N_DATA <= "10010"; -- 27
when "10010" => N_DATA <= "10011"; -- 28
when "10011" => N_DATA <= "10001"; -- 29
when "10001" => N_DATA <= "10000"; -- 30
when "10000" => N_DATA <= "00000"; -- 31
when others => null;
end case;
end process proc_next;
 
DATA <= R_DATA;
 
end syn;
 
/rtl/vlib/memlib/fifo_2c_dram.vbom
0,0 → 1,11
# libs
../slvtypes.vhd
../genlib/genlib.vhd
memlib.vhd
# components
[ghdl,isim]ram_1swar_1ar_gen.vbom
[xst]ram_1swar_1ar_gen_unisim.vbom
../genlib/gray_cnt_gen.vbom
../genlib/gray2bin_gen.vbom
# design
fifo_2c_dram.vhd
/rtl/vlib/memlib/fifo_2c_dram.vhd
0,0 → 1,336
-- $Id: fifo_2c_dram.vhd 424 2011-11-13 16:38:23Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fifo_2c_dram - syn
-- Description: FIFO, two clock domain, distributed RAM based, with
-- enable/busy/valid/hold interface.
--
-- Dependencies: ram_1swar_1ar_gen
-- genlib/gray_cnt_n
-- genlib/gray2bin_gen
--
-- Test bench: tb/tb_fifo_2c_dram
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.1 use capture+sync flops; reset now glitch free
-- 2011-11-07 421 1.0.2 now numeric_std clean
-- 2007-12-28 107 1.0.1 VAL=0 in cycle after RESETR=1
-- 2007-12-28 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2011-11-13 Rev 424: ise 13.1 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUT.l LUT.m LUT.s Flop Slice CLKW CLKR (xst est.)
-- 4 16 41 32 12 38 54 135MHz 115MHz ( 16 words)
-- 5 16 65 64 14 40 80 113MHz 116MHz ( 32 words)
-- - 2007-12-28 Rev 106: ise 8.2.03 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUT.l LUT.m Flop CLKW CLKR (xst est.)
-- 4 16 40 32 42 141MHz 165MHz ( 16 words)
-- 5 16 65 64 52 108MHz 108MHz ( 32 words)
-- 6 16 95 128 61 111MHz 113MHz ( 64 words)
-- 7 16 149 256 74 100MHz 96MHz (128 words)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.genlib.all;
use work.memlib.all;
 
entity fifo_2c_dram is -- fifo, 2 clock, dram based
generic (
AWIDTH : positive := 5; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLKW : in slbit; -- clock (write side)
CLKR : in slbit; -- clock (read side)
RESETW : in slbit; -- W|reset from write side
RESETR : in slbit; -- R|reset from read side
DI : in slv(DWIDTH-1 downto 0); -- W|input data
ENA : in slbit; -- W|write enable
BUSY : out slbit; -- W|write port hold
DO : out slv(DWIDTH-1 downto 0); -- R|output data
VAL : out slbit; -- R|read valid
HOLD : in slbit; -- R|read hold
SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read
);
end fifo_2c_dram;
 
 
architecture syn of fifo_2c_dram is
 
type regw_type is record
raddr_c : slv(AWIDTH-1 downto 0); -- read address (capt from CLKR)
raddr_s : slv(AWIDTH-1 downto 0); -- read address (sync in CLKW)
sizew : slv(AWIDTH-1 downto 0); -- slots to write
busy : slbit; -- busy flag
rstw : slbit; -- resetw active
rstw_sc : slbit; -- resetw (sync-capt from CLKR-CLKW)
rstw_ss : slbit; -- resetw (sync-sync from CLKR-CLKW)
rstr_c : slbit; -- resetr (capt from CLKR)
rstr_s : slbit; -- resetr (sync from CLKR)
end record regw_type;
 
constant regw_init : regw_type := (
slv(to_unsigned(0,AWIDTH)), -- raddr_c
slv(to_unsigned(0,AWIDTH)), -- raddr_s
slv(to_unsigned(0,AWIDTH)), -- sizew
'0', -- busy
'0','0','0', -- rstw,rstw_sc,rstw_ss
'0','0' -- rstr_c,rstr_s
);
 
type regr_type is record
waddr_c : slv(AWIDTH-1 downto 0); -- write address (capt from CLKW)
waddr_s : slv(AWIDTH-1 downto 0); -- write address (sync in CLKR)
sizer : slv(AWIDTH-1 downto 0); -- slots to read
val : slbit; -- valid flag
rstr : slbit; -- resetr active
rstr_sc : slbit; -- resetr (sync-capt from CLKW-CLKR)
rstr_ss : slbit; -- resetr (sync-sync from CLKW-CLKR)
rstw_c : slbit; -- resetw (capt from CLKW)
rstw_s : slbit; -- resetw (sync from CLKW)
end record regr_type;
 
constant regr_init : regr_type := (
slv(to_unsigned(0,AWIDTH)), -- waddr_c
slv(to_unsigned(0,AWIDTH)), -- waddr_s
slv(to_unsigned(0,AWIDTH)), -- sizer
'0', -- val
'0','0','0', -- rstr,rstr_sc,rstr_ss
'0','0' -- rstw_c,rstw_s
);
 
signal R_REGW : regw_type := regw_init; -- write side state registers
signal N_REGW : regw_type := regw_init; -- next values write side
signal R_REGR : regr_type := regr_init; -- read side state registers
signal N_REGR : regr_type := regr_init; -- next values read side
 
signal WADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
signal WADDR_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
signal WADDR_S_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR_S_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
 
signal GCW_RST : slbit := '0';
signal GCW_CE : slbit := '0';
signal GCR_RST : slbit := '0';
signal GCR_CE : slbit := '0';
 
begin
 
RAM : ram_1swar_1ar_gen -- dual ported memory
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH)
port map (
CLK => CLKW,
WE => GCW_CE,
ADDRA => WADDR,
ADDRB => RADDR,
DI => DI,
DOA => open,
DOB => DO
);
GCW : gray_cnt_gen -- gray counter for write address
generic map (
DWIDTH => AWIDTH)
port map (
CLK => CLKW,
RESET => GCW_RST,
CE => GCW_CE,
DATA => WADDR
);
GCR : gray_cnt_gen -- gray counter for read address
generic map (
DWIDTH => AWIDTH)
port map (
CLK => CLKR,
RESET => GCR_RST,
CE => GCR_CE,
DATA => RADDR
);
G2B_WW : gray2bin_gen -- gray->bin for waddr on write side
generic map (DWIDTH => AWIDTH)
port map (DI => WADDR, DO => WADDR_BIN);
G2B_WR : gray2bin_gen -- gray->bin for waddr on read side
generic map (DWIDTH => AWIDTH)
port map (DI => R_REGR.waddr_s, DO => WADDR_S_BIN);
G2B_RW : gray2bin_gen -- gray->bin for raddr on write side
generic map (DWIDTH => AWIDTH)
port map (DI => RADDR, DO => RADDR_BIN);
G2B_RR : gray2bin_gen -- gray->bin for raddr on read side
generic map (DWIDTH => AWIDTH)
port map (DI => R_REGW.raddr_s, DO => RADDR_S_BIN);
proc_regw: process (CLKW)
begin
if rising_edge(CLKW) then
R_REGW <= N_REGW;
end if;
end process proc_regw;
 
proc_nextw: process (R_REGW, RESETW, ENA, R_REGR,
RADDR, RADDR_S_BIN, WADDR_BIN)
 
variable r : regw_type := regw_init;
variable n : regw_type := regw_init;
variable ibusy : slbit := '0';
variable igcw_ce : slbit := '0';
variable igcw_rst : slbit := '0';
variable isizew : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
 
r := R_REGW;
n := R_REGW;
 
isizew := slv(unsigned(RADDR_S_BIN) + unsigned(not WADDR_BIN));
ibusy := '0';
igcw_ce := '0';
igcw_rst := '0';
 
if unsigned(isizew) = 0 then -- if no free slots
ibusy := '1'; -- next cycle busy=1
end if;
 
if ENA='1' and r.busy='0' then -- if ena=1 and this cycle busy=0
igcw_ce := '1'; -- write this value
if unsigned(isizew) = 1 then -- if this last free slot
ibusy := '1'; -- next cycle busy=1
end if;
end if;
if RESETW = '1' then -- reset(write side) request
n.rstw := '1'; -- set RSTW flag
elsif r.rstw_ss = '1' then -- request gone and return seen
n.rstw := '0'; -- clear RSTW flag
end if;
 
if r.rstw='1' and r.rstw_ss='1' then -- RSTW seen on write and read side
igcw_rst := '1'; -- clear write address counter
end if;
if r.rstr_s = '1' then -- RSTR active
igcw_rst := '1'; -- clear write address counter
end if;
 
if RESETW='1' or r.rstw='1' or r.rstw_ss='1' or r.rstr_s='1'
then -- RESETW or RESETR active
ibusy := '1'; -- signal write side busy
isizew := (others=>'1');
end if;
 
n.busy := ibusy;
n.sizew := isizew;
n.raddr_c := RADDR; -- data captuture from CLKR
n.raddr_s := r.raddr_c;
n.rstw_sc := R_REGR.rstw_s;
n.rstw_ss := r.rstw_sc;
n.rstr_c := R_REGR.rstr;
n.rstr_s := r.rstr_c;
 
N_REGW <= n;
 
GCW_CE <= igcw_ce;
GCW_RST <= igcw_rst;
BUSY <= r.busy;
SIZEW <= r.sizew;
 
end process proc_nextw;
 
proc_regr: process (CLKR)
begin
if rising_edge(CLKR) then
R_REGR <= N_REGR;
end if;
end process proc_regr;
 
proc_nextr: process (R_REGR, RESETR, HOLD, R_REGW,
WADDR, WADDR_S_BIN, RADDR_BIN)
 
variable r : regr_type := regr_init;
variable n : regr_type := regr_init;
variable ival : slbit := '0';
variable igcr_ce : slbit := '0';
variable igcr_rst : slbit := '0';
variable isizer : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
 
r := R_REGR;
n := R_REGR;
 
isizer := slv(unsigned(WADDR_S_BIN) - unsigned(RADDR_BIN));
ival := '1';
igcr_ce := '0';
igcr_rst := '0';
 
if unsigned(isizer) = 0 then -- if nothing to read
ival := '0'; -- next cycle val=0
end if;
 
if r.val='1' and HOLD='0' then -- this cycle val=1 and no hold
igcr_ce := '1'; -- retire this value
if unsigned(isizer) = 1 then -- if this is last one
ival := '0'; -- next cycle val=0
end if;
end if;
 
if RESETR = '1' then -- reset(read side) request
n.rstr := '1'; -- set RSTR flag
elsif r.rstr_ss = '1' then -- request gone and return seen
n.rstr := '0'; -- clear RSTR flag
end if;
 
if r.rstr='1' and r.rstr_ss='1' then -- RSTR seen on read and write side
igcr_rst := '1'; -- clear read address counter
end if;
if r.rstw_s = '1' then -- RSTW active
igcr_rst := '1'; -- clear read address counter
end if;
 
if RESETR='1' or r.rstr='1' or r.rstr_ss='1' or r.rstw_s='1'
then -- RESETR or RESETW active
ival := '0'; -- signal read side empty
isizer := (others=>'0');
end if;
n.val := ival;
n.sizer := isizer;
 
n.waddr_c := WADDR; -- data captuture from CLKW
n.waddr_s := r.waddr_c;
n.rstr_sc := R_REGW.rstr_s;
n.rstr_ss := r.rstr_sc;
n.rstw_c := R_REGW.rstw;
n.rstw_s := r.rstw_c;
 
N_REGR <= n;
 
GCR_CE <= igcr_ce;
GCR_RST <= igcr_rst;
VAL <= r.val;
SIZER <= r.sizer;
 
end process proc_nextr;
 
end syn;
/rtl/vlib/serport/serport_1clock.vbom
0,0 → 1,11
# libs
../slvtypes.vhd
serport.vhd
../memlib/memlib.vhd
# components
serport_uart_rxtx_ab.vbom
serport_xonrx.vbom
serport_xontx.vbom
../memlib/fifo_1c_dram.vbom
# design
serport_1clock.vhd
/rtl/vlib/serport/serport_2clock.vbom
0,0 → 1,13
# libs
../slvtypes.vhd
serport.vhd
../genlib/genlib.vhd
../memlib/memlib.vhd
# components
../genlib/cdc_pulse.vbom
serport_uart_rxtx_ab.vbom
serport_xonrx.vbom
serport_xontx.vbom
../memlib/fifo_2c_dram.vbom
# design
serport_2clock.vhd
/rtl/vlib/serport/serport_xonrx.vbom
0,0 → 1,5
# libs
../slvtypes.vhd
serport.vhd
# design
serport_xonrx.vhd
/rtl/vlib/serport/serport_xontx.vbom
0,0 → 1,5
# libs
../slvtypes.vhd
serport.vhd
# design
serport_xontx.vhd
/rtl/vlib/serport/serport_1clock.vhd
0,0 → 1,250
-- $Id: serport_1clock.vhd 438 2011-12-11 23:40:52Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_1clock - syn
-- Description: serial port: serial port module, 1 clock domain
--
-- Dependencies: serport_uart_rxtx_ab
-- serport_xonrx
-- serport_xontx
-- memlib/fifo_1c_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-11-13 424 13.1 O40d xc3s1000-4 157 337 64 232 s 9.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-10 438 1.0.2 internal reset on abact
-- 2011-12-09 437 1.0.1 rename stat->moni port
-- 2011-11-13 424 1.0 Initial version
-- 2011-10-23 419 0.5 First draft
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.serport.all;
use work.memlib.all;
 
entity serport_1clock is -- serial port module, 1 clock domain
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXHOLD : in slbit; -- receiver data hold
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
MONI : out serport_moni_type; -- serport monitor port
RXSD : in slbit; -- receive serial data (uart view)
TXSD : out slbit; -- transmit serial data (uart view)
RXRTS_N : out slbit; -- receive rts (uart view, act.low)
TXCTS_N : in slbit -- transmit cts (uart view, act.low)
);
end serport_1clock;
 
 
architecture syn of serport_1clock is
signal R_RXOK : slbit := '1';
 
signal RESET_INT : slbit := '0';
 
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
 
signal XONTX_TXENA : slbit := '0';
signal XONTX_TXBUSY : slbit := '0';
 
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXFIFO_SIZE : slv(RXFAWIDTH downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
 
signal RXERR : slbit := '0';
signal RXOVR : slbit := '0';
signal RXACT : slbit := '0';
signal ABACT : slbit := '0';
signal ABDONE : slbit := '0';
signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0');
 
signal TXOK : slbit := '0';
signal RXOK : slbit := '0';
begin
 
assert CDWIDTH<=16
report "assert(CDWIDTH<=16): max width of UART clock divider"
severity failure;
 
UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
RXSD => RXSD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
ABACT => ABACT,
ABDONE => ABDONE,
ABCLKDIV => ABCLKDIV
);
 
RESET_INT <= RESET or ABACT;
XONRX : serport_xonrx -- xon/xoff logic rx path
port map (
CLK => CLK,
RESET => RESET_INT,
ENAXON => ENAXON,
ENAESC => ENAESC,
UART_RXDATA => UART_RXDATA,
UART_RXVAL => UART_RXVAL,
RXDATA => RXFIFO_DI,
RXVAL => RXFIFO_ENA,
RXHOLD => RXFIFO_BUSY,
RXOVR => RXOVR,
TXOK => TXOK
);
 
XONTX : serport_xontx -- xon/xoff logic tx path
port map (
CLK => CLK,
RESET => RESET_INT,
ENAXON => ENAXON,
ENAESC => ENAESC,
UART_TXDATA => UART_TXDATA,
UART_TXENA => XONTX_TXENA,
UART_TXBUSY => XONTX_TXBUSY,
TXDATA => TXFIFO_DO,
TXENA => TXFIFO_VAL,
TXBUSY => TXFIFO_HOLD,
RXOK => RXOK,
TXOK => TXOK
);
RXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET_INT,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZE => RXFIFO_SIZE
);
 
TXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET_INT,
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZE => open
);
-- receive back preasure
-- on if fifo more than 3/4 full
-- off if fifo less than 1/2 full
proc_rxok: process (CLK)
constant rxsize_rxok_off : slv3 := "011";
constant rxsize_rxok_on : slv3 := "010";
variable rxsize_msb : slv3 := "000";
begin
if rising_edge(CLK) then
if RESET_INT = '1' then
R_RXOK <= '1';
else
rxsize_msb := RXFIFO_SIZE(RXFAWIDTH downto RXFAWIDTH-2);
if unsigned(rxsize_msb) >= unsigned(rxsize_rxok_off) then
R_RXOK <= '0';
elsif unsigned(rxsize_msb) <= unsigned(rxsize_rxok_on) then
R_RXOK <= '1';
end if;
end if;
end if;
end process proc_rxok;
 
RXOK <= R_RXOK;
RXRTS_N <= not R_RXOK;
 
proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY)
begin
if TXCTS_N = '0' then -- transmit cts asserted
UART_TXENA <= XONTX_TXENA;
XONTX_TXBUSY <= UART_TXBUSY;
else -- transmit cts not asserted
UART_TXENA <= '0';
XONTX_TXBUSY <= '1';
end if;
end process proc_cts;
 
MONI.rxerr <= RXERR;
MONI.rxovr <= RXOVR;
MONI.rxact <= RXACT;
MONI.txact <= UART_TXBUSY;
MONI.abact <= ABACT;
MONI.abdone <= ABDONE;
MONI.rxok <= RXOK;
MONI.txok <= TXOK;
proc_abclkdiv: process (ABCLKDIV)
begin
MONI.abclkdiv <= (others=>'0');
MONI.abclkdiv(ABCLKDIV'range) <= ABCLKDIV;
end process proc_abclkdiv;
 
end syn;
/rtl/vlib/serport/serport_2clock.vhd
0,0 → 1,384
-- $Id: serport_2clock.vhd 438 2011-12-11 23:40:52Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_2clock - syn
-- Description: serial port: serial port module, 2 clock domain
--
-- Dependencies: genlib/cdc_pulse
-- serport_uart_rxtx_ab
-- serport_xonrx
-- serport_xontx
-- memlib/fifo_2c_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-11-13 424 13.1 O40d xc3s1000-4 224 362 64 295 s 8.6/10.1
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-10 438 1.0.2 internal reset on abact
-- 2011-12-09 437 1.0.1 rename stat->moni port
-- 2011-11-13 424 1.0 Initial version
-- 2011-11-07 421 0.5 First draft
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.serport.all;
use work.genlib.all;
use work.memlib.all;
 
entity serport_2clock is -- serial port module, 2 clock domain
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLKU : in slbit; -- clock (backend:user)
RESET : in slbit; -- reset
CLKS : in slbit; -- clock (frontend:serial)
CES_MSEC : in slbit; -- S|1 msec clock enable
ENAXON : in slbit; -- U|enable xon/xoff handling
ENAESC : in slbit; -- U|enable xon/xoff escaping
RXDATA : out slv8; -- U|receiver data out
RXVAL : out slbit; -- U|receiver data valid
RXHOLD : in slbit; -- U|receiver data hold
TXDATA : in slv8; -- U|transmit data in
TXENA : in slbit; -- U|transmit data enable
TXBUSY : out slbit; -- U|transmit busy
MONI : out serport_moni_type; -- U|serport monitor port
RXSD : in slbit; -- S|receive serial data (uart view)
TXSD : out slbit; -- S|transmit serial data (uart view)
RXRTS_N : out slbit; -- S|receive rts (uart view, act.low)
TXCTS_N : in slbit -- S|transmit cts (uart view, act.low)
);
end serport_2clock;
 
 
architecture syn of serport_2clock is
type synu_type is record
rxact_c : slbit; -- rxact (capt from CLKS->CLKU)
rxact_s : slbit; -- rxact (sync in CLKU)
txact_c : slbit; -- txact (capt from CLKS->CLKU)
txact_s : slbit; -- txact (sync in CLKU)
abact_c : slbit; -- abact (capt from CLKS->CLKU)
abact_s : slbit; -- abact (sync in CLKU)
rxok_c : slbit; -- rxok (capt from CLKS->CLKU)
rxok_s : slbit; -- rxok (sync in CLKU)
txok_c : slbit; -- txok (capt from CLKS->CLKU)
txok_s : slbit; -- txok (sync in CLKU)
abclkdiv_c : slv(CDWIDTH-1 downto 0); -- abclkdiv (capt from CLKS->CLKU)
abclkdiv_s : slv(CDWIDTH-1 downto 0); -- abclkdiv (sync in CLKU)
end record synu_type;
 
constant synu_init : synu_type := (
'0','0', -- rxact_c,_s
'0','0', -- txact_c,_s
'0','0', -- abact_c,_s
'0','0', -- rxok_c,_s
'0','0', -- txok_c,_s
slv(to_unsigned(0,CDWIDTH)), -- abclkdiv_c
slv(to_unsigned(0,CDWIDTH)) -- abclkdiv_s
);
type syns_type is record
enaxon_c : slbit; -- enaxon (capt from CLKU->CLKS)
enaxon_s : slbit; -- enaxon (sync in CLKS)
enaesc_c : slbit; -- enaesc (capt from CLKU->CLKS)
enaesc_s : slbit; -- enaesc (sync in CLKS)
end record syns_type;
 
constant syns_init : syns_type := (
'0','0', -- enaxon_c,_s
'0','0' -- enaxon_c,_s
);
signal R_SYNU : synu_type := synu_init; -- sync registers (clku)
signal R_SYNS : syns_type := syns_init; -- sync registers (clks)
 
signal R_RXOK : slbit := '1';
 
signal RESET_INT : slbit := '0';
signal RESET_CLKS : slbit := '0';
 
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
 
signal XONTX_TXENA : slbit := '0';
signal XONTX_TXBUSY : slbit := '0';
 
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXFIFO_SIZEW : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal RXERR : slbit := '0';
signal RXOVR : slbit := '0';
signal RXACT : slbit := '0';
signal ABACT : slbit := '0';
signal ABDONE : slbit := '0';
signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0');
 
signal TXOK : slbit := '0';
signal RXOK : slbit := '0';
 
signal RXERR_CLKU : slbit := '0';
signal RXOVR_CLKU : slbit := '0';
signal ABDONE_CLKU : slbit := '0';
 
begin
 
assert CDWIDTH<=16
report "assert(CDWIDTH<=16): max width of UART clock divider"
severity failure;
 
CDC_RESET : cdc_pulse
generic map (
POUT_SINGLE => false,
BUSY_WACK => false)
port map (
CLKM => CLKU,
RESET => '0',
CLKS => CLKS,
PIN => RESET,
BUSY => open,
POUT => RESET_CLKS
);
UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT)
port map (
CLK => CLKS,
CE_MSEC => CES_MSEC,
RESET => RESET_CLKS,
RXSD => RXSD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
ABACT => ABACT,
ABDONE => ABDONE,
ABCLKDIV => ABCLKDIV
);
 
RESET_INT <= RESET_CLKS or ABACT;
XONRX : serport_xonrx -- xon/xoff logic rx path
port map (
CLK => CLKS,
RESET => RESET_INT,
ENAXON => R_SYNS.enaxon_s,
ENAESC => R_SYNS.enaesc_s,
UART_RXDATA => UART_RXDATA,
UART_RXVAL => UART_RXVAL,
RXDATA => RXFIFO_DI,
RXVAL => RXFIFO_ENA,
RXHOLD => RXFIFO_BUSY,
RXOVR => RXOVR,
TXOK => TXOK
);
 
XONTX : serport_xontx -- xon/xoff logic tx path
port map (
CLK => CLKS,
RESET => RESET_INT,
ENAXON => R_SYNS.enaxon_s,
ENAESC => R_SYNS.enaesc_s,
UART_TXDATA => UART_TXDATA,
UART_TXENA => XONTX_TXENA,
UART_TXBUSY => XONTX_TXBUSY,
TXDATA => TXFIFO_DO,
TXENA => TXFIFO_VAL,
TXBUSY => TXFIFO_HOLD,
RXOK => RXOK,
TXOK => TXOK
);
RXFIFO : fifo_2c_dram -- input fifo, 2 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLKS,
CLKR => CLKU,
RESETW => ABACT, -- clear fifo on abact
RESETR => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZEW => RXFIFO_SIZEW,
SIZER => open
);
 
TXFIFO : fifo_2c_dram -- output fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLKU,
CLKR => CLKS,
RESETW => RESET,
RESETR => ABACT, -- clear fifo on abact
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZEW => open,
SIZER => open
);
 
-- receive back preasure
-- on if fifo more than 3/4 full (less than 1/4 free)
-- off if fifo less than 1/2 full (more than 1/2 free)
proc_rxok: process (CLKS)
constant rxsize_rxok_off : slv2 := "01";
constant rxsize_rxok_on : slv2 := "10";
variable rxsize_msb : slv2 := "00";
begin
if rising_edge(CLKS) then
if RESET_INT = '1' then
R_RXOK <= '1';
else
rxsize_msb := RXFIFO_SIZEW(RXFAWIDTH-1 downto RXFAWIDTH-2);
if unsigned(rxsize_msb) < unsigned(rxsize_rxok_off) then
R_RXOK <= '0';
elsif unsigned(RXSIZE_MSB) >= unsigned(rxsize_rxok_on) then
R_RXOK <= '1';
end if;
end if;
end if;
end process proc_rxok;
 
RXOK <= R_RXOK;
RXRTS_N <= not R_RXOK;
 
proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY)
begin
if TXCTS_N = '0' then -- transmit cts asserted
UART_TXENA <= XONTX_TXENA;
XONTX_TXBUSY <= UART_TXBUSY;
else -- transmit cts not asserted
UART_TXENA <= '0';
XONTX_TXBUSY <= '1';
end if;
end process proc_cts;
 
proc_synu: process (CLKU)
begin
if rising_edge(CLKU) then
R_SYNU.rxact_c <= RXACT;
R_SYNU.rxact_s <= R_SYNU.rxact_c;
R_SYNU.txact_c <= UART_TXBUSY;
R_SYNU.txact_s <= R_SYNU.txact_c;
R_SYNU.abact_c <= ABACT;
R_SYNU.abact_s <= R_SYNU.abact_c;
R_SYNU.rxok_c <= RXOK;
R_SYNU.rxok_s <= R_SYNU.rxok_c;
R_SYNU.txok_c <= TXOK;
R_SYNU.txok_s <= R_SYNU.txok_c;
R_SYNU.abclkdiv_c <= ABCLKDIV;
R_SYNU.abclkdiv_s <= R_SYNU.abclkdiv_c;
end if;
end process proc_synu;
proc_syns: process (CLKS)
begin
if rising_edge(CLKS) then
R_SYNS.enaxon_c <= ENAXON;
R_SYNS.enaxon_s <= R_SYNS.enaxon_c;
R_SYNS.enaesc_c <= ENAESC;
R_SYNS.enaesc_s <= R_SYNS.enaesc_c;
end if;
end process proc_syns;
 
CDC_RXERR : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => RXERR,
BUSY => open,
POUT => RXERR_CLKU
);
CDC_RXOVR : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => RXOVR,
BUSY => open,
POUT => RXOVR_CLKU
);
CDC_ABDONE : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => ABDONE,
BUSY => open,
POUT => ABDONE_CLKU
);
MONI.rxerr <= RXERR_CLKU;
MONI.rxovr <= RXOVR_CLKU;
MONI.rxact <= R_SYNU.rxact_s;
MONI.txact <= R_SYNU.txact_s;
MONI.abact <= R_SYNU.abact_s;
MONI.abdone <= ABDONE_CLKU;
MONI.rxok <= R_SYNU.rxok_s;
MONI.txok <= R_SYNU.txok_s;
proc_abclkdiv: process (R_SYNU.abclkdiv_s)
begin
MONI.abclkdiv <= (others=>'0');
MONI.abclkdiv(R_SYNU.abclkdiv_s'range) <= R_SYNU.abclkdiv_s;
end process proc_abclkdiv;
end syn;
/rtl/vlib/serport/serport_xonrx.vhd
0,0 → 1,144
-- $Id: serport_xonrx.vhd 417 2011-10-22 10:30:29Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_xonrx - syn
-- Description: serial port: xon/xoff logic rx path
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 417 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.serport.all;
 
entity serport_xonrx is -- serial port: xon/xoff logic rx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_RXDATA : in slv8; -- uart data out
UART_RXVAL : in slbit; -- uart data valid
RXDATA : out slv8; -- user data out
RXVAL : out slbit; -- user data valid
RXHOLD : in slbit; -- user data hold
RXOVR : out slbit; -- user data overrun
TXOK : out slbit -- tx channel ok
);
end serport_xonrx;
 
 
architecture syn of serport_xonrx is
 
type regs_type is record
txok : slbit; -- tx channel ok state
escseen : slbit; -- escape seen
rxdata : slv8; -- user rxdata
rxval : slbit; -- user rxval
rxovr : slbit; -- user rxovr
end record regs_type;
 
constant regs_init : regs_type := (
'1', -- txok (startup default is ok !!)
'0', -- escseen
(others=>'0'), -- rxdata
'0','0' -- rxval,rxovr
);
 
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
 
proc_regs: process (CLK)
begin
 
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
 
end process proc_regs;
 
proc_next: process (R_REGS, ENAXON, ENAESC, UART_RXDATA, UART_RXVAL, RXHOLD)
 
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
 
r := R_REGS;
n := R_REGS;
 
if ENAXON = '0' then
n.txok := '1';
end if;
if ENAESC = '0' then
n.escseen := '0';
end if;
 
n.rxovr := '0'; -- ensure single clock pulse
 
if UART_RXVAL = '1' then
if ENAXON='1' and UART_RXDATA=c_serport_xon then
n.txok := '1';
elsif ENAXON='1' and UART_RXDATA=c_serport_xoff then
n.txok := '0';
elsif ENAESC='1' and UART_RXDATA=c_serport_xesc then
n.escseen := '1';
 
else
if r.escseen = '1' then
n.escseen := '0';
end if;
 
if r.rxval = '0' then
n.rxval := '1';
if r.escseen = '1' then
n.rxdata := not UART_RXDATA;
else
n.rxdata := UART_RXDATA;
end if;
else
n.rxovr := '1';
end if;
end if;
end if;
 
if r.rxval='1' and RXHOLD='0' then
n.rxval := '0';
end if;
N_REGS <= n;
 
RXDATA <= r.rxdata;
RXVAL <= r.rxval;
RXOVR <= r.rxovr;
TXOK <= r.txok;
end process proc_next;
 
end syn;
/rtl/vlib/serport/serport_xontx.vhd
0,0 → 1,157
-- $Id: serport_xontx.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_xontx - syn
-- Description: serial port: xon/xoff logic tx path
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 425 1.0 Initial version
-- 2011-10-22 417 0.5 First draft
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.serport.all;
 
entity serport_xontx is -- serial port: xon/xoff logic tx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_TXDATA : out slv8; -- uart data in
UART_TXENA : out slbit; -- uart data enable
UART_TXBUSY : in slbit; -- uart data busy
TXDATA : in slv8; -- user data in
TXENA : in slbit; -- user data enable
TXBUSY : out slbit; -- user data busy
RXOK : in slbit; -- rx channel ok
TXOK : in slbit -- tx channel ok
);
end serport_xontx;
 
 
architecture syn of serport_xontx is
 
type regs_type is record
ibuf : slv8; -- input buffer
ival : slbit; -- ibuf has valid data
obuf : slv8; -- output buffer
oval : slbit; -- obuf has valid data
rxok : slbit; -- rx channel ok state
enaxon_1 : slbit; -- last enaxon
escpend : slbit; -- escape pending
end record regs_type;
 
constant regs_init : regs_type := (
(others=>'0'),'0', -- ibuf,ival
(others=>'0'),'0', -- obuf,oval
'1', -- rxok (startup default is ok !!)
'0', -- enaxon_1
'0' -- escpend
);
 
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
 
proc_regs: process (CLK)
begin
 
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
 
end process proc_regs;
 
proc_next: process (R_REGS, ENAXON, ENAESC, UART_TXBUSY,
TXDATA, TXENA, RXOK, TXOK)
 
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
 
begin
 
r := R_REGS;
n := R_REGS;
 
if TXENA='1' and r.ival='0' then
n.ibuf := TXDATA;
n.ival := '1';
end if;
 
if r.oval = '0' then
if ENAXON='1' and r.rxok/=RXOK then
n.rxok := RXOK;
n.oval := '1';
if r.rxok = '0' then
n.obuf := c_serport_xon;
else
n.obuf := c_serport_xoff;
end if;
elsif TXOK = '1' then
if r.escpend = '1' then
n.obuf := not r.ibuf;
n.oval := '1';
n.escpend := '0';
n.ival := '0';
elsif r.ival = '1' then
if ENAESC='1' and (r.ibuf=c_serport_xon or
r.ibuf=c_serport_xoff or
r.ibuf=c_serport_xesc)
then
n.obuf := c_serport_xesc;
n.oval := '1';
n.escpend := '1';
else
n.obuf := r.ibuf;
n.oval := '1';
n.ival := '0';
end if;
end if;
end if;
end if;
 
if r.oval='1' and UART_TXBUSY='0' then
n.oval := '0';
end if;
-- FIXME: document this hack
n.enaxon_1 := ENAXON;
if ENAXON='1' and r.enaxon_1='0' then
n.rxok := not RXOK;
end if;
N_REGS <= n;
 
TXBUSY <= r.ival;
UART_TXDATA <= r.obuf;
UART_TXENA <= r.oval;
end process proc_next;
 
end syn;
/rtl/vlib/serport/serport.vhd
1,4 → 1,4
-- $Id: serport.vhd 424 2011-11-13 16:38:23Z mueller $
-- $Id: serport.vhd 437 2011-12-09 19:38:07Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
20,6 → 20,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-09 437 1.2.5 rename stat->moni port
-- 2011-10-23 419 1.2.4 remove serport_clkdiv_ consts;
-- 2011-10-22 417 1.2.3 add serport_xon(rx|tx) defs
-- 2011-10-14 416 1.2.2 add c_serport defs
159,7 → 160,7
);
end component;
 
type serport_stat_type is record -- serial port module status
type serport_moni_type is record -- serport monitor port
rxerr : slbit; -- receiver data error (frame error)
rxovr : slbit; -- receiver data overrun
rxact : slbit; -- receiver active
169,9 → 170,9
abclkdiv : slv16; -- autobauder clock divider
rxok : slbit; -- rx channel ok
txok : slbit; -- tx channel ok
end record serport_stat_type;
end record serport_moni_type;
constant serport_stat_init : serport_stat_type := (
constant serport_moni_init : serport_moni_type := (
'0','0', -- rxerr,rxovr
'0','0', -- rxact,txact
'0','0', -- abact,abdone
197,7 → 198,7
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
STAT : out serport_stat_type; -- serport module status
MONI : out serport_moni_type; -- serport monitor port
RXSD : in slbit; -- receive serial data (uart view)
TXSD : out slbit; -- transmit serial data (uart view)
RXRTS_N : out slbit; -- receive rts (uart view, act.low)
224,7 → 225,7
TXDATA : in slv8; -- U|transmit data in
TXENA : in slbit; -- U|transmit data enable
TXBUSY : out slbit; -- U|transmit busy
STAT : out serport_stat_type; -- U|serport module status
MONI : out serport_moni_type; -- U|serport monitor port
RXSD : in slbit; -- S|receive serial data (uart view)
TXSD : out slbit; -- S|transmit serial data (uart view)
RXRTS_N : out slbit; -- S|receive rts (uart view, act.low)
/rtl/vlib/xlib/dcm_sfs_unisim_s3.vhd
0,0 → 1,86
-- $Id: dcm_sfs_unisim_s3.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: dcm_sfs - syn
-- Description: DCM for simple frequency synthesis; SPARTAN-3 version
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-3A,-3E
-- Tool versions: xst 12.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-17 426 1.0.3 rename dcm_sp_sfs -> dcm_sfs, SPARTAN-3 version
-- 2011-11-10 423 1.0.2 add FAMILY generic, SPARTAN-3 support
-- 2010-11-12 338 1.0.1 drop SB_CLK generic; allow DIV=1,MUL=1 without DCM
-- 2010-11-07 337 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library unisim;
use unisim.vcomponents.ALL;
 
use work.slvtypes.all;
 
entity dcm_sfs is -- DCM for simple frequency synthesis
generic (
CLKFX_DIVIDE : positive := 1; -- FX clock divide (1-32)
CLKFX_MULTIPLY : positive := 1; -- FX clock multiply (2-32) (1->no DCM)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- dcm locked
);
end dcm_sfs;
 
 
architecture syn of dcm_sfs is
 
begin
 
assert (CLKFX_DIVIDE=1 and CLKFX_MULTIPLY=1) or CLKFX_MULTIPLY>=2
report "assert((FX_DIV=1 and FX_MULT)=1 or FX_MULT>=2"
severity failure;
 
DCM0: if CLKFX_DIVIDE=1 and CLKFX_MULTIPLY=1 generate
CLKFX <= CLKIN;
LOCKED <= '1';
end generate DCM0;
 
DCM1: if CLKFX_MULTIPLY>=2 generate
DCM : dcm
generic map (
CLK_FEEDBACK => "NONE",
CLKFX_DIVIDE => CLKFX_DIVIDE,
CLKFX_MULTIPLY => CLKFX_MULTIPLY,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DSS_MODE => "NONE")
port map (
CLKIN => CLKIN,
CLKFX => CLKFX,
LOCKED => LOCKED
);
 
end generate DCM1;
end syn;
/rtl/vlib/xlib/dcm_sfs_unisim_s3.vbom
0,0 → 1,5
# libs
../slvtypes.vhd
@lib:unisim
# design
dcm_sfs_unisim_s3.vhd
/doc/w11a_os_guide.txt
1,4 → 1,4
# $Id: w11a_os_guide.txt 428 2011-11-20 12:19:31Z mueller $
# $Id: w11a_os_guide.txt 442 2011-12-23 10:03:28Z mueller $
 
Guide to run operating system images on w11a systems
 
23,9 → 23,11
never gave reliable connections for higher Baud rates.
- A USB-RS232 cable with a FTDI FT232R chip, like the cable offered
by FTDI as US232R-100 worked fine.
- For FTDI USB-RS232 cables it is essential to set the latency
timer to 1 ms (from the power in default of 16 ms), e.g. with
- On older linux kernels (prior 2.6.32) it is essential to set the
latency timer for the FTDI USB-RS232 cable to 1 ms (from the power
in default of 16 ms), e.g. with
sudo $RETROBASE/tools/bin/set_ftdi_lat USB0 1
For linux kernel 2.6.32 or newer the default is 1 ms already.
- the following assumes that a USB-RS232 cable with FTDI chip is used
 
A 460k Baud connection gives in practice a disk throughput of about 20 kB/s.
37,14 → 39,14
 
- for s3board and nexys2
- connect the USB-RS232 cable to the RS232 port of the s3board or nexys2
- set the latency timer of the USB-RS232, e.g. with
- for kernel < 2.6.32: set the latency timer of the USB-RS232, e.g. with
sudo $RETROBASE/tools/bin/set_ftdi_lat USB0 1
- ensure that all 8 switches are in '0' position
- ensure that all 8 switches are in the indicated positions (SWI=xxxxxxxx)
- load the w11a design into the FPGA, e.g. via impact
 
- for nexys3
- connect USB cable to the 'usb uart' port (next to the 5 buttons)
- ensure that all 8 switches are in '0' position
- ensure that all 8 switches are in the indicated positions (SWI=xxxxxxxx)
- load the w11a design into the FPGA, e.g. via impact
 
3. Unix V5 system ---------------------------------------------------------
55,12 → 57,18
$RETROBASE/rtl/sys_gen/w11a/tb
 
- Setup USB-RS232 cable, start xterm in vt100 mode and the server backend
Note: It is essential that the settings of the board switches are correct
in the following indicated by SWI = xxxxxxxx.
 
cd $RETROBASE/rtl/sys_gen/w11a/tb
sudo $RETROBASE/tools/bin/set_ftdi_lat USB0 1
telnet_starter -d DL0 &
[for s3,n2:] dorri -u0,460 @uv5_boot.pcmd
[for n3:] dorri -u0,500,1,0 @uv5_boot.pcmd
[for s3,n2:]
SWI = 00000010
dorri -u0,460,1,2 @uv5_boot.pcmd
[for n3:]
SWI = 00000010
dorri -u0,2000,1,2 @uv5_boot.pcmd
 
- the boot dialog in the console xterm window will look like
(required input is in {..}, with {<CR>} denoting a carriage return:
94,13 → 102,19
$RETROBASE/rtl/sys_gen/w11a/tb
 
- Setup USB-RS232 cable, start two xterm in vt100 mode and the server backend
Note: It is essential that the settings of the board switches are correct
in the following indicated by SWI = xxxxxxxx.
 
cd $RETROBASE/rtl/sys_gen/w11a/tb
sudo $RETROBASE/tools/bin/set_ftdi_lat USB0 1
telnet_starter -d DL0 &
telnet_starter -d DL1 &
[for s3,n2:] dorri -u0,460 @211bsd_rk_boot.pcmd
[for n3:] dorri -u0,500,1,0 @211bsd_rk_boot.pcmd
[for s3,n2:]
SWI = 00000010
dorri -u0,460,1,2 @211bsd_rk_boot.pcmd
[for n3:]
SWI = 00000010
dorri -u0,2000,1,2 @211bsd_rk_boot.pcmd
 
- the boot dialog in the console xterm window will look like
(required input is in {..}, with {<CR>} denoting a carriage return:
/doc/w11a_tb_guide.txt
1,4 → 1,4
# $Id: w11a_tb_guide.txt 433 2011-11-27 22:04:39Z mueller $
# $Id: w11a_tb_guide.txt 442 2011-12-23 10:03:28Z mueller $
 
Guide to running w11a test benches
 
122,6 → 122,28
-> 1220255.0 ns 61003: DONE
-> real 1m09.738s user 1m09.588s sys 0m00.096s
 
- s3board sram controller test
 
cd $RETROBASE/rtl/bplib/s3board/tb
 
make tb_s3_sram_memctl
time tbw tb_s3_sram_memctl |\
tee tb_s3_sram_memctl_dsim.log | egrep "(FAIL|DONE)"
-> 5015.0 ns 241: DONE
-> real 0m00.113s user 0m00.068s sys 0m00.016s
 
 
- nexys2/nexys3 cram controller test
 
cd $RETROBASE/rtl/bplib/nxcramlib/tb
make tb_nx_cram_memctl_as
time tbw tb_nx_cram_memctl_as |\
tee tb_nx_cram_memctl_as_dsim.log | egrep "(FAIL|DONE)"
-> 24272.5 ns 1204: DONE
-> real 0m00.343s user 0m00.248s sys 0m00.100s
 
 
3. System tests benches ---------------------------------------------------
 
The system tests allow to verify to verify a full system design.
139,16 → 161,65
 
Currently two backend implementations are available:
- pi_rri: written in perl (old, slow, but full functionality)
- ti_tti: written in C++ and Tcl (new, fast, but as of V0.53 only with
- ti_tti: written in C++ and Tcl (new, fast, but as of V0.55 only with
limited functionality; will replace pi_rri).
 
4. Available system tests benches -----------------------------------------
 
4a. rlink tester -----------------------------------------------------
4a. serport tester -- --------------------------------------------
 
The sys_tst_serloop design is a test target for validating the serial
link UART stack. Send and receive throughput as well as loop-back tests
are supported
 
- sys_tst_serloop_s3 test bench
 
cd $RETROBASE/rtl/sys_gen/tst_serloop/s3board/tb
make tb_tst_serloop_s3
time tbw tb_tst_serloop_s3 |\
tee tb_tst_serloop_s3_dsim.log | egrep "(FAIL|DONE)"
-> 301353.3 ns 18068: DONE
-> real 0m1.422s user 0m1.372s sys 0m0.024s
 
- sys_tst_serloop_n2 test bench
 
cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys2/tb
make tb_tst_serloop1_n2
time tbw tb_tst_serloop1_n2 |\
tee tb_tst_serloop1_n2_dsim.log | egrep "(FAIL|DONE)"
-> 361560.0 ns 18068: DONE
-> real 0m1.341s user 0m1.340s sys 0m0.016s
 
make tb_tst_serloop2_n2
time tbw tb_tst_serloop2_n2 |\
tee tb_tst_serloop2_n2_dsim.log | egrep "(FAIL|DONE)"
-> 304353.3 ns 18248: DONE
-> real 0m1.933s user 0m1.924s sys 0m0.024s
 
- sys_tst_serloop_n3 test bench
 
cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys3/tb
make tb_tst_serloop1_n3
time tbw tb_tst_serloop1_n3 |\
tee tb_tst_serloop1_n3_dsim.log | egrep "(FAIL|DONE)"
-> 361560.0 ns 18068: DONE
-> real 0m1.371s user 0m1.372s sys 0m0.016s
 
4b. rlink tester -----------------------------------------------------
 
The sys_tst_rlink design is a test target for validating the rlink
and rbus functionality at all levels.
 
- sys_tst_rlink_s3 test bench
 
cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board/tb
make tb_tst_rlink_s3
time ti_rri --run="tbw tb_tst_rlink_s3" --fifo --logl=3 -- \
"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
tee tb_tst_rlink_s3_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
-> 1822195.0 ns 91100: DONE
-> real 0m13.281s
 
- sys_tst_rlink_n2 test bench
 
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb
155,7 → 226,7
make tb_tst_rlink_n2
time ti_rri --run="tbw tb_tst_rlink_n2" --fifo --logl=3 -- \
"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
tee tb_tst_rlink_n2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
tee tb_tst_rlink_n2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
-> 1769140.0 ns 88446: DONE
-> real 0m15.289s
 
165,11 → 236,11
make tb_tst_rlink_n3
time ti_rri --run="tbw tb_tst_rlink_n3" --fifo --logl=3 -- \
"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
tee tb_tst_rlink_n3_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
tee tb_tst_rlink_n3_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
-> 893590.0 ns 89338: DONE
-> real 0m9.510s
 
4b. w11a systems -----------------------------------------------------
4c. w11a systems -----------------------------------------------------
 
The stimulus file used in the w11a core test can be executed in the
full system context (both s3board and nexys2 versions) with the
185,8 → 256,8
time pi_rri --fifo --timeout=40. --cmax=3 \
--run="tbw tb_w11a_s3" -- \
@../../../../w11a/tb/tb_pdp11core_stim.dat |\
tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
-> 7757655.0 ns 387873: DONE
tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
-> 7852095.0 ns 392595: DONE
-> real 0m49.835s user 0m50.203s sys 0m00.696s
 
- sys_w11a_n2 test bench
196,9 → 267,9
time pi_rri --fifo --timeout=40. --cmax=3 \
--run="tbw tb_w11a_n2" -- \
@../../../../w11a/tb/tb_pdp11core_stim.dat |\
tee tb_w11a_n2_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
-> 6673237.2 ns 387035: DONE
-> real 0m56.173s user 0m56.612s sys 0m00.604s
tee tb_w11a_n2_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
-> 7836580.0 ns 391818: DONE
-> real 1m0.854s user 1m1.332s sys 0m0.800s
 
- sys_w11a_n3 test bench
 
207,6 → 278,7
time pi_rri --fifo --timeout=40. --cmax=3 \
--run="tbw tb_w11a_n3" -- \
@../../../../w11a/tb/tb_pdp11core_stim.dat |\
tee tb_w11a_n3_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
-> 4593598.2 ns 390438: DONE
-> real 0m55.326s user 0m55.711s sys 0m00.752s
tee tb_w11a_n3_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
-> 3956540.0 ns 395633: DONE
-> real 1m13.811s user 1m14.389s sys 0m0.948s
 
/doc/README.txt
1,4 → 1,4
# $Id: README.txt 434 2011-12-02 19:17:38Z mueller $
# $Id: README.txt 442 2011-12-23 10:03:28Z mueller $
 
Release notes for w11a
 
25,20 → 25,23
doc Documentation
rtl VHDL sources
rtl/bplib - board and component support libs
rtl/bplib/atlys - for Digilent Atlys board
rtl/bplib/issi - for ISSI parts
rtl/bplib/micron - for Micron parts
rtl/bplib/nexys2 - for Digilent Nexsy2 board
rtl/bplib/nexys3 - for Digilent Nexsy3 board
rtl/bplib/nxcramlib - for CRAM part used in Nexys2/3
rtl/bplib/s3board - for Digilent S3BOARD
rtl/ibus - ibus devices (UNIBUS peripherals)
rtl/sys_gen - top level designs
rtl/sys_gen/tst_rlink - top level designs for an rlink tester
rtl/sys_gen/tst_rlink/nexys2 - rlink tester system for Digilent Nexsy2
rtl/sys_gen/tst_rlink/nexys3 - rlink tester system for Digilent Nexsy3
nexys2,nexys3,s3board - systems for Nexsy2,Nexsy3,S3BOARD
rtl/sys_gen/tst_serloop - top level designs for serport loop tester
nexys2,nexys3,s3board - systems for Nexsy2,Nexsy3,S3BOARD
rtl/sys_gen/tst_snhumanio - top level designs for human I/O tester
atlys,nexys2,nexys3,s3board - systems for Atlys,Nexsy2,Nexsy3,S3BOARD
rtl/sys_gen/w11a - top level designs for w11a SoC
rtl/sys_gen/w11a/nexys2 - w11a SoC for Digilent Nexsy2
rtl/sys_gen/w11a/nexys3 - w11a SoC for Digilent Nexsy3
rtl/sys_gen/w11a/s3board - w11a SoC for Digilent S3BOARD
nexys2,nexys3,s3board - w11a systems for Nexsy2,Nexsy3,S3BOARD
rtl/vlib - VHDL component libs
rtl/vlib/comlib - communication
rtl/vlib/genlib - general
63,21 → 66,54
 
3. Change Log ----------------------------------------------------------------
 
- trunk (2011-12-04: svn rev 15(oc) 436(wfjm); untagged w11a_V0.54) +++++++++
- trunk (2011-12-23: svn rev 16(oc) 442(wfjm); untagged w11a_V0.55) +++++++++
 
- Summary
- added support for nexys3 board for w11a
- added xon/xoff (software flow control) support to serport library
- added test systems for serport verification
- use new serport stack in sys_w11a_* and sys_tst_rlink_* systems
 
- Changes
- retired modules
- vlib/rlink
- rlink_rlb2rl - obsolete, now all in rlink_core8
- rlink_base - use now new rlink_core8
- rlink_serport - obsolete, now all in rlink_sp1c
- rlink_base_serport - use now new rlink_sp1c
 
- New features
- new modules
- vlib/serport
- serport_xonrx - xon/xoff logic rx path
- serport_xontx - xon/xoff logic tx path
- serport_1clock - serial port module (uart, fifo, flow control)
- vlib/rlink
- rlink_core8 - rlink core8 with 8bit interface
- rlink_sp1c - rlink_core8 + serport_1clock combo
- new unit tests
- bplib/s3board/tb/tb_s3_sram_memctl (for s3board sram controller
- bplib/nxcramlib/tb/tb_nx_cram_memctl_as (for nexys2,3 cram controller)
- new systems
- sys_gen/w11a/sys_w11a_n3
- sys_gen/w11a/sys_tst_rlink_n3
- sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2
- sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3
- sys_gen/tst_serloop/s3board/sys_tst_serloop1_s3
- sys_gen/tst_rlink/s3board/sys_tst_rlink_s3
 
- trunk (2011-12-04: svn rev 15(oc) 436(wfjm); untagged w11a_V0.54) +++++++++
 
- Summary
- added support for nexys3 board for w11a
 
- Changes
- module renames:
bplib/nexys2/n2_cram_dummy -> bplib/nxcramlib/nx_cram_dummy
bplib/nexys2/n2_cram_memctl_as -> bplib/nxcramlib/nx_cram_memctl_as
 
- New features
- new systems
- sys_gen/w11a/nexys3/sys_w11a_n3
- sys_gen/w11a/nexys3/sys_tst_rlink_n3
 
- Bug fixes
- tools/src/lib*: backend libraries compile now on 64 bit systems
 
88,13 → 124,6
- added test design for the 'human I/O' interface
- no functional change of w11a CPU core or any existing test systems
 
- New features
- new modules
- rtl/sys_gen/tst_snhumanio
- sub-tree with test design for 'human I/O' interface modules
- atlys, nexys2, and s3board directories contain the systems
for the respectice Digilent boards
 
- Changes
- functional changes
- use now 'a6' polynomial of Koopman et al for crc8 in rlink
104,6 → 133,13
vlib/xlib/dcm_sp_sfs_unisim -> vlib/xlib/dcm_sfs_unisim_s3e
vlib/xlib/tb/tb_dcm_sp_sfs -> vlib/xlib/tb/tb_dcm_sfs
 
- New features
- new modules
- rtl/sys_gen/tst_snhumanio
- sub-tree with test design for 'human I/O' interface modules
- atlys, nexys2, and s3board directories contain the systems
for the respective Digilent boards
 
- trunk (2011-09-11: svn rev 12(oc) 409(wfjm); untagged w11a_V0.531) +++++++++
 
- Summary
136,7 → 172,7
 
- Summary
- Introduce C++ and Tcl based backend server. A set of C++ classes provide
the basic rlink communication promitives. Additional glue classes provide
the basic rlink communication primitives. Additional glue classes provide
a Tcl binding. This first phase contains the basic functionality needed
to control simple test benches.
- add an 'rlink exerciser' (tst_rlink) and a top level design for a Nexys2
228,7 → 264,7
ioto -> rbnak - indicates rbus abort, either no ack or timeout
ioerr -> rberr - indicates that rbus err flag was set
 
- migrate to rbus protocol verion 3
- migrate to rbus protocol version 3
- in rb_mreq use now aval,re,we instead of req,we
- basic rbus transaction now takes 2 cycles, one for address select, one
for data exchange. Same concept and reasoning behind as in ibus V2.
271,7 → 307,7
- renamed RRI_LAM -> RB_LAM in all ibus devices
- renamed CLK -> I_CLK50 in all top level nexys2 and s3board designs
 
- migrate to ibus protocol verion 2
- migrate to ibus protocol version 2
- in ib_mreq use now aval,re,we,rmw instead of req,we,dip
- basic ibus transaction now takes 2 cycles, one for address select, one
for data exchange. This avoids too long logic paths in the ibus logic.
/Makefile
0,0 → 1,67
# $Id: Makefile 442 2011-12-23 10:03:28Z mueller $
#
# 'Meta Makefile' for whole retro project
# allows to make all synthesis targets
# allows to make all test bench targets
#
# Revision History:
# Date Rev Version Comment
# 2011-11-27 433 1.0.2 add new nexys3 ports
# 2011-11-18 426 1.0.1 add tst_serport and tst_snhumanio
# 2011-07-09 391 1.0 Initial version
#
SYN_all += rtl/sys_gen/tst_rlink/nexys2
SYN_all += rtl/sys_gen/tst_rlink/nexys3
SYN_all += rtl/sys_gen/tst_rlink/s3board
SYN_all += rtl/sys_gen/tst_serloop/nexys2
SYN_all += rtl/sys_gen/tst_serloop/nexys3
SYN_all += rtl/sys_gen/tst_serloop/s3board
SYN_all += rtl/sys_gen/tst_snhumanio/atlys
SYN_all += rtl/sys_gen/tst_snhumanio/nexys2
SYN_all += rtl/sys_gen/tst_snhumanio/nexys3
SYN_all += rtl/sys_gen/tst_snhumanio/s3board
SYN_all += rtl/sys_gen/w11a/nexys2
SYN_all += rtl/sys_gen/w11a/nexys3
SYN_all += rtl/sys_gen/w11a/s3board
 
SIM_all += rtl/bplib/nxcramlib/tb
SIM_all += rtl/sys_gen/tst_rlink/nexys2/tb
SIM_all += rtl/sys_gen/tst_rlink/nexys3/tb
SIM_all += rtl/sys_gen/tst_rlink/s3board/tb
SIM_all += rtl/sys_gen/tst_serloop/nexys2/tb
SIM_all += rtl/sys_gen/tst_serloop/nexys3/tb
SIM_all += rtl/sys_gen/tst_serloop/s3board/tb
SIM_all += rtl/sys_gen/w11a/nexys2/tb
SIM_all += rtl/sys_gen/w11a/nexys3/tb
SIM_all += rtl/sys_gen/w11a/s3board/tb
SIM_all += rtl/vlib/rlink/tb
SIM_all += rtl/vlib/serport/tb
SIM_all += rtl/w11a/tb
#
.PHONY : all clean clean_sim clean_sym all_sim all_syn
.PHONY : $(SYN_all) $(SIM_all)
#
all :
@echo "no default action defined, use"
@echo " make all_sim"
@echo " make all_syn"
@echo " make clean"
@echo " make clean_sim"
@echo " make clean_syn"
#
#
clean : clean_sim clean_syn
#
clean_sim :
for dir in $(SIM_all); do $(MAKE) -C $$dir clean; done
clean_syn :
for dir in $(SYN_all); do $(MAKE) -C $$dir clean; done
#
all_sim : $(SIM_all)
all_syn : $(SYN_all)
#
$(SIM_all):
$(MAKE) -C $@
$(SYN_all):
$(MAKE) -C $@
#

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