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Rev 16 → Rev 17

/tools/fx2/src/usb_fifo_init.c
0,0 → 1,210
/* $Id: usb_fifo_init.c 450 2012-01-05 23:21:41Z mueller $ */
/*
* Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
* Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17
* The data fifo treatment is partially inspired by work of Marco Oster
* done at ZITI, Heidelberg in 2010.
*
* - original copyright and licence disclaimer (of usb_jtag_init) -------------
* - Code that turns a Cypress FX2 USB Controller into an USB JTAG adapter
* - Copyright (C) 2005..2007 Kolja Waschk, ixo.de
* - This code is part of usbjtag. usbjtag is free software;
*-----------------------------------------------------------------------------
*
* This program is free software; you may redistribute and/or modify it under
* the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 2, or at your option any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for complete details.
*
*-----------------------------------------------------------------------------
*
* USB FIFO setup
*
* Revision History:
*
* Date Rev Version Comment
* 2012-01-04 450 1.5 new FLAGS layout (D=8-FF,C=4-EF,B=6-FF,A=indexed)
* 2012-01-02 448 1.4 add support for sync fifo w/ int. clock (_ic)
* 2011-07-24 398 1.1 support 0,2, or 3 data FIFO's
* 2011-07-23 397 1.0 Initial version, factored out from usb_jtag_init()
*
*-----------------------------------------------------------------------------
*/
 
#include "fx2regs.h"
#include "syncdelay.h"
 
//-----------------------------------------------------------------------------
 
void usb_fifo_init(void) // Called once at startup
{
// set the CPU clock to 48MHz, enable USB clock output to FPGA
// Note: CLKOUT not connected on nexys2, nexys3 and atlys...
CPUCS = bmCLKOE | bmCLKSPD1;
 
// setup FIFO mode
// bmIFCLKSRC clock source: 0 external clock; 1 internal clock
// bm3048MHZ clock frequency: 0 30 MHz; 1 48 MHz
// bmIFCLKOE IFCLK pin output enable: 0 tri-state; 1 drive
// bmIFCLKPOL clock polarity: 0 rising edge active; 1 falling edge active
// bmASYNC fifo mode: 0 synchrounous; 1 asynchronous
// IFCFG interface mode: bmIFCFGMASK=11->slave fifo
 
#if defined(USE_IC30)
// Use internal 30 MHz, enable output, slave sync FIFO, slave FIFO mode
IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmIFCFGMASK;
#else
// Use internal 30 MHz, enable output, slave async FIFO, slave FIFO mode
IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmASYNC | bmIFCFGMASK;
#endif
 
// Setup PA7 as FLAGD
PORTACFG = 0x80; SYNCDELAY; // 1000 0000: FLAGD=1, SLCS=0
 
// setup usage of FLAG pins
// goal is to support EP4(out) and EP6/EP8(in) synchronous slave fifos
// for synchronous operation usage of empty/full and almost empty/full
// flags is needed, the later are realized with the programmable flags.
// the three empty/full flags are setup as fixed flags, while the three
// almost (or programmable) flags are channeled over one indexed flag pin.
// FLAGA = indexed, PF (the default)
// FLAGB = EP6 FF
// FLAGC = EP4 EF
// FLAGD = EP8 FF
 
PINFLAGSAB = 0xE0; SYNCDELAY; // 1110 0000: B EP6 FF, A indexed
PINFLAGSCD = 0xF9; SYNCDELAY; // 1111 1001: D EP8 FF, C EP4 EF
 
// define endpoint configuration
 
FIFORESET = 0x80; SYNCDELAY; // From now on, NAK all
REVCTL = 3; SYNCDELAY; // Allow FW access to FIFO buffer
 
// FIFOs used for JTAG emulation
// EP1 IN
// EP2 OUT
 
EP1OUTCFG = 0x00; SYNCDELAY; // EP1 OUT: inactive
EP1INCFG = 0xA0; SYNCDELAY; // EP1 IN: active, bulk
EP2FIFOCFG = 0x00; SYNCDELAY; // EP2 slave: 0, not used as slave
FIFORESET = 0x02; SYNCDELAY; // EP2 reset (0x02! see comment below)
EP2CFG = 0xA2; SYNCDELAY; // EP2: 1010 0010: VAL,OUT,BULK,DOUBLE
 
// TMR (Rev *D) page 117: auto in/out initialization sequence
// Auto IN transfers
// 1. setup EPxCFG
// 2. reset the FIFO
// 3. set EPxFIFOCFG.3 = 1
// 4. set EPxAUTOINLENH:L
// Auto OUT transfers
// 1. setup EPxCFG
// 2. reset the FIFO
// 3. arm OUT buffers by writing OUTPKTEND N times w/ skip=1 (N=buf depth)
// 4. set EPxFIFOCFG.4 = 1
 
// 2 FIFOs used for DATA transfer:
// EP4 OUT DOUBLE
// EP6 IN QUAD
 
#if defined(USE_2FIFO) || defined(USE_3FIFO)
EP4CFG = 0xA2; SYNCDELAY; // EP4: 1010 0010: VAL,OUT,BULK,DOUBLE
#if defined(USE_3FIFO)
EP6CFG = 0xE2; SYNCDELAY; // EP6: 1110 0010: VAL,IN,BULK,DOUBLE
EP8CFG = 0xE2; SYNCDELAY; // EP8: 1110 0010: VAL,IN,BULK,DOUBLE
#else
EP6CFG = 0xE0; SYNCDELAY; // EP6: 1110 0000: VAL,IN,BULK,QUAD
EP8CFG = 0x02; SYNCDELAY; // EP8: disabled
#endif
 
// Note: the description of the FIFORESET in the TMR, Rev *D (2011) is
// wrong. The TMR asks to write 0x80,0x82,0x84,0x86,0x88,0x00, e.g
// on page 117, also in other contexts.
// This doesn't work, FIFO's are in fact not reset !
// The proper sequence is 0x80,0x02,0x04,0x06,0x08,0x00, as for
// example stated in http://www.cypress.com/?id=4&rID=32093
FIFORESET = 0x04; SYNCDELAY; // EP4 reset
FIFORESET = 0x06; SYNCDELAY; // EP6 reset
FIFORESET = 0x08; SYNCDELAY; // EP8 reset
FIFORESET = 0x00; SYNCDELAY; // Restore normal behaviour
 
// !! really needed here, before buffers are armed !!
REVCTL = 0; SYNCDELAY; // Reset FW access to FIFO buffer
 
// EP4 OUT setup ---------------------------------------------------
OUTPKTEND = 0x84; SYNCDELAY; // arm all EP4 buffers
OUTPKTEND = 0x84; SYNCDELAY;
// !! hardware only arms endpoint when AUTOOUT 0->1 transition seen
// !! --> clean AUTOOUT to handle for example back-to-back firmware loads
EP4FIFOCFG = 0x00; SYNCDELAY; // EP4: force AUTOOUT 0->1 transition
EP4FIFOCFG = 0x10; SYNCDELAY; // EP4: 0001 0000: AUTOOUT, BYTE
// setup programmable fifo threshold as 'almost empty' at 3 bytes to go
// --> keep active low logic for prgrammable flags
// --> set flag 1 when fill >= threshold (DECIS=1)
// --> almost empty thus at fill<4, effective threshold thus 3 !!
EP4FIFOPFH = 0x80; SYNCDELAY; // 0000 0000: DECIS=1, PFC8=0
EP4FIFOPFL = 0x04; SYNCDELAY; // PFC = 4 = 0 0000 0100
 
// EP6 IN setup ---------------------------------------------------
EP6FIFOCFG = 0x0C; SYNCDELAY; // EP6: 0000 1100: AUTOIN, ZEROLEN, BYTE
EP6AUTOINLENH = 0x02; SYNCDELAY; // 512 byte buffers
EP6AUTOINLENL = 0x00; SYNCDELAY;
 
// setup programmable fifo threshold as 'almost full' at 3 bytes to go
// --> keep active low logic for prgrammable flags
// --> set flag 1 when fill <= threshold (DECIS=0)
// --> use full buffer fill
// --> for dual buffered: (PKSTAT=0, PKTS=1) [in case 3 fifo's used]
// --> for quad buffered: (PKSTAT=0, PKTS=3) [in case 2 fifo's used]
// --> effective threshold thus 3 in both bases
#if defined(USE_3FIFO)
EP6FIFOPFH = 0x09; SYNCDELAY; // 0000 1001: DECIS=0, PK=0:1, PFC8=1
#else
EP6FIFOPFH = 0x19; SYNCDELAY; // 0001 1001: DECIS=0, PK=0:3, PFC8=1
#endif
EP6FIFOPFL = 0xfc; SYNCDELAY; // PFC = 508 = 1 1111 1100
 
#if defined(USE_3FIFO)
// EP8 IN setup ---------------------------------------------------
EP8FIFOCFG = 0x0C; SYNCDELAY; // EP8: 0000 1100: AUTOIN, ZEROLEN, BYTE
EP8AUTOINLENH = 0x02; SYNCDELAY; // 512 byte buffers
EP8AUTOINLENL = 0x00; SYNCDELAY;
// setup programmable fifo threshold as 'almost full' at 4 bytes to go
// like for EP6 above
EP8FIFOPFH = 0x41; SYNCDELAY; // 0100 0001: DECIS=0, PKSTAT=1, PFC8=1
EP8FIFOPFL = 0xfc; SYNCDELAY; // PFC = 508 = 1 1111 1100
 
#else
// EP8 setup
EP8FIFOCFG = 0x00; SYNCDELAY; // EP8 slave: 0, not used as slave
#endif
 
#else
// no FIFOs used for DATA transfer
// EP4,6,8 inactive
EP4CFG = 0x02; SYNCDELAY; // EP4: disabled
EP6CFG = 0x02; SYNCDELAY; // EP6: disabled
EP8CFG = 0x02; SYNCDELAY; // EP8: disabled
 
FIFORESET = 0x04; SYNCDELAY; // EP4 reset
FIFORESET = 0x06; SYNCDELAY; // EP6 reset
FIFORESET = 0x08; SYNCDELAY; // EP8 reset
FIFORESET = 0x00; SYNCDELAY; // Restore normal behaviour
 
EP4FIFOCFG = 0x00; SYNCDELAY; // EP4 slave: 0, not used as slave
EP6FIFOCFG = 0x00; SYNCDELAY; // EP6 slave: 0, not used as slave
EP8FIFOCFG = 0x00; SYNCDELAY; // EP8 slave: 0, not used as slave
 
REVCTL = 0; SYNCDELAY; // Reset FW access to FIFO buffer
#endif
 
// the EP2 endpoint does not come up armed. It is used with double buffering
// so write dummy byte counts twice.
SYNCDELAY; //
EP2BCL = 0x80; SYNCDELAY; // arm EP2OUT
EP2BCL = 0x80; SYNCDELAY; // arm EP2OUT
}
/tools/fx2/src/hardware.h
0,0 → 1,35
/* $Id: hardware.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* Hardware-dependent code for usb_jtag
*-----------------------------------------------------------------------------
* Copyright (C) 2007 Kolja Waschk, ixo.de
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#ifndef _HARDWARE_H
#define _HARDWARE_H 1
 
extern void ProgIO_Init(void);
extern void ProgIO_Poll(void);
extern void ProgIO_Enable(void);
extern void ProgIO_Disable(void);
extern void ProgIO_Deinit(void);
 
extern void ProgIO_Set_State(unsigned char d);
extern unsigned char ProgIO_Set_Get_State(unsigned char d);
extern void ProgIO_ShiftOut(unsigned char x);
extern unsigned char ProgIO_ShiftInOut(unsigned char x);
 
#endif /* _HARDWARE_H */
 
/tools/fx2/src/main.c
0,0 → 1,369
/* $Id: main.c 447 2011-12-31 19:41:32Z mueller $ */
/*
* Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
* Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17
*
* - original copyright and licence disclaimer --------------------------------
* - Code that turns a Cypress FX2 USB Controller into an USB JTAG adapter
* - Copyright (C) 2005..2007 Kolja Waschk, ixo.de
* - This code is part of usbjtag. usbjtag is free software;
*-----------------------------------------------------------------------------
*
* This program is free software; you may redistribute and/or modify it under
* the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 2, or at your option any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for complete details.
*
*-----------------------------------------------------------------------------
*
* EZ-USB FX2 controller main program
*
* Revision History:
*
* Date Rev Version Comment
* 2011-07-23 397 1.1 factor out usb_fifo_init() code
* 2011-07-17 394 1.0 Initial version (from ixo-jtag/usb_jtag Rev 204)
*
*-----------------------------------------------------------------------------
*/
 
#include "isr.h"
#include "timer.h"
#include "delay.h"
#include "fx2regs.h"
#include "fx2utils.h"
#include "usb_common.h"
#include "usb_descriptors.h"
#include "usb_requests.h"
 
#include "syncdelay.h"
 
#include "eeprom.h"
#include "hardware.h"
 
//-----------------------------------------------------------------------------
// Define USE_MOD256_OUTBUFFER:
// Saves about 256 bytes in code size, improves speed a little.
// A further optimization could be not to use an extra output buffer at
// all, but to write directly into EP1INBUF. Not implemented yet. When
// downloading large amounts of data _to_ the target, there is no output
// and thus the output buffer isn't used at all and doesn't slow down things.
 
#define USE_MOD256_OUTBUFFER 1
 
//-----------------------------------------------------------------------------
// Global data
 
typedef bit BOOL;
#define FALSE 0
#define TRUE 1
static BOOL Running;
static BOOL WriteOnly;
 
static BYTE ClockBytes;
static WORD Pending;
 
#ifdef USE_MOD256_OUTBUFFER
static BYTE FirstDataInOutBuffer;
static BYTE FirstFreeInOutBuffer;
#else
static WORD FirstDataInOutBuffer;
static WORD FirstFreeInOutBuffer;
#endif
 
#ifdef USE_MOD256_OUTBUFFER
/* Size of output buffer must be exactly 256 */
#define OUTBUFFER_LEN 0x100
/* Output buffer must begin at some address with lower 8 bits all zero */
xdata at 0xE000 BYTE OutBuffer[OUTBUFFER_LEN];
#else
#define OUTBUFFER_LEN 0x200
static xdata BYTE OutBuffer[OUTBUFFER_LEN];
#endif
 
//-----------------------------------------------------------------------------
 
void usb_jtag_init(void) // Called once at startup
{
WORD tmp;
 
Running = FALSE;
ClockBytes = 0;
Pending = 0;
WriteOnly = TRUE;
FirstDataInOutBuffer = 0;
FirstFreeInOutBuffer = 0;
 
ProgIO_Init();
 
ProgIO_Enable();
 
// Make Timer2 reload at 100 Hz to trigger Keepalive packets
 
tmp = 65536 - ( 48000000 / 12 / 100 );
RCAP2H = tmp >> 8;
RCAP2L = tmp & 0xFF;
CKCON = 0; // Default Clock
T2CON = 0x04; // Auto-reload mode using internal clock, no baud clock.
 
// Enable Autopointer
 
EXTACC = 1; // Enable
APTR1FZ = 1; // Don't freeze
APTR2FZ = 1; // Don't freeze
}
 
void OutputByte(BYTE d)
{
#ifdef USE_MOD256_OUTBUFFER
OutBuffer[FirstFreeInOutBuffer] = d;
FirstFreeInOutBuffer = ( FirstFreeInOutBuffer + 1 ) & 0xFF;
#else
OutBuffer[FirstFreeInOutBuffer++] = d;
if(FirstFreeInOutBuffer >= OUTBUFFER_LEN) FirstFreeInOutBuffer = 0;
#endif
Pending++;
}
 
//-----------------------------------------------------------------------------
// usb_jtag_activity does most of the work. It now happens to behave just like
// the combination of FT245BM and Altera-programmed EPM7064 CPLD in Altera's
// USB-Blaster. The CPLD knows two major modes: Bit banging mode and Byte
// shift mode. It starts in Bit banging mode. While bytes are received
// from the host on EP2OUT, each byte B of them is processed as follows:
//
// Please note: nCE, nCS, LED pins and DATAOUT actually aren't supported here.
// Support for these would be required for AS/PS mode and isn't too complicated,
// but I haven't had the time yet.
//
// Bit banging mode:
//
// 1. Remember bit 6 (0x40) in B as the "Read bit".
//
// 2. If bit 7 (0x40) is set, switch to Byte shift mode for the coming
// X bytes ( X := B & 0x3F ), and don't do anything else now.
//
// 3. Otherwise, set the JTAG signals as follows:
// TCK/DCLK high if bit 0 was set (0x01), otherwise low
// TMS/nCONFIG high if bit 1 was set (0x02), otherwise low
// nCE high if bit 2 was set (0x04), otherwise low
// nCS high if bit 3 was set (0x08), otherwise low
// TDI/ASDI/DATA0 high if bit 4 was set (0x10), otherwise low
// Output Enable/LED active if bit 5 was set (0x20), otherwise low
//
// 4. If "Read bit" (0x40) was set, record the state of TDO(CONF_DONE) and
// DATAOUT(nSTATUS) pins and put it as a byte ((DATAOUT<<1)|TDO) in the
// output FIFO _to_ the host (the code here reads TDO only and assumes
// DATAOUT=1)
//
// Byte shift mode:
//
// 1. Load shift register with byte from host
//
// 2. Do 8 times (i.e. for each bit of the byte; implemented in shift.a51)
// 2a) if nCS=1, set carry bit from TDO, else set carry bit from DATAOUT
// 2b) Rotate shift register through carry bit
// 2c) TDI := Carry bit
// 2d) Raise TCK, then lower TCK.
//
// 3. If "Read bit" was set when switching into byte shift mode,
// record the shift register content and put it into the FIFO
// _to_ the host.
//
// Some more (minor) things to consider to emulate the FT245BM:
//
// a) The FT245BM seems to transmit just packets of no more than 64 bytes
// (which perfectly matches the USB spec). Each packet starts with
// two non-data bytes (I use 0x31,0x60 here). A USB sniffer on Windows
// might show a number of packets to you as if it was a large transfer
// because of the way that Windows understands it: it _is_ a large
// transfer until terminated with an USB packet smaller than 64 byte.
//
// b) The Windows driver expects to get some data packets (with at least
// the two leading bytes 0x31,0x60) immediately after "resetting" the
// FT chip and then in regular intervals. Otherwise a blue screen may
// appear... In the code below, I make sure that every 10ms there is
// some packet.
//
// c) Vendor specific commands to configure the FT245 are mostly ignored
// in my code. Only those for reading the EEPROM are processed. See
// DR_GetStatus and DR_VendorCmd below for my implementation.
//
// All other TD_ and DR_ functions remain as provided with CY3681.
//
//-----------------------------------------------------------------------------
 
void usb_jtag_activity(void) // Called repeatedly while the device is idle
{
if(!Running) return;
 
ProgIO_Poll();
if(!(EP1INCS & bmEPBUSY)) {
if(Pending > 0) {
BYTE o, n;
 
AUTOPTRH2 = MSB( EP1INBUF );
AUTOPTRL2 = LSB( EP1INBUF );
XAUTODAT2 = 0x31;
XAUTODAT2 = 0x60;
if(Pending > 0x3E) { n = 0x3E; Pending -= n; }
else { n = Pending; Pending = 0; };
o = n;
 
#ifdef USE_MOD256_OUTBUFFER
APTR1H = MSB( OutBuffer );
APTR1L = FirstDataInOutBuffer;
while(n--) {
XAUTODAT2 = XAUTODAT1;
APTR1H = MSB( OutBuffer ); // Stay within 256-Byte-Buffer
}
FirstDataInOutBuffer = APTR1L;
#else
APTR1H = MSB( &(OutBuffer[FirstDataInOutBuffer]) );
APTR1L = LSB( &(OutBuffer[FirstDataInOutBuffer]) );
while(n--) {
XAUTODAT2 = XAUTODAT1;
 
if(++FirstDataInOutBuffer >= OUTBUFFER_LEN) {
FirstDataInOutBuffer = 0;
APTR1H = MSB( OutBuffer );
APTR1L = LSB( OutBuffer );
}
}
#endif
SYNCDELAY;
EP1INBC = 2 + o;
TF2 = 1; // Make sure there will be a short transfer soon
} else if(TF2) {
EP1INBUF[0] = 0x31;
EP1INBUF[1] = 0x60;
SYNCDELAY;
EP1INBC = 2;
TF2 = 0;
}
}
 
if(!(EP2468STAT & bmEP2EMPTY) && (Pending < OUTBUFFER_LEN-0x3F)) {
//BYTE i, n = EP2BCL; // bugfix by Sune Mai (Oct 2008,
// https://sourceforge.net/projects/urjtag/forums/forum/682993/topic/2312452)
WORD i, n = EP2BCL|EP2BCH<<8;
 
APTR1H = MSB( EP2FIFOBUF );
APTR1L = LSB( EP2FIFOBUF );
 
for(i=0;i<n;) {
if(ClockBytes > 0) {
//BYTE m; // bugfix by Sune Mai, see above
WORD m;
 
m = n-i;
if(ClockBytes < m) m = ClockBytes;
ClockBytes -= m;
i += m;
 
/* Shift out 8 bits from d */
if(WriteOnly) { /* Shift out 8 bits from d */
while(m--) ProgIO_ShiftOut(XAUTODAT1);
} else { /* Shift in 8 bits at the other end */
while(m--) OutputByte(ProgIO_ShiftInOut(XAUTODAT1));
}
} else {
BYTE d = XAUTODAT1;
WriteOnly = (d & bmBIT6) ? FALSE : TRUE;
 
if(d & bmBIT7) {
/* Prepare byte transfer, do nothing else yet */
 
ClockBytes = d & 0x3F;
} else {
if(WriteOnly)
ProgIO_Set_State(d);
else
OutputByte(ProgIO_Set_Get_State(d));
}
i++;
}
}
 
SYNCDELAY;
EP2BCL = 0x80; // Re-arm endpoint 2
};
}
 
//-----------------------------------------------------------------------------
// Handler for Vendor Requests (
//-----------------------------------------------------------------------------
 
unsigned char app_vendor_cmd(void)
{
// OUT requests. Pretend we handle them all...
 
if ((bRequestType & bmRT_DIR_MASK) == bmRT_DIR_OUT) {
if(bRequest == RQ_GET_STATUS) {
Running = 1;
}
return 1;
}
 
// IN requests.
 
if(bRequest == 0x90) {
BYTE addr = (wIndexL<<1) & 0x7F;
EP0BUF[0] = eeprom[addr];
EP0BUF[1] = eeprom[addr+1];
} else {
// dummy data
EP0BUF[0] = 0x36;
EP0BUF[1] = 0x83;
}
 
EP0BCH = 0;
EP0BCL = (wLengthL<2) ? wLengthL : 2; // Arm endpoint with # bytes to transfer
 
return 1;
}
 
//-----------------------------------------------------------------------------
 
static void main_loop(void)
{
while(1) {
if(usb_setup_packet_avail()) usb_handle_setup_packet();
usb_jtag_activity();
}
}
 
//-----------------------------------------------------------------------------
 
extern void usb_fifo_init(void);
 
void main(void)
{
EA = 0; // disable all interrupts
 
usb_jtag_init();
usb_fifo_init();
eeprom_init();
setup_autovectors ();
usb_install_handlers ();
 
 
EA = 1; // enable interrupts
 
fx2_renumerate(); // simulates disconnect / reconnect
 
main_loop();
}
 
 
 
 
/tools/fx2/src/lib/delay.c
0,0 → 1,75
/* -*- c++ -*- */
/* $Id: delay.c 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* Delay routines
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
/*
* Delay approximately 1 microsecond (including overhead in udelay).
*/
static void
udelay1 (void) _naked
{
_asm ; lcall that got us here took 4 bus cycles
ret ; 4 bus cycles
_endasm;
}
 
/*
* delay for approximately usecs microseconds
*/
void
udelay (unsigned char usecs)
{
do {
udelay1 ();
} while (--usecs != 0);
}
 
 
/*
* Delay approximately 1 millisecond.
* We're running at 48 MHz, so we need 48,000 clock cycles.
*
* Note however, that each bus cycle takes 4 clock cycles (not obvious,
* but explains the factor of 4 problem below).
*/
static void
mdelay1 (void) _naked
{
_asm
mov dptr,#(-1200 & 0xffff)
002$:
inc dptr ; 3 bus cycles
mov a, dpl ; 2 bus cycles
orl a, dph ; 2 bus cycles
jnz 002$ ; 3 bus cycles
 
ret
_endasm;
}
 
void
mdelay (unsigned int msecs)
{
do {
mdelay1 ();
} while (--msecs != 0);
}
 
/tools/fx2/src/lib/syncdelay.h
0,0 → 1,65
/* -*- c++ -*- */
/* $Id: syncdelay.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* Synchronization delay for FX2 access to specific registers
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#ifndef _SYNCDELAY_H_
#define _SYNCDELAY_H_
 
/*
* Magic delay required between access to certain xdata registers (TRM page 15-106).
* For our configuration, 48 MHz FX2 / 48 MHz IFCLK, we need three cycles. Each
* NOP is a single cycle....
*
* From TRM page 15-105:
*
* Under certain conditions, some read and write access to the FX2 registers must
* be separated by a "synchronization delay". The delay is necessary only under the
* following conditions:
*
* - between a write to any register in the 0xE600 - 0xE6FF range and a write to one
* of the registers listed below.
*
* - between a write to one of the registers listed below and a read from any register
* in the 0xE600 - 0xE6FF range.
*
* Registers which require a synchronization delay:
*
* FIFORESET FIFOPINPOLAR
* INPKTEND EPxBCH:L
* EPxFIFOPFH:L EPxAUTOINLENH:L
* EPxFIFOCFG EPxGPIFFLGSEL
* PINFLAGSAB PINFLAGSCD
* EPxFIFOIE EPxFIFOIRQ
* GPIFIE GPIFIRQ
* UDMACRCH:L GPIFADRH:L
* GPIFTRIG EPxGPIFTRIG
* OUTPKTEND REVCTL
* GPIFTCB3 GPIFTCB2
* GPIFTCB1 GPIFTCB0
*/
 
/*
* FIXME ensure that the peep hole optimizer isn't screwing us
*/
#define SYNCDELAY _asm nop; nop; nop; _endasm
#define NOP _asm nop; _endasm
 
 
#endif /* _SYNCDELAY_H_ */
/tools/fx2/src/lib/usb_common.c
0,0 → 1,372
/* -*- c++ -*- */
/* $Id: usb_common.c 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* Common USB code for FX2
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#include "usb_common.h"
#include "fx2regs.h"
#include "syncdelay.h"
#include "fx2utils.h"
#include "isr.h"
#include "usb_descriptors.h"
#include "usb_requests.h"
 
extern xdata char str0[];
extern xdata char str1[];
extern xdata char str2[];
extern xdata char str3[];
extern xdata char str4[];
extern xdata char str5[];
 
volatile bit _usb_got_SUDAV;
 
unsigned char _usb_config = 0;
unsigned char _usb_alt_setting = 0; // FIXME really 1/interface
 
xdata unsigned char *current_device_descr;
xdata unsigned char *current_devqual_descr;
xdata unsigned char *current_config_descr;
xdata unsigned char *other_config_descr;
 
static void
setup_descriptors (void)
{
if (USBCS & bmHSM){ // high speed mode
current_device_descr = high_speed_device_descr;
current_devqual_descr = high_speed_devqual_descr;
current_config_descr = high_speed_config_descr;
other_config_descr = full_speed_config_descr;
}
else {
current_device_descr = full_speed_device_descr;
current_devqual_descr = full_speed_devqual_descr;
current_config_descr = full_speed_config_descr;
other_config_descr = high_speed_config_descr;
}
 
// whack the type fields
// FIXME, may not be required.
// current_config_descr[1] = DT_CONFIG;
// other_config_descr[1] = DT_OTHER_SPEED;
}
 
static void
isr_SUDAV (void) interrupt
{
clear_usb_irq ();
_usb_got_SUDAV = 1;
}
 
static void
isr_USBRESET (void) interrupt
{
clear_usb_irq ();
setup_descriptors ();
}
 
static void
isr_HIGHSPEED (void) interrupt
{
clear_usb_irq ();
setup_descriptors ();
}
 
void
usb_install_handlers (void)
{
setup_descriptors (); // ensure that they're set before use
 
hook_uv (UV_SUDAV, (unsigned short) isr_SUDAV);
hook_uv (UV_USBRESET, (unsigned short) isr_USBRESET);
hook_uv (UV_HIGHSPEED, (unsigned short) isr_HIGHSPEED);
 
USBIE = bmSUDAV | bmURES | bmHSGRANT;
}
 
// On the FX2 the only plausible endpoints are 0, 1, 2, 4, 6, 8
// This doesn't check to see that they're enabled
 
unsigned char
plausible_endpoint (unsigned char ep)
{
ep &= ~0x80; // ignore direction bit
 
if (ep > 8)
return 0;
 
if (ep == 1)
return 1;
 
return (ep & 0x1) == 0; // must be even
}
 
// return pointer to control and status register for endpoint.
// only called with plausible_endpoints
 
xdata volatile unsigned char *
epcs (unsigned char ep)
{
if (ep == 0x01) // ep1 has different in and out CS regs
return EP1OUTCS;
 
if (ep == 0x81)
return EP1INCS;
 
ep &= ~0x80; // ignore direction bit
 
if (ep == 0x00) // ep0
return EP0CS;
 
return EP2CS + (ep >> 1); // 2, 4, 6, 8 are consecutive
}
 
void
usb_handle_setup_packet (void)
{
_usb_got_SUDAV = 0;
 
// handle the standard requests...
 
switch (bRequestType & bmRT_TYPE_MASK){
 
case bmRT_TYPE_CLASS:
case bmRT_TYPE_RESERVED:
fx2_stall_ep0 (); // we don't handle these. indicate error
break;
case bmRT_TYPE_VENDOR:
// call the application code.
// If it handles the command it returns non-zero
 
if (!app_vendor_cmd ())
fx2_stall_ep0 ();
break;
 
case bmRT_TYPE_STD:
// these are the standard requests...
 
if ((bRequestType & bmRT_DIR_MASK) == bmRT_DIR_IN){
 
////////////////////////////////////
// handle the IN requests
////////////////////////////////////
 
switch (bRequest){
 
case RQ_GET_CONFIG:
EP0BUF[0] = _usb_config; // FIXME app should handle
EP0BCH = 0;
EP0BCL = 1;
break;
// --------------------------------
 
case RQ_GET_INTERFACE:
EP0BUF[0] = _usb_alt_setting; // FIXME app should handle
EP0BCH = 0;
EP0BCL = 1;
break;
 
// --------------------------------
 
case RQ_GET_DESCR:
switch (wValueH){
 
case DT_DEVICE:
SUDPTRH = MSB (current_device_descr);
SUDPTRL = LSB (current_device_descr);
break;
case DT_DEVQUAL:
SUDPTRH = MSB (current_devqual_descr);
SUDPTRL = LSB (current_devqual_descr);
break;
 
case DT_CONFIG:
if (0 && wValueL != 1) // FIXME only a single configuration
fx2_stall_ep0 ();
else {
SUDPTRH = MSB (current_config_descr);
SUDPTRL = LSB (current_config_descr);
}
break;
 
case DT_OTHER_SPEED:
if (0 && wValueL != 1) // FIXME only a single configuration
fx2_stall_ep0 ();
else {
SUDPTRH = MSB (other_config_descr);
SUDPTRL = LSB (other_config_descr);
}
break;
 
case DT_STRING:
if (wValueL >= nstring_descriptors)
fx2_stall_ep0 ();
else {
xdata char *p = string_descriptors[wValueL];
SUDPTRH = MSB (p);
SUDPTRL = LSB (p);
}
break;
 
default:
fx2_stall_ep0 (); // invalid request
break;
}
break;
// --------------------------------
 
case RQ_GET_STATUS:
switch (bRequestType & bmRT_RECIP_MASK){
case bmRT_RECIP_DEVICE:
EP0BUF[0] = 0;
EP0BUF[1] = 0;
EP0BCH = 0;
EP0BCL = 2;
break;
 
case bmRT_RECIP_INTERFACE:
EP0BUF[0] = 0;
EP0BUF[1] = 0;
EP0BCH = 0;
EP0BCL = 2;
break;
 
case bmRT_RECIP_ENDPOINT:
if (plausible_endpoint (wIndexL)){
EP0BUF[0] = *epcs (wIndexL) & bmEPSTALL;
EP0BUF[1] = 0;
EP0BCH = 0;
EP0BCL = 2;
}
else
fx2_stall_ep0 ();
break;
 
default:
fx2_stall_ep0 ();
break;
}
break;
 
// --------------------------------
 
case RQ_SYNCH_FRAME: // not implemented
default:
fx2_stall_ep0 ();
break;
}
}
 
else {
 
////////////////////////////////////
// handle the OUT requests
////////////////////////////////////
 
switch (bRequest){
 
case RQ_SET_CONFIG:
_usb_config = wValueL; // FIXME app should handle
break;
 
case RQ_SET_INTERFACE:
_usb_alt_setting = wValueL; // FIXME app should handle
break;
 
// --------------------------------
 
case RQ_CLEAR_FEATURE:
switch (bRequestType & bmRT_RECIP_MASK){
 
case bmRT_RECIP_DEVICE:
switch (wValueL){
case FS_DEV_REMOTE_WAKEUP:
default:
fx2_stall_ep0 ();
}
break;
 
case bmRT_RECIP_ENDPOINT:
if (wValueL == FS_ENDPOINT_HALT && plausible_endpoint (wIndexL)){
*epcs (wIndexL) &= ~bmEPSTALL;
fx2_reset_data_toggle (wIndexL);
}
else
fx2_stall_ep0 ();
break;
 
default:
fx2_stall_ep0 ();
break;
}
break;
 
// --------------------------------
 
case RQ_SET_FEATURE:
switch (bRequestType & bmRT_RECIP_MASK){
 
case bmRT_RECIP_DEVICE:
switch (wValueL){
case FS_TEST_MODE:
// hardware handles this after we complete SETUP phase handshake
break;
 
case FS_DEV_REMOTE_WAKEUP:
default:
fx2_stall_ep0 ();
break;
}
}
break;
 
case bmRT_RECIP_ENDPOINT:
switch (wValueL){
case FS_ENDPOINT_HALT:
if (plausible_endpoint (wIndexL))
*epcs (wIndexL) |= bmEPSTALL;
else
fx2_stall_ep0 ();
break;
 
default:
fx2_stall_ep0 ();
break;
}
break;
 
// --------------------------------
 
case RQ_SET_ADDRESS: // handled by fx2 hardware
case RQ_SET_DESCR: // not implemented
default:
fx2_stall_ep0 ();
}
 
}
break;
 
} // bmRT_TYPE_MASK
 
// ack handshake phase of device request
EP0CS |= bmHSNAK;
}
/tools/fx2/src/lib/isr.h
0,0 → 1,171
/* -*- c++ -*- */
/* $Id: isr.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* Interrupt handling for FX2
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#ifndef _ISR_H_
#define _ISR_H_
 
/*
* ----------------------------------------------------------------
* routines for managing interrupt services routines
* ----------------------------------------------------------------
*/
 
/*
* The FX2 has three discrete sets of interrupt vectors.
* The first set is the standard 8051 vector (13 8-byte entries).
* The second set is USB interrupt autovector (32 4-byte entries).
* The third set is the FIFO/GPIF autovector (14 4-byte entries).
*
* Since all the code we're running in the FX2 is ram based, we
* forego the typical "initialize the interrupt vectors at link time"
* strategy, in favor of calls at run time that install the correct
* pointers to functions.
*/
 
/*
* Standard Vector numbers
*/
 
#define SV_INT_0 0x03
#define SV_TIMER_0 0x0b
#define SV_INT_1 0x13
#define SV_TIMER_1 0x1b
#define SV_SERIAL_0 0x23
#define SV_TIMER_2 0x2b
#define SV_RESUME 0x33
#define SV_SERIAL_1 0x3b
#define SV_INT_2 0x43 // (INT_2) points at USB autovector
#define SV_I2C 0x4b
#define SV_INT_4 0x53 // (INT_4) points at FIFO/GPIF autovector
#define SV_INT_5 0x5b
#define SV_INT_6 0x63
 
#define SV_MIN SV_INT_0
#define SV_MAX SV_INT_6
 
/*
* USB Auto Vector numbers
*/
 
#define UV_SUDAV 0x00
#define UV_SOF 0x04
#define UV_SUTOK 0x08
#define UV_SUSPEND 0x0c
#define UV_USBRESET 0x10
#define UV_HIGHSPEED 0x14
#define UV_EP0ACK 0x18
#define UV_SPARE_1C 0x1c
#define UV_EP0IN 0x20
#define UV_EP0OUT 0x24
#define UV_EP1IN 0x28
#define UV_EP1OUT 0x2c
#define UV_EP2 0x30
#define UV_EP4 0x34
#define UV_EP6 0x38
#define UV_EP8 0x3c
#define UV_IBN 0x40
#define UV_SPARE_44 0x44
#define UV_EP0PINGNAK 0x48
#define UV_EP1PINGNAK 0x4c
#define UV_EP2PINGNAK 0x50
#define UV_EP4PINGNAK 0x54
#define UV_EP6PINGNAK 0x58
#define UV_EP8PINGNAK 0x5c
#define UV_ERRLIMIT 0x60
#define UV_SPARE_64 0x64
#define UV_SPARE_68 0x68
#define UV_SPARE_6C 0x6c
#define UV_EP2ISOERR 0x70
#define UV_EP4ISOERR 0x74
#define UV_EP6ISOERR 0x78
#define UV_EP8ISOERR 0x7c
 
#define UV_MIN UV_SUDAV
#define UV_MAX UV_EP8ISOERR
 
/*
* FIFO/GPIF Auto Vector numbers
*/
 
#define FGV_EP2PF 0x80
#define FGV_EP4PF 0x84
#define FGV_EP6PF 0x88
#define FGV_EP8PF 0x8c
#define FGV_EP2EF 0x90
#define FGV_EP4EF 0x94
#define FGV_EP6EF 0x98
#define FGV_EP8EF 0x9c
#define FGV_EP2FF 0xa0
#define FGV_EP4FF 0xa4
#define FGV_EP6FF 0xa8
#define FGV_EP8FF 0xac
#define FGV_GPIFDONE 0xb0
#define FGV_GPIFWF 0xb4
 
#define FGV_MIN FGV_EP2PF
#define FGV_MAX FGV_GPIFWF
 
 
/*
* Hook standard interrupt vector.
*
* vector_number is from the SV_<foo> list above.
* addr is the address of the interrupt service routine.
*/
void hook_sv (unsigned char vector_number, unsigned short addr);
 
/*
* Hook usb interrupt vector.
*
* vector_number is from the UV_<foo> list above.
* addr is the address of the interrupt service routine.
*/
void hook_uv (unsigned char vector_number, unsigned short addr);
 
/*
* Hook fifo/gpif interrupt vector.
*
* vector_number is from the FGV_<foo> list above.
* addr is the address of the interrupt service routine.
*/
void hook_fgv (unsigned char vector_number, unsigned short addr);
 
/*
* One time call to enable autovectoring for both USB and FIFO/GPIF
*/
void setup_autovectors (void);
 
 
/*
* Must be called in each usb interrupt handler
*/
#define clear_usb_irq() \
EXIF &= ~bmEXIF_USBINT; \
INT2CLR = 0
 
/*
* Must be calledin each fifo/gpif interrupt handler
*/
#define clear_fifo_gpif_irq() \
EXIF &= ~bmEXIF_IE4; \
INT4CLR = 0
 
#endif /* _ISR_H_ */
/tools/fx2/src/lib/delay.h
0,0 → 1,37
/* -*- c++ -*- */
/* $Id: delay.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* Delay routines
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#ifndef _DELAY_H_
#define _DELAY_H_
 
/*
* delay for approximately usecs microseconds
* Note limit of 255 usecs.
*/
void udelay (unsigned char usecs);
 
/*
* delay for approximately msecs milliseconds
*/
void mdelay (unsigned short msecs);
 
 
#endif /* _DELAY_H_ */
/tools/fx2/src/lib/usb_common.h
0,0 → 1,51
/* -*- c++ -*- */
/* $Id: usb_common.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* Common USB code for FX2
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#ifndef _USB_COMMON_H_
#define _USB_COMMON_H_
 
#define bRequestType SETUPDAT[0]
#define bRequest SETUPDAT[1]
#define wValueL SETUPDAT[2]
#define wValueH SETUPDAT[3]
#define wIndexL SETUPDAT[4]
#define wIndexH SETUPDAT[5]
#define wLengthL SETUPDAT[6]
#define wLengthH SETUPDAT[7]
 
#define MSB(x) (((unsigned short) x) >> 8)
#define LSB(x) (((unsigned short) x) & 0xff)
 
extern volatile bit _usb_got_SUDAV;
 
// Provided by user application to report device status.
// returns non-zero if it handled the command.
unsigned char app_get_status (void);
// Provided by user application to handle VENDOR commands.
// returns non-zero if it handled the command.
unsigned char app_vendor_cmd (void);
 
void usb_install_handlers (void);
void usb_handle_setup_packet (void);
 
#define usb_setup_packet_avail() _usb_got_SUDAV
 
#endif /* _USB_COMMON_H_ */
/tools/fx2/src/lib/i2c.c
0,0 → 1,122
/* -*- c++ -*- */
/* $Id: i2c.c 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* I2C read/write functions for FX2
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#include "i2c.h"
#include "fx2regs.h"
#include <string.h>
 
 
// issue a stop bus cycle and wait for completion
 
 
// returns non-zero if successful, else 0
unsigned char
i2c_read (unsigned char addr, xdata unsigned char *buf, unsigned char len)
{
volatile unsigned char junk;
if (len == 0) // reading zero bytes always works
return 1;
while (I2CS & bmSTOP) // wait for stop to clear
;
 
I2CS = bmSTART;
I2DAT = (addr << 1) | 1; // write address and direction (1's the read bit)
 
while ((I2CS & bmDONE) == 0)
;
 
if ((I2CS & bmBERR) || (I2CS & bmACK) == 0) // no device answered...
goto fail;
 
if (len == 1)
I2CS |= bmLASTRD;
 
junk = I2DAT; // trigger the first read cycle
 
while (--len != 0){
while ((I2CS & bmDONE) == 0)
;
 
if (I2CS & bmBERR)
goto fail;
 
if (len == 1)
I2CS |= bmLASTRD;
*buf++ = I2DAT; // get data, trigger another read
}
 
// wait for final byte
while ((I2CS & bmDONE) == 0)
;
if (I2CS & bmBERR)
goto fail;
 
I2CS |= bmSTOP;
*buf = I2DAT;
 
return 1;
 
fail:
I2CS |= bmSTOP;
return 0;
}
 
 
 
// returns non-zero if successful, else 0
unsigned char
i2c_write (unsigned char addr, xdata const unsigned char *buf, unsigned char len)
{
while (I2CS & bmSTOP) // wait for stop to clear
;
 
I2CS = bmSTART;
I2DAT = (addr << 1) | 0; // write address and direction (0's the write bit)
 
while ((I2CS & bmDONE) == 0)
;
 
if ((I2CS & bmBERR) || (I2CS & bmACK) == 0) // no device answered...
goto fail;
 
while (len > 0){
I2DAT = *buf++;
len--;
 
while ((I2CS & bmDONE) == 0)
;
 
if ((I2CS & bmBERR) || (I2CS & bmACK) == 0) // no device answered...
goto fail;
}
 
I2CS |= bmSTOP;
return 1;
 
fail:
I2CS |= bmSTOP;
return 0;
}
/tools/fx2/src/lib/usb_descriptors.h
0,0 → 1,39
/* -*- c++ -*- */
/* $Id: usb_descriptors.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* USB descriptor references
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
extern xdata const char high_speed_device_descr[];
extern xdata const char high_speed_devqual_descr[];
extern xdata const char high_speed_config_descr[];
 
extern xdata const char full_speed_device_descr[];
extern xdata const char full_speed_devqual_descr[];
extern xdata const char full_speed_config_descr[];
 
extern xdata unsigned char nstring_descriptors;
extern xdata char * xdata string_descriptors[];
 
/*
* We patch these locations with info read from the usrp config eeprom
*/
extern xdata char usb_desc_hw_rev_binary_patch_location_0[];
extern xdata char usb_desc_hw_rev_binary_patch_location_1[];
extern xdata char usb_desc_hw_rev_ascii_patch_location_0[];
extern xdata char usb_desc_serial_number_ascii[];
/tools/fx2/src/lib/timer.c
0,0 → 1,48
/* -*- c++ -*- */
/* $Id: timer.c 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* Timer handling for FX2
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#include "timer.h"
#include "fx2regs.h"
#include "isr.h"
 
/*
* Arrange to have isr_tick_handler called at 100 Hz.
*
* The cpu clock is running at 48e6. The input to the timer
* is 48e6 / 12 = 4e6.
*
* We arrange to have the timer overflow every 40000 clocks == 100 Hz
*/
 
#define RELOAD_VALUE ((unsigned short) -40000)
 
void
hook_timer_tick (unsigned short isr_tick_handler)
{
ET2 = 0; // disable timer 2 interrupts
hook_sv (SV_TIMER_2, isr_tick_handler);
RCAP2H = RELOAD_VALUE >> 8; // setup the auto reload value
RCAP2L = RELOAD_VALUE & 0xFF;
 
T2CON = 0x04; // interrupt on overflow; reload; run
ET2 = 1; // enable timer 2 interrupts
}
/tools/fx2/src/lib/fx2utils.c
0,0 → 1,53
/* -*- c++ -*- */
/* $Id: fx2utils.c 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* FX2 specific subroutines
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#include "fx2utils.h"
#include "fx2regs.h"
#include "delay.h"
 
void
fx2_stall_ep0 (void)
{
EP0CS |= bmEPSTALL;
}
 
void
fx2_reset_data_toggle (unsigned char ep)
{
TOGCTL = ((ep & 0x80) >> 3 | (ep & 0x0f));
TOGCTL |= bmRESETTOGGLE;
}
 
void
fx2_renumerate (void)
{
USBCS |= bmDISCON | bmRENUM;
 
// mdelay (1500); // FIXME why 1.5 seconds?
mdelay (250); // FIXME why 1.5 seconds?
USBIRQ = 0xff; // clear any pending USB irqs...
EPIRQ = 0xff; // they're from before the renumeration
 
EXIF &= ~bmEXIF_USBINT;
 
USBCS &= ~bmDISCON; // reconnect USB
}
/tools/fx2/src/lib/i2c.h
0,0 → 1,31
/* -*- c++ -*- */
/* $Id: i2c.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* I2C read/write functions for FX2
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#ifndef _I2C_H_
#define _I2C_H_
 
// returns non-zero if successful, else 0
unsigned char i2c_read (unsigned char addr, xdata unsigned char *buf, unsigned char len);
 
// returns non-zero if successful, else 0
unsigned char i2c_write (unsigned char addr, xdata const unsigned char *buf, unsigned char len);
 
#endif /* _I2C_H_ */
/tools/fx2/src/lib/fx2regs.h
0,0 → 1,715
/* -*- c++ -*- */
/* $Id: fx2regs.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* FX2 register definitions
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
/*
//-----------------------------------------------------------------------------
// File: FX2regs.h
// Contents: EZ-USB FX2 register declarations and bit mask definitions.
//
// $Archive: /USB/Target/Inc/fx2regs.h $
// $Date: 2006-09-13 14:30:04 -0700 (Wed, 13 Sep 2006) $
// $Revision: 3534 $
//
//
// Copyright (c) 2000 Cypress Semiconductor, All rights reserved
//-----------------------------------------------------------------------------
*/
 
 
#ifndef FX2REGS_H /* Header Sentry */
#define FX2REGS_H
 
#define ALLOCATE_EXTERN // required for "right thing to happen" with fx2regs.h
 
/*
//-----------------------------------------------------------------------------
// FX2 Related Register Assignments
//-----------------------------------------------------------------------------
 
// The Ez-USB FX2 registers are defined here. We use FX2regs.h for register
// address allocation by using "#define ALLOCATE_EXTERN".
// When using "#define ALLOCATE_EXTERN", you get (for instance):
// xdata volatile BYTE OUT7BUF[64] _at_ 0x7B40;
// Such lines are created from FX2.h by using the preprocessor.
// Incidently, these lines will not generate any space in the resulting hex
// file; they just bind the symbols to the addresses for compilation.
// You just need to put "#define ALLOCATE_EXTERN" in your main program file;
// i.e. fw.c or a stand-alone C source file.
// Without "#define ALLOCATE_EXTERN", you just get the external reference:
// extern xdata volatile BYTE OUT7BUF[64] ;// 0x7B40;
// This uses the concatenation operator "##" to insert a comment "//"
// to cut off the end of the line, "_at_ 0x7B40;", which is not wanted.
*/
 
 
#ifdef ALLOCATE_EXTERN
#define EXTERN
#define _AT_(a) at a
#else
#define EXTERN extern
#define _AT_ ;/ ## /
#endif
 
typedef unsigned char BYTE;
typedef unsigned short WORD;
 
EXTERN xdata _AT_(0xE400) volatile BYTE GPIF_WAVE_DATA[128];
EXTERN xdata _AT_(0xE480) volatile BYTE RES_WAVEDATA_END ;
 
// General Configuration
 
EXTERN xdata _AT_(0xE600) volatile BYTE CPUCS ; // Control & Status
EXTERN xdata _AT_(0xE601) volatile BYTE IFCONFIG ; // Interface Configuration
EXTERN xdata _AT_(0xE602) volatile BYTE PINFLAGSAB ; // FIFO FLAGA and FLAGB Assignments
EXTERN xdata _AT_(0xE603) volatile BYTE PINFLAGSCD ; // FIFO FLAGC and FLAGD Assignments
EXTERN xdata _AT_(0xE604) volatile BYTE FIFORESET ; // Restore FIFOS to default state
EXTERN xdata _AT_(0xE605) volatile BYTE BREAKPT ; // Breakpoint
EXTERN xdata _AT_(0xE606) volatile BYTE BPADDRH ; // Breakpoint Address H
EXTERN xdata _AT_(0xE607) volatile BYTE BPADDRL ; // Breakpoint Address L
EXTERN xdata _AT_(0xE608) volatile BYTE UART230 ; // 230 Kbaud clock for T0,T1,T2
EXTERN xdata _AT_(0xE609) volatile BYTE FIFOPINPOLAR ; // FIFO polarities
EXTERN xdata _AT_(0xE60A) volatile BYTE REVID ; // Chip Revision
EXTERN xdata _AT_(0xE60B) volatile BYTE REVCTL ; // Chip Revision Control
 
// Endpoint Configuration
 
EXTERN xdata _AT_(0xE610) volatile BYTE EP1OUTCFG ; // Endpoint 1-OUT Configuration
EXTERN xdata _AT_(0xE611) volatile BYTE EP1INCFG ; // Endpoint 1-IN Configuration
EXTERN xdata _AT_(0xE612) volatile BYTE EP2CFG ; // Endpoint 2 Configuration
EXTERN xdata _AT_(0xE613) volatile BYTE EP4CFG ; // Endpoint 4 Configuration
EXTERN xdata _AT_(0xE614) volatile BYTE EP6CFG ; // Endpoint 6 Configuration
EXTERN xdata _AT_(0xE615) volatile BYTE EP8CFG ; // Endpoint 8 Configuration
EXTERN xdata _AT_(0xE618) volatile BYTE EP2FIFOCFG ; // Endpoint 2 FIFO configuration
EXTERN xdata _AT_(0xE619) volatile BYTE EP4FIFOCFG ; // Endpoint 4 FIFO configuration
EXTERN xdata _AT_(0xE61A) volatile BYTE EP6FIFOCFG ; // Endpoint 6 FIFO configuration
EXTERN xdata _AT_(0xE61B) volatile BYTE EP8FIFOCFG ; // Endpoint 8 FIFO configuration
EXTERN xdata _AT_(0xE620) volatile BYTE EP2AUTOINLENH ; // Endpoint 2 Packet Length H (IN only)
EXTERN xdata _AT_(0xE621) volatile BYTE EP2AUTOINLENL ; // Endpoint 2 Packet Length L (IN only)
EXTERN xdata _AT_(0xE622) volatile BYTE EP4AUTOINLENH ; // Endpoint 4 Packet Length H (IN only)
EXTERN xdata _AT_(0xE623) volatile BYTE EP4AUTOINLENL ; // Endpoint 4 Packet Length L (IN only)
EXTERN xdata _AT_(0xE624) volatile BYTE EP6AUTOINLENH ; // Endpoint 6 Packet Length H (IN only)
EXTERN xdata _AT_(0xE625) volatile BYTE EP6AUTOINLENL ; // Endpoint 6 Packet Length L (IN only)
EXTERN xdata _AT_(0xE626) volatile BYTE EP8AUTOINLENH ; // Endpoint 8 Packet Length H (IN only)
EXTERN xdata _AT_(0xE627) volatile BYTE EP8AUTOINLENL ; // Endpoint 8 Packet Length L (IN only)
EXTERN xdata _AT_(0xE630) volatile BYTE EP2FIFOPFH ; // EP2 Programmable Flag trigger H
EXTERN xdata _AT_(0xE631) volatile BYTE EP2FIFOPFL ; // EP2 Programmable Flag trigger L
EXTERN xdata _AT_(0xE632) volatile BYTE EP4FIFOPFH ; // EP4 Programmable Flag trigger H
EXTERN xdata _AT_(0xE633) volatile BYTE EP4FIFOPFL ; // EP4 Programmable Flag trigger L
EXTERN xdata _AT_(0xE634) volatile BYTE EP6FIFOPFH ; // EP6 Programmable Flag trigger H
EXTERN xdata _AT_(0xE635) volatile BYTE EP6FIFOPFL ; // EP6 Programmable Flag trigger L
EXTERN xdata _AT_(0xE636) volatile BYTE EP8FIFOPFH ; // EP8 Programmable Flag trigger H
EXTERN xdata _AT_(0xE637) volatile BYTE EP8FIFOPFL ; // EP8 Programmable Flag trigger L
EXTERN xdata _AT_(0xE640) volatile BYTE EP2ISOINPKTS ; // EP2 (if ISO) IN Packets per frame (1-3)
EXTERN xdata _AT_(0xE641) volatile BYTE EP4ISOINPKTS ; // EP4 (if ISO) IN Packets per frame (1-3)
EXTERN xdata _AT_(0xE642) volatile BYTE EP6ISOINPKTS ; // EP6 (if ISO) IN Packets per frame (1-3)
EXTERN xdata _AT_(0xE643) volatile BYTE EP8ISOINPKTS ; // EP8 (if ISO) IN Packets per frame (1-3)
EXTERN xdata _AT_(0xE648) volatile BYTE INPKTEND ; // Force IN Packet End
EXTERN xdata _AT_(0xE649) volatile BYTE OUTPKTEND ; // Force OUT Packet End
 
// Interrupts
 
EXTERN xdata _AT_(0xE650) volatile BYTE EP2FIFOIE ; // Endpoint 2 Flag Interrupt Enable
EXTERN xdata _AT_(0xE651) volatile BYTE EP2FIFOIRQ ; // Endpoint 2 Flag Interrupt Request
EXTERN xdata _AT_(0xE652) volatile BYTE EP4FIFOIE ; // Endpoint 4 Flag Interrupt Enable
EXTERN xdata _AT_(0xE653) volatile BYTE EP4FIFOIRQ ; // Endpoint 4 Flag Interrupt Request
EXTERN xdata _AT_(0xE654) volatile BYTE EP6FIFOIE ; // Endpoint 6 Flag Interrupt Enable
EXTERN xdata _AT_(0xE655) volatile BYTE EP6FIFOIRQ ; // Endpoint 6 Flag Interrupt Request
EXTERN xdata _AT_(0xE656) volatile BYTE EP8FIFOIE ; // Endpoint 8 Flag Interrupt Enable
EXTERN xdata _AT_(0xE657) volatile BYTE EP8FIFOIRQ ; // Endpoint 8 Flag Interrupt Request
EXTERN xdata _AT_(0xE658) volatile BYTE IBNIE ; // IN-BULK-NAK Interrupt Enable
EXTERN xdata _AT_(0xE659) volatile BYTE IBNIRQ ; // IN-BULK-NAK interrupt Request
EXTERN xdata _AT_(0xE65A) volatile BYTE NAKIE ; // Endpoint Ping NAK interrupt Enable
EXTERN xdata _AT_(0xE65B) volatile BYTE NAKIRQ ; // Endpoint Ping NAK interrupt Request
EXTERN xdata _AT_(0xE65C) volatile BYTE USBIE ; // USB Int Enables
EXTERN xdata _AT_(0xE65D) volatile BYTE USBIRQ ; // USB Interrupt Requests
EXTERN xdata _AT_(0xE65E) volatile BYTE EPIE ; // Endpoint Interrupt Enables
EXTERN xdata _AT_(0xE65F) volatile BYTE EPIRQ ; // Endpoint Interrupt Requests
EXTERN xdata _AT_(0xE660) volatile BYTE GPIFIE ; // GPIF Interrupt Enable
EXTERN xdata _AT_(0xE661) volatile BYTE GPIFIRQ ; // GPIF Interrupt Request
EXTERN xdata _AT_(0xE662) volatile BYTE USBERRIE ; // USB Error Interrupt Enables
EXTERN xdata _AT_(0xE663) volatile BYTE USBERRIRQ ; // USB Error Interrupt Requests
EXTERN xdata _AT_(0xE664) volatile BYTE ERRCNTLIM ; // USB Error counter and limit
EXTERN xdata _AT_(0xE665) volatile BYTE CLRERRCNT ; // Clear Error Counter EC[3..0]
EXTERN xdata _AT_(0xE666) volatile BYTE INT2IVEC ; // Interupt 2 (USB) Autovector
EXTERN xdata _AT_(0xE667) volatile BYTE INT4IVEC ; // Interupt 4 (FIFOS & GPIF) Autovector
EXTERN xdata _AT_(0xE668) volatile BYTE INTSETUP ; // Interrupt 2&4 Setup
 
// Input/Output
 
EXTERN xdata _AT_(0xE670) volatile BYTE PORTACFG ; // I/O PORTA Alternate Configuration
EXTERN xdata _AT_(0xE671) volatile BYTE PORTCCFG ; // I/O PORTC Alternate Configuration
EXTERN xdata _AT_(0xE672) volatile BYTE PORTECFG ; // I/O PORTE Alternate Configuration
EXTERN xdata _AT_(0xE678) volatile BYTE I2CS ; // Control & Status
EXTERN xdata _AT_(0xE679) volatile BYTE I2DAT ; // Data
EXTERN xdata _AT_(0xE67A) volatile BYTE I2CTL ; // I2C Control
EXTERN xdata _AT_(0xE67B) volatile BYTE XAUTODAT1 ; // Autoptr1 MOVX access
EXTERN xdata _AT_(0xE67C) volatile BYTE XAUTODAT2 ; // Autoptr2 MOVX access
 
#define EXTAUTODAT1 XAUTODAT1
#define EXTAUTODAT2 XAUTODAT2
 
// USB Control
 
EXTERN xdata _AT_(0xE680) volatile BYTE USBCS ; // USB Control & Status
EXTERN xdata _AT_(0xE681) volatile BYTE SUSPEND ; // Put chip into suspend
EXTERN xdata _AT_(0xE682) volatile BYTE WAKEUPCS ; // Wakeup source and polarity
EXTERN xdata _AT_(0xE683) volatile BYTE TOGCTL ; // Toggle Control
EXTERN xdata _AT_(0xE684) volatile BYTE USBFRAMEH ; // USB Frame count H
EXTERN xdata _AT_(0xE685) volatile BYTE USBFRAMEL ; // USB Frame count L
EXTERN xdata _AT_(0xE686) volatile BYTE MICROFRAME ; // Microframe count, 0-7
EXTERN xdata _AT_(0xE687) volatile BYTE FNADDR ; // USB Function address
 
// Endpoints
 
EXTERN xdata _AT_(0xE68A) volatile BYTE EP0BCH ; // Endpoint 0 Byte Count H
EXTERN xdata _AT_(0xE68B) volatile BYTE EP0BCL ; // Endpoint 0 Byte Count L
EXTERN xdata _AT_(0xE68D) volatile BYTE EP1OUTBC ; // Endpoint 1 OUT Byte Count
EXTERN xdata _AT_(0xE68F) volatile BYTE EP1INBC ; // Endpoint 1 IN Byte Count
EXTERN xdata _AT_(0xE690) volatile BYTE EP2BCH ; // Endpoint 2 Byte Count H
EXTERN xdata _AT_(0xE691) volatile BYTE EP2BCL ; // Endpoint 2 Byte Count L
EXTERN xdata _AT_(0xE694) volatile BYTE EP4BCH ; // Endpoint 4 Byte Count H
EXTERN xdata _AT_(0xE695) volatile BYTE EP4BCL ; // Endpoint 4 Byte Count L
EXTERN xdata _AT_(0xE698) volatile BYTE EP6BCH ; // Endpoint 6 Byte Count H
EXTERN xdata _AT_(0xE699) volatile BYTE EP6BCL ; // Endpoint 6 Byte Count L
EXTERN xdata _AT_(0xE69C) volatile BYTE EP8BCH ; // Endpoint 8 Byte Count H
EXTERN xdata _AT_(0xE69D) volatile BYTE EP8BCL ; // Endpoint 8 Byte Count L
EXTERN xdata _AT_(0xE6A0) volatile BYTE EP0CS ; // Endpoint Control and Status
EXTERN xdata _AT_(0xE6A1) volatile BYTE EP1OUTCS ; // Endpoint 1 OUT Control and Status
EXTERN xdata _AT_(0xE6A2) volatile BYTE EP1INCS ; // Endpoint 1 IN Control and Status
EXTERN xdata _AT_(0xE6A3) volatile BYTE EP2CS ; // Endpoint 2 Control and Status
EXTERN xdata _AT_(0xE6A4) volatile BYTE EP4CS ; // Endpoint 4 Control and Status
EXTERN xdata _AT_(0xE6A5) volatile BYTE EP6CS ; // Endpoint 6 Control and Status
EXTERN xdata _AT_(0xE6A6) volatile BYTE EP8CS ; // Endpoint 8 Control and Status
EXTERN xdata _AT_(0xE6A7) volatile BYTE EP2FIFOFLGS ; // Endpoint 2 Flags
EXTERN xdata _AT_(0xE6A8) volatile BYTE EP4FIFOFLGS ; // Endpoint 4 Flags
EXTERN xdata _AT_(0xE6A9) volatile BYTE EP6FIFOFLGS ; // Endpoint 6 Flags
EXTERN xdata _AT_(0xE6AA) volatile BYTE EP8FIFOFLGS ; // Endpoint 8 Flags
EXTERN xdata _AT_(0xE6AB) volatile BYTE EP2FIFOBCH ; // EP2 FIFO total byte count H
EXTERN xdata _AT_(0xE6AC) volatile BYTE EP2FIFOBCL ; // EP2 FIFO total byte count L
EXTERN xdata _AT_(0xE6AD) volatile BYTE EP4FIFOBCH ; // EP4 FIFO total byte count H
EXTERN xdata _AT_(0xE6AE) volatile BYTE EP4FIFOBCL ; // EP4 FIFO total byte count L
EXTERN xdata _AT_(0xE6AF) volatile BYTE EP6FIFOBCH ; // EP6 FIFO total byte count H
EXTERN xdata _AT_(0xE6B0) volatile BYTE EP6FIFOBCL ; // EP6 FIFO total byte count L
EXTERN xdata _AT_(0xE6B1) volatile BYTE EP8FIFOBCH ; // EP8 FIFO total byte count H
EXTERN xdata _AT_(0xE6B2) volatile BYTE EP8FIFOBCL ; // EP8 FIFO total byte count L
EXTERN xdata _AT_(0xE6B3) volatile BYTE SUDPTRH ; // Setup Data Pointer high address byte
EXTERN xdata _AT_(0xE6B4) volatile BYTE SUDPTRL ; // Setup Data Pointer low address byte
EXTERN xdata _AT_(0xE6B5) volatile BYTE SUDPTRCTL ; // Setup Data Pointer Auto Mode
EXTERN xdata _AT_(0xE6B8) volatile BYTE SETUPDAT[8] ; // 8 bytes of SETUP data
 
// GPIF
 
EXTERN xdata _AT_(0xE6C0) volatile BYTE GPIFWFSELECT ; // Waveform Selector
EXTERN xdata _AT_(0xE6C1) volatile BYTE GPIFIDLECS ; // GPIF Done, GPIF IDLE drive mode
EXTERN xdata _AT_(0xE6C2) volatile BYTE GPIFIDLECTL ; // Inactive Bus, CTL states
EXTERN xdata _AT_(0xE6C3) volatile BYTE GPIFCTLCFG ; // CTL OUT pin drive
EXTERN xdata _AT_(0xE6C4) volatile BYTE GPIFADRH ; // GPIF Address H
EXTERN xdata _AT_(0xE6C5) volatile BYTE GPIFADRL ; // GPIF Address L
 
EXTERN xdata _AT_(0xE6CE) volatile BYTE GPIFTCB3 ; // GPIF Transaction Count Byte 3
EXTERN xdata _AT_(0xE6CF) volatile BYTE GPIFTCB2 ; // GPIF Transaction Count Byte 2
EXTERN xdata _AT_(0xE6D0) volatile BYTE GPIFTCB1 ; // GPIF Transaction Count Byte 1
EXTERN xdata _AT_(0xE6D1) volatile BYTE GPIFTCB0 ; // GPIF Transaction Count Byte 0
 
#define EP2GPIFTCH GPIFTCB1 // these are here for backwards compatibility
#define EP2GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
#define EP4GPIFTCH GPIFTCB1 // these are here for backwards compatibility
#define EP4GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
#define EP6GPIFTCH GPIFTCB1 // these are here for backwards compatibility
#define EP6GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
#define EP8GPIFTCH GPIFTCB1 // these are here for backwards compatibility
#define EP8GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
 
// EXTERN xdata volatile BYTE EP2GPIFTCH _AT_ 0xE6D0; // EP2 GPIF Transaction Count High
// EXTERN xdata volatile BYTE EP2GPIFTCL _AT_ 0xE6D1; // EP2 GPIF Transaction Count Low
EXTERN xdata _AT_(0xE6D2) volatile BYTE EP2GPIFFLGSEL ; // EP2 GPIF Flag select
EXTERN xdata _AT_(0xE6D3) volatile BYTE EP2GPIFPFSTOP ; // Stop GPIF EP2 transaction on prog. flag
EXTERN xdata _AT_(0xE6D4) volatile BYTE EP2GPIFTRIG ; // EP2 FIFO Trigger
// EXTERN xdata volatile BYTE EP4GPIFTCH _AT_ 0xE6D8; // EP4 GPIF Transaction Count High
// EXTERN xdata volatile BYTE EP4GPIFTCL _AT_ 0xE6D9; // EP4 GPIF Transactionr Count Low
EXTERN xdata _AT_(0xE6DA) volatile BYTE EP4GPIFFLGSEL ; // EP4 GPIF Flag select
EXTERN xdata _AT_(0xE6DB) volatile BYTE EP4GPIFPFSTOP ; // Stop GPIF EP4 transaction on prog. flag
EXTERN xdata _AT_(0xE6DC) volatile BYTE EP4GPIFTRIG ; // EP4 FIFO Trigger
// EXTERN xdata volatile BYTE EP6GPIFTCH _AT_ 0xE6E0; // EP6 GPIF Transaction Count High
// EXTERN xdata volatile BYTE EP6GPIFTCL _AT_ 0xE6E1; // EP6 GPIF Transaction Count Low
EXTERN xdata _AT_(0xE6E2) volatile BYTE EP6GPIFFLGSEL ; // EP6 GPIF Flag select
EXTERN xdata _AT_(0xE6E3) volatile BYTE EP6GPIFPFSTOP ; // Stop GPIF EP6 transaction on prog. flag
EXTERN xdata _AT_(0xE6E4) volatile BYTE EP6GPIFTRIG ; // EP6 FIFO Trigger
// EXTERN xdata volatile BYTE EP8GPIFTCH _AT_ 0xE6E8; // EP8 GPIF Transaction Count High
// EXTERN xdata volatile BYTE EP8GPIFTCL _AT_ 0xE6E9; // EP8GPIF Transaction Count Low
EXTERN xdata _AT_(0xE6EA) volatile BYTE EP8GPIFFLGSEL ; // EP8 GPIF Flag select
EXTERN xdata _AT_(0xE6EB) volatile BYTE EP8GPIFPFSTOP ; // Stop GPIF EP8 transaction on prog. flag
EXTERN xdata _AT_(0xE6EC) volatile BYTE EP8GPIFTRIG ; // EP8 FIFO Trigger
EXTERN xdata _AT_(0xE6F0) volatile BYTE XGPIFSGLDATH ; // GPIF Data H (16-bit mode only)
EXTERN xdata _AT_(0xE6F1) volatile BYTE XGPIFSGLDATLX ; // Read/Write GPIF Data L & trigger transac
EXTERN xdata _AT_(0xE6F2) volatile BYTE XGPIFSGLDATLNOX ; // Read GPIF Data L, no transac trigger
EXTERN xdata _AT_(0xE6F3) volatile BYTE GPIFREADYCFG ; // Internal RDY,Sync/Async, RDY5CFG
EXTERN xdata _AT_(0xE6F4) volatile BYTE GPIFREADYSTAT ; // RDY pin states
EXTERN xdata _AT_(0xE6F5) volatile BYTE GPIFABORT ; // Abort GPIF cycles
 
// UDMA
 
EXTERN xdata _AT_(0xE6C6) volatile BYTE FLOWSTATE ; //Defines GPIF flow state
EXTERN xdata _AT_(0xE6C7) volatile BYTE FLOWLOGIC ; //Defines flow/hold decision criteria
EXTERN xdata _AT_(0xE6C8) volatile BYTE FLOWEQ0CTL ; //CTL states during active flow state
EXTERN xdata _AT_(0xE6C9) volatile BYTE FLOWEQ1CTL ; //CTL states during hold flow state
EXTERN xdata _AT_(0xE6CA) volatile BYTE FLOWHOLDOFF ;
EXTERN xdata _AT_(0xE6CB) volatile BYTE FLOWSTB ; //CTL/RDY Signal to use as master data strobe
EXTERN xdata _AT_(0xE6CC) volatile BYTE FLOWSTBEDGE ; //Defines active master strobe edge
EXTERN xdata _AT_(0xE6CD) volatile BYTE FLOWSTBHPERIOD ; //Half Period of output master strobe
EXTERN xdata _AT_(0xE60C) volatile BYTE GPIFHOLDAMOUNT ; //Data delay shift
EXTERN xdata _AT_(0xE67D) volatile BYTE UDMACRCH ; //CRC Upper byte
EXTERN xdata _AT_(0xE67E) volatile BYTE UDMACRCL ; //CRC Lower byte
EXTERN xdata _AT_(0xE67F) volatile BYTE UDMACRCQUAL ; //UDMA In only, host terminated use only
 
 
// Debug/Test
 
EXTERN xdata _AT_(0xE6F8) volatile BYTE DBUG ; // Debug
EXTERN xdata _AT_(0xE6F9) volatile BYTE TESTCFG ; // Test configuration
EXTERN xdata _AT_(0xE6FA) volatile BYTE USBTEST ; // USB Test Modes
EXTERN xdata _AT_(0xE6FB) volatile BYTE CT1 ; // Chirp Test--Override
EXTERN xdata _AT_(0xE6FC) volatile BYTE CT2 ; // Chirp Test--FSM
EXTERN xdata _AT_(0xE6FD) volatile BYTE CT3 ; // Chirp Test--Control Signals
EXTERN xdata _AT_(0xE6FE) volatile BYTE CT4 ; // Chirp Test--Inputs
 
// Endpoint Buffers
 
EXTERN xdata _AT_(0xE740) volatile BYTE EP0BUF[64] ; // EP0 IN-OUT buffer
EXTERN xdata _AT_(0xE780) volatile BYTE EP1OUTBUF[64] ; // EP1-OUT buffer
EXTERN xdata _AT_(0xE7C0) volatile BYTE EP1INBUF[64] ; // EP1-IN buffer
EXTERN xdata _AT_(0xF000) volatile BYTE EP2FIFOBUF[1024] ; // 512/1024-byte EP2 buffer (IN or OUT)
EXTERN xdata _AT_(0xF400) volatile BYTE EP4FIFOBUF[1024] ; // 512 byte EP4 buffer (IN or OUT)
EXTERN xdata _AT_(0xF800) volatile BYTE EP6FIFOBUF[1024] ; // 512/1024-byte EP6 buffer (IN or OUT)
EXTERN xdata _AT_(0xFC00) volatile BYTE EP8FIFOBUF[1024] ; // 512 byte EP8 buffer (IN or OUT)
 
#undef EXTERN
#undef _AT_
 
/*-----------------------------------------------------------------------------
Special Function Registers (SFRs)
The byte registers and bits defined in the following list are based
on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
If you modify the register definitions below, please regenerate the file
"ezregs.inc" which includes the same basic information for assembly inclusion.
-----------------------------------------------------------------------------*/
 
sfr at 0x80 IOA;
sfr at 0x81 SP;
sfr at 0x82 DPL;
sfr at 0x83 DPH;
sfr at 0x84 DPL1;
sfr at 0x85 DPH1;
sfr at 0x86 DPS;
/* DPS */
sbit at 0x86+0 SEL;
sfr at 0x87 PCON; /* PCON */
//sbit IDLE = 0x87+0;
//sbit STOP = 0x87+1;
//sbit GF0 = 0x87+2;
//sbit GF1 = 0x87+3;
//sbit SMOD0 = 0x87+7;
sfr at 0x88 TCON;
/* TCON */
sbit at 0x88+0 IT0;
sbit at 0x88+1 IE0;
sbit at 0x88+2 IT1;
sbit at 0x88+3 IE1;
sbit at 0x88+4 TR0;
sbit at 0x88+5 TF0;
sbit at 0x88+6 TR1;
sbit at 0x88+7 TF1;
sfr at 0x89 TMOD;
/* TMOD */
//sbit M00 = 0x89+0;
//sbit M10 = 0x89+1;
//sbit CT0 = 0x89+2;
//sbit GATE0 = 0x89+3;
//sbit M01 = 0x89+4;
//sbit M11 = 0x89+5;
//sbit CT1 = 0x89+6;
//sbit GATE1 = 0x89+7;
sfr at 0x8A TL0;
sfr at 0x8B TL1;
sfr at 0x8C TH0;
sfr at 0x8D TH1;
sfr at 0x8E CKCON;
/* CKCON */
//sbit MD0 = 0x89+0;
//sbit MD1 = 0x89+1;
//sbit MD2 = 0x89+2;
//sbit T0M = 0x89+3;
//sbit T1M = 0x89+4;
//sbit T2M = 0x89+5;
// sfr at 0x8F SPC_FNC; // Was WRS in Reg320
/* CKCON */
//sbit WRS = 0x8F+0;
sfr at 0x90 IOB;
sfr at 0x91 EXIF; // EXIF Bit Values differ from Reg320
/* EXIF */
//sbit USBINT = 0x91+4;
//sbit I2CINT = 0x91+5;
//sbit IE4 = 0x91+6;
//sbit IE5 = 0x91+7;
sfr at 0x92 MPAGE;
sfr at 0x98 SCON0;
/* SCON0 */
sbit at 0x98+0 RI;
sbit at 0x98+1 TI;
sbit at 0x98+2 RB8;
sbit at 0x98+3 TB8;
sbit at 0x98+4 REN;
sbit at 0x98+5 SM2;
sbit at 0x98+6 SM1;
sbit at 0x98+7 SM0;
sfr at 0x99 SBUF0;
 
sfr at 0x9A APTR1H;
sfr at 0x9B APTR1L;
sfr at 0x9C AUTODAT1;
sfr at 0x9D AUTOPTRH2;
sfr at 0x9E AUTOPTRL2;
sfr at 0x9F AUTODAT2;
sfr at 0xA0 IOC;
sfr at 0xA1 INT2CLR;
sfr at 0xA2 INT4CLR;
 
#define AUTOPTRH1 APTR1H
#define AUTOPTRL1 APTR1L
 
sfr at 0xA8 IE;
/* IE */
sbit at 0xA8+0 EX0;
sbit at 0xA8+1 ET0;
sbit at 0xA8+2 EX1;
sbit at 0xA8+3 ET1;
sbit at 0xA8+4 ES0;
sbit at 0xA8+5 ET2;
sbit at 0xA8+6 ES1;
sbit at 0xA8+7 EA;
 
sfr at 0xAA EP2468STAT;
/* EP2468STAT */
//sbit EP2E = 0xAA+0;
//sbit EP2F = 0xAA+1;
//sbit EP4E = 0xAA+2;
//sbit EP4F = 0xAA+3;
//sbit EP6E = 0xAA+4;
//sbit EP6F = 0xAA+5;
//sbit EP8E = 0xAA+6;
//sbit EP8F = 0xAA+7;
 
sfr at 0xAB EP24FIFOFLGS;
sfr at 0xAC EP68FIFOFLGS;
sfr at 0xAF AUTOPTRSETUP;
/* AUTOPTRSETUP */
sbit at 0xAF+0 EXTACC;
sbit at 0xAF+1 APTR1FZ;
sbit at 0xAF+2 APTR2FZ;
 
sfr at 0xB0 IOD;
sfr at 0xB1 IOE;
sfr at 0xB2 OEA;
sfr at 0xB3 OEB;
sfr at 0xB4 OEC;
sfr at 0xB5 OED;
sfr at 0xB6 OEE;
 
sfr at 0xB8 IP;
/* IP */
sbit at 0xB8+0 PX0;
sbit at 0xB8+1 PT0;
sbit at 0xB8+2 PX1;
sbit at 0xB8+3 PT1;
sbit at 0xB8+4 PS0;
sbit at 0xB8+5 PT2;
sbit at 0xB8+6 PS1;
 
sfr at 0xBA EP01STAT;
sfr at 0xBB GPIFTRIG;
sfr at 0xBD GPIFSGLDATH;
sfr at 0xBE GPIFSGLDATLX;
sfr at 0xBF GPIFSGLDATLNOX;
 
sfr at 0xC0 SCON1;
/* SCON1 */
sbit at 0xC0+0 RI1;
sbit at 0xC0+1 TI1;
sbit at 0xC0+2 RB81;
sbit at 0xC0+3 TB81;
sbit at 0xC0+4 REN1;
sbit at 0xC0+5 SM21;
sbit at 0xC0+6 SM11;
sbit at 0xC0+7 SM01;
sfr at 0xC1 SBUF1;
sfr at 0xC8 T2CON;
/* T2CON */
sbit at 0xC8+0 CP_RL2;
sbit at 0xC8+1 C_T2;
sbit at 0xC8+2 TR2;
sbit at 0xC8+3 EXEN2;
sbit at 0xC8+4 TCLK;
sbit at 0xC8+5 RCLK;
sbit at 0xC8+6 EXF2;
sbit at 0xC8+7 TF2;
sfr at 0xCA RCAP2L;
sfr at 0xCB RCAP2H;
sfr at 0xCC TL2;
sfr at 0xCD TH2;
sfr at 0xD0 PSW;
/* PSW */
sbit at 0xD0+0 P;
sbit at 0xD0+1 FL;
sbit at 0xD0+2 OV;
sbit at 0xD0+3 RS0;
sbit at 0xD0+4 RS1;
sbit at 0xD0+5 F0;
sbit at 0xD0+6 AC;
sbit at 0xD0+7 CY;
sfr at 0xD8 EICON; // Was WDCON in DS80C320 EICON; Bit Values differ from Reg320
/* EICON */
sbit at 0xD8+3 INT6;
sbit at 0xD8+4 RESI;
sbit at 0xD8+5 ERESI;
sbit at 0xD8+7 SMOD1;
sfr at 0xE0 ACC;
sfr at 0xE8 EIE; // EIE Bit Values differ from Reg320
/* EIE */
sbit at 0xE8+0 EIUSB;
sbit at 0xE8+1 EI2C;
sbit at 0xE8+2 EIEX4;
sbit at 0xE8+3 EIEX5;
sbit at 0xE8+4 EIEX6;
sfr at 0xF0 B;
sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320
/* EIP */
sbit at 0xF8+0 PUSB;
sbit at 0xF8+1 PI2C;
sbit at 0xF8+2 EIPX4;
sbit at 0xF8+3 EIPX5;
sbit at 0xF8+4 EIPX6;
 
/*-----------------------------------------------------------------------------
Bit Masks
-----------------------------------------------------------------------------*/
 
#define bmBIT0 1
#define bmBIT1 2
#define bmBIT2 4
#define bmBIT3 8
#define bmBIT4 16
#define bmBIT5 32
#define bmBIT6 64
#define bmBIT7 128
 
/* CPU Control & Status Register (CPUCS) */
#define bmPRTCSTB bmBIT5
#define bmCLKSPD (bmBIT4 | bmBIT3)
#define bmCLKSPD1 bmBIT4
#define bmCLKSPD0 bmBIT3
#define bmCLKINV bmBIT2
#define bmCLKOE bmBIT1
#define bm8051RES bmBIT0
/* Port Alternate Configuration Registers */
/* Port A (PORTACFG) */
#define bmFLAGD bmBIT7
#define bmINT1 bmBIT1
#define bmINT0 bmBIT0
/* Port C (PORTCCFG) */
#define bmGPIFA7 bmBIT7
#define bmGPIFA6 bmBIT6
#define bmGPIFA5 bmBIT5
#define bmGPIFA4 bmBIT4
#define bmGPIFA3 bmBIT3
#define bmGPIFA2 bmBIT2
#define bmGPIFA1 bmBIT1
#define bmGPIFA0 bmBIT0
/* Port E (PORTECFG) */
#define bmGPIFA8 bmBIT7
#define bmT2EX bmBIT6
#define bmINT6 bmBIT5
#define bmRXD1OUT bmBIT4
#define bmRXD0OUT bmBIT3
#define bmT2OUT bmBIT2
#define bmT1OUT bmBIT1
#define bmT0OUT bmBIT0
 
/* I2C Control & Status Register (I2CS) */
#define bmSTART bmBIT7
#define bmSTOP bmBIT6
#define bmLASTRD bmBIT5
#define bmID (bmBIT4 | bmBIT3)
#define bmBERR bmBIT2
#define bmACK bmBIT1
#define bmDONE bmBIT0
/* I2C Control Register (I2CTL) */
#define bmSTOPIE bmBIT1
#define bm400KHZ bmBIT0
/* Interrupt 2 (USB) Autovector Register (INT2IVEC) */
#define bmIV4 bmBIT6
#define bmIV3 bmBIT5
#define bmIV2 bmBIT4
#define bmIV1 bmBIT3
#define bmIV0 bmBIT2
/* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */
#define bmEP0ACK bmBIT6
#define bmHSGRANT bmBIT5
#define bmURES bmBIT4
#define bmSUSP bmBIT3
#define bmSUTOK bmBIT2
#define bmSOF bmBIT1
#define bmSUDAV bmBIT0
/* Breakpoint register (BREAKPT) */
#define bmBREAK bmBIT3
#define bmBPPULSE bmBIT2
#define bmBPEN bmBIT1
/* Interrupt 2 & 4 Setup (INTSETUP) */
#define bmAV2EN bmBIT3
#define bmINT4IN bmBIT1
#define bmAV4EN bmBIT0
/* USB Control & Status Register (USBCS) */
#define bmHSM bmBIT7
#define bmDISCON bmBIT3
#define bmNOSYNSOF bmBIT2
#define bmRENUM bmBIT1
#define bmSIGRESUME bmBIT0
/* Wakeup Control and Status Register (WAKEUPCS) */
#define bmWU2 bmBIT7
#define bmWU bmBIT6
#define bmWU2POL bmBIT5
#define bmWUPOL bmBIT4
#define bmDPEN bmBIT2
#define bmWU2EN bmBIT1
#define bmWUEN bmBIT0
/* End Point 0 Control & Status Register (EP0CS) */
#define bmHSNAK bmBIT7
/* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */
#define bmEPBUSY bmBIT1
#define bmEPSTALL bmBIT0
/* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */
#define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4)
#define bmEPFULL bmBIT3
#define bmEPEMPTY bmBIT2
/* Endpoint Status (EP2468STAT) SFR bits */
#define bmEP8FULL bmBIT7
#define bmEP8EMPTY bmBIT6
#define bmEP6FULL bmBIT5
#define bmEP6EMPTY bmBIT4
#define bmEP4FULL bmBIT3
#define bmEP4EMPTY bmBIT2
#define bmEP2FULL bmBIT1
#define bmEP2EMPTY bmBIT0
/* SETUP Data Pointer Auto Mode (SUDPTRCTL) */
#define bmSDPAUTO bmBIT0
/* Endpoint Data Toggle Control (TOGCTL) */
#define bmQUERYTOGGLE bmBIT7
#define bmSETTOGGLE bmBIT6
#define bmRESETTOGGLE bmBIT5
#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
/* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */
#define bmEP8IBN bmBIT5
#define bmEP6IBN bmBIT4
#define bmEP4IBN bmBIT3
#define bmEP2IBN bmBIT2
#define bmEP1IBN bmBIT1
#define bmEP0IBN bmBIT0
 
/* PING-NAK enable and request bits (NAKIE/NAKIRQ) */
#define bmEP8PING bmBIT7
#define bmEP6PING bmBIT6
#define bmEP4PING bmBIT5
#define bmEP2PING bmBIT4
#define bmEP1PING bmBIT3
#define bmEP0PING bmBIT2
#define bmIBN bmBIT0
 
/* Interface Configuration bits (IFCONFIG) */
#define bmIFCLKSRC bmBIT7 // set == INTERNAL
#define bm3048MHZ bmBIT6 // set == 48 MHz
#define bmIFCLKOE bmBIT5
#define bmIFCLKPOL bmBIT4
#define bmASYNC bmBIT3
#define bmGSTATE bmBIT2
#define bmIFCFG1 bmBIT1
#define bmIFCFG0 bmBIT0
#define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1)
#define bmIFGPIF bmIFCFG1
 
/* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */
#define bmINFM bmBIT6
#define bmOEP bmBIT5
#define bmAUTOOUT bmBIT4
#define bmAUTOIN bmBIT3
#define bmZEROLENIN bmBIT2
// must be zero bmBIT1
#define bmWORDWIDE bmBIT0
 
/*
* Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specific features
*/
#define bmNOAUTOARM bmBIT1 // these don't match the docs
#define bmSKIPCOMMIT bmBIT0 // these don't match the docs
 
#define bmDYN_OUT bmBIT1 // these do...
#define bmENH_PKT bmBIT0
 
 
/* Fifo Reset bits (FIFORESET) */
#define bmNAKALL bmBIT7
 
/* Endpoint Configuration (EPxCFG) */
#define bmVALID bmBIT7
#define bmIN bmBIT6
#define bmTYPE1 bmBIT5
#define bmTYPE0 bmBIT4
#define bmISOCHRONOUS bmTYPE0
#define bmBULK bmTYPE1
#define bmINTERRUPT (bmTYPE1 | bmTYPE0)
#define bm1KBUF bmBIT3
#define bmBUF1 bmBIT1
#define bmBUF0 bmBIT0
#define bmQUADBUF 0
#define bmINVALIDBUF bmBUF0
#define bmDOUBLEBUF bmBUF1
#define bmTRIPLEBUF (bmBUF1 | bmBUF0)
 
/* OUTPKTEND */
#define bmSKIP bmBIT7 // low 4 bits specify which end point
 
/* GPIFTRIG defs */
#define bmGPIF_IDLE bmBIT7 // status bit
 
#define bmGPIF_EP2_START 0
#define bmGPIF_EP4_START 1
#define bmGPIF_EP6_START 2
#define bmGPIF_EP8_START 3
#define bmGPIF_READ bmBIT2
#define bmGPIF_WRITE 0
 
/* EXIF bits */
#define bmEXIF_USBINT bmBIT4
#define bmEXIF_I2CINT bmBIT5
#define bmEXIF_IE4 bmBIT6
#define bmEXIF_IE5 bmBIT7
 
 
#endif /* FX2REGS_H */
/tools/fx2/src/lib/timer.h
0,0 → 1,34
/* -*- c++ -*- */
/* $Id: timer.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* Timer handling for FX2
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#ifndef _TIMER_H_
#define _TIMER_H_
 
/*
* Arrange to have isr_tick_handler called at 100 Hz
*/
void hook_timer_tick (unsigned short isr_tick_handler);
 
#define clear_timer_irq() \
TF2 = 0 /* clear overflow flag */
 
 
#endif /* _TIMER_H_ */
/tools/fx2/src/lib/fx2utils.h
0,0 → 1,31
/* -*- c++ -*- */
/* $Id: fx2utils.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* FX2 specific subroutines
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#ifndef _FX2UTILS_H_
#define _FX2UTILS_H_
 
void fx2_stall_ep0 (void);
void fx2_reset_data_toggle (unsigned char ep);
void fx2_renumerate (void);
 
 
 
#endif /* _FX2UTILS_H_ */
/tools/fx2/src/lib/usb_requests.h
0,0 → 1,87
/* -*- c++ -*- */
/* $Id: usb_requests.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* USB request definitions
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
// Standard USB requests.
// These are contained in end point 0 setup packets
 
 
#ifndef _USB_REQUESTS_H_
#define _USB_REQUESTS_H_
 
// format of bmRequestType byte
 
#define bmRT_DIR_MASK (0x1 << 7)
#define bmRT_DIR_IN (1 << 7)
#define bmRT_DIR_OUT (0 << 7)
 
#define bmRT_TYPE_MASK (0x3 << 5)
#define bmRT_TYPE_STD (0 << 5)
#define bmRT_TYPE_CLASS (1 << 5)
#define bmRT_TYPE_VENDOR (2 << 5)
#define bmRT_TYPE_RESERVED (3 << 5)
 
#define bmRT_RECIP_MASK (0x1f << 0)
#define bmRT_RECIP_DEVICE (0 << 0)
#define bmRT_RECIP_INTERFACE (1 << 0)
#define bmRT_RECIP_ENDPOINT (2 << 0)
#define bmRT_RECIP_OTHER (3 << 0)
 
 
// standard request codes (bRequest)
 
#define RQ_GET_STATUS 0
#define RQ_CLEAR_FEATURE 1
#define RQ_RESERVED_2 2
#define RQ_SET_FEATURE 3
#define RQ_RESERVED_4 4
#define RQ_SET_ADDRESS 5
#define RQ_GET_DESCR 6
#define RQ_SET_DESCR 7
#define RQ_GET_CONFIG 8
#define RQ_SET_CONFIG 9
#define RQ_GET_INTERFACE 10
#define RQ_SET_INTERFACE 11
#define RQ_SYNCH_FRAME 12
 
// standard descriptor types
 
#define DT_DEVICE 1
#define DT_CONFIG 2
#define DT_STRING 3
#define DT_INTERFACE 4
#define DT_ENDPOINT 5
#define DT_DEVQUAL 6
#define DT_OTHER_SPEED 7
#define DT_INTERFACE_POWER 8
 
// standard feature selectors
 
#define FS_ENDPOINT_HALT 0 // recip: endpoint
#define FS_DEV_REMOTE_WAKEUP 1 // recip: device
#define FS_TEST_MODE 2 // recip: device
 
// Get Status device attributes
 
#define bmGSDA_SELF_POWERED 0x01
#define bmGSDA_REM_WAKEUP 0x02
 
 
#endif /* _USB_REQUESTS_H_ */
/tools/fx2/src/lib/.cvsignore
0,0 → 1,10
*.asm
*.ihx
*.lnk
*.lst
*.map
*.mem
*.rel
*.rst
*.sym
libfx2.lib
/tools/fx2/src/lib/Makefile
0,0 → 1,37
# $Id: Makefile 394 2011-07-17 17:03:19Z mueller $
#-----------------------------------------------------------------------------
# Makefile for FX2 library code
#-----------------------------------------------------------------------------
# Copyright (C) 2007 Kolja Waschk, ixo.de
#-----------------------------------------------------------------------------
# This code is part of usbjtag. usbjtag is free software; you can redistribute
# it and/or modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of the License,
# or (at your option) any later version. usbjtag is distributed in the hope
# that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details. You should have received a
# copy of the GNU General Public License along with this program in the file
# COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
# St, Fifth Floor, Boston, MA 02110-1301 USA
#-----------------------------------------------------------------------------
 
CC=sdcc
CFLAGS+=-mmcs51 --no-xinit-opt -I.
CPPFLAGS+=
OBJS=delay.rel fx2utils.rel i2c.rel isr.rel timer.rel usb_common.rel
AR=sdcclib
 
(%.rel) : %.c
$(CC) $(CFLAGS) $(CPPFLAGS) -c $< -o $*.rel
$(AR) -a $@ $*.rel
rm $*.rel
 
libfx2.lib: libfx2.lib($(OBJS))
 
clean:
rm -f *.lst *.asm *.lib *.sym *.rel *.lib
 
 
 
 
/tools/fx2/src/lib/isr.c
0,0 → 1,169
/* -*- c++ -*- */
/* $Id: isr.c 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* Interrupt handling for FX2
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#include "isr.h"
#include "fx2regs.h"
#include "syncdelay.h"
 
extern xdata unsigned char _standard_interrupt_vector[];
extern xdata unsigned char _usb_autovector[];
extern xdata unsigned char _fifo_gpif_autovector[];
 
#define LJMP_OPCODE 0x02
 
/*
* Hook standard interrupt vector.
*
* vector_number is from the SV_<foo> list.
* addr is the address of the interrupt service routine.
*/
void
hook_sv (unsigned char vector_number, unsigned short addr)
{
bit t;
// sanity checks
 
if (vector_number < SV_MIN || vector_number > SV_MAX)
return;
 
if ((vector_number & 0x0f) != 0x03 && (vector_number & 0x0f) != 0x0b)
return;
 
t = EA;
EA = 0;
_standard_interrupt_vector[vector_number] = LJMP_OPCODE;
_standard_interrupt_vector[vector_number + 1] = addr >> 8;
_standard_interrupt_vector[vector_number + 2] = addr & 0xff;
EA = t;
}
 
/*
* Hook usb interrupt vector.
*
* vector_number is from the UV_<foo> list.
* addr is the address of the interrupt service routine.
*/
void
hook_uv (unsigned char vector_number, unsigned short addr)
{
bit t;
// sanity checks
 
#if UV_MIN>0
if (vector_number < UV_MIN) return;
#endif
if (vector_number > UV_MAX)
return;
 
if ((vector_number & 0x3) != 0)
return;
 
t = EA;
EA = 0;
_usb_autovector[vector_number] = LJMP_OPCODE;
_usb_autovector[vector_number + 1] = addr >> 8;
_usb_autovector[vector_number + 2] = addr & 0xff;
EA = t;
}
 
/*
* Hook fifo/gpif interrupt vector.
*
* vector_number is from the FGV_<foo> list.
* addr is the address of the interrupt service routine.
*/
void
hook_fgv (unsigned char vector_number, unsigned short addr)
{
bit t;
// sanity checks
 
if (vector_number < FGV_MIN || vector_number > FGV_MAX)
return;
 
if ((vector_number & 0x3) != 0)
return;
 
t = EA;
EA = 0;
_fifo_gpif_autovector[vector_number] = LJMP_OPCODE;
_fifo_gpif_autovector[vector_number + 1] = addr >> 8;
_fifo_gpif_autovector[vector_number + 2] = addr & 0xff;
EA = t;
}
 
/*
* One time call to enable autovectoring for both USB and FIFO/GPIF.
*
* This disables all USB and FIFO/GPIF interrupts and clears
* any pending interrupts too. It leaves the master USB and FIFO/GPIF
* interrupts enabled.
*/
void
setup_autovectors (void)
{
// disable master usb and fifo/gpif interrupt enables
EIUSB = 0;
EIEX4 = 0;
 
hook_sv (SV_INT_2, (unsigned short) _usb_autovector);
hook_sv (SV_INT_4, (unsigned short) _fifo_gpif_autovector);
 
// disable all fifo interrupt enables
SYNCDELAY;
EP2FIFOIE = 0; SYNCDELAY;
EP4FIFOIE = 0; SYNCDELAY;
EP6FIFOIE = 0; SYNCDELAY;
EP8FIFOIE = 0; SYNCDELAY;
 
// clear all pending fifo irqs
EP2FIFOIRQ = 0xff; SYNCDELAY;
EP4FIFOIRQ = 0xff; SYNCDELAY;
EP6FIFOIRQ = 0xff; SYNCDELAY;
EP8FIFOIRQ = 0xff; SYNCDELAY;
 
IBNIE = 0;
IBNIRQ = 0xff;
NAKIE = 0;
NAKIRQ = 0xff;
USBIE = 0;
USBIRQ = 0xff;
EPIE = 0;
EPIRQ = 0xff;
SYNCDELAY; GPIFIE = 0;
SYNCDELAY; GPIFIRQ = 0xff;
USBERRIE = 0;
USBERRIRQ = 0xff;
CLRERRCNT = 0;
INTSETUP = bmAV2EN | bmAV4EN | bmINT4IN;
 
// clear master irq's for usb and fifo/gpif
EXIF &= ~bmEXIF_USBINT;
EXIF &= ~bmEXIF_IE4;
// enable master usb and fifo/gpif interrrupts
EIUSB = 1;
EIEX4 = 1;
}
/tools/fx2/src/lib
tools/fx2/src/lib Property changes : Added: svn:ignore ## -0,0 +1,42 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +*.asm +*.ihx +*.lnk +*.lst +*.map +*.mem +*.rel +*.rst +*.sym +libfx2.lib Index: tools/fx2/src/hw_nexys2.c =================================================================== --- tools/fx2/src/hw_nexys2.c (nonexistent) +++ tools/fx2/src/hw_nexys2.c (revision 17) @@ -0,0 +1,284 @@ +/* $Id: hw_nexys2.c 447 2011-12-31 19:41:32Z mueller $ */ +/* + * Copyright 2011- by Walter F.J. Mueller + * Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17 + * + * - original copyright and licence disclaimer -------------------------------- + * - Copyright (C) 2007 Kolja Waschk, ixo.de + * - This code is part of usbjtag. usbjtag is free software; + * - This code was copied from hw_basic.c and adapted for the Digilent Nexys(2) + * - boards by Sune Mai (Oct 2008) with minor cleanups by Hauke Daempfling + * - (May 2010). See http://www.fpga4fun.com/forum/viewtopic.php?t=483&start=50 + * ---------------------------------------------------------------------------- + * + * This program is free software; you may redistribute and/or modify it under + * the terms of the GNU General Public License as published by the Free + * Software Foundation, either version 2, or at your option any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for complete details. + * + * ---------------------------------------------------------------------------- + * Hardware-dependent code for usb_jtag + * + * Revision History: + * + * Date Rev Version Comment + * 2011-12-30 447 1.2.1 move JTAG pin OE intoProgIO_Set_State() + * 2011-12-29 446 1.2 clean-out all code not relevant for nexys2 + * 2011-07-23 397 1.1 move IFCONFIG and CPUCS init to usb_fifo_init + * 2011-07-17 394 1.0 Initial version (from ixo-jtag/usb_jtag Rev 204) + * + *----------------------------------------------------------------------------- + */ + +#include +#include "hardware.h" +#include "delay.h" + +//----------------------------------------------------------------------------- + +/* JTAG TCK, AS/PS DCLK */ + +sbit at 0xB4 TCK; /* Port D.4 */ +#define bmTCKOE bmBIT4 +#define SetTCK(x) do{TCK=(x);}while(0) + +/* JTAG TDI, AS ASDI, PS DATA0 */ + +sbit at 0xB2 TDI; /* Port D.2 */ +#define bmTDIOE bmBIT2 +#define SetTDI(x) do{TDI=(x);}while(0) + +/* JTAG TMS, AS/PS nCONFIG */ + +sbit at 0xB3 TMS; /* Port D.3 */ +#define bmTMSOE bmBIT3 +#define SetTMS(x) do{TMS=(x);}while(0) + +/* JTAG TDO, AS/PS CONF_DONE */ + +sbit at 0xB0 TDO; /* Port D.0 */ +#define bmTDOOE bmBIT0 +#define GetTDO(x) TDO + +/* USB Power-On (Nexys2 specific !!) */ + +sbit at 0xB7 USBPOW; /* Port D.7 */ +#define bmUSBPOWOE bmBIT7 +#define SetUSBPOW(x) do{USBPOW=(x);}while(0) + +//----------------------------------------------------------------------------- + +#define bmPROGOUTOE (bmTCKOE|bmTDIOE|bmTMSOE) +#define bmPROGINOE (bmTDOOE) + +//----------------------------------------------------------------------------- + +void ProgIO_Poll(void) {} +void ProgIO_Enable(void) {} +// These aren't called anywhere in usbjtag.c so far, might come... +void ProgIO_Disable(void) {} +void ProgIO_Deinit(void) {} + + +void ProgIO_Init(void) +{ + /* The following code depends on your actual circuit design. + Make required changes _before_ you try the code! */ + + // power on the onboard FPGA: + // output enable and set to 1 the Nexys2 USB-Power-enable signal + SetUSBPOW(1); + OED=bmUSBPOWOE; + // Note: JTAG signal output enables are in ProgIO_Set_State() below. + + mdelay(500); // wait for supply to come up +} + +void ProgIO_Set_State(unsigned char d) +{ + /* Set state of output pins: + * + * d.0 => TCK + * d.1 => TMS + * d.4 => TDI + */ + + // JTAG signal output enables done at first request: + // this allows to use the JTAG connector with another JTAG cable + // alternatively. + OED=(OED&~bmPROGINOE) | bmPROGOUTOE; // Output enable + + SetTCK((d & bmBIT0) ? 1 : 0); + SetTMS((d & bmBIT1) ? 1 : 0); + SetTDI((d & bmBIT4) ? 1 : 0); +} + +//----------------------------------------------------------------------------- +// dummied AS/PS code +#define GetASDO(x) 1 + +unsigned char ProgIO_Set_Get_State(unsigned char d) +{ + /* Set state of output pins (s.a.) + * then read state of input pins: + * + * TDO => d.0 + * DATAOUT => d.1 (only #ifdef HAVE_AS_MODE) + */ + + ProgIO_Set_State(d); + return (GetASDO()<<1)|GetTDO(); +} + +//----------------------------------------------------------------------------- + +void ProgIO_ShiftOut(unsigned char c) +{ + /* Shift out byte C: + * + * 8x { + * Output least significant bit on TDI + * Raise TCK + * Shift c right + * Lower TCK + * } + */ + + (void)c; /* argument passed in DPL */ + + _asm + MOV A,DPL + ;; Bit0 + RRC A + MOV _TDI,C + SETB _TCK + ;; Bit1 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit2 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit3 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit4 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit5 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit6 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit7 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + NOP + CLR _TCK + ret + _endasm; +} + +/* +;; For ShiftInOut, the timing is a little more +;; critical because we have to read _TDO/shift/set _TDI +;; when _TCK is low. But 20% duty cycle at 48/4/5 MHz +;; is just like 50% at 6 Mhz, and that's still acceptable +*/ + +unsigned char ProgIO_ShiftInOut(unsigned char c) +{ + /* Shift out byte C, shift in from TDO: + * + * 8x { + * Read carry from TDO + * Output least significant bit on TDI + * Raise TCK + * Shift c right, append carry (TDO) at left + * Lower TCK + * } + * Return c. + */ + + (void)c; /* argument passed in DPL */ + + _asm + MOV A,DPL + + ;; Bit0 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit1 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit2 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit3 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit4 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit5 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit6 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit7 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + NOP + CLR _TCK + + MOV DPL,A + ret + _endasm; + + /* return value in DPL */ + + return c; +} + Index: tools/fx2/src/startup.a51 =================================================================== --- tools/fx2/src/startup.a51 (nonexistent) +++ tools/fx2/src/startup.a51 (revision 17) @@ -0,0 +1,79 @@ +;;; -*- asm -*- +;;; $Id: startup.a51 395 2011-07-17 22:02:55Z mueller $ +;;; +;;;----------------------------------------------------------------------------- +;;; Startup code +;;;----------------------------------------------------------------------------- +;;; Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, +;;; Copyright 2003 Free Software Foundation, Inc. +;;;----------------------------------------------------------------------------- +;;; This code is part of usbjtag. usbjtag is free software; you can redistribute +;;; it and/or modify it under the terms of the GNU General Public License as +;;; published by the Free Software Foundation; either version 2 of the License, +;;; or (at your option) any later version. usbjtag is distributed in the hope +;;; that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +;;; warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;;; GNU General Public License for more details. You should have received a +;;; copy of the GNU General Public License along with this program in the file +;;; COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin +;;; St, Fifth Floor, Boston, MA 02110-1301 USA +;;;----------------------------------------------------------------------------- + +;;; The default external memory initialization provided by sdcc is not +;;; appropriate to the FX2. This is derived from the sdcc code, but uses +;;; the FX2 specific _MPAGE sfr. + + + ;; .area XISEG (XDATA) ; the initialized external data area + ;; .area XINIT (CODE) ; the code space consts to init XISEG + .area XSEG (XDATA) ; zero initialized xdata + .area USBDESCSEG (XDATA) ; usb descriptors + + + .area CSEG (CODE) + + ;; sfr that sets upper address byte of MOVX using @r0 or @r1 + _MPAGE = 0x0092 + +__sdcc_external_startup:: + ;; This system is now compiled with the --no-xinit-opt + ;; which means that any initialized XDATA is handled + ;; inline by code in the GSINIT segs emitted for each file. + ;; + ;; We zero XSEG and all of the internal ram to ensure + ;; a known good state for uninitialized variables. + +; _mcs51_genRAMCLEAR() start + mov r0,#l_XSEG + mov a,r0 + orl a,#(l_XSEG >> 8) + jz 00002$ + mov r1,#((l_XSEG + 255) >> 8) + mov dptr,#s_XSEG + clr a + +00001$: movx @dptr,a + inc dptr + djnz r0,00001$ + djnz r1,00001$ + + ;; We're about to clear internal memory. This will overwrite + ;; the stack which contains our return address. + ;; Pop our return address into DPH, DPL +00002$: pop dph + pop dpl + + ;; R0 and A contain 0. This loop will execute 256 times. + ;; + ;; FWIW the first iteration writes direct address 0x00, + ;; which is the location of r0. We get lucky, we're + ;; writing the correct value (0) + +00003$: mov @r0,a + djnz r0,00003$ + + push dpl ; restore our return address + push dph + + mov dpl,#0 ; indicate that data init is still required + ret Index: tools/fx2/src/eeprom.c =================================================================== --- tools/fx2/src/eeprom.c (nonexistent) +++ tools/fx2/src/eeprom.c (revision 17) @@ -0,0 +1,78 @@ +/* $Id: eeprom.c 395 2011-07-17 22:02:55Z mueller $ */ +/*----------------------------------------------------------------------------- + * FTDI EEPROM emulation + *----------------------------------------------------------------------------- + * Copyright (C) 2007 Kolja Waschk, ixo.de + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#include "eeprom.h" +#include "usb_descriptors.h" + +xdata unsigned char eeprom[128]; + +extern xdata char dscr_vidpidver[6]; +extern xdata char dscr_attrpow[2]; +extern xdata char dscr_usbver[2]; +extern xdata char dscr_strorder[4]; +extern xdata char str1[]; +extern xdata char str2[]; +extern xdata char str3[]; + +static unsigned char ee_ptr; +static unsigned short ee_cksum; + +void eeprom_append(unsigned char nb) +{ + unsigned char pree_ptr = ee_ptr & ~1; + if(pree_ptr != ee_ptr) + { + ee_cksum = ee_cksum ^((unsigned short)nb << 8); + ee_cksum = ee_cksum ^ eeprom[pree_ptr]; + ee_cksum = (ee_cksum << 1) | (ee_cksum >> 15); + }; + eeprom[ee_ptr++] = nb; +} + +void eeprom_init(void) +{ + char j,sofs; + ee_ptr = 0; + ee_cksum = 0xAAAA; + + eeprom_append(0x00); + eeprom_append(0x00); + for(j=0;j<6;j++) eeprom_append(dscr_vidpidver[j]); + for(j=0;j<2;j++) eeprom_append(dscr_attrpow[j]); + eeprom_append(0x1C); + eeprom_append(0x00); + for(j=0;j<2;j++) eeprom_append(dscr_usbver[j]); + sofs = 0x80 + ee_ptr + 6; + eeprom_append(sofs); + eeprom_append(str1[0]); + sofs += str1[0]; + eeprom_append(sofs); + eeprom_append(str2[0]); + sofs += str2[0]; + eeprom_append(sofs); + eeprom_append(str3[0]); + for(j=0;j>8)&0xFF; +} + Index: tools/fx2/src/hw_nexys3.c =================================================================== --- tools/fx2/src/hw_nexys3.c (nonexistent) +++ tools/fx2/src/hw_nexys3.c (revision 17) @@ -0,0 +1,274 @@ +/* $Id: hw_nexys3.c 447 2011-12-31 19:41:32Z mueller $ */ +/* + * Copyright 2011- by Walter F.J. Mueller + * Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17 + * + * - original copyright and licence disclaimer -------------------------------- + * - Copyright (C) 2007 Kolja Waschk, ixo.de + * - This code is part of usbjtag. usbjtag is free software; + * - This code was copied from hw_basic.c and adapted for the Digilent Nexys(2) + * - boards by Sune Mai (Oct 2008) with minor cleanups by Hauke Daempfling + * - (May 2010). See http://www.fpga4fun.com/forum/viewtopic.php?t=483&start=50 + * ---------------------------------------------------------------------------- + * + * This program is free software; you may redistribute and/or modify it under + * the terms of the GNU General Public License as published by the Free + * Software Foundation, either version 2, or at your option any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for complete details. + * + * ---------------------------------------------------------------------------- + * Hardware-dependent code for usb_jtag + * + * Revision History: + * + * Date Rev Version Comment + * 2011-12-30 447 1.0.1 move JTAG pin OE intoProgIO_Set_State() + * 2011-12-29 446 1.0 Initial version (adapt&cleanup from hw_nexys2.c) + * + *----------------------------------------------------------------------------- + */ + +#include +#include "hardware.h" +#include "delay.h" + +//----------------------------------------------------------------------------- + +/* JTAG TCK, AS/PS DCLK */ + +sbit at 0xB4 TCK; /* Port D.4 */ +#define bmTCKOE bmBIT4 +#define SetTCK(x) do{TCK=(x);}while(0) + +/* JTAG TDI, AS ASDI, PS DATA0 */ + +sbit at 0xB2 TDI; /* Port D.2 */ +#define bmTDIOE bmBIT2 +#define SetTDI(x) do{TDI=(x);}while(0) + +/* JTAG TMS, AS/PS nCONFIG */ + +sbit at 0xB3 TMS; /* Port D.3 */ +#define bmTMSOE bmBIT3 +#define SetTMS(x) do{TMS=(x);}while(0) + +/* JTAG TDO, AS/PS CONF_DONE */ + +sbit at 0xB0 TDO; /* Port D.0 */ +#define bmTDOOE bmBIT0 +#define GetTDO(x) TDO + +//----------------------------------------------------------------------------- + +#define bmPROGOUTOE (bmTCKOE|bmTDIOE|bmTMSOE) +#define bmPROGINOE (bmTDOOE) + +//----------------------------------------------------------------------------- + +void ProgIO_Poll(void) {} +void ProgIO_Enable(void) {} +// These aren't called anywhere in usbjtag.c so far, might come... +void ProgIO_Disable(void) {} +void ProgIO_Deinit(void) {} + + +void ProgIO_Init(void) +{ + /* The following code depends on your actual circuit design. + Make required changes _before_ you try the code! */ + + // Note: JTAG signal output enables are in ProgIO_Set_State() below. + + mdelay(500); // wait for supply to come up + +} + +void ProgIO_Set_State(unsigned char d) +{ + /* Set state of output pins: + * + * d.0 => TCK + * d.1 => TMS + * d.4 => TDI + */ + + // JTAG signal output enables done at first request: + // this allows to use the JTAG connector with another JTAG cable + // alternatively. + OED=(OED&~bmPROGINOE) | bmPROGOUTOE; // Output enable + + SetTCK((d & bmBIT0) ? 1 : 0); + SetTMS((d & bmBIT1) ? 1 : 0); + SetTDI((d & bmBIT4) ? 1 : 0); +} + +//----------------------------------------------------------------------------- +// dummied AS/PS code +#define GetASDO(x) 1 + +unsigned char ProgIO_Set_Get_State(unsigned char d) +{ + /* Set state of output pins (s.a.) + * then read state of input pins: + * + * TDO => d.0 + * DATAOUT => d.1 (only #ifdef HAVE_AS_MODE) + */ + + ProgIO_Set_State(d); + return (GetASDO()<<1)|GetTDO(); +} + +//----------------------------------------------------------------------------- + +void ProgIO_ShiftOut(unsigned char c) +{ + /* Shift out byte C: + * + * 8x { + * Output least significant bit on TDI + * Raise TCK + * Shift c right + * Lower TCK + * } + */ + + (void)c; /* argument passed in DPL */ + + _asm + MOV A,DPL + ;; Bit0 + RRC A + MOV _TDI,C + SETB _TCK + ;; Bit1 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit2 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit3 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit4 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit5 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit6 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit7 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + NOP + CLR _TCK + ret + _endasm; +} + +/* +;; For ShiftInOut, the timing is a little more +;; critical because we have to read _TDO/shift/set _TDI +;; when _TCK is low. But 20% duty cycle at 48/4/5 MHz +;; is just like 50% at 6 Mhz, and that's still acceptable +*/ + +unsigned char ProgIO_ShiftInOut(unsigned char c) +{ + /* Shift out byte C, shift in from TDO: + * + * 8x { + * Read carry from TDO + * Output least significant bit on TDI + * Raise TCK + * Shift c right, append carry (TDO) at left + * Lower TCK + * } + * Return c. + */ + + (void)c; /* argument passed in DPL */ + + _asm + MOV A,DPL + + ;; Bit0 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit1 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit2 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit3 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit4 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit5 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit6 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit7 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + NOP + CLR _TCK + + MOV DPL,A + ret + _endasm; + + /* return value in DPL */ + + return c; +} + + Index: tools/fx2/src/dscr_gen.A51 =================================================================== --- tools/fx2/src/dscr_gen.A51 (nonexistent) +++ tools/fx2/src/dscr_gen.A51 (revision 17) @@ -0,0 +1,455 @@ +;;; -*- asm -*- +;;; $Id: dscr_gen.A51 457 2012-02-12 22:34:20Z mueller $ +;;; +;;; Copyright 2011-2012 by Walter F.J. Mueller +;;; Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17 +;;; +;;;- original copyright and licence disclaimer --------------------------------- +;;;- Copyright 2005..2007 Kolja Waschk, ixo.de +;;;- Code based on USRP2 firmware (GNU Radio Project), version 3.0.2, +;;;- Copyright 2003 Free Software Foundation, Inc. +;;;- This code is part of usbjtag. usbjtag is free software; +;;;- --------------------------------------------------------------------------- +;;; +;;; This program is free software; you may redistribute and/or modify it under +;;; the terms of the GNU General Public License as published by the Free +;;; Software Foundation, either version 2, or at your option any later version. +;;; +;;; This program is distributed in the hope that it will be useful, but +;;; WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +;;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +;;; for complete details. +;;; +;;;----------------------------------------------------------------------------- +;;; USB Descriptor, common source for jtag + 0, 2, or 3 hardware fifo interface +;;; +;;; Use C preprocessor to create an assembler source for the configurations: +;;; +;;; Endpoint Usage Comment +;;; EP1 IN jtag always defined +;;; EP2 OUT jtag always defined +;;; EP4 OUT data defined if USE_2FIFO or USE_3FIFO +;;; EP6 IN data defined if USE_2FIFO or USE_3FIFO +;;; EP8 IN data defined if USE_3FIFO +;;; +;;; Available preprocessor options +;;; +;;; USE_VID USB Vendor ID +;;; USE_PID USB Product ID +;;; +;;; USE_2FIFO if given EP4 OUT and EP6 IN created +;;; USE_3FIFO if given EP4 OUT, EP6 IN and EP8 IN created +;;; USE_DID=0xhhhh for product version (default 0x0004) +;;; USE_MAXPOWER=nnn for USB max current (in units of 2 mA; default 250) +;;; +;;; USE_NEXYS2 prefix 'nexys2_' in iProduct string +;;; USE_NEXYS3 prefix 'nexys3_' in iProduct string +;;; USE_AS suffix '_as' in iProduct string +;;; USE_IC suffix '_ic' in iProduct string +;;; +;;; Usage +;;; cpp -P -x assembler-with-cpp dscr_gen.A51 > ... +;;; cpp -P -x assembler-with-cpp dscr_gen.A51 -DUSE_2FIFO > ... +;;; cpp -P -x assembler-with-cpp dscr_gen.A51 -DUSE_3FIFO > ... +;;; +;;; +;;; Revision History: +;;; +;;; Date Rev Version Comment +;;; 2012-02-11 457 2.1 iVendor string now reflects firmware file name; +;;; iSerial string now 00000000; +;;; VID/PID now via USE_VID/USE_PID defines +;;; 2011-07-24 398 2.0 Convert all *.a51 to one common source +;;; 2011-07-17 395 1.1 Use USB 2.0; New string values; use 512 byte for +;;; all high speed endpoints +;;; 2011-07-17 395 1.0 Initial version (derived from dscr_jtag.a51) +;;;----------------------------------------------------------------------------- + +#ifndef USE_DID +#define USE_DID 0x0004 +#endif + +#ifndef USE_MAXPOWER +#define USE_MAXPOWER 250 +#endif + +#ifdef USE_3FIFO +#define NUM_EPS 5 +#elif USE_2FIFO +#define NUM_EPS 4 +#else +#define NUM_EPS 2 +#endif + + .module usb_descriptors + + VID = USE_VID ; Vendor ID + PID = USE_PID ; Product ID + VERSION = USE_DID ; Version + + USB_VER = 0x0200 ; Support USB version 2.00 + USB_ATTR = 0x80 ; Bus powered, no remote wakeup + FTD_ATTR = 0x001C ; Set USB version, use version string, enable suspend PD + MAX_POWER = USE_MAXPOWER + + DSCR_DEVICE = 1 ; Descriptor type: Device + DSCR_CONFIG = 2 ; Descriptor type: Configuration + DSCR_STRING = 3 ; Descriptor type: String + DSCR_INTRFC = 4 ; Descriptor type: Interface + DSCR_ENDPNT = 5 ; Descriptor type: Endpoint + DSCR_DEVQUAL = 6 ; Descriptor type: Device Qualifier + + DSCR_DEVICE_LEN = 18 + DSCR_CONFIG_LEN = 9 + DSCR_INTRFC_LEN = 9 + DSCR_ENDPNT_LEN = 7 + DSCR_DEVQUAL_LEN = 10 + + ET_CONTROL = 0 ; Endpoint type: Control + ET_ISO = 1 ; Endpoint type: Isochronous + ET_BULK = 2 ; Endpoint type: Bulk + ET_INT = 3 ; Endpoint type: Interrupt + +;;; -------------------------------------------------------- +;;; external ram data +;;;-------------------------------------------------------- + + .area USBDESCSEG (XDATA) + + .even ; descriptors must be 2-byte aligned for SUDPTR{H,L} to work + + ;; The .even directive isn't really honored by the linker. Bummer! + ;; (There's no way to specify an alignment requirement for a given area, + ;; hence when they're concatenated together, even doesn't work.) + ;; + ;; We work around this by telling the linker to put USBDESCSEG + ;; at absolute address 0xE100 (see LDFLAGS in Makefile). + +;;; ---------------------------------------------------------------- +;;; descriptors used when operating at high speed (480Mbps) +;;; ---------------------------------------------------------------- + +_high_speed_device_descr:: + .db DSCR_DEVICE_LEN + .db DSCR_DEVICE +_dscr_usbver:: + .db USB_VER ; Specification version (MSB) + .db 0x00 ; device class (vendor specific) + .db 0x00 ; device subclass (vendor specific) + .db 0x00 ; device protocol (vendor specific) + .db 64 ; bMaxPacketSize0 for endpoint 0 +_dscr_vidpidver:: + .db VID ; idVendor + .db PID ; idProduct + .db VERSION ; bcdDevice +_dscr_strorder:: + .db SI_VENDOR ; iManufacturer (string index) + .db SI_PRODUCT ; iProduct (string index) + .db SI_SERIAL ; iSerial number (string index) + .db 1 ; bNumConfigurations + + .even +_high_speed_devqual_descr:: + .db DSCR_DEVQUAL_LEN + .db DSCR_DEVQUAL + .db USB_VER ; bcdUSB (MSB) + .db 0xFF ; bDeviceClass + .db 0xFF ; bDeviceSubClass + .db 0xFF ; bDeviceProtocol + .db 64 ; bMaxPacketSize0 + .db 1 ; bNumConfigurations (one config at 12Mbps) + .db 0 ; bReserved + + .even +_high_speed_config_descr:: + .db DSCR_CONFIG_LEN + .db DSCR_CONFIG + .db <(_high_speed_config_descr_end - _high_speed_config_descr) + .db >(_high_speed_config_descr_end - _high_speed_config_descr) + .db 1 ; bNumInterfaces + .db 1 ; bConfigurationValue + .db 0 ; iConfiguration +_dscr_attrpow:: + .db USB_ATTR ; bmAttributes + .db MAX_POWER ; bMaxPower [Unit: 2 mA] + + ;; interface descriptor + + .db DSCR_INTRFC_LEN + .db DSCR_INTRFC + .db 0 ; bInterfaceNumber (zero based) + .db 0 ; bAlternateSetting + .db NUM_EPS ; bNumEndpoints + .db 0xFF ; bInterfaceClass (vendor specific) + .db 0xFF ; bInterfaceSubClass (vendor specific) + .db 0xFF ; bInterfaceProtocol (vendor specific) + .db SI_PRODUCT ; iInterface (description) + + ;; endpoint descriptor (jtag response) + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x81 ; bEndpointAddress (EP 1 IN) + .db ET_BULK ; bmAttributes + .db <512 ; wMaxPacketSize (LSB) !! use only 64 byte + .db >512 ; wMaxPacketSize (MSB) !! use only 64 byte + .db 0 ; bInterval (iso only) + + ;; endpoint descriptor (jtag request) + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x02 ; bEndpointAddress (EP 2 OUT) + .db ET_BULK ; bmAttributes + .db <512 ; wMaxPacketSize (LSB) !! use only 64 byte + .db >512 ; wMaxPacketSize (MSB) !! use only 64 byte + .db 0 ; bInterval (iso only) + +#if defined(USE_2FIFO) || defined(USE_3FIFO) + + ;; endpoint descriptor (RXFIFO HOST->FPGA) + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x04 ; bEndpointAddress (EP 4 OUT) + .db ET_BULK ; bmAttributes + .db <512 ; wMaxPacketSize (LSB) + .db >512 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + + ;; endpoint descriptor (TXFIFO FPGA->HOST) + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x86 ; bEndpointAddress (EP 6 IN) + .db ET_BULK ; bmAttributes + .db <512 ; wMaxPacketSize (LSB) + .db >512 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + +#endif + +#if defined(USE_3FIFO) + + ;; endpoint descriptor (extra FIFO FPGA->HOST) + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x88 ; bEndpointAddress (EP 8 IN) + .db ET_BULK ; bmAttributes + .db <512 ; wMaxPacketSize (LSB) + .db >512 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + +#endif + +_high_speed_config_descr_end: + +;;; ---------------------------------------------------------------- +;;; descriptors used when operating at full speed (12Mbps) +;;; no data fifo endpoints defined, if we are in full speed mode this will be no +;;; fun anyway. Shouldn't happen anyway, unless stone age USB hubs interfere... +;;; ---------------------------------------------------------------- + + .even +_full_speed_device_descr:: + .db DSCR_DEVICE_LEN + .db DSCR_DEVICE + .db USB_VER ; Specification version (MSB) + .db 0x00 ; device class (vendor specific) + .db 0x00 ; device subclass (vendor specific) + .db 0x00 ; device protocol (vendor specific) + .db 64 ; bMaxPacketSize0 for endpoint 0 + .db VID ; idVendor + .db PID ; idProduct + .db VERSION ; bcdDevice + .db SI_VENDOR ; iManufacturer (string index) + .db SI_PRODUCT ; iProduct (string index) + .db SI_SERIAL ; iSerial number (string index) + .db 1 ; bNumConfigurations + +;;; describes the other speed (480Mbps) + .even +_full_speed_devqual_descr:: + .db DSCR_DEVQUAL_LEN + .db DSCR_DEVQUAL + .db USB_VER ; bcdUSB + .db 0xFF ; bDeviceClass + .db 0xFF ; bDeviceSubClass + .db 0xFF ; bDeviceProtocol + .db 64 ; bMaxPacketSize0 + .db 1 ; bNumConfigurations (one config at 480Mbps) + .db 0 ; bReserved + + .even +_full_speed_config_descr:: + .db DSCR_CONFIG_LEN + .db DSCR_CONFIG + .db <(_full_speed_config_descr_end - _full_speed_config_descr) + .db >(_full_speed_config_descr_end - _full_speed_config_descr) + .db 1 ; bNumInterfaces + .db 1 ; bConfigurationValue + .db 0 ; iConfiguration + .db USB_ATTR ; bmAttributes + .db MAX_POWER ; bMaxPower [Unit: 2 mA] + + ;; interface descriptor + + .db DSCR_INTRFC_LEN + .db DSCR_INTRFC + .db 0 ; bInterfaceNumber (zero based) + .db 0 ; bAlternateSetting + .db 2 ; bNumEndpoints + .db 0xFF ; bInterfaceClass (vendor specific) + .db 0xFF ; bInterfaceSubClass (vendor specific) + .db 0xFF ; bInterfaceProtocol (vendor specific) + .db SI_PRODUCT ; iInterface (description) + + ;; endpoint descriptor + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x81 ; bEndpointAddress (EP 1 IN) + .db ET_BULK ; bmAttributes + .db <64 ; wMaxPacketSize (LSB) + .db >64 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + + ;; endpoint descriptor + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x02 ; bEndpointAddress (EP 2 OUT) + .db ET_BULK ; bmAttributes + .db <64 ; wMaxPacketSize (LSB) + .db >64 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + +_full_speed_config_descr_end: + +;;; ---------------------------------------------------------------- +;;; string descriptors +;;; ---------------------------------------------------------------- + +_nstring_descriptors:: + .db (_string_descriptors_end - _string_descriptors) / 2 + +_string_descriptors:: + .db str0 + .db str1 + .db str2 + .db str3 +_string_descriptors_end: + + SI_NONE = 0 + ;; str0 contains the language ID's. + .even +_str0:: +str0: .db str0_end - str0 + .db DSCR_STRING + .db 0 + .db 0 + .db <0x0409 ; magic code for US English (LSB) + .db >0x0409 ; magic code for US English (MSB) +str0_end: + + SI_VENDOR = 1 + .even +_str1:: +str1: .db str1_end - str1 + .db DSCR_STRING + .db 'w, 0 ; 16-bit unicode + .db 'w, 0 + .db 'w, 0 + .db '., 0 + .db 'r, 0 + .db 'e, 0 + .db 't, 0 + .db 'r, 0 + .db 'o, 0 + .db '1, 0 + .db '1, 0 + .db '., 0 + .db 'd, 0 + .db 'e, 0 +str1_end: + + SI_PRODUCT = 2 + .even +_str2:: +str2: .db str2_end - str2 + .db DSCR_STRING +#if defined(USE_NEXYS2) + .db 'n, 0 + .db 'e, 0 + .db 'x, 0 + .db 'y, 0 + .db 's, 0 + .db '2, 0 + .db '_, 0 +#endif +#if defined(USE_NEXYS3) + .db 'n, 0 + .db 'e, 0 + .db 'x, 0 + .db 'y, 0 + .db 's, 0 + .db '3, 0 + .db '_, 0 +#endif + .db 'j, 0 + .db 't, 0 + .db 'a, 0 + .db 'g, 0 +#if defined(USE_2FIFO) + .db '_, 0 + .db '2, 0 + .db 'f, 0 + .db 'i, 0 + .db 'f, 0 + .db 'o, 0 +#endif +#if defined(USE_3FIFO) + .db '_, 0 + .db '3, 0 + .db 'f, 0 + .db 'i, 0 + .db 'f, 0 + .db 'o, 0 +#endif +#if defined(USE_AS) + .db '_, 0 + .db 'a, 0 + .db 's, 0 +#endif +#if defined(USE_IC) + .db '_, 0 + .db 'i, 0 + .db 'c, 0 +#endif +str2_end: + + SI_SERIAL = 3 + .even +_str3:: +str3: .db str3_end - str3 + .db DSCR_STRING + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 +str3_end: Index: tools/fx2/src/vectors.a51 =================================================================== --- tools/fx2/src/vectors.a51 (nonexistent) +++ tools/fx2/src/vectors.a51 (revision 17) @@ -0,0 +1,177 @@ +;;; -*- asm -*- +;;; $Id: vectors.a51 395 2011-07-17 22:02:55Z mueller $ +;;; +;;;----------------------------------------------------------------------------- +;;; Interrupt vectors +;;;----------------------------------------------------------------------------- +;;; Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, +;;; Copyright 2003 Free Software Foundation, Inc. +;;;----------------------------------------------------------------------------- +;;; This code is part of usbjtag. usbjtag is free software; you can redistribute +;;; it and/or modify it under the terms of the GNU General Public License as +;;; published by the Free Software Foundation; either version 2 of the License, +;;; or (at your option) any later version. usbjtag is distributed in the hope +;;; that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +;;; warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;;; GNU General Public License for more details. You should have received a +;;; copy of the GNU General Public License along with this program in the file +;;; COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin +;;; St, Fifth Floor, Boston, MA 02110-1301 USA +;;;----------------------------------------------------------------------------- + +;;; N.B. This object module must come first in the list of modules + + .module vectors + +;;; ---------------------------------------------------------------- +;;; standard FX2 interrupt vectors +;;; ---------------------------------------------------------------- + + .area CSEG (CODE) + .area GSINIT (CODE) + .area CSEG (CODE) +__standard_interrupt_vector:: +__reset_vector:: + ljmp s_GSINIT + + ;; 13 8-byte entries. We point them all at __isr_nop + ljmp __isr_nop ; 3 bytes + .ds 5 ; + 5 = 8 bytes for vector slot + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + +__isr_nop:: + reti + +;;; ---------------------------------------------------------------- +;;; the FIFO/GPIF autovector. 14 4-byte entries. +;;; must start on a 128 byte boundary. +;;; ---------------------------------------------------------------- + + . = __reset_vector + 0x0080 + +__fifo_gpif_autovector:: + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + + +;;; ---------------------------------------------------------------- +;;; the USB autovector. 32 4-byte entries. +;;; must start on a 256 byte boundary. +;;; ---------------------------------------------------------------- + + . = __reset_vector + 0x0100 + +__usb_autovector:: + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop Index: tools/fx2/src/README_iso_jtag.txt =================================================================== --- tools/fx2/src/README_iso_jtag.txt (nonexistent) +++ tools/fx2/src/README_iso_jtag.txt (revision 17) @@ -0,0 +1,123 @@ +$ Id: $ + +usb_jtag using Cypress FX2 chip +=============================== + +== General information == + +The code in this directory is for Cypress FX2 (e.g. CY7C68013A) and can be +compiled with the SDCC compiler (I tried version 2.6 as shipped with Ubuntu +6.10). Once I had a version that could be compiled with Keil tools (until early +2007), but switched to SDCC because I usually develop on a Linux host. + +No logic beside the FX2 itself and only a few external components are required +for a basic JTAG adapter. I don't have detailed schematics available; my test +setup consists of a FX2 on a custom board where it's directly connected to a +Cyclone FPGA. + + ____________ + | | + | Cypress | + USB__| EZ-USB FX2 |__JTAG(TDI,TDO,TCK,TMS) + | CY7C68013A | + |____________| + __|__________ + | | + | 24 MHz XTAL | + |_____________| + + +Similar boards are available from fpga4fun.com - the boards named "Saxo-L" and +"Xylo-EM" are pre-wired for use with an adapted version of my code, while +"Saxo" and "Xylo" can be used after soldering 4 extra wires: + + http://www.fpga4fun.com/board_Xylo.html + +There's a discussion thread in the fpga4fun forum about this firmware: + + http://www.fpga4fun.com/forum/viewtopic.php?t=483 + + +== Use with Nexys 1 / 2 Boards == + +Through a contribution by Sune Mai, this code can be used with the Digilent +Nexys / Nexys2 boards. + + http://www.digilentinc.com/nexys/ + http://www.digilentinc.com/nexys2/ + +The hardware-specific code file is hw_nexys.c, just change the line +"HARDWARE=hw_basic" to "HARDWARE=hw_nexys" in the file "Makefile" to use it. + +Also, you may use the "nexys2prog" script by Andy Ross, available from the +same place this code is available from: + + http://ixo-jtag.sourceforge.net/ + + +== Adapting the code to your hardware == + +As is, the code assumes the following pin assignment: + + Port C.0: TDI + Port C.1: TDO + Port C.2: TCK + Port C.3: TMS + +Other assignments are possible. If you have your signals connected to +bit-addressable I/O pins (port A,B,C or D), I suggest you make a copy of +hw_basic.c and adapt the definitions and ProgIO_Init() in it to your needs. +The file hw_saxo_l is even simpler to adapt if you want only JTAG and no AS/PS +mode. If your signals are not on bit-addressable I/Os (that is, you're using +port E), you could base your adaptation on the slower hw_xpcu_i.c. You may +specify the name of your adapted hardware-specific file when "make"ing, e.g.: + + make HARDWARE=hw_saxo_l + + +The USB identification data (vendor/product ID, strings, ...) can be modified +in dscr.a51. The firmware emulates the 128 byte EEPROM that usually holds +configuration data for the FT245 and which can be read from the host; its +content (including checksum) is computed from the data in dscr.a51 as well. + +The WAKEUP pin should be high for the re-numeration to work reliably (thanks +Jean/fpga4fun!). + + +== Using it with Xilinx JTAG cable == + +There is code to support running in the "Xilinx Platform Cable USB". If you +select HARDWARE=hw_xpcu_i or hw_xpcu_x at the top of the Makefile, a firmware +for the XPCU will be built. I've tested this only with unmodified CPLD version +18 (0x12) on a Spartan-3E starter kit, as it was programmed by my WebPack 8.2i. +The code needs optimization; yet it is merely a proof of concept. +Compile for the XPCU with e.g. "make HARDWARE=hw_xpcu_x". + + hw_xpcu_i: Access "internal" chain (the XPCU CPLD, IC3, itself) + hw_xpcu_x: Access "external" chain (the Spartan 3E, PROM, etc.) + + +== History == + +Changes since previous release 2008-07-05: + - Imported to SourceForge, please see the project page: + http://ixo-jtag.sourceforge.net/ + +Changes since previous release on 2007-02-15: + - Jean Nicolle contributed hw_saxo_l.c for the FX2 boards from fpga4fun.com + - fx2/Makefile fixed to build correct libfx2.lib even under Windows. + +Changes since previous release on 2007-01-28: + - Initial suppport for running on Xilinx XPCU. + - New FX2 code, based on USRP2 from the GNU Radio Project; + - Firmware can now be compiled using SDCC 2.6. No more Keil support. + - EEPROM content is automatically computed from dscr.a51, including checksum. + +Changes since initial release on 2006-04-23: + - added this readme.txt + - reorganized my project folder: diff now created from Subversion repository + - stripped *.dist extension from eeprom.c and dscr.a51 + - added unique proper product and vendor ID (thanks to Antti Lukats!) + - fixed checksum in eeprom.c + - added comments about AS/PS mode pins in usbjtag.c + Index: tools/fx2/src/README.txt =================================================================== --- tools/fx2/src/README.txt (nonexistent) +++ tools/fx2/src/README.txt (revision 17) @@ -0,0 +1,25 @@ +# $Id: README.txt 395 2011-07-17 22:02:55Z mueller $ +# + +The FX2 software is based on the Sourceforge project ixo-jtag + + http://sourceforge.net/projects/ixo-jtag/ + +The usb_jtag sub project was checked out on 2011-07-17 (Rev 204) +from Sourceforge and take as the basis for the further developement. +The original README.txt is preserved under README_iso_jtag.txt. +Only the hw_nexys.c branch is kept on the import. + +Change log: + +2011-07-17 (Rev 395) + - Makefile: reorganized to support multiple target/fifo configs + - renames: + dscr.a51->dscr_jtag.a51 + hw_nexys.c->hw_nexys2.c + usbjtag.c->main.c + - dscr_jtag.a51 + - Use USB 2.0; New string values + - use 512 byte for all high speed endpoints + - dscr_jtag_2fifo.a51 + - dscr with EP4 as HOST->FPGA and EP6 as FPGA->HOST hardware fifo Index: tools/fx2/src/Makefile =================================================================== --- tools/fx2/src/Makefile (nonexistent) +++ tools/fx2/src/Makefile (revision 17) @@ -0,0 +1,219 @@ +# $Id: Makefile 461 2012-04-09 21:17:54Z mueller $ +# +# Copyright 2011-2012 by Walter F.J. Mueller +# Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17 +# +# - original copyright and licence disclaimer -------------------------------- +# - Copyright 2007 Kolja Waschk, ixo.de +# - This code is part of usbjtag. usbjtag is free software; +#----------------------------------------------------------------------------- +# +# This program is free software; you may redistribute and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation, either version 2, or at your option any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for complete details. +#----------------------------------------------------------------------------- +# +# Makefile for FX2 Firmware on Digilent Nexys2, Nexys3, and Atlys boards +# +# Revision History: +# Date Rev Version Comment +# 2012-04-09 461 1.5.1 fixed nexys3_jtag_3fifo_ic.ihx rule,used _2fifo code +# 2012-02-11 457 1.5 re-organize VID/PID and descriptor handling +# 2012-01-02 448 1.4 add support for sync fifo w/ int. clock (_ic) +# 2011-12-29 446 1.3 add nexys3 support +# 2011-07-23 397 1.2 add usb_fifo_init.c +# 2011-07-17 395 1.1 reorganized to support multiple target/fifo configs +# 2011-07-17 394 1.0 Initial version (from ixo-jtag/usb_jtag Rev 204) +#----------------------------------------------------------------------------- +# +# handle USB VID/PID +# - normaly given via the environment variables (as 4 digit hex number) +# RETRO_FX2_VID +# RETRO_FX2_PID +# +# - in the retro11 project the default is: +# VID: 16c0 (VOTI) +# PID: 03ef (VOTI free for internal lab use 1007) +# +# !! Important Note on Usage of this USB VID/PID !! +# This VID/PID is owned by VOTI, a small dutch company. Usage is granted +# for 'internal lab use only' by VOTI under the conditions: +# - the gadgets in which you use those PIDs do not leave your desk +# - you won't complain to VOTI if you get in trouble with duplicate PIDs +# (for instance because someone else did not follow the previous rule). +# See also http://www.voti.nl/pids/pidfaq.html +# +ifndef RETRO_FX2_VID +RETRO_FX2_VID = 16c0 +endif +ifndef RETRO_FX2_PID +RETRO_FX2_PID = 03ef +endif +# +DEFVIDPID=-DUSE_VID=0x${RETRO_FX2_VID} -DUSE_PID=0x${RETRO_FX2_PID} +# +# compiler and assembler flags +# +LIBDIR=lib +LIB=libfx2.lib + +CC=sdcc +CFLAGS+=-mmcs51 --no-xinit-opt -I${LIBDIR} + +AS=asx8051 +ASFLAGS+=-plosgff + +LDFLAGS=--code-loc 0x0000 --code-size 0x1800 +LDFLAGS+=--xram-loc 0x1800 --xram-size 0x0800 +LDFLAGS+=-Wl '-b USBDESCSEG = 0xE100' +LDFLAGS+=-L ${LIBDIR} +# +# compile rules +# +%.rel : %.a51 + $(AS) $(ASFLAGS) $< + +%.rel : %.c + $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@ +# +# link rule +# +%.ihx : + $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $+ +# +# primary target rules +# +ALLIHX =nexys2_jtag.ihx +ALLIHX +=nexys2_jtag_2fifo_as.ihx +ALLIHX +=nexys2_jtag_3fifo_as.ihx +ALLIHX +=nexys2_jtag_2fifo_ic.ihx +ALLIHX +=nexys2_jtag_3fifo_ic.ihx +ALLIHX +=nexys3_jtag.ihx +ALLIHX +=nexys3_jtag_2fifo_as.ihx +ALLIHX +=nexys3_jtag_3fifo_as.ihx +ALLIHX +=nexys3_jtag_2fifo_ic.ihx +ALLIHX +=nexys3_jtag_3fifo_ic.ihx + +.PHONY: all install + +all: $(ALLIHX) + +install: $(ALLIHX) + cp -p $(ALLIHX) ../bin +# +# rules to create USB descriptor sources +# +CPPA51=cpp -P -x assembler-with-cpp + +dscr_nexys2_jtag.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS2 $< > $@ +dscr_nexys2_jtag_2fifo_as.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS2 -DUSE_2FIFO -DUSE_AS $< > $@ +dscr_nexys2_jtag_3fifo_as.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS2 -DUSE_3FIFO -DUSE_AS $< > $@ +dscr_nexys2_jtag_2fifo_ic.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS2 -DUSE_2FIFO -DUSE_IC $< > $@ +dscr_nexys2_jtag_3fifo_ic.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS2 -DUSE_3FIFO -DUSE_IC $< > $@ + +dscr_nexys3_jtag.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS3 $< > $@ +dscr_nexys3_jtag_2fifo_as.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS3 -DUSE_2FIFO -DUSE_AS $< > $@ +dscr_nexys3_jtag_3fifo_as.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS3 -DUSE_3FIFO -DUSE_AS $< > $@ +dscr_nexys3_jtag_2fifo_ic.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS3 -DUSE_2FIFO -DUSE_IC $< > $@ +dscr_nexys3_jtag_3fifo_ic.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS3 -DUSE_3FIFO -DUSE_IC $< > $@ +# +# rules to create usb_fifo_init variants +# +usb_fifo_init_jtag.rel : usb_fifo_init.c + $(CC) -c $(CFLAGS) $< -o $@ +# +usb_fifo_init_jtag_2fifo_as.rel : usb_fifo_init.c + $(CC) -c $(CFLAGS) -DUSE_2FIFO $< -o $@ +usb_fifo_init_jtag_3fifo_as.rel : usb_fifo_init.c + $(CC) -c $(CFLAGS) -DUSE_3FIFO $< -o $@ +# +usb_fifo_init_jtag_2fifo_ic.rel : usb_fifo_init.c + $(CC) -c $(CFLAGS) -DUSE_2FIFO -DUSE_IC30 $< -o $@ +usb_fifo_init_jtag_3fifo_ic.rel : usb_fifo_init.c + $(CC) -c $(CFLAGS) -DUSE_3FIFO -DUSE_IC30 $< -o $@ +# +COM_REL=vectors.rel main.rel eeprom.rel startup.rel +# +I0_REL=usb_fifo_init_jtag.rel +# +IAS2_REL=usb_fifo_init_jtag_2fifo_as.rel +IAS3_REL=usb_fifo_init_jtag_3fifo_as.rel +# +IIC2_REL=usb_fifo_init_jtag_2fifo_ic.rel +IIC3_REL=usb_fifo_init_jtag_3fifo_ic.rel +# +N2_REL=hw_nexys2.rel +N3_REL=hw_nexys3.rel +# +LIB_REL=$(LIBDIR)/$(LIB) +# +# rules to compile all code +# +$(LIBDIR)/$(LIB) : + make -C $(LIBDIR) + +eeprom.rel : eeprom.c eeprom.h +main.rel : main.c hardware.h eeprom.h + +$(N2_REL) : hw_nexys2.c hardware.h +$(N3_REL) : hw_nexys3.c hardware.h + +# +# rules to build Nexys2 firmware images +# +nexys2_jtag.ihx : $(COM_REL) dscr_nexys2_jtag.rel \ + $(N2_REL) $(I0_REL) $(LIB_REL) +# +nexys2_jtag_2fifo_as.ihx : $(COM_REL) dscr_nexys2_jtag_2fifo_as.rel \ + $(N2_REL) $(IAS2_REL) $(LIB_REL) +nexys2_jtag_3fifo_as.ihx : $(COM_REL) dscr_nexys2_jtag_3fifo_as.rel \ + $(N2_REL) $(IAS3_REL) $(LIB_REL) +# +nexys2_jtag_2fifo_ic.ihx : $(COM_REL) dscr_nexys2_jtag_2fifo_ic.rel \ + $(N2_REL) $(IIC2_REL) $(LIB_REL) +nexys2_jtag_3fifo_ic.ihx : $(COM_REL) dscr_nexys2_jtag_3fifo_ic.rel \ + $(N2_REL) $(IIC3_REL) $(LIB_REL) +# +# rules to build Nexys3 firmware images +# +nexys3_jtag.ihx : $(COM_REL) dscr_nexys3_jtag.rel \ + $(N3_REL) $(I0_REL) $(LIB_REL) +# +nexys3_jtag_2fifo_as.ihx : $(COM_REL) dscr_nexys3_jtag_2fifo_as.rel \ + $(N3_REL) $(IAS2_REL) $(LIB_REL) +nexys3_jtag_3fifo_as.ihx : $(COM_REL) dscr_nexys3_jtag_3fifo_as.rel \ + $(N3_REL) $(IAS3_REL) $(LIB_REL) +# +nexys3_jtag_2fifo_ic.ihx : $(COM_REL) dscr_nexys3_jtag_2fifo_ic.rel \ + $(N3_REL) $(IIC2_REL) $(LIB_REL) +nexys3_jtag_3fifo_ic.ihx : $(COM_REL) dscr_nexys3_jtag_3fifo_ic.rel \ + $(N3_REL) $(IIC3_REL) $(LIB_REL) +# +# cleanup phony's +# +.PHONY : clean distclean + +clean : + make -C ${LIBDIR} clean + rm -f *.lst *.asm *.lib *.sym *.rel *.mem *.map *.rst *.lnk + rm -f dscr_*.a51 + +distclean : clean + rm -f *.ihx + + Index: tools/fx2/src/eeprom.h =================================================================== --- tools/fx2/src/eeprom.h (nonexistent) +++ tools/fx2/src/eeprom.h (revision 17) @@ -0,0 +1,27 @@ +/* $Id: eeprom.h 395 2011-07-17 22:02:55Z mueller $ */ +/*----------------------------------------------------------------------------- + * FTDI EEPROM emulation + *----------------------------------------------------------------------------- + * Copyright (C) 2007 Kolja Waschk, ixo.de + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#ifndef _EEPROM_H +#define _EEPROM_H 1 + +extern xdata unsigned char eeprom[128]; +extern void eeprom_init(void); + +#endif /* _EEPROM_H */ + Index: tools/fx2/src/.cvsignore =================================================================== --- tools/fx2/src/.cvsignore (nonexistent) +++ tools/fx2/src/.cvsignore (revision 17) @@ -0,0 +1,10 @@ +*.asm +*.ihx +*.lnk +*.lst +*.map +*.mem +*.rel +*.rst +*.sym +dscr_*.a51 Index: tools/fx2/src =================================================================== --- tools/fx2/src (nonexistent) +++ tools/fx2/src (revision 17)
tools/fx2/src Property changes : Added: svn:ignore ## -0,0 +1,42 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +*.asm +*.ihx +*.lnk +*.lst +*.map +*.mem +*.rel +*.rst +*.sym +dscr_*.a51 Index: tools/fx2/bin/nexys2_jtag.ihx =================================================================== --- tools/fx2/bin/nexys2_jtag.ihx (nonexistent) +++ tools/fx2/bin/nexys2_jtag.ihx (revision 17) @@ -0,0 +1,437 @@ +:06000000020DAC02006BD2 +:03000B0002006B85 +:0300130002006B7D +:03001B0002006B75 +:0300230002006B6D +:03002B0002006B65 +:0300330002006B5D +:03003B0002006B55 +:0300430002006B4D +:03004B0002006B45 +:0300530002006B3D +:03005B0002006B35 +:0300630002006B2D +:01006B003262 +:0900800002006B0002006B00029B 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Index: tools/fx2/bin/nexys2_jtag_3fifo_ic.ihx =================================================================== --- tools/fx2/bin/nexys2_jtag_3fifo_ic.ihx (nonexistent) +++ tools/fx2/bin/nexys2_jtag_3fifo_ic.ihx (revision 17) @@ -0,0 +1,446 @@ +:06000000020E0702006B76 +:03000B0002006B85 +:0300130002006B7D +:03001B0002006B75 +:0300230002006B6D +:03002B0002006B65 +:0300330002006B5D +:03003B0002006B55 +:0300430002006B4D +:03004B0002006B45 +:0300530002006B3D +:03005B0002006B35 +:0300630002006B2D +:01006B003262 +:0900800002006B0002006B00029B +:08008900006B0002006B000295 +:08009100006B0002006B00028D +:08009900006B0002006B000285 +:0800A100006B0002006B00027D +:0800A900006B0002006B000275 +:0700B100006B0002006B0070 +:0901000002006B0002006B00021A +:08010900006B0002006B000214 +:08011100006B0002006B00020C +:08011900006B0002006B000204 +:08012100006B0002006B0002FC +:08012900006B0002006B0002F4 +:08013100006B0002006B0002EC +:08013900006B0002006B0002E4 +:08014100006B0002006B0002DC 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+:0E0C0300091CAA82AB83E0FC4304018A828BA9 +:050C110083ECF0800DF2 +:050C16001207BC80087C +:050C1B001207BC80037C +:030C20001207BCFC +:080C230090E6A0E04480F022FD +:050C2B00AA82BA0300DB +:070C30004005EA249C50017D +:010C3700229A +:090C3800740F5AFBBB0302800794 +:070C4100740F5AFBBB0B45C9 +:0A0C4800A2AF9203C2AFEA2400F548 +:0C0C520082E43400F5837402F07B00742F +:0C0C5E00012AFCE43BFDEC2400F582EDD3 +:0A0C6A003400F583E51DFCF0740270 +:0C0C74002AFAE43BFBEA2400F582EB3492 +:0A0C800000F583AA1C7B00EAF0A235 +:030C8A000392AF23 +:010C8D002244 +:080C8E00E582FA2483500122E3 +:060C9600EA540360012294 +:0A0C9C00A2AF9204C2AFEA2400F5F3 +:0C0CA60082E43401F5837402F07B0074DA +:0C0CB200012AFCE43BFDEC2400F582ED7F +:0A0CBE003401F583E51DF074022AED +:0B0CC800FAE43BFBEA2400F582EB3469 +:080CD30001F583AA1CEAF0A25E +:040CDB000492AF22AE +:050CDF00AA82BA8000AA +:070CE4004005EA244B50011A +:010CEB0022E6 +:060CEC00EA54036001223E +:0A0CF200A2AF9205C2AFEA2480F51C +:0C0CFC0082E43400F5837402F07B007485 +:0C0D0800012AFCE43BFDEC2480F582EDA8 +:0A0D14003400F583E51DF074022A97 +:0B0D1E00FAE43BFBEA2480F582EB3492 +:080D290000F583AA1CEAF0A208 +:040D31000592AF2256 +:080D3500C2E8C2EA751C00755A +:060D3D001D017582431246 +:040D43000C2B751CE4 +:030D470080751D97 +:0C0D4A0000758253120C2B0090E650E460 +:0E0D5600F00090E652E4F00090E654E4F00065 +:0E0D640090E656E4F00090E65174FFF0009027 +:0E0D7200E65374FFF00090E65574FFF0009019 +:0E0D8000E65774FFF00090E658E4F090E65954 +:0E0D8E0074FFF090E65AE4F090E65B74FFF01C +:0E0D9C0090E65CE4F090E65D74FFF090E65E99 +:0E0DAA00E4F090E65F74FFF00090E660E4F085 +:0D0DB8000090E66174FFF090E662E4F090B8 +:0E0DC500E66374FFF090E665E4F090E6687473 +:0A0DD3000BF05391AFD2E8D2EA22F0 +:010DDD0022F3 +:020DDE00AA82E7 +:060DE000120DDDDAFB221A +:030DE60090FB502F +:080DE900A3E582458370F922A5 +:040DF100AA82AB83A4 +:080DF500120DE61ABAFF011B02 +:050DFD00EA4B70F42236 +:030E1000758121C8 +:0A0E13001205D5E5826003020E0B04 +:00000001FF Index: tools/fx2/bin =================================================================== --- tools/fx2/bin (nonexistent) +++ tools/fx2/bin (revision 17)
tools/fx2/bin Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: tools/fx2/sys/99-retro-usb-permissions.rules =================================================================== --- tools/fx2/sys/99-retro-usb-permissions.rules (nonexistent) +++ tools/fx2/sys/99-retro-usb-permissions.rules (revision 17) @@ -0,0 +1,26 @@ +# $Id: 99-retro-usb-permissions.rules 467 2013-01-02 19:49:05Z mueller $ +# +# udev rules to make some USB adaptors writable to group plugdev +# +# copy into /etc/udev/rules.d +# +ACTION!="add", GOTO="special_usb_rules_end" +SUBSYSTEM!="usb", GOTO="special_usb_rules_end" +# +# Cypress FX2 based systems ------------------------------------------ +# - Digilent Nexys2 +ATTR{idVendor}=="1443", ATTR{idProduct}=="0005", MODE="660", GROUP="plugdev" +# - Digilent Nexys3 and Atlys +ATTR{idVendor}=="1443", ATTR{idProduct}=="0007", MODE="660", GROUP="plugdev" +# +# - Cypress - EZ-USB FX2 USB 2.0 default +ATTR{idVendor}=="04b4", ATTR{idProduct}=="8613", MODE="660", GROUP="plugdev" +# +# - ixo.de - USB-JTAG-IF (used by ixo_jtag firmware) +ATTR{idVendor}=="16c0", ATTR{idProduct}=="06ad", MODE="660", GROUP="plugdev" +# - VOTI - free for internal lab use 1007 (used by retro11 firmware; primary) +ATTR{idVendor}=="16c0", ATTR{idProduct}=="03ef", MODE="660", GROUP="plugdev" +# - VOTI - free for internal lab use 1008 (used by retro11 firmware; alternate) +ATTR{idVendor}=="16c0", ATTR{idProduct}=="03f0", MODE="660", GROUP="plugdev" +# +LABEL="special_usb_rules_end" Index: tools/fx2/sys/README.txt =================================================================== --- tools/fx2/sys/README.txt (nonexistent) +++ tools/fx2/sys/README.txt (revision 17) @@ -0,0 +1,17 @@ +# $Id: README.txt 446 2011-12-29 23:27:48Z mueller $ + +to setup udev rules do + + sudo cp -a 99-retro-usb-permissions.rules /etc/udev/rules.d/ + sudo chown root:root /etc/udev/rules.d/99-retro-usb-permissions.rules + dir /etc/udev/rules.d/ + + sudo udevadm control --reload-rules + +to verify whether usb device was really put into group 'plugdev' + + lsusb + --> look for bus/dev of interest + + find /dev/bus/usb -type c | sort| xargs ls -l + --> check whether bus/dev of interest is in group plugdev Index: tools/fx2/sys =================================================================== --- tools/fx2/sys (nonexistent) +++ tools/fx2/sys (revision 17)
tools/fx2/sys Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: tools/fx2 =================================================================== --- tools/fx2 (nonexistent) +++ tools/fx2 (revision 17)
tools/fx2 Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: tools/tcl/rbbram/perf.tcl =================================================================== --- tools/tcl/rbbram/perf.tcl (revision 16) +++ tools/tcl/rbbram/perf.tcl (revision 17) @@ -1,6 +1,6 @@ -# $Id: perf.tcl 376 2011-04-17 12:24:07Z mueller $ +# $Id: perf.tcl 465 2012-12-27 21:29:38Z mueller $ # -# Copyright 2011- by Walter F.J. Mueller +# Copyright 2011-2012 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2012-12-27 495 1.0.1 adopt format, cover small ms and large kb # 2011-04-17 376 1.0 Initial version # @@ -135,7 +136,16 @@ foreach {nr i trun} $pval { set ms [expr double($trun) / double($nr*$i)] set kb [expr double(2*$nr*$i*$nblk) / double($trun)] - append oline [format " %5.1f %5.1f" $ms $kb] + if { $ms < 9.94 } { + append oline [format " %5.2f" $ms] + } else { + append oline [format " %5.1f" $ms] + } + if { $kb > 999.9 } { + append oline [format " %5.0f" $kb] + } else { + append oline [format " %5.1f" $kb] + } } append rval $oline
/tools/tcl/setup_packages
1,5 → 1,5
#! /usr/bin/env tclsh
# $Id: setup_packages 431 2011-11-21 17:56:37Z mueller $
# $Id: setup_packages 445 2011-12-26 21:19:26Z mueller $
#
pkg_mkIndex -verbose ../lib libr*tpp.so
#
11,5 → 11,4
pkg_mkIndex -verbose rbs3hio *.tcl
pkg_mkIndex -verbose rbemon *.tcl
#
#
pkg_mkIndex -verbose tst_rlink *.tcl
pkg_mkIndex -verbose tst_rlink *.tcl
/tools/src/librlink/RlinkPort.cpp
1,4 → 1,4
// $Id: RlinkPort.cpp 375 2011-04-02 07:56:47Z mueller $
// $Id: RlinkPort.cpp 466 2012-12-30 13:26:55Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
13,6 → 13,8
//
// Revision History:
// Date Rev Version Comment
// 2012-12-28 466 1.0.2 allow Close() even when not open
// 2012-12-26 465 1.0.1 add CloseFd() method
// 2011-03-27 375 1.0 Initial version
// 2011-01-15 356 0.1 First draft
// ---------------------------------------------------------------------------
19,7 → 21,7
 
/*!
\file
\version $Id: RlinkPort.cpp 375 2011-04-02 07:56:47Z mueller $
\version $Id: RlinkPort.cpp 466 2012-12-30 13:26:55Z mueller $
\brief Implemenation of RlinkPort.
*/
 
78,14 → 80,12
 
void RlinkPort::Close()
{
if (! IsOpen())
throw logic_error("RlinkPort::Close(): port not open");
if (!IsOpen()) return;
 
close(fFdRead);
if (fFdWrite != fFdRead) close(fFdWrite);
if (fFdWrite == fFdRead) fFdWrite = -1;
CloseFd(fFdWrite);
CloseFd(fFdRead);
 
fFdRead = -1;
fFdWrite = -1;
fIsOpen = false;
fUrl.clear();
fScheme.clear();
338,7 → 338,7
 
return true;
}
 
//
//------------------------------------------+-----------------------------------
//! FIXME_docs
 
359,6 → 359,18
}
 
//------------------------------------------+-----------------------------------
//! FIXME_docs
 
void RlinkPort::CloseFd(int& fd)
{
if (fd >= 0) {
close(fd);
fd = -1;
}
return;
}
 
//------------------------------------------+-----------------------------------
#if (defined(Retro_NoInline) || defined(Retro_RlinkPort_NoInline))
#define inline
#include "RlinkPort.ipp"
/tools/src/librlink/RlinkPortFifo.cpp
1,4 → 1,4
// $Id: RlinkPortFifo.cpp 375 2011-04-02 07:56:47Z mueller $
// $Id: RlinkPortFifo.cpp 466 2012-12-30 13:26:55Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
19,7 → 19,7
 
/*!
\file
\version $Id: RlinkPortFifo.cpp 375 2011-04-02 07:56:47Z mueller $
\version $Id: RlinkPortFifo.cpp 466 2012-12-30 13:26:55Z mueller $
\brief Implemenation of RlinkPortFifo.
*/
 
49,7 → 49,10
//! Destructor
 
RlinkPortFifo::~RlinkPortFifo()
{}
{
// no need to call Close() here, no RlinkPortFifo::Close()
// cleanup will be done by ~RlinkPort()
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
/tools/src/librlink/RlinkPort.hpp
1,4 → 1,4
// $Id: RlinkPort.hpp 380 2011-04-25 18:14:52Z mueller $
// $Id: RlinkPort.hpp 465 2012-12-27 21:29:38Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
13,6 → 13,7
//
// Revision History:
// Date Rev Version Comment
// 2012-12-26 465 1.0.2 add CloseFd() method
// 2011-04-24 380 1.0.1 use boost::noncopyable (instead of private dcl's)
// 2011-03-27 375 1.0 Initial version
// 2011-01-15 356 0.1 First draft
21,7 → 22,7
 
/*!
\file
\version $Id: RlinkPort.hpp 380 2011-04-25 18:14:52Z mueller $
\version $Id: RlinkPort.hpp 465 2012-12-27 21:29:38Z mueller $
\brief Declaration of class RlinkPort.
*/
 
97,6 → 98,7
bool AddOpt(const std::string& key, const std::string& val,
bool hasval, const std::string& optlist,
RerrMsg& emsg);
void CloseFd(int& fd);
 
protected:
bool fIsOpen; //!< is open flag
/tools/src/librlink/Makefile
1,4 → 1,4
# $Id: Makefile 403 2011-08-06 17:36:22Z mueller $
# $Id: Makefile 465 2012-12-27 21:29:38Z mueller $
#
# Revision History:
# Date Rev Version Comment
16,7 → 16,7
# Compile and Link search paths
#
INCLFLAGS = -I${RETROBASE}/tools/src -I${BOOSTINC}
LDLIBS = -lboost_thread -L${RETROBASE}/tools/lib -lrtools
LDLIBS = -lboost_thread -lusb-1.0 -L${RETROBASE}/tools/lib -lrtools
#
# Object files to be included
#
24,7 → 24,8
RlinkCommand.o RlinkCommandExpect.o RlinkCommandList.o \
RlinkConnect.o \
RlinkCrc8.o RlinkPacketBuf.o \
RlinkPort.o RlinkPortFactory.o RlinkPortFifo.o RlinkPortTerm.o
RlinkPort.o RlinkPortFactory.o \
RlinkPortFifo.o RlinkPortTerm.o RlinkPortCuff.o
#
DEP_all = $(OBJ_all:.o=.dep)
#
/tools/src/librlink/RlinkPortFactory.cpp
1,6 → 1,6
// $Id: RlinkPortFactory.cpp 375 2011-04-02 07:56:47Z mueller $
// $Id: RlinkPortFactory.cpp 465 2012-12-27 21:29:38Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
// Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
// This program is free software; you may redistribute and/or modify it under
// the terms of the GNU General Public License as published by the Free
13,6 → 13,7
//
// Revision History:
// Date Rev Version Comment
// 2012-12-26 465 1.1 add cuff: support
// 2011-03-27 374 1.0 Initial version
// 2011-01-15 356 0.1 First draft
// ---------------------------------------------------------------------------
19,7 → 20,7
 
/*!
\file
\version $Id: RlinkPortFactory.cpp 375 2011-04-02 07:56:47Z mueller $
\version $Id: RlinkPortFactory.cpp 465 2012-12-27 21:29:38Z mueller $
\brief Implemenation of RlinkPortFactory.
*/
 
26,6 → 27,7
#include "RlinkPortFactory.hpp"
#include "RlinkPortFifo.hpp"
#include "RlinkPortTerm.hpp"
#include "RlinkPortCuff.hpp"
 
using namespace std;
using namespace Retro;
53,6 → 55,8
return new RlinkPortFifo();
} else if (scheme == "term") {
return new RlinkPortTerm();
} else if (scheme == "cuff") {
return new RlinkPortCuff();
}
emsg.Init("RlinkPortFactory::New()", string("unknown scheme: ") + scheme);
/tools/src/librlink/RlinkPortTerm.cpp
1,4 → 1,4
// $Id: RlinkPortTerm.cpp 440 2011-12-18 20:08:09Z mueller $
// $Id: RlinkPortTerm.cpp 466 2012-12-30 13:26:55Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
24,7 → 24,7
 
/*!
\file
\version $Id: RlinkPortTerm.cpp 440 2011-12-18 20:08:09Z mueller $
\version $Id: RlinkPortTerm.cpp 466 2012-12-30 13:26:55Z mueller $
\brief Implemenation of RlinkPortTerm.
*/
 
263,13 → 263,14
 
void RlinkPortTerm::Close()
{
if (fIsOpen) {
if (fFdWrite >= 0) {
tcflush(fFdWrite, TCIOFLUSH);
tcsetattr(fFdWrite, TCSANOW, &fTiosOld);
}
RlinkPort::Close();
if (!IsOpen()) return;
 
if (fFdWrite >= 0) {
tcflush(fFdWrite, TCIOFLUSH);
tcsetattr(fFdWrite, TCSANOW, &fTiosOld);
}
RlinkPort::Close();
 
return;
}
284,7 → 285,7
uint8_t* po = buf;
if (fRxBuf.size() < size) fRxBuf.resize(size);
 
// repeat read untill at least one byte returned (or an error occurs)
// repeat read until at least one byte returned (or an error occurs)
// this avoids that the Read() returns with 0 in case only one byte is
// seen and this is a kc_xesc. At most two iterations possible because
// in 2nd iteration fPendXesc must be set and thus po pushed.
/tools/src/librlink/RlinkPortCuff.cpp
0,0 → 1,701
// $Id: RlinkPortCuff.cpp 467 2013-01-02 19:49:05Z mueller $
//
// Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
// This program is free software; you may redistribute and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation, either version 2, or at your option any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for complete details.
//
// Revision History:
// Date Rev Version Comment
// 2013-01-02 467 1.0.1 get cleanup code right; add USBErrorName()
// 2012-12-26 465 1.0 Initial version
// ---------------------------------------------------------------------------
 
/*!
\file
\version $Id: RlinkPortCuff.cpp 467 2013-01-02 19:49:05Z mueller $
\brief Implemenation of RlinkPortCuff.
*/
 
#include <errno.h>
#include <unistd.h>
#include <sys/time.h>
#include <time.h>
#include <stdio.h>
 
#include <stdexcept>
 
#include "RlinkPortCuff.hpp"
 
using namespace std;
using namespace Retro;
 
/*!
\class Retro::RlinkPortCuff
\brief FIXME_text
*/
 
//------------------------------------------+-----------------------------------
//! Default constructor
 
RlinkPortCuff::RlinkPortCuff()
: RlinkPort(),
fFdReadDriver(-1),
fFdWriteDriver(-1),
fpUsbContext(0),
fpUsbDevList(0),
fUsbDevCount(0),
fpUsbDevHdl(0),
fLoopState(kLoopStateStopped)
{
fStats.Define(kStatNPollAddCB, "kStatNPollAddCB", "USB poll add cb");
fStats.Define(kStatNPollRemoveCB, "kStatNPollRemoveCB", "USB poll remove cb");
fStats.Define(kStatNUSBWrite, "kStatNUSBWrite", "USB write done");
fStats.Define(kStatNUSBRead, "kStatNUSBRead", "USB read done");
}
 
//------------------------------------------+-----------------------------------
//! Destructor
 
RlinkPortCuff::~RlinkPortCuff()
{
if (IsOpen()) RlinkPortCuff::Close();
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
bool RlinkPortCuff::Open(const std::string& url, RerrMsg& emsg)
{
int irc;
 
if (IsOpen()) Close();
 
if (!ParseUrl(url, "|trace|", emsg)) return false;
 
// initialize USB context
irc = libusb_init(&fpUsbContext);
if (irc != 0) {
emsg.Init("RlinkPortCuff::Open()",
string("libusb_init() failed: ") +
string(USBErrorName(irc)));
Cleanup();
return false;
}
// setup libusb level debug
libusb_set_debug(fpUsbContext, 3); // info->stdout, warn+err->stderr
 
// check for internal timeout handling support
if (libusb_pollfds_handle_timeouts(fpUsbContext) == 0) {
emsg.Init("RlinkPortCuff::Open()",
string("libusb_pollfds_handle_timeouts == 0 : "
"this program will not run on this legacy system"));
Cleanup();
return false;
}
 
// get USB device list
fUsbDevCount = libusb_get_device_list(fpUsbContext, &fpUsbDevList);
 
// determine USB path name
if (fPath.length() == 0) {
char* env_vid = getenv("RETRO_FX2_VID");
char* env_pid = getenv("RETRO_FX2_PID");
if (env_vid && strlen(env_vid) == 4 &&
env_pid && strlen(env_pid) == 4) {
fPath = env_vid;
fPath += ":";
fPath += env_pid;
} else {
emsg.Init("RlinkPortCuff::Open()",
string("RETRO_FX2_VID/PID not or ill defined"));
Cleanup();
return false;
}
}
 
// connect to USB device
libusb_device* mydev = 0;
// path syntax: /bus/dev
if (fPath.length()==8 && fPath[0]=='/' && fPath[4]=='/') {
string busnam = fPath.substr(1,3);
string devnam = fPath.substr(5,3);
char* endptr;
uint8_t busnum = strtol(busnam.c_str(), &endptr, 10);
uint8_t devnum = strtol(devnam.c_str(), &endptr, 10);
for (ssize_t idev=0; idev<fUsbDevCount; idev++) {
libusb_device* udev = fpUsbDevList[idev];
if (libusb_get_bus_number(udev) == busnum &&
libusb_get_device_address(udev) == devnum) {
mydev = udev;
}
}
// path syntax: vend:prod
} else if (fPath.length()==9 && fPath[4]==':') {
string vennam = fPath.substr(0,4);
string pronam = fPath.substr(5,4);
char* endptr;
uint16_t vennum = strtol(vennam.c_str(), &endptr, 16);
uint16_t pronum = strtol(pronam.c_str(), &endptr, 16);
for (ssize_t idev=0; idev<fUsbDevCount; idev++) {
libusb_device* udev = fpUsbDevList[idev];
libusb_device_descriptor devdsc;
libusb_get_device_descriptor(udev, &devdsc);
if (devdsc.idVendor==vennum && devdsc.idProduct==pronum) {
mydev = udev;
}
}
} else {
emsg.Init("RlinkPortCuff::Open()",
string("invalid usb path '") + fPath +
"', not '/bus/dev' or 'vend:prod'");
Cleanup();
return false;
}
if (mydev == 0) {
emsg.Init("RlinkPortCuff::Open()",
string("no usb device '") + fPath + "', found'");
Cleanup();
return false;
}
 
irc = libusb_open(mydev, &fpUsbDevHdl);
if (irc) {
fpUsbDevHdl = 0;
emsg.Init("RlinkPortCuff::Open()",
string("opening usb device '") + fPath + "', failed: " +
string(USBErrorName(irc)));
Cleanup();
return false;
}
if (TraceOn()) cout << "libusb_open ok for '" << fPath << "'" << endl;
 
// claim USB device
irc = libusb_claim_interface(fpUsbDevHdl, 0);
if (irc) {
emsg.Init("RlinkPortCuff::Open()",
string("failed to claim '") + fPath + "': " +
string(USBErrorName(irc)));
Cleanup();
return false;
}
 
// setup write pipe
if (!OpenPipe(fFdWriteDriver, fFdWrite, emsg)) {
Cleanup();
return false;
}
// setup read pipe
if (!OpenPipe(fFdRead, fFdReadDriver, emsg)) {
Cleanup();
return false;
}
 
// setup pollfd list
fPollFds.clear();
 
// 1. write pipe allert (is always 1st in list)
PollfdAdd(fFdWriteDriver, POLLIN);
// 2. libusb callbacks
const libusb_pollfd** plist = libusb_get_pollfds(fpUsbContext);
for (const libusb_pollfd** p = plist; *p !=0; p++) {
PollfdAdd((*p)->fd, (*p)->events);
}
free(plist);
libusb_set_pollfd_notifiers(fpUsbContext, ThunkPollfdAdd,
ThunkPollfdRemove, this);
 
fDriverThread = boost::thread(boost::bind(&RlinkPortCuff::Driver, this));
 
fIsOpen = true;
 
return true;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
void RlinkPortCuff::Close()
{
if (!IsOpen()) return;
 
if (TraceOn()) cout << "Close() started" << endl;
Cleanup();
RlinkPort::Close();
 
if (TraceOn()) cout << "Close() ended" << endl;
return;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
void RlinkPortCuff::Cleanup()
{
// close write pipe from user side -> causes event in driver and driver stop
CloseFd(fFdWrite);
// wait till driver thread terminates
// use timed join, throw in case driver doesn't stop
if (fDriverThread.get_id() != boost::thread::id()) {
if (!fDriverThread.timed_join(boost::posix_time::milliseconds(500))) {
throw runtime_error("RlinkPortCuff::Cleanup(): "
"driver thread failed to stop");
}
}
 
// cleanup pipes
CloseFd(fFdRead);
CloseFd(fFdReadDriver);
CloseFd(fFdWriteDriver);
 
// cleanup USB context
if (fpUsbContext) {
if (fpUsbDevHdl) {
libusb_release_interface(fpUsbDevHdl, 0);
libusb_close(fpUsbDevHdl);
fpUsbDevHdl = 0;
}
if (fpUsbDevList) {
libusb_free_device_list(fpUsbDevList, 1);
fpUsbDevList = 0;
}
libusb_set_pollfd_notifiers(fpUsbContext, NULL, NULL, NULL);
libusb_exit(fpUsbContext);
fpUsbContext = 0;
}
 
fPollFds.clear();
return;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
bool RlinkPortCuff::OpenPipe(int& fdread, int& fdwrite, RerrMsg& emsg)
{
int irc;
int pipefd[2];
 
irc = pipe(pipefd);
if (irc < 0) {
emsg.InitErrno("RlinkPortCuff::OpenPipe()",
string("pipe() failed: "),
errno);
return false;
}
fdread = pipefd[0];
fdwrite = pipefd[1];
 
return true;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
// executed in separate boost thread !!
void RlinkPortCuff::Driver()
{
try {
 
// setup USB read-ahead queue
for (size_t nr=0; nr<kUSBReadQueue; nr++) {
libusb_transfer* t = libusb_alloc_transfer(0);
t->dev_handle = fpUsbDevHdl;
t->flags = LIBUSB_TRANSFER_FREE_BUFFER;
t->endpoint = (unsigned char) (kUSBReadEP|0x80);
t->type = LIBUSB_TRANSFER_TYPE_BULK;
t->timeout = 0;
t->status = LIBUSB_TRANSFER_COMPLETED;
t->buffer = (unsigned char*) malloc(kUSBBufferSize);
t->length = kUSBBufferSize;
t->actual_length = 0;
t->callback = ThunkUSBReadDone;
t->user_data = this;
int irc = libusb_submit_transfer(t);
if (irc) BadUSBCall("RlinkPortCuff::Driver()",
"libusb_submit_transfer()", irc);
fReadQueuePending.push_back(t);
}
 
// event loop
if (TraceOn()) cout << "event loop started" << endl;
fLoopState = kLoopStateRunning;
while(fLoopState == kLoopStateRunning) {
int irc = poll(fPollFds.data(), fPollFds.size(), 1000);
if (irc==-1 && errno==EINTR) continue;
if (irc!=0 && TraceOn()) {
cout << "poll() -> " << irc << " :";
for (size_t i=0; i<fPollFds.size(); i++)
if (fPollFds[i].revents) cout << " (" << fPollFds[i].fd << ","
<< fPollFds[i].events << ","
<< fPollFds[i].revents << ")";
cout << endl;
}
if (irc < 0) BadSysCall("RlinkPortCuff::Driver()", "poll()", irc);
if (fPollFds[0].revents & POLLHUP) { // write pipe close event
fLoopState = kLoopStateStopping;
} else if (fPollFds[0].revents & POLLIN) { // write pipe data event
DriverEventWritePipe();
} else { // assume USB timeout events
DriverEventUSB();
}
}
if (TraceOn()) cout << "event loop ended, cleanup started" << endl;
 
for (size_t i=0; i<fWriteQueuePending.size(); i++) {
libusb_cancel_transfer(fWriteQueuePending[i]);
}
for (size_t i=0; i<fReadQueuePending.size(); i++) {
libusb_cancel_transfer(fReadQueuePending[i]);
}
 
while(fLoopState == kLoopStateStopping &&
fWriteQueuePending.size() + fReadQueuePending.size() > 0) {
int irc = poll(fPollFds.data()+1, fPollFds.size()-1, 1000);
if (irc==-1 && errno==EINTR) continue;
if (irc==0) break;
if (irc < 0) BadSysCall("RlinkPortCuff::Driver()", "poll()", irc);
DriverEventUSB();
}
if (fWriteQueuePending.size() + fReadQueuePending.size())
throw runtime_error("RlinkPortCuff::Driver(): cleanup timeout");
 
fLoopState = kLoopStateStopped;
if (TraceOn()) cout << "cleanup ended" << endl;
 
} catch (exception& e) {
cout << "exception caught in RlinkPortCuff::Driver(): '" << e.what()
<< "'" << endl;
// close read pipe at driver end -> that causes main thread to respond
close(fFdReadDriver);
fFdReadDriver = -1;
}
 
return;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
void RlinkPortCuff::DriverEventWritePipe()
{
libusb_transfer* t = NewWriteTransfer();
 
ssize_t ircs = read(fFdWriteDriver, t->buffer, kUSBBufferSize);
if (TraceOn()) cout << "write pipe read() -> " << ircs << endl;
if (ircs < 0) BadSysCall("RlinkPortCuff::DriverEventWritePipe()",
"read()", ircs);
 
// pipe closed... end driver event loop
if (ircs == 0) {
fLoopState = kLoopStateStopping;
return;
}
 
t->length = (int) ircs;
int irc = libusb_submit_transfer(t);
if (irc) BadUSBCall("RlinkPortCuff::DriverEventWritePipe()",
"libusb_submit_transfer()", irc);
fWriteQueuePending.push_back(t);
 
return;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
void RlinkPortCuff::DriverEventUSB()
{
struct timeval tv;
tv.tv_sec = 0;
tv.tv_usec = 0;
int irc = libusb_handle_events_timeout(fpUsbContext, &tv);
//setting the timeval pointer to NULL should work, but doesn't (in 1.0.6)
//rc = libusb_handle_events_timeout(pUsbContext, 0);
if (irc) BadUSBCall("RlinkPortCuff::DriverEventUSB()",
"libusb_handle_events_timeout()", irc);
return;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
libusb_transfer* RlinkPortCuff::NewWriteTransfer()
{
libusb_transfer* t = 0;
if (!fWriteQueueFree.empty()) {
t = fWriteQueueFree.front();
fWriteQueueFree.pop_front();
} else {
t = libusb_alloc_transfer(0);
t->dev_handle = fpUsbDevHdl;
t->flags = LIBUSB_TRANSFER_FREE_BUFFER;
t->endpoint = (unsigned char) (kUSBWriteEP);
t->type = LIBUSB_TRANSFER_TYPE_BULK;
t->timeout = 1000;
t->buffer = (unsigned char*) malloc(kUSBBufferSize);
t->callback = ThunkUSBWriteDone;
t->user_data = this;
}
 
t->status = LIBUSB_TRANSFER_COMPLETED;
t->length = 0;
t->actual_length = 0;
 
return t;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
bool RlinkPortCuff::TraceOn()
{
if (!UrlFindOpt("trace")) return false;
struct timeval tv;
struct timezone tz;
struct tm tmval;
 
gettimeofday(&tv, &tz);
localtime_r(&tv.tv_sec, &tmval);
char buf[20];
snprintf(buf, 20, "%02d:%02d:%02d.%06d: ",
tmval.tm_hour, tmval.tm_min, tmval.tm_sec, (int) tv.tv_usec);
cout << buf;
return true;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
void RlinkPortCuff::BadSysCall(const char* meth, const char* text, int rc)
{
char buf[1024];
snprintf(buf, 1024, "%s : %s failed with rc=%d errno=%d: %s",
meth, text, rc, errno, strerror(errno));
throw runtime_error(buf);
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
void RlinkPortCuff::BadUSBCall(const char* meth, const char* text, int rc)
{
char buf[1024];
snprintf(buf, 1024, "%s : %s failed with rc=%d: %s",
meth, text, rc, USBErrorName(rc));
throw runtime_error(buf);
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
void RlinkPortCuff::CheckUSBTransfer(const char* meth, libusb_transfer *t)
{
const char* etext = 0;
if (t->status == LIBUSB_TRANSFER_ERROR) etext = "ERROR";
if (t->status == LIBUSB_TRANSFER_STALL) etext = "STALL";
if (t->status == LIBUSB_TRANSFER_NO_DEVICE) etext = "NO_DEVICE";
if (t->status == LIBUSB_TRANSFER_OVERFLOW) etext = "OVERFLOW";
 
if (etext == 0) return;
 
char buf[1024];
snprintf(buf, 1024, "%s : transfer failure on ep=%d: %s",
meth, (int)(t->endpoint&(~0x80)), etext);
throw runtime_error(buf);
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
const char* RlinkPortCuff::USBErrorName(int rc)
{
// Code taken verbatim from libusb-1.0.9.tar.bz2 function libusb_error_name
// The libusb_error_name() function was added rather late in V1.0.9.
// To allow usage with V1.0.8 and earlier this function is include here
switch (rc) {
case LIBUSB_SUCCESS:
return "LIBUSB_SUCCESS";
case LIBUSB_ERROR_IO:
return "LIBUSB_ERROR_IO";
case LIBUSB_ERROR_INVALID_PARAM:
return "LIBUSB_ERROR_INVALID_PARAM";
case LIBUSB_ERROR_ACCESS:
return "LIBUSB_ERROR_ACCESS";
case LIBUSB_ERROR_NO_DEVICE:
return "LIBUSB_ERROR_NO_DEVICE";
case LIBUSB_ERROR_NOT_FOUND:
return "LIBUSB_ERROR_NOT_FOUND";
case LIBUSB_ERROR_BUSY:
return "LIBUSB_ERROR_BUSY";
case LIBUSB_ERROR_TIMEOUT:
return "LIBUSB_ERROR_TIMEOUT";
case LIBUSB_ERROR_OVERFLOW:
return "LIBUSB_ERROR_OVERFLOW";
case LIBUSB_ERROR_PIPE:
return "LIBUSB_ERROR_PIPE";
case LIBUSB_ERROR_INTERRUPTED:
return "LIBUSB_ERROR_INTERRUPTED";
case LIBUSB_ERROR_NO_MEM:
return "LIBUSB_ERROR_NO_MEM";
case LIBUSB_ERROR_NOT_SUPPORTED:
return "LIBUSB_ERROR_NOT_SUPPORTED";
case LIBUSB_ERROR_OTHER:
return "LIBUSB_ERROR_OTHER";
}
return "**UNKNOWN**";
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
void RlinkPortCuff::PollfdAdd(int fd, short events)
{
fStats.Inc(kStatNPollAddCB);
pollfd pfd;
pfd.fd = fd;
pfd.events = events;
pfd.revents = 0;
fPollFds.push_back(pfd);
return;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
void RlinkPortCuff::PollfdRemove(int fd)
{
fStats.Inc(kStatNPollRemoveCB);
for (size_t i=0; i<fPollFds.size(); ) {
if (fPollFds[i].fd == fd) {
fPollFds.erase(fPollFds.begin()+i);
} else {
i++;
}
}
return;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
void RlinkPortCuff::USBWriteDone(libusb_transfer* t)
{
if (TraceOn()) cout << "USB write done -> " << t->actual_length << endl;
 
if (fWriteQueuePending.size() && t == fWriteQueuePending.front())
fWriteQueuePending.pop_front();
else
throw logic_error("RlinkPortCuff::USBWriteDone: "
"fWriteQueuePending disordered");
 
if (fLoopState == kLoopStateRunning) {
CheckUSBTransfer("RlinkPortCuff::USBWriteDone()", t);
fStats.Inc(kStatNUSBWrite);
fWriteQueueFree.push_back(t);
 
} else {
libusb_free_transfer(t);
}
return;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
void RlinkPortCuff::USBReadDone(libusb_transfer* t)
{
if (TraceOn()) cout << "USB read done -> " << t->actual_length << endl;
 
if (fReadQueuePending.size() && t == fReadQueuePending.front())
fReadQueuePending.pop_front();
else
throw logic_error("RlinkPortCuff::USBReadDone: "
"fReadQueuePending disordered");
 
if (fLoopState == kLoopStateRunning) {
CheckUSBTransfer("RlinkPortCuff::USBReadDone()", t);
fStats.Inc(kStatNUSBRead);
if (t->actual_length>0) {
ssize_t ircs = write(fFdReadDriver, t->buffer, (size_t) t->actual_length);
if (ircs < 0) BadSysCall("RlinkPortCuff::USBReadDone()",
"write()", ircs);
}
t->status = LIBUSB_TRANSFER_COMPLETED;
t->actual_length = 0;
int irc = libusb_submit_transfer(t);
if (irc) BadUSBCall("RlinkPortCuff::USBReadDone()",
"libusb_submit_transfer()", irc);
fReadQueuePending.push_back(t);
 
} else {
libusb_free_transfer(t);
}
return;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
void RlinkPortCuff::ThunkPollfdAdd(int fd, short events, void* udata)
{
RlinkPortCuff* pcntx = (RlinkPortCuff*) udata;
pcntx->PollfdAdd(fd, events);
return;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
void RlinkPortCuff::ThunkPollfdRemove(int fd, void* udata)
{
RlinkPortCuff* pcntx = (RlinkPortCuff*) udata;
pcntx->PollfdRemove(fd);
return;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
void RlinkPortCuff::ThunkUSBWriteDone(libusb_transfer* t)
{
RlinkPortCuff* pcntx = (RlinkPortCuff*) t->user_data;
pcntx->USBWriteDone(t);
return;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_text
 
void RlinkPortCuff::ThunkUSBReadDone(libusb_transfer* t)
{
RlinkPortCuff* pcntx = (RlinkPortCuff*) t->user_data;
pcntx->USBReadDone(t);
return;
}
 
//------------------------------------------+-----------------------------------
#if (defined(Retro_NoInline) || defined(Retro_RlinkPortCuff_NoInline))
#define inline
//#include "RlinkPortCuff.ipp"
#undef inline
#endif
/tools/src/librlink/RlinkPortCuff.hpp
0,0 → 1,116
// $Id: RlinkPortCuff.hpp 467 2013-01-02 19:49:05Z mueller $
//
// Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
// This program is free software; you may redistribute and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation, either version 2, or at your option any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for complete details.
//
// Revision History:
// Date Rev Version Comment
// 2013-01-02 467 1.0.1 get cleanup code right; add USBErrorName()
// 2012-12-26 465 1.0 Initial version
// ---------------------------------------------------------------------------
 
 
/*!
\file
\version $Id: RlinkPortCuff.hpp 467 2013-01-02 19:49:05Z mueller $
\brief Declaration of class RlinkPortCuff.
*/
 
#ifndef included_Retro_RlinkPortCuff
#define included_Retro_RlinkPortCuff 1
 
#include "RlinkPort.hpp"
 
#include <poll.h>
 
#include <vector>
#include "boost/thread.hpp"
#include <libusb-1.0/libusb.h>
 
namespace Retro {
 
class RlinkPortCuff : public RlinkPort {
public:
 
RlinkPortCuff();
virtual ~RlinkPortCuff();
 
virtual bool Open(const std::string& url, RerrMsg& emsg);
virtual void Close();
 
// some constants
static const size_t kUSBBufferSize = 4096; //!< USB buffer size
static const int kUSBWriteEP = 4 ; //!< USB write endpoint
static const int kUSBReadEP = 6 ; //!< USB read endpoint
static const size_t kUSBReadQueue = 2 ; //!< USB read queue length
 
// statistics counter indices
enum stats {
kStatNPollAddCB = RlinkPort::kDimStat,
kStatNPollRemoveCB,
kStatNUSBWrite,
kStatNUSBRead,
kDimStat
};
 
// event loop states
enum loopState {
kLoopStateStopped,
kLoopStateRunning,
kLoopStateStopping
};
 
protected:
int fFdReadDriver; //!< fd for read (driver end)
int fFdWriteDriver; //!< fd for write (driver end)
boost::thread fDriverThread; //!< driver thread
libusb_context* fpUsbContext;
libusb_device** fpUsbDevList;
ssize_t fUsbDevCount;
libusb_device_handle* fpUsbDevHdl;
loopState fLoopState;
std::vector<pollfd> fPollFds;
std::deque<libusb_transfer*> fWriteQueueFree;
std::deque<libusb_transfer*> fWriteQueuePending;
std::deque<libusb_transfer*> fReadQueuePending;
 
private:
void Cleanup();
bool OpenPipe(int& fdread, int& fdwrite, RerrMsg& emsg);
void Driver();
void DriverEventWritePipe();
void DriverEventUSB();
libusb_transfer* NewWriteTransfer();
bool TraceOn();
void BadSysCall(const char* meth, const char* text, int rc);
void BadUSBCall(const char* meth, const char* text, int rc);
void CheckUSBTransfer(const char* meth, libusb_transfer *t);
const char* USBErrorName(int rc);
 
void PollfdAdd(int fd, short events);
void PollfdRemove(int fd);
void USBWriteDone(libusb_transfer* t);
void USBReadDone(libusb_transfer* t);
 
static void ThunkPollfdAdd(int fd, short events, void* udata);
static void ThunkPollfdRemove(int fd, void* udata);
static void ThunkUSBWriteDone(libusb_transfer* t);
static void ThunkUSBReadDone(libusb_transfer* t);
 
};
} // end namespace Retro
 
#if !(defined(Retro_NoInline) || defined(Retro_RlinkPortCuff_NoInline))
//#include "RlinkPortCuff.ipp"
#endif
 
#endif
/tools/src/librlinktpp/Makefile
1,7 → 1,8
# $Id: Makefile 401 2011-07-31 21:02:33Z mueller $
# $Id: Makefile 464 2012-12-26 10:14:15Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-12-24 464 1.1.1 add TCLINC
# 2011-07-31 401 1.1 rename realclean->distclean
# 2011-07-01 386 1.0.2 add BOOSTINC
# 2011-03-20 372 1.0.1 renamed ..tcl -> ..tpp
16,7 → 17,7
#
# Compile and Link search paths
#
INCLFLAGS = -I/usr/include/tcl8.4 -I${RETROBASE}/tools/src -I${BOOSTINC}
INCLFLAGS = -I${RETROBASE}/tools/src -I${TCLINC} -I${BOOSTINC}
LDLIBS = -L${RETROBASE}/tools/lib -lrtools -lrtcltools -lrlink
#
# Object files to be included
/tools/src/librutiltpp/Makefile
1,7 → 1,8
# $Id: Makefile 401 2011-07-31 21:02:33Z mueller $
# $Id: Makefile 464 2012-12-26 10:14:15Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-12-24 464 1.1.1 add TCLINC
# 2011-07-31 401 1.1 rename realclean->distclean
# 2011-07-01 386 1.0.2 add BOOSTINC
# 2011-03-20 372 1.0.1 renamed ..tcl -> ..tpp
16,7 → 17,7
#
# Compile and Link search paths
#
INCLFLAGS = -I/usr/include/tcl8.4 -I${RETROBASE}/tools/src -I${BOOSTINC}
INCLFLAGS = -I${RETROBASE}/tools/src -I${TCLINC} -I${BOOSTINC}
LDLIBS = -L${RETROBASE}/tools/lib -lrtcltools
#
# Object files to be included
/tools/src/librtcltools/Makefile
1,7 → 1,8
# $Id: Makefile 401 2011-07-31 21:02:33Z mueller $
# $Id: Makefile 464 2012-12-26 10:14:15Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-12-24 464 1.1.1 add TCLINC
# 2011-07-31 401 1.1 rename realclean->distclean
# 2011-07-01 386 1.0.1 add BOOSTINC
# 2011-02-11 360 1.0 Initial version
15,7 → 16,7
#
# Compile and Link search paths
#
INCLFLAGS = -I/usr/include/tcl8.4 -I${RETROBASE}/tools/src -I${BOOSTINC}
INCLFLAGS = -I${RETROBASE}/tools/src -I${TCLINC} -I${BOOSTINC}
LDLIBS = -L${RETROBASE}/tools/lib -lrtools
#
# Object files to be included
/tools/bin/ti_rri
1,8 → 1,8
#! /usr/bin/env tclsh
# -*- tcl -*-
# $Id: ti_rri 440 2011-12-18 20:08:09Z mueller $
# $Id: ti_rri 467 2013-01-02 19:49:05Z mueller $
#
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
15,6 → 15,9
#
# Revision History:
# Date Rev Version Comment
# 2013-01-02 467 1.1.1 call rlc close only when really open
# 2012-12-27 465 1.1 add --cuff support
# 2012-02-09 457 1.0.4 disable autoexec
# 2011-12-19 440 1.0.3 re-organize option handling for --term and --fifo
# 2011-12-04 435 1.0.2 add flow attribute to --term
# 2011-04-22 379 1.0.1 check for RETROBASE; proper exit handling; help text
24,6 → 27,7
#
# --fifo[=name,opts,...]
# --term[=name,baud,opts,...]
# --cuff[=name,...]
# --run=command
# --log=filename ; default "-"
# --logl=n ; default 2
41,6 → 45,8
fifo_ ""
term 0
term_ ""
cuff 0
cuff_ ""
run_ ""
log_ "-"
logl_ 2
54,6 → 60,9
set optsendseen 0
set runpid {}
 
# disable autoexec
set auto_noexec 1
 
#
# cleanup handler
# must be in a proc so that it can be called from tclreadline
64,8 → 73,8
global runpid
 
# now close rlink connection
if { $opts(fifo) || $opts(term) } {
rlc close
if { $opts(fifo) || $opts(term) || $opts(cuff) } {
if { [rlc open] ne "" } { rlc close }
}
 
# FIXME_code: should sync here with -run process run-down
84,6 → 93,7
switch -regexp -- $arg {
^--?fifo=?.*$ { set opts(fifo) 1; regexp -- {=(.*)} $arg dummy opts(fifo_) }
^--?term=?.*$ { set opts(term) 1; regexp -- {=(.*)} $arg dummy opts(term_) }
^--?cuff=?.*$ { set opts(cuff) 1; regexp -- {=(.*)} $arg dummy opts(cuff_) }
^--?run=.+$ { regexp -- {=(.*)} $arg dummy opts(run_) }
^--?log=.+$ { regexp -- {=(.*)} $arg dummy opts(log_) }
^--?logl=.+$ { regexp -- {=(.*)} $arg dummy opts(logl_) }
107,7 → 117,7
puts { --run=CMD exec's CMD as subprocess before the rlink port opened}
puts { useful to start test benches, usually via 'tbw'}
puts { --fifo[=ARGS] open fifo type rlink port. Optional arguments are:}
puts { --fifo=[NAME[,KEEP]]}
puts { --fifo=[NAME[,OPTS]]}
puts { NAME fifo name prefix, default 'rlink_cext_fifo'}
puts { OPTS further options (comma separated list):}
puts { keep fifo is kept open on exit}
128,6 → 138,12
puts { break send a break, do autobaud}
puts { cts hardware flow control (cts/rts)}
puts { xon software flow control (xon/xoff)}
puts { --cuff[=ARGS] open cuff type rlink port. Optional arguments are:}
puts { --cuff=[NAME[,OPTS]]}
puts { NAME USB path, default derived from environment}
puts { variables RETRO_FX2_VID and RETRO_FX2_PID}
puts { OPTS further options (comma separated list):}
puts { trace trace USB activities}
puts { --log=FILE set log file name. Default is to write to stdout.}
puts { --logl=LVL set log level, default is '2' allowed values:}
puts { 0 no logging}
157,8 → 173,13
return 1
}
 
if { $opts(fifo) && $opts(term) } {
puts "-E: both --fifo and --term given, only one allowed"
set nopen 0;
if { $opts(fifo) } { incr nopen }
if { $opts(term) } { incr nopen }
if { $opts(cuff) } { incr nopen }
 
if { $nopen > 1 } {
puts "-E: more than one of --fifo,--term,--cuff given, only one allowed"
return 1
}
 
219,6 → 240,20
rlc open $url
}
 
# handle --cuff
if { $opts(cuff) } {
set nlist [split $opts(cuff_) ","]
set path [lindex $nlist 0]
set url "cuff:$path"
set delim "?"
foreach opt [lrange $nlist 1 end] {
if {$opt ne ""} {append url "$delim$opt"}
set delim ";"
}
# puts "-I: $url"
rlc open $url
}
 
# setup simulation mode default
set rlink::sim_mode [rlink::isfifo]
 
/tools/bin/vbomconv
1,7 → 1,7
#!/usr/bin/perl -w
# $Id: vbomconv 433 2011-11-27 22:04:39Z mueller $
# $Id: vbomconv 456 2012-02-05 22:19:44Z mueller $
#
# Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2007-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
14,6 → 14,8
#
# Revision History:
# Date Rev Version Comment
# 2012-02-05 456 1.9.4 redo filename substitution (= and :); add --get_top
# 2012-01-02 448 1.9.3 use in ghdl_m -fexplicit also when simprim used
# 2011-11-27 433 1.9.2 use in ghdl_m -fexplicit when unisim used
# 2011-08-13 405 1.9.1 always write 'vhdl' into xst prj files again; for
# -xst_export: remove opt file export, add ucf_cpp
61,6 → 63,7
"xst_export=s",
"ghdl_export=s",
"isim_export=s",
"get_top",
"flist") || exit 1;
 
sub print_help;
68,6 → 71,7
sub scan_vbom;
sub copy_edir;
sub write_vbomdep;
sub canon_fname;
 
my @vbom_list;
my @file_list;
74,7 → 78,7
my %vbom_tbl;
my %file_tbl;
my %read_tbl;
my %conf_tbl;
my %para_tbl;
my @ucf_cpp_list;
my $is_xst = 0; # XST synthesis target
my $is_ghdl = 0; # ghdl simulation target
196,9 → 200,9
 
if ($do_trace) {
print STDERR "\n";
print STDERR "configuration table:\n";
foreach (sort keys %conf_tbl) {
print STDERR " $_ = $conf_tbl{$_}\n";
print STDERR "filename substitution table:\n";
foreach (sort keys %para_tbl) {
print STDERR " $_ = $para_tbl{$_}\n";
}
print STDERR "final file_list:\n";
foreach (@file_list) {
225,10 → 229,10
my $rc = int($wrc/256);
if ($rc == 0) {
my $sig = $wrc % 256;
print STDERR "%vbomconv-I compilation aborted by signal $sig\n";
print STDERR "%vbomconv-I: compilation aborted by signal $sig\n";
exit(1);
} else {
print STDERR "%vbomconv-I compilation failed (rc=$rc) $?\n";
print STDERR "%vbomconv-I: compilation failed (rc=$rc) $?\n";
exit($rc);
}
}
297,7 → 301,8
 
$cmd .= "ghdl -m";
$cmd .= " -o $stem";
$cmd .= ' -fexplicit' if $has_unisim; # needed for ISE 13.1
# -fexplicit needed for ISE 13.1,13.3
$cmd .= ' -fexplicit' if $has_unisim or $has_simprim;
$cmd .= ' -P$XILINX/ghdl/unisim' if $has_unisim;
$cmd .= ' -P$XILINX/ghdl/simprim' if $has_simprim;
$cmd .= " --ieee=synopsys";
519,6 → 524,12
 
}
 
# --get_top ----------------------------------------------------------
 
if (exists $opts{get_top}) {
print "$top\n";
}
 
# --flist ------------------------------------------------------------
 
if (exists $opts{flist}) {
575,6 → 586,51
 
s/\s*$//; # drop trailing blanks
 
# process parameter definitions
if (m{([\w]+)\s*=\s*(.*)}) {
my $para = $1;
my $val = $2;
if ($val eq "") {
print STDERR "%vbomconv-E: invalid \'$_\' in $vbom_file\n";
exit 1;
}
if (not exists $para_tbl{$para}) {
$para_tbl{$para} = canon_fname($vbom_path, $val);
print STDERR "--- define \${$para} = $val\n" if $do_trace;
} else {
print STDERR "--- ignore \${$para} = $val\n" if $do_trace;
}
next;
}
 
# process parameter substitutions
while (m{\$\{([\w]+)\s*(:=)?\s*(.*?)\}}) {
my $para = $1;
my $del = $2;
my $val = $3;
my $pre = $`;
my $post = $';
if (defined $del && $del eq ":=") {
if (not exists $para_tbl{$para}) {
$para_tbl{$para} = canon_fname($vbom_path, $val);
print STDERR "--- define \${$para := $val}\n" if $do_trace;
} else {
print STDERR "--- ignore \${$para := $val}\n" if $do_trace;
}
}
if (defined $para_tbl{$para}) {
if ($do_trace) {
print STDERR "--- use \${$para} -> $para_tbl{$para}\n";
} else {
## print STDERR "%vbomconv-I: \${$para} -> $para_tbl{$para}\n";
}
$_ = $pre . "!" . $para_tbl{$para} . $post;
} else {
print STDERR "%vbomconv-E: undefined \${$para} in $vbom_file\n";
exit 1;
}
}
 
if (/^\[([a-z,]+)\]\s*(.+)$/) { # [xxx,yyy] tag seen
my $qual = $1;
my $name = $2;
599,35 → 655,33
 
my $tag;
my $val = $_;
my $del;
 
# detect tag=val or tag:val lines
if (m{^\s*(.*?)\s*([=:])\s*(.*?)\s*$}) {
# detect tag:val lines
if (m{^\s*(.*?)\s*:\s*(.*?)\s*$}) {
$tag = $1;
$del = $2;
$val = $3;
}
$val = $2;
 
# process @top:<entity> lines
if (defined $del && $del eq ":" && $tag eq '@top') {
$top = $val unless $top_done;
next;
}
# process @top:<entity> lines
if ($tag eq '@top') {
$top = $val unless $top_done;
 
# process @ucf_cpp:<file> lines
if (defined $del && $del eq ":" && $tag eq '@ucf_cpp') {
push @ucf_cpp_list, $val;
next;
}
# process @ucf_cpp:<file> lines
} elsif ($tag eq '@ucf_cpp') {
push @ucf_cpp_list, $val;
 
# process @lib:<name> lines
if (defined $del && $del eq ":" && $tag eq '@lib') {
if ($val eq 'unisim') {
$has_unisim = 1;
} elsif ($val eq 'simprim') {
$has_simprim = 1;
# process @lib:<name> lines
} elsif ($tag eq '@lib') {
if ($val eq 'unisim') {
$has_unisim = 1;
} elsif ($val eq 'simprim') {
$has_simprim = 1;
} else {
print STDERR "%vbomconv-E: invalid lib type \'$tag\' in $vbom_file\n";
exit 1;
}
} else {
die "unknown library type: $val";
print STDERR "%vbomconv-E: invalid \'$tag:\' line in $vbom_file\n";
exit 1;
}
next;
}
637,25 → 691,14
$val =~ s{_ssim\.vhd$}{_tsim.vhd} if $is_tsim;
 
# process normal .vhd or .vbom file lines
# get full relative file name (relative to cwd)
 
my $fname = $val;
$fname = "$vbom_path/$fname" if $vbom_path ne "";
 
# remove 'inner' .., e.g. ../x/../y --> ../y
# this will also canonize the file names, thus same file same name
 
my @flist;
foreach (split "/",$fname) {
if (scalar(@flist) && $flist[$#flist] ne ".." && $_ eq "..") {
pop @flist;
} else {
push @flist, $_;
}
# canonize file name unless not already done by filename substitution
my $fullname;
if ($val =~ m{^!(.*)$}) {
$fullname = $1;
} else {
$fullname = canon_fname($vbom_path, $val);
}
 
my $fullname = join "/", @flist;
 
# determine whether additional libs needed
if ($fullname =~ m{_ssim\.vhd$}) { # ends in _ssim.vhd
$has_unisim = 1;
664,27 → 707,7
$has_simprim = 1;
}
 
# handle configuration statements (tag=val)
if (defined $del && $del eq "=") {
if (exists $conf_tbl{$tag}) {
print STDERR "--- ignore $tag = $fullname\n" if $do_trace;
} else {
$conf_tbl{$tag} = $fullname;
print STDERR "--- config $tag = $fullname\n" if $do_trace;
}
next;
}
 
# handle configurable lines (tag:val)
if (defined $del && $del eq ":") {
if (exists $conf_tbl{$tag}) {
$fullname = $conf_tbl{$tag};
print STDERR "--- use $tag = $fullname\n" if $do_trace;
} else {
print STDERR "--- use $tag = $fullname (default)\n" if $do_trace;
}
}
 
# build vbom table
push @{$vbom_tbl{$vbom}}, $fullname;
print STDERR "--- add $fullname\n" if $do_trace;
759,7 → 782,28
}
 
#-------------------------------------------------------------------------------
sub canon_fname {
my ($vpath,$fname) = @_;
# get full relative file name (relative to cwd)
$fname = "$vpath/$fname" if $vpath ne "";
 
# remove 'inner' .., e.g. ../x/../y --> ../y
# this will also canonize the file names, thus same file same name
 
my @flist;
foreach (split "/",$fname) {
if (scalar(@flist) && $flist[$#flist] ne ".." && $_ eq "..") {
pop @flist;
} else {
push @flist, $_;
}
}
 
return join "/", @flist;
}
 
#-------------------------------------------------------------------------------
 
sub print_help {
print "usage: vbomconf <command> file.vbom\n";
print " --help this message\n";
/tools/bin/isemsg_filter
1,7 → 1,7
#!/usr/bin/perl -w
# $Id: isemsg_filter 406 2011-08-14 21:06:44Z mueller $
# $Id: isemsg_filter 450 2012-01-05 23:21:41Z mueller $
#
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
14,6 → 14,7
#
# Revision History:
# Date Rev Version Comment
# 2012-01-04 450 1.1 preliminary check for par 'all constraints met'
# 2011-08-14 406 1.0 Initial version
#
 
146,6 → 147,7
}
 
close (FFILE);
 
return 0;
}
 
161,9 → 163,13
my $msgorig = "";
my $msgflat = "";
my $inmsg = 0;
my $parallmet = 0;
 
while (<LFILE>) {
chomp;
 
$parallmet = 1 if ($type eq "par" && m/All c/);
 
if (m{^(INFO|WARNING|ERROR):}) {
if ($inmsg) {push @mlist, [$msgorig, $msgflat, 0];}
$inmsg = 1;
184,6 → 190,12
 
close (LFILE);
 
if ($type eq "par" && $parallmet==0) {
printf "!! ----------------------------------- !!\n";
printf "!! par: FAILED TO REACH TIMING CLOSURE !!\n";
printf "!! ----------------------------------- !!\n";
}
 
return 0;
}
 
/tools/bin/fx2load_wrapper
0,0 → 1,261
#!/usr/bin/perl -w
# $Id: fx2load_wrapper 457 2012-02-12 22:34:20Z mueller $
#
# Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation, either version 2, or at your option any later version.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for complete details.
#
# Revision History:
# Date Rev Version Comment
# 2012-02-11 457 1.0.1 use RETRO_FX2_VID/PID; check iProduct string
# 2011-12-29 446 1.0 Initial version
#
 
use 5.005; # require Perl 5.005 or higher
use strict; # require strict checking
use FileHandle;
use Time::HiRes qw(usleep);
 
use Getopt::Long;
 
my %opts = ();
 
GetOptions(\%opts, "help", "dry_run", "force", "cycfx2prog",
"board=s", "file=s", "ihx_path=s")
or exit 1;
 
#
# setup defaults for board and file
#
if (not defined $opts{board}) {
$opts{board} = "nexys2";
}
if (not defined $opts{file}) {
$opts{file} = "nexys2_jtag_2fifo_as.ihx" if $opts{board} eq "nexys2";
$opts{file} = "nexys3_jtag_2fifo_as.ihx" if $opts{board} eq "nexys3";
$opts{file} = "nexys3_jtag_2fifo_as.ihx" if $opts{board} eq "atlys";
}
if (not defined $opts{ihx_path}) {
unless (exists $ENV{RETROBASE}) {
print STDERR "fx2load_wrapper-F: RETROBASE not set\n";
exit 1;
}
$opts{ihx_path} = $ENV{RETROBASE} . "/tools/fx2/bin";
}
 
sub print_help;
sub run_command;
sub get_usb_id;
sub get_usb_prodinfo;
 
autoflush STDOUT 1 if (-p STDOUT); # autoflush if output into pipe
 
if (exists $opts{help}) {
print_help;
exit 0;
}
 
my $board = $opts{board};
my $ifile = $opts{file};
 
# setup digilent default usb id's
 
my $usbid_digi;
 
if ($board eq "nexys2") { $usbid_digi = "1443:0005";}
elsif ($board eq "nexys3") { $usbid_digi = "1443:0007";}
elsif ($board eq "atlys") { $usbid_digi = "1443:0007";}
else {
print STDERR
"fx2load_wrapper-E: only nexys2,3/atlys supported\n";
exit 1;
}
 
# handle USB VID/PID of board
# taken from RETRO_FX2_VID and RETRO_FX2_PID environment variables
# in the retro11 project the default is:
# VID: 16c0 (VOTI)
# PID: 03ef (VOTI free for internal lab use 1007)
#
# !! Important Note on Usage of this USB VID/PID !!
# This VID/PID is owned by VOTI, a small dutch company. Usage is granted
# for 'internal lab use only' by VOTI under the conditions:
# - the gadgets in which you use those PIDs do not leave your desk
# - you won't complain to VOTI if you get in trouble with duplicate PIDs
# (for instance because someone else did not follow the previous rule).
# See also http://www.voti.nl/pids/pidfaq.html
#
 
my $fx2_vid = $ENV{RETRO_FX2_VID};
my $fx2_pid = $ENV{RETRO_FX2_PID};
$fx2_vid = "16c0" unless defined $fx2_vid;
$fx2_pid = "03ef" unless defined $fx2_pid;
 
my $usbid_retro = "$fx2_vid:$fx2_pid";
my $n_digi = 0;
my $n_retro = 0;
 
my $fx2_bus;
my $fx2_dev;
my $fx2_id;
my $fx2_prodinfo;
 
($n_digi, $n_retro, $fx2_bus, $fx2_dev, $fx2_id) = get_usb_id();
 
if ($n_digi+$n_retro == 0) {
print STDERR "fx2load_wrapper-E no board detected\n";
exit 1;
}
if ($n_digi+$n_retro > 1) {
print STDERR "fx2load_wrapper-E more than one board detected\n";
exit 1;
}
 
if ($n_retro > 0) {
$fx2_prodinfo = get_usb_prodinfo($fx2_id);
}
 
if ($n_retro == 1 &&
$opts{file} eq $fx2_prodinfo . ".ihx" &&
(not defined $opts{force}) ) {
print "fx2load_wrapper-I board already configured with $fx2_prodinfo.ihx\n";
exit 0;
}
 
my $full_file = $opts{ihx_path} . "/" . $opts{file};
unless (-r $full_file) {
print STDERR "fx2load_wrapper-E: ihx file \'$full_file\' not found\n";
exit 1;
}
 
my $fx2_path = "/dev/bus/usb/$fx2_bus/$fx2_dev";
 
unless ( -r $fx2_path && -w $fx2_path) {
print STDERR
"fx2load_wrapper-E: usb device \'$fx2_path\' not user accessible\n";
exit 1;
}
 
my $cmd;
 
if ($opts{cycfx2prog}) {
my $proc = `which cycfx2prog`;
chomp $proc;
unless (-x $proc) {
print STDERR "fx2load_wrapper-E: cycfx2prog not found or executable\n";
exit 1;
}
$cmd = "cycfx2prog -id=$fx2_id prg:$full_file run";
 
} else {
my $proc = `which fxload`;
chomp $proc;
$proc = "/sbin/fxload" if ($proc eq "");
unless (-x $proc) {
print STDERR "fx2load_wrapper-E: fxload not found or executable\n";
exit 1;
}
$cmd = "$proc -t fx2 -I $full_file -D $fx2_path";
}
 
my $rc = 0;
if (defined $opts{dry_run}) {
print "$cmd\n";
} else {
print "fx2load_wrapper-I: loading $opts{file}\n";
$rc = run_command($cmd);
print "fx2load_wrapper-I: loaded $opts{file}\n";
usleep(1500000);
}
 
exit $rc;
 
#-------------------------------------------------------------------------------
 
sub run_command {
 
my ($cmd) = @_;
 
my $wrc = system "/bin/sh", "-c", "$cmd";
 
my $rc = 0;
if ($wrc != 0) {
my $rc = int($wrc/256);
if ($rc == 0) {
my $sig = $wrc % 256;
print STDERR "fx2load_wrapper-E \'$cmd\' aborted by signal $sig\n";
$rc = 1;
} else {
print STDERR "fx2load_wrapper-E \'$cmd\' failed (rc=$rc) $?\n";
}
}
 
return $rc;
}
 
#-------------------------------------------------------------------------------
 
sub print_help {
print "usage: fx2load_wrapper [--board=b] [--file=f] <opts>\n";
print " --help this message\n";
print " --dry_run print command only\n";
print " --cycfx2prog use cycfx2prog instead of fxload\n";
print " --board=b type of board (default nexys2)\n";
print " --file=f ihx file to load (default 2fifo_as)\n";
print " --ihx_path=p path to ihx files\n";
}
 
 
#-------------------------------------------------------------------------------
 
sub get_usb_id {
my @lsusb = `lsusb`;
 
my $n_digi = 0;
my $n_retro = 0;
my $fx2_bus;
my $fx2_dev;
my $fx2_id;
 
foreach (@lsusb) {
if (/^Bus\s+(\d+)\s+Device\s+(\d+):\s+ID\s+([:0-9a-f]+)\s+(.*)$/) {
my ($bus,$dev,$id,$text) = ($1,$2,$3,$4);
my $match = 0;
if ($id eq $usbid_digi) {
$n_digi += 1;
$match = 1;
} elsif ($id eq $usbid_retro) {
$n_retro += 1;
$match = 1;
}
if ($match) {
$fx2_bus = $bus;
$fx2_dev = $dev;
$fx2_id = $id;
}
}
}
 
return ($n_digi, $n_retro, $fx2_bus, $fx2_dev, $fx2_id);
 
}
 
#-------------------------------------------------------------------------------
 
sub get_usb_prodinfo {
my ($fx2_id) = @_;
my @lsusb = `lsusb -d $fx2_id -v`;
foreach (@lsusb) {
if (/^\s*iProduct\s*\d*\s*(.*)$/) {
return $1;
}
}
return "";
}
tools/bin/fx2load_wrapper Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tools/bin/config_wrapper =================================================================== --- tools/bin/config_wrapper (revision 16) +++ tools/bin/config_wrapper (revision 17) @@ -1,7 +1,7 @@ #!/usr/bin/perl -w -# $Id: config_wrapper 435 2011-12-04 20:15:25Z mueller $ +# $Id: config_wrapper 467 2013-01-02 19:49:05Z mueller $ # -# Copyright 2010-2011 by Walter F.J. Mueller +# Copyright 2010-2013 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -14,6 +14,8 @@ # # Revision History: # Date Rev Version Comment +# 2013-01-02 467 1.1.7 jconfig: prepend '0x' to support 'jtag #2007' +# 2012-02-11 457 1.1.6 jconfig: use RETRO_FX2_VID/PID for USB VID/PID # 2011-12-03 435 1.1.5 add nexys3 support; # 2011-08-04 402 1.1.4 add atlys support; # 2011-07-25 399 1.1.3 add nexys2-500 support; bsdl path for sp605 @@ -177,7 +179,28 @@ my $jtag_part = $#plist + 1 - $pfpga; - print OFILE "cable usbblaster\n"; + # handle USB VID/PID of board + # taken from RETRO_FX2_VID and RETRO_FX2_PID environment variables + # in the retro11 project the default is: + # VID: 16c0 (VOTI) + # PID: 03ef (VOTI free for internal lab use 1007) + # + # !! Important Note on Usage of this USB VID/PID !! + # This VID/PID is owned by VOTI, a small dutch company. Usage is granted + # for 'internal lab use only' by VOTI under the conditions: + # - the gadgets in which you use those PIDs do not leave your desk + # - you won't complain to VOTI if you get in trouble with duplicate PIDs + # (for instance because someone else did not follow the previous rule). + # See also http://www.voti.nl/pids/pidfaq.html + # + + my $fx2_vid = $ENV{RETRO_FX2_VID}; + my $fx2_pid = $ENV{RETRO_FX2_PID}; + $fx2_vid = "16c0" unless defined $fx2_vid; + $fx2_pid = "03ef" unless defined $fx2_pid; + + # give vid/pid with 0x prefix. jtag #2007 requires this, #1502 tolerates + print OFILE "cable usbblaster vid=0x$fx2_vid pid=0x$fx2_pid\n"; printf OFILE "bsdl path %s\n", $bpath; print OFILE "detect\n"; printf OFILE "part %d\n", $jtag_part;
/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vhd
0,0 → 1,194
-- $Id: tst_fx2loop_hiomap.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_fx2loop_hiomap - syn
-- Description: default human I/O mapper
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.0.2 re-arrange DP,DSP usage
-- 2012-01-03 449 1.0.1 use new fx2ctl_moni layout
-- 2011-12-26 445 1.0 Initial version
------------------------------------------------------------------------------
--
-- Usage of Switches, Buttons, LEDs:
--
-- BTN(3) -- unused --
-- (2) -- unused --
-- (1) -- unused --
-- (0) reset state [!! decoded by top level design !!]
--
-- SWI(7:5) select display
-- (4) -- unused --
-- (3) throttle
-- (2) tx2blast
-- (1:0) mode 00 idle
-- 01 rxblast
-- 10 txblast
-- 11 loop
--
-- LED(7) MONI.fifo_ep4
-- (6) MONI.fifo_ep6
-- (5) MONI.fifo_ep8
-- (4) MONI.flag_ep4_empty
-- (3) MONI.flag_ep4_almost
-- (2) MONI.flag_ep6_full
-- (1) MONI.flag_ep6_almost
-- (0) rxsecnt > 0 (sequence error)
--
-- DSP data as selected by SWI(7:5)
-- 000 -> rxsecnt
-- 001 -> -- unused -- (display ffff)
-- 010 -> rxcnt.l
-- 011 -> rxcnt.h
-- 100 -> txcnt.l
-- 101 -> txcnt.h
-- 110 -> tx2cnt.l
-- 111 -> tx2cnt.h
--
-- DP(3) FX2_TXBUSY (shows tx back preasure)
-- (2) FX2_MONI.slwr (shows tx activity)
-- (1) FX2_RXHOLD (shows rx back preasure)
-- (0) FX2_MONI.slrd (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.fx2lib.all;
use work.tst_fx2looplib.all;
 
-- ----------------------------------------------------------------------------
 
entity tst_fx2loop_hiomap is -- default human I/O mapper
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
HIO_CNTL : out hio_cntl_type; -- tester controls from hio
HIO_STAT : in hio_stat_type; -- tester status to diaplay by hio
FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor to display by hio
SWI : in slv8; -- switch settings
BTN : in slv4; -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end tst_fx2loop_hiomap;
 
architecture syn of tst_fx2loop_hiomap is
 
type regs_type is record
dspdat : slv16; -- display data
dummy : slbit; -- <remove when 2nd signal added...>
end record regs_type;
 
constant regs_init : regs_type := (
(others=>'0'), -- dspdat
'0'
);
 
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
 
begin
 
proc_regs: process (CLK)
begin
 
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
 
end process proc_regs;
 
proc_next: process (R_REGS, HIO_STAT, FX2_MONI, SWI, BTN)
 
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
 
variable icntl : hio_cntl_type := hio_cntl_init;
variable iled : slv8 := (others=>'0');
variable idat : slv16 := (others=>'0');
variable idp : slv4 := (others=>'0');
 
begin
 
r := R_REGS;
n := R_REGS;
 
icntl := hio_cntl_init;
iled := (others=>'0');
idat := (others=>'0');
idp := (others=>'0');
 
-- setup tester controls
icntl.mode := SWI(1 downto 0);
icntl.tx2blast := SWI(2);
icntl.throttle := SWI(3);
-- setup leds
iled(7) := FX2_MONI.fifo_ep4;
iled(6) := FX2_MONI.fifo_ep6;
iled(5) := FX2_MONI.fifo_ep8;
iled(4) := FX2_MONI.flag_ep4_empty;
iled(3) := FX2_MONI.flag_ep4_almost;
iled(2) := FX2_MONI.flag_ep6_full;
iled(1) := FX2_MONI.flag_ep6_almost;
if unsigned(HIO_STAT.rxsecnt) > 0 then iled(0) := '1'; end if;
-- setup display data
case SWI(7 downto 5) is
when "000" => idat := HIO_STAT.rxsecnt;
when "001" => idat := (others=>'1');
when "010" => idat := HIO_STAT.rxcnt(15 downto 0);
when "011" => idat := HIO_STAT.rxcnt(31 downto 16);
when "100" => idat := HIO_STAT.txcnt(15 downto 0);
when "101" => idat := HIO_STAT.txcnt(31 downto 16);
when "110" => idat := HIO_STAT.tx2cnt(15 downto 0);
when "111" => idat := HIO_STAT.tx2cnt(31 downto 16);
when others => null;
end case;
n.dspdat := idat;
 
-- setup display decimal points
 
idp(3) := HIO_STAT.txbusy; -- tx back preasure
idp(2) := FX2_MONI.slwr; -- tx activity
idp(1) := HIO_STAT.rxhold; -- rx back preasure
idp(0) := FX2_MONI.slrd; -- rx activity
 
N_REGS <= n;
 
HIO_CNTL <= icntl;
LED <= iled;
DSP_DAT <= r.dspdat;
DSP_DP <= idp;
end process proc_next;
end syn;
/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vbom
0,0 → 1,7
# libs
../../vlib/slvtypes.vhd
../../bplib/fx2lib/fx2lib.vhd
tst_fx2looplib.vbom
# components
# design
tst_fx2loop_hiomap.vhd
/rtl/sys_gen/tst_fx2loop/tst_fx2loop.vhd
0,0 → 1,265
-- $Id: tst_fx2loop.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_fx2loop - syn
-- Description: simple stand-alone tester for fx2lib components
--
-- Dependencies: comlib/byte2word
-- comlib/word2byte
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.0 Initial version
-- 2011-12-26 445 0.5 First draft
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.comlib.all;
use work.fx2lib.all;
use work.tst_fx2looplib.all;
 
-- ----------------------------------------------------------------------------
 
entity tst_fx2loop is -- tester for fx2lib components
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
HIO_CNTL : in hio_cntl_type; -- humanio controls
HIO_STAT : out hio_stat_type; -- humanio status
FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor
RXDATA : in slv8; -- receiver data out
RXVAL : in slbit; -- receiver data valid
RXHOLD : out slbit; -- receiver data hold
TXDATA : out slv8; -- transmit data in
TXENA : out slbit; -- transmit data enable
TXBUSY : in slbit; -- transmit busy
TX2DATA : out slv8; -- transmit 2 data in
TX2ENA : out slbit; -- transmit 2 data enable
TX2BUSY : in slbit -- transmit 2 busy
);
end tst_fx2loop;
 
architecture syn of tst_fx2loop is
 
type regs_type is record
rxdata : slv16; -- next rx word
txdata : slv16; -- next tx word
tx2data : slv16; -- next tx2 word
rxsecnt : slv16; -- rx sequence error counter
rxcnt : slv32; -- rx word counter
txcnt : slv32; -- tx word counter
tx2cnt : slv32; -- tx2 word counter
rxthrottle : slbit; -- rx throttle flag
end record regs_type;
 
constant regs_init : regs_type := (
(others=>'0'), -- rxdata
(others=>'0'), -- txdata
(others=>'0'), -- tx2data
(others=>'0'), -- rxsecnt
(others=>'0'), -- rxcnt
(others=>'0'), -- txcnt
(others=>'0'), -- tx2cnt
'0' -- rxthrottle
);
 
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
 
signal RXWDATA : slv16 := (others=>'0');
signal RXWVAL : slbit := '0';
signal RXWHOLD : slbit := '0';
signal RXODD : slbit := '0';
signal TXWDATA : slv16 := (others=>'0');
signal TXWENA : slbit := '0';
signal TXWBUSY : slbit := '0';
signal TXODD : slbit := '0';
signal TX2WDATA : slv16 := (others=>'0');
signal TX2WENA : slbit := '0';
signal TX2WBUSY : slbit := '0';
signal TX2ODD : slbit := '0';
 
signal RXHOLD_L : slbit := '0'; -- local copy of out port signal
signal TXENA_L : slbit := '0'; -- local copy of out port signal
signal TX2ENA_L : slbit := '0'; -- local copy of out port signal
signal CNTL_RESET_L : slbit := '0'; -- local copy of out port signal
 
begin
 
CNTL_RESET_L <= '0'; -- so far unused
 
RXB2W : byte2word
port map (
CLK => CLK,
RESET => CNTL_RESET_L,
DI => RXDATA,
ENA => RXVAL,
BUSY => RXHOLD_L,
DO => RXWDATA,
VAL => RXWVAL,
HOLD => RXWHOLD,
ODD => RXODD
);
 
TX1W2B : word2byte
port map (
CLK => CLK,
RESET => CNTL_RESET_L,
DI => TXWDATA,
ENA => TXWENA,
BUSY => TXWBUSY,
DO => TXDATA,
VAL => TXENA_L,
HOLD => TXBUSY,
ODD => TXODD
);
 
TX2W2B : word2byte
port map (
CLK => CLK,
RESET => CNTL_RESET_L,
DI => TX2WDATA,
ENA => TX2WENA,
BUSY => TX2WBUSY,
DO => TX2DATA,
VAL => TX2ENA_L,
HOLD => TX2BUSY,
ODD => TX2ODD
);
 
proc_regs: process (CLK)
begin
 
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
 
end process proc_regs;
 
proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, FX2_MONI,
RXWDATA, RXWVAL, TXWBUSY, TX2WBUSY)
 
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
 
variable irxwhold : slbit := '1';
variable itxwena : slbit := '0';
variable itxwdata : slv16 := (others=>'0');
variable itx2wena : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
 
irxwhold := '1';
itxwena := '0';
itxwdata := RXWDATA;
itx2wena := '0';
 
if HIO_CNTL.throttle = '1' then
if CE_MSEC = '1' then
n.rxthrottle := not r.rxthrottle;
end if;
else
n.rxthrottle := '0';
end if;
 
case HIO_CNTL.mode is
when c_mode_idle =>
null;
 
when c_mode_rxblast =>
if RXWVAL='1' and r.rxthrottle='0' then
irxwhold := '0';
if RXWDATA /= r.rxdata then
n.rxsecnt := slv(unsigned(r.rxsecnt) + 1);
end if;
n.rxdata := slv(unsigned(RXWDATA) + 1);
end if;
when c_mode_txblast =>
itxwdata := r.txdata;
if TXWBUSY = '0' then
itxwena := '1';
n.txdata := slv(unsigned(r.txdata) + 1);
end if;
irxwhold := '0';
when c_mode_loop =>
itxwdata := RXWDATA;
if RXWVAL='1' and r.rxthrottle='0' and TXWBUSY = '0' then
irxwhold := '0';
itxwena := '1';
end if;
when others => null;
end case;
 
if HIO_CNTL.tx2blast = '1' then
if TX2WBUSY = '0' then
itx2wena := '1';
n.tx2data := slv(unsigned(r.tx2data) + 1);
end if;
end if;
if RXWVAL='1' and irxwhold='0' then
n.rxcnt := slv(unsigned(r.rxcnt) + 1);
end if;
if itxwena = '1' then
n.txcnt := slv(unsigned(r.txcnt) + 1);
end if;
 
if itx2wena = '1' then
n.tx2cnt := slv(unsigned(r.tx2cnt) + 1);
end if;
N_REGS <= n;
 
RXWHOLD <= irxwhold;
TXWENA <= itxwena;
TXWDATA <= itxwdata;
TX2WENA <= itx2wena;
TX2WDATA <= r.tx2data;
 
HIO_STAT.rxhold <= RXHOLD_L;
HIO_STAT.txbusy <= TXBUSY;
HIO_STAT.tx2busy <= TX2BUSY;
HIO_STAT.rxsecnt <= r.rxsecnt;
HIO_STAT.rxcnt <= r.rxcnt;
HIO_STAT.txcnt <= r.txcnt;
HIO_STAT.tx2cnt <= r.tx2cnt;
 
end process proc_next;
 
RXHOLD <= RXHOLD_L;
TXENA <= TXENA_L;
TX2ENA <= TX2ENA_L;
end syn;
/rtl/sys_gen/tst_fx2loop/tst_fx2loop.c
0,0 → 1,1044
/* $Id: tst_fx2loop.c 465 2012-12-27 21:29:38Z mueller $ */
/*
* Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
*
* This program is free software; you may redistribute and/or modify it under
* the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 2, or at your option any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for complete details.
*
*
* Revision History:
* Date Rev Version Comment
* 2012-04-09 461 2.1.1 fix loop back code: fix run-down, add pipe drain
* 2012-03-24 460 2.1 add message loop back code (preliminary)
* 2012-03-10 459 2.0 re-write for asynchronous libusb interface
* 2012-02-12 457 1.1 redo argument handling; add -stat and -rndm
* 2012-01-15 453 1.0.1 add -tx2blast; fix bug in loop read loop
* 2011-12-29 446 1.0 Initial version (only -read/write/loop)
*/
 
#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <string.h>
#include <limits.h>
#include <signal.h>
#include <poll.h>
#include <errno.h>
#include <sys/timerfd.h>
 
#include <libusb-1.0/libusb.h>
 
static int nsigint = 0;
static int endpoll = 0;
static libusb_context* pUsbContext = 0;
static libusb_device** pUsbDevList = 0;
static int UsbDevCount = 0;
static libusb_device_handle* pUsbDevHdl = 0;
 
static struct pollfd pollfd_fds[16];
static int pollfd_nfds = 0;
 
struct dsc_queue {
int par_nfrm;
int par_nque;
double stat_nbuf;
double stat_nbyt;
double stat_npt;
uint16_t cval;
};
 
static struct dsc_queue dsc_rx;
static struct dsc_queue dsc_tx1;
static struct dsc_queue dsc_tx2;
 
static int par_nwmsg = 0;
static int par_nwrndm = 0;
static int par_stat = 0;
static int par_trace = 0;
static int par_nsec = 0;
 
static int cur_nwmsg = 0;
static double stat_nmsg = 0.;
 
static double t_start;
static int nreq = 0;
 
static char** argv;
static int argc;
static int argi;
 
 
void usage(FILE* of);
int get_pint(char* p);
double get_double(char* p);
int get_arg_pint(int min, int max, const char* text);
 
void do_write(uint16_t* buf, int nw);
void do_read(int ep);
void do_run();
void do_stat();
void usb_claim();
void usb_release();
char* usb_strerror(int rc);
void prt_time(void);
double get_time(void);
void bad_syscall_exit(const char* text, int rc);
void bad_usbcall_exit(const char* text, int rc);
void bad_transfer_exit(struct libusb_transfer *t, const char* text);
 
void sigint_handler(int signum)
{
printf("\n");
nsigint += 1;
if (nsigint > 3) {
fprintf(stderr, "tst_fx2loop-F: 3rd ^C, aborting\n");
exit(EXIT_FAILURE);
}
return;
}
 
int main(int main_argc, char *main_argv[])
{
argc = main_argc;
argv = main_argv;
argi = 1;
int i;
 
/* setup ^C handler */
struct sigaction new_action;
 
new_action.sa_handler = sigint_handler;
sigemptyset (&new_action.sa_mask);
new_action.sa_flags = 0;
sigaction (SIGINT, &new_action, NULL);
 
/* capture -help case here */
for (i = 1; i < argc; i++) {
if (strcmp(argv[i], "-help") == 0) {
usage(stdout);
return EXIT_SUCCESS;
}
}
 
/* determine usb device path (first arg or from RETRO_FX2_VID/PID */
char devbuf[10];
char* path = 0;
 
if (argc > argi && argv[argi][0] != '-') {
path = argv[argi];
argi += 1;
} else {
char* env_vid = getenv("RETRO_FX2_VID");
char* env_pid = getenv("RETRO_FX2_PID");
if (env_vid && strlen(env_vid) == 4 &&
env_pid && strlen(env_pid) == 4) {
strncpy(devbuf , env_vid,4);
devbuf[4] = ':';
strncpy(devbuf+5, env_pid,4);
devbuf[9] = 0;
path = devbuf;
} else {
fprintf(stderr,
"tst_fx2loop-F: RETRO_FX2_VID/PID not or ill defined\n");
return EXIT_FAILURE;
}
}
 
/* init libusb, connect to device */
libusb_init(&pUsbContext);
libusb_set_debug(pUsbContext, 3);
UsbDevCount = libusb_get_device_list(pUsbContext, &pUsbDevList);
 
libusb_device* mydev = 0;
 
if (strlen(path)==8 && path[0]=='/' && path[4]=='/') {
char busnam[4];
char devnam[4];
strncpy(busnam, path+1, 3);
strncpy(devnam, path+5, 3);
busnam[3] = 0;
devnam[3] = 0;
 
char* endptr;
uint8_t busnum = strtol(busnam, &endptr, 10);
uint8_t devnum = strtol(devnam, &endptr, 10);
 
int idev;
for (idev=0; idev<UsbDevCount; idev++) {
libusb_device* udev = pUsbDevList[idev];
if (libusb_get_bus_number(udev) == busnum &&
libusb_get_device_address(udev) == devnum) {
mydev = udev;
}
}
 
} else if (strlen(path)==9 && path[4]==':') {
char vennam[5];
char pronam[5];
memcpy(vennam, path, 4);
memcpy(pronam, path+5, 4);
vennam[4] = 0;
pronam[4] = 0;
 
char* endptr;
uint16_t vennum = strtol(vennam, &endptr, 16);
uint16_t pronum = strtol(pronam, &endptr, 16);
 
int idev;
for (idev=0; idev<UsbDevCount; idev++) {
libusb_device* udev = pUsbDevList[idev];
struct libusb_device_descriptor devdsc;
libusb_get_device_descriptor(udev, &devdsc);
if (devdsc.idVendor==vennum && devdsc.idProduct==pronum) {
mydev = udev;
}
}
 
} else {
fprintf(stderr, "tst_fx2loop-F: dev not in /bus/dev or vend:prod form\n");
return EXIT_FAILURE;
}
 
if (mydev == 0) {
fprintf(stderr, "tst_fx2loop-F: no usb device %s found\n", path);
return EXIT_FAILURE;
}
 
int rc;
rc = libusb_open(mydev, &pUsbDevHdl);
if (rc) {
fprintf(stderr, "tst_fx2loop-F: failed to open %s rc=%d: %s\n",
path, rc, usb_strerror(rc));
return EXIT_FAILURE;
}
 
/* check for internal timeout handling support */
if (libusb_pollfds_handle_timeouts(pUsbContext) == 0) {
fprintf(stderr, "tst_fx2loop-F: libusb_pollfds_handle_timeouts == 0\n"
" this program will not run on this legacy system\n");
return EXIT_FAILURE;
}
 
for (; argi < argc; ) {
 
/* handle setup options ----------------------------------------------- */
if (strcmp(argv[argi],"-nbrx") == 0) {
argi += 1;
dsc_rx.par_nfrm = get_arg_pint(1, 256, "rx buffer size invalid");
} else if (strcmp(argv[argi],"-nqrx") == 0) {
argi += 1;
dsc_rx.par_nque = get_arg_pint(1, 8, "rx buffer count invalid");
 
} else if (strcmp(argv[argi],"-nbtx") == 0) {
argi += 1;
dsc_tx1.par_nfrm = get_arg_pint(1, 256, "tx1 buffer size invalid");
} else if (strcmp(argv[argi],"-nqtx") == 0) {
argi += 1;
dsc_tx1.par_nque = get_arg_pint(1, 8, "tx1 buffer count invalid");
 
} else if (strcmp(argv[argi],"-nbtx2") == 0) {
argi += 1;
dsc_tx2.par_nfrm = get_arg_pint(1, 256, "tx2 buffer size invalid");
} else if (strcmp(argv[argi],"-nqtx2") == 0) {
argi += 1;
dsc_tx2.par_nque = get_arg_pint(1, 8, "tx2 buffer count invalid");
 
} else if (strcmp(argv[argi],"-nwmsg") == 0) {
argi += 1;
par_nwmsg = get_arg_pint(1, 4096, "loopback message size invalid");
 
} else if (strcmp(argv[argi],"-rndm") == 0) {
argi += 1;
par_nwrndm = 1;
} else if (strcmp(argv[argi],"-stat") == 0) {
argi += 1;
par_stat = 1;
} else if (strcmp(argv[argi],"-trace") == 0) {
argi += 1;
par_trace = 1;
 
/* handle action options ---------------------------------------------- */
} else if (strcmp(argv[argi],"-write") == 0) {
uint16_t buf[4096];
int nw = 0;
argi += 1;
while(argi < argc && nw < 4096) {
char *argp = argv[argi];
if (argp[0] == '-') break;
char* endptr;
long val = strtol(argp, &endptr, 0);
if ((endptr && endptr[0]) || val < 0 || val > 0xffff) {
nw = 0;
break;
}
argi += 1;
buf[nw++] = (uint16_t)val;
}
if (nw == 0) {
fprintf(stderr, "tst_fx2loop-E: bad word list\n");
break;
}
do_write(buf, nw);
 
} else if (strcmp(argv[argi],"-read") == 0) {
argi += 1;
int ep = 6;
if (argi < argc) ep = get_pint(argv[argi++]);
if (ep != 6 && ep != 8) {
fprintf(stderr, "tst_fx2loop-F: bad read endpoint (must be 6 or 8)\n");
return EXIT_FAILURE;
}
do_read(ep);
} else if (strcmp(argv[argi],"-run") == 0) {
argi += 1;
if (argi < argc) par_nsec = get_pint(argv[argi++]);
if (par_nsec < 0) {
fprintf(stderr, "tst_fx2loop-E: bad args for -run\n");
break;
}
do_run();
do_stat();
 
} else {
fprintf(stderr, "tst_fx2loop-F: unknown option %s\n", argv[argi]);
usage(stderr);
return EXIT_FAILURE;
}
}
 
return EXIT_SUCCESS;
}
 
/*--------------------------------------------------------------------------*/
void usage(FILE* of)
{
fprintf(of, "Usage: tst_fx2loop [dev] [setup-opts...] [action-opts...]\n");
fprintf(of, " arguments:\n");
fprintf(of, " dev path usb device, either bus/dev or vend:prod\n");
fprintf(of, " default is $RETRO_FX2_VID:$RETRO_FX2_VID\n");
fprintf(of, " setup options:\n");
fprintf(of, " -nbrx nb buffer size (in 512B) for rxblast\n");
fprintf(of, " -nqrx nb number of buffers for rxblast\n");
fprintf(of, " -nbtx nb buffer size (in 512B) for txblast or loop\n");
fprintf(of, " -nqtx nb number of buffers for txblast or loop\n");
fprintf(of, " -nbtx2 nb buffer size (in 512B) for tx2blast\n");
fprintf(of, " -nqtx2 nb number of buffers for tx2blast\n");
fprintf(of, " -nwmsg nw number words for loop test\n");
fprintf(of, " -rndm use random length for loop test\n");
fprintf(of, " -stat print live stats\n");
fprintf(of, " -trace trace usb calls\n");
fprintf(of, " action options:\n");
fprintf(of, " -write w0 w1 ... write list of words to endpoint 4\n");
fprintf(of, " -read ep read from endpoint ep\n");
fprintf(of, " -run ns run tests for nw seconds\n");
}
 
/*--------------------------------------------------------------------------*/
 
int get_pint(char* p)
{
char *endptr;
long num = 0;
 
num = strtol(p, &endptr, 0);
if ((endptr && *endptr) || num < 0 || num > INT_MAX) {
fprintf(stderr, "tst_fx2loop-E: \"%s\" not a non-negative integer\n", p);
return -1;
}
return num;
}
 
/*--------------------------------------------------------------------------*/
 
double get_double(char* p)
{
char *endptr;
double num = 0.;
 
num = strtod(p, &endptr);
if ((endptr && *endptr) || num < 0.) {
fprintf(stderr, "tst_fx2loop-E: \"%s\" not a valid positive float\n", p);
return -1.;
}
return num;
}
 
/*--------------------------------------------------------------------------*/
 
int get_arg_pint(int min, int max, const char* text)
{
int tmp = -1;
if (argi < argc) tmp = get_pint(argv[argi++]);
if (tmp < min || tmp > max) {
fprintf(stderr, "tst_fx2loop-F: %s\n", text);
exit(EXIT_FAILURE);
}
return tmp;
}
 
/*--------------------------------------------------------------------------*/
 
void do_write(uint16_t* buf, int nw)
{
int rc;
int i;
int ntrans;
int tout = 1000;
int ep = 4;
 
usb_claim();
rc = libusb_bulk_transfer(pUsbDevHdl, ep,
(unsigned char *)buf, nw*2, &ntrans, tout);
if (rc!=0 || ntrans != nw*2) {
fprintf(stderr, "tst_fx2loop-E: bulk write failed ntrans=%d rc=%d: %s \n",
ntrans, rc, usb_strerror(rc));
} else {
prt_time();
printf("write %4d word:", nw);
for (i = 0; i < nw; i++) printf(" %4.4x", buf[i]);
printf("\n");
}
usb_release();
 
return;
}
 
/*--------------------------------------------------------------------------*/
 
void do_read(int ep)
{
int rc;
int i;
int ntrans;
uint16_t buf[4096];
int tout = 1000;
int nloop;
 
usb_claim();
for (nloop=0;;nloop++) {
rc = libusb_bulk_transfer(pUsbDevHdl, ep|0x80,
(unsigned char *)buf, 2*4096, &ntrans, tout);
if (ntrans==0 && rc) {
if (rc==LIBUSB_ERROR_TIMEOUT && ntrans==0 && nloop>0) break;
fprintf(stderr, "tst_fx2loop-E: bulk read failed ntrans=%d rc=%d: %s \n",
ntrans, rc, usb_strerror(rc));
break;
}
prt_time();
printf("read %4d word:", ntrans/2);
int nprt = ntrans/2;
if (nprt > 7) nprt = 7;
for (i = 0; i < nprt; i++) printf(" %4.4x", (uint16_t)buf[i]);
printf("\n");
if (nsigint>0) break;
}
usb_release();
return;
}
 
/*----------------------------------------------------------*/
void pollfd_add(int fd, short events, void *user_data)
{
if (pollfd_nfds >= 16) {
fprintf(stderr, "tst_fx2loop-F: pollfd list overflow\n");
exit(EXIT_FAILURE);
}
if (par_trace) {
prt_time();
printf("pollfd_add: fd=%3d evt=%4.4x\n", fd, events);
}
pollfd_fds[pollfd_nfds].fd = fd;
pollfd_fds[pollfd_nfds].events = events;
pollfd_fds[pollfd_nfds].revents = 0;
pollfd_nfds += 1;
return;
}
 
/*----------------------------------------------------------*/
void pollfd_remove(int fd, void *user_data)
{
int iw = 0;
int ir = 0;
if (par_trace) {
prt_time();
printf("pollfd_remove: fd=%3d\n", fd);
}
for (ir = 0; ir < pollfd_nfds; ir++) {
if (pollfd_fds[ir].fd != fd) {
pollfd_fds[iw].fd = pollfd_fds[ir].fd;
pollfd_fds[iw].events = pollfd_fds[ir].events;
pollfd_fds[iw].revents = pollfd_fds[ir].revents;
iw += 1;
}
}
pollfd_nfds = iw;
return;
}
 
/*----------------------------------------------------------*/
void pollfd_init()
{
const struct libusb_pollfd** plist = libusb_get_pollfds(pUsbContext);
const struct libusb_pollfd** p;
for (p = plist; *p !=0; p++) {
pollfd_add((*p)->fd, (*p)->events, NULL);
}
 
free(plist);
 
libusb_set_pollfd_notifiers(pUsbContext, pollfd_add, pollfd_remove,NULL);
 
return;
}
 
/*----------------------------------------------------------*/
int keep_running()
{
if (nsigint > 0) return 0;
if (par_nsec > 0 && (get_time()-t_start) > par_nsec) return 0;
return 1;
}
 
/* forward declaration needed... */
void cb_rxblast(struct libusb_transfer *t);
 
/*----------------------------------------------------------*/
void que_write()
{
int rc;
int i;
int nw = 512*dsc_rx.par_nfrm/2;
int length = 2*nw;
uint16_t* pdat;
 
struct libusb_transfer* t = libusb_alloc_transfer(0);
 
t->dev_handle = pUsbDevHdl;
t->flags = LIBUSB_TRANSFER_FREE_TRANSFER | LIBUSB_TRANSFER_FREE_BUFFER;
t->endpoint = 4;
t->type = LIBUSB_TRANSFER_TYPE_BULK;
t->timeout = 1000;
t->status = 0;
t->buffer = malloc(length);
t->length = length;
t->actual_length = 0;
t->callback = cb_rxblast;
t->user_data = 0;
 
pdat = (uint16_t*)(t->buffer);
for (i = 0; i < nw; i++) *pdat++ = dsc_rx.cval++;
rc = libusb_submit_transfer(t);
if (rc) bad_usbcall_exit("libusb_submit_transfer()", rc);
 
nreq += 1;
 
if (par_trace) {
prt_time();
printf("que_write: ep=%1d l=%5d\n", t->endpoint&(~0x80), t->length);
}
 
return;
}
 
/*----------------------------------------------------------*/
void que_read(int ep, int nb, libusb_transfer_cb_fn cb)
{
int rc;
int length = 512*nb;
 
struct libusb_transfer* t = libusb_alloc_transfer(0);
 
t->dev_handle = pUsbDevHdl;
t->flags = LIBUSB_TRANSFER_FREE_TRANSFER | LIBUSB_TRANSFER_FREE_BUFFER;
t->endpoint = (unsigned char) (ep|0x80);
t->type = LIBUSB_TRANSFER_TYPE_BULK;
t->timeout = 1000;
t->status = 0;
t->buffer = malloc(length);
t->length = length;
t->actual_length = 0;
t->callback = cb;
t->user_data = 0;
 
rc = libusb_submit_transfer(t);
if (rc) bad_usbcall_exit("libusb_submit_transfer()", rc);
 
nreq += 1;
 
if (par_trace) {
prt_time();
printf("que_read: ep=%1d l=%5d\n", t->endpoint&(~0x80), t->length);
}
 
return;
}
 
/*----------------------------------------------------------*/
void send_msg()
{
int rc;
int i;
int nw = par_nwmsg;
int length;
uint16_t* pdat;
 
if (par_nwrndm) nw = 1 + (random() % par_nwmsg);
length = 2 * nw;
cur_nwmsg = nw;
 
struct libusb_transfer* t = libusb_alloc_transfer(0);
 
t->dev_handle = pUsbDevHdl;
t->flags = LIBUSB_TRANSFER_FREE_TRANSFER | LIBUSB_TRANSFER_FREE_BUFFER;
t->endpoint = 4;
t->type = LIBUSB_TRANSFER_TYPE_BULK;
t->timeout = 1000;
t->status = 0;
t->buffer = malloc(length);
t->length = length;
t->actual_length = 0;
t->callback = cb_rxblast;
t->user_data = 0;
 
pdat = (uint16_t*)(t->buffer);
for (i = 0; i < nw-1; i++) *pdat++ = dsc_rx.cval++;
*pdat++ = 0xdead;
rc = libusb_submit_transfer(t);
if (rc) bad_usbcall_exit("libusb_submit_transfer()", rc);
 
nreq += 1;
 
if (par_trace) {
prt_time();
printf("send_msg: ep=%1d l=%5d", t->endpoint&(~0x80), t->length);
printf(" buf=%4.4x,..", ((uint16_t*)(t->buffer))[0]);
for (i = nw-2; i < nw; i++) {
printf(",%4.4x", ((uint16_t*)(t->buffer))[i]);
}
printf("\n");
}
return;
}
 
/*----------------------------------------------------------*/
void cb_rxblast(struct libusb_transfer *t)
{
nreq -= 1;
 
if (par_trace) {
prt_time();
printf("cb_rx : ep=%d l=%5d al=%5d\n",
t->endpoint&(~0x80), t->length, t->actual_length);
}
 
bad_transfer_exit(t, "cb_rxblast");
dsc_rx.stat_nbuf += 1;
dsc_rx.stat_nbyt += t->actual_length;
 
if (par_nwmsg==0 && keep_running()) que_write();
 
return;
}
 
/*----------------------------------------------------------*/
void cb_txblast(struct libusb_transfer *t, int ep, libusb_transfer_cb_fn cb,
struct dsc_queue* pdsc)
{
nreq -= 1;
 
if (par_trace) {
prt_time();
printf("cb_txx: ep=%d l=%5d al=%5d\n",
t->endpoint&(~0x80), t->length, t->actual_length);
}
 
bad_transfer_exit(t, "cb_txblast");
if (t->actual_length > 0) {
uint16_t* pdat = (uint16_t*)(t->buffer);
int nw = t->actual_length/2;
int i;
if (pdsc->stat_nbuf == 0) pdsc->cval = pdat[0];
for (i = 0; i < nw; i++) {
uint16_t dat = *pdat++;
if (pdsc->cval != dat) {
prt_time();
printf("FAIL: on ep=%d seen %4.4x expect %4.4x after %10.0f char\n",
ep&(~0x80), dat, pdsc->cval, pdsc->stat_nbyt+2*i);
pdsc->cval = dat;
}
pdsc->cval += 1;
}
}
 
pdsc->stat_nbuf += 1;
pdsc->stat_nbyt += t->actual_length;
if (t->actual_length < t->length) pdsc->stat_npt += 1;
 
if (keep_running()) que_read(ep, pdsc->par_nfrm, cb);
}
 
/*----------------------------------------------------------*/
void cb_tx1blast(struct libusb_transfer *t)
{
cb_txblast(t, 6, cb_tx1blast, &dsc_tx1);
return;
}
 
/*----------------------------------------------------------*/
void cb_tx2blast(struct libusb_transfer *t)
{
cb_txblast(t, 8, cb_tx2blast, &dsc_tx2);
return;
}
 
/*----------------------------------------------------------*/
void cb_txloop(struct libusb_transfer *t)
{
nreq -= 1;
 
if (par_trace) {
prt_time();
printf("cb_txl: ep=%d l=%5d al=%5d\n",
t->endpoint&(~0x80), t->length, t->actual_length);
}
 
bad_transfer_exit(t, "cb_txloop");
if (t->actual_length > 0) {
uint16_t* pdat = (uint16_t*)(t->buffer);
int nw = t->actual_length/2;
int i;
 
for (i = 0; i < nw; i++) {
uint16_t dat = *pdat++;
 
if (cur_nwmsg > 0) {
uint16_t dat_exp = (cur_nwmsg>1) ? dsc_tx1.cval++ : 0xdead;
if (dat_exp != dat) {
prt_time();
printf("FAIL: on ep=6 seen %4.4x expect %4.4x after %10.0f char\n",
dat, dat_exp, dsc_tx1.stat_nbyt+2*i);
if (cur_nwmsg>1) dsc_tx1.cval = dat + 1;
}
cur_nwmsg -= 1;
if (cur_nwmsg==0 && dat==0xdead) stat_nmsg += 1;
} else {
prt_time();
printf("FAIL: on ep=6 seen %4.4x unexpected after %10.0f char\n",
dat, dsc_tx1.stat_nbyt+2*i);
}
}
}
 
dsc_tx1.stat_nbuf += 1;
dsc_tx1.stat_nbyt += t->actual_length;
if (t->actual_length < t->length) dsc_tx1.stat_npt += 1;
 
if (cur_nwmsg==0) { /* end of message seen */
if (keep_running()) {
send_msg();
} else {
if (par_trace) { prt_time(); printf("set endpoll = 1\n"); }
endpoll = 1;
}
}
que_read(6, dsc_tx1.par_nfrm, cb_txloop);
 
return;
}
 
/*----------------------------------------------------------*/
void tx_pipe_drain(int ep)
{
unsigned char buf[16384];
int ntrans;
int rc = libusb_bulk_transfer(pUsbDevHdl, ep|0x80,
buf, sizeof(buf), &ntrans, 10);
if (rc == LIBUSB_ERROR_TIMEOUT) return;
if (rc) bad_usbcall_exit("pipe drain: libusb_bulk_transfer()", rc);
 
fprintf(stderr, "tst_fx2loop-I: pipe drain for ep=%d: ntrans=%d\n",
ep&(~0x80), ntrans);
 
return;
}
 
/*--------------------------------------------------------------------------*/
void do_run()
{
int rc;
int fd_timer = -1;
int i;
struct itimerspec tspec;
struct dsc_queue dsc_rx_last = dsc_rx;
struct dsc_queue dsc_tx1_last = dsc_tx1;
struct dsc_queue dsc_tx2_last = dsc_tx2;
 
if (par_trace) {
prt_time();
printf("rx:nf=%d,nq=%d; tx1:nf=%d,nq=%d; tx2:nf=%d,nq=%d\n",
dsc_rx.par_nfrm, dsc_rx.par_nque,
dsc_tx1.par_nfrm, dsc_tx2.par_nque,
dsc_tx2.par_nfrm, dsc_tx2.par_nque);
}
 
/* setup pollfd list */
fd_timer = timerfd_create(CLOCK_MONOTONIC, TFD_NONBLOCK);
if (fd_timer < 0) bad_syscall_exit("timerfd_create() failed", fd_timer);
tspec.it_interval.tv_sec = 1;
tspec.it_interval.tv_nsec = 0;
tspec.it_value.tv_sec = 1;
tspec.it_value.tv_nsec = 0;
rc = timerfd_settime(fd_timer, 0, &tspec, NULL);
if (rc<0) bad_syscall_exit("timerfd_settime() failed", rc);
pollfd_fds[0].fd = fd_timer;
pollfd_fds[0].events = POLLIN;
pollfd_fds[0].revents = 0;
pollfd_nfds = 1;
 
pollfd_init();
 
/* setup loop */
if (par_nwmsg > 0) {
dsc_rx.par_nfrm = 0;
dsc_rx.par_nque = 0;
if (dsc_tx1.par_nfrm == 0) dsc_tx1.par_nfrm = 1;
if (dsc_tx1.par_nque == 0) dsc_tx1.par_nque = 1;
 
tx_pipe_drain(6); /* drain tx1 */
for (i = 0; i < dsc_tx1.par_nque; i++) /* prime tx1 */
que_read(6, dsc_tx1.par_nfrm, cb_txloop);
send_msg();
}
 
/* setup rxblast */
if (dsc_rx.par_nfrm > 0) {
int i;
if (dsc_rx.par_nque == 0) dsc_rx.par_nque = 1;
for (i = 0; i < dsc_rx.par_nque; i++) que_write();
}
 
/* setup txblast */
if (par_nwmsg==0 && dsc_tx1.par_nfrm>0) {
int i;
if (dsc_tx1.par_nque == 0) dsc_tx1.par_nque = 1;
for (i = 0; i < dsc_tx1.par_nque; i++)
que_read(6, dsc_tx1.par_nfrm, cb_tx1blast);
}
 
/* setup tx2blast */
if (dsc_tx2.par_nfrm > 0) {
int i;
if (dsc_tx2.par_nque == 0) dsc_tx2.par_nque = 1;
for (i = 0; i < dsc_tx2.par_nque; i++)
que_read(8, dsc_tx2.par_nfrm, cb_tx2blast);
}
 
t_start = get_time();
 
while(nreq>0 && endpoll==0) {
uint64_t tbuf;
rc = poll(pollfd_fds, pollfd_nfds, 2000);
if (rc==-1 && errno==EINTR) continue;
if (rc < 0) bad_syscall_exit("poll() failed", rc);
if (rc == 0) fprintf(stderr, "tst_fx2loop-I: poll() timeout\n");
 
if (par_trace) {
int i;
prt_time();
printf("poll: rc=%d:", rc);
for (i = 0; i < pollfd_nfds; i++) {
printf(" %d,%2.2x", pollfd_fds[i].fd, pollfd_fds[i].revents);
}
printf("\n");
}
 
if (pollfd_fds[0].revents == POLLIN) {
errno = EBADMSG; /* to be reported on short read */
rc = read(fd_timer, &tbuf, sizeof(tbuf));
if (rc != sizeof(tbuf)) bad_syscall_exit("read(fd_timer,...) failed", rc);
if (par_stat) {
prt_time();
if (par_nwmsg>0 || dsc_rx.par_nque>0) {
double nbuf = dsc_rx.stat_nbuf - dsc_rx_last.stat_nbuf;
double nbyt = dsc_rx.stat_nbyt - dsc_rx_last.stat_nbyt;
printf("rx: %5.0f,%7.1f ", nbuf, nbyt/1000.);
}
if (dsc_tx1.par_nque > 0 ) {
double nbuf = dsc_tx1.stat_nbuf - dsc_tx1_last.stat_nbuf;
double nbyt = dsc_tx1.stat_nbyt - dsc_tx1_last.stat_nbyt;
printf("tx1: %5.0f,%7.1f ", nbuf, nbyt/1000.);
}
if (dsc_tx2.par_nque > 0 ) {
double nbuf = dsc_tx2.stat_nbuf - dsc_tx2_last.stat_nbuf;
double nbyt = dsc_tx2.stat_nbyt - dsc_tx2_last.stat_nbyt;
printf("tx2: %5.0f,%7.1f ", nbuf, nbyt/1000.);
}
printf("\n");
dsc_rx_last = dsc_rx;
dsc_tx1_last = dsc_tx1;
dsc_tx2_last = dsc_tx2;
}
} else {
struct timeval tv;
tv.tv_sec = 0;
tv.tv_usec = 0;
rc = libusb_handle_events_timeout(pUsbContext, &tv);
//setting the timeval pointer to NULL should work, but doesn't (in 1.0.6)
//rc = libusb_handle_events_timeout(pUsbContext, 0);
if (rc) bad_usbcall_exit("libusb_handle_events_timeout()", rc);
}
}
 
return;
}
 
/*--------------------------------------------------------------------------*/
 
void do_stat()
{
printf("run statistics:\n");
printf("runtime : %13.3f\n", get_time()-t_start);
printf("nbuf_rx : %13.0f\n", dsc_rx.stat_nbuf);
printf("nbyt_rx : %13.0f\n", dsc_rx.stat_nbyt);
printf("nbuf_tx1 : %13.0f\n", dsc_tx1.stat_nbuf);
printf("nbyt_tx1 : %13.0f\n", dsc_tx1.stat_nbyt);
printf("npt_tx1 : %13.0f\n", dsc_tx1.stat_npt);
printf("nbuf_tx2 : %13.0f\n", dsc_tx2.stat_nbuf);
printf("nbyt_tx2 : %13.0f\n", dsc_tx2.stat_nbyt);
printf("npt_tx2 : %13.0f\n", dsc_tx2.stat_npt);
printf("nmsg : %13.0f\n", stat_nmsg);
return;
}
 
/*--------------------------------------------------------------------------*/
 
void usb_claim()
{
int rc = libusb_claim_interface(pUsbDevHdl, 0);
if (rc) bad_usbcall_exit("libusb_claim_interface()", rc);
return;
}
 
/*--------------------------------------------------------------------------*/
 
void usb_release()
{
int rc = libusb_release_interface(pUsbDevHdl, 0);
if (rc) bad_usbcall_exit("libusb_release_interface()", rc);
return;
}
 
/*--------------------------------------------------------------------------*/
 
char* usb_strerror(int rc)
{
switch(rc) {
case LIBUSB_SUCCESS:
return "";
case LIBUSB_ERROR_IO:
return "Input/output error";
case LIBUSB_ERROR_INVALID_PARAM:
return "Invalid parameter";
case LIBUSB_ERROR_ACCESS:
return "Access denied";
case LIBUSB_ERROR_NO_DEVICE:
return "No such device";
case LIBUSB_ERROR_NOT_FOUND:
return "Entity not found";
case LIBUSB_ERROR_BUSY:
return "Resource busy";
case LIBUSB_ERROR_TIMEOUT:
return "Operation timed out";
case LIBUSB_ERROR_OVERFLOW:
return "Overflow";
case LIBUSB_ERROR_PIPE:
return "Pipe error";
case LIBUSB_ERROR_INTERRUPTED:
return "System call interrupted";
case LIBUSB_ERROR_NO_MEM:
return "Insufficient memory";
case LIBUSB_ERROR_NOT_SUPPORTED:
return "Operation not supported";
case LIBUSB_ERROR_OTHER:
return "Other error";
default:
return "Unknown libusb error code";
}
}
 
/*--------------------------------------------------------------------------*/
 
void prt_time(void)
{
struct timeval tv;
struct timezone tz;
struct tm tmval;
 
gettimeofday(&tv, &tz);
localtime_r(&tv.tv_sec, &tmval);
printf("%02d:%02d:%02d.%06d: ", tmval.tm_hour, tmval.tm_min, tmval.tm_sec,
(int) tv.tv_usec);
}
 
/*--------------------------------------------------------------------------*/
 
double get_time(void)
{
struct timeval tv;
struct timezone tz;
gettimeofday(&tv, &tz);
return (double)tv.tv_sec + 1.e-6 * (double)tv.tv_usec;
}
 
/*--------------------------------------------------------------------------*/
 
void bad_syscall_exit(const char* text, int rc)
{
fprintf(stderr, "tst_fx2loop-F: %s failed with rc=%d errno=%d : %s\n",
text, rc, errno, strerror(errno));
exit(EXIT_FAILURE);
}
 
/*--------------------------------------------------------------------------*/
 
void bad_usbcall_exit(const char* text, int rc)
{
fprintf(stderr, "tst_fx2loop-F: %s failed with rc=%d: %s\n",
text, rc, usb_strerror(rc));
exit(EXIT_FAILURE);
}
 
/*--------------------------------------------------------------------------*/
 
void bad_transfer_exit(struct libusb_transfer *t, const char* text)
{
const char* etext = 0;
 
if (t->status == LIBUSB_TRANSFER_ERROR) etext = "ERROR";
if (t->status == LIBUSB_TRANSFER_STALL) etext = "STALL";
if (t->status == LIBUSB_TRANSFER_NO_DEVICE) etext = "NO_DEVICE";
if (t->status == LIBUSB_TRANSFER_OVERFLOW) etext = "OVERFLOW";
 
if (etext == 0) return;
fprintf(stderr, "tst_fx2loop-F: transfer failure in %s on ep=%d: %s\n",
text, (int)(t->endpoint&(~0x80)), etext);
exit(EXIT_FAILURE);
}
 
/rtl/sys_gen/tst_fx2loop/tst_fx2loop.vbom
0,0 → 1,10
# libs
../../vlib/slvtypes.vhd
../../vlib/comlib/comlib.vhd
../../bplib/fx2lib/fx2lib.vhd
tst_fx2looplib.vhd
# components
../../vlib/comlib/byte2word.vbom
../../vlib/comlib/word2byte.vbom
# design
tst_fx2loop.vhd
/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd
0,0 → 1,354
-- $Id: sys_tst_fx2loop_n2.vhd 461 2012-04-09 21:17:54Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_fx2loop_n2 - syn
-- Description: test of Cypress EZ-USB FX2 controller
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bpgen/sn_humanio
-- tst_fx2loop_hiomap
-- tst_fx2loop
-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"]
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
-- bplib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2012-04-09 461 13.3 O76d xc3s1200e-4 307 390 64 325 p 9.9 as2/100
-- 2012-04-09 461 13.3 O76d xc3s1200e-4 358 419 64 369 p 9.4 ic2/100
-- 2012-04-09 461 13.3 O76c xc3s1200e-4 436 537 96 476 p 8.9 ic3/100
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.1 now generic for as,ic,ic3 controllers
-- 2011-12-26 445 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_fx2looplib.all;
use work.fx2lib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
 
-- ----------------------------------------------------------------------------
 
entity sys_tst_fx2loop_n2 is -- top level
-- implements nexys2_aif + fx2 pins
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_tst_fx2loop_n2;
 
architecture syn of sys_tst_fx2loop_n2 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
 
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
 
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal LED_MAP : slv8 := (others=>'0');
 
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
 
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal FX2_TX2DATA : slv8 := (others=>'0');
signal FX2_TX2ENA : slbit := '0';
signal FX2_TX2BUSY : slbit := '1';
signal FX2_TX2AFULL : slbit := '0';
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
 
begin
 
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
 
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good for up to 127 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
 
HIO : sn_humanio
generic map (
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
 
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_fx2loop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
FX2_MONI => FX2_MONI,
SWI => SWI,
BTN => BTN,
LED => LED_MAP,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
 
proc_led: process (SWI, LED_MAP, FX2_TX2BUSY, FX2_TX2ENA,
FX2_TXBUSY, FX2_TXENA, FX2_RXHOLD, FX2_RXVAL)
begin
 
if SWI(4) = '1' then
LED(7) <= '0';
LED(6) <= '0';
LED(5) <= FX2_TX2BUSY;
LED(4) <= FX2_TX2ENA;
LED(3) <= FX2_TXBUSY;
LED(2) <= FX2_TXENA;
LED(1) <= FX2_RXHOLD;
LED(0) <= FX2_RXVAL;
else
LED <= LED_MAP;
end if;
end process proc_led;
TST : tst_fx2loop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
FX2_MONI => FX2_MONI,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY
);
 
FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate
CNTL : fx2_2fifoctl_as
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
PETOWIDTH => sys_conf_fx2_petowidth,
RDPWLDELAY => sys_conf_fx2_rdpwldelay,
RDPWHDELAY => sys_conf_fx2_rdpwhdelay,
WRPWLDELAY => sys_conf_fx2_wrpwldelay,
WRPWHDELAY => sys_conf_fx2_wrpwhdelay,
FLAGDELAY => sys_conf_fx2_flagdelay)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_AS;
 
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC;
 
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
CNTL : fx2_3fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
TX2AFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY,
TX2AFULL => FX2_TX2AFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC3;
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
 
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
 
O_TXD <= I_RXD; -- loop-back in serial port...
end syn;
 
/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom
0,0 → 1,30
# this is the vbom for the 'generic' top level entity
# to be referenced in the vbom's of the specific systems
# ./as/sys_tst_fx2loop_as_n2
# ./ic/sys_tst_fx2loop_ic_n2
# ./ic3/sys_tst_fx2loop_ic3_n2
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../bplib/bpgen/bpgenlib.vbom
../tst_fx2looplib.vbom
../../../bplib/fx2lib/fx2lib.vhd
../../../bplib/nxcramlib/nxcramlib.vhd
${sys_conf}
# components
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/sn_humanio.vbom
../tst_fx2loop_hiomap.vbom
../tst_fx2loop.vbom
../../../bplib/fx2lib/fx2_2fifoctl_as.vbom
../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom
../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom
../../../bplib/nxcramlib/nx_cram_dummy.vbom
# design
sys_tst_fx2loop_n2.vhd
## no @ucf_cpp
 
/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_conf.vhd
0,0 → 1,58
-- $Id: sys_conf.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_fx2loop_ic_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package sys_conf is
 
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 2;
 
constant sys_conf_fx2_type : string := "ic2";
 
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
 
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
 
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
 
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
 
end package sys_conf;
/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.mfset
0,0 → 1,63
# $Id: sys_tst_fx2loop_ic_n2.mfset 453 2012-01-15 17:51:18Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
 
Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
 
Node <TST/R_REGS.tx2data_\d*> of sequential type is unconnected
Node <HIO/HIO/IOB_BTN/R_DI_\d> of sequential type is unconnected
Node <HIO/HIO/DEB.DEB_BTN/R_REGS\..*_\d> of sequential type is unconnected
Node <TST/TX2W2B/R_REGS.datl_\d*> of sequential type is unconnected
Node <TST/TX2W2B/R_REGS.dath_\d*> of sequential type is unconnected
 
Signal <FX2_TX2DATA> is assigned but never used
 
Input <BTN> is never used
Input <SWI<4>> is never used
Input <FX2_MONI.pktend> is never used
Input <FX2_MONI.slrd> is never used
Input <FX2_MONI.slwr> is never used
Input <I_MEM_WAIT> is never used
 
Signal <TXODD> is assigned but never used
Signal <TX2ODD> is assigned but never used
Signal <RXODD> is assigned but never used
 
#
# ----------------------------------------------------------------------------
[tra]
INFO:.* - TNM 'I_CLK50', used in period specification.*was traced into DCM_SP
The Offset constraint .*, is specified without a duration
 
#
# ----------------------------------------------------------------------------
[map]
The signal <I_MEM_WAIT_IBUF> is incomplete
The signal <I_BTN<1>_IBUF> is incomplete
The signal <I_BTN<2>_IBUF> is incomplete
The signal <I_BTN<3>_IBUF> is incomplete
INFO:.*
 
#
# ----------------------------------------------------------------------------
[par]
A clock IOB / clock component pair have been found that are not placed at
The Offset constraint .*, is specified without a duration
The signal I_MEM_WAIT_IBUF has no load
The signal I_BTN<1>_IBUF has no load
The signal I_BTN<2>_IBUF has no load
The signal I_BTN<3>_IBUF has no load
There are 4 loadless signals in this design
 
#
# ----------------------------------------------------------------------------
[bgn]
Spartan-3 1200E and 1600E devices do not support bitstream
To achieve optimal frequency synthesis performance .* consult
The signal <I_MEM_WAIT_IBUF> is incomplete
The signal <I_BTN<1>_IBUF> is incomplete
The signal <I_BTN<2>_IBUF> is incomplete
The signal <I_BTN<3>_IBUF> is incomplete
/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.ucf_cpp
0,0 → 1,15
## $Id: sys_tst_fx2loop_ic_n2.ucf_cpp 453 2012-01-15 17:51:18Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-12-26 445 1.0 Initial version
##
 
NET "I_CLK50" TNM_NET = "I_CLK50";
TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK50";
OFFSET = OUT 20 ns AFTER "I_CLK50";
 
#include "bplib/nexys2/nexys2_pins.ucf"
#include "bplib/nexys2/nexys2_pins_fx2.ucf"
#include "bplib/nexys2/nexys2_time_fx2_ic.ucf"
/rtl/sys_gen/tst_fx2loop/nexys2/ic/Makefile
0,0 → 1,29
# $Id: Makefile 453 2012-01-15 17:51:18Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-01-15 453 1.0 Initial version
#
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
ISE_BOARD = nexys2
ISE_PATH = xc3s1200e-fg320-4
FX2_FILE = nexys2_jtag_2fifo_ic.ihx
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make/generic_ghdl.mk
#
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
#
/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.vbom
0,0 → 1,8
# conf
sys_conf = sys_conf.vhd
# libs
# components
# design
../sys_tst_fx2loop_n2.vbom
@ucf_cpp: sys_tst_fx2loop_ic_n2.ucf
@top: sys_tst_fx2loop_n2
/rtl/sys_gen/tst_fx2loop/nexys2/ic/.cvsignore
0,0 → 1,4
_impactbatch.log
sys_tst_fx2loop_ic_n2.ucf
*.dep_ucf_cpp
*.svf
/rtl/sys_gen/tst_fx2loop/nexys2/ic
rtl/sys_gen/tst_fx2loop/nexys2/ic Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_fx2loop_ic_n2.ucf +*.dep_ucf_cpp +*.svf Index: rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom =================================================================== --- rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom (nonexistent) +++ rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom (revision 17) @@ -0,0 +1,8 @@ +# conf +sys_conf = sys_conf.vhd +# libs +# components +# design +../sys_tst_fx2loop_n2.vbom +@ucf_cpp: sys_tst_fx2loop_ic3_n2.ucf +@top: sys_tst_fx2loop_n2 Index: rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd =================================================================== --- rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd (nonexistent) +++ rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd (revision 17) @@ -0,0 +1,58 @@ +-- $Id: sys_conf.vhd 453 2012-01-15 17:51:18Z mueller $ +-- +-- Copyright 2012- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_fx2loop_ic3_n2 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.3; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2012-01-15 453 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkfx_divide : positive := 1; + constant sys_conf_clkfx_multiply : positive := 2; + + constant sys_conf_fx2_type : string := "ic3"; + + -- dummy values defs for generic parameters of as controller + constant sys_conf_fx2_rdpwldelay : positive := 1; + constant sys_conf_fx2_rdpwhdelay : positive := 1; + constant sys_conf_fx2_wrpwldelay : positive := 1; + constant sys_conf_fx2_wrpwhdelay : positive := 1; + constant sys_conf_fx2_flagdelay : positive := 1; + + -- pktend timer setting + -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) + constant sys_conf_fx2_petowidth : positive := 10; + + constant sys_conf_fx2_ccwidth : positive := 5; + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- derived constants + + constant sys_conf_clksys : integer := + (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + +end package sys_conf; Index: rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset =================================================================== --- rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset (nonexistent) +++ rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset (revision 17) @@ -0,0 +1,58 @@ +# $Id: sys_tst_fx2loop_ic3_n2.mfset 453 2012-01-15 17:51:18Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Mux is complete : default of case is discarded + +Unconnected output port 'LOCKED' of component 'dcm_sfs' +Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' + +Node of sequential type is unconnected +Node of sequential type is unconnected + +Input is never used +Input > is never used +Input is never used +Input is never used +Input is never used +Input is never used + +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used + +# +# ---------------------------------------------------------------------------- +[tra] +INFO:.* - TNM 'I_CLK50', used in period specification.*was traced into DCM_SP +The Offset constraint .*, is specified without a duration + +# +# ---------------------------------------------------------------------------- +[map] +The signal is incomplete +The signal _IBUF> is incomplete +The signal _IBUF> is incomplete +The signal _IBUF> is incomplete +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] +A clock IOB / clock component pair have been found that are not placed at +The Offset constraint .*, is specified without a duration +The signal I_MEM_WAIT_IBUF has no load +The signal I_BTN<1>_IBUF has no load +The signal I_BTN<2>_IBUF has no load +The signal I_BTN<3>_IBUF has no load +There are 4 loadless signals in this design + +# +# ---------------------------------------------------------------------------- +[bgn] +Spartan-3 1200E and 1600E devices do not support bitstream +To achieve optimal frequency synthesis performance .* consult +The signal is incomplete +The signal _IBUF> is incomplete +The signal _IBUF> is incomplete +The signal _IBUF> is incomplete Index: rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp =================================================================== --- rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp (nonexistent) +++ rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp (revision 17) @@ -0,0 +1,15 @@ +## $Id: sys_tst_fx2loop_ic3_n2.ucf_cpp 453 2012-01-15 17:51:18Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-12-26 445 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +#include "bplib/nexys2/nexys2_pins.ucf" +#include "bplib/nexys2/nexys2_pins_fx2.ucf" +#include "bplib/nexys2/nexys2_time_fx2_ic.ucf" Index: rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile =================================================================== --- rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile (nonexistent) +++ rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile (revision 17) @@ -0,0 +1,29 @@ +# $Id: Makefile 453 2012-01-15 17:51:18Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2012-01-15 453 1.0 Initial version +# +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +ISE_BOARD = nexys2 +ISE_PATH = xc3s1200e-fg320-4 +FX2_FILE = nexys2_jtag_3fifo_ic.ihx +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +# Index: rtl/sys_gen/tst_fx2loop/nexys2/ic3/.cvsignore =================================================================== --- rtl/sys_gen/tst_fx2loop/nexys2/ic3/.cvsignore (nonexistent) +++ rtl/sys_gen/tst_fx2loop/nexys2/ic3/.cvsignore (revision 17) @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_fx2loop_ic3_n2.ucf +*.dep_ucf_cpp +*.svf Index: rtl/sys_gen/tst_fx2loop/nexys2/ic3 =================================================================== --- rtl/sys_gen/tst_fx2loop/nexys2/ic3 (nonexistent) +++ rtl/sys_gen/tst_fx2loop/nexys2/ic3 (revision 17)
rtl/sys_gen/tst_fx2loop/nexys2/ic3 Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_fx2loop_ic3_n2.ucf +*.dep_ucf_cpp +*.svf Index: rtl/sys_gen/tst_fx2loop/nexys2 =================================================================== --- rtl/sys_gen/tst_fx2loop/nexys2 (nonexistent) +++ rtl/sys_gen/tst_fx2loop/nexys2 (revision 17)
rtl/sys_gen/tst_fx2loop/nexys2 Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd =================================================================== --- rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd (nonexistent) +++ rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd (revision 17) @@ -0,0 +1,109 @@ +-- $Id: tst_fx2looplib.vhd 453 2012-01-15 17:51:18Z mueller $ +-- +-- Copyright 2011-2012 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: tst_fx2looplib +-- Description: Definitions for tst_fx2loop records and helpers +-- +-- Dependencies: - +-- Tool versions: xst 13.3; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2012-01-15 453 1.1 drop pecnt, add rxhold,(tx|tx2)busy in hio_stat +-- 2011-12-26 445 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.fx2lib.all; + +package tst_fx2looplib is + + constant c_ctltyp_2fifo_as : integer := 0; -- fx2ctl type: 2fifo_as + constant c_ctltyp_2fifo_ic : integer := 1; -- fx2ctl type: 2fifo_ic + constant c_ctltyp_3fifo_ic : integer := 2; -- fx2ctl type: 3fifo_ic + + constant c_mode_idle : slv2 := "00"; -- mode: idle (no tx activity) + constant c_mode_rxblast : slv2 := "01"; -- mode: rxblast (check rx activity) + constant c_mode_txblast : slv2 := "10"; -- mode: txblast (saturate tx) + constant c_mode_loop : slv2 := "11"; -- mode: loop (rx->tx loop-back) + + type hio_cntl_type is record -- humanio controls + mode : slv2; -- mode (idle,(tx|tx)blast,loop) + tx2blast : slbit; -- enable tx2 blast + throttle : slbit; -- enable 1 msec tx throttling + end record hio_cntl_type; + + constant hio_cntl_init : hio_cntl_type := ( + c_mode_idle, -- mode + '0','0' -- tx2blast,throttle + ); + + type hio_stat_type is record -- humanio status + rxhold : slbit; -- rx hold + txbusy : slbit; -- tx busy + tx2busy : slbit; -- tx2 busy + rxsecnt : slv16; -- rx sequence error counter + rxcnt : slv32; -- rx word counter + txcnt : slv32; -- tx word counter + tx2cnt : slv32; -- tx2 word counter + end record hio_stat_type; + + constant hio_stat_init : hio_stat_type := ( + '0','0','0', -- rxhold,txbusy,tx2busy + (others=>'0'), -- rxsecnt + (others=>'0'), -- rxcnt + (others=>'0'), -- txcnt + (others=>'0') -- tx2cnt + ); + +-- ------------------------------------- + +component tst_fx2loop is -- tester for serport components + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CE_MSEC : in slbit; -- msec pulse + HIO_CNTL : in hio_cntl_type; -- humanio controls + HIO_STAT : out hio_stat_type; -- humanio status + FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor + RXDATA : in slv8; -- receiver data out + RXVAL : in slbit; -- receiver data valid + RXHOLD : out slbit; -- receiver data hold + TXDATA : out slv8; -- transmit data in + TXENA : out slbit; -- transmit data enable + TXBUSY : in slbit; -- transmit busy + TX2DATA : out slv8; -- transmit 2 data in + TX2ENA : out slbit; -- transmit 2 data enable + TX2BUSY : in slbit -- transmit 2 busy + ); +end component; + +component tst_fx2loop_hiomap is -- default human I/O mapper + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + HIO_CNTL : out hio_cntl_type; -- tester controls from hio + HIO_STAT : in hio_stat_type; -- tester status to display by hio + FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor to display by hio + SWI : in slv8; -- switch settings + BTN : in slv4; -- button settings + LED : out slv8; -- led data + DSP_DAT : out slv16; -- display data + DSP_DP : out slv4 -- display decimal points + ); +end component; + +end package tst_fx2looplib; Index: rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vbom =================================================================== --- rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vbom (nonexistent) +++ rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vbom (revision 17) @@ -0,0 +1,4 @@ +# libs +../../vlib/slvtypes.vhd +../../bplib/fx2lib/fx2lib.vhd +tst_fx2looplib.vhd Index: rtl/sys_gen/tst_fx2loop/.cvsignore =================================================================== --- rtl/sys_gen/tst_fx2loop/.cvsignore (nonexistent) +++ rtl/sys_gen/tst_fx2loop/.cvsignore (revision 17) @@ -0,0 +1,2 @@ +tst_fx2loop +tst_fx2loop_si Index: rtl/sys_gen/tst_fx2loop/Makefile =================================================================== --- rtl/sys_gen/tst_fx2loop/Makefile (nonexistent) +++ rtl/sys_gen/tst_fx2loop/Makefile (revision 17) @@ -0,0 +1,34 @@ +# $Id: Makefile 461 2012-04-09 21:17:54Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2012-02-26 458 1.1 add tst_fx2loop_si +# 2011-12-26 445 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +ISE_PATH = xc3s1200e-fg320-4 +# +.PHONY : all clean realclean +# +all : tst_fx2loop tst_fx2loop_si +# +clean : ise_clean +# +realclean : + rm -f tst_fx2loop tst_fx2loop_si +# +CFLAGS = -Wall -O2 -g -lusb-1.0 +# +tst_fx2loop : tst_fx2loop.c + ${CC} ${CFLAGS} -o tst_fx2loop tst_fx2loop.c +tst_fx2loop_si : tst_fx2loop_si.c + ${CC} ${CFLAGS} -o tst_fx2loop_si tst_fx2loop_si.c +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +include $(VBOM_all:.vbom=.dep_xst) +# Index: rtl/sys_gen/tst_fx2loop =================================================================== --- rtl/sys_gen/tst_fx2loop (nonexistent) +++ rtl/sys_gen/tst_fx2loop (revision 17)
rtl/sys_gen/tst_fx2loop Property changes : Added: svn:ignore ## -0,0 +1,34 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tst_fx2loop +tst_fx2loop_si Index: rtl/sys_gen/tst_rlink/nexys2/tb/tb_tst_rlink_n2.vbom =================================================================== --- rtl/sys_gen/tst_rlink/nexys2/tb/tb_tst_rlink_n2.vbom (revision 16) +++ rtl/sys_gen/tst_rlink/nexys2/tb/tb_tst_rlink_n2.vbom (revision 17) @@ -1,7 +1,7 @@ # configure tb_nexsy2_fusp with sys_tst_rlink_n2 target; # use vhdl configure file (tb_tst_rlink_n2.vhd) to allow # that all configurations will co-exist in work library -nexys2_aif : ../sys_tst_rlink_n2.vbom +${nexys2_aif := ../sys_tst_rlink_n2.vbom} sys_conf = sys_conf_sim.vhd ../../../../bplib/nexys2/tb/tb_nexys2_fusp.vbom tb_tst_rlink_n2.vhd Index: rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd =================================================================== --- rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd (revision 16) +++ rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd (revision 17) @@ -1,4 +1,4 @@ --- $Id: sys_tst_rlink_n2.vhd 442 2011-12-23 10:03:28Z mueller $ +-- $Id: sys_tst_rlink_n2.vhd 465 2012-12-27 21:29:38Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -31,6 +31,7 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2012-12-27 453 13.3 O76d xc3s1200e-4 754 1605 96 1057 t 14.5 -- 2011-12-18 440 13.1 O40d xc3s1200e-4 754 1605 96 1057 t 16.8 -- 2011-06-26 385 12.1 M53d xc3s1200e-4 688 1500 68 993 t 16.2 -- 2011-04-02 375 12.1 M53d xc3s1200e-4 688 1572 68 994 t 13.8 @@ -38,6 +39,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-12-23 444 1.2 remove clksys output hack -- 2011-12-18 440 1.1.6 use now rbd_tst_rlink and rlink_sp1c -- 2011-11-26 433 1.1.5 use nx_cram_dummy now -- 2011-11-23 432 1.1.4 update O_FLA_CE_N usage @@ -49,21 +51,21 @@ ------------------------------------------------------------------------------ -- Usage of Nexys 2 Switches, Buttons, LEDs: -- --- SWI(7:2): no function (only connected to sn_humanio_rbus) --- SWI(1): 1 enable XON --- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob +-- SWI(7:2) no function (only connected to sn_humanio_rbus) +-- (1) 1 enable XON +-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob -- 1 -> Pmod B/top RS232 port / -- --- LED(7): SER_MONI.abact --- LED(6:2): no function (only connected to sn_humanio_rbus) --- LED(0): timer 0 busy --- LED(1): timer 1 busy +-- LED(7) SER_MONI.abact +-- (6:2) no function (only connected to sn_humanio_rbus) +-- (0) timer 0 busy +-- (1) timer 1 busy -- -- DSP: SER_MONI.clkdiv (from auto bauder) --- DP(3): not SER_MONI.txok (shows tx back preasure) --- DP(2): SER_MONI.txact (shows tx activity) --- DP(1): not SER_MONI.rxok (shows rx back preasure) --- DP(0): SER_MONI.rxact (shows rx activity) +-- DP(3) not SER_MONI.txok (shows tx back preasure) +-- (2) SER_MONI.txact (shows tx activity) +-- (1) not SER_MONI.rxok (shows rx back preasure) +-- (0) SER_MONI.rxact (shows rx activity) -- library ieee; @@ -85,7 +87,6 @@ -- implements nexys2_fusp_aif port ( I_CLK50 : in slbit; -- 50 MHz clock - O_CLKSYS : out slbit; -- DCM derived system clock I_RXD : in slbit; -- receive data (board view) O_TXD : out slbit; -- transmit data (board view) I_SWI : in slv8; -- n2 switches @@ -162,8 +163,6 @@ LOCKED => open ); - O_CLKSYS <= CLK; - CLKDIV : clkdivce generic map ( CDUWIDTH => 7,
/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom
7,7 → 7,7
../../../vlib/rlink/rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/nxcramlib/nxcramlib.vhd
sys_conf : sys_conf.vhd
${sys_conf := sys_conf.vhd}
# components
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
/rtl/sys_gen/tst_rlink/nexys2/Makefile
1,4 → 1,4
# $Id: Makefile 410 2011-09-18 11:23:09Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
16,7 → 16,7
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_rlink_n2.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
/rtl/sys_gen/tst_rlink/nexys3/tb/tb_tst_rlink_n3.vbom
1,7 → 1,7
# configure tb_nexsy3_fusp with sys_tst_rlink_n3 target;
# use vhdl configure file (tb_tst_rlink_n3.vhd) to allow
# that all configurations will co-exist in work library
nexys3_fusp_aif : ../sys_tst_rlink_n3.vbom
${nexys3_fusp_aif := ../sys_tst_rlink_n3.vbom}
sys_conf = sys_conf_sim.vhd
../../../../bplib/nexys3/tb/tb_nexys3_fusp.vbom
tb_tst_rlink_n3.vhd
/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vbom
7,7 → 7,7
../../../vlib/rlink/rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/nxcramlib/nxcramlib.vhd
sys_conf : sys_conf.vhd
${sys_conf := sys_conf.vhd}
# components
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
/rtl/sys_gen/tst_rlink/nexys3/Makefile
1,4 → 1,4
# $Id: Makefile 433 2011-11-27 22:04:39Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
18,7 → 18,7
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_rlink_n3.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
/rtl/sys_gen/tst_rlink/s3board/tb/tb_tst_rlink_s3.vbom
1,7 → 1,7
# configure tb_s3board_fusp with sys_tst_rlink_s3 target;
# use vhdl configure file (tb_tst_rlink_s3.vhd) to allow
# that all configurations will co-exist in work library
s3board_aif : ../sys_tst_rlink_s3.vbom
${s3board_aif := ../sys_tst_rlink_s3.vbom}
sys_conf = sys_conf_sim.vhd
../../../../bplib/s3board/tb/tb_s3board_fusp.vbom
tb_tst_rlink_s3.vhd
/rtl/sys_gen/tst_rlink/s3board/Makefile
1,4 → 1,4
# $Id: Makefile 442 2011-12-23 10:03:28Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
15,7 → 15,7
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_rlink_s3.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
/rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vbom
6,7 → 6,7
../../../vlib/rlink/rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/s3board/s3boardlib.vbom
sys_conf : sys_conf.vhd
${sys_conf := sys_conf.vhd}
# components
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd
1,4 → 1,4
-- $Id: sys_w11a_n2.vhd 440 2011-12-18 20:08:09Z mueller $
-- $Id: sys_w11a_n2.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
64,6 → 64,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.3 remove clksys output hack
-- 2011-12-18 440 1.2.7 use rlink_sp1c
-- 2011-11-26 433 1.2.6 use nx_cram_(dummy|memctl_as) now
-- 2011-11-23 432 1.2.5 update O_FLA_CE_N usage
142,7 → 143,6
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
265,8 → 265,6
LOCKED => open
);
 
O_CLKSYS <= CLK;
 
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
/rtl/sys_gen/w11a/nexys2/Makefile
1,4 → 1,4
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
16,7 → 16,7
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_w11a_n2.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
sys_w11a_n2.mcs : sys_w11a_n2.bit
promgen -w -x xcf04s -p mcs -u 0 sys_w11a_n2
/rtl/sys_gen/w11a/nexys3/Makefile
1,4 → 1,4
# $Id: Makefile 430 2011-11-20 20:48:39Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
18,7 → 18,7
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_w11a_n3.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
/rtl/sys_gen/w11a/s3board/Makefile
1,4 → 1,4
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
21,7 → 21,7
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_w11a_s3.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
sys_w11a_s3.mcs : sys_w11a_s3.bit
promgen -w -x xcf04s -p mcs -u 0 sys_w11a_s3
/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vhd
1,4 → 1,4
-- $Id: sys_tst_snhumanio_n2.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: sys_tst_snhumanio_n2.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
31,6 → 31,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 remove clksys output hack
-- 2011-11-26 433 1.0.3 use nx_cram_dummy now
-- 2011-11-23 432 1.0.3 update O_FLA_CE_N usage
-- 2011-10-25 419 1.0.2 get entity name right...
54,7 → 55,6
-- implements nexys2_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
94,7 → 94,6
RESET <= '0'; -- so far not used
CLK <= I_CLK50;
O_CLKSYS <= CLK;
 
CLKDIV : clkdivce
generic map (
/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vbom
3,7 → 3,7
../../../vlib/genlib/genlib.vhd
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/nxcramlib/nxcramlib.vhd
sys_conf : sys_conf.vhd
${sys_conf := sys_conf.vhd}
# components
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/sn_humanio.vbom
/rtl/sys_gen/tst_snhumanio/nexys2/Makefile
1,4 → 1,4
# $Id: Makefile 410 2011-09-18 11:23:09Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
15,7 → 15,7
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_snhumanio_n2.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
/rtl/sys_gen/tst_snhumanio/nexys3/sys_tst_snhumanio_n3.vbom
3,7 → 3,7
../../../vlib/genlib/genlib.vhd
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/nxcramlib/nxcramlib.vhd
sys_conf : sys_conf.vhd
${sys_conf := sys_conf.vhd}
# components
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/sn_humanio.vbom
/rtl/sys_gen/tst_snhumanio/nexys3/Makefile
1,4 → 1,4
# $Id: Makefile 433 2011-11-27 22:04:39Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
18,7 → 18,7
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_snhumanio_n3.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vbom
2,7 → 2,7
../../../vlib/slvtypes.vhd
../../../vlib/genlib/genlib.vhd
../../../bplib/bpgen/bpgenlib.vbom
sys_conf : sys_conf.vhd
${sys_conf := sys_conf.vhd}
# components
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/sn_humanio_demu.vbom
/rtl/sys_gen/tst_snhumanio/atlys/Makefile
1,4 → 1,4
# $Id: Makefile 414 2011-10-11 19:38:12Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
18,7 → 18,7
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_snhumanio_atlys.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.vbom
3,7 → 3,7
../../../vlib/genlib/genlib.vhd
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/s3board/s3boardlib.vhd
sys_conf : sys_conf.vhd
${sys_conf := sys_conf.vhd}
# components
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/sn_humanio.vbom
/rtl/sys_gen/tst_snhumanio/s3board/Makefile
1,4 → 1,4
# $Id: Makefile 410 2011-09-18 11:23:09Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
15,7 → 15,7
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_snhumanio_s3.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vhd
0,0 → 1,381
-- $Id: sys_tst_rlink_cuff_n2.vhd 467 2013-01-02 19:49:05Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_cuff_n2 - syn
-- Description: rlink tester design for nexys2 with fx2 interface
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"]
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
-- tst_rlink_cuff
-- bplib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2012-12-29 466 13.3 O76d xc3s1200e-4 808 1739 160 1172 p 16.3 as2/ 50
-- 2013-01-02 467 13.3 O76d xc3s1200e-4 843 1792 160 1209 p 15.2 ic2/ 50
-- 2012-12-29 466 13.3 O76d xc3s1200e-4 863 1850 192 1266 p 13.6 ic3/ 50
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 1.0 Initial version; derived from sys_tst_fx2loop_n2
-- the now obsoleted sys_tst_rlink_n2_cuff design
------------------------------------------------------------------------------
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
-- SWI(7:3) no function (only connected to sn_humanio_rbus)
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- (1) 1 enable XON
-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7) SER_MONI.abact
-- (6:2) no function (only connected to sn_humanio_rbus)
-- (0) timer 0 busy
-- (1) timer 1 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- for SWI(2)='0' (serport)
-- DP(3) not SER_MONI.txok (shows tx back preasure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back preasure)
-- (0) SER_MONI.rxact (shows rx activity)
-- for SWI(2)='1' (fx2)
-- DP(3) FX2_TX2BUSY (shows tx2 back preasure)
-- (2) FX2_TX2ENA(stretched) (shows tx2 activity)
-- (1) FX2_TXENA(streched) (shows tx activity)
-- (0) FX2_RXVAL(stretched) (shows rx activity)
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.rblib.all;
use work.fx2lib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
 
-- ----------------------------------------------------------------------------
 
entity sys_tst_rlink_cuff_n2 is -- top level
-- implements nexys2_fusp_cuff_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_tst_rlink_cuff_n2;
 
architecture syn of sys_tst_rlink_cuff_n2 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
 
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXSD : slbit := '0';
signal TXSD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
 
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
 
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal FX2_TX2DATA : slv8 := (others=>'0');
signal FX2_TX2ENA : slbit := '0';
signal FX2_TX2BUSY : slbit := '0';
signal FX2_TX2AFULL : slbit := '0';
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
 
constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
 
begin
 
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
 
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good for up to 127 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
 
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXSD,
TXD => TXSD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
 
HIO : sn_humanio_rbus
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
 
FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate
CNTL : fx2_2fifoctl_as
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
PETOWIDTH => sys_conf_fx2_petowidth,
RDPWLDELAY => sys_conf_fx2_rdpwldelay,
RDPWHDELAY => sys_conf_fx2_rdpwhdelay,
WRPWLDELAY => sys_conf_fx2_wrpwldelay,
WRPWHDELAY => sys_conf_fx2_wrpwhdelay,
FLAGDELAY => sys_conf_fx2_flagdelay)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_AS;
 
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC;
 
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
CNTL : fx2_3fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
TX2AFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY,
TX2AFULL => FX2_TX2AFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC3;
TST : entity work.tst_rlink_cuff
port map (
CLK => CLK,
RESET => '0',
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RB_MREQ_TOP => RB_MREQ,
RB_SRES_TOP => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
RXSD => RXSD,
TXSD => TXSD,
RTS_N => RTS_N,
CTS_N => CTS_N,
FX2_RXDATA => FX2_RXDATA,
FX2_RXVAL => FX2_RXVAL,
FX2_RXHOLD => FX2_RXHOLD,
FX2_TXDATA => FX2_TXDATA,
FX2_TXENA => FX2_TXENA,
FX2_TXBUSY => FX2_TXBUSY,
FX2_TX2DATA => FX2_TX2DATA,
FX2_TX2ENA => FX2_TX2ENA,
FX2_TX2BUSY => FX2_TX2BUSY,
FX2_MONI => FX2_MONI
);
 
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
 
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
 
/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.mfset
0,0 → 1,104
# $Id: sys_tst_rlink_cuff_ic_n2.mfset 466 2012-12-30 13:26:55Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
 
Register <R_MONI_C.fifo_ep8> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_C.flag_ep8_full> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_C.flag_ep8_almost> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_S.flag_ep8_almost> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_S.flag_ep8_full> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_S.fifo_ep8> in unit <fx2_2fifoctl_ic> has a constant value
 
Unconnected output port 'SIZE' of component 'fifo_1c_dram'
Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen'
Unconnected output port 'RL_MONI' of component 'rlink_core8'
 
Input <I_MEM_WAIT> is never used
Input <RB_MREQ.din<\d+:\d+>> is never used
Input <RB_MREQ.init> is never used
Input <BTN> is never used
Input <SWI<7:3>> is never used
Input <SWI<0>> is never used
Input <FX2_MONI.pktend> is never used
Input <FX2_MONI.slrd> is never used
Input <FX2_MONI.slwr> is never used
Input <FX2_MONI.flag_ep4_empty> is never used
Input <FX2_MONI.flag_ep4_almost> is never used
Input <FX2_MONI.flag_ep6_full> is never used
Input <FX2_MONI.flag_ep6_almost> is never used
Input <FX2_MONI.flag_ep8_full> is never used
Input <FX2_MONI.flag_ep8_almost> is never used
Input <FX2_MONI.fifo_ep4> is never used
Input <FX2_MONI.fifo_ep6> is never used
Input <FX2_MONI.fifo_ep8> is never used
 
Output <FX2_TX2DATA> is never assigned
 
Signal <L_DO<17:16>> is assigned but never used
Signal <FIFO_SIZE> is assigned but never used
Signal <RXFIFO_SIZE<2:0>> is assigned but never used
Signal <RB_LAM_TEST<1:0>> is assigned but never used
Signal <SER_MONI.rxovr> is assigned but never used
Signal <SER_MONI.rxerr> is assigned but never used
Signal <SER_MONI.abdone> is assigned but never used
Signal <STAT<7:2>> is assigned but never used
Signal <FX2_FLAG_N<3>> is assigned but never used
Signal <FX2_TXAFULL> is assigned but never used
Signal <FX2_RXAEMPTY> is assigned but never used
Signal <FX2_TX2ENA> is assigned but never used
Signal <FX2_TX2DATA> is assigned but never used
Signal <TXSIZE_FX2> is assigned but never used
 
Signal <FX2_TX2ENA_L> is used but never assigned
Signal <RESET> is used but never assigned
Signal <FX2_TX2BUSY> is used but never assigned
 
Signal <FX2_TX2AFULL> is never used or assigned
 
FF/Latch <R_REGS.rbre> in Unit <rlink_core> is equivalent
 
FF/Latch <R_REGS.ucnt_6> has a constant value of 0
FF/Latch <HIO/R_REGS.ledin_[2-6]> has a constant value of 0
FF/Latch <R_REGS.rxpipe> has a constant value of 0
FF/Latch <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW].rst[rw]> has a constant value of 0
FF/Latch <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW].rst[rw]_(c|s|sc|ss)> has a constant value of 0
 
Node <HIO/R_REGS.swieff_[3-7]> of sequential type is unconnected
Node <HIO/R_REGS.swi_[3-7]> of sequential type is unconnected
Node <HIO/R_REGS.btn_[0-3]> of sequential type is unconnected
Node <HIO/R_REGS.btneff_[0-3]> of sequential type is unconnected
Node <TST/SERPORT/XONRX/R_REGS.rxovr> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS.moneop> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS.monlamp> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS.monattn> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/R_MONI_S..*> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/R_MONI_C..*> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/R_REGS..*> of sequential type is unconnected
 
Node <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW].size[rw]_[0-4]> of sequential type is unconnected
#
# ----------------------------------------------------------------------------
[tra]
 
#
# ----------------------------------------------------------------------------
[map]
The signal <I_MEM_WAIT_IBUF> is incomplete
Signal I_FX2_FLAG<3> connected to top level port I_FX2_FLAG<3> has been removed
INFO:.*
 
#
# ----------------------------------------------------------------------------
[par]
The signal I_MEM_WAIT_IBUF has no load
There are 1 loadless signals in this design
This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied
#
# ----------------------------------------------------------------------------
[bgn]
Spartan-3 1200E and 1600E devices do not support bitstream
The signal <I_MEM_WAIT_IBUF> is incomplete
/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.ucf_cpp
0,0 → 1,22
## $Id: sys_tst_rlink_cuff_ic_n2.ucf_cpp 466 2012-12-30 13:26:55Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2012-12-29 466 1.0 Initial version
##
 
NET "I_CLK50" TNM_NET = "I_CLK50";
TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK50";
OFFSET = OUT 20 ns AFTER "I_CLK50";
 
#include "bplib/nexys2/nexys2_pins.ucf"
##
## Pmod B0 - RS232
##
#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf"
##
## Cypress FX2
##
#include "bplib/nexys2/nexys2_pins_fx2.ucf"
#include "bplib/nexys2/nexys2_time_fx2_ic.ucf"
/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_conf.vhd
0,0 → 1,62
-- $Id: sys_conf.vhd 466 2012-12-30 13:26:55Z mueller $
--
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_cuff_ic_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package sys_conf is
 
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
 
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
 
constant sys_conf_fx2_type : string := "ic2";
 
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
 
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
 
constant sys_conf_fx2_ccwidth : positive := 5;
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
 
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
 
end package sys_conf;
/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.vbom
0,0 → 1,8
# conf
sys_conf = sys_conf.vhd
# libs
# components
# design
../sys_tst_rlink_cuff_n2.vbom
@ucf_cpp: sys_tst_rlink_cuff_ic_n2.ucf
@top: sys_tst_rlink_cuff_n2
/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/Makefile
0,0 → 1,29
# $Id: Makefile 466 2012-12-30 13:26:55Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-12-29 466 1.0 Initial version
#
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
ISE_BOARD = nexys2
ISE_PATH = xc3s1200e-fg320-4
FX2_FILE = nexys2_jtag_2fifo_ic.ihx
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make/generic_ghdl.mk
#
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
#
/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/.cvsignore
0,0 → 1,4
_impactbatch.log
sys_tst_rlink_cuff_ic_n2.ucf
*.dep_ucf_cpp
*.svf
/rtl/sys_gen/tst_rlink_cuff/nexys2/ic
rtl/sys_gen/tst_rlink_cuff/nexys2/ic Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_rlink_cuff_ic_n2.ucf +*.dep_ucf_cpp +*.svf Index: rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vbom =================================================================== --- rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vbom (nonexistent) +++ rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vbom (revision 17) @@ -0,0 +1,30 @@ +# this is the vbom for the 'generic' top level entity +# to be referenced in the vbom's of the specific systems +# ./as/sys_tst_rlink_cuff_as_n2 +# ./ic/sys_tst_rlink_cuff_ic_n2 +# ./ic3/sys_tst_rlink_cuff_ic3_n2 +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../../../vlib/rbus/rblib.vhd +../../../bplib/fx2lib/fx2lib.vhd +../../../bplib/nxcramlib/nxcramlib.vhd +${sys_conf} +# components +[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../bplib/fx2lib/fx2_2fifoctl_as.vbom +../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom +../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom +../tst_rlink_cuff.vbom +../../../bplib/nxcramlib/nx_cram_dummy.vbom +# design +sys_tst_rlink_cuff_n2.vhd +## no @ucf_cpp + Index: rtl/sys_gen/tst_rlink_cuff/nexys2 =================================================================== --- rtl/sys_gen/tst_rlink_cuff/nexys2 (nonexistent) +++ rtl/sys_gen/tst_rlink_cuff/nexys2 (revision 17)
rtl/sys_gen/tst_rlink_cuff/nexys2 Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vhd =================================================================== --- rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vhd (nonexistent) +++ rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vhd (revision 17) @@ -0,0 +1,281 @@ +-- $Id: tst_rlink_cuff.vhd 467 2013-01-02 19:49:05Z mueller $ +-- +-- Copyright 2012-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tst_rlink_cuff - syn +-- Description: tester for rlink over cuff +-- +-- Dependencies: vlib/rlink/rlink_core8 +-- vlib/rlink/rlink_rlbmux +-- vlib/serport/serport_1clock +-- ../tst_rlink/rbd_tst_rlink +-- vlib/rbus/rb_sres_or_2 +-- vlib/genlib/led_pulse_stretch +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.3; ghdl 0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-01-02 467 1.0.1 use 64 usec led pulse width +-- 2012-12-29 466 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.serport.all; +use work.fx2lib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity tst_rlink_cuff is -- tester for rlink over cuff + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CE_USEC : in slbit; -- usec pulse + CE_MSEC : in slbit; -- msec pulse + RB_MREQ_TOP : out rb_mreq_type; -- rbus: request + RB_SRES_TOP : in rb_sres_type; -- rbus: response from top level + SWI : in slv8; -- hio: switches + BTN : in slv4; -- hio: buttons + LED : out slv8; -- hio: leds + DSP_DAT : out slv16; -- hio: display data + DSP_DP : out slv4; -- hio: display decimal points + RXSD : in slbit; -- receive serial data (uart view) + TXSD : out slbit; -- transmit serial data (uart view) + RTS_N : out slbit; -- receive rts (uart view, act.low) + CTS_N : in slbit; -- transmit cts (uart view, act.low) + FX2_RXDATA : in slv8; -- fx2: receiver data out + FX2_RXVAL : in slbit; -- fx2: receiver data valid + FX2_RXHOLD : out slbit; -- fx2: receiver data hold + FX2_TXDATA : out slv8; -- fx2: transmit data in + FX2_TXENA : out slbit; -- fx2: transmit data enable + FX2_TXBUSY : in slbit; -- fx2: transmit busy + FX2_TX2DATA : out slv8; -- fx2: transmit 2 data in + FX2_TX2ENA : out slbit; -- fx2: transmit 2 data enable + FX2_TX2BUSY : in slbit; -- fx2: transmit 2 busy + FX2_MONI : in fx2ctl_moni_type -- fx2: fx2ctl monitor + ); +end tst_rlink_cuff; + +architecture syn of tst_rlink_cuff is + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv3 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + signal STAT : slv8 := (others=>'0'); + + signal RLB_DI : slv8 := (others=>'0'); + signal RLB_ENA : slbit := '0'; + signal RLB_BUSY : slbit := '0'; + signal RLB_DO : slv8 := (others=>'0'); + signal RLB_VAL : slbit := '0'; + signal RLB_HOLD : slbit := '0'; + + signal SER_RXDATA : slv8 := (others=>'0'); + signal SER_RXVAL : slbit := '0'; + signal SER_RXHOLD : slbit := '0'; + signal SER_TXDATA : slv8 := (others=>'0'); + signal SER_TXENA : slbit := '0'; + signal SER_TXBUSY : slbit := '0'; + + signal FX2_TX2ENA_L : slbit := '0'; + signal FX2_TXENA_L : slbit := '0'; + + signal FX2_TX2ENA_LED : slbit := '0'; + signal FX2_TXENA_LED : slbit := '0'; + signal FX2_RXVAL_LED : slbit := '0'; + + signal R_LEDDIV : slv6 := (others=>'0'); -- clock divider for LED pulses + signal R_LEDCE : slbit := '0'; -- ce every 64 usec + +begin + + RLCORE : rlink_core8 + generic map ( + ATOWIDTH => 6, + ITOWIDTH => 6, + CPREF => c_rlink_cpref, + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon) + port map ( + CLK => CLK, + CE_INT => CE_MSEC, + RESET => RESET, + RLB_DI => RLB_DI, + RLB_ENA => RLB_ENA, + RLB_BUSY => RLB_BUSY, + RLB_DO => RLB_DO, + RLB_VAL => RLB_VAL, + RLB_HOLD => RLB_HOLD, + RL_MONI => open, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT + ); + + RLBMUX : rlink_rlbmux + port map ( + SEL => SWI(2), + RLB_DI => RLB_DI, + RLB_ENA => RLB_ENA, + RLB_BUSY => RLB_BUSY, + RLB_DO => RLB_DO, + RLB_VAL => RLB_VAL, + RLB_HOLD => RLB_HOLD, + P0_RXDATA => SER_RXDATA, + P0_RXVAL => SER_RXVAL, + P0_RXHOLD => SER_RXHOLD, + P0_TXDATA => SER_TXDATA, + P0_TXENA => SER_TXENA, + P0_TXBUSY => SER_TXBUSY, + P1_RXDATA => FX2_RXDATA, + P1_RXVAL => FX2_RXVAL, + P1_RXHOLD => FX2_RXHOLD, + P1_TXDATA => FX2_TXDATA, + P1_TXENA => FX2_TXENA_L, + P1_TXBUSY => FX2_TXBUSY + ); + + SERPORT : serport_1clock + generic map ( + CDWIDTH => 15, + CDINIT => sys_conf_ser2rri_cdinit, + RXFAWIDTH => 5, + TXFAWIDTH => 5) + port map ( + CLK => CLK, + CE_MSEC => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ENAESC => SWI(1), + RXDATA => SER_RXDATA, + RXVAL => SER_RXVAL, + RXHOLD => SER_RXHOLD, + TXDATA => SER_TXDATA, + TXENA => SER_TXENA, + TXBUSY => SER_TXBUSY, + MONI => SER_MONI, + RXSD => RXSD, + TXSD => TXSD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N + ); + + RBDTST : entity work.rbd_tst_rlink + port map ( + CLK => CLK, + RESET => RESET, + CE_USEC => CE_USEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TST, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RB_SRES_TOP => RB_SRES, + RXSD => RXSD, + RXACT => SER_MONI.rxact, + STAT => STAT + ); + + RB_SRES_OR1 : rb_sres_or_2 + port map ( + RB_SRES_1 => RB_SRES_TOP, + RB_SRES_2 => RB_SRES_TST, + RB_SRES_OR => RB_SRES + ); + + TX2ENA_PSTR : led_pulse_stretch + port map ( + CLK => CLK, + CE_INT => R_LEDCE, + RESET => '0', + DIN => FX2_TX2ENA_L, + POUT => FX2_TX2ENA_LED + ); + TXENA_PSTR : led_pulse_stretch + port map ( + CLK => CLK, + CE_INT => R_LEDCE, + RESET => '0', + DIN => FX2_TXENA_L, + POUT => FX2_TXENA_LED + ); + RXVAL_PSTR : led_pulse_stretch + port map ( + CLK => CLK, + CE_INT => R_LEDCE, + RESET => '0', + DIN => FX2_RXVAL, + POUT => FX2_RXVAL_LED + ); + + proc_clkdiv: process (CLK) + begin + + if rising_edge(CLK) then + R_LEDCE <= '0'; + if CE_USEC = '1' then + R_LEDDIV <= slv(unsigned(R_LEDDIV) - 1); + if unsigned(R_LEDDIV) = 0 then + R_LEDCE <= '1'; + end if; + end if; + end if; + + end process proc_clkdiv; + + proc_hiomux : process (SWI, SER_MONI, STAT, FX2_TX2BUSY, + FX2_TX2ENA_LED, FX2_TXENA_LED, FX2_RXVAL_LED) + begin + + DSP_DAT <= SER_MONI.abclkdiv; + + LED(7) <= SER_MONI.abact; + LED(6 downto 2) <= (others=>'0'); + LED(1) <= STAT(1); + LED(0) <= STAT(0); + + if SWI(2) = '0' then + DSP_DP(3) <= not SER_MONI.txok; + DSP_DP(2) <= SER_MONI.txact; + DSP_DP(1) <= not SER_MONI.rxok; + DSP_DP(0) <= SER_MONI.rxact; + else + DSP_DP(3) <= FX2_TX2BUSY; + DSP_DP(2) <= FX2_TX2ENA_LED; + DSP_DP(1) <= FX2_TXENA_LED; + DSP_DP(0) <= FX2_RXVAL_LED; + end if; + + end process proc_hiomux; + + RB_MREQ_TOP <= RB_MREQ; + FX2_TX2ENA <= FX2_TX2ENA_L; + FX2_TXENA <= FX2_TXENA_L; + +end syn; Index: rtl/sys_gen/tst_rlink_cuff/Makefile =================================================================== --- rtl/sys_gen/tst_rlink_cuff/Makefile (nonexistent) +++ rtl/sys_gen/tst_rlink_cuff/Makefile (revision 17) @@ -0,0 +1,24 @@ +# $Id: Makefile 466 2012-12-30 13:26:55Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2012-12-29 466 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +ISE_PATH = xc3s1200e-fg320-4 +# +.PHONY : all clean realclean +# +all : $(NGC_all) +# +clean : ise_clean +# +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +include $(VBOM_all:.vbom=.dep_xst) +# Index: rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vbom =================================================================== --- rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vbom (nonexistent) +++ rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vbom (revision 17) @@ -0,0 +1,17 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/genlib/genlib.vhd +../../vlib/rbus/rblib.vhd +../../vlib/rlink/rlinklib.vbom +../../vlib/serport/serport.vhd +../../bplib/fx2lib/fx2lib.vhd +${sys_conf := nexys2/as/sys_conf.vhd} +# components +../../vlib/rlink/rlink_core8.vbom +../../vlib/rlink/rlink_rlbmux.vbom +../../vlib/serport/serport_1clock.vbom +../tst_rlink/rbd_tst_rlink.vbom +../../vlib/rbus/rb_sres_or_2.vbom +../../vlib/genlib/led_pulse_stretch.vbom +# design +tst_rlink_cuff.vhd Index: rtl/sys_gen/tst_rlink_cuff =================================================================== --- rtl/sys_gen/tst_rlink_cuff (nonexistent) +++ rtl/sys_gen/tst_rlink_cuff (revision 17)
rtl/sys_gen/tst_rlink_cuff Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vhd =================================================================== --- rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vhd (revision 16) +++ rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vhd (revision 17) @@ -1,4 +1,4 @@ --- $Id: tb_tst_serloop.vhd 441 2011-12-20 17:01:16Z mueller $ +-- $Id: tb_tst_serloop.vhd 444 2011-12-25 10:04:58Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -15,7 +15,8 @@ -- Module Name: tb_tst_serloop - sim -- Description: Generic test bench for sys_tst_serloop_xx -- --- Dependencies: vlib/serport/serport_uart_rxtx +-- Dependencies: vlib/simlib/simclkcnt +-- vlib/serport/serport_uart_rxtx -- vlib/serport/serport_xontx -- -- To test: sys_tst_serloop_xx @@ -24,6 +25,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-12-23 444 1.1 use new simclkcnt -- 2011-11-13 425 1.0 Initial version -- 2011-11-06 420 0.5 First draft ------------------------------------------------------------------------------ @@ -59,7 +61,7 @@ architecture sim of tb_tst_serloop is signal CLK_STOP_L : slbit := '0'; - signal CLK_CYCLE : slv31 := (others=>'0'); + signal CLK_CYCLE : integer := 0; signal UART_RESET : slbit := '0'; signal UART_RXD : slbit := '1'; @@ -101,12 +103,7 @@ begin - proc_cycle: process (CLKS) - begin - if rising_edge(CLKS) then - CLK_CYCLE <= slv(unsigned(CLK_CYCLE) + 1); - end if; - end process proc_cycle; + CLKCNT : simclkcnt port map (CLK => CLKS, CLK_CYCLE => CLK_CYCLE); UART : serport_uart_rxtx generic map (
/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vbom
3,6 → 3,7
../../../vlib/simlib/simlib.vhd
../../../vlib/serport/serport.vhd
# components
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
../../../vlib/serport/serport_xontx.vbom
# design
/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vhd
1,4 → 1,4
-- $Id: tb_tst_serloop1_n2.vhd 441 2011-12-20 17:01:16Z mueller $
-- $Id: tb_tst_serloop1_n2.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
25,6 → 25,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk; remove clksys output hack
-- 2011-12-16 439 1.0 Initial version
------------------------------------------------------------------------------
 
78,7 → 79,6
OFFSET => clock_offset)
port map (
CLK => CLK50,
CLK_CYCLE => open,
CLK_STOP => CLK_STOP
);
 
85,7 → 85,6
UUT : entity work.sys_tst_serloop1_n2
port map (
I_CLK50 => CLK50,
O_CLKSYS => open,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vhd
1,4 → 1,4
-- $Id: tb_tst_serloop2_n2.vhd 441 2011-12-20 17:01:16Z mueller $
-- $Id: tb_tst_serloop2_n2.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
26,6 → 26,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk; remove clksys output hack
-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-13 424 1.0 Initial version
84,7 → 85,6
OFFSET => clock_offset)
port map (
CLK => CLK50,
CLK_CYCLE => open,
CLK_STOP => CLK_STOP
);
 
113,7 → 113,6
UUT : entity work.sys_tst_serloop2_n2
port map (
I_CLK50 => CLK50,
O_CLKSYS => open,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
/rtl/sys_gen/tst_serloop/nexys2/tb/Makefile
1,11 → 1,15
# $Id: Makefile 441 2011-12-20 17:01:16Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-11-13 424 1.0 Initial version
#
EXE_all = tb_tst_serloop1_n2 tb_tst_serloop2_n2
EXE_all = tb_tst_serloop1_n2
EXE_all += tb_tst_serloop2_n2
#
ISE_BOARD = nexys2
ISE_PATH = xc3s1200e-fg320-4
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vhd
1,4 → 1,4
-- $Id: sys_tst_serloop1_n2.vhd 441 2011-12-20 17:01:16Z mueller $
-- $Id: sys_tst_serloop1_n2.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
34,7 → 34,8
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-16 439 0.5 Initial version
-- 2011-12-23 444 1.1 remove clksys output hack
-- 2011-12-16 439 1.0 Initial version
------------------------------------------------------------------------------
--
 
57,7 → 58,6
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
117,7 → 117,6
begin
 
CLK <= I_CLK50;
O_CLKSYS <= CLK;
 
CLKDIV : clkdivce
generic map (
/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vhd
1,4 → 1,4
-- $Id: sys_tst_serloop2_n2.vhd 441 2011-12-20 17:01:16Z mueller $
-- $Id: sys_tst_serloop2_n2.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
37,6 → 37,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 remove clksys output hack
-- 2011-12-09 437 1.0.4 rename serport stat->moni port
-- 2011-11-26 433 1.0.3 use nx_cram_dummy now
-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage
65,7 → 66,6
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
138,8 → 138,6
LOCKED => open
);
 
O_CLKSYS <= '0';
 
CLKDIV_U : clkdivce
generic map (
CDUWIDTH => 7,
/rtl/sys_gen/tst_serloop/nexys2/Makefile
1,4 → 1,4
# $Id: Makefile 441 2011-12-20 17:01:16Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
15,8 → 15,7
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_serloop1_n2.ucf
rm -f sys_tst_serloop2_n2.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vbom
5,7 → 5,7
../tst_serlooplib.vbom
../../../vlib/serport/serport.vhd
../../../bplib/nxcramlib/nxcramlib.vhd
sys_conf : sys_conf1.vhd
${sys_conf := sys_conf1.vhd}
# components
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
/rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vbom
6,7 → 6,7
../tst_serlooplib.vbom
../../../vlib/serport/serport.vhd
../../../bplib/nxcramlib/nxcramlib.vhd
sys_conf : sys_conf2.vhd
${sys_conf := sys_conf2.vhd}
# components
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
/rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vhd
1,4 → 1,4
-- $Id: tb_tst_serloop1_n3.vhd 441 2011-12-20 17:01:16Z mueller $
-- $Id: tb_tst_serloop1_n3.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
25,6 → 25,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk
-- 2011-12-11 438 1.0 Initial version
------------------------------------------------------------------------------
 
77,7 → 78,6
OFFSET => clock_offset)
port map (
CLK => CLK100,
CLK_CYCLE => open,
CLK_STOP => CLK_STOP
);
 
/rtl/sys_gen/tst_serloop/nexys3/tb/Makefile
1,4 → 1,4
# $Id: Makefile 442 2011-12-23 10:03:28Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
7,6 → 7,12
#
EXE_all = tb_tst_serloop1_n3
#
ISE_BOARD = nexys3
ISE_PATH = xc6slx16-csg324-2
#
XFLOWOPT_SYN = syn_s6_speed.opt
XFLOWOPT_IMP = imp_s6_speed.opt
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
/rtl/sys_gen/tst_serloop/nexys3/Makefile
1,4 → 1,4
# $Id: Makefile 441 2011-12-20 17:01:16Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
18,8 → 18,7
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_serloop1_n3.ucf
rm -f sys_tst_serloop2_n3.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
/rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vbom
6,7 → 6,7
../tst_serlooplib.vbom
../../../vlib/serport/serport.vhd
../../../bplib/nxcramlib/nxcramlib.vhd
sys_conf : sys_conf1.vhd
${sys_conf := sys_conf1.vhd}
# components
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vbom
6,7 → 6,7
../tst_serlooplib.vbom
../../../vlib/serport/serport.vhd
../../../bplib/s3board/s3boardlib.vbom
sys_conf : sys_conf.vhd
${sys_conf := sys_conf.vhd}
# components
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
/rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vhd
1,4 → 1,4
-- $Id: tb_tst_serloop_s3.vhd 441 2011-12-20 17:01:16Z mueller $
-- $Id: tb_tst_serloop_s3.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
26,6 → 26,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-06 420 1.0 Initial version
------------------------------------------------------------------------------
82,7 → 83,6
OFFSET => clock_offset)
port map (
CLK => CLK50,
CLK_CYCLE => open,
CLK_STOP => CLK_STOP
);
 
/rtl/sys_gen/tst_serloop/s3board/Makefile
1,4 → 1,4
# $Id: Makefile 441 2011-12-20 17:01:16Z mueller $
# $Id: Makefile 448 2012-01-02 21:55:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
15,7 → 15,7
all : $(BIT_all)
#
clean : ise_clean
rm -f sys_tst_serloop_s3.ucf
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
/rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vbom
7,8 → 7,9
../../../vlib/simlib/simlib.vhd
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../micron/mt45w8mw16b.vbom
uut : tbd_nx_cram_memctl_as.vbom
${uut := tbd_nx_cram_memctl_as.vbom}
# design
tb_nx_cram_memctl.vhd
@top:tb_nx_cram_memctl
/rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vhd
1,4 → 1,4
-- $Id: tb_nx_cram_memctl.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: tb_nx_cram_memctl.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
16,6 → 16,7
-- Description: Test bench for nx_cram_memctl
--
-- Dependencies: vlib/simlib/simclk
-- vlib/simlib/simclkcnt
-- bplib/micron/mt45w8mw16b
-- tbd_nx_cram_memctl [UUT, abstact]
--
25,6 → 26,7
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.4 use new simclk/simclkcnt
-- 2011-11-26 433 1.3 renamed from tb_n2_cram_memctl
-- 2011-11-21 432 1.2 now numeric_std clean; update O_FLA_CE_N usage
-- 2010-05-30 297 1.1 use abstact uut tbd_nx_cram_memctl
109,7 → 111,7
signal R_REF_ADDR_DL : slv22 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : slv31 := (others=>'0');
signal CLK_CYCLE : integer := 0;
 
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
118,16 → 120,17
 
begin
 
SYSCLK : simclk
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
CLK_STOP => CLK_STOP
);
 
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
 
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
/rtl/bplib/fx2lib/fx2_2fifoctl_ic.vhd
0,0 → 1,561
-- $Id: fx2_2fifoctl_ic.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fx2_2fifoctl_ic - syn
-- Description: Cypress EZ-USB FX2 driver (2 fifo; int clk)
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_i_gen
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
-- memlib/fifo_2c_dram
--
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2012-01-14 453 13.3 O76x xc3s1200e-4 101 173 64 159 s 8.3/7.4
-- 2012-01-08 451 13.3 O76x xc3s1200e-4 110 166 64 163 s 7.5
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.1 use aempty/afull logic; collapse tx and pe flows
-- 2012-01-09 451 1.0 Initial version
-- 2012-01-01 448 0.5 First draft
--
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.xlib.all;
use work.memlib.all;
use work.fx2lib.all;
 
entity fx2_2fifoctl_ic is -- EZ-USB FX2 driver (2 fifo; int clk)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1); -- threshold for tx afull flag
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit data busy
TXAFULL : out slbit; -- transmit almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end fx2_2fifoctl_ic;
 
 
architecture syn of fx2_2fifoctl_ic is
 
constant c_rxfifo : slv2 := c_fifo_ep4;
constant c_txfifo : slv2 := c_fifo_ep6;
 
constant c_flag_prog : integer := 0;
constant c_flag_tx_ff : integer := 1;
constant c_flag_rx_ef : integer := 2;
constant c_flag_tx2_ff : integer := 3;
type state_type is (
s_idle, -- s_idle: idle state
s_rxprep0, -- s_rxprep0: switch to rx-fifo
s_rxprep1, -- s_rxprep1: fifo addr setup
s_rxprep2, -- s_rxprep2: wait for flags
s_rxdisp, -- s_rxdisp: read, dispatch
s_rxpipe, -- s_rxpipe: read, pipe drain
s_txprep0, -- s_txprep0: switch to tx-fifo
s_txprep1, -- s_txprep1: fifo addr setup
s_txprep2, -- s_txprep2: wait for flags
s_txdisp -- s_txdisp: write, dispatch
);
type regs_type is record
state : state_type; -- state
petocnt : slv(PETOWIDTH-1 downto 0); -- pktend time out counter
pepend : slbit; -- pktend pending
rxpipe : slbit; -- read transaction in flight
ccnt : slv(CCWIDTH-1 downto 0); -- chunk counter
moni_ep4_sel : slbit; -- ep4 (rx) select
moni_ep6_sel : slbit; -- ep6 (tx) select
moni_ep4_pf : slbit; -- ep4 (rx) prog flag
moni_ep6_pf : slbit; -- ep6 (tx) prog flag
end record regs_type;
 
constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0');
constant ccnt_init : slv(CCWIDTH-1 downto 0) := (others=>'0');
 
constant regs_init : regs_type := (
s_idle, -- state
petocnt_init, -- petocnt
'0','0', -- pepend,rxpipe
ccnt_init, -- ccnt
'0','0', -- moni_ep(4|6)_sel
'0','0' -- moni_ep(4|6)_pf
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
 
signal FX2_FIFO : slv2 := (others=>'0');
signal FX2_FIFO_CE : slbit := '0';
signal FX2_FLAG_N : slv4 := (others=>'0');
signal FX2_SLRD_N : slbit := '1';
signal FX2_SLWR_N : slbit := '1';
signal FX2_SLOE_N : slbit := '1';
signal FX2_PKTEND_N : slbit := '1';
signal FX2_DATA_CEI : slbit := '0';
signal FX2_DATA_CEO : slbit := '0';
signal FX2_DATA_OE : slbit := '0';
 
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXSIZE_FX2 : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal RXSIZE_USR : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal TXSIZE_FX2 : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TXSIZE_USR : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
 
signal TXBUSY_L : slbit := '0';
 
signal R_MONI_C : fx2ctl_moni_type := fx2ctl_moni_init;
signal R_MONI_S : fx2ctl_moni_type := fx2ctl_moni_init;
 
begin
 
assert RXAEMPTY_THRES<=2**RXFAWIDTH-1 and
TXAFULL_THRES<=2**TXFAWIDTH-1
report "assert((RXAEMPTY|TXAFULL)_THRES <= 2**(RX|TX)FAWIDTH)-1"
severity failure;
 
 
IOB_FX2_FIFO : iob_reg_o_gen
generic map (
DWIDTH => 2,
INIT => '0')
port map (
CLK => I_FX2_IFCLK,
CE => FX2_FIFO_CE,
DO => FX2_FIFO,
PAD => O_FX2_FIFO
);
IOB_FX2_FLAG : iob_reg_i_gen
generic map (
DWIDTH => 4,
INIT => '0')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DI => FX2_FLAG_N,
PAD => I_FX2_FLAG
);
IOB_FX2_SLRD : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLRD_N,
PAD => O_FX2_SLRD_N
);
IOB_FX2_SLWR : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLWR_N,
PAD => O_FX2_SLWR_N
);
IOB_FX2_SLOE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLOE_N,
PAD => O_FX2_SLOE_N
);
IOB_FX2_PKTEND : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_PKTEND_N,
PAD => O_FX2_PKTEND_N
);
 
IOB_FX2_DATA : iob_reg_io_gen
generic map (
DWIDTH => 8,
PULL => "KEEP")
port map (
CLK => I_FX2_IFCLK,
CEI => FX2_DATA_CEI,
CEO => FX2_DATA_CEO,
OE => FX2_DATA_OE,
DI => RXFIFO_DI, -- input data (read from pad)
DO => TXFIFO_DO, -- output data (write to pad)
PAD => IO_FX2_DATA
);
 
RXFIFO : fifo_2c_dram -- input fifo, 2 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => I_FX2_IFCLK,
CLKR => CLK,
RESETW => '0',
RESETR => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZEW => RXSIZE_FX2,
SIZER => RXSIZE_USR
);
 
TXFIFO : fifo_2c_dram -- output fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLK,
CLKR => I_FX2_IFCLK,
RESETW => RESET,
RESETR => '0',
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY_L,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZEW => TXSIZE_USR,
SIZER => TXSIZE_FX2
);
proc_regs: process (I_FX2_IFCLK)
begin
 
if rising_edge(I_FX2_IFCLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
 
end process proc_regs;
 
proc_next: process (R_REGS,
FX2_FLAG_N, TXFIFO_VAL, RXSIZE_FX2,
RXFIFO_BUSY, TXBUSY_L)
 
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
 
variable ififo_ce : slbit := '0';
variable ififo : slv2 := "00";
 
variable irxfifo_ena : slbit := '0';
variable itxfifo_hold : slbit := '0';
 
variable islrd : slbit := '0';
variable islwr : slbit := '0';
variable isloe : slbit := '0';
variable ipktend : slbit := '0';
 
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
variable idata_oe : slbit := '0';
 
variable imoni : fx2ctl_moni_type := fx2ctl_moni_init;
 
variable slrxok : slbit := '0';
variable sltxok : slbit := '0';
variable pipeok : slbit := '0';
 
variable cc_clr : slbit := '0';
variable cc_cnt : slbit := '0';
variable cc_done : slbit := '0';
begin
 
r := R_REGS;
n := R_REGS;
 
ififo_ce := '0';
ififo := "00";
 
irxfifo_ena := '0';
itxfifo_hold := '1';
islrd := '0';
islwr := '0';
isloe := '0';
ipktend := '0';
 
idata_cei := '0';
idata_ceo := '0';
idata_oe := '0';
 
imoni := fx2ctl_moni_init;
slrxok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low!
sltxok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low!
pipeok := FX2_FLAG_N(c_flag_prog); -- almost flag is act.low!
 
cc_clr := '0';
cc_cnt := '0';
if unsigned(r.ccnt) = 0 then
cc_done := '1';
else
cc_done := '0';
end if;
 
case r.state is
when s_idle => -- s_idle:
if slrxok='1' and RXFIFO_BUSY='0' then
ififo_ce := '1';
ififo := c_rxfifo;
n.state := s_rxprep1;
elsif sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1')then
ififo_ce := '1';
ififo := c_txfifo;
n.state := s_txprep1;
end if;
 
when s_rxprep0 => -- s_rxprep0: switch to rx-fifo
ififo_ce := '1';
ififo := c_rxfifo;
n.state := s_rxprep1;
 
when s_rxprep1 => -- s_rxprep1: fifo addr setup
cc_clr := '1';
n.state := s_rxprep2;
 
when s_rxprep2 => -- s_rxprep2: wait for flags
isloe := '1';
n.state := s_rxdisp;
 
when s_rxdisp => -- s_rxdisp: read, dispatch
isloe := '1';
if r.rxpipe = '1' then -- read in flight ?
irxfifo_ena := '1'; -- capture rxdata
n.rxpipe := '0';
end if;
 
-- if chunk done and tx or pe pending and possible
if cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1') then
n.state := s_txprep0;
-- if more rx to do and possible
elsif slrxok='1' and RXFIFO_BUSY='0' then
cc_cnt := '1';
idata_cei := '1';
islrd := '1';
if false and pipeok='1' and unsigned(RXSIZE_FX2)>2 then
n.rxpipe := '1';
n.state := s_rxdisp;
else
n.state := s_rxpipe;
end if;
-- otherwise back to idle
else
n.state := s_idle;
end if;
 
when s_rxpipe => -- s_rxpipe: read, pipe drain
isloe := '1';
irxfifo_ena := '1'; -- capture rxdata
if pipeok='1' and unsigned(RXSIZE_FX2)>1 then
n.state := s_rxdisp;
else
n.state := s_rxprep2;
end if;
 
when s_txprep0 => -- s_txprep0: switch to tx-fifo
ififo_ce := '1';
ififo := c_txfifo;
n.state := s_txprep1;
 
when s_txprep1 => -- s_txprep1: fifo addr setup
cc_clr := '1';
n.state := s_txprep2;
 
when s_txprep2 => -- s_txprep2: wait for flags
n.state := s_txdisp;
 
when s_txdisp => -- s_txdisp: write, dispatch
-- if chunk done and rx pending and possible
if cc_done='1' and slrxok='1' and RXFIFO_BUSY='0' then
n.state := s_rxprep0;
-- if pktend to do and possible
elsif sltxok = '1' and r.pepend = '1' then
ipktend := '1';
n.pepend := '0';
n.state := s_idle;
-- if more tx to do and possible
elsif sltxok = '1' and TXFIFO_VAL = '1' then
cc_cnt := '1'; -- inc chunk count
n.pepend := '0'; -- cancel pe (avoid back-2-back tx+pe)
itxfifo_hold := '0';
idata_ceo := '1';
idata_oe := '1';
islwr := '1';
if pipeok = '1' then -- if not almost full
n.state := s_txdisp; -- stream
else
n.state := s_txprep1; -- wait for full flag
end if;
-- otherwise back to idle
else
n.state := s_idle;
end if;
when others => null;
end case;
 
-- chunk counter handling
if cc_clr = '1' then
n.ccnt := (others=>'1');
elsif cc_cnt='1' and unsigned(r.ccnt) > 0 then
n.ccnt := slv(unsigned(r.ccnt) - 1);
end if;
-- pktend time-out handling:
-- if tx fifo is non-empty, set counter to max
-- if tx fifo is empty, count down every usec
-- on 1->0 transition queue pktend request
if TXFIFO_VAL = '1' then
n.petocnt := (others=>'1');
else
if unsigned(r.petocnt) /= 0 then
n.petocnt := slv(unsigned(r.petocnt) - 1);
if unsigned(r.petocnt) = 1 then
n.pepend := '1';
end if;
end if;
end if;
 
n.moni_ep4_sel := '0';
n.moni_ep6_sel := '0';
if r.state = s_rxdisp or r.state = s_rxpipe then
n.moni_ep4_sel := '1';
n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog);
elsif r.state = s_txdisp then
n.moni_ep6_sel := '1';
n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog);
end if;
 
N_REGS <= n;
 
FX2_FIFO_CE <= ififo_ce;
FX2_FIFO <= ififo;
 
FX2_SLRD_N <= not islrd;
FX2_SLWR_N <= not islwr;
FX2_SLOE_N <= not isloe;
FX2_PKTEND_N <= not ipktend;
 
FX2_DATA_CEI <= idata_cei;
FX2_DATA_CEO <= idata_ceo;
FX2_DATA_OE <= idata_oe;
 
RXFIFO_ENA <= irxfifo_ena;
TXFIFO_HOLD <= itxfifo_hold;
end process proc_next;
 
proc_moni: process (CLK)
begin
 
if rising_edge(CLK) then
if RESET = '1' then
R_MONI_C <= fx2ctl_moni_init;
R_MONI_S <= fx2ctl_moni_init;
else
R_MONI_C <= fx2ctl_moni_init;
R_MONI_C.fifo_ep4 <= R_REGS.moni_ep4_sel;
R_MONI_C.fifo_ep6 <= R_REGS.moni_ep6_sel;
R_MONI_C.flag_ep4_empty <= not FX2_FLAG_N(c_flag_rx_ef);
R_MONI_C.flag_ep4_almost <= R_REGS.moni_ep4_pf;
R_MONI_C.flag_ep6_full <= not FX2_FLAG_N(c_flag_tx_ff);
R_MONI_C.flag_ep6_almost <= R_REGS.moni_ep6_pf;
R_MONI_C.slrd <= not FX2_SLRD_N;
R_MONI_C.slwr <= not FX2_SLWR_N;
R_MONI_C.pktend <= not FX2_PKTEND_N;
R_MONI_S <= R_MONI_C;
end if;
end if;
 
end process proc_moni;
 
proc_almost: process (RXSIZE_USR, TXSIZE_USR)
begin
 
-- rxsize_usr is the number of bytes to read
-- txsize_usr is the number of bytes to write
if unsigned(RXSIZE_USR) <= RXAEMPTY_THRES then
RXAEMPTY <= '1';
else
RXAEMPTY <= '0';
end if;
 
if unsigned(TXSIZE_USR) <= TXAFULL_THRES then
TXAFULL <= '1';
else
TXAFULL <= '0';
end if;
 
end process proc_almost;
 
TXBUSY <= TXBUSY_L;
 
MONI <= R_MONI_S;
end syn;
/rtl/bplib/fx2lib/fx2_3fifoctl_ic.vhd
0,0 → 1,690
-- $Id: fx2_3fifoctl_ic.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fx2_3fifoctl_ic - syn
-- Description: Cypress EZ-USB FX2 driver (3 fifo; int clk)
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_i_gen
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
-- memlib/fifo_2c_dram
--
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2012-01-15 453 13.3 O76x xc3s1200e-4 156 259 96 238 s 7.9/7.5
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-09 453 1.0 Initial version (derived from 2fifo_ic)
--
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.xlib.all;
use work.memlib.all;
use work.fx2lib.all;
 
entity fx2_3fifoctl_ic is -- EZ-USB FX2 driver (3 fifo; int clk)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
TX2AFULL_THRES : natural := 1); -- threshold for tx2 afull flag
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit 1 data in
TXENA : in slbit; -- transmit 1 data enable
TXBUSY : out slbit; -- transmit 1 data busy
TXAFULL : out slbit; -- transmit 1 almost full flag
TX2DATA : in slv8; -- transmit 2 data in
TX2ENA : in slbit; -- transmit 2 data enable
TX2BUSY : out slbit; -- transmit 2 data busy
TX2AFULL : out slbit; -- transmit 2 almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end fx2_3fifoctl_ic;
 
 
architecture syn of fx2_3fifoctl_ic is
 
constant c_rxfifo : slv2 := c_fifo_ep4;
constant c_txfifo : slv2 := c_fifo_ep6;
constant c_tx2fifo: slv2 := c_fifo_ep8;
 
constant c_flag_prog : integer := 0;
constant c_flag_tx_ff : integer := 1;
constant c_flag_rx_ef : integer := 2;
constant c_flag_tx2_ff : integer := 3;
type state_type is (
s_idle, -- s_idle: idle state
s_rxprep0, -- s_rxprep0: switch to rx-fifo
s_rxprep1, -- s_rxprep1: fifo addr setup
s_rxprep2, -- s_rxprep2: wait for flags
s_rxdisp, -- s_rxdisp: read, dispatch
s_rxpipe, -- s_rxpipe: read, pipe drain
s_txprep0, -- s_txprep0: switch to tx-fifo
s_txprep1, -- s_txprep1: fifo addr setup
s_txprep2, -- s_txprep2: wait for flags
s_txdisp, -- s_txdisp: write, dispatch
s_tx2prep0, -- s_tx2prep0: switch to tx2-fifo
s_tx2prep1, -- s_tx2prep1: fifo addr setup
s_tx2prep2, -- s_tx2prep2: wait for flags
s_tx2disp -- s_tx2disp: write, dispatch
);
type regs_type is record
state : state_type; -- state
petocnt : slv(PETOWIDTH-1 downto 0); -- pktend 1 time out counter
pe2tocnt : slv(PETOWIDTH-1 downto 0); -- pktend 2 time out counter
pepend : slbit; -- pktend 1 pending
pe2pend : slbit; -- pktend 2 pending
rxpipe : slbit; -- read transaction in flight
ccnt : slv(CCWIDTH-1 downto 0); -- chunk counter
moni_ep4_sel : slbit; -- ep4 (rx) select
moni_ep6_sel : slbit; -- ep6 (tx) select
moni_ep8_sel : slbit; -- ep8 (tx2) select
moni_ep4_pf : slbit; -- ep4 (rx) prog flag
moni_ep6_pf : slbit; -- ep6 (tx) prog flag
moni_ep8_pf : slbit; -- ep8 (tx2) prog flag
end record regs_type;
 
constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0');
constant ccnt_init : slv(CCWIDTH-1 downto 0) := (others=>'0');
 
constant regs_init : regs_type := (
s_idle, -- state
petocnt_init, -- petocnt
petocnt_init, -- pe2tocnt
'0','0','0', -- pepend,pe2pend,rxpipe
ccnt_init, -- ccnt
'0','0','0', -- moni_ep(4|6|8)_sel
'0','0','0' -- moni_ep(4|6|8)_pf
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
 
signal FX2_FIFO : slv2 := (others=>'0');
signal FX2_FIFO_CE : slbit := '0';
signal FX2_FLAG_N : slv4 := (others=>'0');
signal FX2_SLRD_N : slbit := '1';
signal FX2_SLWR_N : slbit := '1';
signal FX2_SLOE_N : slbit := '1';
signal FX2_PKTEND_N : slbit := '1';
signal FX2_DATA_CEI : slbit := '0';
signal FX2_DATA_CEO : slbit := '0';
signal FX2_DATA_OE : slbit := '0';
signal FX2_DATA_DO : slv8 := (others=>'0');
 
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXSIZE_FX2 : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal RXSIZE_USR : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal TXSIZE_FX2 : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TXSIZE_USR : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TX2FIFO_DO : slv8 := (others=>'0');
signal TX2FIFO_VAL : slbit := '0';
signal TX2FIFO_HOLD : slbit := '0';
signal TX2SIZE_FX2 : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TX2SIZE_USR : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
 
signal TXBUSY_L : slbit := '0';
signal TX2BUSY_L : slbit := '0';
 
signal R_MONI_C : fx2ctl_moni_type := fx2ctl_moni_init;
signal R_MONI_S : fx2ctl_moni_type := fx2ctl_moni_init;
 
begin
 
assert RXAEMPTY_THRES<=2**RXFAWIDTH-1 and
TXAFULL_THRES<=2**TXFAWIDTH-1 and
TX2AFULL_THRES<=2**TXFAWIDTH-1
report "assert((RXAEMPTY|TXAFULL|TX2AFULL)_THRES <= 2**(RX|TX)FAWIDTH)-1"
severity failure;
 
 
IOB_FX2_FIFO : iob_reg_o_gen
generic map (
DWIDTH => 2,
INIT => '0')
port map (
CLK => I_FX2_IFCLK,
CE => FX2_FIFO_CE,
DO => FX2_FIFO,
PAD => O_FX2_FIFO
);
IOB_FX2_FLAG : iob_reg_i_gen
generic map (
DWIDTH => 4,
INIT => '0')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DI => FX2_FLAG_N,
PAD => I_FX2_FLAG
);
IOB_FX2_SLRD : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLRD_N,
PAD => O_FX2_SLRD_N
);
IOB_FX2_SLWR : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLWR_N,
PAD => O_FX2_SLWR_N
);
IOB_FX2_SLOE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLOE_N,
PAD => O_FX2_SLOE_N
);
IOB_FX2_PKTEND : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_PKTEND_N,
PAD => O_FX2_PKTEND_N
);
 
IOB_FX2_DATA : iob_reg_io_gen
generic map (
DWIDTH => 8,
PULL => "KEEP")
port map (
CLK => I_FX2_IFCLK,
CEI => FX2_DATA_CEI,
CEO => FX2_DATA_CEO,
OE => FX2_DATA_OE,
DI => RXFIFO_DI, -- input data (read from pad)
DO => FX2_DATA_DO, -- output data (write to pad)
PAD => IO_FX2_DATA
);
 
RXFIFO : fifo_2c_dram -- input fifo, 2 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => I_FX2_IFCLK,
CLKR => CLK,
RESETW => '0',
RESETR => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZEW => RXSIZE_FX2,
SIZER => RXSIZE_USR
);
 
TXFIFO : fifo_2c_dram -- output fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLK,
CLKR => I_FX2_IFCLK,
RESETW => RESET,
RESETR => '0',
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY_L,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZEW => TXSIZE_USR,
SIZER => TXSIZE_FX2
);
TX2FIFO : fifo_2c_dram -- output 2 fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLK,
CLKR => I_FX2_IFCLK,
RESETW => RESET,
RESETR => '0',
DI => TX2DATA,
ENA => TX2ENA,
BUSY => TX2BUSY_L,
DO => TX2FIFO_DO,
VAL => TX2FIFO_VAL,
HOLD => TX2FIFO_HOLD,
SIZEW => TX2SIZE_USR,
SIZER => TX2SIZE_FX2
);
proc_regs: process (I_FX2_IFCLK)
begin
 
if rising_edge(I_FX2_IFCLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
 
end process proc_regs;
 
proc_next: process (R_REGS,
FX2_FLAG_N, TXFIFO_VAL, TX2FIFO_VAL,
TXFIFO_DO, TX2FIFO_DO,
RXSIZE_FX2, RXFIFO_BUSY, TXBUSY_L, TX2BUSY_L)
 
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
 
variable ififo_ce : slbit := '0';
variable ififo : slv2 := "00";
 
variable irxfifo_ena : slbit := '0';
variable itxfifo_hold : slbit := '0';
variable itx2fifo_hold : slbit := '0';
 
variable islrd : slbit := '0';
variable islwr : slbit := '0';
variable isloe : slbit := '0';
variable ipktend : slbit := '0';
 
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
variable idata_oe : slbit := '0';
variable idata_do : slv8 := (others=>'0');
 
variable imoni : fx2ctl_moni_type := fx2ctl_moni_init;
 
variable slrxok : slbit := '0';
variable sltxok : slbit := '0';
variable sltx2ok : slbit := '0';
variable pipeok : slbit := '0';
 
variable cc_clr : slbit := '0';
variable cc_cnt : slbit := '0';
variable cc_done : slbit := '0';
begin
 
r := R_REGS;
n := R_REGS;
 
ififo_ce := '0';
ififo := "00";
 
irxfifo_ena := '0';
itxfifo_hold := '1';
itx2fifo_hold := '1';
islrd := '0';
islwr := '0';
isloe := '0';
ipktend := '0';
 
idata_cei := '0';
idata_ceo := '0';
idata_oe := '0';
idata_do := TXFIFO_DO;
 
imoni := fx2ctl_moni_init;
slrxok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low!
sltxok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low!
sltx2ok := FX2_FLAG_N(c_flag_tx2_ff); -- full flag is act.low!
pipeok := FX2_FLAG_N(c_flag_prog); -- almost flag is act.low!
 
cc_clr := '0';
cc_cnt := '0';
if unsigned(r.ccnt) = 0 then
cc_done := '1';
else
cc_done := '0';
end if;
 
case r.state is
when s_idle => -- s_idle:
if slrxok='1' and RXFIFO_BUSY='0' then
ififo_ce := '1';
ififo := c_rxfifo;
n.state := s_rxprep1;
elsif sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1')then
ififo_ce := '1';
ififo := c_txfifo;
n.state := s_txprep1;
elsif sltx2ok='1' and (TX2FIFO_VAL='1' or r.pe2pend='1')then
ififo_ce := '1';
ififo := c_tx2fifo;
n.state := s_tx2prep1;
end if;
 
when s_rxprep0 => -- s_rxprep0: switch to rx-fifo
ififo_ce := '1';
ififo := c_rxfifo;
n.state := s_rxprep1;
 
when s_rxprep1 => -- s_rxprep1: fifo addr setup
cc_clr := '1';
n.state := s_rxprep2;
 
when s_rxprep2 => -- s_rxprep2: wait for flags
isloe := '1';
n.state := s_rxdisp;
 
when s_rxdisp => -- s_rxdisp: read, dispatch
isloe := '1';
if r.rxpipe = '1' then -- read in flight ?
irxfifo_ena := '1'; -- capture rxdata
n.rxpipe := '0';
end if;
 
-- if chunk done and tx or pe pending and possible
if cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1') then
n.state := s_txprep0;
-- if chunk done and tx2 or pe2 pending and possible
elsif cc_done='1' and sltx2ok='1' and (TX2FIFO_VAL='1' or r.pe2pend='1')
then
n.state := s_tx2prep0;
-- if more rx to do and possible
elsif slrxok='1' and RXFIFO_BUSY='0' then
cc_cnt := '1';
idata_cei := '1';
islrd := '1';
if false and pipeok='1' and unsigned(RXSIZE_FX2)>2 then
n.rxpipe := '1';
n.state := s_rxdisp;
else
n.state := s_rxpipe;
end if;
-- otherwise back to idle
else
n.state := s_idle;
end if;
 
when s_rxpipe => -- s_rxpipe: read, pipe drain
isloe := '1';
irxfifo_ena := '1'; -- capture rxdata
if pipeok='1' and unsigned(RXSIZE_FX2)>1 then
n.state := s_rxdisp;
else
n.state := s_rxprep2;
end if;
 
when s_txprep0 => -- s_txprep0: switch to tx-fifo
ififo_ce := '1';
ififo := c_txfifo;
n.state := s_txprep1;
 
when s_txprep1 => -- s_txprep1: fifo addr setup
cc_clr := '1';
n.state := s_txprep2;
 
when s_txprep2 => -- s_txprep2: wait for flags
n.state := s_txdisp;
 
when s_txdisp => -- s_txdisp: write, dispatch
-- if chunk done and tx2 or pe2 pending and possible
if cc_done='1' and sltx2ok='1' and (TX2FIFO_VAL='1' or r.pe2pend='1')
then
n.state := s_tx2prep0;
-- if chunk done and rx pending and possible
elsif cc_done='1' and slrxok='1' and RXFIFO_BUSY='0' then
n.state := s_rxprep0;
-- if pktend to do and possible
elsif sltxok = '1' and r.pepend = '1' then
ipktend := '1';
n.pepend := '0';
n.state := s_idle;
-- if more tx to do and possible
elsif sltxok = '1' and TXFIFO_VAL = '1' then
cc_cnt := '1'; -- inc chunk count
n.pepend := '0'; -- cancel pe (avoid back-2-back tx+pe)
itxfifo_hold := '0';
idata_do := TXFIFO_DO;
idata_ceo := '1';
idata_oe := '1';
islwr := '1';
if pipeok = '1' then -- if not almost full
n.state := s_txdisp; -- stream
else
n.state := s_txprep1; -- wait for full flag
end if;
-- otherwise back to idle
else
n.state := s_idle;
end if;
when s_tx2prep0 => -- s_tx2prep0: switch to tx2-fifo
ififo_ce := '1';
ififo := c_tx2fifo;
n.state := s_tx2prep1;
 
when s_tx2prep1 => -- s_tx2prep1: fifo addr setup
cc_clr := '1';
n.state := s_tx2prep2;
 
when s_tx2prep2 => -- s_tx2prep2: wait for flags
n.state := s_tx2disp;
 
when s_tx2disp => -- s_tx2disp: write, dispatch
-- if chunk done and rx pending and possible
if cc_done='1' and slrxok='1' and RXFIFO_BUSY='0' then
n.state := s_rxprep0;
-- if chunk done and tx or pe pending and possible
elsif cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1')
then
n.state := s_txprep0;
-- if pktend 2 to do and possible
elsif sltx2ok = '1' and r.pe2pend = '1' then
ipktend := '1';
n.pe2pend := '0';
n.state := s_idle;
-- if more tx2 to do and possible
elsif sltx2ok = '1' and TX2FIFO_VAL = '1' then
cc_cnt := '1'; -- inc chunk count
n.pe2pend := '0'; -- cancel pe (avoid back-2-back tx+pe)
itx2fifo_hold := '0';
idata_do := TX2FIFO_DO;
idata_ceo := '1';
idata_oe := '1';
islwr := '1';
if pipeok = '1' then -- if not almost full
n.state := s_tx2disp; -- stream
else
n.state := s_tx2prep1; -- wait for full flag
end if;
-- otherwise back to idle
else
n.state := s_idle;
end if;
when others => null;
end case;
 
-- chunk counter handling
if cc_clr = '1' then
n.ccnt := (others=>'1');
elsif cc_cnt='1' and unsigned(r.ccnt) > 0 then
n.ccnt := slv(unsigned(r.ccnt) - 1);
end if;
-- pktend time-out handling:
-- if tx fifo is non-empty, set counter to max
-- if tx fifo is empty, count down every usec
-- on 1->0 transition queue pktend request
if TXFIFO_VAL = '1' then
n.petocnt := (others=>'1');
else
if unsigned(r.petocnt) /= 0 then
n.petocnt := slv(unsigned(r.petocnt) - 1);
if unsigned(r.petocnt) = 1 then
n.pepend := '1';
end if;
end if;
end if;
if TX2FIFO_VAL = '1' then
n.pe2tocnt := (others=>'1');
else
if unsigned(r.pe2tocnt) /= 0 then
n.pe2tocnt := slv(unsigned(r.pe2tocnt) - 1);
if unsigned(r.pe2tocnt) = 1 then
n.pe2pend := '1';
end if;
end if;
end if;
 
n.moni_ep4_sel := '0';
n.moni_ep6_sel := '0';
n.moni_ep8_sel := '0';
if r.state = s_rxdisp or r.state = s_rxpipe then
n.moni_ep4_sel := '1';
n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog);
elsif r.state = s_txdisp then
n.moni_ep6_sel := '1';
n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog);
elsif r.state = s_tx2disp then
n.moni_ep8_sel := '1';
n.moni_ep8_pf := not FX2_FLAG_N(c_flag_prog);
end if;
 
N_REGS <= n;
 
FX2_FIFO_CE <= ififo_ce;
FX2_FIFO <= ififo;
 
FX2_SLRD_N <= not islrd;
FX2_SLWR_N <= not islwr;
FX2_SLOE_N <= not isloe;
FX2_PKTEND_N <= not ipktend;
 
FX2_DATA_CEI <= idata_cei;
FX2_DATA_CEO <= idata_ceo;
FX2_DATA_OE <= idata_oe;
FX2_DATA_DO <= idata_do;
 
RXFIFO_ENA <= irxfifo_ena;
TXFIFO_HOLD <= itxfifo_hold;
TX2FIFO_HOLD <= itx2fifo_hold;
end process proc_next;
 
proc_moni: process (CLK)
begin
 
if rising_edge(CLK) then
if RESET = '1' then
R_MONI_C <= fx2ctl_moni_init;
R_MONI_S <= fx2ctl_moni_init;
else
R_MONI_C <= fx2ctl_moni_init;
R_MONI_C.fifo_ep4 <= R_REGS.moni_ep4_sel;
R_MONI_C.fifo_ep6 <= R_REGS.moni_ep6_sel;
R_MONI_C.fifo_ep8 <= R_REGS.moni_ep8_sel;
R_MONI_C.flag_ep4_empty <= not FX2_FLAG_N(c_flag_rx_ef);
R_MONI_C.flag_ep4_almost <= R_REGS.moni_ep4_pf;
R_MONI_C.flag_ep6_full <= not FX2_FLAG_N(c_flag_tx_ff);
R_MONI_C.flag_ep6_almost <= R_REGS.moni_ep6_pf;
R_MONI_C.flag_ep8_full <= not FX2_FLAG_N(c_flag_tx2_ff);
R_MONI_C.flag_ep8_almost <= R_REGS.moni_ep8_pf;
R_MONI_C.slrd <= not FX2_SLRD_N;
R_MONI_C.slwr <= not FX2_SLWR_N;
R_MONI_C.pktend <= not FX2_PKTEND_N;
R_MONI_S <= R_MONI_C;
end if;
end if;
 
end process proc_moni;
 
proc_almost: process (RXSIZE_USR, TXSIZE_USR, TX2SIZE_USR)
begin
 
-- rxsize_usr is the number of bytes to read
-- txsize_usr is the number of bytes to write
if unsigned(RXSIZE_USR) <= RXAEMPTY_THRES then
RXAEMPTY <= '1';
else
RXAEMPTY <= '0';
end if;
 
if unsigned(TXSIZE_USR) <= TXAFULL_THRES then
TXAFULL <= '1';
else
TXAFULL <= '0';
end if;
 
if unsigned(TX2SIZE_USR) <= TX2AFULL_THRES then
TX2AFULL <= '1';
else
TX2AFULL <= '0';
end if;
 
end process proc_almost;
 
TXBUSY <= TXBUSY_L;
TX2BUSY <= TX2BUSY_L;
 
MONI <= R_MONI_S;
end syn;
/rtl/bplib/fx2lib/fx2_2fifoctl_ic.vbom
0,0 → 1,13
# libs
../../vlib/slvtypes.vhd
../../vlib/xlib/xlib.vhd
../../vlib/memlib/memlib.vhd
fx2lib.vhd
# components
../../vlib/xlib/iob_reg_o.vbom
../../vlib/xlib/iob_reg_i_gen.vbom
../../vlib/xlib/iob_reg_o_gen.vbom
../../vlib/xlib/iob_reg_io_gen.vbom
../../vlib/memlib/fifo_2c_dram.vbom
# design
fx2_2fifoctl_ic.vhd
/rtl/bplib/fx2lib/fx2_3fifoctl_ic.vbom
0,0 → 1,13
# libs
../../vlib/slvtypes.vhd
../../vlib/xlib/xlib.vhd
../../vlib/memlib/memlib.vhd
fx2lib.vhd
# components
../../vlib/xlib/iob_reg_o.vbom
../../vlib/xlib/iob_reg_i_gen.vbom
../../vlib/xlib/iob_reg_o_gen.vbom
../../vlib/xlib/iob_reg_io_gen.vbom
../../vlib/memlib/fifo_2c_dram.vbom
# design
fx2_3fifoctl_ic.vhd
/rtl/bplib/fx2lib/fx2lib.vhd
0,0 → 1,172
-- $Id: fx2lib.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: fx2lib
-- Description: Cypress ez-usb fx2 support
--
-- Dependencies: -
-- Tool versions: xst 12.1, 13.1, 13.3; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-14 453 1.3 use afull/aempty logic instead of exporting size
-- 2012-01-03 449 1.2.1 reorganize fx2ctl_moni; hardcode ep's
-- 2012-01-01 448 1.2 add fx2_2fifoctl_ic
-- 2011-12-25 445 1.1 change pktend iface in fx2_2fifoctl_as
-- 2011-07-17 394 1.0.1 add c_fifo_epx and fx2ctl_moni_type
-- 2011-07-07 389 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package fx2lib is
 
constant c_fifo_ep2 : slv2 := "00"; -- fifo address: end point 2
constant c_fifo_ep4 : slv2 := "01"; -- fifo address: end point 4
constant c_fifo_ep6 : slv2 := "10"; -- fifo address: end point 6
constant c_fifo_ep8 : slv2 := "11"; -- fifo address: end point 8
 
type fx2ctl_moni_type is record -- fx2ctl monitor port
fifo_ep4 : slbit; -- fifo 1 (ep4) active;
fifo_ep6 : slbit; -- fifo 2 (ep6) active;
fifo_ep8 : slbit; -- fifo 3 (ep8) active;
flag_ep4_empty : slbit; -- ep4 empty flag (latched);
flag_ep4_almost : slbit; -- ep4 almost empty flag (latched);
flag_ep6_full : slbit; -- ep6 full flag (latched);
flag_ep6_almost : slbit; -- ep6 almost full flag (latched);
flag_ep8_full : slbit; -- ep8 full flag (latched);
flag_ep8_almost : slbit; -- ep8 almost full flag (latched);
slrd : slbit; -- read strobe
slwr : slbit; -- write strobe
pktend : slbit; -- pktend strobe
end record fx2ctl_moni_type;
 
constant fx2ctl_moni_init : fx2ctl_moni_type := (
'0','0','0', -- fifo_ep[468]
'0','0', -- flag_ep4_(empty|almost)
'0','0', -- flag_ep6_(full|almost)
'0','0', -- flag_ep8_(full|almost)
'0','0','0' -- slrd, slwr, pktend
);
 
 
-- -------------------------------------
component fx2_2fifoctl_as is -- EZ-USB FX2 driver (2 fifo; async)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
RDPWLDELAY : positive := 5; -- slrd low delay in clock cycles
RDPWHDELAY : positive := 5; -- slrd high delay in clock cycles
WRPWLDELAY : positive := 5; -- slwr low delay in clock cycles
WRPWHDELAY : positive := 7; -- slwr high delay in clock cycles
FLAGDELAY : positive := 2); -- flag delay in clock cycles
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit data busy
TXAFULL : out slbit; -- transmit almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
 
component fx2_2fifoctl_ic is -- EZ-USB FX2 driver (2 fifo; int clk)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1); -- threshold for tx afull flag
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit data busy
TXAFULL : out slbit; -- transmit almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
 
component fx2_3fifoctl_ic is -- EZ-USB FX2 driver (3 fifo; int clk)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
TX2AFULL_THRES : natural := 1); -- threshold for tx2 afull flag
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit 1 data in
TXENA : in slbit; -- transmit 1 data enable
TXBUSY : out slbit; -- transmit 1 data busy
TXAFULL : out slbit; -- transmit 1 almost full flag
TX2DATA : in slv8; -- transmit 2 data in
TX2ENA : in slbit; -- transmit 2 data enable
TX2BUSY : out slbit; -- transmit 2 data busy
TX2AFULL : out slbit; -- transmit 2 almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
 
end package fx2lib;
/rtl/bplib/fx2lib/fx2_2fifoctl_as.vhd
0,0 → 1,647
-- $Id: fx2_2fifoctl_as.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fx2_2fifoctl_as - syn
-- Description: Cypress EZ-USB FX2 driver (2 fifo; async)
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_i_gen
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
-- memlib/fifo_1c_dram
--
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 12.1, 13.1, 13.3; ghdl 0.26-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2012-01-14 453 13.3 O76x xc3s1200e-4 65 153 64 133 s 7.2
-- 2012-01-03 449 13.3 O76x xc3s1200e-4 67 149 64 133 s 7.2
-- 2011-12-25 445 13.3 O76x xc3s1200e-4 61 147 64 127 s 7.2
-- 2011-12-25 444 13.3 O76x xc3s1200e-4 54 140 64 123 s 7.2
-- 2011-07-07 389 12.1 M53d xc3s1200e-4 45 132 64 109 s 7.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-14 453 1.3 common DELAY for PE and WR; use aempty/afull logic
-- 2012-01-04 450 1.2.2 use new FLAG layout (EF,FF now fixed)
-- 2012-01-03 449 1.2.1 use new fx2ctl_moni layout; hardcode ep's
-- 2011-12-25 445 1.2 change pktend handling, now timer based
-- 2011-11-25 433 1.1.1 now numeric_std clean
-- 2011-07-30 400 1.1 capture rx data in 2nd last s_rdpwh cycle
-- 2011-07-24 389 1.0.2 use FX2_FLAG_N to signal that flags are act.low
-- 2011-07-17 394 1.0.1 (RX|TX)FIFOEP now generics; add MONI port
-- 2011-07-08 390 1.0 Initial version
--
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.xlib.all;
use work.memlib.all;
use work.fx2lib.all;
 
entity fx2_2fifoctl_as is -- EZ-USB FX2 driver (2 fifo; async)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
RDPWLDELAY : positive := 5; -- slrd low delay in clock cycles
RDPWHDELAY : positive := 5; -- slrd high delay in clock cycles
WRPWLDELAY : positive := 5; -- slwr low delay in clock cycles
WRPWHDELAY : positive := 7; -- slwr high delay in clock cycles
FLAGDELAY : positive := 2); -- flag delay in clock cycles
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit data busy
TXAFULL : out slbit; -- transmit almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end fx2_2fifoctl_as;
 
 
architecture syn of fx2_2fifoctl_as is
 
constant c_rxfifo : slv2 := c_fifo_ep4;
constant c_txfifo : slv2 := c_fifo_ep6;
constant c_flag_prog : integer := 0;
constant c_flag_tx_ff : integer := 1;
constant c_flag_rx_ef : integer := 2;
constant c_flag_tx2_ff : integer := 3;
 
type state_type is (
s_init, -- s_init: init state
s_rdprep, -- s_rdprep: prepare read
s_rdwait, -- s_rdwait: wait for data
s_rdpwl, -- s_rdpwl: read, strobe low
s_rdpwh, -- s_rdpwh: read, strobe high
s_wrprep, -- s_wrprep: prepare write
s_wrpwl, -- s_wrpwl: write, strobe low
s_wrpwh, -- s_wrpwh: write, strobe high
s_peprep, -- s_peprep: prepare pktend
s_pepwl, -- s_pepwl: pktend, strobe low
s_pepwh -- s_pepwh: pktend, strobe high
);
type regs_type is record
state : state_type; -- state
petocnt : slv(PETOWIDTH-1 downto 0); -- pktend time out counter
pepend : slbit; -- pktend pending
dlycnt : slv4; -- wait delay counter
moni_ep4_sel : slbit; -- ep4 (rx) select
moni_ep6_sel : slbit; -- ep6 (tx) select
moni_ep4_pf : slbit; -- ep4 (rx) prog flag
moni_ep6_pf : slbit; -- ep6 (rx) prog flag
end record regs_type;
 
constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0');
 
constant regs_init : regs_type := (
s_init, -- state
petocnt_init, -- petocnt
'0', -- pepend
(others=>'0'), -- cntdly
'0','0', -- moni_ep(4|6)_sel
'0','0' -- moni_ep(4|6)_pf
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
 
signal FX2_FIFO : slv2 := (others=>'0');
signal FX2_FIFO_CE : slbit := '0';
signal FX2_FLAG_N : slv4 := (others=>'0');
signal FX2_SLRD_N : slbit := '1';
signal FX2_SLWR_N : slbit := '1';
signal FX2_SLOE_N : slbit := '1';
signal FX2_PKTEND_N : slbit := '1';
signal FX2_DATA_CEI : slbit := '0';
signal FX2_DATA_CEO : slbit := '0';
signal FX2_DATA_OE : slbit := '0';
 
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXSIZE : slv(RXFAWIDTH downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal TXSIZE : slv(TXFAWIDTH downto 0) := (others=>'0');
 
signal TXBUSY_L : slbit := '0';
begin
 
assert RDPWLDELAY<=2**R_REGS.dlycnt'length and
RDPWHDELAY<=2**R_REGS.dlycnt'length and RDPWHDELAY>=2 and
WRPWLDELAY<=2**R_REGS.dlycnt'length and
WRPWHDELAY<=2**R_REGS.dlycnt'length and
FLAGDELAY<=2**R_REGS.dlycnt'length
report "assert(*DELAY <= 2**dlycnt'length and RDPWHDELAY >=2)"
severity failure;
 
assert RXAEMPTY_THRES<=2**RXFAWIDTH and
TXAFULL_THRES<=2**TXFAWIDTH
report "assert((RXAEMPTY|TXAFULL)_THRES <= 2**(RX|TX)FAWIDTH)"
severity failure;
 
IOB_FX2_FIFO : iob_reg_o_gen
generic map (
DWIDTH => 2,
INIT => '0')
port map (
CLK => CLK,
CE => FX2_FIFO_CE,
DO => FX2_FIFO,
PAD => O_FX2_FIFO
);
IOB_FX2_FLAG : iob_reg_i_gen
generic map (
DWIDTH => 4,
INIT => '0')
port map (
CLK => CLK,
CE => '1',
DI => FX2_FLAG_N,
PAD => I_FX2_FLAG
);
IOB_FX2_SLRD : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_SLRD_N,
PAD => O_FX2_SLRD_N
);
IOB_FX2_SLWR : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_SLWR_N,
PAD => O_FX2_SLWR_N
);
IOB_FX2_SLOE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_SLOE_N,
PAD => O_FX2_SLOE_N
);
IOB_FX2_PKTEND : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_PKTEND_N,
PAD => O_FX2_PKTEND_N
);
 
IOB_FX2_DATA : iob_reg_io_gen
generic map (
DWIDTH => 8,
PULL => "KEEP")
port map (
CLK => CLK,
CEI => FX2_DATA_CEI,
CEO => FX2_DATA_CEO,
OE => FX2_DATA_OE,
DI => RXFIFO_DI, -- input data (read from pad)
DO => TXFIFO_DO, -- output data (write to pad)
PAD => IO_FX2_DATA
);
 
RXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZE => RXSIZE
);
 
TXFIFO : fifo_1c_dram -- output fifo, 1 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET,
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY_L,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZE => TXSIZE
);
proc_regs: process (CLK)
begin
 
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
 
end process proc_regs;
 
proc_next: process (R_REGS, CE_USEC,
FX2_FLAG_N, TXFIFO_VAL, RXFIFO_BUSY, TXBUSY_L)
 
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
 
variable idly_ld : slbit := '0';
variable idly_val : slv(r.dlycnt'range) := (others=>'0');
variable idly_end : slbit := '0';
variable idly_end1 : slbit := '0';
 
variable iflag_rdok : slbit := '0';
variable iflag_wrok : slbit := '0';
 
variable ififo_ce : slbit := '0';
variable ififo : slv2 := "00";
 
variable irxfifo_ena : slbit := '0';
variable itxfifo_hold : slbit := '0';
 
variable islrd : slbit := '0';
variable islwr : slbit := '0';
variable isloe : slbit := '0';
variable ipktend : slbit := '0';
 
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
variable idata_oe : slbit := '0';
 
variable imoni : fx2ctl_moni_type := fx2ctl_moni_init;
procedure go_rdprep(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ififo_ce : out slbit;
ififo : out slv2) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length));
ififo_ce := '1';
ififo := c_rxfifo;
nstate := s_rdprep;
end procedure go_rdprep;
 
procedure go_wrprep(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ififo_ce : out slbit;
ififo : out slv2) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length));
ififo_ce := '1';
ififo := c_txfifo;
nstate := s_wrprep;
end procedure go_wrprep;
 
procedure go_peprep(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ififo_ce : out slbit;
ififo : out slv2) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length));
ififo_ce := '1';
ififo := c_txfifo;
nstate := s_peprep;
end procedure go_peprep;
 
procedure go_rdpwl(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
islrd : out slbit) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(RDPWLDELAY-1, n.dlycnt'length));
islrd := '1';
nstate := s_rdpwl;
end procedure go_rdpwl;
 
procedure go_wrpwl(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
islwr : out slbit) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWLDELAY-1, n.dlycnt'length));
islwr := '1';
nstate := s_wrpwl;
end procedure go_wrpwl;
 
procedure go_pepwl(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ipktend : out slbit) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWLDELAY-1, n.dlycnt'length));
ipktend := '1';
nstate := s_pepwl;
end procedure go_pepwl;
begin
 
r := R_REGS;
n := R_REGS;
 
ififo_ce := '0';
ififo := "00";
 
irxfifo_ena := '0';
itxfifo_hold := '1';
islrd := '0';
islwr := '0';
isloe := '0';
ipktend := '0';
 
idata_cei := '0';
idata_ceo := '0';
idata_oe := '0';
 
imoni := fx2ctl_moni_init;
iflag_rdok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low!
iflag_wrok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low!
idly_ld := '0';
idly_val := (others=>'0');
idly_end := '1';
idly_end1 := '0';
if unsigned(r.dlycnt) /= 0 then
idly_end := '0';
end if;
if unsigned(r.dlycnt) = 1 then
idly_end1 := '1';
end if;
 
case r.state is
when s_init => -- s_init:
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
 
when s_rdprep => -- s_rdprep: prepare read
if idly_end = '1' then
n.state := s_rdwait;
end if;
 
when s_rdwait => -- s_rdwait: wait for data
if r.pepend='1' and TXFIFO_VAL='0' then
go_peprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
elsif iflag_rdok='1' and
(RXFIFO_BUSY='0' and TXBUSY_L='0') then
go_rdpwl(n.state, idly_ld, idly_val, islrd);
 
elsif TXFIFO_VAL = '1' then
go_wrprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
when s_rdpwl => -- s_rdpwl: read, strobe low
idata_cei := '1';
isloe := '1';
if idly_end = '1' then
idly_ld := '1';
idly_val := slv(to_unsigned(RDPWHDELAY-1, n.dlycnt'length));
n.state := s_rdpwh;
else
islrd := '1';
n.state := s_rdpwl;
end if;
 
-- Note: data is sampled and written into rxfifo in 2nd last cycle in the
-- last cycle the rxfifo busy reflects therefore last written byte
-- and safely indicates whether another byte will fit.
when s_rdpwh => -- s_rdpwh: read, strobe high
idata_cei := '1';
isloe := '1';
if idly_end1 = '1' then -- 2nd last cycle
irxfifo_ena := '1'; -- capture rxdata
end if;
if idly_end = '1' then -- last cycle
if iflag_rdok='1' and
(RXFIFO_BUSY='0' and TXBUSY_L='0') then
go_rdpwl(n.state, idly_ld, idly_val, islrd);
 
elsif TXFIFO_VAL = '1' then
go_wrprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
 
else
n.state := s_rdwait;
end if;
end if;
 
when s_wrprep => -- s_wrprep: prepare write
if idly_end = '1' then
if iflag_wrok = '1' then
go_wrpwl(n.state, idly_ld, idly_val, islwr);
else
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
end if;
when s_wrpwl => -- s_wrpwl: write, strobe low
idata_ceo := '1';
idata_oe := '1';
if idly_end = '1' then
idata_ceo := '0';
itxfifo_hold := '0';
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWHDELAY-1, n.dlycnt'length));
n.state := s_wrpwh;
else
islwr := '1';
n.state := s_wrpwl;
end if;
 
when s_wrpwh => -- s_wrpwh: write, strobe high
idata_oe := '1';
if idly_end = '1' then
if iflag_wrok='1' and TXFIFO_VAL='1' then
go_wrpwl(n.state, idly_ld, idly_val, islwr);
elsif iflag_wrok='1' and r.pepend='1' and TXFIFO_VAL='0' then
go_pepwl(n.state, idly_ld, idly_val, ipktend);
else
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
end if;
 
when s_peprep => -- s_peprep: prepare pktend
if idly_end = '1' then
if iflag_wrok = '1' then
go_pepwl(n.state, idly_ld, idly_val, ipktend);
else
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
end if;
when s_pepwl => -- s_pepwl: pktend, strobe low
if idly_end = '1' then
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWHDELAY-1, n.dlycnt'length));
n.state := s_pepwh;
else
ipktend := '1';
n.state := s_pepwl;
end if;
when s_pepwh => -- s_pepwh: pktend, strobe high
if idly_end = '1' then
n.pepend := '0';
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
 
when others => null;
end case;
 
if idly_ld = '1' then
n.dlycnt := idly_val;
elsif idly_end = '0' then
n.dlycnt := slv(unsigned(r.dlycnt) - 1);
end if;
 
-- pktend time-out handling:
-- if tx fifo is non-empty, set counter to max
-- if tx fifo is empty, count down every usec
-- on 1->0 transition queue pktend request
if TXFIFO_VAL = '1' then
n.petocnt := (others=>'1');
else
if CE_USEC = '1' and unsigned(r.petocnt) /= 0 then
n.petocnt := slv(unsigned(r.petocnt) - 1);
if unsigned(r.petocnt) = 1 then
n.pepend := '1';
end if;
end if;
end if;
 
n.moni_ep4_sel := '0';
n.moni_ep6_sel := '0';
if r.state = s_wrprep or r.state = s_wrpwl or r.state = s_wrpwh or
r.state = s_peprep or r.state = s_pepwl or r.state = s_pepwh then
n.moni_ep6_sel := '1';
n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog);
else
n.moni_ep4_sel := '1';
n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog);
end if;
imoni.fifo_ep4 := r.moni_ep4_sel;
imoni.fifo_ep6 := r.moni_ep6_sel;
imoni.flag_ep4_empty := not FX2_FLAG_N(c_flag_rx_ef);
imoni.flag_ep4_almost := r.moni_ep4_pf;
imoni.flag_ep6_full := not FX2_FLAG_N(c_flag_tx_ff);
imoni.flag_ep6_almost := r.moni_ep6_pf;
imoni.slrd := islrd;
imoni.slwr := islwr;
imoni.pktend := ipktend;
N_REGS <= n;
 
FX2_FIFO_CE <= ififo_ce;
FX2_FIFO <= ififo;
 
FX2_SLRD_N <= not islrd;
FX2_SLWR_N <= not islwr;
FX2_SLOE_N <= not isloe;
FX2_PKTEND_N <= not ipktend;
 
FX2_DATA_CEI <= idata_cei;
FX2_DATA_CEO <= idata_ceo;
FX2_DATA_OE <= idata_oe;
 
RXFIFO_ENA <= irxfifo_ena;
TXFIFO_HOLD <= itxfifo_hold;
 
MONI <= imoni;
end process proc_next;
 
proc_almost: process (RXSIZE, TXSIZE)
begin
 
-- (rx|tx)size is the number of bytes in fifo
-- --> rxsize is number of bytes which can be read
-- --> 2**txfawidth-txsize is is number of bytes which can be written
if unsigned(RXSIZE) <= RXAEMPTY_THRES then
RXAEMPTY <= '1';
else
RXAEMPTY <= '0';
end if;
 
if unsigned(TXSIZE) >= 2**TXFAWIDTH-TXAFULL_THRES then
TXAFULL <= '1';
else
TXAFULL <= '0';
end if;
 
end process proc_almost;
 
TXBUSY <= TXBUSY_L;
end syn;
/rtl/bplib/fx2lib/fx2_2fifoctl_as.vbom
0,0 → 1,13
# libs
../../vlib/slvtypes.vhd
../../vlib/xlib/xlib.vhd
../../vlib/memlib/memlib.vhd
fx2lib.vhd
# components
../../vlib/xlib/iob_reg_o.vbom
../../vlib/xlib/iob_reg_i_gen.vbom
../../vlib/xlib/iob_reg_o_gen.vbom
../../vlib/xlib/iob_reg_io_gen.vbom
../../vlib/memlib/fifo_1c_dram.vbom
# design
fx2_2fifoctl_as.vhd
/rtl/bplib/fx2lib/Makefile
0,0 → 1,24
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2010-05-23 293 1.0 Initial version (cloned..)
#
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
ISE_PATH = xc3s1200e-fg320-4
#
.PHONY : all clean
#
all : $(NGC_all)
#
clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
include $(VBOM_all:.vbom=.dep_xst)
#
/rtl/bplib/fx2lib
rtl/bplib/fx2lib Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: rtl/bplib/nexys2/nexys2lib.vhd =================================================================== --- rtl/bplib/nexys2/nexys2lib.vhd (revision 16) +++ rtl/bplib/nexys2/nexys2lib.vhd (revision 17) @@ -1,4 +1,4 @@ --- $Id: nexys2lib.vhd 433 2011-11-27 22:04:39Z mueller $ +-- $Id: nexys2lib.vhd 467 2013-01-02 19:49:05Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -20,6 +20,8 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2013-01-01 467 1.4 add nexys2_cuff_aif, nexys2_fusp_cuff_aif +-- 2011-12-23 444 1.3 remove clksys output hack -- 2011-11-26 433 1.2 remove n2_cram_* modules, now in nxcramlib -- 2011-11-23 432 1.1 remove O_FLA_CE_N port in cram driver/dummy -- 2010-11-13 338 1.0.2 add O_CLKSYS to aif's (DCM derived system clock) @@ -40,7 +42,6 @@ component nexys2_aif is -- NEXYS 2, abstract iface, base port ( I_CLK50 : in slbit; -- 50 MHz board clock - O_CLKSYS : out slbit; -- DCM derived system clock I_RXD : in slbit; -- receive data (board view) O_TXD : out slbit; -- transmit data (board view) I_SWI : in slv8; -- n2 switches @@ -65,7 +66,6 @@ component nexys2_fusp_aif is -- NEXYS 2, abstract iface, base+fusp port ( I_CLK50 : in slbit; -- 50 MHz board clock - O_CLKSYS : out slbit; -- DCM derived system clock I_RXD : in slbit; -- receive data (board view) O_TXD : out slbit; -- transmit data (board view) I_SWI : in slv8; -- n2 switches @@ -91,4 +91,72 @@ ); end component; +component nexys2_cuff_aif is -- NEXYS 2, abstract iface, base+cuff + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end component; + +component nexys2_fusp_cuff_aif is -- NEXYS 2, abstract iface, +fusp+cuff + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit; -- fusp: rs232 tx + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end component; + end package nexys2lib;
/rtl/bplib/nexys2/tb/nexys2_fusp_dummy.vhd
1,4 → 1,4
-- $Id: nexys2_fusp_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: nexys2_fusp_dummy.vhd 467 2013-01-02 19:49:05Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
12,7 → 12,7
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys2_dummy - syn
-- Module Name: nexys2_fusp_dummy - syn
-- Description: nexys2 minimal target (base; serport loopback)
--
-- Dependencies: -
22,6 → 22,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.3 remove clksys output hack
-- 2011-11-26 433 1.2 use nxcramlib
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_dummy
-- 2010-11-13 338 1.0.2 add O_CLKSYS (for DCM derived system clock)
39,7 → 40,6
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
69,7 → 69,6
begin
 
O_CLKSYS <= I_CLK50; -- use 50 MHz clock
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
1,4 → 1,4
-- $Id: tb_nexys2_fusp.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: tb_nexys2_fusp.vhd 467 2013-01-02 19:49:05Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
15,9 → 15,12
-- Module Name: tb_nexys2_fusp - sim
-- Description: Test bench for nexys2 (base+fusp)
--
-- Dependencies: vlib/rlink/tb/tbcore_rlink_dcm
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/dcm_sfs
-- rlink/tb/tbcore_rlink
-- tb_nexys2_core
-- vlib/serport/serport_uart_rxtx
-- serport/serport_uart_rxtx
-- nexys2_fusp_aif [UUT]
--
-- To test: generic, any nexys2_fusp_aif target
27,6 → 30,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.2 new system clock scheme, new tbcore_rlink iface
-- 2011-11-26 433 3.1.1 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 3.1 update O_FLA_CE_N usage
-- 2011-11-19 427 3.0.1 now numeric_std clean
46,9 → 50,11
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serport.all;
use work.xlib.all;
use work.nexys2lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
 
entity tb_nexys2_fusp is
end tb_nexys2_fusp;
56,8 → 62,11
architecture sim of tb_nexys2_fusp is
signal CLKOSC : slbit := '0';
signal CLKSYS : slbit := '0';
signal CLKCOM : slbit := '0';
 
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
105,29 → 114,44
 
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
 
constant clockosc_period : time := 20 ns;
constant clockosc_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 9 ns;
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
 
begin
TBCORE : tbcore_rlink_dcm
CLKGEN : simclk
generic map (
CLKOSC_PERIOD => clockosc_period,
CLKOSC_OFFSET => clockosc_offset,
SETUP_TIME => setup_time,
C2OUT_TIME => c2out_time)
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLKOSC => CLKOSC,
CLKSYS => CLKSYS,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
DCM_COM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
 
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
 
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
 
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
 
N2CORE : entity work.tb_nexys2_core
149,7 → 173,6
UUT : nexys2_fusp_aif
port map (
I_CLK50 => CLKOSC,
O_CLKSYS => CLKSYS,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
178,7 → 201,7
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKSYS,
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
217,11 → 240,10
begin
loop
wait until rising_edge(CLKSYS);
wait for c2out_time;
wait until rising_edge(CLKCOM);
 
if RXERR = '1' then
writetimestamp(oline, SB_CLKCYCLE, " : seen RXERR=1");
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom
7,14 → 7,19
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serport.vhd
../../../vlib/xlib/xlib.vhd
../nexys2lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/rlink/tb/tbcore_rlink_dcm.vbom
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/dcm_sfs_gsim.vbom
tb_nexys2_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
nexys2_fusp_aif : nexys2_fusp_dummy.vbom
${nexys2_fusp_aif := nexys2_fusp_dummy.vbom}
# design
tb_nexys2_fusp.vhd
@top:tb_nexys2_fusp
/rtl/bplib/nexys2/tb/Makefile
1,7 → 1,8
# $Id: Makefile 433 2011-11-27 22:04:39Z mueller $
# $Id: Makefile 467 2013-01-02 19:49:05Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-01-01 467 1.2.1 add tb_nexys2_fusp_cuff_dummy
# 2011-11-26 433 1.2 remove tb_n2_cram_memctl_as (moved to nxcramlib)
# 2011-08-13 405 1.1 use includes from rtl/make
# 2010-05-30 297 1.0.2 use tb_n2_cram_memctl_as now
8,7 → 9,9
# 2010-05-28 295 1.0.1 add tb_.._dummy's
# 2007-09-23 84 1.0 Initial version
#
EXE_all = tb_nexys2_dummy tb_nexys2_fusp_dummy
EXE_all = tb_nexys2_dummy
EXE_all += tb_nexys2_fusp_dummy
EXE_all += tb_nexys2_fusp_cuff_dummy
#
ISE_PATH = xc3s1200e-fg320-4
#
/rtl/bplib/nexys2/nexys2_time_fx2_ic.ucf
0,0 → 1,26
## $Id: nexys2_time_fx2_ic.ucf 448 2012-01-02 21:55:11Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2012-01-01 448 1.0 Initial version
##
## timing rules for a 30 MHz internal clock design:
## Period: 30 MHz
## clk->out: longest setup time in FX2 is t_SRD (clk->SLRD) of 18.7 ns
## clk->out < 33.3-18.7 = 14.6 ns
## --> use 10 ns
##
 
## The nexys2 board has unfortunately the FX2 IFCLK *not* connected to a
## clock capable pin -> not ok when FX2 uses internal clock. So allow par
## to route from a 'normal' pin to a clock net. Not nice, compromizes the
## timing, but unavoidable on nexys2 (Note: nexys3 and atlys are ok).
## In practice IFCLK to pad times are quite similar on nexys2 and nexys3...
NET "I_FX2_IFCLK" CLOCK_DEDICATED_ROUTE = FALSE;
 
##
NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK";
TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %;
OFFSET = IN 2.5 ns BEFORE "I_FX2_IFCLK";
OFFSET = OUT 10 ns AFTER "I_FX2_IFCLK";
/rtl/bplib/nexys2/nexys2_pins_fx2.ucf
0,0 → 1,36
## $Id: nexys2_pins_fx2.ucf 397 2011-07-24 09:43:07Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-07-05 389 1.0 Initial version
##
## Cypress EZ-USB FX2 Interface ----------------------------------------------
##
##
NET "I_FX2_IFCLK" LOC = "t15" | IOSTANDARD=LVCMOS33;
##
NET "IO_FX2_DATA<0>" LOC = "r14" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<1>" LOC = "r13" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<2>" LOC = "p13" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<3>" LOC = "t12" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<4>" LOC = "n11" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<5>" LOC = "r11" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<6>" LOC = "p10" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<7>" LOC = "r10" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER;
##
NET "O_FX2_SLWR_N" LOC = "v9" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_FX2_SLRD_N" LOC = "n9" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_FX2_SLOE_N" LOC = "v15" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
NET "O_FX2_PKTEND_N" LOC = "v12" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
NET "O_FX2_FIFO<0>" LOC = "t14" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_FX2_FIFO<1>" LOC = "v13" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
## assume that PA.7 is used a FLAGD (and not as SLCS#)
NET "I_FX2_FLAG<0>" LOC = "v14" | IOSTANDARD=LVCMOS33; ## flag a (program)
NET "I_FX2_FLAG<1>" LOC = "u14" | IOSTANDARD=LVCMOS33; ## flag b (full)
NET "I_FX2_FLAG<2>" LOC = "v16" | IOSTANDARD=LVCMOS33; ## flag c (empty)
NET "I_FX2_FLAG<3>" LOC = "t16" | IOSTANDARD=LVCMOS33; ## flag d (slcs)
##
/rtl/bplib/nexys2/nexys2_pins.ucf
1,4 → 1,4
## $Id: nexys2_pins.ucf 432 2011-11-25 20:16:28Z mueller $
## $Id: nexys2_pins.ucf 444 2011-12-25 10:04:58Z mueller $
##
## Pin locks for Nexys 2 core functionality (for 1200k FPGA)
## - internal RS232
7,6 → 7,7
##
## Revision History:
## Date Rev Version Comment
## 2011-11-23 444 1.1 remove clksys output hack
## 2010-11-13 338 1.0.3 add O_CLKSYS (for DCM derived system clock)
## 2010-11-06 336 1.0.2 Rename CLK -> I_CLK50
## 2010-05-23 294 1.0.1 use ADV_N rather ADV
17,10 → 18,6
## clocks --------------------------------------------------------------------
NET "I_CLK50" LOC = "b8" | IOSTANDARD=LVCMOS33;
##
## system clock on FX2 connector ---------------------------------------------
## (use FX2_CLKIO pin; currently only used to make test benches happy !!)
NET "O_CLKSYS" LOC = "m9" | IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW;
##
## RS232 interface -----------------------------------------------------------
NET "I_RXD" LOC = "u6" | IOSTANDARD=LVCMOS33;
NET "O_TXD" LOC = "p9" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW;
/rtl/bplib/nexys3/tb/nexys3_fusp_dummy.vbom File deleted
/rtl/bplib/nexys3/tb/nexys3_fusp_dummy.vhd File deleted
/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd
1,4 → 1,4
-- $Id: tb_nexys3_fusp.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: tb_nexys3_fusp.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
15,10 → 15,12
-- Module Name: tb_nexys3_fusp - sim
-- Description: Test bench for nexys3 (base+fusp)
--
-- Dependencies: vlib/rlink/tb/tbcore_rlink_dcm
-- vlib/xlib/dcm_sfs
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/dcm_sfs
-- rlink/tb/tbcore_rlink
-- tb_nexys3_core
-- vlib/serport/serport_uart_rxtx
-- serport/serport_uart_rxtx
-- nexys3_fusp_aif [UUT]
--
-- To test: generic, any nexys3_fusp_aif target
28,6 → 30,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_fusp)
------------------------------------------------------------------------------
 
52,9 → 55,12
 
architecture sim of tb_nexys3_fusp is
signal CLKOSC : slbit := '0';
signal CLKSYS : slbit := '0';
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
 
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
103,30 → 109,21
 
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
 
constant clockosc_period : time := 10 ns;
constant clockosc_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 9 ns;
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
 
begin
TBCORE : tbcore_rlink_dcm
CLKGEN : simclk
generic map (
CLKOSC_PERIOD => clockosc_period,
CLKOSC_OFFSET => clockosc_offset,
SETUP_TIME => setup_time,
C2OUT_TIME => c2out_time)
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLKOSC => CLKOSC,
CLKSYS => CLKSYS,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
 
DCM_SYS : dcm_sfs
DCM_COM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
133,10 → 130,23
CLKIN_PERIOD => 10.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKSYS,
CLKFX => CLKCOM,
LOCKED => open
);
 
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
 
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
 
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
 
N3CORE : entity work.tb_nexys3_core
187,7 → 197,7
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKSYS,
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
226,11 → 236,10
begin
loop
wait until rising_edge(CLKSYS);
wait for c2out_time;
wait until rising_edge(CLKCOM);
 
if RXERR = '1' then
writetimestamp(oline, SB_CLKCYCLE, " : seen RXERR=1");
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom
11,13 → 11,15
../nexys3lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
sys_conf : sys_conf_sim.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/rlink/tb/tbcore_rlink_dcm.vbom
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/dcm_sfs_gsim.vbom
tb_nexys3_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
nexys3_fusp_aif : nexys3_fusp_dummy.vbom
${nexys3_fusp_aif := nexys3_fusp_dummy.vbom}
# design
tb_nexys3_fusp.vhd
@top:tb_nexys3_fusp
/rtl/bplib/bpgen/bp_swibtnled.vbom
3,7 → 3,7
../../vlib/genlib/genlib.vhd
../../vlib/xlib/xlib.vhd
bpgenlib.vbom
## sys_conf : sys_conf.vhd
## ${sys_conf := sys_conf.vhd}
# components
../../vlib/xlib/iob_reg_i_gen.vbom
../../vlib/xlib/iob_reg_o_gen.vbom
/rtl/bplib/s3board/tb/tb_s3_sram_memctl.vbom
4,7 → 4,8
../../../vlib/simlib/simlib.vhd
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../issi/is61lv25616al.vbom
uut : ../s3_sram_memctl.vbom
${uut := ../s3_sram_memctl.vbom}
# design
tb_s3_sram_memctl.vhd
/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd
1,4 → 1,4
-- $Id: tb_s3board_fusp.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: tb_s3board_fusp.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
15,10 → 15,12
-- Module Name: tb_s3board_fusp - sim
-- Description: Test bench for s3board (base+fusp)
--
-- Dependencies: vlib/rlink/tb/tbcore_rlink_dcm
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tb/tbcore_rlink
-- tb_s3board_core
-- vlib/serport/serport_uart_rxtx
-- s3board_fusp_aif [UUT]
-- serport/serport_uart_rxtx
--
-- To test: generic, any s3board_fusp_aif target
--
26,6 → 28,7
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-30 351 3.0 use rlink/tb now
-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50
55,6 → 58,9
architecture sim of tb_s3board_fusp is
signal CLK : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
100,24 → 106,29
 
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
 
begin
 
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
 
TBCORE : tbcore_rlink
generic map (
CLK_PERIOD => clock_period,
CLK_OFFSET => clock_offset,
SETUP_TIME => setup_time,
C2OUT_TIME => c2out_time)
port map (
CLK => CLK,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
CLK => CLK,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
 
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
200,10 → 211,9
loop
wait until rising_edge(CLK);
wait for c2out_time;
 
if RXERR = '1' then
writetimestamp(oline, SB_CLKCYCLE, " : seen RXERR=1");
writetimestamp(oline, CLK_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom
11,10 → 11,12
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
tb_s3board_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
s3board_fusp_aif : s3board_fusp_dummy.vbom
${s3board_fusp_aif := s3board_fusp_dummy.vbom}
# design
tb_s3board_fusp.vhd
@top:tb_s3board_fusp
/rtl/bplib/s3board/tb/Makefile
1,4 → 1,4
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
# $Id: Makefile 444 2011-12-25 10:04:58Z mueller $
#
# Revision History:
# Date Rev Version Comment
9,7 → 9,9
# 2007-11-26 98 1.1 use make includes
# 2007-09-23 84 1.0 Initial version
#
EXE_all = tb_s3board_dummy tb_s3board_fusp_dummy tb_s3_sram_memctl
EXE_all = tb_s3board_dummy
EXE_all += tb_s3board_fusp_dummy
EXE_all += tb_s3_sram_memctl
#
ISE_PATH = xc3s1000-ft256-4
#
/rtl/bplib/s3board/tb/tb_s3_sram_memctl.vhd
1,4 → 1,4
-- $Id: tb_s3_sram_memctl.vhd 432 2011-11-25 20:16:28Z mueller $
-- $Id: tb_s3_sram_memctl.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
16,6 → 16,7
-- Description: Test bench for s3_sram_memctl
--
-- Dependencies: vlib/simlib/simclk
-- vlib/simlib/simclkcnt
-- bplib/issi/is61lv25616al
-- s3_sram_memctl [UUT]
--
30,6 → 31,7
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk/simclkcnt
-- 2011-11-21 432 1.0.6 now numeric_std clean
-- 2010-05-23 293 1.0.5 output # busy cycles; change CHK pipeline logic
-- 2010-05-16 291 1.0.4 rename tb_memctl_s3sram->tb_s3_sram_memctl
86,7 → 88,7
signal R_REF_ADDR_DL : slv18 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : slv31 := (others=>'0');
signal CLK_CYCLE : integer := 0;
 
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
95,16 → 97,17
 
begin
 
SYSCLK : simclk
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
CLK_STOP => CLK_STOP
);
 
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
 
MEM_L : entity work.is61lv25616al
port map (
CE_N => O_MEM_CE_N(0),
/rtl/w11a/pdp11_mem70.vbom
2,7 → 2,7
../vlib/slvtypes.vhd
../ibus/iblib.vhd
pdp11.vbom
sys_conf : sys_conf.vhd
${sys_conf := sys_conf.vhd}
# components
# design
pdp11_mem70.vhd
/rtl/w11a/pdp11_vmbox.vbom
2,7 → 2,7
../vlib/slvtypes.vhd
../ibus/iblib.vhd
pdp11.vbom
sys_conf : sys_conf.vhd
${sys_conf := sys_conf.vhd}
# components
pdp11_mmu.vbom
pdp11_ubmap.vbom
/rtl/w11a/tb/tb_pdp11core.vhd
1,4 → 1,4
-- $Id: tb_pdp11core.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: tb_pdp11core.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
46,6 → 46,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.4 use new simclk/simclkcnt
-- 2011-11-18 427 1.3.2 now numeric_std clean
-- 2011-01-02 352 1.3.1 rename .cpmon->.rlmon
-- 2010-12-30 351 1.3 rename tb_pdp11_core -> tb_pdp11core
116,6 → 117,7
signal CP_DOUT : slv16 := (others=>'0');
 
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
 
signal R_CHKDAT : slv16 := (others=>'0');
signal R_CHKMSK : slv16 := (others=>'0');
130,15 → 132,16
begin
 
SYSCLK : simclk
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_CYCLE => SB_CLKCYCLE,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
 
UUT: entity work.tbd_pdp11core
port map (
626,7 → 629,7
wait for 4*clock_period;
CLK_STOP <= '1';
 
writetimestamp(oline, SB_CLKCYCLE, ": DONE ");
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait; -- suspend proc_stim forever
/rtl/w11a/tb/tb_pdp11core.vbom
6,6 → 6,7
../pdp11.vbom
# components
../../vlib/simlib/simclk.vbom
tbd_pdp11core : tbd_pdp11core.vbom
../../vlib/simlib/simclkcnt.vbom
${tbd_pdp11core := tbd_pdp11core.vbom}
# design
tb_pdp11core.vhd
/rtl/w11a/tb/tbd_pdp11core.vbom
4,7 → 4,7
../../ibus/iblib.vhd
../../ibus/ibdlib.vhd
../pdp11.vbom
sys_conf : ../sys_conf.vhd
${sys_conf := ../sys_conf.vhd}
# components
../../vlib/genlib/clkdivce.vbom
../pdp11_core.vbom
/rtl/w11a/pdp11_tmu.vhd
1,4 → 1,4
-- $Id: pdp11_tmu.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: pdp11_tmu.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
23,6 → 23,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use local clkcycle count instead of simbus global
-- 2011-11-18 427 1.0.7 now numeric_std clean
-- 2010-10-17 333 1.0.6 use ibus V2 interface
-- 2010-06-26 309 1.0.5 add ibmreq.dip,.cacc,.racc to trace
66,6 → 67,7
 
proc_tm: process (CLK)
variable oline : line;
variable clkcycle : integer := 0;
variable ipsw : slv16 := (others=>'0');
variable ibaddr : slv16 := (others=>'0');
variable emaddr : slv22 := (others=>'0');
76,9 → 78,10
file ofile : text open write_mode is "tmu_ofile";
begin
 
 
if rising_edge(CLK) then
 
clkcycle := clkcycle + 1;
if R_FIRST = '1' then
R_FIRST <= '0';
write(oline, string'("#"));
168,7 → 171,7
end if;
 
if wcycle then
write(oline, to_integer(unsigned(SB_CLKCYCLE)), right, 9);
write(oline, clkcycle, right, 9);
write(oline, string'(" 0"));
writeoct(oline, DM_STAT_DP.pc, right, 7);
writeoct(oline, ipsw, right, 7);
/rtl/w11a/pdp11_sys70.vbom
2,7 → 2,7
../vlib/slvtypes.vhd
../ibus/iblib.vhd
pdp11.vbom
sys_conf : sys_conf.vhd
${sys_conf := sys_conf.vhd}
# components
# design
pdp11_sys70.vhd
/rtl/vlib/rlink/rlinklib.vhd
1,6 → 1,6
-- $Id: rlinklib.vhd 442 2011-12-23 10:03:28Z mueller $
-- $Id: rlinklib.vhd 466 2012-12-30 13:26:55Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
16,10 → 16,12
-- Description: Definitions for rlink interface and bus entities
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.3; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 3.3.1 add rlink_rlbmux
-- 2011-12-23 444 3.3 CLK_CYCLE now integer
-- 2011-12-21 442 3.2.1 retire old, deprecated interfaces
-- 2011-12-09 437 3.2 add rlink_core8
-- 2011-11-18 427 3.1.3 now numeric_std clean
169,6 → 171,30
);
end component;
 
component rlink_rlbmux is -- rlink rlb multiplexer
port (
SEL : in slbit; -- port select (0:RLB<->P0; 1:RLB<->P1)
RLB_DI : out slv8; -- rlb: data in
RLB_ENA : out slbit; -- rlb: data enable
RLB_BUSY : in slbit; -- rlb: data busy
RLB_DO : in slv8; -- rlb: data out
RLB_VAL : in slbit; -- rlb: data valid
RLB_HOLD : out slbit; -- rlb: data hold
P0_RXDATA : in slv8; -- p0: rx data
P0_RXVAL : in slbit; -- p0: rx valid
P0_RXHOLD : out slbit; -- p0: rx hold
P0_TXDATA : out slv8; -- p0: tx data
P0_TXENA : out slbit; -- p0: tx enable
P0_TXBUSY : in slbit; -- p0: tx busy
P1_RXDATA : in slv8; -- p1: rx data
P1_RXVAL : in slbit; -- p1: rx valid
P1_RXHOLD : out slbit; -- p1: rx hold
P1_TXDATA : out slv8; -- p1: tx data
P1_TXENA : out slbit; -- p1: tx enable
P1_TXBUSY : in slbit -- p1: tx busy
);
end component;
 
--
-- core + concrete_interface combo's
--
214,7 → 240,7
DWIDTH : positive := 9); -- data port width (8 or 9)
port (
CLK : in slbit; -- clock
CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number
CLK_CYCLE : in integer := 0; -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
/rtl/vlib/rlink/rlink_rlbmux.vhd
0,0 → 1,92
-- $Id: rlink_rlbmux.vhd 466 2012-12-30 13:26:55Z mueller $
--
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_rlbmux - syn
-- Description: rlink rlb multiplexer
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
 
entity rlink_rlbmux is -- rlink rlb multiplexer
port (
SEL : in slbit; -- port select (0:RLB<->P0; 1:RLB<->P1)
RLB_DI : out slv8; -- rlb: data in
RLB_ENA : out slbit; -- rlb: data enable
RLB_BUSY : in slbit; -- rlb: data busy
RLB_DO : in slv8; -- rlb: data out
RLB_VAL : in slbit; -- rlb: data valid
RLB_HOLD : out slbit; -- rlb: data hold
P0_RXDATA : in slv8; -- p0: rx data
P0_RXVAL : in slbit; -- p0: rx valid
P0_RXHOLD : out slbit; -- p0: rx hold
P0_TXDATA : out slv8; -- p0: tx data
P0_TXENA : out slbit; -- p0: tx enable
P0_TXBUSY : in slbit; -- p0: tx busy
P1_RXDATA : in slv8; -- p1: rx data
P1_RXVAL : in slbit; -- p1: rx valid
P1_RXHOLD : out slbit; -- p1: rx hold
P1_TXDATA : out slv8; -- p1: tx data
P1_TXENA : out slbit; -- p1: tx enable
P1_TXBUSY : in slbit -- p1: tx busy
);
end rlink_rlbmux;
 
 
architecture syn of rlink_rlbmux is
 
begin
 
proc_rlmux : process (SEL, RLB_DO, RLB_VAL, RLB_BUSY,
P0_RXDATA, P0_RXVAL, P0_TXBUSY,
P1_RXDATA, P1_RXVAL, P1_TXBUSY)
begin
 
P0_TXDATA <= RLB_DO;
P1_TXDATA <= RLB_DO;
if SEL = '0' then
RLB_DI <= P0_RXDATA;
RLB_ENA <= P0_RXVAL;
P0_RXHOLD <= RLB_BUSY;
P0_TXENA <= RLB_VAL;
RLB_HOLD <= P0_TXBUSY;
P1_RXHOLD <= '0';
P1_TXENA <= '0';
else
RLB_DI <= P1_RXDATA;
RLB_ENA <= P1_RXVAL;
P1_RXHOLD <= RLB_BUSY;
P1_TXENA <= RLB_VAL;
RLB_HOLD <= P1_TXBUSY;
P0_RXHOLD <= '0';
P0_TXENA <= '0';
end if;
end process proc_rlmux;
 
end syn;
/rtl/vlib/rlink/rlink_mon_sb.vhd
1,6 → 1,6
-- $Id: rlink_mon_sb.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: rlink_mon_sb.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
16,11 → 16,14
-- Description: simbus wrapper for rlink monitor
--
-- Dependencies: simbus
-- simlib/simclkcnt
-- rlink_mon
-- Test bench: -
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 use simclkcnt instead of simbus global
-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.0 renamed rritb_cpmon_sb -> rlink_mon_sb
-- 2010-05-02 287 1.0.1 use sbcntl_sbf_cpmon def
54,12 → 57,15
architecture sim of rlink_mon_sb is
 
signal ENA : slbit := '0';
signal CLK_CYCLE : integer := 0;
 
begin
 
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
report "assert(ENAPIN in SB_CNTL'range)" severity failure;
 
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
 
ENA <= to_x01(SB_CNTL(ENAPIN));
CPMON : rlink_mon
67,7 → 73,7
DWIDTH => DWIDTH)
port map (
CLK => CLK,
CLK_CYCLE => SB_CLKCYCLE,
CLK_CYCLE => CLK_CYCLE,
ENA => ENA,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
/rtl/vlib/rlink/tb/tbcore_rlink_dcm.vbom File deleted
/rtl/vlib/rlink/tb/tbcore_rlink_dcm.vhd File deleted
/rtl/vlib/rlink/tb/tbcore_rlink.vbom
7,7 → 7,7
rlinktblib.vhd
rlink_cext_vhpi.vhd
# components
../../simlib/simclk.vbom
../../simlib/simclkcnt.vbom
# vhpi
rlink_cext.c
# design
/rtl/vlib/rlink/tb/tb_rlink.vhd
1,4 → 1,4
-- $Id: tb_rlink.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: tb_rlink.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
16,6 → 16,7
-- Description: Test bench for rlink_core
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- genlib/clkdivce
-- rbus/tbd_tester
-- rbus/rb_mon
31,6 → 32,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 use new simclk/simclkcnt
-- 2011-11-19 427 3.0.7 fix crc8_update_tbl usage; now numeric_std clean
-- 2010-12-29 351 3.0.6 use new rbd_tester addr 111100xx (from 111101xx)
-- 2010-12-26 348 3.0.5 use simbus to export clkcycle (for tbd_..serport)
106,7 → 108,6
use work.rbdlib.all;
use work.rlinklib.all;
use work.simlib.all;
use work.simbus.all;
 
entity tb_rlink is
end tb_rlink;
146,6 → 147,7
signal RB_SRES : rb_sres_type := rb_sres_init;
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
 
constant slv9_zero : slv9 := (others=>'0');
constant slv16_zero : slv16 := (others=>'0');
192,22 → 194,22
 
begin
 
SYSCLK : simclk
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_CYCLE => SB_CLKCYCLE,
CLK_STOP => CLK_STOP
);
 
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
 
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => 4,
MSECDIV => 5
)
MSECDIV => 5)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
245,7 → 247,7
DWIDTH => RL_DI'length)
port map (
CLK => CLK,
CLK_CYCLE => SB_CLKCYCLE,
CLK_CYCLE => CLK_CYCLE,
ENA => RLMON_EN,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
260,7 → 262,7
DBASE => 2)
port map (
CLK => CLK,
CLK_CYCLE => SB_CLKCYCLE,
CLK_CYCLE => CLK_CYCLE,
ENA => RBMON_EN,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
345,7 → 347,7
begin
if sv_rxind < sv_nrxlist then
for i in sv_rxind to sv_nrxlist-1 loop
writetimestamp(oline, SB_CLKCYCLE, ": moni ");
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, string'(" FAIL MISSING DATA="));
write(oline, sv_rxlist(i)(8));
write(oline, string'(" "));
575,7 → 577,7
RL_DI <= txlist(i);
RL_ENA <= '1';
 
writetimestamp(oline, SB_CLKCYCLE, ": stim");
writetimestamp(oline, CLK_CYCLE, ": stim");
write(oline, txlist(i)(8), right, 3);
write(oline, txlist(i)(7 downto 0), right, 9);
if txlist(i)(8) = '1' then
611,7 → 613,7
wait for 50*clock_period;
 
checkmiss_rx;
writetimestamp(oline, SB_CLKCYCLE, ": DONE ");
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
 
CLK_STOP <= '1';
631,7 → 633,7
wait for c2out_time;
 
if RL_VAL = '1' then
writetimestamp(oline, SB_CLKCYCLE, ": moni");
writetimestamp(oline, CLK_CYCLE, ": moni");
write(oline, RL_DO(8), right, 3);
write(oline, RL_DO(7 downto 0), right, 9);
if RL_DO(8) = '1' then
/rtl/vlib/rlink/tb/tbcore_rlink.vhd
1,4 → 1,4
-- $Id: tbcore_rlink.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: tbcore_rlink.vhd 445 2011-12-26 21:19:26Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
15,7 → 15,7
-- Module Name: tbcore_rlink - sim
-- Description: Core for a rlink_cext based test bench
--
-- Dependencies: simlib/simclk
-- Dependencies: simlib/simclkcnt
--
-- To test: generic, any rlink_cext based target
--
23,6 → 23,8
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-25 445 3.1.1 add SB_ init drivers to avoid SB_VAL='U' at start
-- 2011-12-23 444 3.1 redo clock handling, remove simclk, CLK now input
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-29 351 3.0 rename rritb_core->tbcore_rlink; use rbv3 naming
-- 2010-06-05 301 1.1.2 rename .rpmon -> .rbmon
47,13 → 49,9
use work.rlink_cext_vhpi.all;
 
entity tbcore_rlink is -- core of rlink_cext based test bench
generic (
CLK_PERIOD : time := 20 ns; -- clock period
CLK_OFFSET : time := 200 ns; -- clock offset (time to start clock)
SETUP_TIME : time := 5 ns; -- setup time
C2OUT_TIME : time := 10 ns); -- clock to output time
port (
CLK : out slbit; -- main clock
CLK : in slbit; -- control interface clock
CLK_STOP : out slbit; -- clock stop trigger
RX_DATA : out slv8; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
63,24 → 61,13
end tbcore_rlink;
 
architecture sim of tbcore_rlink is
signal CLK_CYCLE : integer := 0;
 
signal CLK_L : slbit := '0';
signal CLK_STOP : slbit := '0';
 
begin
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
 
SYSCLK : simclk
generic map (
PERIOD => CLK_PERIOD,
OFFSET => CLK_OFFSET)
port map (
CLK => CLK_L,
CLK_CYCLE => SB_CLKCYCLE,
CLK_STOP => CLK_STOP
);
 
CLK <= CLK_L;
proc_conf: process
file fconf : text open read_mode is "rlink_cext_conf";
variable iline : line;
162,12 → 149,15
end loop; -- file_loop:
 
SB_VAL <= 'L';
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
 
wait; -- halt process here
end process proc_conf;
proc_stim: process
variable icycle : integer := 0;
variable irxint : integer := 0;
variable irxslv : slv24 := (others=>'0');
variable ibit : integer := 0;
177,22 → 167,31
variable idata : slv16 := (others=>'0');
begin
 
wait for CLK_OFFSET;
wait for 10*CLK_PERIOD;
-- setup init values for all output ports
CLK_STOP <= '0';
RX_DATA <= (others=>'0');
RX_VAL <= '0';
 
SB_VAL <= 'Z';
SB_ADDR <= (others=>'Z');
SB_DATA <= (others=>'Z');
 
-- wait for 10 clock cycles (design run up)
for i in 0 to 9 loop
wait until rising_edge(CLK);
end loop; -- i
stim_loop: loop
wait until rising_edge(CLK_L);
wait for CLK_PERIOD-SETUP_TIME;
 
wait until falling_edge(CLK);
 
SB_ADDR <= (others=>'Z');
SB_DATA <= (others=>'Z');
 
icycle := to_integer(unsigned(SB_CLKCYCLE));
RX_VAL <= '0';
 
if RX_HOLD = '0' then
irxint := rlink_cext_getbyte(icycle);
irxint := rlink_cext_getbyte(CLK_CYCLE);
if irxint >= 0 then
if irxint <= 16#ff# then -- normal data byte
RX_DATA <= slv(to_unsigned(irxint, 8));
201,7 → 200,7
irxslv := slv(to_unsigned(irxint mod 16#1000000#, 24));
iaddr := irxslv(23 downto 16);
idata := irxslv(15 downto 0);
writetimestamp(oline, SB_CLKCYCLE, ": OOB-MSG");
writetimestamp(oline, CLK_CYCLE, ": OOB-MSG");
write(oline, irxslv(23 downto 16), right, 9);
write(oline, irxslv(15 downto 8), right, 9);
write(oline, irxslv( 7 downto 0), right, 9);
233,10 → 232,14
end loop;
wait for 50*CLK_PERIOD;
-- wait for 50 clock cycles (design run down)
for i in 0 to 49 loop
wait until rising_edge(CLK);
end loop; -- i
CLK_STOP <= '1';
writetimestamp(oline, SB_CLKCYCLE, ": DONE ");
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
 
wait; -- suspend proc_stim forever
251,8 → 254,7
begin
loop
wait until rising_edge(CLK_L);
wait for C2OUT_TIME;
wait until rising_edge(CLK);
if TX_ENA = '1' then
itxdata := to_integer(unsigned(TX_DATA));
itxrc := rlink_cext_putbyte(itxdata);
/rtl/vlib/rlink/tb/tbd_rlink_sp1c.vbom
7,10 → 7,11
../../simlib/simlib.vhd
../../simlib/simbus.vhd
# components
tbu_rlink_sp1c : tbu_rlink_sp1c.vbom
${tbu_rlink_sp1c := tbu_rlink_sp1c.vbom}
../../serport/serport_uart_tx.vbom
../../serport/serport_uart_rx.vbom
../../comlib/byte2cdata.vbom
../../comlib/cdata2byte.vbom
../../simlib/simclkcnt.vbom
# design
tbd_rlink_sp1c.vhd
/rtl/vlib/rlink/tb/tb_rlink.vbom
10,14 → 10,14
../../rbus/rbdlib.vhd
../rlinklib.vbom
../../simlib/simlib.vhd
../../simlib/simbus.vhd
# components
../../simlib/simclk.vbom
../../simlib/simclkcnt.vbom
../../genlib/clkdivce.vbom
../../rbus/rbd_tester.vbom
../../rbus/rb_mon.vbom
../rlink_mon.vbom
tbd_rlink_gen : tbd_rlink_direct.vbom
${tbd_rlink_gen := tbd_rlink_direct.vbom}
# design
tb_rlink.vhd
@top:tb_rlink
/rtl/vlib/rlink/tb/rlinktblib.vhd
1,6 → 1,6
-- $Id: rlinktblib.vhd 389 2011-07-07 21:59:00Z mueller $
-- $Id: rlinktblib.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
16,9 → 16,10
-- Description: rlink test environment components
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 new clock iface for tbcore_rlink; drop .._dcm
-- 2010-12-29 351 3.0.1 add rbtba_aif;
-- 2010-12-24 347 3.0 rename rritblib->rlinktblib, CP_*->RL_*;
-- many rri->rlink renames; drop rbus parts;
125,13 → 126,9
end component;
 
component tbcore_rlink is -- core of vhpi_cext based test bench
generic (
CLK_PERIOD : time := 20 ns; -- clock period
CLK_OFFSET : time := 200 ns; -- clock offset (time to start clock)
SETUP_TIME : time := 5 ns; -- setup time
C2OUT_TIME : time := 10 ns); -- clock to output time
port (
CLK : out slbit; -- main clock
CLK : in slbit; -- control interface clock
CLK_STOP : out slbit; -- clock stop trigger
RX_DATA : out slv8; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
140,23 → 137,6
);
end component;
 
component tbcore_rlink_dcm is -- dcm aware core of vhpi_cext based tb
generic (
CLKOSC_PERIOD : time := 20 ns; -- clock osc period
CLKOSC_OFFSET : time := 200 ns; -- clock osc offset (time to start clk)
SETUP_TIME : time := 5 ns; -- setup time
C2OUT_TIME : time := 10 ns); -- clock to output time
port (
CLKOSC : out slbit; -- clock osc
CLKSYS : in slbit; -- DCM derived system clock
RX_DATA : out slv8; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
TX_DATA : in slv8; -- write data (data tb->ext)
TX_ENA : in slbit -- write data enable (data tb->ext)
);
end component;
 
-- FIXME after this point !!
 
component rricp_rp is -- rri comm->reg port aif forwarder
/rtl/vlib/rlink/tb/tbd_rlink_sp1c.vhd
1,4 → 1,4
-- $Id: tbd_rlink_sp1c.vhd 442 2011-12-23 10:03:28Z mueller $
-- $Id: tbd_rlink_sp1c.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
23,6 → 23,7
-- serport_uart_rx
-- byte2cdata
-- cdata2byte
-- simlib/simclkcnt
--
-- To test: rlink_sp1c
--
31,6 → 32,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.2 use simclkcnt instead of simbus global
-- 2011-12-22 442 3.1 renamed and retargeted to tbu_rlink_sp1c
-- 2011-11-19 427 3.0.5 now numeric_std clean
-- 2010-12-28 350 3.0.4 use CLKDIV/CDINIT=0;
110,7 → 112,8
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal CLKDIV : slv13 := slv(to_unsigned(c_cdinit,CDWIDTH));
signal CLK_CYCLE : integer := 0;
 
component tbu_rlink_sp1c is -- rlink core+serport combo
port (
CLK : in slbit; -- clock
223,6 → 226,8
HOLD => TXBUSY
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
 
proc_moni: process
variable oline : line;
variable rts_last : slbit := '0';
231,7 → 236,7
loop
wait until rising_edge(CLK); -- check at end of clock cycle
if RTS_N /= rts_last then
writetimestamp(oline, SB_CLKCYCLE, ": rts ");
writetimestamp(oline, CLK_CYCLE, ": rts ");
write(oline, string'(" RTS_N "));
write(oline, rts_last, right, 1);
write(oline, string'(" -> "));
/rtl/vlib/rlink/rlink_mon.vhd
1,4 → 1,4
-- $Id: rlink_mon.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: rlink_mon.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
21,6 → 21,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 CLK_CYCLE now integer
-- 2011-11-19 427 3.0.2 now numeric_std clean
-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.0 renamed rritb_cpmon -> rlink_mon
45,7 → 46,7
DWIDTH : positive := 9); -- data port width (8 or 9)
port (
CLK : in slbit; -- clock
CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number
CLK_CYCLE : in integer := 0; -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
/rtl/vlib/rlink/rlink_rlbmux.vbom
0,0 → 1,5
# libs
../slvtypes.vhd
# components
# design
rlink_rlbmux.vhd
/rtl/vlib/rlink/rlink_mon_sb.vbom
4,6 → 4,7
../simlib/simbus.vhd
rlinklib.vbom
# components
../simlib/simclkcnt.vbom
rlink_mon.vbom
# design
rlink_mon_sb.vhd
/rtl/vlib/simlib/simlib.vhd
1,4 → 1,4
-- $Id: simlib.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: simlib.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
22,6 → 22,8
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 2.0 drop CLK_CYCLE from simclk,simclkv; use integer for
-- simclkcnt(CLK_CYCLE),writetimestamp(clkcyc);
-- 2011-11-18 427 1.3.8 now numeric_std clean
-- 2010-12-22 346 1.3.7 rename readcommand -> readdotcomm
-- 2010-11-13 338 1.3.6 add simclkcnt; xx.x ns time in writetimestamp()
197,7 → 199,7
 
procedure writetimestamp(
L: inout line;
clkcyc: in slv31;
clkcyc: in integer;
str : in string := null_string);
 
-- ----------------------------------------------------------------------------
208,7 → 210,6
OFFSET : time := 200 ns); -- clock offset (first up transition)
port (
CLK : out slbit; -- clock
CLK_CYCLE : out slv31; -- clock cycle number
CLK_STOP : in slbit -- clock stop trigger
);
end component;
217,7 → 218,6
-- with variable periods
port (
CLK : out slbit; -- clock
CLK_CYCLE : out slv31; -- clock cycle number
CLK_PERIOD : in time; -- clock period
CLK_HOLD : in slbit; -- if 1, hold clocks in 0 state
CLK_STOP : in slbit -- clock stop trigger
227,7 → 227,7
component simclkcnt is -- test bench system clock cycle counter
port (
CLK : in slbit; -- clock
CLK_CYCLE : out slv31 -- clock cycle number
CLK_CYCLE : out integer -- clock cycle number
);
end component;
 
1062,7 → 1062,7
 
procedure writetimestamp(
L: inout line;
clkcyc: in slv31;
clkcyc: in integer;
str: in string := null_string) is
 
variable t_nsec : integer := 0;
1081,7 → 1081,7
write(L, t_dnsec, right, 1);
write(L, string'(" ns"));
write(L, to_integer(unsigned(clkcyc)), right, 7);
write(L, clkcyc, right, 7);
if str /= null_string then
write(L, str);
end if;
/rtl/vlib/simlib/simbus.vhd
1,6 → 1,6
-- $Id: simbus.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: simbus.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
16,9 → 16,10
-- Description: Global signals for support control in test benches
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.25
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 2.0 remove global clock cycle signal
-- 2010-04-24 282 1.1 add SB_(VAL|ADDR|DATA)
-- 2008-03-24 129 1.0.1 use 31 bits for SB_CLKCYCLE
-- 2007-08-27 76 1.0 Initial version
32,7 → 33,6
package simbus is
signal SB_CLKSTOP : slbit := '0'; -- global clock stop
signal SB_CLKCYCLE : slv31 := (others=>'0'); -- global clock cycle
signal SB_CNTL : slv16 := (others=>'0'); -- global signals tb -> uut
signal SB_STAT : slv16 := (others=>'0'); -- global signals uut -> tb
signal SB_VAL : slbit := '0'; -- init bcast valid
/rtl/vlib/simlib/simclk.vhd
1,4 → 1,4
-- $Id: simclk.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: simclk.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
18,10 → 18,11
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 2.0 remove CLK_CYCLE output port
-- 2011-11-18 427 1.0.3 now numeric_std clean
-- 2008-03-24 129 1.0.2 CLK_CYCLE now 31 bits
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
30,7 → 31,6
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
 
entity simclk is -- test bench clock generator
39,7 → 39,6
OFFSET : time := 200 ns); -- clock offset (first up transition)
port (
CLK : out slbit; -- clock
CLK_CYCLE : out slv31; -- clock cycle number
CLK_STOP : in slbit -- clock stop trigger
);
end entity simclk;
49,22 → 48,16
 
proc_clk: process
constant clock_halfperiod : time := PERIOD/2;
variable icycle : slv31 := (others=>'0');
begin
 
CLK <= '0';
CLK_CYCLE <= (others=>'0');
wait for OFFSET;
 
clk_loop: loop
CLK <= '1';
wait for 0 ns; -- make a delta cycle so that clock
icycle := slv(unsigned(icycle) + 1); -- cycle number is updated after the
CLK_CYCLE <= icycle; -- clock transition. all edge triggered
-- proc's will thus read old value.
wait for clock_halfperiod;
CLK <= '0';
wait for clock_halfperiod;
wait for PERIOD-clock_halfperiod;
exit clk_loop when CLK_STOP = '1';
end loop;
71,7 → 64,7
CLK <= '1'; -- final clock cycle for clk_sim
wait for clock_halfperiod;
CLK <= '0';
wait for clock_halfperiod;
wait for PERIOD-clock_halfperiod;
wait; -- endless wait, simulator will stop
/rtl/vlib/simlib/simclkcnt.vhd
1,4 → 1,4
-- $Id: simclkcnt.vhd 423 2011-11-12 22:22:25Z mueller $
-- $Id: simclkcnt.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
22,6 → 22,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 2.0 CLK_CYCLE now an integer
-- 2011-11-12 423 1.0.1 now numeric_std clean
-- 2010-11-13 72 1.0 Initial version
------------------------------------------------------------------------------
28,18 → 29,17
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
 
entity simclkcnt is -- test bench system clock cycle counter
port (
CLK : in slbit; -- clock
CLK_CYCLE : out slv31 -- clock cycle number
CLK_CYCLE : out integer -- clock cycle number
);
end entity simclkcnt;
 
architecture sim of simclkcnt is
signal R_CLKCNT : slv31 := (others=>'0');
signal R_CLKCNT : integer := 0;
begin
 
proc_clk: process (CLK)
46,7 → 46,7
begin
 
if rising_edge(CLK) then
R_CLKCNT <= slv(unsigned(R_CLKCNT) + 1);
R_CLKCNT <= R_CLKCNT + 1;
end if;
end process proc_clk;
/rtl/vlib/genlib/genlib.vhd
1,6 → 1,6
-- $Id: genlib.vhd 422 2011-11-10 18:44:06Z mueller $
-- $Id: genlib.vhd 466 2012-12-30 13:26:55Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
16,9 → 16,10
-- Description: some general purpose components
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 13.3; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 1.0.9 add led_pulse_stretch
-- 2011-11-09 421 1.0.8 add cdc_pulse
-- 2010-04-17 277 1.0.7 timer: no default for START,DONE,BUSY; drop STOP
-- 2010-04-02 273 1.0.6 add timer
168,4 → 169,14
);
end component;
 
component led_pulse_stretch is -- pulse stretcher for leds
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- pulse time unit clock enable
RESET : in slbit := '0'; -- reset
DIN : in slbit; -- data in
POUT : out slbit -- pulse out
);
end component;
 
end package genlib;
/rtl/vlib/genlib/led_pulse_stretch.vhd
0,0 → 1,97
-- $Id: led_pulse_stretch.vhd 466 2012-12-30 13:26:55Z mueller $
--
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: led_pulse_stretch - syn
-- Description: pulse stretcher for leds
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
 
entity led_pulse_stretch is -- pulse stretcher for leds
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- pulse time unit clock enable
RESET : in slbit := '0'; -- reset
DIN : in slbit; -- data in
POUT : out slbit -- pulse out
);
end entity led_pulse_stretch;
 
architecture syn of led_pulse_stretch is
 
type regs_type is record -- state registers
seen : slbit; -- DIN seen
busy : slbit; -- POUT busy
end record regs_type;
 
constant regs_init : regs_type := (
'0', -- seen
'0' -- busy
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
 
begin
proc_regs: process (CLK)
begin
 
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
 
end process proc_regs;
 
proc_next: process (R_REGS, CE_INT, DIN)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
 
begin
 
r := R_REGS;
n := R_REGS;
 
if CE_INT='1' then
n.seen := DIN;
n.busy := r.seen;
else
if DIN='1' then
n.seen := '1';
end if;
end if;
N_REGS <= n;
 
POUT <= r.busy;
end process proc_next;
end syn;
/rtl/vlib/genlib/led_pulse_stretch.vbom
0,0 → 1,5
# libs
../slvtypes.vhd
# components
# design
led_pulse_stretch.vhd
/rtl/vlib/comlib/word2byte.vhd
0,0 → 1,151
-- $Id: word2byte.vhd 432 2011-11-25 20:16:28Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: word2byte - syn
-- Description: 1 word -> 2 byte stream converter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-21 432 1.0.1 now numeric_std clean
-- 2011-07-30 400 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
 
entity word2byte is -- 1 word -> 2 byte stream converter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv16; -- input data (word)
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv8; -- output data (byte)
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
ODD : out slbit -- odd byte pending
);
end word2byte;
 
 
architecture syn of word2byte is
 
type state_type is (
s_idle,
s_valw,
s_valh
);
 
type regs_type is record
datl : slv8; -- lsb data
dath : slv8; -- msb data
state : state_type; -- state
end record regs_type;
 
constant regs_init : regs_type := (
(others=>'0'),
(others=>'0'),
s_idle
);
 
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
 
begin
 
proc_regs: process (CLK)
begin
 
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
 
end process proc_regs;
 
proc_next: process (R_REGS, DI, ENA, HOLD)
 
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
 
variable ival : slbit := '0';
variable ibusy : slbit := '0';
variable iodd : slbit := '0';
begin
 
r := R_REGS;
n := R_REGS;
 
ival := '0';
ibusy := '0';
iodd := '0';
case r.state is
when s_idle =>
if ENA = '1' then
n.datl := DI( 7 downto 0);
n.dath := DI(15 downto 8);
n.state := s_valw;
end if;
 
when s_valw =>
ibusy := '1';
ival := '1';
if HOLD = '0' then
n.datl := r.dath;
n.state := s_valh;
end if;
 
when s_valh =>
ival := '1';
iodd := '1';
if HOLD = '0' then
if ENA = '1' then
n.datl := DI( 7 downto 0);
n.dath := DI(15 downto 8);
n.state := s_valw;
else
n.state := s_idle;
end if;
else
ibusy := '1';
end if;
 
when others => null;
end case;
 
N_REGS <= n;
 
DO <= r.datl;
VAL <= ival;
BUSY <= ibusy;
ODD <= iodd;
end process proc_next;
 
 
end syn;
/rtl/vlib/comlib/byte2word.vhd
0,0 → 1,147
-- $Id: byte2word.vhd 432 2011-11-25 20:16:28Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: byte2word - syn
-- Description: 2 byte -> 1 word stream converter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-21 432 1.0.1 now numeric_std clean
-- 2011-07-30 400 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
 
entity byte2word is -- 2 byte -> 1 word stream converter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv8; -- input data (byte)
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv16; -- output data (word)
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
ODD : out slbit -- odd byte pending
);
end byte2word;
 
 
architecture syn of byte2word is
 
type state_type is (
s_idle,
s_vall,
s_valw
);
 
type regs_type is record
datl : slv8; -- lsb data
dath : slv8; -- msb data
state : state_type; -- state
end record regs_type;
 
constant regs_init : regs_type := (
(others=>'0'),
(others=>'0'),
s_idle
);
 
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
 
begin
 
proc_regs: process (CLK)
begin
 
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
 
end process proc_regs;
 
proc_next: process (R_REGS, DI, ENA, HOLD)
 
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
 
variable ival : slbit := '0';
variable ibusy : slbit := '0';
variable iodd : slbit := '0';
begin
 
r := R_REGS;
n := R_REGS;
 
ival := '0';
ibusy := '0';
iodd := '0';
case r.state is
when s_idle =>
if ENA = '1' then
n.datl := DI;
n.state := s_vall;
end if;
 
when s_vall =>
iodd := '1';
if ENA = '1' then
n.dath := DI;
n.state := s_valw;
end if;
 
when s_valw =>
ival := '1';
if HOLD = '0' then
if ENA = '1' then
n.datl := DI;
n.state := s_vall;
else
n.state := s_idle;
end if;
else
ibusy := '1';
end if;
 
when others => null;
end case;
 
N_REGS <= n;
 
DO <= r.dath & r.datl;
VAL <= ival;
BUSY <= ibusy;
ODD <= iodd;
end process proc_next;
 
 
end syn;
/rtl/vlib/comlib/word2byte.vbom
0,0 → 1,4
# libs
../slvtypes.vhd
# design
word2byte.vhd
/rtl/vlib/comlib/byte2word.vbom
0,0 → 1,4
# libs
../slvtypes.vhd
# design
byte2word.vhd
/rtl/vlib/rbus/rb_mon_sb.vhd
1,6 → 1,6
-- $Id: rb_mon_sb.vhd 346 2010-12-22 22:59:26Z mueller $
-- $Id: rb_mon_sb.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
16,11 → 16,14
-- Description: simbus wrapper for rbus monitor (for tb's)
--
-- Dependencies: simbus
-- simlib/simclkcnt
-- rb_mon
-- Test bench: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 use simclkcnt instead of simbus global
-- 2010-12-22 346 3.0 renamed rritb_rbmon_sb -> rb_mon_sb
-- 2010-06-05 301 2.0.2 renamed _rpmon -> _rbmon
-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
57,6 → 60,7
architecture sim of rb_mon_sb is
 
signal ENA : slbit := '0';
signal CLK_CYCLE : integer := 0;
begin
 
63,6 → 67,8
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
report "assert(ENAPIN in SB_CNTL'range)" severity failure;
 
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
 
ENA <= to_x01(SB_CNTL(ENAPIN));
RBMON : rb_mon
70,7 → 76,7
DBASE => DBASE)
port map (
CLK => CLK,
CLK_CYCLE => SB_CLKCYCLE,
CLK_CYCLE => CLK_CYCLE,
ENA => ENA,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
/rtl/vlib/rbus/rb_mon.vhd
1,4 → 1,4
-- $Id: rb_mon.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: rb_mon.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
21,6 → 21,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 CLK_CYCLE now integer
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-22 346 3.0 renamed rritb_rbmon -> rb_mon
-- 2010-06-05 301 2.1.1 renamed _rpmon -> _rbmon
49,7 → 50,7
DBASE : positive := 2); -- base for writing data values
port (
CLK : in slbit; -- clock
CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number
CLK_CYCLE : in integer := 0; -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
/rtl/vlib/rbus/rb_mon_sb.vbom
4,6 → 4,7
../simlib/simbus.vhd
rblib.vhd
# components
../simlib/simclkcnt.vbom
rb_mon.vbom
# design
rb_mon_sb.vhd
/rtl/vlib/rbus/rblib.vhd
1,4 → 1,4
-- $Id: rblib.vhd 405 2011-08-14 08:16:28Z mueller $
-- $Id: rblib.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
16,10 → 16,11
-- Description: Definitions for rbus interface and bus entities
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 CLK_CYCLE now integer
-- 2011-08-13 405 3.0.3 add in direction for FADDR,SEL ports
-- 2010-12-26 349 3.0.2 add rb_sel
-- 2010-12-22 346 3.0.1 add rb_mon and rb_mon_sb;
168,7 → 169,7
DBASE : positive := 2); -- base for writing data values
port (
CLK : in slbit; -- clock
CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number
CLK_CYCLE : in integer := 0; -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
/rtl/vlib/serport/tb/tb_serport_uart_rxtx.vhd
1,4 → 1,4
-- $Id: tb_serport_uart_rxtx.vhd 417 2011-10-22 10:30:29Z mueller $
-- $Id: tb_serport_uart_rxtx.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
33,6 → 33,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.2 use new simclk/simclkcnt
-- 2011-10-22 417 1.1.3 now numeric_std clean
-- 2010-04-24 281 1.1.2 use direct instatiation for tbd_
-- 2008-03-24 129 1.1.1 CLK_CYCLE now 31 bits
69,7 → 70,7
signal TXBUSY : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : slv31 := (others=>'0');
signal CLK_CYCLE : integer := 0;
signal N_MON_VAL : slbit := '0';
signal N_MON_DAT : slv8 := (others=>'0');
85,16 → 86,17
 
begin
 
SYSCLK : simclk
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
CLK_STOP => CLK_STOP
);
 
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
 
UUT : entity work.tbd_serport_uart_rxtx
port map (
CLK => CLK,
/rtl/vlib/serport/tb/tb_serport_autobaud.vhd
1,4 → 1,4
-- $Id: tb_serport_autobaud.vhd 417 2011-10-22 10:30:29Z mueller $
-- $Id: tb_serport_autobaud.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
16,6 → 16,7
-- Description: Test bench for serport_autobaud
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- tbd_serport_autobaud [UUT]
--
-- To test: serport_autobaud
33,6 → 34,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.2 use new simclk/simclkcnt
-- 2011-10-22 417 1.1.3 now numeric_std clean
-- 2010-04-24 281 1.1.2 use direct instatiation for tbd_
-- 2008-03-24 129 1.1.1 CLK_CYCLE now 31 bits
77,7 → 79,7
signal RXACT3 : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : slv31 := (others=>'0');
signal CLK_CYCLE : integer := 0;
signal N_MON_VAL : slbit := '0';
signal N_MON_DAT : slv8 := (others=>'0');
93,16 → 95,17
 
begin
 
SYSCLK : simclk
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
CLK_STOP => CLK_STOP
);
 
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
 
UUT : entity work.tbd_serport_autobaud
port map (
CLK => CLK,
/rtl/vlib/serport/tb/tb_serport_uart_rx.vbom
4,6 → 4,7
../serport.vhd
# components
../../simlib/simclk.vbom
tbd_serport_uart_rx : tbd_serport_uart_rx.vbom
../../simlib/simclkcnt.vbom
${tbd_serport_uart_rx := tbd_serport_uart_rx.vbom}
# design
tb_serport_uart_rx.vhd
/rtl/vlib/serport/tb/tb_serport_uart_rxtx.vbom
4,6 → 4,7
../serport.vhd
# components
../../simlib/simclk.vbom
tbd_serport_uart_rxtx : tbd_serport_uart_rxtx.vbom
../../simlib/simclkcnt.vbom
${tbd_serport_uart_rxtx := tbd_serport_uart_rxtx.vbom}
# design
tb_serport_uart_rxtx.vhd
/rtl/vlib/serport/tb/tb_serport_uart_rx.vhd
1,4 → 1,4
-- $Id: tb_serport_uart_rx.vhd 417 2011-10-22 10:30:29Z mueller $
-- $Id: tb_serport_uart_rx.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
16,6 → 16,7
-- Description: Test bench for serport_uart_rx
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- tbd_serport_uart_rx [UUT]
--
-- To test: serport_uart_rx
30,6 → 31,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk/simclkcnt
-- 2011-10-22 417 1.0.3 now numeric_std clean
-- 2010-04-24 281 1.0.2 use direct instatiation for tbd_
-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits
61,7 → 63,7
signal RXACT : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : slv31 := (others=>'0');
signal CLK_CYCLE : integer := 0;
 
signal N_MON_VAL : slbit := '0';
signal N_MON_ERR : slbit := '0';
80,15 → 82,16
 
begin
 
SYSCLK : simclk
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
 
UUT : entity work.tbd_serport_uart_rx
port map (
/rtl/vlib/serport/tb/tb_serport_autobaud.vbom
4,6 → 4,7
../serport.vhd
# components
../../simlib/simclk.vbom
tbd_serport_autobaud : tbd_serport_autobaud.vbom
../../simlib/simclkcnt.vbom
${tbd_serport_autobaud := tbd_serport_autobaud.vbom}
# design
tb_serport_autobaud.vhd
/rtl/vlib/serport/tb/Makefile
1,4 → 1,4
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
# $Id: Makefile 444 2011-12-25 10:04:58Z mueller $
#
# Revision History:
# Date Rev Version Comment
7,7 → 7,9
# 2007-11-26 98 1.1 use make includes
# 2007-06-03 48 1.0 Initial version
#
EXE_all = tb_serport_uart_rx tb_serport_uart_rxtx tb_serport_autobaud
EXE_all = tb_serport_uart_rx
EXE_all += tb_serport_uart_rxtx
EXE_all += tb_serport_autobaud
#
.PHONY : all all_ssim all_tsim clean
#
/rtl/make/generic_xflow.mk
1,7 → 1,11
# $Id: generic_xflow.mk 406 2011-08-14 21:06:44Z mueller $
# $Id: generic_xflow.mk 456 2012-02-05 22:19:44Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-02-05 456 1.7.5 use vbomvonv --get_top for xflow calls
# 2012-01-08 451 1.7.4 use xilinx_ghdl_sdf_filter
# 2012-01-04 450 1.7.3 display isemsg_filter for ncd and bit targets too
# 2011-12-29 446 1.7.2 add fx2load_wrapper in jconfig target
# 2011-08-14 406 1.7.1 use isemsg_filter; new %.mfsum target
# 2011-08-13 405 1.7 renamed, moved to rtl/make;
# 2011-07-17 394 1.6.2 add rm *.svf to ise_clean rule
78,7 → 82,8
if [ -r ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ]; then \
cp ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ./ise; fi
if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} $*.prj
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} \
-g top_entity:`vbomconv --get_top $<` $*.prj
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.ngc ]; then cp -p ./ise/$*.ngc .; fi
if [ -r ./ise/$*_xst.log ]; then cp -p ./ise/$*_xst.log .; fi
99,7 → 104,8
if [ -r ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ]; then \
cp ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ./ise; fi
if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} $*.prj
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} \
-g top_entity:`vbomconv --get_top $<` $*.prj
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.ngc ]; then cp -p ./ise/$*.ngc .; fi
if [ -r ./ise/$*_xst.log ]; then cp -p ./ise/$*_xst.log .; fi
137,6 → 143,21
if [ -r ./ise/$*.par ]; then cp -p ./ise/$*.par ./$*_par.log; fi
if [ -r ./ise/$*_pad.txt ]; then cp -p ./ise/$*_pad.txt ./$*_pad.log; fi
if [ -r ./ise/$*.twr ]; then cp -p ./ise/$*.twr ./$*_twr.log; fi
@ if [ -r $*.mfset ]; then \
echo "=============================================================";\
echo "* Translate Diagnostic Summary *";\
echo "=============================================================";\
isemsg_filter tra $*.mfset $*_tra.log;\
echo "=============================================================";\
echo "* MAP Diagnostic Summary *";\
echo "=============================================================";\
isemsg_filter map $*.mfset $*_map.log;\
echo "=============================================================";\
echo "* PAR Diagnostic Summary *";\
echo "=============================================================";\
isemsg_filter par $*.mfset $*_par.log;\
echo "=============================================================";\
fi
#
# Implement 2 (bitgen)
# input: %.ncd
152,6 → 173,13
if [ -r ./ise/$*.bit ]; then cp -p ./ise/$*.bit .; fi
if [ -r ./ise/$*.msk ]; then cp -p ./ise/$*.msk .; fi
if [ -r ./ise/$*.bgn ]; then cp -p ./ise/$*.bgn ./$*_bgn.log; fi
@ if [ -r $*.mfset ]; then \
echo "=============================================================";\
echo "* Bitgen Diagnostic Summary *";\
echo "=============================================================";\
isemsg_filter bgn $*.mfset $*_bgn.log;\
echo "=============================================================";\
fi
#
# Create svf from bitstream
# input: %.bit
173,7 → 201,12
# input: %.svf
# output: .PHONY
#
ifneq "$(origin FX2_FILE)" "undefined"
FX2LOAD_OPT = --file=${FX2_FILE}
endif
#
%.jconfig: %.svf
fx2load_wrapper --board=${ISE_BOARD} ${FX2LOAD_OPT}
config_wrapper --board=${ISE_BOARD} --path=${ISE_PATH} jconfig $*.svf
 
#
225,9 → 258,12
if [ -r ./ise/$*.nlf ]; then cp -p ./ise/$*.nlf ./$*_ngn_fsim.log; fi
#
# Post-par timing simulation model (netgen -sim)
# input: %.ncd
# input: %.ncd
# %.tsim_xon_dat xon disable descriptor file (optional)
# output: %_tsim.vhd
# %_ngn_tsim.log netgen log file (renamed time_sim.nlf)
# %_ngn_tsim.log netgen log file (renamed time_sim.nlf)
# %_tsim.sdf delay annotation
# %_tsim.sdf_ghdl delay annotation with ghdl patches
#
#!! use netgen directly because xflow 8.1 goes mad when -tsim used a 2nd time
#!! see blog_xilinx_webpack.txt 2007-06-10
243,6 → 279,7
if [ -r ./ise/$*_tsim.sdf ]; then cp -p ./ise/$*_tsim.sdf .; fi
if [ -r ./ise/$*_tsim.nlf ]; then cp -p ./ise/$*_tsim.nlf ./$*_ngn_tsim.log; fi
if [ -r $*_tsim.vhd -a -r $*.tsim_xon_dat ]; then xilinx_tsim_xon $*; fi
if [ -r $*_tsim.sdf ]; then xilinx_ghdl_sdf_filter $*_tsim.sdf > $*_tsim.sdf_ghdl ; fi
#
# generate dep_xst files from vbom
#
271,6 → 308,7
rm -rf *.svf
rm -rf *_[sft]sim.vhd
rm -rf *_tsim.sdf
rm -rf *_tsim.sdf_ghdl
rm -rf *_xst.log
rm -rf *_tra.log
rm -rf *_map.log
/rtl/make/syn_s6_speed.opt
1,9 → 1,10
FLOWTYPE = FPGA_SYNTHESIS;
#
# $Id: syn_s6_speed.opt 405 2011-08-14 08:16:28Z mueller $
# $Id: syn_s6_speed.opt 456 2012-02-05 22:19:44Z mueller $
#
# Revision History:
# Date Rev Version Comment
# Date Rev Version Comment
# 2012-02-05 456 1.1 use $top_entity variable for -top attribute
# 2011-08-13 405 1.0 Initial version
#
# Derived from ISE xst_mixed.opt
27,7 → 28,7
"-ifmt mixed"; # Input Format (Verilog and VHDL)
"-ofn <design>"; # Output File Name
"-ofmt ngc"; # Output File Format
"-top <design>"; # Top Design Name
"-top $top_entity"; # Top Design Name
"-p <partname>"; # Target Device
"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED
"-opt_level 2"; # Optimization Effort Criteria: 2=High
/rtl/make/imp_s6_speed.opt
1,10 → 1,11
FLOWTYPE = FPGA;
#
# $Id: imp_s6_speed.opt 405 2011-08-14 08:16:28Z mueller $
# $Id: imp_s6_speed.opt 449 2012-01-04 08:14:11Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.0 Initial version
# 2012-01-03 449 1.1 use '-mt 2' in map and par
# 2011-08-13 405 1.0 Initial version
#
# Derived from ISE balanced.opt
# Uses uses settings like 'mapgloboptlogoptregdup' SmartExplorer strategy
39,6 → 40,7
-logic_opt on; # Perform physical synthesis combinatorial logic opt.
-register_duplication on;# Duplicate registers/luts during timing-driven packing
-w; # Always overwrite any existing output files
-mt 2; # Multi-threading
<inputdir><design>.ngd; # Input NGD file
<inputdir><design>.pcf; # Physical constraints file
END Program map
69,6 → 71,7
-ol high; # Overall effort level
-xe n; # extra effort level
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-mt 2; # Multi-threading
<design>_map.ncd; # Input mapped NCD file
<inputdir><design>.ncd; # Output placed and routed NCD
<inputdir><design>.pcf; # Input physical constraints file
/doc/INSTALL_urjtag.txt
0,0 → 1,51
# $Id: INSTALL_urjtag.txt 467 2013-01-02 19:49:05Z mueller $
 
The w11 project uses the open source JTAG Access software from the
SourceForge project
 
urjtag
 
for configuring FPGA over the Cypress FX2 USB Interface available on Digilent
Nexys2, Nexys3 and Atlys boards.
 
The most recent version works fine. This version is delivered with
Ubuntu 12.04 LTS and later Ubuntu versions. In this case simply install the
package 'urjtag'. Try the command
 
jtag
 
it should print
 
UrJTAG 0.10 #2007
 
and show a version number of '#2007' or higher.
 
Old versions unfortunately have a string size limitation problem with can
lead to problems when used with Digilent S3BOARDS (or other cases with
multiple devices in the jtag chain). Therefore for
 
Debian Squeeze and older
Ubuntu 11.10 (oneiric) and older
 
or if the 'jtag' command prints something like
 
UrJTAG 0.10 #1502
UrJTAG 0.9 #1476
 
it is advisible to install the urjtag software from sources.
 
Simlest is to install an up-to-date version directly from the SourceForge
svn repository, start at
http://sourceforge.net/scm/?type=svn&group_id=193266&source=navbar
do a 'svn co' for revision 2007 or later, build and install.
 
Alternatively start with the V0.10 (rev #1502) tarball available from
http://sourceforge.net/projects/urjtag/files/?source=navbar
and download
urjtag-0.10.tar.gz (dated 2009-04-17)
 
Change in file src/cmd/parse.c the line
 
#define MAXINPUTLINE 100 /* Maximum input line length */
 
and replace '100' with '512', build and install.
/doc/INSTALL_ghdl.txt
0,0 → 1,27
# $Id: INSTALL_ghdl.txt 467 2013-01-02 19:49:05Z mueller $
 
The w11 project uses the open source VHDL simulator
 
ghdl
 
It used to be part of most distributions. Unfortunately the Debian maintainer
for ghdl refused at some point to integrate ghdl into Debian Etch. Therefore
ghdl is part of Debian Lenny, and again of Debian Squeeze (the current
'stable'). So for an up-to-date Debian simply install the ghdl package.
 
The glitch at Debian unfortunately lead to the removal of ghdl from Ubuntu,
which is based on Debian. Ubuntu Lucid (10.04) and up to Oneiric (11.10)
included ghdl, the currently maintained versions Precise (12.04 LTS) and
Quantal (12.10) don't.
 
Thanks to Peter Gavin Ubuntu packages for GHDL are available from his PPA
'Personal Package Archives', see
 
https://launchpad.net/~pgavin/+archive/ghdl
 
So to install ghdl under Ubuntu use
 
sudo add-apt-repository ppa:pgavin/ghdl
sudo apt-get update
sudo apt-get install ghdl
 
/doc/INSTALL.txt
1,4 → 1,4
# $Id: INSTALL.txt 433 2011-11-27 22:04:39Z mueller $
# $Id: INSTALL.txt 467 2013-01-02 19:49:05Z mueller $
 
Guide to install and build w11a systems, test benches and support software
 
5,20 → 5,24
Table of content:
1. Download
2. Setup environment variables
3. Compile UNISIM/SIMPRIM libraries for ghdl
4. Compile and install the support software
2. System requirements
3. Setup system environment
a. Setup environment variables
b. Setup USB access
4. Compile UNISIM/SIMPRIM libraries for ghdl
5. Compile and install the support software
a. Compile sharable libraries
b. Setup Tcl packages
5. The build system
6. Building test benches
c. Rebuild Cypress FX2 firmware
6. The build system
7. Building test benches
a. General instructions
b. Available test benches
7. Building systems
8. Building systems
a. General instructions
b. Available systems
b. Configuring FPGAs
c. Available systems
 
 
1. Download ---------------------------------------------------------------
 
All instructions below assume that the project files reside in a
34,8 → 38,51
cd <wdir>
svn co http://opencores.org/ocsvn/w11/w11/trunk
 
2. Setup environment variables --------------------------------------------
2. System requirements ----------------------------------------------------
This project contains not only VHDL code but also support software. Therefore
quite a few software packages are expected to be installed. The following
list gives the Ubuntu/Debian package names, but mapping this to other
distributions should be straight forward.
 
- building the bit files for the FPGAs requires a Xilinx WebPACK installation
 
- building and using the RLink backend software requires:
- full C/C++ development chain (gcc,g++,cpp,make)
-> package: build-essential
- Boost C++ library (>= 1.40), with date-time, thread, and regex
-> package: libboost-dev libboost-date-time-dev libboost-thread-dev
libboost-regex-dev
- libusb 1.0 (>= 1.0.6)
-> package: libusb-1.0-0-dev
- Perl (>= 5.10) (usually included in base installations)
- Tcl (>= 8.4), with tclreadline support
-> package: tcl tcl-dev tcllib tclreadline
 
- the download contains pre-build firmware images for the Cypress FX2
USB Interface. Re-building them requires
- Small Device C Compiler
-> package: sdcc sdcc-ucsim
 
- for FX2 firmware download and jtag programming over USB one needs
- fxload
-> package: fxload
- urjtag
-> package: urjtag for Ubuntu 12.04
-> see INSTALL_urjtag.txt for other distributions !!
 
- for VHDL simulations one needs
- ghdl
-> see INSTALL_ghdl.txt for the unfortunately gory details
 
- optional but very useful is:
- gtkwave
-> package: gtkwave
 
3. Setup system environment -----------------------------------------------
 
3a. Setup environment variables --------------------------------------
 
The make flow for building test benches (ghdl and ISim based) and systems
(Xilinx xst based) as well as the support software (mainly the rlink backend
server) requires
43,6 → 90,8
- the definition of the environment variables:
- RETROBASE: must refer to the installation root directory
- BOOSTINC: pathname for includes of boost library
- TCLINC: pathname for includes of Tcl runtime library
- RETRO_FX2_VID and RETRO_FX2_PID: default USB VID/PID, see below
- that the tools binary directory is in the path
- that the tools library directory is in the library path
54,15 → 103,43
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RETROBASE/tools/lib
 
In most cases the boost library version coming with the distribution will
work, in those cases simply use
work, similar for Tcl, in those cases simply use
 
export BOOSTINC=/usr/include
export TCLINC=/usr/include/tcl8.5
 
After that building functional model based test benches will work. If you
want to also build post-xst or post-par test benches read next section.
 
3. Compile UNISIM/SIMPRIM libraries for ghdl ------------------------------
If the Cypress USB controller available on Digilent Nexys2, Nexys3 and
Atlys boards is used the default USB VID and PID is defined by two
environment variables. For internal lab use one can use
 
export RETRO_FX2_VID=16c0
export RETRO_FX2_PID=03ef
 
!! Carefully read the disclaimer about usage of USB VID/PID numbers !!
!! in the file README_USB-VID-PID.txt. You'll be responsible for any !!
!! misuse of the defaults provided with the project sources. !!
!! Usage of this VID/PID in any commercial product is forbidden. !!
 
3b. Setup USB access -------------------------------------------------
 
For using the Cypress FX2 USB interface on Digilent Nexys2, Nexys3 and
Atlys boards 'udev' rules must be setup to allow user level access to
these devices. A set of rules is provided under
 
$RETROBASE/tools/fx2/sys
 
Follow the 'README.txt' file in this directory.
 
Notes:
- the provided udev rules use the VID/PID for 'internal lab use' as
described above. If other VID/PID used the file must be modified.
- your user account must be in group 'plugdev' (should be the default).
 
4. Compile UNISIM/SIMPRIM libraries for ghdl ------------------------------
 
The build system for test benches also supports test benches run against
the gate level models derived after the xst, map or par step. In this
case ghdl has to link against a compiled UNISIM or SIMPRIM library.
83,17 → 160,18
 
If you have several WebPack versions installed, repeat for each version.
 
4. Compile and install the support software -------------------------------
5. Compile and install the support software -------------------------------
 
4a. Compile sharable libraries ---------------------------------------
5a. Compile sharable libraries ---------------------------------------
 
Required tools and libraries:
g++ >= 4.3 (decltype support assumed in usage of boost::bind)
boost >= 1.35 (boost::thread api changed, new one is used)
linusb >= 1.0.5 (timerfd support)
 
Build was tested under:
ubuntu lucid (10.04 LTS): gcc 4.4.3 boost 1.40.0
debian lenny (5.0.8): gcc 4.3.2 boost 1.xx.x (t.b.c.)
ubuntu lucid (12.04 LTS): gcc 4.6.3 boost 1.46.1 libusb 1.0.9
debian squezze (6.0.6): gcc 4.4.5 boost 1.46.1 libusb 1.0.8
 
To build all sharable libraries
 
106,7 → 184,7
rm_dep
make realclean
 
4b. Setup Tcl environment --------------------------------------------
5b. Setup Tcl environment --------------------------------------------
 
The Tcl files are organized in several packages. To create the Tcl
package files (pkgIndex.tcl)
131,9 → 209,26
ln -s $RETROBASE/tools/tcl/.tclshrc .
ln -s $RETROBASE/tools/tcl/.wishrc .
 
5c. Rebuild Cypress FX2 firmware -------------------------------------
 
5. The build system -------------------------------------------------------
The download includes pre-build firmware images for the Cypress FX2
USB interface used on the Digilent Nexys2, Nexys3 and Atlys Boards.
These firmware images are under
 
$RETROBASE/tools/fx2/bin
 
To re-build them, e.g. because a different USB VID/PID is to be used
 
cd $RETROBASE/tools/fx2/src
make clean
make
make install
Please read README_USB_VID-PID.txt carefully to understand the usage
of USB VID and PID.
 
6. The build system -------------------------------------------------------
 
Simulation and synthesis tools usually need a list of the VHDL source
files, often in proper compilation order (libraries before components).
The different tools have different formats of these 'project files'.
160,9 → 255,9
even more. Using the vbom's a large number of designs can be easily
maintained.
 
6. Building test benches --------------------------------------------------
7. Building test benches --------------------------------------------------
 
6a. General instructions ---------------------------------------------
7a. General instructions ---------------------------------------------
 
To compile a test bench named <tbench> all is needed is
 
182,13 → 277,13
The 'make ghdl_tmp_clean' is needed to flush the ghdl work area from
the compilation remains of earlier functional model compiles.
 
6b. Available test benches -------------------------------------------
7b. Available test benches -------------------------------------------
 
See file w11a_tb_guide.txt
 
7. Building systems -------------------------------------------------------
8. Building systems -------------------------------------------------------
 
7a. General instructions ---------------------------------------------
8a. General instructions ---------------------------------------------
 
To generate a bit file for a system named <sys> all is needed is
 
214,8 → 309,38
make <sys>.ngc
make <sys>.ncd
 
7b. Available systems ------------------------------------------------
A simple 'message filter' system is also integrated into the make build flow.
For many (though not all) systems a .mfset file has been provided which
defines the xst,par and bitgen messages which are considered ok. To see
only the remaining message extracted from the vaious .log files simply
use the make target
 
make <sys>.mfsum
 
after a re-build.
 
8b. Configuring FPGAs ------------------------------------------------
 
The make flow supports also loading the bitstream into FPGAs, either
via Xilinx Impact, or via the Cypress FX2 USB controller is available.
 
For Xilinx Impact a Xilinx USB Cable II has to be properly setup, than
simply use
 
make <sys>.iconfig
 
For using the Cypress FX2 USB controlle on Digilent Nexys2, Nexys3 and
Atlys boards just connect the USB cable and
 
make <sys>.jconfig
 
This will automatically check and optionaly re-load the FX2 firmware
to a version matching the FPGA design, generate a .svf file from the
.bit file, and configure the FPGA. In case the bit file is out-of-date
the whole design will be re-implemented before.
 
8c. Available systems ------------------------------------------------
 
Note: Currently ready to build versions exist for
Digilent S3BOARD (-1000 FPGA version)
Digilent Nexys2 board (-1200 FPGA version)
232,7 → 357,13
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3
make sys_tst_rlink_n3.bit
 
2. w11a systems
2. rlink over USB tester
a. for Digilent Nexys2 board
 
cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys2/ic
make sys_tst_rlink_cuff_ic_n2.bit
 
3. w11a systems
a. for Digilent S3BOARD
cd $RETROBASE/rtl/sys_gen/w11a/s3board
/doc/w11a_tb_guide.txt
1,4 → 1,4
# $Id: w11a_tb_guide.txt 442 2011-12-23 10:03:28Z mueller $
# $Id: w11a_tb_guide.txt 443 2011-12-23 11:21:03Z mueller $
 
Guide to running w11a test benches
 
89,20 → 89,22
make tb_rlink_direct
time tbw tb_rlink_direct |\
tee tb_rlink_direct_dsim.log | egrep "(FAIL|DONE)"
-> 142355.0 ns 7108: DONE
-> 147755.0 ns 7378: DONE
-> real 0m00.317s user 0m00.324s sys 0m00.028s
 
- rlink core test via serial port interface
 
make tb_rlink_serport
time tbw tb_rlink_serport tb_rlink_serport_stim.dat |\
tee tb_rlink_serport_stim2_dsim.log | egrep "(FAIL|DONE)"
-> 72735.0 ns 3627: DONE
-> real 0m00.266s user 0m00.264s sys 0m00.008s
cd $RETROBASE/rtl/vlib/rlink/tb
make tb_rlink_sp1c
time tbw tb_rlink_sp1c tb_rlink_sp1c_stim.dat |\
tee tb_rlink_sp1c_stim2_dsim.log | egrep "(FAIL|DONE)"
-> 24695.0 ns 1225: DONE
-> real 0m0.133s user 0m0.104s sys 0m0.008s
 
time tbw tb_rlink_serport tb_rlink_stim.dat |\
tee tb_rlink_serport_dsim.log | egrep "(FAIL|DONE)"
-> 536155.0 ns 26798: DONE
 
time tbw tb_rlink_sp1c tb_rlink_stim.dat |\
tee tb_rlink_sp1c_dsim.log | egrep "(FAIL|DONE)"
-> 551935.0 ns 27587: DONE
-> real 0m01.714s user 0m01.704s sys 0m00.044s
 
- w11a core test (using behavioural model)
125,7 → 127,6
- s3board sram controller test
 
cd $RETROBASE/rtl/bplib/s3board/tb
 
make tb_s3_sram_memctl
time tbw tb_s3_sram_memctl |\
tee tb_s3_sram_memctl_dsim.log | egrep "(FAIL|DONE)"
136,7 → 137,6
- nexys2/nexys3 cram controller test
 
cd $RETROBASE/rtl/bplib/nxcramlib/tb
make tb_nx_cram_memctl_as
time tbw tb_nx_cram_memctl_as |\
tee tb_nx_cram_memctl_as_dsim.log | egrep "(FAIL|DONE)"
/doc/README.txt
1,4 → 1,4
# $Id: README.txt 442 2011-12-23 10:03:28Z mueller $
# $Id: README.txt 467 2013-01-02 19:49:05Z mueller $
 
Release notes for w11a
 
26,6 → 26,7
rtl VHDL sources
rtl/bplib - board and component support libs
rtl/bplib/atlys - for Digilent Atlys board
rtl/bplib/fx2lib - for Cypress FX2 USB interface controller
rtl/bplib/issi - for ISSI parts
rtl/bplib/micron - for Micron parts
rtl/bplib/nexys2 - for Digilent Nexsy2 board
34,8 → 35,12
rtl/bplib/s3board - for Digilent S3BOARD
rtl/ibus - ibus devices (UNIBUS peripherals)
rtl/sys_gen - top level designs
rtl/sys_gen/tst_fx2loop - top level designs for Cypress FX2 tester
nexys2 - systems for Nexsy2
rtl/sys_gen/tst_rlink - top level designs for an rlink tester
nexys2,nexys3,s3board - systems for Nexsy2,Nexsy3,S3BOARD
rtl/sys_gen/tst_rlink_cuff - top level designs for rlink over FX2 tester
nexys2 - systems for Nexsy2
rtl/sys_gen/tst_serloop - top level designs for serport loop tester
nexys2,nexys3,s3board - systems for Nexsy2,Nexsy3,S3BOARD
rtl/sys_gen/tst_snhumanio - top level designs for human I/O tester
56,16 → 61,77
tools/bin - scripts and binaries
tools/dox - Doxygen documentation configuration
tools/make - make includes
tools/src - C++ sources
tools/fx2 - Firmware for Cypress FX2 USB Interface
tools/fx2/bin - pre-build firmware images in .ihx format
tools/fx2/src - C and asm sources
tools/fx2/sys - udev rules for USB on fpga eval boards
tools/src - C++ sources for rlink backend software
tools/src/librlink - basic rlink interface
tools/src/librlinktpp - C++ to tcl binding for rlink interface
tools/src/librtcltools - support classes to implement Tcl bindings
tools/src/librtools - general support classes and methods
tools/src/librtcltools - support classes to implement Tcl bindings
tools/src/librutiltpp - Tcl support commands implemented in C++
tools/tcl - Tcl scripts
 
3. Change Log ----------------------------------------------------------------
 
- trunk (2013-01-02: svn rev 17(oc) 467(wfjm); untagged w11a_V0.56) ++++++++++
 
- Summary
- re-organized handling of board and derived clocks in test benches
- added message filter definitions for some designs (.mfset files)
- added Cypress EZ-USB FX2 controller (USB interface)
- added firmware for EZ-USB FX2 supporting jtag access and data transfer
- FPGA configure over USB now supported directly in make build flow
- added test systems for USB testing and rlink over USB verification
- no functional change of w11a CPU core or any pre-existing test systems
- Note: Carefully read the disclaimer about usage of USB VID/PID numbers
in the file README_USB-VID-PID.txt. You'll be responsible for any
misuse of the defaults provided with the project sources !!
 
- New refernce system
The development and test system was upgraded from Kubuntu 10.04 to 12.04.
The version of several key tools and libraries changed:
linux kernel 3.2.0 (was 2.6.32)
gcc/g++ 4.6.3 (was 4.4.3)
boost 1.46.1 (was 1.40)
libusb 1.0.9 (was 1.0.6)
perl 5.14.2 (was 5.10.1)
tcl 8.5.11 (was 8.4.19)
xilinx ise 13.3 (was 13.1)
--> see INSTALL.txt, INSTALL_ghdl.txt and INSTALL_urjtag.txt
 
- New features
- added firmware for Cypress FX2 controller
- tools/fx2
- bin - pre-build firmware images in .ihx file format
- src - C and asm sources
- sys - udev rules for usb interfaces on fpga eval boards
- new modules
- rtl/bplib/fx2lib
- fx2_2fifoctl_ic - Cypress EZ-USB FX2 controller (2 fifo; int clk)
- fx2_3fifoctl_ic - Cypress EZ-USB FX2 controller (3 fifo; int clk)
- new systems
- rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2
- rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2
- rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2
- tools/bin
- xilinx_sdf_ghdl_filter: tool to patch ISE sdf files for usage with ghdl
 
- Changes
- documentation
- added a 'system requirements' section in INSTALL.txt
- added INSTALL_ghdl.txt and INSTALL_urjtag.txt covering ghdl and urjtag
- added README_USB-VID-PID.txt
- organizational changes
- added TCLINC,RETRO_FX2_VID,RETRO_FX2_PID environment variables
- functional changes
- tools/bin
- vbomconv - file name substitution handling redone; many vboms updated
- retired modules
- vlib/rlink/tb/
- tbcore_rlink_dcm - obsolete, use tbcore_rlink
 
- trunk (2011-12-23: svn rev 16(oc) 442(wfjm); untagged w11a_V0.55) +++++++++
 
- Summary
73,14 → 139,6
- added test systems for serport verification
- use new serport stack in sys_w11a_* and sys_tst_rlink_* systems
 
- Changes
- retired modules
- vlib/rlink
- rlink_rlb2rl - obsolete, now all in rlink_core8
- rlink_base - use now new rlink_core8
- rlink_serport - obsolete, now all in rlink_sp1c
- rlink_base_serport - use now new rlink_sp1c
 
- New features
- new modules
- vlib/serport
99,21 → 157,29
- sys_gen/tst_serloop/s3board/sys_tst_serloop1_s3
- sys_gen/tst_rlink/s3board/sys_tst_rlink_s3
 
- Changes
- retired modules
- vlib/rlink
- rlink_rlb2rl - obsolete, now all in rlink_core8
- rlink_base - use now new rlink_core8
- rlink_serport - obsolete, now all in rlink_sp1c
- rlink_base_serport - use now new rlink_sp1c
 
- trunk (2011-12-04: svn rev 15(oc) 436(wfjm); untagged w11a_V0.54) +++++++++
 
- Summary
- added support for nexys3 board for w11a
 
- New features
- new systems
- sys_gen/w11a/nexys3/sys_w11a_n3
- sys_gen/w11a/nexys3/sys_tst_rlink_n3
 
- Changes
- module renames:
bplib/nexys2/n2_cram_dummy -> bplib/nxcramlib/nx_cram_dummy
bplib/nexys2/n2_cram_memctl_as -> bplib/nxcramlib/nx_cram_memctl_as
 
- New features
- new systems
- sys_gen/w11a/nexys3/sys_w11a_n3
- sys_gen/w11a/nexys3/sys_tst_rlink_n3
 
- Bug fixes
- tools/src/lib*: backend libraries compile now on 64 bit systems
 
221,6 → 287,11
- Introduce rbus protocol V3
- reorganize rbus and rlink modules, many renames
 
- New features
- vlib/rbus
- added several rbus devices useful for debugging
- rbd_tester: test target, used for example in test benches
 
- Changes
- module renames:
- the rri (remote-register-interface) components were re-organized and
282,11 → 353,6
- rlink_serport (re-written) is an adapter to a serial interface
- rlink_base_serport (renamed) combines rlink_base and rlink_serport
 
- New features
- vlib/rbus
- added several rbus devices useful for debugging
- rbd_tester: test target, used for example in test benches
 
- trunk (2010-11-28: svn rev 8(oc) 341(wfjm); untagged w11a_V0.51) +++++++++++
 
- Summary
294,6 → 360,15
- Nexys2 systems use DCM
- sys_w11a_n2 now runs with 58 MHz
 
- New features
- ibus
- added ib_sres_or_mon to check for miss-behaving ibus devices
- added ib_sel to encapsulate address select logic
- nexys2 systems
- now DCM derived system clock supported
- sys_gen/w11a/nexys2
- sys_w11a_n2 now runs with 58 MHz clksys
 
- Changes
- module renames:
- in future 'box' is used for large autonomous blocks, therefore use
312,15 → 387,6
- basic ibus transaction now takes 2 cycles, one for address select, one
for data exchange. This avoids too long logic paths in the ibus logic.
 
- New features
- ibus
- added ib_sres_or_mon to check for miss-behaving ibus devices
- added ib_sel to encapsulate address select logic
- nexys2 systems
- now DCM derived system clock supported
- sys_gen/w11a/nexys2
- sys_w11a_n2 now runs with 58 MHz clksys
 
- Bug fixes
- rtl/vlib/Makefile.xflow: use default .opt files under rtl/vlib again.
 
/doc/README_USB-VID-PID.txt
0,0 → 1,55
# $Id: README_USB-VID-PID.txt 467 2013-01-02 19:49:05Z mueller $
 
!! Read this disclaimer carefully. You'll be responsible for any !!
!! misuse of the defaults provided with the project sources. !!
 
USB drivers identify hardware by means of two 16 bit identifiers
 
VID - Vendor ID
PID - Product ID
 
In a 'softcoded' USB Controler like the Cypress FX2 each firmware with a
specific functionality should have a unique VID/PID so that drivers can
automatically detect and configure.
 
The assignment of USB VID/PID is done by usb.org. Unfortunately there is no
VID range reserved for 'development' or 'internal use', the only official way
to obtain a VID is to buy one from usb.org, see
http://www.usb.org/developers/vendor/
 
The 'usb_jtag' project bought many years ago a small PID range from a re-seller
and used
VID=16C0
PID=06AD
for a project which implemented an Altera UsbBlaster compatible JTAG interface.
 
The firmware provided with this project provides
- a JTAG interface (via EP1 and EP2)
- data channels (via EP4, EP6 and optionally EP8)
The JTAG part is compatible with the 'usb_jtag' implementation and by extension
compatible with the 'usbblaster' cable driver provided by 'UrJtag', and can
therefore be operated with the 'jtag' command.
 
However, because the firmware offers additional functionality it should have a
separate VID/PID. Unfortunately it is not longer possible to buy at very modest
cost a PID sub-range, as was done by the 'usb_jtag' project bought many years
ago.
 
VOTI, a small dutch company, has bought a VID for it's own developments and
made a small range of PID publicly available as "free for internal lab use".
Usage is granted for 'internal lab use only' by VOTI under the conditions:
- the gadgets in which you use those PIDs do not leave your desk
- you won't complain to VOTI if you get in trouble with duplicate PIDs
(for instance because someone else did not follow the previous rule).
- See http://www.voti.nl/pids/pidfaq.html for further details.
 
The retro11 project uses one of these 'free for internal lab use' PIDs
 
VID=16C0
PID=03EF
 
from VOTI as default VID/PID.
 
==> This is is perfectly fine for plain hobbyist usage
==> But respect the ownership of VOTI of this VID/PID and do not
use this VID/PID for other purposes
/Makefile
1,4 → 1,4
# $Id: Makefile 442 2011-12-23 10:03:28Z mueller $
# $Id: Makefile 466 2012-12-30 13:26:55Z mueller $
#
# 'Meta Makefile' for whole retro project
# allows to make all synthesis targets
6,13 → 6,19
#
# Revision History:
# Date Rev Version Comment
# 2012-12-29 466 1.0.5 add tst_rlink_cuff
# 2011-12-26 445 1.0.4 add tst_fx2loop
# 2011-12-23 444 1.0.3 enforce -j 1 in sub-makes
# 2011-11-27 433 1.0.2 add new nexys3 ports
# 2011-11-18 426 1.0.1 add tst_serport and tst_snhumanio
# 2011-07-09 391 1.0 Initial version
#
SYN_all += rtl/sys_gen/tst_fx2loop/nexys2/ic
SYN_all += rtl/sys_gen/tst_fx2loop/nexys2/ic3
SYN_all += rtl/sys_gen/tst_rlink/nexys2
SYN_all += rtl/sys_gen/tst_rlink/nexys3
SYN_all += rtl/sys_gen/tst_rlink/s3board
SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic
SYN_all += rtl/sys_gen/tst_serloop/nexys2
SYN_all += rtl/sys_gen/tst_serloop/nexys3
SYN_all += rtl/sys_gen/tst_serloop/s3board
43,8 → 49,8
#
all :
@echo "no default action defined, use"
@echo " make all_sim"
@echo " make all_syn"
@echo " make -j 4 all_sim"
@echo " make -j 4 all_syn"
@echo " make clean"
@echo " make clean_sim"
@echo " make clean_syn"
58,10 → 64,20
for dir in $(SYN_all); do $(MAKE) -C $$dir clean; done
#
all_sim : $(SIM_all)
#
all_syn : $(SYN_all)
@if [ -n "`find -name "*_par.log" | xargs grep -L 'All constraints were met'`" ] ; then \
echo "++++++++++ some designs have no timing closure: ++++++++++"; \
find -name "*_par.log" | xargs grep -L 'All constraints were met'; \
echo "++++++++++ ++++++++++++++++++++++++++++++++++++ ++++++++++"; \
fi
#
# Neither ghdl nor xst allow multiple parallel compiles in one directory.
# The following ensures that the sub-makes are called with -j 1 and will
# not try to run multiple compiles on one directory.
#
$(SIM_all):
$(MAKE) -C $@
$(MAKE) -j 1 -C $@
$(SYN_all):
$(MAKE) -C $@
$(MAKE) -j 1 -C $@
#

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