OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /w11/trunk
    from Rev 8 to Rev 9
    ↔ Reverse comparison
  •

Rev 8 → Rev 9

/tools/bin/pi_rri
1,5 → 1,5
#!/usr/bin/perl -w
# $Id: pi_rri 314 2010-07-09 17:38:41Z mueller $
# $Id: pi_rri 351 2010-12-30 21:50:54Z mueller $
#
# Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
14,6 → 14,7
#
# Revision History:
# Date Rev Version Comment
# 2010-12-29 351 1.6.3 rename rriext->cext and cpmon->rlmon
# 2010-06-27 310 1.6.2 fix autoflush for fh_log; duplicate exec err to log
# 2010-06-18 306 1.6.1 PDPCP_ADDR_IBRB now 020, PDPCP_ADDR_IBR now 0200;
# ibrbase now just drops the 6 lsb's; pdpcp mode:
2089,7 → 2090,7
}
 
#-------------------------------------------------------------------------------
# .cpmon 0|1
# .rlmon 0|1
# .rbmon 0|1
# .scntl n 0|1
# .sinit g8 g16
2117,8 → 2118,8
$cmd_rest = "";
$cmd_bad = 0;
 
if ($cmd =~ /^(\.cpmon|\.rbmon)\s+([01])/) { # .cpmon, .rbmon -------------
my $ind = ($1 eq ".cpmon") ? 15 : 14;
if ($cmd =~ /^(\.rlmon|\.rbmon)\s+([01])/) { # .rlmon, .rbmon -------------
my $ind = ($1 eq ".rlmon") ? 15 : 14;
$cmd_rest = $';
rri_sideband(0x00, ($ind<<8) + $2);
 
2708,7 → 2709,7
# .tostp n
# .togo n
# .anena 0|1
# .cpmon 0|1
# .rlmon 0|1
# .rbmon 0|1
# .scntl n 0|1
# .sinit g8 g16
2777,9 → 2778,9
data => $ena_data};
rri_cmdlist_do();
 
} elsif ($cmd =~ /^(\.cpmon|\.rbmon)\s+([01])/) { # .cpmon, .rbmon ---------
} elsif ($cmd =~ /^(\.rlmon|\.rbmon)\s+([01])/) { # .rlmon, .rbmon ---------
$cmd_rest = $';
my $ind = ($1 eq ".cpmon") ? 15 : 14;
my $ind = ($1 eq ".rlmon") ? 15 : 14;
$cmd_rest = $';
rri_sideband(0x00, ($ind<<8) + $2);
 
3237,7 → 3238,7
my $val = cget_bool();
return if $cmd_bad or cget_chkblank();
my $ind;
$ind = 15 if $pnam eq "cpmon";
$ind = 15 if $pnam eq "rlmon";
$ind = 14 if $pnam eq "rbmon";
$ind = 13 if $pnam eq "tmu";
if (defined $ind) {
6370,7 → 6371,7
sub fifo_open { # chan fifo: open handler
my ($arg) = @_;
my ($file,$keep) = split /,/,$arg;
my $file_base = $file ? $file : "tb_rriext_fifo";
my $file_base = $file ? $file : "rlink_cext_fifo";
my $file_snd = $file_base . "_rx";
my $file_rcv = $file_base . "_tx";
 
/rtl/ibus/ibdr_dl11.vhd
1,4 → 1,4
-- $Id: ibdr_dl11.vhd 335 2010-10-24 22:24:23Z mueller $
-- $Id: ibdr_dl11.vhd 350 2010-12-28 16:40:11Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
22,9 → 22,9
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53 xc3s1000-4 39 126 0 72 s 7.6
-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 38 119 0 69 s 6.3
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 23 61 0 40 s 5.5
-- 2010-10-17 333 12.1 M53d xc3s1000-4 39 126 0 72 s 7.6
-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 38 119 0 69 s 6.3
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 23 61 0 40 s 5.5
--
-- Revision History:
-- Date Rev Version Comment
/rtl/ibus/ibdr_pc11.vhd
1,4 → 1,4
-- $Id: ibdr_pc11.vhd 335 2010-10-24 22:24:23Z mueller $
-- $Id: ibdr_pc11.vhd 350 2010-12-28 16:40:11Z mueller $
--
-- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
22,8 → 22,8
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53 xc3s1000-4 26 97 0 57 s 6.0
-- 2009-06-28 230 10.1.03 K39 xc3s1000-4 25 92 0 54 s 4.9
-- 2010-10-17 333 12.1 M53d xc3s1000-4 26 97 0 57 s 6.0
-- 2009-06-28 230 10.1.03 K39 xc3s1000-4 25 92 0 54 s 4.9
--
-- Revision History:
-- Date Rev Version Comment
/rtl/ibus/ibdr_lp11.vhd
1,4 → 1,4
-- $Id: ibdr_lp11.vhd 335 2010-10-24 22:24:23Z mueller $
-- $Id: ibdr_lp11.vhd 350 2010-12-28 16:40:11Z mueller $
--
-- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
22,8 → 22,8
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53 xc3s1000-4 12 35 0 24 s 5.6
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 11 30 0 19 s 5.8
-- 2010-10-17 333 12.1 M53d xc3s1000-4 12 35 0 24 s 5.6
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 11 30 0 19 s 5.8
--
-- Revision History:
-- Date Rev Version Comment
/rtl/ibus/ibd_kw11l.vhd
1,4 → 1,4
-- $Id: ibd_kw11l.vhd 335 2010-10-24 22:24:23Z mueller $
-- $Id: ibd_kw11l.vhd 350 2010-12-28 16:40:11Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
22,8 → 22,8
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53 xc3s1000-4 9 23 0 14 s 5.3
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 8 25 0 15 s 5.3
-- 2010-10-17 333 12.1 M53d xc3s1000-4 9 23 0 14 s 5.3
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 8 25 0 15 s 5.3
--
-- Revision History:
-- Date Rev Version Comment
/rtl/ibus/ibdr_rk11.vhd
1,4 → 1,4
-- $Id: ibdr_rk11.vhd 335 2010-10-24 22:24:23Z mueller $
-- $Id: ibdr_rk11.vhd 350 2010-12-28 16:40:11Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
22,9 → 22,9
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53 xc3s1000-4 46 248 16 137 s 7.2
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 46 249 16 148 s 7.1
-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 36 189 16 111 s 6.0
-- 2010-10-17 333 12.1 M53d xc3s1000-4 46 248 16 137 s 7.2
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 46 249 16 148 s 7.1
-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 36 189 16 111 s 6.0
--
-- Revision History:
-- Date Rev Version Comment
/rtl/ibus/iblib.vhd
1,4 → 1,4
-- $Id: iblib.vhd 335 2010-10-24 22:24:23Z mueller $
-- $Id: iblib.vhd 346 2010-12-22 22:59:26Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
113,15 → 113,6
);
end component;
 
component ib_sres_or_mon is -- ibus result or monitor
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_4 : in ib_sres_type := ib_sres_init -- ib_sres input 4
);
end component;
 
type intmap_type is record -- interrupt map entry type
vec : integer; -- vector address
pri : integer; -- priority
142,5 → 133,18
EI_VECT : out slv9_2 -- interrupt vector
);
end component;
 
--
-- components for use in test benches (not synthesizable)
--
component ib_sres_or_mon is -- ibus result or monitor
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_4 : in ib_sres_type := ib_sres_init -- ib_sres input 4
);
end component;
 
end package iblib;
/rtl/ibus/ibd_iist.vhd
1,4 → 1,4
-- $Id: ibd_iist.vhd 335 2010-10-24 22:24:23Z mueller $
-- $Id: ibd_iist.vhd 350 2010-12-28 16:40:11Z mueller $
--
-- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
22,10 → 22,10
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53 xc3s1000-4 112 510 0 291 s 15.8
-- 2010-10-17 314 12.1 M53 xc3s1000-4 111 504 0 290 s 15.6
-- 2009-06-01 223 10.1.03 K39 xc3s1000-4 111 439 0 256 s 9.8
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 111 449 0 258 s 13.3
-- 2010-10-17 333 12.1 M53d xc3s1000-4 112 510 0 291 s 15.8
-- 2010-10-17 314 12.1 M53d xc3s1000-4 111 504 0 290 s 15.6
-- 2009-06-01 223 10.1.03 K39 xc3s1000-4 111 439 0 256 s 9.8
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 111 449 0 258 s 13.3
--
-- Revision History:
-- Date Rev Version Comment
/rtl/ibus/ibdr_minisys.vhd
1,4 → 1,4
-- $Id: ibdr_minisys.vhd 335 2010-10-24 22:24:23Z mueller $
-- $Id: ibdr_minisys.vhd 350 2010-12-28 16:40:11Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
27,8 → 27,8
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53 xc3s1000-4 128 469 16 265 s 7.8
-- 2010-10-17 314 12.1 M53 xc3s1000-4 122 472 16 269 s 7.6
-- 2010-10-17 333 12.1 M53d xc3s1000-4 128 469 16 265 s 7.8
-- 2010-10-17 314 12.1 M53d xc3s1000-4 122 472 16 269 s 7.6
--
-- Revision History:
-- Date Rev Version Comment
/rtl/ibus/ibdr_maxisys.vhd
1,4 → 1,4
-- $Id: ibdr_maxisys.vhd 335 2010-10-24 22:24:23Z mueller $
-- $Id: ibdr_maxisys.vhd 350 2010-12-28 16:40:11Z mueller $
--
-- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
31,8 → 31,8
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53 xc3s1000-4 312 1058 16 617 s 10.3
-- 2010-10-17 314 12.1 M53 xc3s1000-4 300 1094 16 626 s 10.4
-- 2010-10-17 333 12.1 M53d xc3s1000-4 312 1058 16 617 s 10.3
-- 2010-10-17 314 12.1 M53d xc3s1000-4 300 1094 16 626 s 10.4
--
-- Revision History:
-- Date Rev Version Comment
/rtl/ibus/ibdr_sdreg.vhd
1,4 → 1,4
-- $Id: ibdr_sdreg.vhd 335 2010-10-24 22:24:23Z mueller $
-- $Id: ibdr_sdreg.vhd 350 2010-12-28 16:40:11Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
22,8 → 22,8
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53 xc3s1000-4 34 40 0 30 s 4.0
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 32 39 0 29 s 2.5
-- 2010-10-17 333 12.1 M53d xc3s1000-4 34 40 0 30 s 4.0
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 32 39 0 29 s 2.5
--
-- Revision History:
-- Date Rev Version Comment
/rtl/sys_gen/w11a/nexys2/tb/tbw.dat
1,6 → 1,6
# $Id: tbw.dat 295 2010-05-29 16:58:01Z mueller $
# $Id: tbw.dat 351 2010-12-30 21:50:54Z mueller $
#
[tb_w11a_n2]
tb_rriext_fifo_rx = <fifo>
tb_rriext_fifo_tx = <fifo>
tb_rriext_conf = <null>
rlink_cext_fifo_rx = <fifo>
rlink_cext_fifo_tx = <fifo>
rlink_cext_conf = <null>
/rtl/sys_gen/w11a/nexys2/tb/tb_w11a_n2_ssim.vbom
0,0 → 1,6
# configure for _*sim case
# Note: this tb uses sys_w11a_n2.vbom in local directory
# (not in .. as usual) to allow a tb specific configure !!!
nexys2_fusp_aif = sys_w11a_n2_ssim.vhd
tb_w11a_n2.vbom
@top:tb_w11a_n2
/rtl/sys_gen/w11a/nexys2/tb/.cvsignore
1,8 → 1,8
tb_w11a_n2
tb_w11a_n2_[sft]sim
tb_rriext_fifo_rx
tb_rriext_fifo_tx
tb_rriext_conf
rlink_cext_fifo_rx
rlink_cext_fifo_tx
rlink_cext_conf
tmu_ofile
sys_w11a_n2.ucf
*.dep_ucf_cpp
/rtl/sys_gen/w11a/nexys2/tb
rtl/sys_gen/w11a/nexys2/tb Property changes : Modified: svn:ignore ## -32,9 +32,9 ## *_[dsft]sim.log tb_w11a_n2 tb_w11a_n2_[sft]sim -tb_rriext_fifo_rx -tb_rriext_fifo_tx -tb_rriext_conf +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf tmu_ofile sys_w11a_n2.ucf *.dep_ucf_cpp Index: rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd =================================================================== --- rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd (revision 8) +++ rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd (revision 9) @@ -1,4 +1,4 @@ --- $Id: sys_w11a_n2.vhd 341 2010-11-27 23:05:43Z mueller $ +-- $Id: sys_w11a_n2.vhd 351 2010-12-30 21:50:54Z mueller $ -- -- Copyright 2010- by Walter F.J. Mueller -- @@ -18,10 +18,10 @@ -- Dependencies: vlib/xlib/dcm_sp_sfs -- vlib/genlib/clkdivce -- bplib/s3board/s3_rs232_iob_int_ext --- bplib/s3board/s3_humanio_rri --- vlib/rri/rri_core_serport +-- bplib/s3board/s3_humanio_rbus +-- vlib/rlink/rlink_base_serport -- vlib/rri/rb_sres_or_3 --- w11a/pdp11_core_rri +-- w11a/pdp11_core_rbus -- w11a/pdp11_core -- w11a/pdp11_bram -- vlib/nexys2/n2_cram_dummy @@ -40,6 +40,7 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2010-12-30 351 12.1 M53d xc3s1200e-4 1389 4368 242 2674 ok: LP+PC+DL+II -- 2010-11-06 336 12.1 M53d xc3s1200e-4 1357 4304* 242 2618 ok: LP+PC+DL+II -- 2010-10-24 335 12.1 M53d xc3s1200e-4 1357 4546 242 2618 ok: LP+PC+DL+II -- 2010-10-17 333 12.1 M53d xc3s1200e-4 1350 4541 242 2617 ok: LP+PC+DL+II @@ -61,6 +62,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2010-12-30 351 1.2 ported to rbv3 -- 2010-11-27 341 1.1.8 add DCM; new sys_conf consts for mem and clkdiv -- 2010-11-13 338 1.1.7 add O_CLKSYS (for DCM derived system clock) -- 2010-11-06 336 1.1.6 rename input pin CLK -> I_CLK50 @@ -80,7 +82,7 @@ ------------------------------------------------------------------------------ -- -- w11a test design for nexys2 --- w11a + rri + serport +-- w11a + rlink + serport -- -- Usage of Nexys 2 Switches, Buttons, LEDs: -- @@ -96,7 +98,7 @@ -- if cpugo=0 shows cpurust -- (3:0) cpurust code -- (4) '1' --- (5) cmdbusy (all rri access, mostly rdma) +-- (5) cmdbusy (all rlink access, mostly rdma) -- (6) MEM_ACT_R -- (7) MEM_ACT_W -- @@ -112,7 +114,8 @@ use work.slvtypes.all; use work.xlib.all; use work.genlib.all; -use work.rrilib.all; +use work.rblib.all; +use work.rlinklib.all; use work.s3boardlib.all; use work.nexys2lib.all; use work.iblib.all; @@ -276,7 +279,7 @@ O_RTS1_N => O_FUSP_RTS_N ); - HIO : s3_humanio_rri + HIO : s3_humanio_rbus generic map ( DEBOUNCE => sys_conf_hio_debounce, RB_ADDR => rbaddr_hio) @@ -298,10 +301,12 @@ O_SEG_N => O_SEG_N ); - RRI : rri_core_serport + RLINK : rlink_base_serport generic map ( ATOWIDTH => 6, -- 64 cycles access timeout ITOWIDTH => 6, -- 64 periods max idle timeout + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 0, -- no output fifo CDWIDTH => 13, CDINIT => sys_conf_ser2rri_cdinit) port map ( @@ -317,7 +322,9 @@ RB_MREQ => RB_MREQ, RB_SRES => RB_SRES, RB_LAM => RB_LAM, - RB_STAT => RB_STAT + RB_STAT => RB_STAT, + RL_MONI => open, + RL_SER_MONI => open ); RB_SRES_OR : rb_sres_or_3 @@ -328,7 +335,7 @@ RB_SRES_OR => RB_SRES ); - RB2CP : pdp11_core_rri + RB2CP : pdp11_core_rbus generic map ( RB_ADDR_CORE => rbaddr_core0, RB_ADDR_IBUS => rbaddr_ibus)
/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom
2,7 → 2,8
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../vlib/rri/rrilib.vhd
../../../vlib/rbus/rblib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../bplib/s3board/s3boardlib.vbom
../../../bplib/nexys2/nexys2lib.vhd
../../../ibus/iblib.vhd
14,10 → 15,10
[ghdl]../../../vlib/xlib/dcm_sp_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/s3board/s3_rs232_iob_int_ext.vbom
../../../bplib/s3board/s3_humanio_rri.vbom
../../../vlib/rri/rri_core_serport.vbom
../../../vlib/rri/rb_sres_or_3.vbom
../../../w11a/pdp11_core_rri.vbom
../../../bplib/s3board/s3_humanio_rbus.vbom
../../../vlib/rlink/rlink_base_serport.vbom
../../../vlib/rbus/rb_sres_or_3.vbom
../../../w11a/pdp11_core_rbus.vbom
../../../w11a/pdp11_core.vbom
../../../w11a/pdp11_bram.vbom
../../../bplib/nexys2/n2_cram_dummy.vbom
/rtl/sys_gen/w11a/s3board/tb/tb_w11a_s3_ssim.vbom
0,0 → 1,6
# configure for _*sim case
# Note: this tb uses sys_w11a_s3.vbom in local directory
# (not in .. as usual) to allow a tb specific configure !!!
s3board_fusp_aif = sys_w11a_s3_ssim.vhd
tb_w11a_s3.vbom
@top:tb_w11a_s3
/rtl/sys_gen/w11a/s3board/tb/tbw.dat
1,6 → 1,6
# $Id: tbw.dat 295 2010-05-29 16:58:01Z mueller $
# $Id: tbw.dat 351 2010-12-30 21:50:54Z mueller $
#
[tb_w11a_s3]
tb_rriext_fifo_rx = <fifo>
tb_rriext_fifo_tx = <fifo>
tb_rriext_conf = <null>
rlink_cext_fifo_rx = <fifo>
rlink_cext_fifo_tx = <fifo>
rlink_cext_conf = <null>
/rtl/sys_gen/w11a/s3board/tb/.cvsignore
1,8 → 1,8
tb_w11a_s3
tb_w11a_s3_[sft]sim
tb_rriext_fifo_rx
tb_rriext_fifo_tx
tb_rriext_conf
rlink_cext_fifo_rx
rlink_cext_fifo_tx
rlink_cext_conf
tmu_ofile
sys_w11a_s3.ucf
*.dep_ucf_cpp
/rtl/sys_gen/w11a/s3board/tb
rtl/sys_gen/w11a/s3board/tb Property changes : Modified: svn:ignore ## -32,9 +32,9 ## *_[dsft]sim.log tb_w11a_s3 tb_w11a_s3_[sft]sim -tb_rriext_fifo_rx -tb_rriext_fifo_tx -tb_rriext_conf +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf tmu_ofile sys_w11a_s3.ucf *.dep_ucf_cpp Index: rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd =================================================================== --- rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd (revision 8) +++ rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd (revision 9) @@ -1,4 +1,4 @@ --- $Id: sys_w11a_s3.vhd 336 2010-11-06 18:28:27Z mueller $ +-- $Id: sys_w11a_s3.vhd 351 2010-12-30 21:50:54Z mueller $ -- -- Copyright 2007-2010 by Walter F.J. Mueller -- @@ -18,9 +18,9 @@ -- Dependencies: vlib/genlib/clkdivce -- bplib/s3board/s3_rs232_iob_int_ext -- bplib/s3board/s3_humanio --- vlib/rri/rri_core_serport --- vlib/rri/rb_sres_or_2 --- w11a/pdp11_core_rri +-- vlib/rlink/rlink_base_serport +-- vlib/rbus/rb_sres_or_2 +-- w11a/pdp11_core_rbus -- w11a/pdp11_core -- w11a/pdp11_bram -- vlib/s3board/s3_sram_dummy @@ -39,6 +39,7 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2010-12-30 351 12.1 M53d xc3s1000-4 1316 4291 242 2609 OK: LP+PC+DL+II -- 2010-11-06 336 12.1 M53d xc3s1000-4 1284 4253* 242 2575 OK: LP+PC+DL+II -- 2010-10-24 335 12.1 M53d xc3s1000-4 1284 4495 242 2575 OK: LP+PC+DL+II -- 2010-05-01 285 11.4 L68 xc3s1000-4 1239 4086 224 2471 OK: LP+PC+DL+II @@ -70,6 +71,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2010-12-30 351 1.4 ported to rbv3 -- 2010-11-06 336 1.3.7 rename input pin CLK -> I_CLK50 -- 2010-10-23 335 1.3.3 rename RRI_LAM->RB_LAM; -- 2010-06-26 309 1.3.2 use constants for rbus addresses (rbaddr_...) @@ -113,7 +115,7 @@ ------------------------------------------------------------------------------ -- -- w11a test design for s3board --- w11a + rri + serport +-- w11a + rlink + serport -- -- Usage of S3BOARD Switches, Buttons, LEDs: -- LED(7..0):last RXDATA @@ -129,7 +131,8 @@ use work.slvtypes.all; use work.genlib.all; -use work.rrilib.all; +use work.rblib.all; +use work.rlinklib.all; use work.s3boardlib.all; use work.iblib.all; use work.ibdlib.all; @@ -285,10 +288,12 @@ O_SEG_N => O_SEG_N ); - RRI : rri_core_serport + RLINK : rlink_base_serport generic map ( ATOWIDTH => 6, -- 64 cycles access timeout ITOWIDTH => 6, -- 64 periods max idle timeout + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 0, -- no output fifo CDWIDTH => 13, CDINIT => sys_conf_ser2rri_cdinit) port map ( @@ -304,7 +309,9 @@ RB_MREQ => RB_MREQ, RB_SRES => RB_SRES, RB_LAM => RB_LAM, - RB_STAT => RB_STAT + RB_STAT => RB_STAT, + RL_MONI => open, + RL_SER_MONI => open ); RB_SRES_OR : rb_sres_or_2 @@ -314,7 +321,7 @@ RB_SRES_OR => RB_SRES ); - RP2CP : pdp11_core_rri + RP2CP : pdp11_core_rbus generic map ( RB_ADDR_CORE => rbaddr_core0, RB_ADDR_IBUS => rbaddr_ibus)
/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom
1,7 → 1,8
# libs
../../../vlib/slvtypes.vhd
../../../vlib/genlib/genlib.vhd
../../../vlib/rri/rrilib.vhd
../../../vlib/rbus/rblib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../bplib/s3board/s3boardlib.vbom
../../../ibus/iblib.vhd
../../../ibus/ibdlib.vhd
11,9 → 12,9
../../../vlib/genlib/clkdivce.vbom
../../../bplib/s3board/s3_rs232_iob_int_ext.vbom
../../../bplib/s3board/s3_humanio.vbom
../../../vlib/rri/rri_core_serport.vbom
../../../vlib/rri/rb_sres_or_2.vbom
../../../w11a/pdp11_core_rri.vbom
../../../vlib/rlink/rlink_base_serport.vbom
../../../vlib/rbus/rb_sres_or_2.vbom
../../../w11a/pdp11_core_rbus.vbom
../../../w11a/pdp11_core.vbom
../../../w11a/pdp11_bram.vbom
../../../bplib/s3board/s3_sram_dummy.vbom
/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
1,4 → 1,4
-- $Id: tb_nexys2_fusp.vhd 339 2010-11-22 21:20:51Z mueller $
-- $Id: tb_nexys2_fusp.vhd 351 2010-12-30 21:50:54Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
15,7 → 15,7
-- Module Name: tb_nexys2_fusp - sim
-- Description: Test bench for nexys2 (base+fusp)
--
-- Dependencies: vlib/rri/tb/rritb_core_dcm
-- Dependencies: vlib/rlink/tb/tbcore_rlink_dcm
-- tb_nexys2_core
-- vlib/serport/serport_uart_rxtx
-- nexys2_fusp_aif [UUT]
27,6 → 27,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 3.0 use rlink/tb now
-- 2010-11-13 338 1.0.2 now dcm aware: add O_CLKSYS, use rritb_core_dcm
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0 Initial version (derived from tb_s3board_fusp)
39,8 → 40,8
use std.textio.all;
 
use work.slvtypes.all;
use work.rrilib.all;
use work.rritblib.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serport.all;
use work.nexys2lib.all;
use work.simlib.all;
108,7 → 109,7
 
begin
TBCORE : rritb_core_dcm
TBCORE : tbcore_rlink_dcm
generic map (
CLKOSC_PERIOD => clockosc_period,
CLKOSC_OFFSET => clockosc_offset,
/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom
4,14 → 4,14
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rri/rrilib.vhd
../../../vlib/rri/tb/rritblib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serport.vhd
../nexys2lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/rri/tb/rritb_core_dcm.vbom
../../../vlib/rlink/tb/tbcore_rlink_dcm.vbom
tb_nexys2_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
nexys2_fusp_aif : nexys2_fusp_dummy.vbom
/rtl/bplib/s3board/s3_humanio_rri.vbom File deleted
/rtl/bplib/s3board/s3_humanio_rri.vhd File deleted
/rtl/bplib/s3board/s3_humanio_rbus.vhd
0,0 → 1,286
-- $Id: s3_humanio_rbus.vhd 352 2011-01-02 13:01:37Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: s3_humanio_rbus - syn
-- Description: s3_humanio with rbus interceptor
--
-- Dependencies: s3board/s3_humanio
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-29 300 12.1 M53d xc3s1000-4 93 138 0 111 s 6.8 ns
-- 2010-06-03 300 11.4 L68 xc3s1000-4 92 137 0 111 s 6.7 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 1.1 renamed from s3_humanio_rri; ported to rbv3
-- 2010-06-18 306 1.0.1 rename rbus data fields to _rbf_
-- 2010-06-03 300 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Address Bits Name r/w/f Function
-- bbbbbb00 cntl r/w/- Control register and BTN access
-- 11 dat_en r/w/- if 1 display data will be driven by rri
-- 10 dp_en r/w/- if 1 display dp's will be driven by rri
-- 9 led_en r/w/- if 1 LED will be driven by rri
-- 8 swi_en r/w/- if 1 SWI will be driven by rri
-- 3:00 btn r/w/- r: return hio BTN status
-- w: BTN is hio BTN ored with this fields
--
-- bbbbbb01 7:00 swi r/w/- r: return hio SWI status
-- w: will drive SWI when swi_en=1
--
-- bbbbbb10 leddp r/w/- Interface to LED and DSP_DP
-- 11:09 dsp_dp r/w/- r: returns DSP_DP status
-- w: will drive display dp's when dp_en=1
-- 7:00 led r/w/- r: returns LED status
-- w: will drive led's when led_en=1
--
-- bbbbbb11 15:00 dsp_dat r/w/- r: return hio DSP_DAT status
-- w: will drive DSP_DAT when dat_en=1
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
use work.rblib.all;
use work.s3boardlib.all;
 
-- ----------------------------------------------------------------------------
 
entity s3_humanio_rbus is -- human i/o handling /w rbus intercept
generic (
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv8; -- switch settings, debounced
BTN : out slv4; -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv4; -- pad-i: buttons
O_LED : out slv8; -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
);
end s3_humanio_rbus;
 
architecture syn of s3_humanio_rbus is
type regs_type is record
rbsel : slbit; -- rbus select
swi : slv8; -- rbus swi
btn : slv4; -- rbus btn
led : slv8; -- rbus led
dsp_dat : slv16; -- rbus dsp_dat
dsp_dp : slv4; -- rbus dsp_dp
swi_en : slbit; -- enable: swi from rri
led_en : slbit; -- enable: led from rri
dat_en : slbit; -- enable: dsp_dat from rri
dp_en : slbit; -- enable: dsp_dp from rri
end record regs_type;
constant regs_init : regs_type := (
'0', -- rbsel
(others=>'0'), -- swi
(others=>'0'), -- btn
(others=>'0'), -- led
(others=>'0'), -- dsp_dat
(others=>'0'), -- dsp_dp
'0','0','0','0' -- (swi|led|dat|dp)_en
);
 
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
 
constant cntl_rbf_dat_en: integer := 11;
constant cntl_rbf_dp_en: integer := 10;
constant cntl_rbf_led_en: integer := 9;
constant cntl_rbf_swi_en: integer := 8;
subtype cntl_rbf_btn is integer range 3 downto 0;
subtype leddp_rbf_dsp_dp is integer range 11 downto 8;
subtype leddp_rbf_led is integer range 7 downto 0;
 
constant rbaddr_cntl: slv2 := "00"; -- 0 -/r/w
constant rbaddr_swi: slv2 := "01"; -- 1 -/r/w
constant rbaddr_leddp: slv2 := "10"; -- 2 -/r/w
constant rbaddr_dsp: slv2 := "11"; -- 3 -/r/w
 
signal HIO_SWI : slv8 := (others=>'0');
signal HIO_BTN : slv4 := (others=>'0');
signal HIO_LED : slv8 := (others=>'0');
signal HIO_DSP_DAT : slv16 := (others=>'0');
signal HIO_DSP_DP : slv4 := (others=>'0');
 
begin
 
HIO : s3_humanio
generic map (
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => HIO_SWI,
BTN => HIO_BTN,
LED => HIO_LED,
DSP_DAT => HIO_DSP_DAT,
DSP_DP => HIO_DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
proc_regs: process (CLK)
begin
 
if CLK'event and CLK='1' then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
 
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, LED, DSP_DAT, DSP_DP,
HIO_SWI, HIO_BTN, HIO_LED, HIO_DSP_DAT, HIO_DSP_DP)
 
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
 
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
begin
 
r := R_REGS;
n := R_REGS;
 
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
 
irbena := RB_MREQ.re or RB_MREQ.we;
 
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2) then
n.rbsel := '1';
end if;
 
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
 
case RB_MREQ.addr(1 downto 0) is
 
when rbaddr_cntl =>
irb_dout(cntl_rbf_dat_en) := r.dat_en;
irb_dout(cntl_rbf_dp_en) := r.dp_en;
irb_dout(cntl_rbf_led_en) := r.led_en;
irb_dout(cntl_rbf_swi_en) := r.swi_en;
irb_dout(cntl_rbf_btn) := HIO_BTN;
if RB_MREQ.we = '1' then
n.dat_en := RB_MREQ.din(cntl_rbf_dat_en);
n.dp_en := RB_MREQ.din(cntl_rbf_dp_en);
n.led_en := RB_MREQ.din(cntl_rbf_led_en);
n.swi_en := RB_MREQ.din(cntl_rbf_swi_en);
n.btn := RB_MREQ.din(cntl_rbf_btn);
end if;
when rbaddr_swi =>
irb_dout(HIO_SWI'range) := HIO_SWI;
if RB_MREQ.we = '1' then
n.swi := RB_MREQ.din(n.swi'range);
end if;
when rbaddr_leddp =>
irb_dout(leddp_rbf_dsp_dp) := HIO_DSP_DP;
irb_dout(leddp_rbf_led) := HIO_LED;
if RB_MREQ.we = '1' then
n.dsp_dp := RB_MREQ.din(leddp_rbf_dsp_dp);
n.led := RB_MREQ.din(leddp_rbf_led);
end if;
when rbaddr_dsp =>
irb_dout := HIO_DSP_DAT;
if RB_MREQ.we = '1' then
n.dsp_dat := RB_MREQ.din;
end if;
 
when others => null;
end case;
 
end if;
 
BTN <= HIO_BTN or r.btn;
if r.swi_en = '0' then
SWI <= HIO_SWI;
else
SWI <= r.swi;
end if;
 
if r.led_en = '0' then
HIO_LED <= LED;
else
HIO_LED <= r.led;
end if;
if r.dp_en = '0' then
HIO_DSP_DP <= DSP_DP;
else
HIO_DSP_DP <= r.dsp_dp;
end if;
if r.dat_en = '0' then
HIO_DSP_DAT <= DSP_DAT;
else
HIO_DSP_DAT <= r.dsp_dat;
end if;
N_REGS <= n;
 
RB_SRES <= rb_sres_init;
RB_SRES.ack <= irb_ack;
RB_SRES.busy <= irb_busy;
RB_SRES.err <= irb_err;
RB_SRES.dout <= irb_dout;
 
end process proc_next;
 
end syn;
/rtl/bplib/s3board/s3boardlib.vbom
1,4 → 1,4
# libs
../../vlib/slvtypes.vhd
../../vlib/rri/rrilib.vhd
../../vlib/rbus/rblib.vhd
s3boardlib.vhd
/rtl/bplib/s3board/s3_humanio_rbus.vbom
0,0 → 1,8
# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
s3boardlib.vbom
# components
s3_humanio.vbom
# design
s3_humanio_rbus.vhd
/rtl/bplib/s3board/s3boardlib.vhd
1,4 → 1,4
-- $Id: s3boardlib.vhd 336 2010-11-06 18:28:27Z mueller $
-- $Id: s3boardlib.vhd 351 2010-12-30 21:50:54Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
16,9 → 16,10
-- Description: S3BOARD components
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-30 351 1.3.2 use rblib; rename human s3_humanio_rri -> _rbus
-- 2010-11-06 336 1.3.1 rename input pin CLK -> I_CLK50
-- 2010-06-03 300 1.3 add s3_humanio_rri (now needs rrilib)
-- 2010-05-21 292 1.2.2 rename _PM1_ -> _FUSP_
40,7 → 41,7
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
use work.rrilib.all;
use work.rblib.all;
 
package s3boardlib is
 
118,7 → 119,7
);
end component;
 
component s3_humanio_rri is -- human i/o handling with rri intercept
component s3_humanio_rbus is -- human i/o handling /w rbus intercept
generic (
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8));
/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd
1,4 → 1,4
-- $Id: tb_s3board_fusp.vhd 336 2010-11-06 18:28:27Z mueller $
-- $Id: tb_s3board_fusp.vhd 351 2010-12-30 21:50:54Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
15,7 → 15,7
-- Module Name: tb_s3board_fusp - sim
-- Description: Test bench for s3board (base+fusp)
--
-- Dependencies: vlib/rri/tb/rritb_core
-- Dependencies: vlib/rlink/tb/tbcore_rlink_dcm
-- tb_s3board_core
-- vlib/serport/serport_uart_rxtx
-- s3board_fusp_aif [UUT]
23,9 → 23,10
-- To test: generic, any s3board_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-30 351 3.0 use rlink/tb now
-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50
-- 2010-05-21 292 1.0.3 rename _PM1_ -> _FUSP_
-- 2010-05-16 291 1.0.2 rename tb_s3board_usp->tb_s3board_fusp
40,8 → 41,8
use std.textio.all;
 
use work.slvtypes.all;
use work.rrilib.all;
use work.rritblib.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serport.all;
use work.s3boardlib.all;
use work.simlib.all;
103,7 → 104,7
 
begin
TBCORE : rritb_core
TBCORE : tbcore_rlink
generic map (
CLK_PERIOD => clock_period,
CLK_OFFSET => clock_offset,
/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom
4,14 → 4,14
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rri/rrilib.vhd
../../../vlib/rri/tb/rritblib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serport.vhd
../s3boardlib.vbom
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/rri/tb/rritb_core.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
tb_s3board_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
s3board_fusp_aif : s3board_fusp_dummy.vbom
/rtl/w11a/pdp11_core_rri.vhd File deleted
/rtl/w11a/pdp11_core_rri.vbom File deleted
/rtl/w11a/pdp11.vbom
1,5 → 1,5
# libs
../vlib/slvtypes.vhd
../ibus/iblib.vhd
../vlib/rri/rrilib.vhd
../vlib/rbus/rblib.vhd
pdp11.vhd
/rtl/w11a/pdp11_core_rbus.vbom
0,0 → 1,6
# libs
../vlib/slvtypes.vhd
../vlib/rbus/rblib.vhd
pdp11.vbom
# design
pdp11_core_rbus.vhd
/rtl/w11a/pdp11_mmu_sadr.vhd
1,4 → 1,4
-- $Id: pdp11_mmu_sadr.vhd 336 2010-11-06 18:28:27Z mueller $
-- $Id: pdp11_mmu_sadr.vhd 351 2010-12-30 21:50:54Z mueller $
--
-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
23,6 → 23,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-30 351 1.3.2 BUGFIX: fix sensitivity list of proc_eaddr
-- 2010-10-23 335 1.3.1 change proc_eaddr logic, shorten logic path
-- 2010-10-17 333 1.3 use ibus V2 interface
-- 2008-08-22 161 1.2.2 rename ubf_ -> ibf_; use iblib
213,7 → 214,7
-- and reduce the eaddr mux to a 4-input LUT. Last resort is a 2 cycle ibus
-- access with a state flop marking the 2nd cycle of a re/we transaction.
proc_eaddr: process (IB_MREQ, MODE, ASN)
proc_eaddr: process (IB_MREQ, MODE, ASN, R_IBSEL_DR, R_IBSEL_AR)
variable eaddr : slv6 := (others=>'0');
variable idr : slbit := '0';
variable iar : slbit := '0';
/rtl/w11a/tb/tb_pdp11_core.vbom File deleted
/rtl/w11a/tb/tb_pdp11_core_ssim.vbom File deleted
/rtl/w11a/tb/tbd_pdp11_core.vhd File deleted
/rtl/w11a/tb/tbd_pdp11_core.vbom File deleted
/rtl/w11a/tb/tb_pdp11_core_stim.dat File deleted
/rtl/w11a/tb/tb_pdp11_core.vhd File deleted
/rtl/w11a/tb/tb_pdp11core_ssim.vbom
0,0 → 1,4
# configure for _*sim case
tbd_pdp11core = tbd_pdp11core_ssim.vhd
tb_pdp11core.vbom
@top:tb_pdp11core
/rtl/w11a/tb/tbw.dat
1,12 → 1,5
# $Id: tbw.dat 81 2007-09-09 20:50:42Z mueller $
# $Id: tbw.dat 351 2010-12-30 21:50:54Z mueller $
#
[tb_rritba_pdp11core]
tb_rritba_stim = tb_rritba_pdp11core_stim.dat
[tb_rlink_tba_pdp11core]
tb_rlink_tba_stim = tb_rlink_tba_pdp11core_stim.dat
#
[tb_rripdp_pdp11core]
tb_rripdp_stim = tb_pdp11_core_stim.dat
#
[tb_rriext_pdp11core]
tb_rriext_fifo_rx = <fifo>
tb_rriext_fifo_tx = <fifo>
tb_rriext_conf = <null>
/rtl/w11a/tb/tb_pdp11core.vhd
0,0 → 1,672
-- $Id: tb_pdp11core.vhd 352 2011-01-02 13:01:37Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_pdp11core - sim
-- Description: Test bench for pdp11_core
--
-- Dependencies: simlib/simclk
-- tbd_pdp11core [UUT]
-- pdp11_intmap
--
-- To test: pdp11_core
--
-- Target Devices: generic
-- Tool versions: ghdl 0.18-0.29; ISim 11.3
--
-- Verified (with tb_pdp11core_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2010-12-30 351 - 0.29 - - u:ok
-- 2010-12-30 351 _ssim 0.29 12.1 M53d xc3s1000 u:ok
-- 2010-06-20 308 - 0.29 - - u:ok
-- 2009-11-22 252 - 0.26 - - u:ok
-- 2007-12-30 107 - 0.25 - - u:ok
-- 2007-10-26 92 _tsim 0.26 8.1.03 I27 xc3s1000 c:fail -> blog_ghdl
-- 2007-10-26 92 _tsim 0.26 9.2.02 J39 xc3s1000 d:ok (full tsim!)
-- 2007-10-26 92 _tsim 0.26 9.1 J30 xc3s1000 d:ok (full tsim!)
-- 2007-10-26 92 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok (full tsim!)
-- 2007-10-26 92 _fsim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-26 92 _ssim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-08 88 _ssim 0.18 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-08 88 _ssim 0.18 9.1 J30 xc3s1000 d:ok
-- 2007-10-08 88 _ssim 0.18 9.2.02 J39 xc3s1000 d:ok
-- 2007-10-07 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-10-07 88 _ssim 0.26 8.1 I24 xc3s1000 c:fail -> blog_webpack
-- 2007-10-07 88 - 0.26 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-01-02 352 1.3.1 rename .cpmon->.rlmon
-- 2010-12-30 351 1.3 rename tb_pdp11_core -> tb_pdp11core
-- 2010-06-20 308 1.2.2 add wibrb, ribr, wibr commands for ibr accesses
-- 2010-06-20 307 1.2.1 add CP_ADDR_racc, CP_ADDR_be to tbd interface
-- 2010-06-13 305 1.2 add CP_CNTL_rnum and CP_ADDR_...; emulate old
-- 'sta' behaviour with new 'stapc' command; rename
-- lal,lah -> wal,wah and implement locally; new
-- output format with cpfunc name
-- 2010-06-05 301 1.1.14 renamed .rpmon -> .rbmon
-- 2010-04-24 281 1.1.13 use direct instatiation for tbd_
-- 2009-11-28 253 1.1.12 add hack for ISim 11.3
-- 2009-05-10 214 1.1.11 add .scntl command (set/clear SB_CNTL bits)
-- 2008-08-29 163 1.1.10 allow, but ignore, the wtlam command
-- 2008-05-03 143 1.1.9 rename _cpursta->_cpurust
-- 2008-04-27 140 1.1.8 use cpursta interface, remove cpufail
-- 2008-04-19 137 1.1.7 use SB_CLKCYCLE now
-- 2008-03-24 129 1.1.6 CLK_CYCLE now 31 bits
-- 2008-03-02 121 1.1.5 redo sta,cont,wtgo commands; sta,cont now wait for
-- command completion, wtgo waits for CPU to halt.
-- added .cerr,.merr directive, check cmd(m)err state
-- added .sdef as ignored directive
-- 2008-02-24 119 1.1.4 added lah,rps,wps command
-- 2008-01-26 114 1.1.3 add handling of d=val,msk
-- 2008-01-06 111 1.1.2 remove .eireq, EI's now handled in tbd_pdp11_core
-- 2007-10-26 92 1.0.2 use DONE timestamp at end of execution
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-02 79 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.pdp11_sim.all;
use work.pdp11.all;
 
entity tb_pdp11core is
end tb_pdp11core;
 
architecture sim of tb_pdp11core is
 
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal UNUSEDSIGNAL : slbit := '0'; -- FIXME: hack to make ISim 11.3 happy
signal CP_CNTL_req : slbit := '0';
signal CP_CNTL_func : slv5 := (others=>'0');
signal CP_CNTL_rnum : slv3 := (others=>'0');
signal CP_ADDR_addr : slv22_1 := (others=>'0');
signal CP_ADDR_racc : slbit := '0';
signal CP_ADDR_be : slv2 := "11";
signal CP_ADDR_ena_22bit : slbit := '0';
signal CP_ADDR_ena_ubmap : slbit := '0';
signal CP_DIN : slv16 := (others=>'0');
signal CP_STAT_cmdbusy : slbit := '0';
signal CP_STAT_cmdack : slbit := '0';
signal CP_STAT_cmderr : slbit := '0';
signal CP_STAT_cmdmerr : slbit := '0';
signal CP_STAT_cpugo : slbit := '0';
signal CP_STAT_cpustep : slbit := '0';
signal CP_STAT_cpuhalt : slbit := '0';
signal CP_STAT_cpurust : slv4 := (others=>'0');
signal CP_DOUT : slv16 := (others=>'0');
 
signal CLK_STOP : slbit := '0';
 
signal R_CHKDAT : slv16 := (others=>'0');
signal R_CHKMSK : slv16 := (others=>'0');
signal R_CHKREQ : slbit := '0';
 
signal R_WAITCMD : slbit := '0';
signal R_WAITSTEP : slbit := '0';
signal R_WAITGO : slbit := '0';
signal R_WAITOK : slbit := '0';
signal R_CP_STAT : cp_stat_type := cp_stat_init;
signal R_CP_DOUT : slv16 := (others=>'0');
begin
 
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_CYCLE => SB_CLKCYCLE,
CLK_STOP => CLK_STOP
);
 
UUT: entity work.tbd_pdp11core
port map (
CLK => CLK,
RESET => RESET,
CP_CNTL_req => CP_CNTL_req,
CP_CNTL_func => CP_CNTL_func,
CP_CNTL_rnum => CP_CNTL_rnum,
CP_ADDR_addr => CP_ADDR_addr,
CP_ADDR_racc => CP_ADDR_racc,
CP_ADDR_be => CP_ADDR_be,
CP_ADDR_ena_22bit => CP_ADDR_ena_22bit,
CP_ADDR_ena_ubmap => CP_ADDR_ena_ubmap,
CP_DIN => CP_DIN,
CP_STAT_cmdbusy => CP_STAT_cmdbusy,
CP_STAT_cmdack => CP_STAT_cmdack,
CP_STAT_cmderr => CP_STAT_cmderr,
CP_STAT_cmdmerr => CP_STAT_cmdmerr,
CP_STAT_cpugo => CP_STAT_cpugo,
CP_STAT_cpustep => CP_STAT_cpustep,
CP_STAT_cpuhalt => CP_STAT_cpuhalt,
CP_STAT_cpurust => CP_STAT_cpurust,
CP_DOUT => CP_DOUT
);
proc_stim: process
file ifile : text open read_mode is "tb_pdp11core_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable idummy : integer := 0;
variable dcycle : integer := 0;
variable irqline : integer := 0;
variable ireq : boolean := false;
variable ifunc : slv5 := (others=>'0');
variable irnum : slv3 := (others=>'0');
variable idin : slv16 := (others=>'0');
variable imsk : slv16 := (others=>'1');
variable ichk : boolean := false;
variable idosta: slbit := '0';
 
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable rind : integer := 0;
variable nblk : integer := 0;
variable xmicmd : string(1 to 3) := (others=>' ');
variable iwtstp : boolean := false;
variable iwtgo : boolean := false;
variable icerr : integer := 0;
variable imerr : integer := 0;
variable to_cmd : integer := 50;
variable to_stp : integer := 100;
variable to_go : integer := 5000;
variable ien : slbit := '0';
variable ibit : integer := 0;
variable imemi : boolean := false;
variable ioff : slv6 := (others=>'0');
variable idoibr : boolean := false;
 
variable r_addr : slv22_1 := (others=>'0');
variable r_ena_22bit : slbit := '0';
variable r_ena_ubmap : slbit := '0';
variable r_ibrbase : slv(c_ibrb_ibf_base) := (others=>'0');
variable r_ibrbe : slv2 := (others=>'0');
 
begin
 
SB_CNTL <= (others=>'L');
 
wait for clock_offset - setup_time;
 
RESET <= '1';
wait for clock_period;
 
RESET <= '0';
wait for 9*clock_period;
file_loop: while not endfile(ifile) loop
 
-- this logic is a quick hack to implement the 'stapc' command
if idosta = '0' then
readline (ifile, iline);
 
iwtstp := false;
iwtgo := false;
if nblk>0 and -- outstanding [rw]mi lines ?
iline'length>=3 and -- and 3 leading blanks
iline(iline'left to iline'left+2)=" " then
nblk := nblk - 1; -- than fill [rw]mi command in again
iline(iline'left to iline'left+2) := xmicmd;
end if;
readcomment(iline, ok);
next file_loop when ok;
 
readword(iline, dname, ok);
 
else
idosta := '0';
dname := "sta ";
ok := true;
end if;
 
if ok then
 
case dname is
when "rsp " => dname := "rr6 "; -- rsp -> rr6
when "rpc " => dname := "rr7 "; -- rpc -> rr7
when "wsp " => dname := "wr6 "; -- wsp -> wr6
when "wpc " => dname := "wr7 "; -- wpc -> wr7
when others => null;
end case;
rind := character'pos(dname(3)) - character'pos('0');
if (dname(1)='r' or dname(1)='w') and -- check for [rw]r[0-7]
dname(2)='r' and
(rind>=0 and rind<=7) then
dname(3) := '|'; -- replace with [rw]r|
end if;
 
if dname(1) = '.' then
case dname is
when ".mode " => -- .mode
readword_ea(iline, dname);
assert dname="pdpcp "
report "assert .mode == pdpcp" severity failure;
 
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
 
RESET <= '0';
wait for 9*clock_period;
 
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
 
when ".tocmd" => -- .tocmd
read_ea(iline, idelta);
to_cmd := idelta;
 
when ".tostp" => -- .tostp
read_ea(iline, idelta);
to_stp := idelta;
 
when ".togo " => -- .togo
read_ea(iline, idelta);
to_go := idelta;
 
when ".sdef " => -- .sdef (ignore it)
readempty(iline);
when ".cerr " => -- .cerr
read_ea(iline, icerr);
when ".merr " => -- .merr
read_ea(iline, imerr);
 
when ".anena" => -- .anena (ignore it)
readempty(iline);
when ".rlmon" => -- .rlmon (ignore it)
readempty(iline);
when ".rbmon" => -- .rbmon (ignore it)
readempty(iline);
 
when ".scntl" => -- .scntl
read_ea(iline, ibit);
read_ea(iline, ien);
assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high)
report "assert bit number in range of SB_CNTL"
severity failure;
if ien = '1' then
SB_CNTL(ibit) <= 'H';
else
SB_CNTL(ibit) <= 'L';
end if;
 
when others => -- bad directive
write(oline, string'("?? unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
 
testempty_ea(iline);
next file_loop;
 
else
 
ireq := true;
ifunc := c_cpfunc_noop;
irnum := "000";
ichk := false;
idin := (others=>'0');
imsk := (others=>'1');
imemi := false;
idoibr := false;
case dname is
when "brm " => -- brm
read_ea(iline, nblk);
xmicmd := "rmi";
next file_loop;
when "bwm " => -- bwm
read_ea(iline, nblk);
xmicmd := "wmi";
next file_loop;
 
when "rr| " => -- rr[0-7]
ifunc := c_cpfunc_rreg;
irnum := conv_std_logic_vector(rind, 3);
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
 
when "wr| " => -- wr[0-7]
ifunc := c_cpfunc_wreg;
irnum := conv_std_logic_vector(rind, 3);
readoct_ea(iline, idin);
 
-- Note: there are no field definitions for wal, wah, wibrb because
-- there is no corresponding cp command. Therefore the
-- rbus field definitions are used here
when "wal " => -- wal
readoct_ea(iline, idin);
r_addr := (others=>'0'); -- write to al clears ah !!
r_ena_22bit := '0';
r_ena_ubmap := '0';
r_addr(c_al_rbf_addr) := idin(c_al_rbf_addr);
testempty_ea(iline);
next file_loop;
when "wah " => -- wah
readoct_ea(iline, idin);
r_addr(21 downto 16) := idin(c_ah_rbf_addr);
r_ena_22bit := idin(c_ah_rbf_ena_22bit);
r_ena_ubmap := idin(c_ah_rbf_ena_ubmap);
testempty_ea(iline);
next file_loop;
 
when "wibrb " => -- wibrb
readoct_ea(iline, idin);
r_ibrbase := idin(c_ibrb_ibf_base);
if idin(c_ibrb_ibf_be) /= "00" then
r_ibrbe := idin(c_ibrb_ibf_be);
else
r_ibrbe := "11";
end if;
testempty_ea(iline);
next file_loop;
 
when "rm " => -- rm
ifunc := c_cpfunc_rmem;
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "rmi " => -- rmi
ifunc := c_cpfunc_rmem;
imemi := true;
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
 
when "wm " => -- wm
ifunc := c_cpfunc_wmem;
readoct_ea(iline, idin);
when "wmi " => -- wmi
ifunc := c_cpfunc_wmem;
imemi := true;
readoct_ea(iline, idin);
 
when "ribr " => -- ribr
ifunc := c_cpfunc_rmem;
idoibr := true;
readoct_ea(iline, ioff);
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "wibr " => -- wibr
ifunc := c_cpfunc_wmem;
idoibr := true;
readoct_ea(iline, ioff);
readoct_ea(iline, idin);
 
when "rps " => -- rps
ifunc := c_cpfunc_rpsw;
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "wps " => -- wps
ifunc := c_cpfunc_wpsw;
readoct_ea(iline, idin);
 
-- Note: in old version 'sta addr' was an atomic operation, loading
-- the pc and starting the cpu. Now this is action is two step
-- first a wpc followed by a 'sta'.
when "stapc " => -- stapc
ifunc := c_cpfunc_wreg;
irnum := c_gpr_pc;
readoct_ea(iline, idin);
idosta := '1'; -- request 'sta' to be done next
 
when "sta " => -- sta
ifunc := c_cpfunc_sta;
when "sto " => -- sto
ifunc := c_cpfunc_sto;
when "cont " => -- cont
ifunc := c_cpfunc_cont;
when "step " => -- step
ifunc := c_cpfunc_step;
iwtstp := true;
when "rst " => -- rst
ifunc := c_cpfunc_rst;
 
when "wtgo " => -- wtgo
iwtgo := true;
ireq := false; -- no cp request !
 
when "wtlam " => -- wtlam (ignore it)
readempty(iline);
next file_loop;
 
when others => -- bad directive
write(oline, string'("?? unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
end if;
testempty_ea(iline);
 
end if;
if idoibr then
CP_ADDR_addr(15 downto 13) <= "111";
CP_ADDR_addr(c_ibrb_ibf_base) <= r_ibrbase;
CP_ADDR_addr(5 downto 1) <= ioff(5 downto 1);
CP_ADDR_racc <= '1';
CP_ADDR_be <= r_ibrbe;
CP_ADDR_ena_22bit <= '0';
CP_ADDR_ena_ubmap <= '0';
else
CP_ADDR_addr <= r_addr;
CP_ADDR_racc <= '0';
CP_ADDR_be <= "11";
CP_ADDR_ena_22bit <= r_ena_22bit;
CP_ADDR_ena_ubmap <= r_ena_ubmap;
end if;
 
if ireq then
CP_CNTL_req <= '1';
CP_CNTL_func <= ifunc;
CP_CNTL_rnum <= irnum;
end if;
if ichk then
CP_DIN <= (others=>'0');
R_CHKDAT <= idin;
R_CHKMSK <= imsk;
R_CHKREQ <= '1';
else
CP_DIN <= idin;
R_CHKREQ <= '0';
end if;
R_WAITCMD <= '0';
R_WAITSTEP <= '0';
R_WAITGO <= '0';
if iwtgo then
idelta := to_go;
R_WAITGO <= '1';
elsif iwtstp then
idelta := to_stp;
R_WAITSTEP <= '1';
else
idelta := to_cmd;
R_WAITCMD <= '1';
end if;
 
wait for clock_period;
CP_CNTL_req <= '0';
 
dcycle := 1;
while idelta>0 and R_WAITOK='0' loop
wait for clock_period;
dcycle := dcycle + 1;
idelta := idelta - 1;
end loop;
 
if imemi then -- rmi or wmi seen ? then inc ar
r_addr := unsigned(r_addr) + 1;
end if;
write(oline, dcycle, right, 4);
write(oline, string'(" "));
if ireq then
case ifunc is
when c_cpfunc_rreg => write(oline, string'("rreg"));
when c_cpfunc_wreg => write(oline, string'("wreg"));
when c_cpfunc_rpsw => write(oline, string'("rpsw"));
when c_cpfunc_wpsw => write(oline, string'("wpsw"));
when c_cpfunc_rmem =>
if idoibr then
write(oline, string'("ribr"));
else
write(oline, string'("rmem"));
end if;
when c_cpfunc_wmem =>
if idoibr then
write(oline, string'("wibr"));
else
write(oline, string'("wmem"));
end if;
when c_cpfunc_sta => write(oline, string'("sta "));
when c_cpfunc_sto => write(oline, string'("sto "));
when c_cpfunc_cont => write(oline, string'("cont"));
when c_cpfunc_step => write(oline, string'("step"));
when c_cpfunc_rst => write(oline, string'("rst "));
when others =>
write(oline, string'("?"));
writeoct(oline, ifunc, right, 2);
write(oline, string'("?"));
end case;
writeoct(oline, irnum, right, 2);
writeoct(oline, idin, right, 8);
else
write(oline, string'("---- - ------"));
end if;
 
write(oline, R_CP_STAT.cmdbusy, right, 3);
write(oline, R_CP_STAT.cmdack, right, 2);
write(oline, R_CP_STAT.cmderr, right, 2);
write(oline, R_CP_STAT.cmdmerr, right, 2);
writeoct(oline, R_CP_DOUT, right, 8);
write(oline, R_CP_STAT.cpugo, right, 3);
write(oline, R_CP_STAT.cpustep, right, 2);
write(oline, R_CP_STAT.cpuhalt, right, 2);
writeoct(oline, R_CP_STAT.cpurust, right, 3);
 
if R_WAITOK = '1' then
if R_CP_STAT.cmderr='1' or icerr=1 then
if R_CP_STAT.cmderr='1' and icerr=0 then
write(oline, string'(" FAIL CMDERR"));
elsif R_CP_STAT.cmderr='1' and icerr=1 then
write(oline, string'(" CHECK CMDERR SEEN"));
elsif R_CP_STAT.cmderr='0' and icerr=1 then
write(oline, string'(" FAIL CMDERR EXPECTED,MISSED"));
end if;
elsif R_CP_STAT.cmdmerr='1' or imerr=1 then
if R_CP_STAT.cmdmerr='1' and imerr=0 then
write(oline, string'(" FAIL CMDMERR"));
elsif R_CP_STAT.cmdmerr='1' and imerr=1 then
write(oline, string'(" CHECK CMDMERR SEEN"));
elsif R_CP_STAT.cmdmerr='0' and imerr=1 then
write(oline, string'(" FAIL CMDMERR EXPECTED,MISSED"));
end if;
elsif R_CHKREQ='1' then
if unsigned((R_CP_DOUT xor R_CHKDAT) and (not R_CHKMSK))=0 then
write(oline, string'(" CHECK OK"));
else
write(oline, string'(" CHECK FAILED, d="));
writeoct(oline, R_CHKDAT, right, 7);
if unsigned(R_CHKMSK)/=0 then
write(oline, string'(","));
writeoct(oline, R_CHKMSK, right, 7);
end if;
end if;
end if;
 
if iwtgo then
write(oline, string'(" WAIT GO OK "));
elsif iwtstp then
write(oline, string'(" WAIT STEP OK"));
end if;
else
write(oline, string'(" WAIT FAILED (will reset)"));
RESET <= '1';
wait for clock_period;
 
RESET <= '0';
wait for 9*clock_period;
end if;
writeline(output, oline);
end loop;
wait for 4*clock_period;
CLK_STOP <= '1';
 
writetimestamp(oline, SB_CLKCYCLE, ": DONE ");
writeline(output, oline);
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
 
end process proc_stim;
proc_moni: process
begin
 
loop
wait until CLK'event and CLK='1';
wait for c2out_time;
 
R_WAITOK <= '0';
if R_WAITCMD = '1' then
if CP_STAT_cmdack = '1' then
R_WAITOK <= '1';
end if;
elsif R_WAITGO = '1' then
if CP_STAT_cmdbusy='0' and CP_STAT_cpugo='0' then
R_WAITOK <= '1';
end if;
elsif R_WAITSTEP = '1' then
if CP_STAT_cmdbusy='0' and CP_STAT_cpustep='0' then
R_WAITOK <= '1';
end if;
end if;
R_CP_STAT.cmdbusy <= CP_STAT_cmdbusy;
R_CP_STAT.cmdack <= CP_STAT_cmdack;
R_CP_STAT.cmderr <= CP_STAT_cmderr;
R_CP_STAT.cmdmerr <= CP_STAT_cmdmerr;
R_CP_STAT.cpugo <= CP_STAT_cpugo;
R_CP_STAT.cpustep <= CP_STAT_cpustep;
R_CP_STAT.cpuhalt <= CP_STAT_cpuhalt;
R_CP_STAT.cpurust <= CP_STAT_cpurust;
R_CP_DOUT <= CP_DOUT;
end loop;
end process proc_moni;
end sim;
/rtl/w11a/tb/tb_pdp11core.vbom
0,0 → 1,11
# libs
../../vlib/slvtypes.vhd
../../vlib/simlib/simlib.vhd
../../vlib/simlib/simbus.vhd
../pdp11_sim.vhd
../pdp11.vbom
# components
../../vlib/simlib/simclk.vbom
tbd_pdp11core : tbd_pdp11core.vbom
# design
tb_pdp11core.vhd
/rtl/w11a/tb/tb_pdp11core_stim.dat
0,0 → 1,8569
# $Id: tb_pdp11core_stim.dat 351 2010-12-30 21:50:54Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2010-06-20 308 2.2.1 add wibrb, ribr, wibr based tests
# 2010-06-13 305 2.2 adopt to new rri address and function semantics
# 2009-11-22 252 2.1.14 change SSR0 expects, adapt to ECO-021.
# 2009-05-02 211 2.1.13 add nop after spl in pirq test, 11/70 spl now !!
# 2008-08-29 163 2.1.12 add wtlam to harvest attn after sto in test 13
# 2008-04-27 139 2.1.11 adapt expected ssr1 after mtpi/d after ECO-009 fix
# 2008-03-15 125 2.1.10 exclude some tests from simh ([[off/on]]
# 2008-03-09 124 2.1.9 fixed addr-mode in code 34, shifted 47+50
# 2008-03-02 121 2.1.8 add meory access error tests
# add Code 13, testing WAIT and bwm/brm while CPU runs
# 2008-02-24 119 2.1.7 add tests for lah,rps,wps; use rps,wps
# use 22bit mode for nxm test (now needed!)
# 2008-02-23 118 2.1.6 for nxm tests use mmu and page below i/o-page
# in code 35 use access to 160000 to test trap
# 2007-09-23 84 2.1.5 use .reset to make it re-executable
# 2007-09-16 83 2.1.4 clear CPUERR in beginning of test 20 {runs in FPGA}
# 2007-09-02 79 2.1.3 add .mode command (for pi_rri use)
# 2007-08-25 75 2.1.2 add .cpmon/.rpmon (for use with rri)
# 2007-08-16 74 2.1.1 adapt to changed LAM handling
# 2007-08-12 73 2.1 use wtgo (revised conv_stim)
# 2007-08-03 71 2.0 convert to command mode with conv_stim
# 2007-07-08 65 1.2 removed 1st 'delay' parameter; use .to_(cmd|stp|go)
# 2007-06-10 51 1.1 consolidate w11a test bench
# 2007-05-13 29 1.0 initial version (imported)
#
.mode pdpcp
.tocmd 50
.tostp 100
.togo 5000
.rlmon 0
.rbmon 0
.scntl 13 0
#
.reset
.wait 10
.anena 1
#
C "Code 0" Some elementary initial tests
C write registers
#
wr0 000001 -- set r0,..,r7
wr1 000101 --
wr2 000201 --
wr3 000301 --
wr4 000401 --
wr5 000501 --
wsp 000601 --
wpc 000701 --
#
C read registers
#
rr0 d=000001 -- ! r0
rr1 d=000101 -- ! r1
rr2 d=000201 -- ! r2
rr3 d=000301 -- ! r3
rr4 d=000401 -- ! r4
rr5 d=000501 -- ! r5
rsp d=000601 -- ! sp
rpc d=000701 -- ! pc
#
C write memory
#
wal 002000 -- write mem(2000,...,2006)
bwm 4
007700 --
007710 --
007720 --
007730 --
#
C read memory
#
wal 002000
brm 4
d=007700 -- ! mem(2000)
d=007710 -- ! mem(2002)
d=007720 -- ! mem(2004)
d=007730 -- ! mem(2006)
#
C write/read PSW via various mechanisms
C via wps/rps
#
wps 000017
rps d=000017
wps 000000
rps d=000000
#
C via 16bit cp addressing (wal 177776)
#
wal 177776
wm 000017 -- set all cc flags in psw
rm d=000017 -- ! psw
rps d=000017
wm 000000 -- clear psw
rm d=000000 -- ! psw
rps d=000000
#
C via 22bit cp addressing (wal 177776; wah 177)
#
wal 177776
wah 000177
wm 000017 -- set all cc flags in psw
rm d=000017 -- ! psw
rps d=000017
wm 000000 -- clear psw
rm d=000000 -- ! psw
rps d=000000
#
C via ibr (ibrb 177700)
#
wibrb 177700
wibr 76 000017 -- set all cc flags in psw
ribr 76 d=000017 -- ! psw
rps d=000017
wibr 76 000000 -- set all cc flags in psw
ribr 76 d=000000 -- ! psw
rps d=000000
#
C write register set 1, sm,um stack
#
wps 004000 -- psw: cm=kernel, set=1
wr0 010001 -- set r0,..,r5 [[r10]]
wr1 010101 -- [[r11]]
wr2 010201 -- [[r12]]
wr3 010301 -- [[r13]]
wr4 010401 -- [[r14]]
wr5 010501 -- [[r15]]
wps 044000 -- psw: cm=super(01),set=1
wsp 010601 -- set ssp [[ssp]]
wps 144000 -- psw: cm=user(11),set=1
wsp 110601 -- set usp [[usp]]
#
C read all registers set 0/1, km,sm,um stack
#
wps 000000 -- psw: cm=kernel(00),set=0
rr0 d=000001 -- ! r0
rr1 d=000101 -- ! r1
rr2 d=000201 -- ! r2
rr3 d=000301 -- ! r3
rr4 d=000401 -- ! r4
rr5 d=000501 -- ! r5
rsp d=000601 -- ! ksp
rpc d=000701 -- ! pc
wps 040000 -- psw: cm=super(01),set=0
rsp d=010601 -- ! ssp [[ssp]]
wps 140000 -- psw: cm=user(11),set=0
rsp d=110601 -- ! usp [[usp]]
wps 144000 -- psw: cm=user(11),set=1
rr0 d=010001 -- ! r0 [[r10]]
rr1 d=010101 -- ! r1 [[r11]]
rr2 d=010201 -- ! r2 [[r12]]
rr3 d=010301 -- ! r3 [[r13]]
rr4 d=010401 -- ! r4 [[r14]]
rr5 d=010501 -- ! r5 [[r15]]
#
C write IB space: MMU SAR supervisor mode (16 bit regs)
#
wal 172240 -- set first three SM I space address regs
bwm 3
012340
012342
012344
#
C read IB space: MMU SAR supervisor mode (16 bit regs)
#
wal 172240 -- ! verify first three SM I space address regs
brm 3
d=012340
d=012342
d=012344
#
C read IB space via ibr: MMU SAR supervisor mode (16 bit regs)
#
wibrb 172200
ribr 40 d=012340
ribr 42 d=012342
ribr 44 d=012344
#
C byte write IB space via ibr: MMU SAR supervisor mode (16 bit regs)
#
wibrb 172201 -- write low byte
wibr 40 177000
wibr 42 177002
wibr 44 177004
wal 172240 -- ! verify
brm 3
d=012000
d=012002
d=012004
#
wibrb 172202 -- write high byte
wibr 40 000377
wibr 42 022377
wibr 44 044377
wal 172240 -- ! verify
brm 3
d=000000
d=022002
d=044004
#
wibrb 172203 -- write high and low byte (both be set)
wibr 40 012340
wibr 42 012342
wibr 44 012344
wal 172240 -- ! verify
brm 3
d=012340
d=012342
d=012344
#
#[[off]] - this tests cp not the cpu - meaningless in simh
#
C test access error handling to memory (use 17740000)
C with wm/rm
#
wal 140000
wah 000177
.merr 1
.sdef s=10000001
wm 000000
rm d=-
.merr 0
.sdef s=00000000,01110000
#
C with bwm/brm
#
wal 140000
wah 000177
.merr 1
.sdef s=10000001
bwm 2
000000
000000
.merr 0
.sdef s=00000000,01110000
#
wal 140000
wah 000177
.merr 1
.sdef s=10000001
brm 2
d=-
d=-
.merr 0
.sdef s=00000000,01110000
#
C test access error handling to IB space (use 00160000)
C with wm/rm
wal 160000
.merr 1
.sdef s=10000001
wm 000000
rm d=-
.merr 0
.sdef s=00000000,01110000
C with bwm/brm
#
wal 160000
.merr 1
.sdef s=10000001
bwm 2
000000
000000
.merr 0
.sdef s=00000000,01110000
#
wal 160000
.merr 1
.sdef s=10000001
brm 2
d=-
d=-
.merr 0
.sdef s=00000000,01110000
#[[on]]
#-----------------------------------------------------------------------------
C Setup trap catchers
#
wal 000004 -- vectors: 4...34 (trap catcher)
bwm 14
000006 -- PC:06 ; vector 4
000000 -- PS:0
000012 -- PC:12 ; vector 10
000000 -- PS:0
000016 -- PC:16 ; vector 14 (T bit; BPT)
000000 -- PS:0
000022 -- PC:22 ; vector 20 (IOT)
000000 -- PS:0
000026 -- PC:26 ; vector 24 (Power fail, not used)
000000 -- PS:0
000032 -- PC:32 ; vector 30 (EMT)
000000 -- PS:0
000036 -- PC:36 ; vector 34 (TRAP)
000000 -- PS:0
wal 000240 -- vectors: 240,244,250 (trap catcher)
bwm 6
000242 -- PC:242 ; vector 240 (PIRQ)
000000 -- PS:0
000246 -- PC:246 ; vector 244 (FPU)
000000 -- PS:0
000252 -- PC:252 ; vector 250 (MMU)
000000 -- PS:0
#
C Setup MMU
#
wal 172300 -- kernel I space DR
bwm 8
077406 -- slf=127; ed=0(up); acf=6(w/r)
077406 -- slf=127; ed=0(up); acf=6(w/r)
077406 -- slf=127; ed=0(up); acf=6(w/r)
077406 -- slf=127; ed=0(up); acf=6(w/r)
077406 -- slf=127; ed=0(up); acf=6(w/r)
077406 -- slf=127; ed=0(up); acf=6(w/r)
077406 -- slf=127; ed=0(up); acf=6(w/r)
077406 -- slf=127; ed=0(up); acf=6(w/r)
wal 172340 -- kernel I space AR
bwm 8
000000 -- 0
000200 -- 200 020000 base
000400 -- 400 040000 base
000600 -- 600 060000 base
001000 -- 1000 100000 base
001200 -- 1200 120000 base
001400 -- 1400 140000 base
177600 -- 176000 (map to I/O page)
#-----------------------------------------------------------------------------
C Setup code 1 [base 2100] (very basics: cont,start; 'simple' instructions)
#
wal 002100 -- code test 1: (sec+clc+halt)
bwm 3
000261 -- sec
000250 -- cln
000000 -- halt
#-----
wal 002120 -- code test 2: (4 *inc R2, starting from -2)
bwm 5
005202 -- inc r2
005202 -- inc r2
005202 -- inc r2
005202 -- inc r2
#2130
000000 -- halt
#-----
wal 002140 -- code test 3: (dec r3; bne -2; halt)
bwm 3
005303 -- dec r3
001376 -- bne -2
000000 -- halt
#-----
wal 002160 -- code test 4: (inc r1; sob r0,-2; halt)
bwm 3
005201 -- inc r1
077002 -- sob r0,-2
000000 -- halt
#
C Exec code 1 (very basics: cont,start; 'simple' instructions)
C Exec test 1.1 (sec+clc+halt)
#
wpc 002100 -- pc=2100
wps 000010 -- psw: set N flag
cont -- cont @ 2100
wtgo
rpc d=002106 -- ! pc
rps d=000001 -- ! N cleared, C set now
#
C Exec test 1.2 (4 *inc R2, starting from -2)
#
wr2 177776 -- r2=-2
stapc 002120 -- start @ 2120
wtgo
rr2 d=000002 -- ! r2=2
rpc d=002132 -- ! pc
#
C Exec test 1.3 (dec r3; bne -2; halt)
#
wr3 000002 -- r3=2
stapc 002140 -- start @ 2140
wtgo
rr3 d=000000 -- ! r3=0
rpc d=002146 -- ! pc
#
C Exec test 1.4 (inc r1; sob r0,-2; halt)
#
wr0 000002 -- r0=2
wr1 000000 -- r1=0
stapc 002160 -- start @ 2160
wtgo
rr0 d=000000 -- ! r0=0
rr1 d=000002 -- ! r1=2
rpc d=002166 -- ! pc
#-----------------------------------------------------------------------------
C Setup code 2 [base 2200] (bpt against trap catcher @14)
#
wal 002200 -- code:
bwm 4
000257 -- cl(nzvc)
000261 -- sec
000003 -- bpt
000000 -- halt
#
C Exec code 2 (bpt against trap catcher @14)
#
wsp 001400 -- sp=1400
stapc 002200 -- start @ 2200
wtgo
rsp d=001374 -- ! sp
rpc d=000020 -- ! pc
wal 001374
brm 2
d=002206 -- ! (sp) old pc
d=000341 -- ! 2(sp) old ps
#-----------------------------------------------------------------------------
C Setup code 3 [base 2300] (bpt against trap handler doing inc r0; rtt)
#
wal 002300 -- code:
bwm 4
000257 -- cl(nzvc)
000003 -- bpt
005201 -- inc r1
000000 -- halt
wal 000014 -- vector: 14
bwm 2
002320 -- PC:2320
000002 -- PS:2
wal 002320 -- code (trap 14):
bwm 3
005200 -- inc r0
000006 -- rtt
000000 -- halt
#
C Exec code 3 (bpt against trap handler doing inc r0; rtt)
#
wr0 000000 -- r0=0
wr1 000000 -- r1=0
wsp 001400 -- sp=1400
stapc 002300 -- start @ 2300
wtgo
rr0 d=000001 -- ! r0
rr1 d=000001 -- ! r1
rsp d=001400 -- ! sp
rpc d=002310 -- ! pc
#-----------------------------------------------------------------------------
C Setup code 4 [base 2400] (enable T-trap on handler of code 3; run 2* inc r1)
#
wal 002400
bwm 4
000006 -- rtt
005201 -- inc r1
005201 -- inc r1
000000 -- halt
#
C Exec code 4 (enable T-trap on handler of code 3; run 2* inc r1)
#
wr0 000000 -- r0=0
wr1 000000 -- r1=0
wsp 001374 -- sp=1374
wal 001374 -- setup stack with rtt return frame setting T flag
bwm 2
002402 -- start address
000020 -- set T flag in PSW
stapc 002400 -- start @ 2400 -> rtt -> 2402 from stack
wtgo
rr0 d=000002 -- ! r0
rr1 d=000002 -- ! r1
rsp d=001400 -- ! sp
rpc d=002410 -- ! pc
#
rst -- console reset (to clear T flag)
wal 000014 -- vector: 14 -> trap catcher again
bwm 2
000016 -- PC:16
000000 -- PS:0
#-----------------------------------------------------------------------------
C Setup code 5 [base 2500] (srcr modes: mov xxx,rn: (r0),(r0)+,-(r0),@(r0))
#
wal 002500 -- code:
bwm 6
011001 -- mov (r0),r1
012002 -- mov (r0)+,r2
012003 -- mov (r0)+,r3
014004 -- mov -(r0),r4
013005 -- mov @(r0)+,r5
000000 -- halt
#
wal 002540 -- data:
bwm 2
000070 --
002550 --
wal 002550 -- data:
bwm 2
000072 --
000074 --
#
C Exec code 5 (srcr modes: mov xxx,rn: (r0),(r0)+,-(r0),@(r0))
#
wr0 002540 -- r0=2540
wr1 000000 -- r1=0
wr2 000000 -- r2=0
wr3 000000 -- r3=0
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 002500 -- start @ 2500
wtgo
rr0 d=002544 -- ! r0
rr1 d=000070 -- ! r1
rr2 d=000070 -- ! r2
rr3 d=002550 -- ! r3
rr4 d=002550 -- ! r4
rr5 d=000072 -- ! r5
rsp d=001400 -- ! sp
rpc d=002514 -- ! pc
#-----------------------------------------------------------------------------
C Setup code 6 [base 2600] (srcr modes: mov xxx,rn: x(r0),@x(r0), pc modes)
#
wal 002600 -- code:
bwm 11
016001 -- mov 2(r0),r1
000002
017002 -- mov @2(r0),r2
000002
012703 -- mov (pc)+,r3 ; #377
000377
013704 -- mov @(pc)+,r4 ; @#2552 (in previous code !)
002552
#2620
112705 -- movb (pc)+,r5 ; #377
000377
000000 -- halt
#
C Exec code 6 (srcr modes: mov xxx,rn: x(r0),@x(r0), pc modes)
#
wr0 002540 -- r0=2540 (in previous code !)
wr1 000000 -- r1=0
wr2 000000 -- r2=0
wr3 000000 -- r3=0
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 002600 -- start @ 2600
wtgo
rr0 d=002540 -- ! r0
rr1 d=002550 -- ! r1
rr2 d=000072 -- ! r2
rr3 d=000377 -- ! r3
rr4 d=000074 -- ! r4
rr5 d=177777 -- ! r5
rsp d=001400 -- ! sp
rpc d=002626 -- ! pc
#-----------------------------------------------------------------------------
C Setup code 7 [base 2700] (dstw modes: mov rn,xxx: all non-r modes)
#
wal 002700 -- code:
bwm 18
012710 -- mov #110,(r0) (to 2750)
000110
012721 -- mov #120,(r1)+ (to 2752)
000120
012732 -- mov #130,@(r2)+ (to 2754)
000130
012743 -- mov #140,-(r3) (to 2756)
000140
#2720
012754 -- mov #150,@-(r4) (to 2760)
000150
012760 -- mov #160,12(r0) (to 2762)
000160
000012
012770 -- mov #170,@24(r0) (to 2764)
000170
000024
#2740
010546 -- mov r5,-(r6)
000000 -- halt
#
wal 002770 -- data:
bwm 3
002754 -- mem(2770)=2754
002760 -- mem(2772)=2760
002764 -- mem(2774)=2764
#
C Exec code 7 (dstw modes: mov rn,xxx: all non-r modes)
#
wr0 002750 -- r0=2750
wr1 002752 -- r1=2752
wr2 002770 -- r2=2770
wr3 002760 -- r3=2760
wr4 002774 -- r4=2774
wr5 000666 -- r5=666
wsp 001400 -- sp=1400
stapc 002700 -- start @ 2700
wtgo
rr0 d=002750 -- ! r0
rr1 d=002754 -- ! r1
rr2 d=002772 -- ! r2
rr3 d=002756 -- ! r3
rr4 d=002772 -- ! r4
rr5 d=000666 -- ! r5
rsp d=001376 -- ! sp
rpc d=002744 -- ! pc
wal 002750
brm 7
d=000110 -- ! mem(2750)=110
d=000120 -- ! mem(2752)=120
d=000130 -- ! mem(2754)=130
d=000140 -- ! mem(2756)=140
d=000150 -- ! mem(2760)=150
d=000160 -- ! mem(2762)=160
d=000170 -- ! mem(2764)=170
wal 001376
rmi d=000666 -- ! mem(sp)=666
#-----------------------------------------------------------------------------
C Setup code 10 [base 3000] (dstm modes: inc xxx: all non-r modes)
#
wal 003000 -- code:
bwm 10
005210 -- inc (r0) (to 3050)
005221 -- inc (r1)+ (to 3052)
005232 -- inc @(r2)+ (to 3054)
005243 -- inc -(r3) (to 3056)
005254 -- inc @-(r4) (to 3060)
005260 -- inc 12(r0) (to 3062)
000012
005270 -- inc @24(r0) (to 3064)
#3020
000024
000000 -- halt
#
wal 003050 -- data:
bwm 7
000110 -- mem(3050)=110
000120 -- mem(3052)=120
000130 -- mem(3054)=130
000140 -- mem(3056)=140
000150 -- mem(3060)=150
000160 -- mem(3062)=160
000170 -- mem(3064)=170
wal 003070 -- data:
bwm 3
003054 -- mem(3070)=3054
003060 -- mem(3072)=3060
003064 -- mem(3074)=3064
#
C Exec code 10 (dstm modes: inc xxx: all non-r modes)
#
wr0 003050 -- r0=3050
wr1 003052 -- r1=3052
wr2 003070 -- r2=3070
wr3 003060 -- r3=3060
wr4 003074 -- r4=3074
wsp 001400 -- sp=1400
stapc 003000 -- start @ 3000
wtgo
rr0 d=003050 -- ! r0
rr1 d=003054 -- ! r1
rr2 d=003072 -- ! r2
rr3 d=003056 -- ! r3
rr4 d=003072 -- ! r4
rpc d=003024 -- ! pc
wal 003050
brm 7
d=000111 -- ! mem(3050)=111
d=000121 -- ! mem(3052)=121
d=000131 -- ! mem(3054)=131
d=000141 -- ! mem(3056)=141
d=000151 -- ! mem(3060)=151
d=000161 -- ! mem(3062)=161
d=000171 -- ! mem(3064)=171
#-----------------------------------------------------------------------------
C Setup code 11 [base 3100; use 31-32] (dsta modes: jsr pc,xxx: all non-r modes)
#
wal 003100 -- code:
bwm 10
004710 -- jsr pc,(r0) (to 3210) r0->3210
004721 -- jsr pc,(r1)+ (to 3220) r1->3220
004732 -- jsr pc,@(r2)+ (to 3230) r2->3140->3230
004743 -- jsr pc,-(r3) (to 3240) r3->3242
004754 -- jsr pc,@-(r4) (to 3250) r4->3142->3250
004760 -- jsr pc,50(r0) (to 3260) r0->3210+50->3260
000050
004770 -- jsr pc,@-44(r0) (to 3270) r0->3210-44->3144->3270
#3120
177734
000000 -- halt
#
wal 003140 -- data:
bwm 3
003230 -- mem(3140)=3230
003250 -- mem(3142)=3250
003270 -- mem(3144)=3270
#
wal 003210 -- code:
bwm 28
012725 -- mov #110,(r5)+
000110
000207 -- rts pc
000000 -- halt
#3220
012725 -- mov #120,(r5)+
000120
000207 -- rts pc
000000 -- halt
012725 -- mov #130,(r5)+
000130
000207 -- rts pc
000000 -- halt
#3240
012725 -- mov #140,(r5)+
000140
000207 -- rts pc
000000 -- halt
012725 -- mov #150,(r5)+
000150
000207 -- rts pc
000000 -- halt
#3260
012725 -- mov #160,(r5)+
000160
000207 -- rts pc
000000 -- halt
012725 -- mov #170,(r5)+
000170
000207 -- rts pc
000000 -- halt
#
C Exec code 11 (dsta modes: jsr pc,xxx: all non-r modes)
#
wr0 003210 -- r0=3210
wr1 003220 -- r1=3220
wr2 003140 -- r2=3140
wr3 003242 -- r3=3242
wr4 003144 -- r4=3144
wr5 003160 -- r5=3160
wsp 001400 -- sp=1400
stapc 003100 -- start @ 3100
wtgo
rr0 d=003210 -- ! r0=3210
rr1 d=003222 -- ! r1=3222
rr2 d=003142 -- ! r2=3142
rr3 d=003240 -- ! r3=3240
rr4 d=003142 -- ! r4=3142
rr5 d=003176 -- ! r5=3176
rsp d=001400 -- ! sp
rpc d=003124 -- ! pc
wal 003160
brm 7
d=000110 -- ! mem(3160)=110
d=000120 -- ! mem(3162)=120
d=000130 -- ! mem(3164)=130
d=000140 -- ! mem(3166)=140
d=000150 -- ! mem(3170)=150
d=000160 -- ! mem(3172)=160
d=000170 -- ! mem(3174)=170
#-----------------------------------------------------------------------------
C Setup code 12 [base 3300; use 33-34] (PSW access via sex,clx,spl,mov, and clr)
#
wal 003300 -- code:
bwm 23
011025 -- mov (r0),(r5)+
012710 -- mov #030000,(r0) ; write full PSW: pmode=um
030000
011025 -- mov (r0),(r5)+
000263 -- se(v,c)
011025 -- mov (r0),(r5)+
000237 -- spl 7
011025 -- mov (r0),(r5)+
#3320
000274 -- se(n,z)
011025 -- mov (r0),(r5)+
000233 -- spl 3
011025 -- mov (r0),(r5)+
000241 -- clc
011025 -- mov (r0),(r5)+
112710 -- movb #40,(r0) ; write PSW_low (set pri=1)
000040
#3340
011025 -- mov (r0),(r5)+
112711 -- movb #20,(r1) ; write PSW_high: pmode=sm
000020
011025 -- mov (r0),(r5)+
005010 -- clr (r0)
011025 -- mov (r0),(r5)+
000000 -- halt
#
C Exec code 12 (PSW access via sex,clx,spl,mov, and clr)
#
wps 000017 -- psw: set all condition codes (to check psw clear @ start)
#
wr0 177776 -- r0=177776
wr1 177777 -- r1=177777
wr5 003400 -- r5=3400
wsp 001400 -- sp=1400
stapc 003300 -- start @ 3300
wtgo
rr5 d=003424 -- ! r5=3424
rpc d=003356 -- ! pc
wal 003400
brm 10
d=000340 -- ! mem(3400) after start
d=030000 -- ! mem(3402) after mov #030000,(r0)
d=030003 -- ! mem(3404) after se(v,c) (VC)
d=030341 -- ! mem(3406) after spl 7 (pri=7,C)
d=030355 -- ! mem(3410) after se(n,z) (pri=7,NZC)
d=030141 -- ! mem(3412) after spl 3 (pri=3,C)
d=030140 -- ! mem(3414) after clc (pri=3)
d=030040 -- ! mem(3416) after movb #40,(r0) (pri=1)
d=010040 -- ! mem(3420) after movb #20,(r1) pmode=sm
d=000000 -- ! mem(3422) after clr (r0)
#-----------------------------------------------------------------------------
C Setup code 13 [base 3500] (test WAIT and rdma (bwm/rwm while CPU running)
#
#[[off]] - can't emulate 'sto' command in simh, rdma meaningless in simh
#
wal 003500 -- code 13.1 (to be stepped)
bwm 4
000001 -- wait
000001 -- wait
000001 -- wait
000000 -- halt
#
wal 003520 -- code 13.2 (busy loop)
bwm 3
005700 -- tst r0
001776 -- beq .-1
000000 -- halt
#
wal 003540 -- code 13.3 (just a WAIT)
bwm 2
000001 -- wait
000000 -- halt
#
C Exec code 13.1a (run WAIT)
#
stapc 003500 -- start @ 3500
.wait 20 -- let it go
rpc d=003502 -- ! should hang here ...
.wait 20 -- let it go
rpc d=003502 -- ! should hang here ...
sto
wtlam d=000001 -- harvest attn due to go 1->0 transition of sto command
rpc d=003502 -- ! should stay there ...
#
C Exec code 13.1b (step WAIT)
wpc 003500 -- pc=3500
step -- step over 1st WAIT
rpc d=003502 -- !
step -- step over 2nd WAIT
rpc d=003504 -- !
step -- step over 3rd WAIT
rpc d=003506 -- !
step -- step over HALT
rpc d=003510 -- !
#
C Exec code 13.2 (test bwm/brm while CPU busy looping)
wr0 000000 -- r0=0
stapc 003520 -- start @ 3520
#
wal 003560 -- write data while CPU active
bwm 8
003560
003562
003564
003566
003570
003572
003574
003576
wal 003560 -- read data while CPU active
brm 8
d=003560
d=003562
d=003564
d=003566
d=003570
d=003572
d=003574
d=003576
#
wr0 000001 -- r0=1 --> should end loop
wtgo
rpc d=003526 -- !
#
C Exec code 13.3 (test bwm/brm while CPU on WAIT)
#
stapc 003540 -- start @ 3540
#
wal 003560 -- write data while CPU active
bwm 8
073560
073562
073564
073566
073570
073572
073574
073576
wal 003560 -- read data while CPU active
brm 8
d=073560
d=073562
d=073564
d=073566
d=073570
d=073572
d=073574
d=073576
#
sto
wtlam d=000001 -- harvest attn due to go 1->0 transition of sto command
rpc d=003542 -- !
#[[on]]
#-----------------------------------------------------------------------------
# Setup code 14 --- code 14 doesn't exist anymore...
#-----------------------------------------------------------------------------
C Setup code 15 [base 3600; use 36-37] (test 4 traps)
#
wal 003600 -- code:
bwm 5
000003 -- bpt (to 14)
000004 -- iot (to 20)
104077 -- emt 77 (to 30)
104477 -- trap 77 (to 34)
000000 -- halt
#
wal 003620 -- code: trap handlers
bwm 11
010025 -- mov r0,(r5)+ (@ 3620)
000405 -- br .+10
010125 -- mov r1,(r5)+ (@ 3624)
000403 -- br .+6
010225 -- mov r2,(r5)+ (@ 3630)
000401 -- br .+2
010325 -- mov r3,(r5)+ (@ 3634)
#3640
011604 -- mov (sp),r4 ; r4 points after instruction
016425 -- mov -2(r4),(r5)+ ; load instruction
177776
000002 -- rti
#
wal 000014 -- vector: 14+20
bwm 4
003620 -- PC:3620
000000 -- PS:0
003624 -- PC:3624
000000 -- PS:0
wal 000030 -- vector: 30+34
bwm 4
003630 -- PC:3630
000000 -- PS:0
003634 -- PC:3634
000000 -- PS:0
#
C Exec code 15 (test 4 traps)
#
wr0 000011 -- r0=11
wr1 000022 -- r1=22
wr2 000033 -- r2=33
wr3 000044 -- r3=44
wr5 003700 -- r5=3700
wsp 001400 -- sp=140
stapc 003600 -- start @ 3600
wtgo
rr5 d=003720 -- ! r5=3720
rsp d=001400 -- ! sp
rpc d=003612 -- ! pc
wal 003700
brm 8
d=000011 -- ! mem(3700)=11
d=000003 -- ! mem(3702)=3
d=000022 -- ! mem(3704)=22
d=000004 -- ! mem(3706)=4
d=000033 -- ! mem(3710)=33
d=104077 -- ! mem(3712)=104077
d=000044 -- ! mem(3714)=44
d=104477 -- ! mem(3716)=104477
wal 000014 -- vector: 14+20 -> trap catcher again
bwm 4
000016 -- PC:16
000000 -- PS:0
000022 -- PC:22
000000 -- PS:0
wal 000030 -- vector: 30+34 -> trap catcher again
bwm 4
000032 -- PC:32
000000 -- PS:0
000036 -- PC:36
000000 -- PS:0
#-----------------------------------------------------------------------------
C Setup code 16 [base 4000] (enable MMU, check ssr1, ssr2 response)
#
wal 172516 -- SSR3
wmi 000002 -- I/D enabled for sm only (to check CRESET)
wal 177572 -- SSR0
wmi 000001 -- set enable bit
#
wal 004000 -- code (to be single stepped...)
bwm 7
011105 -- mov (r1),r5
012105 -- mov (r1)+,r5
014105 -- mov -(r1),r5
012122 -- mov (r1)+,(r2)+
112105 -- movb (r1)+,r5
112721 -- movb #200,(r1)+
000200
#
wal 004030 -- code test 1:
wmi 000000 -- halt
#
wal 004040 -- data:
bwm 2
000001
000300
#
C Exec code 16 (enable MMU, check ssr1, ssr2 response)
#
wr1 004040 -- r1=4040
wr2 004060 -- r2=4060
wsp 001400 -- sp=1400
wpc 004000 -- pc=4000
step -- step (mov (r1),r5)
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=000000 -- ! SSR1:
d=004000 -- ! SSR2: 4000 (eff. PC)
rr1 d=004040 -- ! r1
rr5 d=000001 -- ! r5
step -- step (mov (r1)+,r5)
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=000021 -- ! SSR1: rb none; ra=1,+2
d=004002 -- ! SSR2: 4002 (eff. PC)
rr1 d=004042 -- ! r1
rr5 d=000001 -- ! r5
step -- step (mov -(r1),r5)
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=000361 -- ! SSR1: rb none; ra=1,-2
d=004004 -- ! SSR2: 4004 (eff. PC)
rr1 d=004040 -- ! r1
rr5 d=000001 -- ! r5
step -- step (mov (r1)+,(r2)+)
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=011021 -- ! SSR1: rb=2,2; ra=1,2
d=004006 -- ! SSR2: 4006 (eff. PC)
rr1 d=004042 -- ! r1
rr2 d=004062 -- ! r2
step -- step (movb (r1)+,r5)
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=000011 -- ! SSR1: rb=none; ra=1,1
d=004010 -- ! SSR2: 4010 (eff. PC)
rr1 d=004043 -- ! r1
rr5 d=177700 -- ! r5
step -- step (movb #200,(r1)+)
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=004427 -- ! SSR1: rb=1,1; ra=7,2
d=004012 -- ! SSR2: 4012 (eff. PC)
rr1 d=004044 -- ! r1
#
C Exec test 16.1 (check CRESET of PSW, SSR0, SSR3 after start)
#
wps 000000 -- psw: set pri=0
stapc 004030 -- start @ 4030 (just HALT, testing console reset)
wtgo
rpc d=004032 -- ! pc=4032
rps d=000340 -- ! psw: reset by CRESET
wal 172516 -- SSR3
rmi d=000000 -- ! cleared by CRESET
wal 177572 -- SSR0
rmi d=000000 -- ! cleared by CRESET
#-----------------------------------------------------------------------------
C Setup code 17 [base 4100; use 41-46] (basic instruction and cc test)
#
wal 004100 -- code: (length 70)
bwm 32
010124 -- mov r1,(r4)+ (#4711, #123456)
020124 -- cmp r1,(r4)+ (#4711, #123456)
020224 -- cmp r2,(r4)+ (#123456,#4711)
020124 -- cmp r1,(r4)+ (#4711, #4711)
005024 -- clr (r4)+ (#123456)
030124 -- bit r1,(r4)+ (#4711, #11)
030124 -- bit r1,(r4)+ (#4711, #66)
040124 -- bic r1,(r4)+ (#4711, #123456)
#4120
050124 -- bis r1,(r4)+ (#4711, #123456)
060124 -- add r1,(r4)+ (#4711, #123456)
160124 -- sub r1,(r4)+ (#4711, #123456)
005124 -- com (r4)+ (#123456)
005224 -- inc (r4)+ (#123456)
005324 -- dec (r4)+ (#123456)
005424 -- neg (r4)+ (#123456)
005724 -- tst (r4)+ (#123456)
#4140
006024 -- ror (r4)+ (#100201) Cin=0; Cout=1
006024 -- ror (r4)+ (#002201) Cin=1; Cout=1
006124 -- rol (r4)+ (#100200) Cin=1; Cout=1
006224 -- asr (r4)+ (#200)
006224 -- asr (r4)+ (#100200)
006324 -- asl (r4)+ (#200)
006324 -- asl (r4)+ (#100200)
060124 -- add r1,(r4)+ (#4711, #077777)
#4160
005524 -- adc (r4)+ (#200)
160124 -- sub r1,(r4)+ (#4711, #4700)
005624 -- sbc (r4)+ (#200)
000324 -- swap (r4)+ (#111000)
006724 -- sxt (r4)+ (#111111 with N=1)
074124 -- xor r1,(r4)+ (#070707,#4711)
006724 -- sxt (r4)+ (#111111 with N=0)
000000 -- halt
#
wal 000014 -- vector: 14
bwm 2
004270 -- PC:4270
000000 -- PS:0
#-----
wal 004270 -- code: (trap 14):
bwm 3
016625 -- mov 2(sp),(r5)+
000002
000006 -- rtt
#-----
wal 004300 -- data 1: (length 66)
bwm 31
123456 --
123456 --
004711 --
004711 --
123456 --
000011 --
000066 --
123456 --
#4320
123456 --
123456 --
123456 --
123456 --
123456 --
123456 --
123456 --
123456 --
#4340
100201 --
002201 --
100200 --
000200 --
100200 --
000200 --
100200 --
177000 --
#4360
000200 --
004701 --
000200 --
111000 --
111111 --
070707 --
111111 --
#
C Exec code 17 (basic instruction and cc test)
#
wr1 004711 -- r1=4711
wr2 123456 -- r2=123456
wr4 004300 -- r4=4300
wr5 004500 -- r5=4500
wsp 001374 -- sp=1374
wal 001374 -- setup stack with rtt return frame setting T flag
bwm 2
004100 -- start address (code 17 @ 4100)
000020 -- set T flag in PSW
stapc 004274 -- start @ 4274 -> rtt -> 4100 from stack
wtgo
rr1 d=004711 -- ! r1=4711
rr2 d=123456 -- ! r2=123456
rr4 d=004376 -- ! r4=4376
rr5 d=004576 -- ! r5=4576
rsp d=001400 -- ! sp=1400
rpc d=004200 -- ! pc=4200
wal 004300
brm 31
d=004711 -- ! mem(4300)=004711; mov r1,(r4)+ (#4711, #123456)
d=123456 -- ! mem(4302)=123456; cmp r1,(r4)+ (#4711, #123456)
d=004711 -- ! mem(4304)=004711; cmp r1,(r4)+ (#123456,#4711)
d=004711 -- ! mem(4306)=004711; cmp r1,(r4)+ (#4711, #4711)
d=000000 -- ! mem(4310)=000000; clr (r4)+ (#123456)
d=000011 -- ! mem(4312)=000011; bit r1,(r4)+ (#4711, #11)
d=000066 -- ! mem(4314)=000066; bit r1,(r4)+ (#4711, #66)
d=123046 -- ! mem(4316)=123046; bic r1,(r4)+ (#4711, #123456)
d=127757 -- ! mem(4320)=127757; bis r1,(r4)+ (#4711, #123456)
d=130367 -- ! mem(4322)=130367; add r1,(r4)+ (#4711, #123456)
d=116545 -- ! mem(4324)=116545; sub r1,(r4)+ (#4711, #123456)
d=054321 -- ! mem(4326)=054321; com (r4)+ (#123456)
d=123457 -- ! mem(4330)=123457; inc (r4)+ (#123456)
d=123455 -- ! mem(4332)=123455; dec (r4)+ (#123456)
d=054322 -- ! mem(4334)=054322; neg (r4)+ (#123456)
d=123456 -- ! mem(4336)=123456; tst (r4)+ (#123456)
d=040100 -- ! mem(4340)=040100; ror (r4)+ (#100201)
d=101100 -- ! mem(4342)=101100; ror (r4)+ (#002201)
d=000401 -- ! mem(4344)=000401; rol (r4)+ (#100200)
d=000100 -- ! mem(4346)=000100; asr (r4)+ (#200)
d=140100 -- ! mem(4350)=140100; asr (r4)+ (#100200)
d=000400 -- ! mem(4352)=000400; asl (r4)+ (#200)
d=000400 -- ! mem(4354)=000400; asl (r4)+ (#100200)
d=003711 -- ! mem(4356)=003711; add r1,(r4)+ (#4711, ,#177000)
d=000201 -- ! mem(4360)=000201; adc (r4)+ (#200)
d=177770 -- ! mem(4362)=177770; sub r1,(r4)+ (#4711, #4701)
d=000177 -- ! mem(4364)=000177; sbc (r4)+ (#200)
d=000222 -- ! mem(4366)=000222; swap (r4)+ (#111000)
d=177777 -- ! mem(4370)=177777; sxt (r4)+ (#111111)
d=074016 -- ! mem(4372)=074016; xor r1,(r4)+ (#070707)
d=000000 -- ! mem(4374)=000000; sxt (r4)+ (#111111)
#
wal 004500 -- NZVC
brm 31
d=000020 -- ! mem(4500)=0000; mov r1,(r4)+ (#4711, #123456)
d=000021 -- ! mem(4502)=000C; cmp r1,(r4)+ (#4711, #123456)
d=000030 -- ! mem(4504)=N000; cmp r1,(r4)+ (#123456,#4711)
d=000024 -- ! mem(4506)=0Z00; cmp r1,(r4)+ (#4711, #4711)
d=000024 -- ! mem(4510)=0Z00; clr (r4)+ (#123456)
d=000020 -- ! mem(4512)=0000; bit r1,(r4)+ (#4711, #11)
d=000024 -- ! mem(4514)=0Z00; bit r1,(r4)+ (#4711, #66)
d=000030 -- ! mem(4516)=N000; bic r1,(r4)+ (#4711, #123456)
d=000030 -- ! mem(4520)=N000; bis r1,(r4)+ (#4711, #123456)
d=000030 -- ! mem(4522)=N000; add r1,(r4)+ (#4711, #123456)
d=000030 -- ! mem(4524)=N000; sub r1,(r4)+ (#4711, #123456)
d=000021 -- ! mem(4526)=000C; com (r4)+ (#123456)
d=000031 -- ! mem(4530)=N00C; inc (r4)+ (#123456) keep C!
d=000031 -- ! mem(4532)=N00C; dec (r4)+ (#123456) keep C!
d=000021 -- ! mem(4534)=000C; neg (r4)+ (#123456)
d=000030 -- ! mem(4536)=N000; tst (r4)+ (#123456)
d=000023 -- ! mem(4540)=00VC; ror (r4)+ (#100201)
d=000031 -- ! mem(4542)=N00C; ror (r4)+ (#002201)
d=000023 -- ! mem(4544)=00VC; rol (r4)+ (#100200)
d=000020 -- ! mem(4546)=0000; asr (r4)+ (#200)
d=000032 -- ! mem(4550)=N0V0; asr (r4)+ (#100200)
d=000020 -- ! mem(4552)=0000; asl (r4)+ (#200)
d=000023 -- ! mem(4554)=00VC; asl (r4)+ (#100200)
d=000021 -- ! mem(4556)=000C; add r1,(r4)+ (#4711, ,#177000)
d=000020 -- ! mem(4560)=0000; adc (r4)+ (#200)
d=000031 -- ! mem(4562)=N00C; sub r1,(r4)+ (#4711, #4701)
d=000020 -- ! mem(4564)=0000; sbc (r4)+ (#200)
d=000030 -- ! mem(4566)=N000; swap (r4)+ (#111000)
d=000030 -- ! mem(4570)=N000; sxt (r4)+ (#111111 with N=1)
d=000020 -- ! mem(4572)=0000; xor r1,(r4)+ (#4711, #070707)
d=000024 -- ! mem(4574)=0Z00; sxt (r4)+ (#111111 with N=0)
#
rst -- console reset (to clear T flag)
wal 000014 -- vector: 14 -> trap catcher again
bwm 2
000016 -- PC:16
000000 -- PS:0
#-----------------------------------------------------------------------------
C Setup code 20 [base 4700] (check CPUERR and error handling)
#[[off]]
wal 004700 -- code (to be single stepped...)
bwm 11
010025 -- mov r0,(r5)+ (@ 4777)
010025 -- mov r0,(r5)+ (@ 150000)
010025 -- mov r0,(r5)+ (@ 160000)
000101 -- jmp r1
004701 -- jsr pc,r1
000000 -- halt
014321 -- mov -(r3),(r1)+ (@ 20000)
024321 -- cmp -(r3),(r1)+ (@ 20400)
#4720
064321 -- add -(r3),(r1)+ (@ 20000)
010046 -- mov r0,-(sp) (@ 340)
000004 -- iot (with sp=342,...)
#
wal 000004 -- vector: 4+10 (trap catch)
bwm 4
000006 -- PC:6
000000 -- PS:0
000012 -- PC:12
000000 -- PS:0
#----------
C Exec code 20 (check CPUERR and error handling)
C Exec test 20.1 (odd address abort)
rst -- console reset
wps 000000 -- psw: clear
wal 001374 -- clean stack
bwm 2
000000 --
000000 --
wal 177766 -- check initial CPUERR (=0!)
rm d=000000 -- !
wr0 000011 -- r0=11
wr5 004775 -- r5=4775
wsp 001400 -- sp=1400
wpc 004700 -- pc=4700
step -- step (mov r0,(r5)+): trap 4 + CPUERR.adderr set [[s:2]]
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=001374 -- ! sp=1374
wal 001374 -- check stack
brm 2
d=004702 -- ! pc=4702
d=000000 -- ! ps=0
wal 177766 -- check CPUERR
rm d=000100 -- ! CPUERR: (adderr=1)
wm 000000 -- any write access will clear CPUERR
rm d=000000 -- ! CPUERR: 0
#----------
C Exec test 20.2 (non-existent memory abort)
wal 172354 -- kernel I space AR(6)
wm 177400 -- (map to 8 k below I/O page, never available in w11a)
wal 177572 -- SSR0
wmi 000001 -- enable
wal 172516 -- SSR3
wmi 000020 -- ena_22bit=1
#
wr5 140000 -- r5=140000
wsp 001400 -- sp=1400
wpc 004702 -- pc=4702
step -- step (mov r0,(r5)+): trap 4 + CPUERR.nxm set [[s:2]]
rpc d=000006 -- ! pc= 6 (trap 4 catch)
rsp d=001374 -- ! sp=1374
wal 177766 -- check CPUERR
rm d=000040 -- ! CPUERR: (nxm=1)
wm 000000 -- any write access will clear CPUERR
rm d=000000 -- ! CPUERR: 0
#
wal 177572 -- SSR0
wmi 000000 -- disable
wal 172354 -- kernel I space AR(6)
wm 001400 -- 1400 140000 base (default 1-to-1 map)
#----------
C Exec test 20.3 (I/O bus timeout abort)
wr5 160000 -- r5=160000
wsp 001400 -- sp=1400
wpc 004704 -- pc=4704
step -- step (mov r0,(r5)+): trap 4 + CPUERR.iobto set [[s:2]]
rpc d=000006 -- ! pc= 6 (trap 4 catch)
rsp d=001374 -- ! sp=1374
wal 177766 -- check CPUERR
rm d=000020 -- ! CPUERR: (iobto=1)
wm 000000 -- clear CPUERR
#----------
C Exec test 20.4 (address error abort after jmp r1)
wsp 001400 -- sp=1400
wpc 004706 -- pc=4706
step -- step (jmp r1): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 10 catch)
rsp d=001374 -- ! sp=1374
wal 177766 -- check CPUERR
rm d=000000 -- ! CPUERR: none
wm 000000 -- clear CPUERR
#----------
C Exec test 20.5 (address error abort after jsr pc,r1)
wsp 001400 -- sp=1400
wpc 004710 -- pc=4710
step -- step (jsr pc,r1): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 10 catch)
rsp d=001374 -- ! sp=1374
wal 177766 -- check CPUERR
rm d=000000 -- ! CPUERR: none
wm 000000 -- clear CPUERR
#----------
C Exec test 20.6 (halt in user mode)
wsp 001400 -- sp=1400 (kernel)
wpc 004712 -- pc=4712
wps 170000 -- psw: cmode=pmode=11 (user)
step -- step (halt): trap 4 + CPUERR.illhlt set [[s:2]]
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=001374 -- ! sp=1374 (now kernel again...)
wal 001374 -- check stack
brm 2
d=004714 -- !
d=170000 -- !
wal 177766 -- check CPUERR
rm d=000200 -- ! CPUERR: (illhlt=1)
wm 000000 -- clear CPUERR
#
wps 000000 -- psw: cmode=pmode=0 (kernel)
#----------
#
# test mmu aborts
#
wal 000250 -- vector: 250 -> trap catcher
bwm 2
000252 -- PC:252
000000 -- PS:0
#
wal 177572 -- SSR0
wmi 000001 -- enable
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077400 -- slf=127; ed=0(up); acf=0 (non-resident)
#----------
C Exec test 20.7 (non resident abort)
wr1 020000 -- r1=20000
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
wsp 001400 -- sp=1400
wpc 004714 -- pc=4714
step -- step (mov -(r3),(r1)+): abort to 250 [[s:2]]
rr1 d=020002 -- ! r1=20002 (inc done before trap (here dstw))
rr3 d=000014 -- ! r3=16 (dec done before trap)
rpc d=000252 -- ! pc=252 (trap 250 catch)
rsp d=001374 -- ! sp=1374
wal 177572 -- check SSR0/1/2
brm 3
d=100003 -- ! SSR0: (abo_nonres=1,seg=1,ena=1)
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
d=004714 -- ! SSR2: 4714 (eff. PC)
#
wal 177572 -- SSR0
wmi 000001 -- enable and clear error bits
#----------
C Exec test 20.8 (segment length violation abort)
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 001406 -- slf=3; ed=0(up); acf=6 (w/r)
#
wr1 020400 -- r1=20400
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
wsp 001400 -- sp=1400
wpc 004716 -- pc=4716
step -- step (cmp -(r3),(r1)+): abort to 250 [[s:2]]
rr1 d=020402 -- ! r1=20402 (inc done before trap (here dstr))
rr3 d=000014 -- ! r3=16 (dec done before trap)
rpc d=000252 -- ! pc=252 (trap 250 catch)
rsp d=001374 -- ! sp=1374
wal 177572 -- check SSR0/1/2
brm 3
d=040003 -- ! SSR0: (abo_length=1,seg=1,ena=1)
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
d=004716 -- ! SSR2: 4716 (eff. PC)
#
wal 177572 -- SSR0
wmi 000001 -- enable and clear error bits
#----------
C Exec test 20.9 (read-only abort)
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077402 -- slf=127; ed=0(up); acf=2 (read-only)
#
wr1 020000 -- r1=20000
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
wsp 001400 -- sp=1400
wpc 004720 -- pc=4720
step -- step (add -(r3),(r1)+): abort to 250 [[s:2]]
rr1 d=020002 -- ! r1=20000 (inc done before trap (here dstm))
rr3 d=000014 -- ! r3=16 (dec done before trap)
rpc d=000252 -- ! pc=252 (trap 250 catch)
rsp d=001374 -- ! sp=1374
wal 177572 -- check SSR0/1/2
brm 3
d=020003 -- ! SSR0: (abo_rdonly=1,seg=1,ena=1)
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
d=004720 -- ! SSR2: 4720 (eff. PC)
#
# mmu back to default setup, disable
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
wal 177572 -- SSR0
wmi 000000 -- disable
#----------
#
# test mmu trap
#
wal 177572 -- SSR0
wmi 001001 -- enable, trap enable
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077404 -- slf=127; ed=0(up); acf=4 (r/w, trap on r/w)
#----------
C Exec test 20.10 (trap on write)
wr1 020000 -- r1=20000
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
wsp 001400 -- sp=1400
wpc 004714 -- pc=4714
step -- step (mov -(r3),(r1)+): trap to 250 [[s:2]]
rr1 d=020002 -- ! r1=20002 (inc done before trap)
rr3 d=000014 -- ! r3=16 (dec done before trap)
rpc d=000252 -- ! pc=252 (trap 250 catch)
rsp d=001374 -- ! sp=1374
wal 020000 -- check target area
rm d=000016 -- ! mem(20000)=16
wm 000000 -- clean tainted memory
wal 177572 -- check SSR0
brm 3
d=011001 -- ! SSR0: (trap_mmu=1,ena_trap=1,seg=0,ena=1)
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
d=004714 -- ! SSR2: 4714 (eff. PC)
#----------
C Exec test 20.11 (2nd write, should not trap again)
wr1 020002 -- r1=20002
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
wsp 001400 -- sp=1400
wpc 004714 -- pc=4714
step -- step (mov -(r3),(r1)+): no trap [[s:2]]
rr1 d=020004 -- ! r1=20004 (inc done before trap)
rr3 d=000014 -- ! r3=16 (dec done before trap)
rpc d=004716 -- ! pc=252 (trap 250 catch)
rsp d=001400 -- ! sp=1374
wal 020002 -- check target area
rm d=000016 -- ! mem(20002)=16
wm 000000 -- clean tainted memory
wal 177572 -- check SSR0
brm 3
d=011003 -- ! SSR0: (trap_mmu=1,ena_trap=1,seg=1,ena=1)
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
d=004714 -- ! SSR2: 4714 (eff. PC)
#
# mmu back to default setup, disable
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
wal 177572 -- SSR0
wmi 000000 -- disable
#----------
#
# now test stack limit logic
#
C Exec test 20.12 (red stack abort when pushing data to stack)
wr0 123456 -- r0=123456
wsp 000340 -- sp=340
wpc 004722 -- pc=4722
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=000000 -- ! sp=0
wal 000336 -- check that stack wasn't written
rm d=000000 -- ! mem(336) untainted
wal 000000 -- check emergency stack at 0,2
brm 2
d=004724 -- ! mem(0): PC
d=000010 -- ! mem(2): PS
wal 177766 -- check CPUERR
rm d=000004 -- ! CPUERR: (rsv=1)
wm 000000 -- clear CPUERR
#----------
C Exec test 20.13 (red stack abort on 2nd word of interrupt/trap push)
wps 000017 -- psw: set all cc flags
wsp 000342 -- sp=342
wpc 004724 -- pc=4724
step -- step (iot): abort to 4 [[s:2]]
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=000000 -- ! sp=0
wal 000336 -- check stack
brm 2
d=000000 -- ! mem(336) untainted
d=000017 -- ! mem(340) PS of 1st attempt
wal 000000 -- check emergency stack at 0,2
brm 2
d=004726 -- ! mem(0): PC
d=000000 -- ! mem(2): PS (will be 0, orgininal PS lost !!)
wal 177766 -- check CPUERR
rm d=000004 -- ! CPUERR: (rsv=1)
wm 000000 -- clear CPUERR
#----------
C Exec test 20.14 (yellow stack trap when pushing data to stack; sp=400)
wps 000017 -- psw: set all cc flags
wr0 123456 -- r0=123456
wsp 000400 -- sp=400
wpc 004722 -- pc=4722
step -- step (mov r0,-(sp)): trap to 4
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=000372 -- ! sp=372
wal 000372 -- check stack
brm 3
d=004724 -- ! mem(372) PC of trapped instruction
d=000011 -- ! mem(374) PS of trapped instruction
d=123456 -- ! mem(376) pushed word
wal 177766 -- check CPUERR
rm d=000010 -- ! CPUERR: (ysv=1)
wm 000000 -- clear CPUERR
#----------
C Exec test 20.15 (yellow stack trap on 2nd word of interrupt/trap push; sp=402)
wps 000017 -- psw: set all cc flags
wsp 000402 -- sp=402
wpc 004724 -- pc=4724
step -- step (iot): abort to 4 [[s:2]]
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=000372 -- ! sp=372
wal 000372 -- check stack
brm 4
d=000022 -- ! mem(372) PC of IOT handler
d=000000 -- ! mem(374) PS of IOT handler
d=004726 -- ! mem(376) PC of IOT trap
d=000017 -- ! mem(400) PS of IOT trap
wal 177766 -- check CPUERR
rm d=000010 -- ! CPUERR: (ysv=1)
wm 000000 -- clear CPUERR
#----------
# now test red stack escalation
#
C Exec test 20.16 (red stack escalation: abort kernel stack odd; sp=1001)
wr0 123456 -- r0=123456
wsp 001001 -- sp=1001
wpc 004722 -- pc=4722
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=000000 -- ! sp=0
wal 000000 -- check emergency stack at 0,2
brm 2
d=004724 -- ! mem(0): PC
d=000010 -- ! mem(2): PS
wal 177766 -- check CPUERR
rm d=000104 -- ! CPUERR: (rsv=1,adderr=1)
wm 000000 -- clear CPUERR
#----------
C Exec test 20.17 (red stack escalation: abort kernel stack in non-mem)
wal 172354 -- kernel I space AR(6)
wm 177400 -- (map to 8 k below I/O page, never available in w11a)
wal 177572 -- SSR0
wmi 000001 -- enable
wal 172516 -- SSR3
wmi 000020 -- ena_22bit=1
#
wr0 123456 -- r0=123456
wsp 140004 -- sp=140004
wpc 004722 -- pc=4722
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=000000 -- ! sp=0
wal 000000 -- check emergency stack at 0,2
brm 2
d=004724 -- ! mem(0): PC
d=000010 -- ! mem(2): PS
wal 177766 -- check CPUERR
rm d=000044 -- ! CPUERR: (rsv=1,nxm=1)
wm 000000 -- clear CPUERR
#
wal 177572 -- SSR0
wmi 000000 -- disable
wal 172354 -- kernel I space AR(6)
wm 001400 -- 1400 140000 base (default 1-to-1 map)
#----------
C Exec test 20.18 (red stack escalation: abort kernel stack iob-to;sp=160004)
wr0 123456 -- r0=123456
wsp 160004 -- sp=160004
wpc 004722 -- pc=4722
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=000000 -- ! sp=0
wal 000000 -- check emergency stack at 0,2
brm 2
d=004724 -- ! mem(0): PC
d=000010 -- ! mem(2): PS
wal 177766 -- check CPUERR
rm d=000024 -- ! CPUERR: (rsv=1,iobto=1)
wm 000000 -- clear CPUERR
#----------
C Exec test 20.19 (red stack escalation: abort kernel stack mmu abort;sp=020004)
#
wal 177572 -- SSR0
wmi 000001 -- enable
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077400 -- slf=127; ed=0(up); acf=0 (non-resident)
#
wr0 123456 -- r0=123456
wsp 020004 -- sp=020004
wpc 004722 -- pc=4722
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=000000 -- ! sp=0
wal 020002 -- check that stack wasn't written
rm d=000000 -- ! mem(20002) untainted
wal 000000 -- check emergency stack at 0,2
brm 2
d=004724 -- ! mem(0): PC
d=000010 -- ! mem(2): PS
wal 177766 -- check CPUERR
rm d=000104 -- ! CPUERR: (rsv=1,adderr=1)
wm 000000 -- clear CPUERR
# mmu back to default setup
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
wal 177572 -- SSR0
wmi 000000 -- disable
wal 172516 -- SSR3
wmi 000000 -- disable
#
#[[on]]
#-----------------------------------------------------------------------------
C Setup code 21 [base 4740] (MTPx/MFPx; MMU for user mode with I/D)
#
#use setting as for test 22
wal 177600 -- user I space DR
wmi 077406 -- slf=127; ed=0(up); acf=6(w/r)
wal 177620 -- user D space DR
wmi 077406 -- slf=127; ed=0(up); acf=6(w/r)
wal 177640 -- user I space AR
wmi 000053 -- 53 -> maps 0 -> 5300
wal 177660 -- user D space AR
wmi 000055 -- 55 -> maps 0 -> 5500
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wal 172516 -- SSR3
wmi 000001 -- enable D space for user mode
#
wal 004740 -- code (to be single stepped...)
bwm 6
006610 -- mtpi (r0)
106610 -- mtpd (r0)
006606 -- mtpi r6
006510 -- mfpi (r0)
106510 -- mfpd (r0)
006506 -- mfpi r6
#
C Exec code 21 (MTPx/MFPx; MMU for user mode with I/D)
#
wps 030000 -- psw: cmode=0, pmode=11
wal 001372 -- setup kernel stack
bwm 3
012300 --
001230 --
000666 --
wr0 000002 -- r0=2
wsp 001372 -- sp=1372
#
wpc 004740 -- pc=4740
step -- step (mtpi (r0))
rpc d=004742 -- ! pc=next
rsp d=001374 -- ! sp=1374 (one popped)
wal 005302 -- user I base
rm d=012300 -- ! mem_ui(2) = 012300
#
step -- step (mtpd (r0))
rpc d=004744 -- ! pc=next
rsp d=001376 -- ! sp=1376 (one popped)
wal 005502 -- user D base
rm d=001230 -- ! mem_ud(2) = 001230
#
step -- step (mtpi r6)
rpc d=004746 -- ! pc=next
rsp d=001400 -- ! sp=1400 (one popped)
wps 170000 -- psw: cmode=11, pmode=11
rsp d=000666 -- ! sp_um=666 [[usp]]
wps 030000 -- psw: cmode=0, pmode=11
#
wal 001374 -- clear stack
bwm 3
000000 --
000000 --
000000 --
#
step -- step (mfpi (r0))
rpc d=004750 -- ! pc=next
rsp d=001376 -- ! sp=1376 (one pushed)
wal 001376 -- top of stack
rm d=012300 -- !
#
step -- step (mfpd (r0))
rpc d=004752 -- ! pc=next
rsp d=001374 -- ! sp=1374 (one pushed)
wal 001374 -- top of stack
rm d=001230 -- !
#
step -- step (mtpi r6)
rpc d=004754 -- ! pc=next
rsp d=001372 -- ! sp=1372 (one pushed)
wal 001372 -- top of stack
rm d=000666 -- !
#
wal 005302 -- clean tainted memory
wm 000000 --
wal 005502 --
wm 000000 --
#
wps 000000 -- psw: cmode=pmode=0 (kernel)
#-----------------------------------------------------------------------------
C Setup code 22 [base 5000, use 50-57] (MMU ; run user mode code with I/D)
#
wal 177600 -- user I space DR
wmi 000002 -- slf=0; ed=0(up); acf=2(read-only)
wal 177620 -- user D space DR
wmi 000006 -- slf=0; ed=0(up); acf=6(w/r)
wal 177640 -- user I space AR
wmi 000053 -- 53 -> maps 0 -> 5300
wal 177660 -- user D space AR
wmi 000055 -- 55 -> maps 0 -> 5500
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wal 172516 -- SSR3
wmi 000001 -- enable D space for user mode
#
wal 005000 -- code (kernel):
bwm 5
012746 -- mov #144000,-(sp) ;PS for RTI
174000 -- cmode=11,pmode=11,rset=1
012746 -- mov #0,-(sp) ;PC for RTI
000000 --
000002 -- rti
#-----
wal 000034 -- vector: 34 (TRAP)
bwm 2
005020 -- PC:5020
000340 -- PS: pri=7
#-----
wal 005020 -- code (kernel, trap 34):
bwm 4
011600 -- mov (sp),r0
006560 -- mfpi -2(r0)
177776
000000 -- halt
#-----
wal 000250 -- vector: 250 (MMU)
bwm 2
005040 -- PC:5040
000340 -- PS: pri=7
#-----
wal 005040 -- code (kernel, trap 4):
bwm 68
005337 -- dec @#5256
005256
001001 -- bne .+2
000000 -- halt
013700 -- mov ssr0,r0
177572
042700 -- bic #177741,r0 ; clear all but id+asn fields
177741
#5060
062700 -- add #177600,r0 ; user DR address base
177600
# 5 23 062710 0 -- add #400,(r0)
# 5 23 000400 0
105260 -- incb 1(r0) ; odd address IB access fails !!
000001
010025 -- mov r0,(r5)+
012025 -- mov (r0),(r5)+
013700 -- mov ssr1,r0
177574
#5100
010025 -- mov r0,(r5)+
012701 -- mov #2,r1
000002
052737 -- bis #004000,psw
004000
177776
005046 -- clr -(sp)
106506 -- mfpd sp
#5120
010546 -- mov r5,-(sp)
010446 -- mov r4,-(sp)
010346 -- mov r3,-(sp)
010246 -- mov r2,-(sp)
010146 -- mov r1,-(sp)
010046 -- mov r0,-(sp)
042737 -- bic #004000,psw
004000
#5140
177776
010002 -- L1: mov r0,r2
110003 -- movb r0,r3
042702 -- bic #177770,r2 ; mask regnum field
177770
006302 -- asl r2
060602 -- add sp,r2 ; address of reg on stack
006203 -- asr r3 ; shift delta field down 3 bit
#5160
006203 -- asr r3
006203 -- asr r3
160312 -- sub r3,(r2) ; correct register contents
000300 -- swap r0
077114 -- sob r1,L1 (.-12)
052737 -- bis #004000,psw
004000
177776
#5200
012600 -- mov (sp)+,r0
012601 -- mov (sp)+,r1
012602 -- mov (sp)+,r2
012603 -- mov (sp)+,r3
012604 -- mov (sp)+,r4
012605 -- mov (sp)+,r5
106606 -- mtpd sp
005726 -- tst (sp)+
#5220
042737 -- bic #004000,psw
004000
177776
013700 -- mov ssr2,r0
177576
010025 -- mov r0,(r5)+
010016 -- mov r0,(sp)
042737 -- bic #160000,ssr0 ; clear abort bits
#5240
160000
177572
000002 -- rti
000000 -- halt
#-----
wal 005256 -- data (kernel):
wmi 000003 -- stop at 3rd call of MMU handler
#-----
wal 005300 -- code (user):
bwm 8
012706 -- mov #100,sp
000100
005000 -- clr r0
012701 -- mov #074,r1
000074
062021 -- add (r0)+,(r1)+ ; r1 = 74
000137 -- jmp @#74
000074
#
wal 005374 -- .=5374
bwm 4
062021 -- add (r0)+,(r1)+ ; r1 = 76
062021 -- add (r0)+,(r1)+ ; r1 = 100
#5400
062021 -- add (r0)+,(r1)+ ; r1 = 102
104417 -- trap 17
#
wal 005500 -- data (user):
bwm 4
002001 -- mem_ud(0)=02001
002002 -- mem_ud(2)=02002
002003 -- mem_ud(4)=02003
002004 -- mem_ud(6)=02004
wal 005574 -- data (user):
bwm 4
000300 -- mem_ud(074)=0300
000300 -- mem_ud(076)=0300
000300 -- mem_ud(100)=0300
000300 -- mem_ud(102)=0300
#
C Exec code 22 (MMU ; run user mode code with I/D)
wr5 005260 -- r5=5260
wsp 001400 -- sp=1400
wpc 005000 -- pc=5000
cont -- cont @ 5000
wtgo
rsp d=001372 -- ! sp
rpc d=005030 -- ! pc (halt in TRAP handler)
wal 001372 -- check stack (1372)
brm 3
d=104417 -- ! TRAP instruction
d=000104 -- ! PC trap
d=174000 -- ! PS trap
#
wal 005256 --
brm 9
d=000001 -- ! mem(5256) (mmu 3 - trap count)
d=177620 -- ! mem(5260) (1st trap: address fixed DR)
d=000406 -- ! mem(5262) (1st trap: new content of DR)
d=010420 -- ! mem(5264) (1st trap: ssr1: ra=0,2;rb=1,2)
d=000076 -- ! mem(5266) (1st trap: ssr2: pc)
d=177600 -- ! mem(5270) (2nd trap: address fixed DR)
d=000402 -- ! mem(5272) (2nd trap: new content of DR)
d=000000 -- ! mem(5274) (2nd trap: ssr1: none)
d=000100 -- ! mem(5276) (2nd trap: ssr2: pc)
#
wal 005574
brm 4
d=002301 -- ! mem(5574)=02301 was mem_ud(074)
d=002302 -- ! mem(5576)=02302 was mem_ud(076)
d=002303 -- ! mem(5600)=02303 was mem_ud(100)
d=002304 -- ! mem(5602)=02304 was mem_ud(102)
#
wal 000034 -- vector: 34 -> trap catcher again
bwm 2
000036 -- PC:36
000000 -- PS:0
wal 000250 -- vector: 250 -> trap catcher again
bwm 2
000252 -- PC:252
000000 -- PS:0
#
wps 000000 -- psw: cmode=pmode=0 (kernel)
#-----------------------------------------------------------------------------
C Setup code 23 [base 5700; use 57-63] (test cmp and conditional branch)
#
wal 005700 -- code test 1:
bwm 5
012012 -- mov (r0)+,(r2) ; load PSW from table
004737 -- jsr pc,@#6000
006000
077104 -- sob r1,-4
000000 -- halt
#
wal 005720 -- code test 2:
bwm 6
000230 -- spl 0
005720 -- tst (r0)+ ; verify tst response
004737 -- jsr pc,@#6000
006000
077104 -- sob r1,-4
000000 -- halt
#
wal 005740 -- code test 3:
bwm 6
000230 -- spl 0
022020 -- cmp (r0+),(r0)+ ; verify cmp response
004737 -- jsr pc,@#6000
006000
077104 -- sob r1,-4
000000 -- halt
#
# test 1 test 2 test 3
# - C V Z N < = > < = >
# code branch condition mask 1 2 3 4 5 1 2 3 1 2 3 4 5 6 7
# BNE if Z = 0 000004 y y y y y y y y y y y y
# BEQ if Z = 1 000010 y y y
# BGE if (N xor V) = 0 000020 y y y y y y y y y
# BLT if (N xor V) = 1 000040 y y y y y y
# BGT if (Z or (N xor V)) = 0 000100 y y y y y y
# BLE if (Z or (N xor V)) = 1 000200 y y y y y y y y y
# BPL if N = 0 000400 y y y y y y y y y y
# BMI if N = 1 001000 y y y y y
# BHI if (C or Z) = 0 002000 y y y y y y y y
# BLOS if (C or Z) = 1 004000 y y y y y y y
# BVC if V = 0 010000 y y y y y y y y y y y y
# BVS if V = 1 020000 y y y
# BCC if C = 0 (aka BHIS) 040000 y y y y y y y y y y y
# BCS if C = 1 (aka BLO) 100000 y y y y
#
wal 006000 -- code check:
bwm 63
011203 -- mov (r2),r3 ; save PSW
012704 -- mov #177774,r4 ; set pattern store
177774 --
010312 -- mov r3,(r2) ; restore PSW
001003 -- bne .+3
042704 -- bic #000004,r4
000004 --
010312 -- mov r3,(r2)
#6020
001403 -- beq .+3
042704 -- bic #000010,r4
000010 --
010312 -- mov r3,(r2)
002003 -- bge .+3
042704 -- bic #000020,r4
000020 --
010312 -- mov r3,(r2)
#6040
002403 -- blt .+3
042704 -- bic #000040,r4
000040 --
010312 -- mov r3,(r2)
003003 -- bgt .+3
042704 -- bic #000100,r4
000100 --
010312 -- mov r3,(r2)
#6060
003403 -- ble .+3
042704 -- bic #000200,r4
000200 --
010312 -- mov r3,(r2)
100003 -- bpl .+3
042704 -- bic #000400,r4
000400 --
010312 -- mov r3,(r2)
#6100
100403 -- bmi .+3
042704 -- bic #001000,r4
001000 --
010312 -- mov r3,(r2)
101003 -- bhi .+3
042704 -- bic #002000,r4
002000 --
010312 -- mov r3,(r2)
#6120
101403 -- blos .+3
042704 -- bic #004000,r4
004000 --
010312 -- mov r3,(r2)
102003 -- bvc .+3
042704 -- bic #010000,r4
010000 --
010312 -- mov r3,(r2)
#6140
102403 -- bvs .+3
042704 -- bic #020000,r4
020000 --
010312 -- mov r3,(r2)
103003 -- bcc .+3
042704 -- bic #040000,r4
040000 --
010312 -- mov r3,(r2)
#6160
103403 -- bcs .+3
042704 -- bic #100000,r4
100000 --
010312 -- mov r3,(r2)
010325 -- mov r3,(r5)+
010425 -- mov r4,(r5)+
000207 -- rts pc
#
wal 006200 -- data test 1:
bwm 5
000000 -- PSW - no cc
000001 -- PSW - C=1
000002 -- PSW - V=1
000004 -- PSW - Z=1
000010 -- PSW - N=1
#
wal 006220 -- data test 2:
bwm 3
177777 -- tst -1
000000 -- tst 0
000001 -- tst 1
#
wal 006230 -- data test 3:
bwm 14
000001 -- cmp 1,2
000002
000001 -- cmp 1,1
000001
#6240
000002 -- cmp 2,1
000001
177777 -- cmp -1,2
000002
000002 -- cmp 2,-1
177777
100000 -- cmp 100000,077777
077777
#6260
077777 -- cmp 077777,100000
100000
#
C Exec code 23 (test cmp and conditional branch)
C Exec test 23.1 (explict cc setting)
#
wr0 006200 -- r0=6200 (input data)
wr1 000005 -- r1=5
wr2 177776 -- r2=177776 (PS address)
wr5 006300 -- r5=6300 (output data)
wsp 001400 -- sp=1400
stapc 005700 -- start @ 5700
wtgo
rr0 d=006212 -- ! r0
rr1 d=000000 -- ! r1
rr5 d=006324 -- ! r5
rsp d=001400 -- ! sp
rpc d=005712 -- ! pc
wal 006300 -- use BCC/BCS naming below
brm 10
d=000000 -- ! mem(6300) 1 PS: none
d=052524 -- ! mem(6302) 1 BNE,BGE,BGT,BPL,BHI,BVC,BCC
d=000001 -- ! mem(6304) 2 PS: C=1
d=114524 -- ! mem(6306) 2 BNE,BGE,BGT,BPL,BLOS,BVC,BCS
d=000002 -- ! mem(6310) 3 PS: V=1
d=062644 -- ! mem(6312) 3 BNE,BLT,BLE,BPL,BHI,BVS,BCC
d=000004 -- ! mem(6314) 4 PS: Z=1
d=054630 -- ! mem(6316) 4 BEQ,BGE,BLE,BPL,BLOS,BVC,BCC
d=000010 -- ! mem(6320) 5 PS: N=1
d=053244 -- ! mem(6322) 5 BNE,BLT,BLE,BMI,BHI,BVC,BCC
#
C Exec test 23.2 (tst testing)
#
wr0 006220 -- r0=6220 (input data)
wr1 000003 -- r1=3
wr2 177776 -- r2=177776 (PS address)
wr5 006330 -- sp=6330 (output data)
wsp 001400 -- sp=1400
stapc 005720 -- start @ 5720
wtgo
rr0 d=006226 -- ! r0
rr1 d=000000 -- ! r1
rr5 d=006344 -- ! r5
rsp d=001400 -- ! sp
rpc d=005734 -- ! pc
wal 006330 -- use BHIS(BCC)/BLO(BLO) naming below
brm 6
d=000010 -- ! mem(6330) 1 PS: tst -1: N=1
d=053244 -- ! mem(6332) 1 BNE,BLT,BLE,BMI,BHI,BVC,BHIS
d=000004 -- ! mem(6334) 2 PS: tst 0: Z=1
d=054630 -- ! mem(6336) 2 BEQ,BGE,BLE,BPL,BLOS,BVC,BHIS
d=000000 -- ! mem(6340) 3 PS: tst 1: all 0
d=052524 -- ! mem(6342) 3 BNE,BGE,BGT,BPL,BHI,BVC,BHIS
#
C Exec test 23.3 (cmp testing)
#
wr0 006230 -- r0=6230 (input data)
wr1 000007 -- r1=7
wr2 177776 -- r2=177776 (PS address)
wr5 006344 -- sp=6344 (output data)
wsp 001400 -- sp=1400
stapc 005740 -- start @ 5740
wtgo
rr0 d=006264 -- ! r0
rr1 d=000000 -- ! r1
rr5 d=006400 -- ! r5
rsp d=001400 -- ! sp
rpc d=005754 -- ! pc
wal 006344 -- cmp= S-D !
brm 14
d=000011 -- ! mem(6344) 1 PS: cmp 1,2: N=1,C=1 ok
d=115244 -- ! mem(6346) 1 BNE,BLT,BLE,BMI,BLOS,BVC,BLO
d=000004 -- ! mem(6350) 2 PS: cmp 1,1: Z=1 ok
d=054630 -- ! mem(6352) 2 BEQ,BGE,BLE,BPL,BLOS,BVC,BHIS
d=000000 -- ! mem(6354) 3 PS: cmp 2,1: none ok
d=052524 -- ! mem(6356) 3 BNE,BGE,BGT,BPL,BHI,BVC,BHIS
d=000010 -- ! mem(6360) 4 PS: cmp -1,2: N=1
d=053244 -- ! mem(6362) 4 BNE,BLT,BLE,BMI,BHI,BVC,BHIS ok
d=000001 -- ! mem(6364) 5 PS: cmp 2,-1: C=1
d=114524 -- ! mem(6366) 5 BNE,BGE,BGT,BPL,BLOS,BVC,BLO ok
d=000002 -- ! mem(6370) 6 PS: cmp 10..,07..: V=1
d=062644 -- ! mem(6372) 6 BNE,BLT,BLE,BPL,BHI,BVS,BHIS ok
d=000013 -- ! mem(6374) 7 PS: cmp 07..,10..: N=1,V=1,C=1
d=125124 -- ! mem(6376) 7 BNE,BGE,BGT,BMI,BLOS,BVS,BLO ok
#
#-----------------------------------------------------------------------------
C Setup code 24 [base 6400] (test MARK instruction)
#
wal 006400 -- code (main):
bwm 13
010546 -- mov r5,-(sp) ; push old r5 on stack
012746 -- mov #101,-(sp) ; push 1st parameter
000101
012746 -- mov #102,-(sp) ; push 2nd parameter
000102
012746 -- mov #103,-(sp) ; push 3rd parameter
000103
012746 -- mov #mark3,-(sp) ; push MARK 3
#6420
006403
010605 -- mov sp,r5 ; address of MARK N
004737 -- jsr pc,@#6440 ; call procedure
006440
000000 -- halt
#
# stack of procedure when called:
# addr content
# 576 12(sp) 10(r5) old r5
# 574 10(sp) 6(r5) param1
# 572 6(sp) 4(r5) param2
# 570 4(sp) 2(r5) param3
# 566 2(sp) (r5) mark 3
# 564 (sp) return pc
#
wal 006440 -- code (procedure):
bwm 7
016520 -- mov 6(r5),(r0)+ ; get 1st param
000006
016520 -- mov 4(r5),(r0)+ ; get 2nd param
000004
016520 -- mov 2(r5),(r0)+ ; get 3rd param
000002
000205 -- rts r5
#
C Exec code 24 (test MARK instruction)
#
wr0 006470 -- r0=6470
wr5 123456 -- r5=123456
wsp 001400 -- sp=1400
stapc 006400 -- start @ 6400
wtgo
rr0 d=006476 -- ! r0=6476 (3 words written)
rr5 d=123456 -- ! r5 (restored)
rsp d=001400 -- ! sp
rpc d=006432 -- ! pc
wal 001364 -- check stack
brm 6
d=006430 -- ! mem(1364)
d=006403 -- ! mem(1366)
d=000103 -- ! mem(1370)
d=000102 -- ! mem(1372)
d=000101 -- ! mem(1374)
d=123456 -- ! mem(1376)
wal 006470 -- check stored values
brm 3
d=000101 -- ! mem(6470) (1st param)
d=000102 -- ! mem(6472) (2nd param)
d=000103 -- ! mem(6474) (3rd param)
#
# probably first and last time MARK is used. It's a bastard anyway.
#
#-----------------------------------------------------------------------------
C Setup code 25 [base 6500; use 65-66] (basic byte instruction and cc test)
#
wal 006500 -- code:
bwm 22
110124 -- movb r1,(r4)+ (#123, #333)
120124 -- cmpb r1,(r4)+ (#123, #333)
120224 -- cmpb r2,(r4)+ (#321, #111)
120124 -- cmpb r1,(r4)+ (#123, #123)
105024 -- clrb (r4)+ (#333)
130124 -- bitb r1,(r4)+ (#123, #11)
130124 -- bitb r1,(r4)+ (#123, #44)
140124 -- bicb r1,(r4)+ (#123, #333)
#6520
150124 -- bisb r1,(r4)+ (#123, #111)
105124 -- comb (r4)+ (#321)
105224 -- incb (r4)+ (#321)
105324 -- decb (r4)+ (#321)
105424 -- negb (r4)+ (#321)
105724 -- tstb (r4)+ (#321)
106024 -- rorb (r4)+ (#201) Cin=0; Cout=1
106024 -- rorb (r4)+ (#021) Cin=1; Cout=1
#6540
106124 -- rolb (r4)+ (#210) Cin=1; Cout=1
106224 -- asrb (r4)+ (#020)
106224 -- asrb (r4)+ (#220)
106324 -- aslb (r4)+ (#020)
106324 -- aslb (r4)+ (#220)
000000 -- halt
#
wal 000014 -- vector: 14
bwm 2
006560 -- PC:6560
000000 -- PS:0
#
wal 006560 -- code: (trap 14):
bwm 3
016625 -- mov 2(sp),(r5)+
000002
000006 -- rtt
#
wal 006600 -- data 1:
bwm 11
155733 -- (#333,#333)
051511 -- (#123,#111)
044333 -- (#11 ,#333)
155444 -- (#333,#44)
150511 -- (#321,#111)
150721 -- (#321,#321)
150721 -- (#321,#321)
010601 -- (#021,#201)
#6620
010210 -- (#020,#210)
010220 -- (#020,#220)
000220 -- (....,#220)
#
C Exec code 25 (basic byte instruction and cc test)
#
wr1 000123 -- r1=123
wr2 000321 -- r2=321
wr4 006600 -- r4=6600
wr5 006626 -- r5=6626
wsp 001374 -- sp=1374
wal 001374 -- setup stack with rtt return frame setting T flag
bwm 2
006500 -- start address (code 25 @ 6500)
000020 -- set T flag in PSW
stapc 006564 -- start @ 6564 -> rtt -> 6500 from stack
wtgo
rr1 d=000123 -- ! r1=123
rr2 d=000321 -- ! r2=321
rr4 d=006625 -- ! r4=6625
rr5 d=006700 -- ! r5=6700
rsp d=001400 -- ! sp=1400
rpc d=006554 -- ! pc=6554
wal 006600
brm 11
d=155523 -- ! mem(6600)=123; movb r1,(r4)+ (#123, #333)
# ! mem(6601)=333; cmpb r1,(r4)+ (#123, #333)
d=051511 -- ! mem(6602)=111; cmpb r1,(r4)+ (#321, #111)
# ! mem(6603)=123; cmpb r1,(r4)+ (#123, #123)
d=044000 -- ! mem(6604)=000; clrb (r4)+ (#333)
# ! mem(6605)=011; bitb r1,(r4)+ (#123, #11)
d=104044 -- ! mem(6606)=044; bitb r1,(r4)+ (#123, #44)
# ! mem(6607)=210; bicb r1,(r4)+ (#123, #333)
d=027133 -- ! mem(6610)=133; bisb r1,(r4)+ (#123, #111)
# ! mem(6611)=056; comb (r4)+ (#321)
d=150322 -- ! mem(6612)=322; incb (r4)+ (#321)
# ! mem(6613)=320; decb (r4)+ (#321)
d=150457 -- ! mem(6614)=057; negb (r4)+ (#321)
# ! mem(6615)=321; tstb (r4)+ (#321)
d=104100 -- ! mem(6616)=100; rorb (r4)+ (#201) Cout=1
# ! mem(6617)=210; rorb (r4)+ (#021) Cout=1
d=004021 -- ! mem(6620)=021; rolb (r4)+ (#210) Cout=1
# ! mem(6621)=010; asrb (r4)+ (#020)
d=020310 -- ! mem(6622)=310; asrb (r4)+ (#220)
# ! mem(6623)=040; aslb (r4)+ (#020)
d=000040 -- ! mem(6624)=040; aslb (r4)+ (#220)
#
wal 006626 -- NZVC
brm 21
d=000020 -- ! mem(6626)=0000; movb r1,(r4)+ (#123, #333)
d=000021 -- ! mem(6630)=000C; cmpb r1,(r4)+ (#123, #333)
d=000030 -- ! mem(6632)=N000; cmpb r1,(r4)+ (#321, #111)
d=000024 -- ! mem(6634)=0Z00; cmpb r1,(r4)+ (#123, #123)
d=000024 -- ! mem(6636)=0Z00; clrb (r4)+ (#333)
d=000020 -- ! mem(6640)=0000; bitb r1,(r4)+ (#123, #11)
d=000024 -- ! mem(6642)=0Z00; bitb r1,(r4)+ (#123, #44)
d=000030 -- ! mem(6644)=N000; bicb r1,(r4)+ (#123, #333)
d=000020 -- ! mem(6646)=0000; bisb r1,(r4)+ (#123, #111)
d=000021 -- ! mem(6650)=000C; comb (r4)+ (#321)
d=000031 -- ! mem(6652)=N00C; incb (r4)+ (#321) keep C!
d=000031 -- ! mem(6654)=N00C; decb (r4)+ (#321) keep C!
d=000021 -- ! mem(6656)=000C; negb (r4)+ (#321)
d=000030 -- ! mem(6660)=N000; tstb (r4)+ (#321)
d=000023 -- ! mem(6662)=00VC; rorb (r4)+ (#201)
d=000031 -- ! mem(6664)=N00C; rorb (r4)+ (#021)
d=000023 -- ! mem(6666)=00VC; rolb (r4)+ (#210)
d=000020 -- ! mem(6670)=0000; asrb (r4)+ (#020)
d=000032 -- ! mem(6672)=N0V0; asrb (r4)+ (#220)
d=000020 -- ! mem(6674)=0000; aslb (r4)+ (#020)
d=000023 -- ! mem(6676)=00VC; aslb (r4)+ (#220)
#
rst -- console reset (to clear T flag)
wal 000014 -- vector: 14 -> trap catcher again
bwm 2
000016 -- PC:16
000000 -- PS:0
#-----------------------------------------------------------------------------
C Setup code 26 [base 6700; use 67-70] (address modes torture tests)
#
wal 006700 -- code test 1:
bwm 5
012020 -- mov (r0)+,(r0)+
062020 -- add (r0)+,(r0)+
014141 -- mov -(r1),-(r1)
064141 -- add -(r1),-(r1)
#6710
000000 -- halt
#-----
wal 006720 -- code test 2:
bwm 8
016767 -- mov a(pc),b(pc)
000014 -- here pc=6724, target@6740 --> index=14
000014 -- here pc=6726, target@6742 --> index=14
066767 -- add c(pc),d(pc)
#6730
000012 -- here pc=6732, target@6744 --> index=12
000012 -- here pc=6734, target@6746 --> index=12
000000 -- halt
000000 -- halt
#
wal 006740 -- data (pc relative) for test 2:
bwm 4
006740 -- target for mov a(pc)
006742 -- target for ,b(pc)
000011 -- target for add c(pc)
006746 -- target for ,d(pc)
#-----
wal 006750 -- code test 3:
bwm 12
012727 -- mov #1,#0
000001
000000
062727 -- add #1,#2
#6760
000001
000002
016767 -- mov -14(pc),2(pc)
177764 -- pc here: 6770: read dst of mov #1,#0 (@6754)
000002 -- pc here: 6772: write src of add #0,r0 (@6774)
062700 -- add #0,r0
000000
000000 -- halt
#-----
wal 007000 -- code test 4:
bwm 8
005200 -- inc r0
010001 -- mov r0,r1
010702 -- mov pc,r2
005007 -- clr pc
000000 -- halt
000000 -- halt
005203 -- L1: inc r3
000000 -- halt
#-----
wal 000000 -- code test 4 (handler at address=0):
bwm 2
000137 -- jmp @#L1
007014
#-----
wal 007020 -- code test 5:
bwm 11
012707 -- mov #L2,pc
007032
000000 -- halt
000000 -- halt
000000 -- halt
062707 -- L2: add #2,pc
000002
005201 -- inc r1
#7040
005201 -- inc r1
005201 -- inc r1
000000 -- halt
#-----
wal 007060 -- data for test 1 (r0)+ part:
bwm 4
000111
000222
000333
000444
wal 007070 -- data for test 1 -(r1) part:
bwm 4
000111
000222
000333
000444
C Exec code 26 (address modes torture tests)
C Exec test 26.1 (test src-dst update hazards with (r0)+,(r0)+ ect):
#
wr0 007060 -- r0=7060 (input data for (r0)+...)
wr1 007100 -- r1=7100 (input data for -(r1)...)
wsp 001400 -- sp=1400
stapc 006700 -- start @ 6700
wtgo
rr0 d=007070 -- ! r0
rr1 d=007070 -- ! r1
rpc d=006712 -- ! pc
wal 007060 --
brm 4
d=000111 -- ! mem(7060)
d=000111 -- ! mem(7062)
d=000333 -- ! mem(7064)
d=000777 -- ! mem(7066)
wal 007070 --
brm 4
d=000333 -- ! mem(7070)
d=000222 -- ! mem(7072)
d=000444 -- ! mem(7074)
d=000444 -- ! mem(7076)
C Exec test 26.2 (test indexed mode with pc (mode 67)):
#
wsp 001400 -- sp=1400
stapc 006720 -- start @ 6720
wtgo
rpc d=006736 -- ! pc
wal 006740 --
brm 4
d=006740 -- ! mem(6740)
d=006740 -- ! mem(6742)
d=000011 -- ! mem(6744)
d=006757 -- ! mem(6746)
C Exec test 26.3 (test (pc)+ as dst):
#
wr0 000111 -- r0=0111
wsp 001400 -- sp=1400
stapc 006750 -- start @ 6750
wtgo
rr0 d=000112 -- ! r0
rpc d=007000 -- ! pc
wal 006752 --
brm 2
d=000001 -- ! mem(6752) src mov #1,#0
d=000001 -- ! mem(6754) dst mov #1,#0
wal 006760 --
brm 2
d=000001 -- ! mem(6760) src add #1,#2
d=000003 -- ! mem(6762) dst add #1,#2
wal 006774 -- !
rmi d=000001 -- ! mem(6774) dst mov -12(pc),2(pc)
C Exec test 26.4 (test pc as dst in clr):
#
wr0 000100 -- r0=0100
wr1 000110 -- r1=0110
wr2 000120 -- r2=0120
wr3 000130 -- r3=0130
wsp 001400 -- sp=1400
stapc 007000 -- start @ 7000
wtgo
rr0 d=000101 -- ! r0
rr1 d=000101 -- ! r1
rr2 d=007006 -- ! r2 (pc after mov pc,r2)
rr3 d=000131 -- ! r3
rpc d=007020 -- ! pc
# cleanup 'vector 0':
wal 000000
bwm 2
000000
000000
C Exec test 26.5 (test pc as dst in mov and add):
#
wr1 000000 -- r1=0
wsp 001400 -- sp=1400
stapc 007020 -- start @ 7020
wtgo
rr1 d=000002 -- ! r1
rpc d=007046 -- ! pc
#-----------------------------------------------------------------------------
C Setup code 27 [base 7100; use 71-101] (test ASH/ASHC instruction)
#
wal 007100 -- code test 1 (ash)
bwm 7
000230 -- spl 0
012004 -- L1: mov (r0)+,r4 -- load low
072420 -- ash (r0)+,r4 -- shift
011321 -- mov (r3),(r1)+ -- store psw
010421 -- mov r4,(r1)+ -- store low
077205 -- sob r2,L1 (.-5)
000000 -- halt
#-----
wal 007120 -- code test 2 (ashc even)
bwm 9
000230 -- spl 0
012004 -- L1: mov (r0)+,r4 -- load high
012005 -- mov (r0)+,r5 -- load low
073420 -- ashc (r0)+,r4 -- shift
011321 -- mov (r3),(r1)+ -- store psw
010421 -- mov r4,(r1)+ -- store high
010521 -- mov r5,(r1)+ -- store low
077207 -- sob r2,L1 (.-7)
#7140
000000 -- halt
#-----
wal 007150 -- code test 3 (ashc odd)
bwm 7
000230 -- spl 0
012005 -- L1: mov (r0)+,r5 -- load low
073520 -- ashc (r0)+,r5 -- shift
011321 -- mov (r3),(r1)+ -- store psw
#7160
010521 -- mov r5,(r1)+ -- store low
077205 -- sob r2,L1 (.-5)
000000 -- halt
#-----
wal 007200 -- data 1:
bwm 24
000200 -- (000200, +1)
000001 --
000200 -- (000200, -1)
177777 --
000200 -- (000200, +7)
000007 --
000200 -- (000200, +8)
000010 --
#7220
000200 -- (000200, +9)
000011 --
000200 -- (000200, -7)
177771 --
100000 -- (100000, 0)
000000 --
000000 -- (000000, 0)
000000 --
#7240
000200 -- (000200, -8)
177770 --
000200 -- (000200, 0)
000000 --
100000 -- (100000, -6)
177772 --
040000 -- (040000, +1)
000001 --
#-----
wal 007300 -- data 2:
bwm 30
000020 -- (000020,000200, +1)
000200 --
000001 --
000020 -- (000020,000200, -1)
000200 --
177777 --
000020 -- (000020,000200, +7)
000200 --
#7320
000007 --
000020 -- (000020,000200, +8)
000200 --
000010 --
000020 -- (000020,000200, +9)
000200 --
000011 --
000000 -- (000000,000200, +23)
#7340
000200 --
000027 --
000000 -- (000000,000200, +24)
000200 --
000030 --
000000 -- (000000,000200, +25)
000200 --
000031 --
#7360
000020 -- (000020,000200, -5)
000200 --
177773 --
000020 -- (000020,000200, -8)
000200 --
177770 --
#-----
wal 007440 -- data 3:
bwm 6
000200 -- (000200, +1)
000001 --
000200 -- (000200, -1)
177777 --
000201 -- (000201, -1)
177777 --
#
C Exec code 27 (test ASH/ASHC instruction)
C Exec test 27.1 (test ash)
#
wr0 007200 -- r0=7200 (input data)
wr1 007500 -- r1=7500 (output data)
wr2 000014 -- r2=14 (test count)
wr3 177776 -- r3=177776 (#PSW)
wsp 001400 -- sp=1400
stapc 007100 -- start @ 7100
wtgo
rr0 d=007260 -- ! r0
rr1 d=007560 -- ! r1
rpc d=007116 -- ! pc
wal 007500 --
brm 24
d=000000 -- ! mem(7500) ash +1, 000200 -> nzvc=0
d=000400 -- ! mem(7502)
d=000000 -- ! mem(7504) ash -1, 000200 -> nzvc=0
d=000100 -- ! mem(7506)
d=000000 -- ! mem(7510) ash +7, 000200 -> nzvc=0
d=040000 -- ! mem(7512)
d=000012 -- ! mem(7514) ash +8, 000200 -> n1,z0,v1,c0
d=100000 -- ! mem(7516)
d=000007 -- ! mem(7520) ash +9, 000200 -> n0,z1,v1,c1
d=000000 -- ! mem(7522)
d=000000 -- ! mem(7524) ash -7, 000200 -> nzvc=0
d=000001 -- ! mem(7526)
d=000010 -- ! mem(7530) ash 0, 100000 -> n1,z0,v0,c0
d=100000 -- ! mem(7532)
d=000004 -- ! mem(7534) ash 0, 000000 -> n0,z1,v0,c0
d=000000 -- ! mem(7536)
d=000005 -- ! mem(7540) ash -8, 000200 -> n1,z1,v0,c1
d=000000 -- ! mem(7542)
d=000000 -- ! mem(7544) ash 0, 000200 -> n0,z0,v0,c0
d=000200 -- ! mem(7546)
d=000010 -- ! mem(7550) ash -6, 100000 -> n1,z0,v0,c0
d=177000 -- ! mem(7552)
d=000012 -- ! mem(7554) ash +1, 040000 -> n1,z0,v1,c0
d=100000 -- ! mem(7556)
#----
C Exec test 27.2 (test ashc even)
#
wr0 007300 -- r0=7300 (input data)
wr1 007600 -- r1=7600 (output data)
wr2 000012 -- r2=12 (test count)
wr3 177776 -- r3=177776 (#PSW)
wsp 001400 -- sp=1400
stapc 007120 -- start @ 7120
wtgo
rr0 d=007374 -- ! r0
rr1 d=007674 -- ! r1
rpc d=007142 -- ! pc
wal 007600 --
brm 30
d=000000 -- ! mem(7600) ashc +1, 000020,000200 -> nzvc=0
d=000040 -- ! mem(7602)
d=000400 -- ! mem(7604)
d=000000 -- ! mem(7606) ashc -1, 000020,000200 -> nzvc=0
d=000010 -- ! mem(7610)
d=000100 -- ! mem(7612)
d=000000 -- ! mem(7614) ashc +7, 000020,000200 -> nzvc=0
d=004000 -- ! mem(7616)
d=040000 -- ! mem(7620)
d=000000 -- ! mem(7622) ashc +8, 000020,000200 -> nzvc=0
d=010000 -- ! mem(7624)
d=100000 -- ! mem(7626)
d=000000 -- ! mem(7630) ashc +9, 000020,000200 -> nzvc=0
d=020001 -- ! mem(7632)
d=000000 -- ! mem(7634)
d=000000 -- ! mem(7636) ashc +23, 000000,000200 -> nzvc=0
d=040000 -- ! mem(7640)
d=000000 -- ! mem(7642)
d=000012 -- ! mem(7644) ashc +24, 000000,000200 -> n1z0v1c0
d=100000 -- ! mem(7646)
d=000000 -- ! mem(7650)
d=000007 -- ! mem(7652) ashc +25, 000000,000200 -> n0z1v1c1
d=000000 -- ! mem(7654)
d=000000 -- ! mem(7656)
d=000000 -- ! mem(7660) ashc -5, 000020,000200 -> nzvc=0
d=000000 -- ! mem(7662)
d=100004 -- ! mem(7664)
d=000001 -- ! mem(7666) ashc -8, 000020,000200 -> n0z0v0c1
d=000000 -- ! mem(7670)
d=010000 -- ! mem(7672)
#----
C Exec test 27.3 (test ashc odd)
#
wr0 007440 -- r0=7440 (input data)
wr1 007740 -- r1=7740 (output data)
wr2 000003 -- r2=3 (test count)
wr3 177776 -- r3=177776 (#PSW)
wsp 001400 -- sp=1400
stapc 007150 -- start @ 7150
wtgo
rr0 d=007454 -- ! r0
rr1 d=007754 -- ! r1
rpc d=007166 -- ! pc
wal 007740 --
brm 6
d=000000 -- ! mem(7740) ashc +1, 000200 -> nzvc=0
d=000400 -- ! mem(7742)
d=000000 -- ! mem(7744) ashc -1, 000200 -> nzvc=0
d=000100 -- ! mem(7746)
d=000001 -- ! mem(7750) ashc -1, 000201 -> n0z0v0c1
d=100100 -- ! mem(7752)
#-----------------------------------------------------------------------------
C Setup code 30 [base 10200; use 102-103] (test MUL instruction)
#
wal 010200 -- code test 1 (mul even)
bwm 8
000230 -- spl 0
012004 -- L1: mov (r0)+,r4 -- load p1
070420 -- mul (r0)+,r4 -- mul
011321 -- mov (r3),(r1)+ -- store psw
010421 -- mov r4,(r1)+ -- store p_high
010521 -- mov r5,(r1)+ -- store p_low
077206 -- sob r2,L1 (.-6)
000000 -- halt
#-----
wal 010220 -- code test 2 (mul odd)
bwm 7
000230 -- spl 0
012005 -- L1: mov (r0)+,r5 -- load p1
070520 -- mul (r0)+,r5 -- mul
010521 -- mov r5,(r1)+ -- store p_low
060403 -- add r4,r3 -- check r4
077205 -- sob r2,L1 (.-5)
000000 -- halt
#
# 31022 074456 * 9562 022532 -> 296632364 010656,040054
# 18494 044076 * -24041 121027 -> -444614254 162577,134622
# -12549 147373 * 2397 004535 -> -30079953 177065,002057
# -20493 127763 * -23858 121316 -> 488921994 016444,055612
#
# 105 000151 * 198 000306 -> 20790 000000,050466
# 233 000351 * -94 177642 -> -21902 177777,125162
# 186 000272 * -205 177463 -> -38130 177777,065416
#
wal 010240 -- data 1:
bwm 16
074456 --
022532 --
044076 --
121027 --
147373 --
004535 --
127763 --
121316 --
#10260
000151 --
000306 --
000351 --
177642 --
000272 --
177463 --
000000 --
000272 --
#
C Exec code 30 (test MUL instruction)
C Exec test 30.1 (test mul even)
#
wr0 010240 -- r0=10240 (input data)
wr1 010300 -- r1=10300 (output data)
wr2 000010 -- r2=10 (test count)
wr3 177776 -- r3=177776 (#PSW)
wsp 001400 -- sp=1400
stapc 010200 -- start @ 10200
wtgo
rr0 d=010300 -- ! r0
rr1 d=010360 -- ! r1
rpc d=010220 -- ! pc
wal 010300 --
brm 24
d=000001 -- ! mem(10300) mul 074456,022532 -> n0z0v0c1
d=010656 -- ! mem(10302)
d=040054 -- ! mem(10304)
d=000011 -- ! mem(10306) mul 044076,121027 -> n1z0v0c1
d=162577 -- ! mem(10310)
d=134622 -- ! mem(10312)
d=000011 -- ! mem(10314) mul 147373,004535 -> n1z0v0c1
d=177065 -- ! mem(10316)
d=002057 -- ! mem(10320)
d=000001 -- ! mem(10322) mul 127763,121316 -> n0z0v0c1
d=016444 -- ! mem(10324)
d=055612 -- ! mem(10326)
d=000000 -- ! mem(10330) mul 000151,000306 -> n0z0v0c0
d=000000 -- ! mem(10332)
d=050466 -- ! mem(10334)
d=000010 -- ! mem(10336) mul 000351,177642 -> n1z0v0c0
d=177777 -- ! mem(10340)
d=125162 -- ! mem(10342)
d=000011 -- ! mem(10344) mul 000272,177463 -> n1z0v0c1
d=177777 -- ! mem(10346)
d=065416 -- ! mem(10350)
d=000004 -- ! mem(10352) mul 000000,000272 -> n0z1v0c0
d=000000 -- ! mem(10354)
d=000000 -- ! mem(10356)
#----
C Exec test 30.2 (test mul odd)
#
wr0 010240 -- r0=10240 (input data)
wr1 010360 -- r1=10300 (output data)
wr2 000010 -- r2=10 (test count)
wr3 000000 -- r3=0
wr4 000000 -- r4=0
wsp 001400 -- sp=1400
stapc 010220 -- start @ 10220
wtgo
rr0 d=010300 -- ! r0
rr1 d=010400 -- ! r1
rr3 d=000000 -- ! r3
rpc d=010236 -- ! pc
wal 010360 --
brm 8
d=040054 -- ! mem(10360)
d=134622 -- ! mem(10362)
d=002057 -- ! mem(10364)
d=055612 -- ! mem(10366)
d=050466 -- ! mem(10370)
d=125162 -- ! mem(10372)
d=065416 -- ! mem(10374)
d=000000 -- ! mem(10376)
#
#-----------------------------------------------------------------------------
C Setup code 31 [base 10400; use 104-110] (test DIV instruction, also ADC,SXT)
# Note: test 2 uses sbc too, but if div/div work correctly we have always
# C=0 for sbc, so sbc isn't tested. adc has C=0 or C=1 though.
#
wal 010400 -- code test 1
bwm 8
012004 -- L1: mov (r0)+,r4 -- load dd high
012005 -- mov (r0)+,r5 -- load dd low
071420 -- div (r0)+,r4 -- div
011321 -- mov (r3),(r1)+ -- store psw
010421 -- mov r4,(r1)+ -- store q
010521 -- mov r5,(r1)+ -- store r
077207 -- sob r2,L1 (.-7)
000000 -- halt
#-----
wal 010420 -- code test 2
bwm 24
012146 -- L1: mov (r1)+,-(sp) -- save psw on stack
016002 -- mov 4(r0),r2 -- load divisor
000004
070221 -- mul (r1)+,r2 -- multiply with quotient
061103 -- add (r1),r3 -- add reminder
005502 -- adc r2
005721 -- tst (r1)+
006704 -- sxt r4
#10440
060402 -- add r4,r2
166003 -- sub 2(r0),r3 -- subtract divident
000002
005602 -- sbc r2
161002 -- sub (r0),r2
001002 -- bne L2 (.+2) -- error if !=0
005703 -- tst r3
001404 -- beq L3 (.+4) -- error if !=0
#10460
032726 -- L2: bit #3,(sp)+ -- check V,C bits
000003
001001 -- bne L3 (.+1) -- if V or C =1, ignore
000000 -- halt
062700 -- L3: add #6,r0 --
000006 --
077527 -- sob r5,L1 (.-23)
000000 -- halt
# r q
# 6249 014151 * 9158 021706 + 4989 011575 -> 57233331 001551,047663 y n
# 5194 012112 * -23807 121401 + -3990 170152 -> -123657548 174241,021264 n y
# -19943 131031 * 27112 064750 + -16037 140533 -> -540710653 157705,064403 y n
# -20493 127763 * -23858 121316 + 10744 024770 -> 488932738 016444,102602 y y
#
# -12549 147373 * 2397 004535 + -11187 152115 -> -30091140 177064,154174 n n
# 22620 054134 * -9272 155710 + -19907 131075 -> -209752547 171577,067035 y y
# 10723 024743 * 7931 017373 + 9824 023140 -> 85053937 002421,150761 n n
# -3548 171044 * -15677 141303 + 3019 005713 -> 55625015 001520,142467 n y
#
## 1 000001 * -32767 100001 + 0 000000 -> -32767 177777,100001 V=0
## -1 177777 * 32767 077777 + 0 000000 -> -32767 177777,100001 V=0
# 1 000001 * -32768 100000 + 0 000000 -> -32768 177777,100000 V=1
# -1 177777 * ...... ...... + 0 000000 -> -32768 177777,100000 V=1
#
# 32767 077777 * 32767 077777 + 32766 077776 -> 1073709055 037777,077777 V=0
# 32767 077777 * ............ + ............ -> 1073709056 037777,100000 V=1
# 32767 077777 * -32767 100001 + -32766 100002 ->-1073709055 140000,100001 V=0
# 32767 077777 * ............ + ............ ->-1073709056 140000,100000 V=1
#
# 32767 077777 * ............ + ............ -> 1073741824 040000,000000 V=1
##32767 077777 * ............ + ............ ->-2147483648 100000,000000 V=1
#
#
wal 010500 -- data 1:
bwm 63
000000 -- (000000,000042, 000005) 34/ 5 -> q: 6 r: 4
000042 --
000005 --
000000 -- (000000,000042, 177773) 34/-5 -> q:-6 r: 4
000042 --
177773 --
177777 -- (177777,177736, 000005) -34/ 5 -> q:-6 r:-4
177736 --
#010520
000005 --
177777 -- (177777,177736, 177773) -34/-5 -> q: 6 r:-4
177736 --
177773 --
001551 -- (001551,047663, 014151) 57233331 / 6249
047663 -- -> q: 9158 r: 4989
014151 --
174241 -- (174241,021264, 012112) -123657548 / 5194
#010540
021264 -- -> q: -23807 r: -3990
012112 --
157705 -- (157705,064403, 131031) -540710653 / -19943
064403 -- -> q: 27112 r: -16037
131031 --
016444 -- (016444,102602, 127763) 488932738 / -20493
102602 -- -> q: -23858 r: 10744
127763 --
#010560
177064 -- (177064,154174, 147373) -30091140 / -12549
154174 -- -> q: 2397 r: -11187
147373 --
171577 -- (171577,067035, 054134) -209752547 / 22620
067035 -- -> q: -9272 r: -19907
054134 --
002421 -- (002421,150761, 024743) 85053937 / 10723
150761 -- -> q: 7931 r: 9824
#010600
024743 --
001520 -- (001520,142467, 171044) 55625015 / -3548
142467 -- -> q: -15677 r: 3019
171044 --
001520 -- (001520,142467,000000) 55625015 / 0
142467 --
000000 --
000000 -- (000000,000000,021706) 0 / 9158
#010620
000000 --
021706 --
177777 -- (177777,100000,000001) -32768 / 1
100000 --
000001 --
177777 -- (177777,100000,177777) -32768 / -1
100000 --
177777 --
#010640
037777 -- (037777,077777,077777) 1073709055 / 32767
077777 --
077777 --
037777 -- (037777,100000,077777) 1073709056 / 32767
100000 --
077777 --
140000 -- (140000,100001,077777) -1073709055 / 32767
100001 --
#010660
077777 --
140000 -- (140000,100000,077777) -1073709056 / 32767
100000 --
077777 --
040000 -- (040000,000000,077777) 1073741824 / 32767
000000 --
077777 --
#
C Exec code 31 (test DIV instruction, also ADC,SXT)
C Exec test 31.1 (test div)
#
wr0 010500 -- r0=10500 (input data)
wr1 010700 -- r1=10700 (output data)
wr2 000025 -- r2=25 (test count)
wr3 177776 -- r3=177776 (#PSW)
wsp 001400 -- sp=1400
rst -- console reset ; do reset; cont to start with
wps 000000 -- clear psw ; psw cc code dump below
wpc 010400 -- pc=10400
cont -- cont @ 10400
wtgo
rr0 d=010676 -- ! r0
rr1 d=011076 -- ! r1
rpc d=010420 -- ! pc
wal 010700 --
brm 63
d=000000 -- ! mem(10700) div 000000, 000042,000005 -> n0z0v0c0
d=000006 -- ! mem(10702) 34/ 5 -> 6,4
d=000004 -- ! mem(10704)
d=000010 -- ! mem(10706) div 000000,000042, 177773 -> n1z0v0c0
d=177772 -- ! mem(10710) 34/-5 -> -6,4
d=000004 -- ! mem(10712)
d=000010 -- ! mem(10714) div 177777,177736, 000005 -> n1z0v0c0
d=177772 -- ! mem(10716) -34/ 5 -> -6,-4
d=177774 -- ! mem(10720)
d=000000 -- ! mem(10722) div 177777,177736, 177773 -> n0z0v0c0
d=000006 -- ! mem(10724) -34/-5 -> 6,-4
d=177774 -- ! mem(10726)
d=000000 -- ! mem(10730) div 001551,047663, 014151 -> n0z0v0c0
d=021706 -- ! mem(10732) 57233331/6249 -> 9158,4989
d=011575 -- ! mem(10734)
d=000010 -- ! mem(10736) div 174241,021264, 012112 -> n1z0v0c0
d=121401 -- ! mem(10740) -123657548/5194 -> -23807,-3990
d=170152 -- ! mem(10742)
d=000000 -- ! mem(10744) div 157705,064403, 131031 -> n0z0v0c0
d=064750 -- ! mem(10746) -540710653/-19943 -> 27112,-16037
d=140533 -- ! mem(10750)
d=000010 -- ! mem(10752) div 016444,102602, 127763 -> n1z0v0c0
d=121316 -- ! mem(10754) 488932738/-20493 -> -23858, 10744
d=024770 -- ! mem(10756)
d=000000 -- ! mem(10760) div 177064,154174, 147373 -> n0z0v0c0
d=004535 -- ! mem(10762) -30091140/-12549 -> 2397,-11187
d=152115 -- ! mem(10764)
d=000010 -- ! mem(10766) div 171577,067035, 054134 -> n1z0v0c0
d=155710 -- ! mem(10770) -209752547/22620 -> -9272,-19907
d=131075 -- ! mem(10772)
d=000000 -- ! mem(10774) div 002421,150761, 024743 -> n0z0v0c0
d=017373 -- ! mem(10776) 85053937/10723 -> 7931,9824
d=023140 -- ! mem(11000)
d=000010 -- ! mem(11002) div 001520,142467, 171044 -> n1z0v0c0
d=141303 -- ! mem(11004) 55625015/-3548 -> -15677,3019
d=005713 -- ! mem(11006)
d=000007 -- ! mem(11010) div 001520,142467,000000 -> n0z1v1c1
d=001520 -- ! mem(11012) 55625015/0 -> V=1, keep regs
d=142467 -- ! mem(11014)
d=000004 -- ! mem(11016) div 000000,000000,021706 -> n0z1v1c0
d=000000 -- ! mem(11020) 0/9158 -> 0,0
d=000000 -- ! mem(11022)
d=000012 -- ! mem(11024) div 177777,100000,000001->n1z0v1c0 [[s:10]]
d=177777 -- ! mem(11026) -32768/1 -> overflow [[s:100000]]
d=100000 -- ! mem(11030) [[s:000000]]
d=000002 -- ! mem(11032) div 177777,100000,177777 -> n0z0v1c0 ?? 2
d=177777 -- ! mem(11034) -32768/-1 -> overflow
d=100000 -- ! mem(11036)
d=000000 -- ! mem(11040) div 037777,077777,077777 -> n0z0v0c0
d=077777 -- ! mem(11042) 1073709055/32767 -> 32767,32766
d=077776 -- ! mem(11044)
d=000002 -- ! mem(11046) div 037777,100000,077777 -> n0z0v1c0
d=037777 -- ! mem(11050) 1073709056/32767 -> overflow
d=100000 -- ! mem(11052)
d=000010 -- ! mem(11054) div 140000,100001,077777 -> n1z0v0c0
d=100001 -- ! mem(11056) -1073709055/32767 -> -32767,-32766
d=100002 -- ! mem(11060)
d=000012 -- ! mem(11062) div 140000,100000,077777->n1z0v1c0 [[s:10]]
d=140000 -- ! mem(11064) -1073709056/32767 -> overflow [[s:100000]]
d=100000 -- ! mem(11066) [[s:000000]]
d=000002 -- ! mem(11070) div 040000,000000,077777 -> n0z0v1c0
d=040000 -- ! mem(11072) 1073741824/32767 -> overflow
d=000000 -- ! mem(11074)
#
# simh notes:
# 1. a quotient of 100000 leads to an overflow (V=1) on the W11
# simh will not indicate overflow and returns q=100000
#
#----
C Exec test 31.2 (test mul after div)
#
wr0 010500 -- r0=10500 (input data from DIV)
wr1 010700 -- r1=10700 (output data from DIV)
wr5 000016 -- r5=16 (test count)
wsp 001400 -- sp=1400
stapc 010420 -- start @ 10420
wtgo
rr0 d=010624 -- ! r0
rr1 d=011024 -- ! r1
rr2 d=000000 -- ! r2
rr3 d=000000 -- ! r3
rr5 d=000000 -- ! r5
rpc d=010500 -- ! pc
#-----------------------------------------------------------------------------
C Setup code 32 [base 11100; use 111-112] (PIRQ test)
# The code will exercise all 7 pirq interrupt levels:
# set 1+3 -> handle 3, set 7 -> handle 7, set 6+4 -> handle 6
# -> handle 4, set 5+2 -> handle 5 -> handle 2 > handle 1
#
wal 011100 -- code:
bwm 14
000237 -- spl 7
011425 -- mov (r4),(r5)+ ; save PSW
012713 -- mov #1000,(r3) ; set PIRQ 1
001000
011325 -- mov (r3),(r5)+ ; save PIRQ
112763 -- movb #12,1(r3) ; set PIRQ 1+3
000012
000001
#11120
011325 -- mov (r3),(r5)+ ; save PIRQ
000232 -- spl 2 ; now pri=2
000240 -- nop ; allow interrupt to happen
000230 -- spl 0 ; now pri=0
#11130
000240 -- nop ; allow interrupt to happen
000000 -- halt
#-----
wal 000240 -- vector: 240
bwm 2
011134 -- PC:11134
000340 -- PS:pri=7
#-----
wal 011134 -- code: (vector 240)
bwm 18
011300 -- mov (r3),r0 ; get pirq
010625 -- mov sp,(r5)+ ; save sp
#11140
010025 -- mov r0,(r5)+ ; save pirq
110014 -- movb r0,(r4) ; PSW=PIRQ (sets priority)
042700 -- bic #177761,r0 ; mask out index bits
177761
010001 -- mov r0,r1 ; r0 is word index (pri*2)
006201 -- asr r1 ; r1 is byte index (pri*1)
012702 -- mov #400,r2
000400
#11160
072201 -- ash r1,r2 ; r2 = 1<<(pri)
040213 -- bic r2,(r3) ; clear current level in pirq
010246 -- mov r2,-(sp) ; save pirq level mask
056013 -- bis 11200(r0),(r3) ; trigger new pirq's
011200
000240 -- noop
012625 -- mov (sp)+,(r5)+ ; save pirq level mask
000002 -- rti
#11200
#-----
wal 011200 -- data:
bwm 8
000000 -- mem(11200)=0 ; new pirq @ level 0
000000 -- mem(11202)=0 ; new pirq @ level 1
000000 -- mem(11204)=0 ; new pirq @ level 2
100000 -- mem(11206)=100000 ; new pirq @ level 3 -> 7
022000 -- mem(11210)=022000 ; new pirq @ level 4 -> 5+2
000000 -- mem(11212)=0 ; new pirq @ level 5
000000 -- mem(11214)=0 ; new pirq @ level 6
050000 -- mem(11216)=050000 ; new pirq @ level 7 -> 6+4
#
C Exec code 32 (PIRQ test)
#
wr3 177772 -- r3=177772 (#PIRQ)
wr4 177776 -- r4=177776 (#PSW)
wr5 011220 -- r1=11220 (output data)
wsp 001400 -- sp=1400
stapc 011100 -- start @ 11100
wtgo
rr5 d=011300 -- ! r5
rsp d=001400 -- ! sp
rpc d=011134 -- ! pc
rps d=000000 -- ! PSW
wal 177772 --
rmi d=000000 -- ! PIRQ
wal 011220 --
brm 24
d=000340 -- ! mem(11220) PSW after SPL 7
d=001042 -- ! mem(11222) PIRQ when 1 set
d=005146 -- ! mem(11224) PIRQ when 1+3 set
d=001374 -- ! mem(11226) -> PI:3 SP
d=005146 -- ! mem(11230) PIRQ (3+1 pending)
d=001366 -- ! mem(11232) -> PI:7 SP
d=101356 -- ! mem(11234) PIRQ (7+1 pending)
d=100000 -- ! mem(11236) <- PI:7 mask
d=001366 -- ! mem(11240) -> PI:6 SP
d=051314 -- ! mem(11242) PIRQ (6+4+1 pending)
d=040000 -- ! mem(11244) <- PI:6 mask
d=001366 -- ! mem(11246) -> PI:4 SP
d=011210 -- ! mem(11250) PIRQ (4+1 pending)
d=001360 -- ! mem(11252) -> PI:5 SP
d=023252 -- ! mem(11254) PIRQ (5+2+1 pending)
d=020000 -- ! mem(11256) <- PI:5 mask
d=010000 -- ! mem(11260) <- PI:4 mask
d=004000 -- ! mem(11262) <- PI:3 mask
d=001374 -- ! mem(11264) -> PI:2 SP
d=003104 -- ! mem(11266) PIRQ
d=002000 -- ! mem(11270) <- PI:2 mask
d=001374 -- ! mem(11272) -> PI:1 SP
d=001042 -- ! mem(11274) PIRQ
d=001000 -- ! mem(11276) <- PI:1 mask
#
wal 000240 -- vector: 240 -> trap catcher again
bwm 2
000242 -- PC:242
000000 -- PS:0
#-----------------------------------------------------------------------------
C Setup code 33 [base 11200; use 112-113] (adc(b) and sbc(b) test)
#
wal 011200 -- code test 1: (adc)
bwm 5
006020 -- L1: ror (r0)+
005520 -- adc (r0)+
006120 -- rol (r0)+
077104 -- sob r1,L1 (.-4)
000000 -- halt
#-----
wal 011220 -- code test 2: (sbc)
bwm 5
006020 -- L1: ror (r0)+
005620 -- sbc (r0)+
006120 -- rol (r0)+
077104 -- sob r1,L1 (.-4)
000000 -- halt
#-----
wal 011240 -- code test 3: (adcb)
bwm 5
006020 -- L1: ror (r0)+
105520 -- adcb (r0)+
106120 -- rolb (r0)+
077104 -- sob r1,L1 (.-4)
000000 -- halt
#-----
wal 011260 -- code test 4: (sbcb)
bwm 5
006020 -- L1: ror (r0)+
105620 -- sbcb (r0)+
106120 -- rolb (r0)+
077104 -- sob r1,L1 (.-4)
000000 -- halt
#-----
wal 011300 -- data test 1: (adc)
bwm 9
000000 -- 177776 + 0 -> 177776 + 0
177776
000000
000001 -- 177776 + 1 -> 177777 + 0
177776
000000
000001 -- 177777 + 1 -> 000000 + 1
177777
000000
#-----
wal 011324 -- data test 2: (sbc)
bwm 9
000000 -- 000002 - 0 -> 000002 - 0
000002
000000
000001 -- 000002 - 1 -> 000001 - 0
000002
000000
000001 -- 000000 - 1 -> 177777 - 1
000000
000000
#-----
wal 011350 -- data test 3: (adcb)
bwm 6
000000 -- 376 + 0 -> 376 + 0
000376
000001 -- 376 + 1 -> 377 + 0
000376
000001 -- 377 + 1 -> 000 + 1
000377
#-----
wal 011364 -- data test 4: (sbcb)
bwm 6
000000 -- 002 - 0 -> 002 - 0
000002
000001 -- 002 - 1 -> 001 - 0
000002
000001 -- 000 - 1 -> 337 - 1
000000
#
C Exec code 33 (adc and sbc test)
C Exec test 33.1 (adc)
#
wr0 011300 -- r0=11300
wr1 000003 -- r1=3
wsp 001400 -- sp=1400
stapc 011200 -- start @ 11200
wtgo
rr0 d=011322 -- ! r0=11322
rpc d=011212 -- ! pc
wal 011300
brm 9
d=000000 -- ! mem(11300)=000000 -- 177776 + 0 -> 177776 + 0
d=177776 -- ! mem(11302)=000000
d=000000 -- ! mem(11304)=000000
d=000000 -- ! mem(11306)=000000 -- 177776 + 1 -> 177777 + 0
d=177777 -- ! mem(11310)=000000
d=000000 -- ! mem(11312)=000000
d=000000 -- ! mem(11314)=000000 -- 177777 + 1 -> 000000 + 1
d=000000 -- ! mem(11316)=000000
d=000001 -- ! mem(11320)=000000
#----
C Exec test 33.2 (sbc)
#
wr0 011324 -- r0=11324
wr1 000003 -- r1=3
wsp 001400 -- sp=1400
stapc 011220 -- start @ 11220
wtgo
rr0 d=011346 -- ! r0=11346
rpc d=011232 -- ! pc
wal 011324
brm 9
d=000000 -- ! mem(11324)=000000 -- 000002 - 0 -> 000002 - 0
d=000002 -- ! mem(11326)=000000
d=000000 -- ! mem(11330)=000000
d=000000 -- ! mem(11332)=000000 -- 000002 - 1 -> 000001 - 0
d=000001 -- ! mem(11334)=000000
d=000000 -- ! mem(11336)=000000
d=000000 -- ! mem(11340)=000000 -- 000000 - 1 -> 177777 - 1
d=177777 -- ! mem(11342)=000000
d=000001 -- ! mem(11344)=000000
#----
C Exec test 33.3 (adcb)
#
wr0 011350 -- r0=11350
wr1 000003 -- r1=3
wsp 001400 -- sp=1400
stapc 011240 -- start @ 11240
wtgo
rr0 d=011364 -- ! r0=11364
rpc d=011252 -- ! pc
wal 011350
brm 6
d=000000 -- ! mem(11350)=000000 -- 376 + 0 -> 376 + 0
d=000376 -- ! mem(11352)=000000
d=000000 -- ! mem(11354)=000000 -- 376 + 1 -> 377 + 0
d=000377 -- ! mem(11356)=000000
d=000000 -- ! mem(11360)=000000 -- 377 + 1 -> 000 + 1
d=000400 -- ! mem(11362)=000000
#----
C Exec test 33.4 (sbcb)
#
wr0 011364 -- r0=11364
wr1 000003 -- r1=3
wsp 001400 -- sp=1400
stapc 011260 -- start @ 11260
wtgo
rr0 d=011400 -- ! r0=11400
rpc d=011272 -- ! pc
wal 011364
brm 6
d=000000 -- ! mem(11364)=000000 -- 002 - 0 -> 002 - 0
d=000002 -- ! mem(11366)=000000
d=000000 -- ! mem(11370)=000000 -- 002 - 1 -> 001 - 0
d=000001 -- ! mem(11372)=000000
d=000000 -- ! mem(11374)=000000 -- 000 - 1 -> 337 - 1
d=000777 -- ! mem(11377)=000000
#-----------------------------------------------------------------------------
C Setup code 34 [base 11400; use 114-115] (11/34 self test code)
# code adapted from M9312 23-248F1 console PROM, the 11/04-34 Diagnostic PROM
#
wal 011400 -- code:
bwm 51
005000 -- clr r0 ; r0=000000 c=0
005200 -- inc r0 ; r0=000001 c=0
005100 -- com r0 ; r0=177776 c=1
006200 -- asr r0 ; r0=177777 c=0
006300 -- asl r0 ; r0=177776 c=1
006000 -- ror r0 ; r0=177777 c=0
005700 -- tst r0 ; r0=177777 c=0 ?impact unclear?
005400 -- neg r0 ; r0=000001 c=1
#11420
005300 -- dec r0 ; r0=000000 c=1
005600 -- sbc r0 ; r0=177777 c=1
006100 -- rol r0 ; r0=177777 c=1
005500 -- adc r0 ; r0=000000 c=1
000300 -- swab r0 ; r0=000000 c=0
001401 -- beq .+1 ;
000000 -- halt ;
012702 -- mov #data0,r2 ; r2=011560
#11440
011560
011203 -- mov (r2),r3 ; r2=011560 r3=011560
022203 -- cmp (r2)+,r3 ; r2=011562 r3=011560
001401 -- beq .+1 ;
000000 -- halt ;
063203 -- add @(r2)+,r3 ; r2=011564 r3=<2*11560>
165203 -- sub @-(r2),r3 ; r2=011562 r3=011560
044203 -- bic -(r2),r3 ; r2=011560 r3=000000
#11460
056203 -- bis 12(r2),r3 ; r2=011560 r3=011566
000012
037203 -- bis @12(r2),r3 ; r2=011560 r3=011566
000012
001001 -- bne .+1 ;
000000 -- halt ;
010701 -- mov pc,r1 ; r1=011476
000121 -- jmp (r1)+ ; jump 1.self 2. next; r1=011500
#11500
012701 -- mov #L2,r1 ; r1=011510
011510
000131 -- jmp @(r1)+ ; r1=011512 pc=011506
000111 -- L1:jmp (r1) ; r1=011512 pc=011512
011506 -- L2:.word L1
105737 -- tstb data1 ;
011564
001401 -- beq .+1 ;
#11520
000000 -- halt ;
010204 -- mov r2,r4 ; keep r2 for later check
022424 -- cmp (r4)+,(r4)+ ; r4=011564
105724 -- tstb (r4)+ ; r4=011565 (r4)+=000
001401 -- beq .+1 ;
000000 -- halt ;
105714 -- tstb (r4) ; r4=011565 (r4)=200
100402 -- bmi .+2 ;
#11540
000000 -- halt ;
000000 -- halt ;
000000 -- halt ;
#-----
wal 011560 -- data:
bwm 8
011560 -- data0: .word data0
011560 -- .word data0
100000 -- data1: .byte 000,200
177777 -- data2: .word 177777
011566 -- .word data2
011566 -- .word data2
000700 -- .word mem+0
000701 -- .word mem+1
#
C Exec code 34 (11/34 self test code)
# D RE RQ FU DAT
stapc 011400 -- start @ 11400
wtgo
rr0 d=000000 -- ! r0
rr1 d=011512 -- ! r1
rr2 d=011560 -- ! r2
rr3 d=011566 -- ! r3
rr4 d=011565 -- ! r4
rpc d=011546 -- ! pc
#-----------------------------------------------------------------------------
C Setup code 35 [base 11600; use 116-121] (11/70 self test code)
# code adapted from M9312 23-616F1 console PROM, the 11/60-70 Diagnostic PROM
#
wal 011600 -- code:
bwm 117
005006 -- clr sp ; sp=000000
100404 -- bmi L3 ;
102403 -- bvs L3 ;
101002 -- bhi L3 ;
002401 -- blt L3 ;
101401 -- blos L4 ;
000000 -- L3: halt ;
005306 -- L3: dec sp ; sp=177777
#11620
100003 -- bpl L5 ;
001402 -- beq L5 ;
002001 -- bge L5 ;
003401 -- ble L6 ;
000000 -- L5: halt ;
006006 -- L6: ror sp ; sp=077777
102002 -- bvc L7 ;
103001 -- bcc L7 ;
#11640
001001 -- bne L8 ;
000000 -- L7: halt ;
012706 -- L8: mov #125252,sp ; sp=125252
125252
010600 -- mov sp,r0 ;
010001 -- mov r0,r1 ;
010102 -- mov r1,r2 ;
010203 -- mov r2,r3 ;
#11660
010304 -- mov r3,r4 ;
010405 -- mov r4,r5 ;
160501 -- sub r5,r1 ; r1=00000
002401 -- blt L9a ;
001401 -- beq L9 ;
000000 -- L9a: halt ;
006102 -- L9: rol r2 ; r2=052524 c=1
103001 -- bcc L10 ;
#11700
002401 -- blt L11 ;
000000 -- L10: halt ;
060203 -- L11: add r2,r3 ; r3=177776 (125252+052524)
005203 -- inc r3 ; r3=177777
005103 -- com r3 ; r3=000000
060301 -- add r3,r1 ; r1=000000 c=0
103401 -- bcs L12 ;
003401 -- ble L13 ;
#11720
000000 -- L12: halt ;
006004 -- L13: ror r4 ; r4=052525
050403 -- bis r4,r3 ; r3=052525 (r3 was 0)
060503 -- add r5,r3 ; r3=177777 c=0 (125252+052525)
005203 -- inc r3 ; r3=000000 c=0 (kept)
103402 -- bcs L14 ;
005301 -- dec r1 ; r1=177777
002401 -- blt L15 ;
#11740
000000 -- L14: halt ;
005100 -- L15: com r0 ; r0=052525
101401 -- blos L16 ;
000000 -- halt ;
040001 -- L16: bic r0,r1 ; r1=125252
060101 -- L16: add r1,r1 ; r1=052524 c=1
003001 -- bgt L17 ;
003401 -- ble L18 ;
#11760
000000 -- L17: halt ;
000301 -- L18: swab r1 ; r1=052125
020127 -- cmp r1,#052125 ;
052125
001004 -- bne L19 ;
030405 -- bit r4,r5 ;
003002 -- bgt L19 ;
005105 -- com r5 ; r5=052525
#12000
001001 -- bne L20 ;
000000 -- L19: halt ;
112700 -- L20: movb #177401,r0 ;
177401
100001 -- bpl L21 ;
000000 -- L22: halt ;
077002 -- L21: sob r0,L22 ;
000261 -- sec ; c=1
#12020
006100 -- rol r0 ; r0=000001
006100 -- rol r0 ; r0=000002
006100 -- rol r0 ; r0=000004
010001 -- mov r0,r1 ; r1=000004
005401 -- neg r1 ; r1=177774
005201 -- L23: inc r1 ;
077002 -- sob r0,L23 ;
005700 -- tst r0 ; here r0=r1=0
#12040
001002 -- bne L24 ;
005701 -- tst r1 ;
001401 -- beq L25 ;
000000 -- L24: halt ;
012706 -- L25: mov #776,sp ;
000776 --
004767 -- jsr pc,L26 ;
000002
#12060
000000 -- N2: halt ;
022716 -- L26: cmp #N2,(sp) ;
012060
001401 -- beq L27 ;
000000 -- halt ;
012716 -- L27: mov #N3,(sp) ;
012102
000207 -- rts pc ;
#12100
000000 -- halt ;
005046 -- N3: clr -(sp) ;
012746 -- mov #N4,-(sp) ;
012114
000002 -- rti ;
000000 -- halt ;
000137 -- N4: jmp @#N5 ;
012122
#12120
000000 -- halt ;
012705 -- N5: mov #160000,r5 ; r5=160000
160000
005037 -- clr @#6 ;
000006
012737 -- mov #N6,@#4 ;
012150
000004
#12140
012706 -- mov #776,sp ; sp=776
000776
005715 -- tst (r5) ; will fail, first word of I/O page
000000 -- halt ;
000000 -- N6: halt ;
#
C Exec code 35 (11/70 self test code)
# D RE RQ FU DAT
stapc 011600 -- start @ 11600
wtgo
rpc d=012152 -- ! pc
wal 000004 -- vector: 4 -> trap catcher again
bwm 2
000006 -- PC:6
000000 -- PS:0
#-----------------------------------------------------------------------------
# Up to here code and data (both input and result) occupied 'fresh' memory.
# Easy to debug, but inconvenient when test should be extended later.
# From here on, only code will always occupy fresh memory.
# Data will be put into the upper part of the 16 kbyte memory:
# test vector: 036000 (512 byte area)
# result data: 037000 (512 byte area)
#-----------------------------------------------------------------------------
C Setup code 36 [base 12200] (systematic CMP test)
#
wal 012200 -- code:
bwm 7
000230 -- spl 0
012400 -- L1: mov (r4)+,r0
012401 -- mov (r4)+,r1
020001 -- cmp r0,r1
011225 -- mov (r2),(r5)+
077305 -- sob r3,L1
000000 -- halt
#
C Exec code 36 (systematic CMP test)
C Exec test 36.1: data adapted from cmp.s11 code of Begemot p11-2.10c
#
wal 036000 -- setup test vector:
bwm 22
000000 -- 000000, 000000 --> nzvc=0100
000000 --
000001 -- 000001, 000001 --> nzvc=0100
000001 --
177777 -- 177777, 177777 --> nzvc=0100
177777 --
000000 -- 000000, 000001 --> nzvc=1001
000001 --
000000 -- 000000, 177777 --> nzvc=0001
177777 --
000001 -- 000001, 000000 --> nzvc=0000
000000 --
177777 -- 177777, 000000 --> nzvc=1000
000000 --
000001 -- 000001, 177777 --> nzvc=0001
177777 --
177777 -- 177777, 000001 --> nzvc=1000
000001 --
077777 -- 077777, 100000 --> nzvc=1011
100000 --
100000 -- 100000, 077777 --> nzvc=0010
077777 --
#----
wr2 177776 -- r2=177776 -> psw
wr3 000013 -- r3=13 -> test count
wr4 036000 -- r4=36000 -> input area
wr5 037000 -- r5=37000 -> output area
wsp 001400 -- sp=1400
stapc 012200 -- start @ 12200
wtgo
rpc d=012216 -- ! pc
rr3 d=000000 -- ! r3=0
rr4 d=036054 -- ! r4=12354
rr5 d=037026 -- ! r5=12426
wal 037000 --
brm 11
d=000004 -- 000000, 000000 --> nzvc=0100
d=000004 -- 000001, 000001 --> nzvc=0100
d=000004 -- 177777, 177777 --> nzvc=0100
d=000011 -- 000000, 000001 --> nzvc=1001
d=000001 -- 000000, 177777 --> nzvc=0001
d=000000 -- 000001, 000000 --> nzvc=0000
d=000010 -- 177777, 000000 --> nzvc=1000
d=000001 -- 000001, 177777 --> nzvc=0001
d=000010 -- 177777, 000001 --> nzvc=1000
d=000013 -- 077777, 100000 --> nzvc=1011
d=000002 -- 100000, 077777 --> nzvc=0010
#-----------------------------------------------------------------------------
C Setup code 37 [base 12300] (systematic DIV test)
#
wal 012300 -- code:
bwm 9
000230 -- spl 0
012400 -- L1: mov (r4)+,r0
012401 -- mov (r4)+,r1
071024 -- div (r4)+,r0
011225 -- mov (r2),(r5)+
010025 -- mov r0,(r5)+
010125 -- mov r1,(r5)+
077307 -- sob r3,L1
#12520
000000 -- halt
#
C Exec code 37 (systematic DIV test)
C Exec test 37.1: data adapted from div.s11 code of Begemot p11-2.10c
#
wal 036000 -- setup test vector:
bwm 57
000000 -- 0, 4, 0, 7, 0, 4# 4/ 0 -> 0111 0 4
000004 --
000000 --
000000 -- 0, 4, 2, 0, 2, 0# 4/ 2 -> 0000 2 0
000004 --
000002 --
000000 -- 0, 6, 2, 0, 3, 0# 6/ 2 -> 0000 3 0
000006 --
000002 --
000000 -- 0, 4, -2, 10, -2, 0# 4/-2 ->1000 -2 0
000004 --
177776 --
#36030
000002 -- 2, 0, 1, 2, 2, 0# 0x20000 / 1
000000 --
000001 --
000002 -- 2, 0, -2, 12, 2, 0# 0x20000 / -2
000000 --
177776 --
100000 -- 100000, 0, 1, 12,100000, 0# 0x80000000 / 1
000000 --
000001 --
177776 -- 177776,177777, -1, 2,177776,177777# -0x10001 / -1
177777 --
177777 --
#36060
177777 -- 177777,177773, 2, 10, -2, -1# -5 / 2
177773 --
000002 --
177777 -- 177777,177773, -2, 0, 2, -1# -5 / -2
177773 --
177776 --
177776 -- 177776, 0, 40000, 10, -10, 0# -0x20000/0x4000
000000 --
040000 --
000100 -- 100, 200,177601, 12, 100, 200# 0x400080 / -0x7f
000200 --
177601 --
#36110
000000 -- 0, 1, 0, 7, 0, 1 # zero divide
000001 --
000000 --
177777 -- -1, -1, 0, 7, -1, -1 # zero divide
177777 --
000000 --
000000 -- 0, 0, 0, 7, 0, 0 # zero divide
000000 --
000000 --
000001 -- 1, 1, 1, 2, 1, 1 # overflow
000001 --
000001 --
#36140
000001 -- 1, 1, -1, 012, 1, 1 # overflow
000001 --
177777 --
177777 -- -1, -1, 1, 010, -1, 0 # wfjm corrected, not overflow
177777 --
000001 --
177777 -- -1, -1, -1, 0, 1, 0 # wfjm corrected, not overflow
177777 --
177777 --
#----
wr2 177776 -- r2=177776 -> psw
wr3 000023 -- r3=23 -> test count
wr4 036000 -- r4=36000 -> input area
wr5 037000 -- r5=37000 -> output area
wsp 001400 -- sp=1400
stapc 012300 -- start @ 12300
wtgo
rpc d=012322 -- ! pc
rr3 d=000000 -- ! r3=0
rr4 d=036162 -- ! r4=36162
rr5 d=037162 -- ! r5=37162
wal 037000 --
brm 57
d=000007 --! 0, 4, 0, 7, 0, 4# 4/ 0 -> 0111 0 4
d=000000 --!
d=000004 --!
d=000000 --! 0, 4, 2, 0, 2, 0# 4/ 2 -> 0000 2 0
d=000002 --!
d=000000 --!
d=000000 --! 0, 6, 2, 0, 3, 0# 6/ 2 -> 0000 3 0
d=000003 --!
d=000000 --!
d=000010 --! 0, 4, -2, 10, -2, 0# 4/-2 ->1000 -2 0
d=177776 --!
d=000000 --!
#37030
d=000002 --! 2, 0, 1, 2, 2, 0# 0x20000 / 1
d=000002 --!
d=000000 --!
d=000012 --! 2, 0, -2, 12, 2, 0# 0x20000 / -2
d=000002 --!
d=000000 --!
d=000012 --!100000, 0, 1, 12,100000, 0# 0x80000000 / 1
d=100000 --!
d=000000 --!
d=000002 --!177776,177777, -1, 2,177776,177777# -0x10001 / -1
d=177776 --!
d=177777 --!
#37060
d=000010 --!177777,177773, 2, 10, -2, -1# -5 / 2
d=177776 --!
d=177777 --!
d=000000 --!177777,177773, -2, 0, 2, -1# -5 / -2
d=000002 --!
d=177777 --!
d=000010 --!177776, 0, 40000, 10, -10, 0# -0x20000/0x4000
d=177770 --!
d=000000 --!
d=000012 --! 100, 200,177601, 12, 100, 200# 0x400080 / -0x7f
d=000100 --!
d=000200 --!
#37110
d=000007 --! 0, 1, 0, 7, 0, 1 # zero divide
d=000000 --!
d=000001 --!
d=000007 --! -1, -1, 0, 7, -1, -1 # zero divide
d=177777 --!
d=177777 --!
d=000007 --! 0, 0, 0, 7, 0, 0 # zero divide
d=000000 --!
d=000000 --!
d=000002 --! 1, 1, 1, 2, 1, 1 # overflow
d=000001 --!
d=000001 --!
#13740
d=000012 --! 1, 1, -1, 012, 1, 1 # overflow
d=000001 --!
d=000001 --!
d=000010 --! -1, -1, 1, 010, -1, 0 # wfjm corrected, not overflow
d=177777 --!
d=000000 --!
d=000000 --! -1, -1, -1, 0, 1, 0 # wfjm corrected, not overflow
d=000001 --!
d=000000 --!
#--------
C Exec test 37.2: data adapted from KDJ11.MAC, test 213, p. 139-141
# D RE RQ FU DAT
wal 036000 -- setup test vector:
bwm 51
177777 -- 177777,177777,177777, 0, 1, 0#
177777 --
177777 --
000000 -- 0,177777,177777,12, 0,177777#
177777 --
177777 --
177777 -- 177777, 0,177777, 2,177777, 0#
000000 --
177777 --
000000 -- 0, 7642, 7643, 4, 0, 7642#
007642 --
007643 --
000000 -- 0, 137,177543, 4, 0, 137#
000137 --
177543 --
000000 -- 0, 7643, 7643, 0, 1, 0#
007643 --
007643 --
100000 -- 100000, 4376, 10021,12,100000, 4376#
004376 --
010021 --
177700 -- 177700,170033, 10021,10,176024,171307#
170033 --
010021 --
177700 -- 177700,170033,167757, 0, 1754,171307#
170033 --
167757 --
000000 -- 0,177777, 1, 2, 0,177777#
177777 --
000001 --
177777 -- 177777, 45716, 1,12,177777, 45716#
045716 --
000001 --
000000 -- 0, 2,177770, 4, 0, 2#
000002 --
177770 --
177777 -- 177777,177776, 10, 4, 0,177776#
177776 --
000010 --
000001 -- 1,177777, 1, 2, 1,177777#
177777 --
000001 --
000001 -- 1, 0, 2, 2, 1, 0#
000000 --
000002 --
000001 -- 1, 0, 3, 0, 52525, 1#
000000 --
000003 --
000023 -- 23, 16054, 16537, 0, 246, 10222#
016054 --
016537 --
#----
wr2 177776 -- r2=177776 -> psw
wr3 000021 -- r3=21 (17.) -> test count
wr4 036000 -- r4=36000 -> input area
wr5 037000 -- r5=37000 -> output area
wsp 001400 -- sp=1400
stapc 012300 -- start @ 12300
wtgo
rpc d=012322 -- ! pc
rr3 d=000000 -- ! r3=0
rr4 d=036146 -- ! r4=36146
rr5 d=037146 -- ! r5=37146
wal 037000 --
brm 51
d=000000 --!177777,177777,177777, 0, 1, 0#
d=000001 --!
d=000000 --!
d=000012 --! 0,177777,177777,12, 0,177777#
d=000000 --!
d=177777 --!
d=000002 --!177777, 0,177777, 2,177777, 0#
d=177777 --!
d=000000 --!
d=000004 --! 0, 7642, 7643, 4, 0, 7642#
d=000000 --!
d=007642 --!
d=000004 --! 0, 137,177543, 4, 0, 137#
d=000000 --!
d=000137 --!
d=000000 --! 0, 7643, 7643, 0, 1, 0#
d=000001 --!
d=000000 --!
d=000012 --!100000, 4376, 10021,12,100000, 4376#
d=100000 --!
d=004376 --!
d=000010 --!177700,170033, 10021,10,176024,171307#
d=176024 --!
d=171307 --!
d=000000 --!177700,170033,167757, 0, 1754,171307#
d=001754 --!
d=171307 --!
d=000002 --! 0,177777, 1, 2, 0,177777#
d=000000 --!
d=177777 --!
d=000012 --!177777, 45716, 1,12,177777, 45716#
d=177777 --!
d=045716 --!
d=000004 --! 0, 2,177770, 4, 0, 2#
d=000000 --!
d=000002 --!
d=000004 --!177777,177776, 10, 4, 0,177776#
d=000000 --!
d=177776 --!
d=000002 --! 1,177777, 1, 2, 1,177777#
d=000001 --!
d=177777 --!
d=000002 --! 1, 0, 2, 2, 1, 0#
d=000001 --!
d=000000 --!
d=000000 --! 1, 0, 3, 0, 52525, 1#
d=052525 --!
d=000001 --!
d=000000 --! 23, 16054, 16537, 0, 246, 10222#
d=000246 --!
d=010222 --!
#-----------------------------------------------------------------------------
C Setup code 40 [base 12400] (systematic ASH test)
#
wal 012400 -- code:
bwm 15
000230 -- spl 0
016400 -- L1: mov 2(r4),r0
000002
011412 -- mov (r4),(r2)
072064 -- ash 4(r4),r0
000004
011265 -- mov (r2),2(r5)
000002
#12420
010015 -- mov r0,(r5)
062704 -- add #6,r4
000006
062705 -- add #4,r5
000004
077315 -- sob r3,L1
000000 -- halt
#
C Exec code 40 (systematic ASH test)
C Exec test 40.1: data adapted from ash.s11 code of Begemot p11-2.10c
#
# The {} comments are original comments from Harti Brandt
# Annotations starting with !! indicated mods for W11
# Note, that the W11 does not have the microcode bugs of the J11 !
#
wal 036000 -- setup test vector:
# test shift amount 0
bwm 150
000000 -- 00, 000000, 000000, 000000, 04
000000 --
000000 --
000017 -- 17, 000000, 000000, 000000, 04
000000 --
000000 --
000017 -- 17, 100001, 000000, 100001, 10
100001 --
000000 --
000017 -- 17, 040001, 000000, 040001, 00
040001 --
000000 --
000017 -- 17, 040001, 177700, 040001, 00
040001 --
177700 --
# right shift positive values
000000 -- 00, 000000, 000077, 000000, 04
000000 --
000077 --
000017 -- 17, 000000, 000077, 000000, 04
000000 --
000077 --
000000 -- 00, 000002, 000077, 000001, 00
000002 --
000077 --
000000 -- 00, 000001, 000077, 000000, 05
000001 --
000077 --
000000 -- 00, 000003, 000076, 000000, 05
000003 --
000076 --
000000 -- 00, 000001, 000076, 000000, 04
000001 --
000076 --
000000 -- 00, 040000, 000062, 000001, 00
040000 --
000062 --
000000 -- 00, 040000, 000061, 000000, 05
040000 --
000061 --
000000 -- 00, 040000, 000060, 000000, 04
040000 --
000060 --
000000 -- 00, 040000, 000042, 000000, 04
040000 --
000042 --
000000 -- 00, 040000, 000041, 000000, 04
040000 --
000041 --
000000 -- 00, 040000, 000040, 000000, 04
040000 --
000040 --
000000 -- 00, 040000, 100037, 000000, 04
040000 --
100037 --
# right shift negative numbers
000000 -- 00, 100002, 000077, 140001, 10
100002 --
000077 --
000000 -- 00, 100002, 000076, 160000, 11
100002 --
000076 --
000000 -- 00, 100002, 000075, 170000, 10
100002 --
000075 --
000000 -- 00, 100002, 000062, 177776, 10
100002 --
000062 --
000000 -- 00, 100002, 000061, 177777, 10
100002 --
000061 --
000000 -- 00, 100002, 000060, 177777, 11
100002 --
000060 --
000000 -- 00, 100002, 000057, 177777, 11
100002 --
000057 --
000000 -- 00, 100002, 000056, 177777, 11
100002 --
000056 --
000000 -- 00, 100002, 000041, 177777, 11
100002 --
000041 --
000000 -- 00, 100002, 000040, 177777, 11
100002 --
000040 --
000000 -- 00, 100002, 040037, 177777, 11
100002 --
040037 --
# left shift positive numbers
000000 -- 00, 000000, 000001, 000000, 04
000000 --
000001 --
000017 -- 17, 000000, 000001, 000000, 04
000000 --
000001 --
000000 -- 00, 000001, 000007, 000200, 00
000001 --
000007 --
000000 -- 00, 000001, 000016, 040000, 00
000001 --
000016 --
000000 -- 00, 000001, 000017, 100000, 12
000001 --
000017 --
000000 -- 00, 000001, 000020, 000000, 07
000001 --
000020 --
000000 -- 00, 000001, 000021, 000000, 06
000001 --
000021 --
000000 -- 00, 000001, 000036, 000000, 06
000001 --
000036 --
000000 -- 00, 000001, 000037, 000000, 04 {????}
000001 --
000037 --
000000 -- 00, 000001, 000040, 000000, 04 {right shift!}
000001 --
000040 --
000000 -- 00, 000001, 010037, 000000, 04 {right shift!}
000001 --
010037 --
# left shift negative numbers
000000 -- 00, 100001, 000001, 000002, 03
100001 --
000001 --
000000 -- 00, 140001, 000001, 100002, 11
140001 --
000001 --
000000 -- 00, 140001, 000002, 000004, 03
140001 --
000002 --
000000 -- 00, 140001, 000016, 040000, 02
140001 --
000016 --
000000 -- 00, 140001, 000017, 100000, 12
140001 --
000017 --
000000 -- 00, 140001, 000020, 000000, 07
140001 --
000020 --
000000 -- 00, 140001, 000021, 000000, 06
140001 --
000021 --
000000 -- 00, 140002, 000035, 000000, 06
140002 --
000035 --
000000 -- 00, 140002, 000036, 000000, 06
140002 --
000036 --
000000 -- 00, 140002, 000037, 177777, 11 {????}
140002 --
000037 --
#----
wr2 177776 -- r2=177776 -> psw
wr3 000062 -- r3=62 -> test count
wr4 036000 -- r4=36000 -> input area
wr5 037000 -- r5=37000 -> output area
wsp 001400 -- sp=1400
stapc 012400 -- start @ 12400
wtgo
rpc d=012436 -- ! pc
rr3 d=000000 -- ! r3=0
rr4 d=036454 -- ! r4=36454
rr5 d=037310 -- ! r5=37310
wal 037000 --
# test shift amount 0
brm 100
d=000000 -- 00, 000000, 000000, 000000, 04
d=000004 --
d=000000 -- 17, 000000, 000000, 000000, 04
d=000004 --
d=100001 -- 17, 100001, 000000, 100001, 10
d=000010 --
d=040001 -- 17, 040001, 000000, 040001, 00
d=000000 --
d=040001 -- 17, 040001, 177700, 040001, 00
d=000000 --
#37024 # right shift positive values
d=000000 -- 00, 000000, 000077, 000000, 04
d=000004 --
d=000000 -- 17, 000000, 000077, 000000, 04
d=000004 --
d=000001 -- 00, 000002, 000077, 000001, 00
d=000000 --
#37040
d=000000 -- 00, 000001, 000077, 000000, 05
d=000005 --
d=000000 -- 00, 000003, 000076, 000000, 05
d=000005 --
d=000000 -- 00, 000001, 000076, 000000, 04
d=000004 --
d=000001 -- 00, 040000, 000062, 000001, 00
d=000000 --
#37060
d=000000 -- 00, 040000, 000061, 000000, 05
d=000005 --
d=000000 -- 00, 040000, 000060, 000000, 04
d=000004 --
d=000000 -- 00, 040000, 000042, 000000, 04
d=000004 --
d=000000 -- 00, 040000, 000041, 000000, 04
d=000004 --
#37100
d=000000 -- 00, 040000, 000040, 000000, 04
d=000004 --
d=000000 -- 00, 040000, 100037, 000000, 04
d=000006 -- !!04->06
#37110 # right shift negative numbers
d=140001 -- 00, 100002, 000077, 140001, 10
d=000010 --
d=160000 -- 00, 100002, 000076, 160000, 11
d=000011 --
#37120
d=170000 -- 00, 100002, 000075, 170000, 10
d=000010 --
d=177776 -- 00, 100002, 000062, 177776, 10
d=000010 --
d=177777 -- 00, 100002, 000061, 177777, 10
d=000010 --
d=177777 -- 00, 100002, 000060, 177777, 11
d=000011 --
#37140
d=177777 -- 00, 100002, 000057, 177777, 11
d=000011 --
d=177777 -- 00, 100002, 000056, 177777, 11
d=000011 --
d=177777 -- 00, 100002, 000041, 177777, 11
d=000011 --
d=177777 -- 00, 100002, 000040, 177777, 11
d=000011 -- see Note below [[s:10]]
d=000000 -- 00, 100002, 040037, 177777, 11 !!-1->0
d=000006 -- !!11->06
#37164 # left shift positive numbers
d=000000 -- 00, 000000, 000001, 000000, 04
d=000004 --
d=000000 -- 17, 000000, 000001, 000000, 04
d=000004 --
d=000200 -- 00, 000001, 000007, 000200, 00
d=000000 --
#37200
d=040000 -- 00, 000001, 000016, 040000, 00
d=000000 --
d=100000 -- 00, 000001, 000017, 100000, 12
d=000012 --
d=000000 -- 00, 000001, 000020, 000000, 07
d=000007 --
d=000000 -- 00, 000001, 000021, 000000, 06
d=000006 --
#37220
d=000000 -- 00, 000001, 000036, 000000, 06
d=000006 --
d=000000 -- 00, 000001, 000037, 000000, 04 {????}
d=000006 -- !!04->06
d=000000 -- 00, 000001, 000040, 000000, 04 {right shift!}
d=000004 --
d=000000 -- 00, 000001, 010037, 000000, 04 {right shift!}
d=000006 -- !!04->06
#37240 # left shift negative numbers
d=000002 -- 00, 100001, 000001, 000002, 03
d=000003 --
d=100002 -- 00, 140001, 000001, 100002, 11
d=000011 --
d=000004 -- 00, 140001, 000002, 000004, 03
d=000003 --
d=040000 -- 00, 140001, 000016, 040000, 02
d=000002 --
#37260
d=100000 -- 00, 140001, 000017, 100000, 12
d=000012 --
d=000000 -- 00, 140001, 000020, 000000, 07
d=000007 --
d=000000 -- 00, 140001, 000021, 000000, 06
d=000006 --
d=000000 -- 00, 140002, 000035, 000000, 06
d=000006 --
#37300
d=000000 -- 00, 140002, 000036, 000000, 06
d=000006 --
d=000000 -- 00, 140002, 000037, 177777, 11 {????} !!-1->0
d=000006 -- !!11->06
#
# simh notes:
# 1. ash dst=100002,src=040 sets C=0 in simh. PSW is: s:10 b:11 W11:11
#
#-----------------------------------------------------------------------------
C Setup code 41 [base 12500] (systematic ASHC even test)
#
wal 012500 -- code:
bwm 19
000230 -- spl 0
016400 -- L1: mov 2(r4),r0
000002
016401 -- mov 4(r4),r1
000004
011412 -- mov (r4),(r2)
073064 -- ashc 6(r4),r0
000006
#12520
011265 -- mov (r2),4(r5)
000004
010015 -- mov r0,(r5)
010165 -- mov r1,2(r5)
000002
062704 -- add #10,r4
000010
062705 -- add #6,r5
#12540
000006
077321 -- sob r3,L1
000000 -- halt
#
C Exec code 41 (systematic ASHC even test)
C Exec test 41.1: data adapted from ashc.s11 code of Begemot p11-2.10c
#
# The {} comments are original comments from Harti Brandt
# Annotations starting with !! indicated mods for W11
# Note, that the W11 does not have the microcode bugs of the J11 !
#
wal 036000 -- setup test vector:
# test when no shift at all, cc must be correctly set
bwm 188
000000 -- 00, 000000, 000000, 000000, 000000, 000000, 04
000000 --
000000 --
000000 --
000017 -- 17, 000000, 000000, 000000, 000000, 000000, 04
000000 --
000000 --
000000 --
000017 -- 17, 040000, 000001, 000000, 040000, 000001, 00
040000 --
000001 --
000000 --
000017 -- 17, 100000, 000001, 000000, 100000, 000001, 10
100000 --
000001 --
000000 --
000017 -- 17, 100000, 000001, 177700, 100000, 000001, 10
100000 --
000001 --
177700 --
# right shifts of positive numbers
000000 -- 00, 000000, 000000, 000077, 000000, 000000, 04
000000 --
000000 --
000077 --
000017 -- 17, 000000, 000000, 000077, 000000, 000000, 04
000000 --
000000 --
000077 --
000000 -- 00, 040000, 000000, 000077, 020000, 000000, 00
040000 --
000000 --
000077 --
000000 -- 00, 040000, 000000, 177777, 020000, 000000, 00
040000 --
000000 --
000077 --
000000 -- 00, 040000, 000000, 000060, 000000, 040000, 00
040000 --
000000 --
000060 --
000000 -- 00, 040000, 000000, 000042, 000000, 000001, 00
040000 --
000000 --
000042 --
000000 -- 00, 040000, 000000, 000041, 000000, 000000, 05
040000 --
000000 --
000041 --
000000 -- 00, 040000, 000000, 000040, 000000, 000000, 04
040000 --
000000 --
000040 --
000000 -- 00, 040000, 000000, 177737, 000000, 000000, 04
040000 --
000000 --
177737 --
000000 -- 00, 000000, 000001, 177737, 000000, 000000, 04
000000 --
000001 --
177737 --
# right shifts of negative numbers
000000 -- 00, 100000, 000002, 000077, 140000, 000001, 10
100000 --
000002 --
000077 --
000000 -- 00, 100020, 000001, 000077, 140010, 000000, 11
100020 --
000001 --
000077 --
000000 -- 00, 177777, 177776, 000077, 177777, 177777, 10
177777 --
177776 --
000077 --
000000 -- 00, 177777, 177777, 000077, 177777, 177777, 11
177777 --
177777 --
000077 --
000000 -- 00, 100000, 100000, 000060, 177777, 100000, 11
100000 --
100000 --
000060 --
000000 -- 00, 100000, 000000, 000060, 177777, 100000, 10
100000 --
000000 --
000060 --
000000 -- 00, 100000, 000001, 000042, 177777, 177776, 10
100000 --
000001 --
000042 --
000000 -- 00, 100000, 000001, 000041, 177777, 177777, 10
100000 --
000001 --
000041 --
000000 -- 00, 100000, 000001, 000040, 177777, 177777, 11
100000 --
000001 --
000040 --
000000 -- 00, 100000, 000001, 177737, 177777, 177777, 11
100000 --
000001 --
177737 --
# left shifts of positive numbers
000000 -- 00, 000000, 000000, 000001, 000000, 000000, 04
000000 --
000000 --
000001 --
000017 -- 17, 000000, 000000, 000001, 000000, 000000, 04
000000 --
000000 --
000001 --
000000 -- 00, 000002, 000001, 000001, 000004, 000002, 00
000002 --
000001 --
000001 --
000000 -- 00, 000002, 100000, 000001, 000005, 000000, 00
000002 --
100000 --
000001 --
000000 -- 00, 040000, 000000, 000001, 100000, 000000, 12
040000 --
000000 --
000001 --
000000 -- 00, 040000, 000000, 000002, 000000, 000000, 07
040000 --
000000 --
000002 --
000000 -- 00, 040000, 000000, 000003, 000000, 000000, 06
040000 --
000000 --
000003 --
000000 -- 00, 000000, 000001, 177701, 000000, 000002, 00
000000 --
000001 --
177701 --
000000 -- 00, 000000, 000001, 177735, 020000, 000000, 00
000000 --
000001 --
177735 --
000000 -- 00, 000000, 000001, 177736, 040000, 000000, 00
000000 --
000001 --
177736 --
000000 -- 00, 000000, 000001, 000037, 100000, 000000, 12 {left shift!}
000000 --
000001 --
000037 --
000000 -- 00, 000000, 000001, 177737, 000000, 000000, 04 {right shift!}
000000 --
000001 --
177737 --
000000 -- 00, 000000, 000001, 020037, 000000, 000000, 04 {right shift!}
000000 --
000001 --
020037 --
# left shifts of negative numbers
000000 -- 00, 177777, 177777, 000001, 177777, 177776, 11
177777 --
177777 --
000001 --
000000 -- 00, 177777, 177777, 000002, 177777, 177774, 11
177777 --
177777 --
000002 --
000000 -- 00, 177777, 177777, 000036, 140000, 000000, 11
177777 --
177777 --
000036 --
000000 -- 00, 177777, 177777, 000037, 100000, 000000, 11
177777 --
177777 --
000037 --
000000 -- 00, 177777, 177776, 000037, 000000, 000000, 07
177777 --
177776 --
000037 --
000000 -- 00, 177777, 177774, 000037, 000000, 000000, 06
177777 --
177774 --
000037 --
000000 -- 00, 177777, 177777, 177701, 177777, 177776, 11
177777 --
177777 --
177701 --
000000 -- 00, 177777, 177777, 001037, 177777, 177777, 11 {right shift!}
177777 --
177777 --
001037 --
000000 -- 00, 177777, 177777, 001036, 140000, 000000, 11
177777 --
177777 --
001036 --
#----
wr2 177776 -- r2=177776
wr3 000057 -- r3=57 (47.)
wr4 036000 -- r4=36000
wr5 037000 -- r5=37000
wsp 001400 -- sp=1400
stapc 012500 -- start @ 12500
wtgo
rpc d=012546 -- ! pc
rr3 d=000000 -- ! r3=0
rr4 d=036570 -- ! r4=36570
rr5 d=037432 -- ! r5=37432
wal 037000 --
# test when no shift at all, cc must be correctly set
brm 141
d=000000 --!00, 000000, 000000, 000000, 000000, 000000, 04
d=000000 --!
d=000004 --!
d=000000 --!17, 000000, 000000, 000000, 000000, 000000, 04
d=000000 --!
d=000004 --!
d=040000 --!17, 040000, 000001, 000000, 040000, 000001, 00
d=000001 --!
d=000000 --!
d=100000 --!17, 100000, 000001, 000000, 100000, 000001, 10
d=000001 --!
d=000010 --!
#37030
d=100000 --!17, 100000, 000001, 177700, 100000, 000001, 10
d=000001 --!
d=000010 --!
# right shifts of positive numbers
d=000000 --!00, 000000, 000000, 000077, 000000, 000000, 04
d=000000 --!
d=000004 --!
d=000000 --!17, 000000, 000000, 000077, 000000, 000000, 04
d=000000 --!
d=000004 --!
d=020000 --!00, 040000, 000000, 000077, 020000, 000000, 00
d=000000 --!
d=000000 --!
#37060
d=020000 --!00, 040000, 000000, 177777, 020000, 000000, 00
d=000000 --!
d=000000 --!
d=000000 --!00, 040000, 000000, 000060, 000000, 040000, 00
d=040000 --!
d=000000 --!
d=000000 --!00, 040000, 000000, 000042, 000000, 000001, 00
d=000001 --!
d=000000 --!
d=000000 --!00, 040000, 000000, 000041, 000000, 000000, 05
d=000000 --!
d=000005 --!
#37110
d=000000 --!00, 040000, 000000, 000040, 000000, 000000, 04
d=000000 --!
d=000004 --!
d=000000 --!00, 040000, 000000, 177737, 000000, 000000, 04
d=000000 --!
d=000006 --! !!04->06
d=100000 --!00, 000000, 000001, 177737, 000000, 000000, 04!!->100000
d=000000 --!
d=000012 --! !!04->12
# right shifts of negative numbers
d=140000 --!00, 100000, 000002, 000077, 140000, 000001, 10
d=000001 --!
d=000010 --!
#37140
d=140010 --!00, 100020, 000001, 000077, 140010, 000000, 11
d=000000 --!
d=000011 --!
d=177777 --!00, 177777, 177776, 000077, 177777, 177777, 10
d=177777 --!
d=000010 --!
d=177777 --!00, 177777, 177777, 000077, 177777, 177777, 11
d=177777 --!
d=000011 --!
d=177777 --!00, 100000, 100000, 000060, 177777, 100000, 11
d=100000 --!
d=000011 --!
#37170
d=177777 --!00, 100000, 000000, 000060, 177777, 100000, 10
d=100000 --!
d=000010 --!
d=177777 --!00, 100000, 000001, 000042, 177777, 177776, 10
d=177776 --!
d=000010 --!
d=177777 --!00, 100000, 000001, 000041, 177777, 177777, 10
d=177777 --!
d=000010 --!
d=177777 --!00, 100000, 000001, 000040, 177777, 177777, 11
d=177777 --!
d=000011 --!
#37220
d=100000 --!00, 100000, 000001, 177737, 177777, 177777, 11!!->100000
d=000000 --! !!->000000
d=000012 --! !!11->12
# left shifts of positive numbers
d=000000 --!00, 000000, 000000, 000001, 000000, 000000, 04
d=000000 --!
d=000004 --!
d=000000 --!17, 000000, 000000, 000001, 000000, 000000, 04
d=000000 --!
d=000004 --!
d=000004 --!00, 000002, 000001, 000001, 000004, 000002, 00
d=000002 --!
d=000000 --!
#37250
d=000005 --!00, 000002, 100000, 000001, 000005, 000000, 00
d=000000 --!
d=000000 --!
d=100000 --!00, 040000, 000000, 000001, 100000, 000000, 12
d=000000 --!
d=000012 --!
d=000000 --!00, 040000, 000000, 000002, 000000, 000000, 07
d=000000 --!
d=000007 --!
d=000000 --!00, 040000, 000000, 000003, 000000, 000000, 06
d=000000 --!
d=000006 --!
#37300
d=000000 --!00, 000000, 000001, 177701, 000000, 000002, 00
d=000002 --!
d=000000 --!
d=020000 --!00, 000000, 000001, 177735, 020000, 000000, 00
d=000000 --!
d=000000 --!
d=040000 --!00, 000000, 000001, 177736, 040000, 000000, 00
d=000000 --!
d=000000 --!
d=100000 --!00, 000000, 000001, 000037, 100000, 000000, 12 {left shift!}
d=000000 --!
d=000012 --!
#37330
d=100000 --!00, 000000, 000001, 177737, 000000, 000000, 04 {right shift!} !!->100000
d=000000 --!
d=000012 --! !!04->12
d=100000 --!00, 000000, 000001, 020037, 000000, 000000, 04 {right shift!} !!->100000
d=000000 --!
d=000012 --! !!04->12
# left shifts of negative numbers
d=177777 --!00, 177777, 177777, 000001, 177777, 177776, 11
d=177776 --!
d=000011 --!
d=177777 --!00, 177777, 177777, 000002, 177777, 177774, 11
d=177774 --!
d=000011 --!
#37360
d=140000 --!00, 177777, 177777, 000036, 140000, 000000, 11
d=000000 --!
d=000011 --!
d=100000 --!00, 177777, 177777, 000037, 100000, 000000, 11
d=000000 --!
d=000011 --!
d=000000 --!00, 177777, 177776, 000037, 000000, 000000, 07
d=000000 --!
d=000007 --!
d=000000 --!00, 177777, 177774, 000037, 000000, 000000, 06
d=000000 --!
d=000006 --!
#37410
d=177777 --!00, 177777, 177777, 177701, 177777, 177776, 11
d=177776 --!
d=000011 --!
d=100000 --!00, 177777, 177777, 001037, 177777, 177777, 11 {right shift!} !!->100000
d=000000 --! !!->00000
d=000011 --!
d=140000 --!00, 177777, 177777, 001036, 140000, 000000, 11
d=000000 --!
d=000011 --!
#-----------------------------------------------------------------------------
C Setup code 42 [base 12600] (systematic ASHC odd test)
#
wal 012600 -- code:
bwm 15
000230 -- spl 0
016401 -- L1: mov 2(r4),r1
000002
011412 -- mov (r4),(r2)
073164 -- ashc 4(r4),r1
000004
011265 -- mov (r2),2(r5)
000002
#12620
010115 -- mov r1,(r5)
062704 -- add #6,r4
000006
062705 -- add #4,r5
000004
077315 -- sob r3,L1
000000 -- halt
#
C Exec code 42 (systematic ASHC odd test)
C Exec test 42.1: data adapted from ashc.s11 code of Begemot p11-2.10c
#
# The {} comments are original comments from Harti Brandt
# Annotations starting with !! indicated mods for W11
# Note, that the W11 does not have the microcode bugs of the J11 !
#
wal 036000 -- setup test vector:
# test shift amount 0
bwm 165
000000 -- 00, 000000, 000000, 000000, 04
000000 --
000000 --
000017 -- 17, 000000, 000000, 000000, 04
000000 --
000000 --
000017 -- 17, 100001, 000000, 100001, 10
100001 --
000000 --
000017 -- 17, 040001, 000000, 040001, 00
040001 --
000000 --
000017 -- 17, 040001, 177700, 040001, 00
040001 --
177700 --
# right rotate positive values
000000 -- 00, 000000, 000077, 000000, 04
000000 --
000077 --
000017 -- 17, 000000, 000077, 000000, 04
000000 --
000077 --
000000 -- 00, 000002, 000077, 000001, 00
000002 --
000077 --
000000 -- 00, 000001, 000077, 100000, 01 {cc is funny!}
000001 --
000077 --
000000 -- 00, 000003, 000076, 140000, 01
000003 --
000076 --
000000 -- 00, 000001, 000076, 040000, 00
000001 --
000076 --
000000 -- 00, 040000, 000060, 040000, 00
040000 --
000060 --
000000 -- 00, 040000, 000043, 000002, 00
040000 --
000043 --
000000 -- 00, 040000, 000042, 000001, 00
040000 --
000042 --
000000 -- 00, 040000, 000041, 000000, 05
040000 --
000041 --
000000 -- 00, 040000, 000040, 000000, 04
040000 --
000040 --
000000 -- 00, 040000, 100037, 000000, 04
040000 --
100037 --
000000 -- 00, 020000, 000043, 000001, 00
020000 --
000043 --
000000 -- 00, 020000, 000042, 000000, 05
020000 --
000042 --
000000 -- 00, 020000, 000041, 000000, 04
020000 --
000041 --
# right rotate negative numbers
000000 -- 00, 100002, 000077, 040001, 10
100002 --
000077 --
000000 -- 00, 100002, 000076, 120000, 11
100002 --
000076 --
000000 -- 00, 100002, 000075, 050000, 10
100002 --
000075 --
000000 -- 00, 100002, 000061, 000005, 10
100002 --
000061 --
000000 -- 00, 100002, 000060, 100002, 11
100002 --
000060 --
000000 -- 00, 100002, 000057, 140001, 10
100002 --
000057 --
000000 -- 00, 100002, 000056, 160000, 11
100002 --
000056 --
000000 -- 00, 100002, 000055, 170000, 10
100002 --
000055 --
000000 -- 00, 100002, 000042, 177776, 10
100002 --
000042 --
000000 -- 00, 100002, 000041, 177777, 10
100002 --
000041 --
000000 -- 00, 100002, 000040, 177777, 11
100002 --
000040 --
000000 -- 00, 100002, 040037, 177777, 11
100002 --
040037 --
# left rotate positive numbers
000000 -- 00, 000000, 000001, 000000, 04
000000 --
000001 --
000000 -- 17, 000000, 000001, 000000, 04
000000 --
000001 --
000000 -- 00, 000001, 000007, 000200, 00
000001 --
000007 --
000000 -- 00, 000001, 000016, 040000, 00
000001 --
000016 --
000000 -- 00, 000001, 000017, 100000, 12
000001 --
000017 --
000000 -- 00, 000001, 000020, 000000, 03
000001 --
000020 --
000000 -- 00, 000001, 000021, 000000, 02
000001 --
000021 --
000000 -- 00, 000001, 000036, 000000, 02
000001 --
000036 --
000000 -- 00, 000001, 000037, 000000, 12
000001 --
000037 --
000000 -- 00, 000001, 000040, 000000, 04 {right shift!}
000001 --
000040 --
000000 -- 00, 000001, 010037, 000000, 04 {right shift!}
000001 --
010037 --
# left rotate negative numbers
000000 -- 00, 100001, 000001, 000002, 03
100001 --
000001 --
000000 -- 00, 140001, 000001, 100002, 11
140001 --
000001 --
000000 -- 00, 140001, 000002, 000004, 03
140001 --
000002 --
000000 -- 00, 140001, 000016, 040000, 02
140001 --
000016 --
000000 -- 00, 140001, 000017, 100000, 12
140001 --
000017 --
000000 -- 00, 140001, 000020, 000000, 13
140001 --
000020 --
000000 -- 00, 140001, 000021, 000000, 13
140001 --
000021 --
000000 -- 00, 140001, 000022, 000000, 03
140001 --
000022 --
000000 -- 00, 140001, 000023, 000000, 02
140001 --
000023 --
000000 -- 00, 140002, 000035, 000000, 02
140002 --
000035 --
000000 -- 00, 140002, 000036, 000000, 12
140002 --
000036 --
000000 -- 00, 140002, 000037, 000000, 07
140002 --
000037 --
#----
wr2 177776 -- r2=177776 -> psw
wr3 000067 -- r3=67 (55.) -> test count
wr4 036000 -- r4=36000 -> input area
wr5 037000 -- r5=37000 -> output area
wsp 001400 -- sp=1400
stapc 012600 -- start @ 12600
wtgo
rpc d=012636 -- ! pc
rr3 d=000000 -- ! r3=0
rr4 d=036512 -- ! r4=36512
rr5 d=037334 -- ! r5=37334
wal 037000 --
# test shift amount 0
brm 110
d=000000 --!00, 000000, 000000, 000000, 04
d=000004 --!
d=000000 --!17, 000000, 000000, 000000, 04
d=000004 --!
d=100001 --!17, 100001, 000000, 100001, 10
d=000010 --!
d=040001 --!17, 040001, 000000, 040001, 00
d=000000 --!
#37020
d=040001 --!17, 040001, 177700, 040001, 00
d=000000 --!
# right rotate positive values
d=000000 --!00, 000000, 000077, 000000, 04
d=000004 --!
d=000000 --!17, 000000, 000077, 000000, 04
d=000004 --!
d=000001 --!00, 000002, 000077, 000001, 00
d=000000 --!
#37040
d=100000 --!00, 000001, 000077, 100000, 01 {cc is funny!}
d=000001 --!
d=140000 --!00, 000003, 000076, 140000, 01
d=000001 --!
d=040000 --!00, 000001, 000076, 040000, 00
d=000000 --!
d=040000 --!00, 040000, 000060, 040000, 00
d=000000 --!
#37060
d=000002 --!00, 040000, 000043, 000002, 00
d=000000 --!
d=000001 --!00, 040000, 000042, 000001, 00
d=000000 --!
d=000000 --!00, 040000, 000041, 000000, 05
d=000005 --!
d=000000 --!00, 040000, 000040, 000000, 04
d=000004 --!
#37100
d=000000 --!00, 040000, 100037, 000000, 04
d=000006 --! !!04->06
d=000001 --!00, 020000, 000043, 000001, 00
d=000000 --!
d=000000 --!00, 020000, 000042, 000000, 05
d=000005 --!
d=000000 --!00, 020000, 000041, 000000, 04
d=000004 --!
#37120 # right rotate negative numbers
d=040001 --!00, 100002, 000077, 040001, 10
d=000010 --!
d=120000 --!00, 100002, 000076, 120000, 11
d=000011 --!
d=050000 --!00, 100002, 000075, 050000, 10
d=000010 --!
d=000005 --!00, 100002, 000061, 000005, 10
d=000010 --!
#37140
d=100002 --!00, 100002, 000060, 100002, 11
d=000011 --!
d=140001 --!00, 100002, 000057, 140001, 10
d=000010 --!
d=160000 --!00, 100002, 000056, 160000, 11
d=000011 --!
d=170000 --!00, 100002, 000055, 170000, 10
d=000010 --!
#37160
d=177776 --!00, 100002, 000042, 177776, 10
d=000010 --!
d=177777 --!00, 100002, 000041, 177777, 10
d=000010 --!
d=177777 --!00, 100002, 000040, 177777, 11
d=000011 --!
d=000000 --!00, 100002, 040037, 177777, 11 !!->000000
d=000007 --! !!11->07
#37200 # left rotate positive numbers
d=000000 --!00, 000000, 000001, 000000, 04
d=000004 --!
d=000000 --!17, 000000, 000001, 000000, 04
d=000004 --!
d=000200 --!00, 000001, 000007, 000200, 00
d=000000 --!
d=040000 --!00, 000001, 000016, 040000, 00
d=000000 --!
#37220
d=100000 --!00, 000001, 000017, 100000, 12
d=000012 --!
d=000000 --!00, 000001, 000020, 000000, 03
d=000003 --!
d=000000 --!00, 000001, 000021, 000000, 02
d=000002 --!
d=000000 --!00, 000001, 000036, 000000, 02
d=000002 --!
#37240
d=000000 --!00, 000001, 000037, 000000, 12
d=000012 --!
d=000000 --!00, 000001, 000040, 000000, 04 {right shift!}
d=000004 --!
d=000000 --!00, 000001, 010037, 000000, 04 {right shift!}
d=000012 --! !!04->12
# left rotate negative numbers
d=000002 --!00, 100001, 000001, 000002, 03
d=000003 --!
#37260
d=100002 --!00, 140001, 000001, 100002, 11
d=000011 --!
d=000004 --!00, 140001, 000002, 000004, 03
d=000003 --!
d=040000 --!00, 140001, 000016, 040000, 02
d=000002 --!
d=100000 --!00, 140001, 000017, 100000, 12
d=000012 --!
#37300
d=000000 --!00, 140001, 000020, 000000, 13
d=000013 --!
d=000000 --!00, 140001, 000021, 000000, 13
d=000013 --!
d=000000 --!00, 140001, 000022, 000000, 03
d=000003 --!
d=000000 --!00, 140001, 000023, 000000, 02
d=000002 --!
#37320
d=000000 --!00, 140002, 000035, 000000, 02
d=000002 --!
d=000000 --!00, 140002, 000036, 000000, 12
d=000012 --!
d=000000 --!00, 140002, 000037, 000000, 07
d=000007 --!
#-----------------------------------------------------------------------------
C Setup code 43 [base 12700] (Begemot MARK instruction test)
# test data and code adapted from Mark.s11 code of Begemot p11-2.10c
#
wal 012700 -- code test 1: (basics)
bwm 14
012705 -- mov #77077,r5 ; cookie
077077
010546 -- mov r5,-(sp) ; push r5
012746 -- mov #12,-(sp) ; parameter 1
000012
012746 -- mov #23,-(sp) ; parameter 2
000023
012746 -- mov #mark+2,-(sp) ; now the mark instruction
#12720
006402
010605 -- mov sp,r5 ; let r5 point to mark instruction
004737 -- jsr pc,subr ; call subroutine
012770
000240 -- noop
000000 -- halt
#-----
wal 012740 -- code test 2: (MARK with max. # of args)
bwm 10
010546 -- mov r5, -(sp) ; push r5
162706 -- sub #2*77, sp ; max number
000176
012746 -- mov #mark+77, -(sp) ; the mark instruction
006477
010605 -- mov sp, r5 ; let r5 point to mark instruction
004737 -- jsr pc, subr ; call subroutine
012770
#12760
000240 -- noop
000000 -- halt
#-----
wal 012770 -- code (procedure):
wmi 000205 -- subr: rts r5
#-----
C Exec code 43 (Begemot MARK test)
C Exec test 43.1 (basics)
# D RE RQ FU DAT
wsp 001400 -- sp=1400
stapc 012700 -- start @ 12700
wtgo
rpc d=012734 -- ! pc
rr5 d=077077 -- ! r5
rsp d=001400 -- ! sp
wal 001366 --
brm 5
d=012730 -- ! mem(1366)
d=006402 -- ! mem(1370)
d=000023 -- ! mem(1372)
d=000012 -- ! mem(1374)
d=077077 -- ! mem(1376)
#----
C Exec test 43.2 (MARK with max. # of args)
# D RE RQ FU DAT
wsp 001400 -- sp=1400
stapc 012740 -- start @ 12740
wtgo
rpc d=012764 -- ! pc
rr5 d=077077 -- ! r5
rsp d=001400 -- ! sp
#-----------------------------------------------------------------------------
C Setup code 44 [base 13000] (Implementation variations)
# test various PDP11 implementation variations (DCJ11 user guide, table C-1)
#
wal 013000 -- code: (to be single stepped mostly)
bwm 22
010424 -- mov r4,(r4)+ ; case 1 and 2
010444 -- mov r4,-(r4)
010764 -- mov pc,2(r4)
000002
000124 -- jmp (r4)+
000104 -- jmp r4
000304 -- swab r4
005214 -- inc (r4)
#13020
000006 -- rtt
000000 -- halt
000002 -- rti
000000 -- halt
010011 -- mov r0,(r1)
010046 -- mov r0,-(sp)
000114 -- jmp (r4)
010021 -- mov r0,(r1)+
#13040
012100 -- mov (r1)+,r0
005221 -- inc (r1)+
106621 -- mtpd (r1)+
106506 -- mfpd sp
106606 -- mtpd sp
000003 -- bpt
#-----
wal 013070 -- code: (target for rtt,rti tests)
bwm 2
000240 -- noop
000000 -- halt
#-----
C Exec code 44 (Implementation variations)
C test 44.1: OPR R,(R)+ : incremented before {J11} or after {70} use as source
#
rst -- console reset
wps 000000 -- clear psw
wr4 001600 -- r4=1600
wsp 001400 -- sp=1400
wpc 013000 -- pc=13000
step -- step (mov r4,(r4)+)
rpc d=013002 -- ! pc=13002
rr4 d=001602 -- ! r4=1602
wal 001600 -- check target location
rmi d=001600 -- ! ; initial content of R expected for 11/70
#
C test 44.2: OPR R,-(R) : decremented before {J11} or after {70} use as source
#
wr4 001600 -- r4=1600
wsp 001400 -- sp=1400
wpc 013002 -- pc=13002
step -- step (mov r4,-(r4))
rpc d=013004 -- ! pc=13004
rr4 d=001576 -- ! r4=1576
wal 001600 -- check target location
rmi d=001600 -- ! ; initial content of R expected for 11/70
#
C test 44.3: OPR PC,A(R) : store PC+2 {70} or PC+4 {J11}
#
wr4 001600 -- r4=1600
wsp 001400 -- sp=1400
wpc 013004 -- pc=13004
step -- step (mov pc,2(r4))
rpc d=013010 -- ! pc=13010
wal 001602 -- check target location
rmi d=013006 -- ! ; PC+2 expected for 11/70
#
C test 44.4: JMP (R)+ : R used {70;J11} or R+2 used {05,10,15,20}
#
wr4 013074 -- r4=13074
wsp 001400 -- sp=1400
wpc 013010 -- pc=13010
step -- step (jmp (r4)+)
rpc d=013074 -- ! pc=13074 ; R expected for 11/70
rr4 d=013076 -- ! r4=13076
#
C test 44.5: JMP R : traps to 10 {44,45,70;J11} or 4 {all others}
C Note: J11 doc is wrong, 11/70 traps 10, not 4, as stated
#
wal 177766 -- clear CPUERR
wm 000000 --
wr4 000000 -- r4=0
wsp 001400 -- sp=1400
wpc 013012 -- pc=13012
step -- step (jmp r4) [[s:2]]
rpc d=000012 -- ! pc=12 ; trap 10 expected for 11/70 [[s:10]]
rsp d=001374 -- ! sp=1374
wal 177766 -- check CPUERR
rm d=000000 -- ! CPUERR: no bit set
wm 000000 -- clear CPUERR
#
C test 44.6: SWAB does not change V {15,20} or clears V {all others}
#
wr4 000300 -- r4=3000
wsp 001400 -- sp=1400
wpc 013014 -- pc=13014
wps 000017 -- psw: set all cc flags in psw
step -- step (swab r4)
rpc d=013016 -- ! pc=13074
rr4 d=140000 -- ! r4=140000
rps d=000004 -- ! psw: Z=1 ; clear V expected for 11/70
#
C test 44.7: CPU access to 177700-177717 (regs) timesout {70,J11} or not {05,10}
#
wr4 177700 -- r4=177700
wsp 001400 -- sp=1400
wpc 013016 -- pc=13016
step -- step (inc (r4)) [[s:2]]
rpc d=000006 -- ! pc=6 ; trap 4 expected for 11/70 [[s:10]]
rsp d=001374 -- ! sp=1374
wal 177766 -- check CPUERR
rm d=000020 -- ! CPUERR: (iobto=1)
wm 000000 -- clear CPUERR
#
C test 44.10: If RTT sets T bit, trap occurs after instr. following RTT {70,J11}
#
wal 001374 -- setup stack with rtt return frame setting T flag
bwm 2
013070 -- start address (points to: noop, halt)
000020 -- set T flag in PSW
wsp 001374 -- sp=1374
wpc 013020 -- pc=13020
cont -- cont (rtt)
wtgo
rpc d=000020 -- ! pc=20 ; T-trap executed
rsp d=001374 -- ! sp=1374
wal 001374 -- check stack
brm 2
d=013072 -- trap address: address after noop expected for 11/70
d=000020 -- PSW
rst -- console reset (to clear T flag)
#
C test 44.11: If RTI sets T bit, T trap occurs immediately {70,J11}
#
wal 001374 -- setup stack with rtt return frame setting T flag
bwm 2
013070 -- start address (points to: noop, halt)
000020 -- set T flag in PSW
wsp 001374 -- sp=1374
wpc 013024 -- pc=13024
cont -- cont (rti)
wtgo
rpc d=000020 -- ! pc=20 ; T-trap executed
rsp d=001374 -- ! sp=1374
wal 001374 -- check stack
brm 2
d=013070 -- trap address: address of noop expected for 11/70
d=000020 -- PSW
rst -- console reset (to clear T flag)
#
C test 44.14: Direct access to PSW can {05..20} / cannot {others} set T bit
#
wr0 000030 -- r0=30 (set T bit, N also)
wr1 177776 -- r1=177776 (PSW address)
wsp 001400 -- sp=1400
wpc 013030 -- pc=13030
step -- step (mov r0,(r1))
rpc d=013032 -- ! pc=13032
rps d=000010 -- ! psw: T bit not set expected for 11/70
#
C test 44.15: odd address using SP causes HALT {<=20} or emmergency stack {>35}
#
wsp 001401 -- sp=1401
wpc 013032 -- pc=13032
step -- step (mov r0,-(sp)) [[s:2]]
rpc d=000006 -- ! pc=6 ; trap 4 [[s:13034]]
rsp d=000000 -- ! sp=0 ; emergency stack expected for 11/70 [[s:4]]
wal 000000 -- check emergency stack
brm 2
d=013034 -- ! PC of abort [[s:0]]
d=000000 -- ! PS of abort (currently gets lost...)
rst -- console reset (to clear CPUERR reg)
wal 000000 -- clean tainted memory
bwm 2
000000 --
000000 --
#
# simh notes:
# 1. apparently not consistently implemented in simh. SP is set to 4, but
# interrupt/trap sequence isn't executed. Effectively, simh halt's.
#
# for the test 28/29/30x enable MMU and make address 100000 unavailable
#
wal 172310 -- kernel I space DR segment 4 (base 100000)
wmi 077400 -- slf=127; ed=0(up); acf=0 (non resident)
#
C test 44.28: If PC->bad memory, PC incremented {others} / not inc'ed {35,40}
#
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wr4 100000 -- r4=100000
wsp 001400 -- sp=1400
wpc 013034 -- pc=13034
cont -- cont (jmp (r4))
wtgo
rpc d=000254 -- ! pc=254 ; trap 240 ; Note: halt is executed, was cont !
rsp d=001374 -- ! sp=1374
wal 001374 -- check stack
brm 2
d=100002 -- trap address: PC inc'ed expected for 11/70 [[s:100000]]
d=000340 -- PSW
rst -- console reset (to clear CPUERR reg)
#
# simh notes:
# 1. simh reads instruction, later increments PC. Thus PC not inc'ed in simh.
#
C test 44.29/30a: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
C test for dstw chain (mov r0,(r1)+)
#
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wr1 100000 -- r1=100000
wsp 001400 -- sp=1400
wpc 013036 -- pc=13036
step -- step (mov r0,(r1)+) [[s:2]]
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
rsp d=001374 -- ! sp=1374
rr1 d=100002 -- ! r1=100002
wal 177572 -- check SSR0/1
brm 2
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
d=000021 -- ! SSR1: ra=1,2
rst -- console reset (to clear CPUERR reg)
#
C test 44.29/30b: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
C test for srcr chain (mov (r1)+,r0)
#
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wr1 100000 -- r1=100000
wsp 001400 -- sp=1400
wpc 013040 -- pc=13040
step -- step ((mov (r1)+,r0) [[s:2]]
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
rsp d=001374 -- ! sp=1374
rr1 d=100002 -- ! r1=100002
wal 177572 -- check SSR0/1
brm 2
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
d=000021 -- ! SSR1: ra=1,2
rst -- console reset (to clear CPUERR reg)
#
C test 44.29/30c: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
C test for dstr chain (inc (r1)+)
#
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wr1 100000 -- r1=100000
wsp 001400 -- sp=1400
wpc 013042 -- pc=13042
step -- step (inc (r1)+) [[s:2]]
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
rsp d=001374 -- ! sp=1374
rr1 d=100002 -- ! r1=100002
wal 177572 -- check SSR0/1
brm 2
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
d=000021 -- ! SSR1: ra=1,2
rst -- console reset (to clear CPUERR reg)
C test 44.29/30d: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
C test for dsta chain (mtpd (r1)+)
#
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wr1 100000 -- r1=100000
wsp 001376 -- sp=1376
wpc 013044 -- pc=13044
wal 001376 -- push a word on stack for mtpd
wmi 123456 --
step -- step (mtpd (r1)+) [[s:2]]
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
rsp d=001374 -- ! sp=1374
rr1 d=100002 -- ! r1=100002
wal 177572 -- check SSR0/1
brm 2
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
d=010426 -- ! SSR1: rb=1,2; ra=6,2
rst -- console reset (to clear CPUERR reg)
#
# simh notes:
# 1. simh first pops, than writes to destination, reversing ra,rb in SSR1
#
# now reset MMU to default
#
wal 172310 -- kernel I space DR segment 4 (base 100000)
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
#
C test 44.39: cmode=10 will cause abort {70,J11}, treated as kmode {23,24}
#
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wr1 001400 -- r1=1400
wsp 001400 -- sp=1400
wps 100000 -- psw: set cm=10, pm=00
wpc 013042 -- pc=13042
step -- step (inc (r1)+) [[s:2]]
rpc d=000252 -- ! pc=252 ; trap 250; as expected for 11/70 [[s:254]]
rsp d=001374 -- ! sp=1374
rr1 d=001400 -- ! r1=1400
wal 177572 -- check SSR0/1
brm 3
d=140101 -- ! SSR0: (abo_nr=1,abo_l=1,m=10,seg=0,ena=1) [[s:140301]]
d=000000 -- ! SSR1: ra=none
d=013042 -- ! SSR2: PC of failed instruction
wal 001374 -- check stack
brm 2
d=013044 -- ! PC after failed instruction [[s:013042]]
d=100000 -- ! PS
rst -- console reset (to clear CPUERR reg, PSW)
#
# simh notes:
# 1. simh saves PC of failed instruction on stack, not PC after instruction
#
C test 44.43: user mode HALT: trap 4 {70} or 10 {others}
#
wal 177766 -- check CPUERR ;??? remove if console reset fixed
wm 000000 -- clear
wsp 001400 -- sp=1400
wps 170000 -- psw: set cm=11, pm=11
wpc 013022 -- pc=13022
step -- step (halt in user mode) [[s:2]]
rpc d=000006 -- ! pc=6 ; trap 4; as expected for 11/70 [[s:10]]
rsp d=001374 -- ! sp=1374
wal 001374 -- check stack
brm 2
d=013024 -- ! PC after failed instruction
d=170000 -- ! PS
wal 177766 -- check CPUERR
rm d=000200 -- ! CPUERR: (illhalt=1)
rst -- console reset (to clear CPUERR reg, PSW)
#
C test 44.44: PDR bit<0> implemented {70} or not {others}
#
wal 172310 -- kernel I space DR, segment 4
wm 077401 -- set acf bit 0: slf=127; ed=0(up); acf=1 (r+trap)
rm d=077401 -- ! check; works as expected for 11/70
wm 077406 -- restore: slf=127; ed=0(up); acf=6(w/r)
#
C test 44.45: PDR bit<7>(AIB any access) implemented {70} or not {others}
#
wal 172300 -- kernel I space DR, reset segment 0 and 1
bwm 2
077404 -- slf=127; ed=0(up); acf=4(w/r and trap)
077404 -- slf=127; ed=0(up); acf=4(w/r and trap)
wal 172300 -- check kernel I space DR, segment 0 and 1
brm 2
d=077404 -- !
d=077404 -- !
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wr0 123456 -- r0=123456
wr1 030000 -- r1=30000
wsp 001400 -- sp=1400
wpc 013030 -- pc=13030
step -- step (mov r0,(r1))
rpc d=013032 -- ! pc=next
rsp d=001400 -- ! sp=1400
wal 030000 -- check target memory, untaint
rm d=123456 -- !
wm 000000 --
wal 172300 -- check kernel I space DR, segment 0 and 1
brm 2
d=077604 -- ! slf=127; ed=0(up); acf=4(w/r+trap); aib=10 (A=1,W=0)
d=077704 -- ! slf=127; ed=0(up); acf=4(w/r+trap); aib=11 (A=1,W=1)
wal 172300 -- kernel I space DR, reset segment 0 and 1
bwm 2
077406 -- slf=127; ed=0(up); acf=6(w/r)
077406 -- slf=127; ed=0(up); acf=6(w/r)
rst -- console reset (to clear CPUERR reg)
#
C test 44.46: Full PAR implemented {44,70,J11} or not {others}
#
wal 172350 -- kernel I space AR, segment 4
wm 177777 -- set all bits
rm d=177777 -- ! check; works as expected for 11/70
wm 001000 -- restore: 1000 100000 base
#
C test 44.47: MMR0<9>(mmu trap) implemented {70} or not {others}
#
wal 177572 -- SSR0
wm 001000 -- set trap enable
rm d=001000 -- ! check; works as expected for 11/70
wm 000000 -- restore
#
C test 44.48: MMR3<2:0>(D space) implemented {44,70,J11} or not {others}
#
wal 172516 -- SSR3
wm 000007 -- set D space bis
rm d=000007 -- ! check; works as expected for 11/70
wm 000000 -- restore
#
C test 44.49: MMR3<5:4>(UMAP, 22 bit) implemented {44,70,J11} or not {others}
#
wal 172516 -- SSR3
wm 000060 -- set D space bits
rm d=000060 -- ! check; available, as expected for 11/70
wm 000000 -- restore
#
C test 44.50: MMR3<3>(CSM enable) implemented {44,J11} or not {others}
#
wal 172516 -- SSR3
wm 000010 -- set D space bit
rm d=000000 -- ! check; not available, as expected for 11/70
wm 000000 -- restore
#
C test 44.51: MMR2 tracks fetches {70} or instructions only {others}
C here W11 behaves like {others}, fetches are not tracked in SSR2
C Also: instruction complete flag set in SSR0 after bpt.
#
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wsp 001400 -- sp=1400
wpc 013052 -- pc=13052
step -- step (bpt)
rpc d=000016 -- ! pc=16; trap 14 see note [[s:13054]]
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=000000 -- ! SSR1: ra=none
d=013052 -- ! SSR2: PC of bpt
step -- step (halt)
rpc d=000020 -- ! pc=20 (after halt)
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=000000 -- ! SSR1: ra=none
d=000016 -- ! SSR2: PC of halt
rst -- console reset (to clear CPUERR reg, PSW)
#
# simh notes:
# 1. when simh steps over a BPT,IOT,..., the PC is pointing after the
# instruction. The trap sequence together with first instruction is
# executed in next step.
#
C test 44.52: MT/FPx SP for pmode=10 unpredictable {others} / user SP {J11}
# write registers
#
wr0 000001 -- set r0,..,r7
wr1 000101 --
wr2 000201 --
wr3 000301 --
wr4 000401 --
wr5 000501 --
wsp 001400 --
wpc 000701 --
# write register set 1, sm,um stack
#
wps 004000 -- psw: cm=kernel, set=1
wr0 010001 -- set r0,..,r5 [[r10]]
wr1 010101 -- [[r11]]
wr2 010201 -- [[r12]]
wr3 010301 -- [[r13]]
wr4 010401 -- [[r14]]
wr5 010501 -- [[r15]]
wps 044000 -- psw: cm=super(01),set=1
wsp 010601 -- set ssp [[ssp]]
wps 144000 -- psw: cm=user(11),set=1
wsp 110601 -- set usp [[usp]]
#
C 52a: MFPS for pmode=10
#
wps 020000 -- psw: set cm=00, pm=10
wpc 013046 -- pc=13046
step -- step (mfpd sp)
rpc d=013050 -- ! pc=next
rsp d=001376 -- ! sp=1376
wal 001376 -- check stack
rmi d=013046 -- ! it returns PC like 11/70 unpredictable [[s:0]]
rst -- console reset (to clear CPUERR reg)
#
# simh note:
# 1. simh returns 0 here, just unpredictable in a different way ...
#
C 52a: MTPS for pmode=10
#
wal 001376 -- setup stack with value for mtpd
wmi 123446 --
wps 020000 -- psw: set cm=00, pm=10
wpc 013050 -- pc=13050
step -- step (mtpd sp)
rpc d=013052 -- ! pc=next
rsp d=001400 -- ! sp=1400
# check registers
#
rr0 d=000001 -- ! r0,..,r7
rr1 d=000101 -- !
rr2 d=000201 -- !
rr3 d=000301 -- !
rr4 d=000401 -- !
rr5 d=000501 -- !
# check register set 1, sm,um stack
#
wps 004000 -- psw: cm=kernel, set=1
rr0 d=010001 -- ! r0,..,r5 [[r10]]
rr1 d=010101 -- ! [[r11]]
rr2 d=010201 -- ! [[r12]]
rr3 d=010301 -- ! [[r13]]
rr4 d=010401 -- ! [[r14]]
rr5 d=010501 -- ! [[r15]]
wps 044000 -- psw: cm=super(01),set=1
rsp d=010601 -- ! ssp [[ssp]]
wps 144000 -- psw: cm=user(11),set=1
rsp d=110601 -- ! usp [[usp]]
# --> all preset values intact; -> mtpd thus noop --> like 11/70 unpredictable
#
rst -- console reset (to clear CPUERR reg)
#
# simh notes on MMR0:
# 1. simh doesn't freeze MMR0 bit 7, the instr.compl. bit is set again after
# executing first instruction of trap handler.
#
#-----------------------------------------------------------------------------
C Setup code 45 [base 13100] (mmr1 and instructions with implicit stack push/pop
#
wal 013100 -- code: (to be single stepped mostly)
bwm 5
106621 -- mtpd (r1)+
106521 -- mfpd (r1)+
004721 -- jsr pc,(r1)+
000000 -- halt
#13110
000207 -- rts pc
#-----
C Exec code 45 (mmr1 and instructions with implicit stack push/pop)
C test 45.1: mtpd (r1)+
#
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wal 001376 -- setup stack with value for mtpd
wmi 123456 --
wr1 030000 -- r1=30000
wsp 001376 -- sp=1376
wpc 013100 -- pc=13100
step -- step (mtpd (r1)+)
rpc d=013102 -- ! pc=next
rsp d=001400 -- ! sp=1400
rr1 d=030002 -- ! r1=30002
wal 177572 -- check SSR0/1/2
brm 3
d=000003 -- ! SSR0: (seg=1,ena=1)
d=010426 -- ! SSR1: rb=1,2; ra=6,2
d=013100 -- ! SSR2: PC of mtpd
wal 030000 -- check target memory
rm d=123456 -- !
rst -- console reset
#
C test 45.2: mfpd (r1)+
#
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wr1 030000 -- r1=30000
wsp 001400 -- sp=1400
wpc 013102 -- pc=13102
step -- step (mfpd (r1)+)
rpc d=013104 -- ! pc=next
rsp d=001376 -- ! sp=1376
rr1 d=030002 -- ! r1=30002
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (seg=0,ena=1)
d=173021 -- ! SSR1: rb=6,-2; ra=1,2
d=013102 -- ! SSR2: PC of mtpd
wal 001376 -- check stack
rmi d=123456 -- !
wal 030000 -- clear tainted target memory
wm 000000 --
rst -- console reset
#
C test 45.3: jsr pc,(r1)+ and rts pc
#
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wr1 013110 -- r1=13110
wsp 001400 -- sp=1400
wpc 013104 -- pc=13104
step -- step (jsr pc,(r1)+)
rpc d=013110 -- ! pc=target
rsp d=001376 -- ! sp=1376
rr1 d=013112 -- ! r1=13112
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (seg=0,ena=1)
d=173021 -- ! SSR1: rb=6,-2; ra=1,2
d=013104 -- ! SSR2: PC of jsr
wal 001376 -- check stack
rmi d=013106 -- ! PC after jsr
step -- step (rts pc)
rpc d=013106 -- ! pc=target
rsp d=001400 -- ! sp=1400
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (seg=0,ena=1)
d=000026 -- ! SSR1: ra=6,2 [[s:0]]
d=013110 -- ! SSR2: PC of rts
rst -- console reset
#
# simh notes:
# 1. simh reads stack and incremets sp later. In case of an MMU abort on
# stack read, simh SSR1 will be 0, while W11 shows the sp increment
#
#-----------------------------------------------------------------------------
C Setup code 46 [base 13200] (systematic result+cc test of 1+2op instructions)
# the following codes expect:
# r0-> psw
# r1-> loop count
# r2-> input ptr
# r3-> output ptr
# r4-> src reg
# r5-> dst reg
#
wal 013200 -- code 1: test 1op register
bwm 8
000230 -- spl 0
012205 -- L1: mov (r2)+,r5 ; load dst
000000 -- halt ; ccmov set cc's
000000 -- halt ; iut instr. under test
011023 -- mov (r0),(r3)+ ; save psw
010523 -- mov r5,(r3)+ ; save dst
077106 -- sob r1,L1 (.-6)
000000 -- halt
#----
wal 013220 -- code 2: test 1op memory
bwm 8
000230 -- spl 0
012215 -- L1: mov (r2)+,(r5) ; load dst
000000 -- halt ; ccmov set cc's
000000 -- halt ; iut instr. under test
011023 -- mov (r0),(r3)+ ; save psw
011523 -- mov (r5),(r3)+ ; save dst
077106 -- sob r1,L1 (.-6)
000000 -- halt
#-----
wal 013240 -- code 3: test 2op register
bwm 9
000230 -- spl 0
012204 -- L1: mov (r2)+,r4 ; load src
012205 -- mov (r2)+,r5 ; load dst
000000 -- halt ; ccmov set cc's
000000 -- halt ; iut instr. under test
011023 -- mov (r0),(r3)+ ; save psw
010523 -- mov r5,(r3)+ ; save dst
077107 -- sob r1,L1 (.-7)
#13260
000000 -- halt
#-----
wal 013270 -- code 4: test 2op memory
bwm 9
000230 -- spl 0
012214 -- L1: mov (r2)+,(r4) ; load src
012215 -- mov (r2)+,(r5) ; load dst
000000 -- halt ; ccmov set cc's
#13300
000000 -- halt ; iut instr. under test
011023 -- mov (r0),(r3)+ ; save psw
011523 -- mov (r5),(r3)+ ; save dst
077107 -- sob r1,L1 (.-7)
000000 -- halt
#----
C Exec code 46 pass 1 (systematic result+cc test of 1+2op instructions; word)
C Exec test 46.1wr: COM - reg
#
wal 036000 -- setup test vector: for com,inc,dec,neg,adc,sbc,tst
bwm 5
000000 -- com 000000
000001 -- com 000001
077777 -- com 077777
100000 -- com 100000
177777 -- com 177777
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
005105 -- iut= com r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000011 -- ! com 000000 -> n1z0v0c1; 177777
d=177777 -- !
d=000011 -- ! com 000001 -> n1z0v0c1; 177776
d=177776 -- !
d=000011 -- ! com 077777 -> n1z0v0c1; 100000
d=100000 -- !
d=000001 -- ! com 100000 -> n0z0v0c1; 077777
d=077777 -- !
d=000005 -- ! com 177777 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.1wm: COM - mem
#
wal 013224 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
005115 -- iut= com (r5)
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
stapc 013220 -- start @ 13220 (1op mem)
wtgo
rpc d=013240 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000011 -- ! com 000000 -> n1z0v0c1; 177777
d=177777 -- !
d=000011 -- ! com 000001 -> n1z0v0c1; 177776
d=177776 -- !
d=000011 -- ! com 077777 -> n1z0v0c1; 100000
d=100000 -- !
d=000001 -- ! com 100000 -> n0z0v0c1; 077777
d=077777 -- !
d=000005 -- ! com 177777 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.2wrc0: INC - reg,C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
005205 -- iut= inc r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000000 -- ! inc 000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! inc 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000012 -- ! inc 077777 -> n1z0v1c0; 100000
d=100000 -- !
d=000010 -- ! inc 100000 -> n1z0v0c0; 100001
d=100001 -- !
d=000004 -- ! inc 177777 -> n0z1v0c0; 000000
d=000000 -- !
#--------
C Exec test 46.2wrc1: INC - reg,C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
005205 -- iut= inc r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000001 -- ! inc 000000 -> n0z0v0c1; 000001
d=000001 -- !
d=000001 -- ! inc 000001 -> n0z0v0c1; 000002
d=000002 -- !
d=000013 -- ! inc 077777 -> n1z0v1c1; 100000
d=100000 -- !
d=000011 -- ! inc 100000 -> n1z0v0c1; 100001
d=100001 -- !
d=000005 -- ! inc 177777 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.3wrc0: DEC - reg,C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
005305 -- iut= dec r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000010 -- ! dec 000000 -> n1z0v0c0; 177777
d=177777 -- !
d=000004 -- ! dec 000001 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! dec 077777 -> n0z0v0c0; 077776
d=077776 -- !
d=000002 -- ! dec 100000 -> n0z0v1c0; 077777
d=077777 -- !
d=000010 -- ! dec 177777 -> n1z0v0c0; 177776
d=177776 -- !
#--------
C Exec test 46.3wrc1: DEC - reg,C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
005305 -- iut= dec r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000011 -- ! dec 000000 -> n1z0v0c1; 177777
d=177777 -- !
d=000005 -- ! dec 000001 -> n0z1v0c1; 000000
d=000000 -- !
d=000001 -- ! dec 077777 -> n0z0v0c1; 077776
d=077776 -- !
d=000003 -- ! dec 100000 -> n0z0v1c1; 077777
d=077777 -- !
d=000011 -- ! dec 177777 -> n1z0v0c1; 177776
d=177776 -- !
#--------
C Exec test 46.4wr: NEG - reg
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
005405 -- iut= neg r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! neg 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000011 -- ! neg 000001 -> n1z0v0c1; 177777
d=177777 -- !
d=000011 -- ! neg 077777 -> n1z0v0c1; 100001
d=100001 -- !
d=000013 -- ! neg 100000 -> n1z0v1c1; 100000
d=100000 -- !
d=000001 -- ! neg 177777 -> n0z0v0c1; 000001
d=000001 -- !
#--------
C Exec test 46.5wrc0: ADC - reg,C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
005505 -- iut= adc r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! adc 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! adc 000001 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! adc 077777 -> n0z0v0c0; 077777
d=077777 -- !
d=000010 -- ! adc 100000 -> n1z0v0c0; 100000
d=100000 -- !
d=000010 -- ! adc 177777 -> n1z0v0c0; 177777
d=177777 -- !
#--------
C Exec test 46.5wrc1: ADC - reg,C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
005505 -- iut= adc r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000000 -- ! adc 000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! adc 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000012 -- ! adc 077777 -> n1z0v1c0; 100000
d=100000 -- !
d=000010 -- ! adc 100000 -> n1z0v0c0; 100001
d=100001 -- !
d=000005 -- ! adc 177777 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.6wrc0: SBC - reg,C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
005605 -- iut= sbc r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! sbc 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! sbc 000001 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! sbc 077777 -> n0z0v0c0; 077777
d=077777 -- !
d=000010 -- ! sbc 100000 -> n1z0v0c0; 100000
d=100000 -- !
d=000010 -- ! sbc 177777 -> n1z0v0c0; 177777
d=177777 -- !
#--------
C Exec test 46.6wrc1: SBC - reg,C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
005605 -- iut= sbc r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000011 -- ! sbc 000000 -> n1z0v0c1; 177777
d=177777 -- !
d=000004 -- ! sbc 000001 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! sbc 077777 -> n0z0v0c0; 077776
d=077776 -- !
d=000002 -- ! sbc 100000 -> n0z0v1c0; 077777
d=077777 -- !
d=000010 -- ! sbc 177777 -> n1z0v0c0; 177776
d=177776 -- !
#--------
C Exec test 46.7wr: TST - reg
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
005705 -- iut= tst r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! tst 000000 -> n0z1v0c0;
d=000000 -- !
d=000000 -- ! tst 000001 -> n0z0v0c0;
d=000001 -- !
d=000000 -- ! tst 077777 -> n0z0v0c0;
d=077777 -- !
d=000010 -- ! tst 100000 -> n1z0v0c0;
d=100000 -- !
d=000010 -- ! tst 177777 -> n1z0v0c0;
d=177777 -- !
#--------
C Exec test 46.7wm: TST - mem
#
wal 013224 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
005715 -- iut= tst (r5)
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
stapc 013220 -- start @ 13220 (1op mem)
wtgo
rpc d=013240 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! tst 000000 -> n0z1v0c0;
d=000000 -- !
d=000000 -- ! tst 000001 -> n0z0v0c0;
d=000001 -- !
d=000000 -- ! tst 077777 -> n0z0v0c0;
d=077777 -- !
d=000010 -- ! tst 100000 -> n1z0v0c0;
d=100000 -- !
d=000010 -- ! tst 177777 -> n1z0v0c0;
d=177777 -- !
#--------
C Exec test 46.8wrc0: ROR - reg, C=0
#
wal 036000 -- setup test vector: for ror,rol,ars,asl
bwm 7
000000 -- ror 000000
000001 -- ror 000001
100000 -- ror 100000
000100 -- ror 000100
000101 -- ror 000101
040100 -- ror 040100
100100 -- ror 100100
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
006005 -- iut= ror r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! ror 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000007 -- ! ror 000001 -> n0z1v1c1; 000000
d=000000 -- !
d=000000 -- ! ror 100000 -> n0z0v0c0; 040000
d=040000 -- !
d=000000 -- ! ror 000100 -> n0z0v0c0; 000040
d=000040 -- !
d=000003 -- ! ror 000101 -> n0z0v1c1; 000040
d=000040 -- !
d=000000 -- ! ror 040100 -> n0z0v0c0; 020040
d=020040 -- !
d=000000 -- ! ror 100100 -> n0z0v0c0; 040040
d=040040 -- !
#--------
C Exec test 46.8wrc1: ROR - reg, C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
006005 -- iut= ror r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000012 -- ! ror 000000 -> n1z0v1c0; 100000
d=100000 -- !
d=000011 -- ! ror 000001 -> n1z0v0c1; 100000
d=100000 -- !
d=000012 -- ! ror 100000 -> n1z0v1c0; 140000
d=140000 -- !
d=000012 -- ! ror 000100 -> n1z0v1c0; 100040
d=100040 -- !
d=000011 -- ! ror 000101 -> n1z0v0c1; 100040
d=100040 -- !
d=000012 -- ! ror 040100 -> n1z0v1c0; 120040
d=120040 -- !
d=000012 -- ! ror 100100 -> n1z0v1c0; 140040
d=140040 -- !
#--------
C Exec test 46.9wrc0: ROL - reg, C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
006105 -- iut= rol r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! rol 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! rol 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000007 -- ! rol 100000 -> n0z1v1c1; 000000
d=000000 -- !
d=000000 -- ! rol 000100 -> n0z0v0c0; 000200
d=000200 -- !
d=000000 -- ! rol 000101 -> n0z0v0c0; 000202
d=000202 -- !
d=000012 -- ! rol 040100 -> n1z0v1c0; 100200
d=100200 -- !
d=000003 -- ! rol 100100 -> n0z0v1c1; 000200
d=000200 -- !
#--------
C Exec test 46.9wrc1: ROL - reg, C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
006105 -- iut= rol r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000000 -- ! rol 000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! rol 000001 -> n0z0v0c0; 000003
d=000003 -- !
d=000003 -- ! rol 100000 -> n0z0v1c1; 000001
d=000001 -- !
d=000000 -- ! rol 000100 -> n0z0v0c0; 000201
d=000201 -- !
d=000000 -- ! rol 000101 -> n0z0v0c0; 000203
d=000203 -- !
d=000012 -- ! rol 040100 -> n1z0v1c0; 100201
d=100201 -- !
d=000003 -- ! rol 100100 -> n0z0v1c1; 000201
d=000201 -- !
#--------
C Exec test 46.10wrc0: ASR - reg, C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
006205 -- iut= asr r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! asr 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000007 -- ! asr 000001 -> n0z1v1c1; 000000
d=000000 -- !
d=000012 -- ! asr 100000 -> n1z0v1c0; 140000
d=140000 -- !
d=000000 -- ! asr 000100 -> n0z0v0c0; 000040
d=000040 -- !
d=000003 -- ! asr 000101 -> n0z0v1c1; 000040
d=000040 -- !
d=000000 -- ! asr 040100 -> n0z0v0c0; 020040
d=020040 -- !
d=000012 -- ! asr 100100 -> n1z0v1c0; 140040
d=140040 -- !
#--------
C Exec test 46.10wrc1: ASR - reg, C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
006205 -- iut= asr r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! asr 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000007 -- ! asr 000001 -> n0z1v1c1; 000000
d=000000 -- !
d=000012 -- ! asr 100000 -> n1z0v1c0; 140000
d=140000 -- !
d=000000 -- ! asr 000100 -> n0z0v0c0; 000040
d=000040 -- !
d=000003 -- ! asr 000101 -> n0z0v1c1; 000040
d=000040 -- !
d=000000 -- ! asr 040100 -> n0z0v0c0; 020040
d=020040 -- !
d=000012 -- ! asr 100100 -> n1z0v1c0; 140040
d=140040 -- !
#--------
C Exec test 46.11wrc0: ASL - reg, C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
006305 -- iut= asl r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! asl 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! asl 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000007 -- ! asl 100000 -> n0z1v1c1; 000000
d=000000 -- !
d=000000 -- ! asl 000100 -> n0z0v0c0; 000200
d=000200 -- !
d=000000 -- ! asl 000101 -> n0z0v0c0; 000202
d=000202 -- !
d=000012 -- ! asl 040100 -> n1z0v1c0; 100200
d=100200 -- !
d=000003 -- ! asl 100100 -> n0z0v1c1; 000200
d=000200 -- !
#--------
C Exec test 46.11wrc1: ASL - reg, C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
006305 -- iut= asl r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! asl 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! asl 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000007 -- ! asl 100000 -> n0z1v1c1; 000000
d=000000 -- !
d=000000 -- ! asl 000100 -> n0z0v0c0; 000200
d=000200 -- !
d=000000 -- ! asl 000101 -> n0z0v0c0; 000202
d=000202 -- !
d=000012 -- ! asl 040100 -> n1z0v1c0; 100200
d=100200 -- !
d=000003 -- ! asl 100100 -> n0z0v1c1; 000200
d=000200 -- !
#--------
C Exec test 46.12wrc0: MOV - reg, C=0
#
wal 036000 -- setup test vector: for mov
bwm 6
000000 -- mov 000000,000000
000000 --
000001 -- mov 000001,000000
000000 --
100000 -- mov 100000,000000
000000 --
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
010405 -- iut= mov r4,r5
wr0 177776 -- r0=177776
wr1 000003 -- r1=3
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 6
d=000004 -- ! mov 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! mov 000001,000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000010 -- ! mov 100000,000000 -> n1z0v0c0; 100000
d=100000 -- !
#--------
C Exec test 46.12wrc1: MOV - reg, C=1
#
wal 013246 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
010405 -- iut= mov r4,r5
wr0 177776 -- r0=177776
wr1 000003 -- r1=3
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 6
d=000005 -- ! mov 000000,000000 -> n0z1v0c1; 000000
d=000000 -- !
d=000001 -- ! mov 000001,000000 -> n0z0v0c1; 000001
d=000001 -- !
d=000011 -- ! mov 100000,000000 -> n1z0v0c1; 100000
d=100000 -- !
#--------
C Exec test 46.12mc0: MOV - mem, C=0
#
wal 013276 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
011415 -- iut= mov (r4),(r5)
wr0 177776 -- r0=177776
wr1 000003 -- r1=3
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
stapc 013270 -- start @ 13270 (2op mem)
wtgo
rpc d=013312 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 6
d=000004 -- ! mov 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! mov 000001,000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000010 -- ! mov 100000,000000 -> n1z0v0c0; 100000
d=100000 -- !
#--------
C Exec test 46.13wrc0: BIT - reg, C=0
#
wal 036000 -- setup test vector: for bit,bic,bis,xor
bwm 12
000000 -- bit 000000,000000
000000 --
000011 -- bit 000011,000000
000000 --
000011 -- bit 000011,000110
000110 --
000011 -- bit 000011,001100
001100 --
110000 -- bit 110000,011000
011000 --
110000 -- bit 110000,110000
110000 --
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
030405 -- iut= bit r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bit 000000,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000004 -- ! bit 000011,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000000 -- ! bit 000011,000110 -> n0z0v0c0; (000010)
d=000110 -- !
d=000004 -- ! bit 000011,001100 -> n0z1v0c0; (000000)
d=001100 -- !
d=000000 -- ! bit 110000,011000 -> n0z0v0c0; (010000)
d=011000 -- !
d=000010 -- ! bit 110000,110000 -> n1z0v0c0; (100000)
d=110000 -- !
#--------
C Exec test 46.13wrc1: BIT - reg, C=1
#
wal 013246 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
030405 -- iut= bit r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000005 -- ! bit 000000,000000 -> n0z1v0c1; (000000)
d=000000 -- !
d=000005 -- ! bit 000011,000000 -> n0z1v0c1; (000000)
d=000000 -- !
d=000001 -- ! bit 000011,000110 -> n0z0v0c1; (000010)
d=000110 -- !
d=000005 -- ! bit 000011,001100 -> n0z1v0c1; (000000)
d=001100 -- !
d=000001 -- ! bit 110000,011000 -> n0z0v0c1; (010000)
d=011000 -- !
d=000011 -- ! bit 110000,110000 -> n1z0v0c1; (100000)
d=110000 -- !
#--------
C Exec test 46.13wmc0: BIT - mem, C=0
#
wal 013276 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
031415 -- iut= bit (r4),(r5)
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
stapc 013270 -- start @ 13270 (2op mem)
wtgo
rpc d=013312 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bit 000000,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000004 -- ! bit 000011,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000000 -- ! bit 000011,000110 -> n0z0v0c0; (000010)
d=000110 -- !
d=000004 -- ! bit 000011,001100 -> n0z1v0c0; (000000)
d=001100 -- !
d=000000 -- ! bit 110000,011000 -> n0z0v0c0; (010000)
d=011000 -- !
d=000010 -- ! bit 110000,110000 -> n1z0v0c0; (100000)
d=110000 -- !
#--------
C Exec test 46.14wrc0: BIC - reg, C=0
#
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
040405 -- iut= bic r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bic 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000004 -- ! bic 000011,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! bic 000011,000110 -> n0z0v0c0; 000100
d=000100 -- !
d=000000 -- ! bic 000011,001100 -> n0z0v0c0; 001100
d=001100 -- !
d=000000 -- ! bic 110000,011000 -> n0z0v0c0; 001000
d=001000 -- !
d=000004 -- ! bic 110000,110000 -> n0z1v0c0; 000000
d=000000 -- !
#--------
C Exec test 46.14wrc1: BIC - reg, C=1
#
wal 013246 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
040405 -- iut= bic r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000005 -- ! bic 000000,000000 -> n0z1v0c1; 000000
d=000000 -- !
d=000005 -- ! bic 000011,000000 -> n0z1v0c1; 000000
d=000000 -- !
d=000001 -- ! bic 000011,000110 -> n0z0v0c1; 000100
d=000100 -- !
d=000001 -- ! bic 000011,001100 -> n0z0v0c1; 001100
d=001100 -- !
d=000001 -- ! bic 110000,011000 -> n0z0v0c1; 001000
d=001000 -- !
d=000005 -- ! bic 110000,110000 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.14wrc0: BIC - mem, C=0
#
wal 013276 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
041415 -- iut= bic (r4),(r5)
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
stapc 013270 -- start @ 13270 (2op mem)
wtgo
rpc d=013312 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bic 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000004 -- ! bic 000011,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! bic 000011,000110 -> n0z0v0c0; 000100
d=000100 -- !
d=000000 -- ! bic 000011,001100 -> n0z0v0c0; 001100
d=001100 -- !
d=000000 -- ! bic 110000,011000 -> n0z0v0c0; 001000
d=001000 -- !
d=000004 -- ! bic 110000,110000 -> n0z1v0c0; 000000
d=000000 -- !
#--------
C Exec test 46.15wrc0: BIS - reg, C=0
#
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
050405 -- iut= bis r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bis 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! bis 000011,000000 -> n0z0v0c0; 000011
d=000011 -- !
d=000000 -- ! bis 000011,000110 -> n0z0v0c0; 000111
d=000111 -- !
d=000000 -- ! bis 000011,001100 -> n0z0v0c0; 001111
d=001111 -- !
d=000010 -- ! bis 110000,011000 -> n1z0v0c0; 111000
d=111000 -- !
d=000010 -- ! bis 110000,110000 -> n1z0v0c0; 110000
d=110000 -- !
#--------
C Exec test 46.15wrc1: BIS - reg, C=1
#
wal 013246 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
050405 -- iut= bis r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000005 -- ! bis 000000,000000 -> n0z1v0c1; 000000
d=000000 -- !
d=000001 -- ! bis 000011,000000 -> n0z0v0c1; 000011
d=000011 -- !
d=000001 -- ! bis 000011,000110 -> n0z0v0c1; 000111
d=000111 -- !
d=000001 -- ! bis 000011,001100 -> n0z0v0c1; 001111
d=001111 -- !
d=000011 -- ! bis 110000,011000 -> n1z0v0c1; 111000
d=111000 -- !
d=000011 -- ! bis 110000,110000 -> n1z0v0c1; 110000
d=110000 -- !
#--------
C Exec test 46.16wrc0: XOR - reg, C=0
#
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
074405 -- iut= xor r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! xor 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! xor 000011,000000 -> n0z0v0c0; 000011
d=000011 -- !
d=000000 -- ! xor 000011,000110 -> n0z0v0c0; 000101
d=000101 -- !
d=000000 -- ! xor 000011,001100 -> n0z0v0c0; 001111
d=001111 -- !
d=000010 -- ! xor 110000,011000 -> n1z0v0c0; 101000
d=101000 -- !
d=000004 -- ! xor 110000,110000 -> n1z0v0c0; 000000
d=000000 -- !
#--------
C Exec test 46.16wrc1: XOR - reg, C=1
#
wal 013246 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
074405 -- iut= xor r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000005 -- ! xor 000000,000000 -> n0z1v0c1; 000000
d=000000 -- !
d=000001 -- ! xor 000011,000000 -> n0z0v0c1; 000011
d=000011 -- !
d=000001 -- ! xor 000011,000110 -> n0z0v0c1; 000101
d=000101 -- !
d=000001 -- ! xor 000011,001100 -> n0z0v0c1; 001111
d=001111 -- !
d=000011 -- ! xor 110000,011000 -> n1z0v0c1; 101000
d=101000 -- !
d=000005 -- ! xor 110000,110000 -> n1z0v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.17wr: CMP - reg
#
wal 036000 -- setup test vector: for cmp,add,sub
bwm 38
000000 -- cmp 000000,000000
000000 --
000001 -- cmp 000001,000000
000000 --
177777 -- cmp 177777,000000
000000 --
000000 -- cmp 000000,000001
000001 --
000001 -- cmp 000001,000001
000001 --
177777 -- cmp 177777,000001
000001 --
077776 -- cmp 077776,077777
077777 --
077777 -- cmp 077777,077777
077777 --
100000 -- cmp 100000,077777
077777 --
000001 -- cmp 000001,077777
077777 --
177777 -- cmp 177777,077777
077777 --
077777 -- cmp 077777,100000
100000 --
100000 -- cmp 100000,100000
100000 --
100001 -- cmp 100001,100000
100000 --
000001 -- cmp 000001,100000
100000 --
177777 -- cmp 177777,100000
100000 --
000000 -- cmp 000000,177777
177777 --
000001 -- cmp 000001,177777
177777 --
177777 -- cmp 177777,177777
177777 --
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
020405 -- iut= cmp r4,r5
wr0 177776 -- r0=177776
wr1 000023 -- r1=23 (19.)
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0 (Note: C=1 if dst > src unsigned)
wal 037000 -- check result area (Note: V=1 if s xor d and r eq d)
brm 38
d=000004 -- ! cmp 000000,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000000 -- ! cmp 000001,000000 -> n0z0v0c0; (000001)
d=000000 -- !
d=000010 -- ! cmp 177777,000000 -> n1z0v0c0; (177777)
d=000000 -- !
d=000011 -- ! cmp 000000,000001 -> n1z0v0c1; (177777+C)
d=000001 -- !
d=000004 -- ! cmp 000001,000001 -> n0z1v0c0; (000000)
d=000001 -- !
d=000010 -- ! cmp 177777,000001 -> n1z0v0c0; (177776)
d=000001 -- !
d=000011 -- ! cmp 077776,077777 -> n1z0v0c1; (177777+C)
d=077777 -- !
d=000004 -- ! cmp 077777,077777 -> n0z1v0c0; (000000)
d=077777 -- !
d=000002 -- ! cmp 100000,077777 -> n0z0v1c0; (000001)
d=077777 -- !
d=000011 -- ! cmp 000001,077777 -> n1z0v0c1; (100002+C)
d=077777 -- !
d=000010 -- ! cmp 177777,077777 -> n1z0v0c0; (100000)
d=077777 -- !
d=000013 -- ! cmp 077777,100000 -> n1z0v1c1; (177777+C)
d=100000 -- !
d=000004 -- ! cmp 100000,100000 -> n0z1v0c0; (000000)
d=100000 -- !
d=000000 -- ! cmp 100001,100000 -> n0z0v0c0; (000001)
d=100000 -- !
d=000013 -- ! cmp 000001,100000 -> n1z0v1c1; (100001+C)
d=100000 -- !
d=000000 -- ! cmp 177777,100000 -> n0z0v0c0; (077777)
d=100000 -- !
d=000001 -- ! cmp 000000,177777 -> n0z0v0c1; (000001+C)
d=177777 -- !
d=000001 -- ! cmp 000001,177777 -> n0z0v0c1; (000002+C)
d=177777 -- !
d=000004 -- ! cmp 177777,177777 -> n0z1v0c0; (000000)
d=177777 -- !
#--------
C Exec test 46.18r: ADD - reg
#
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
060405 -- iut= add r4,r5
wr0 177776 -- r0=177776
wr1 000023 -- r1=23 (19.)
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V=1 if s eq d and r neq d)
brm 38
d=000004 -- ! add 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! add 000001,000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000010 -- ! add 177777,000000 -> n1z0v0c0; 177777
d=177777 -- !
d=000000 -- ! add 000000,000001 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! add 000001,000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000005 -- ! add 177777,000001 -> n0z1v0c1; 000000+C
d=000000 -- !
d=000012 -- ! add 077776,077777 -> n1z0v1c0; 177775
d=177775 -- !
d=000012 -- ! add 077777,077777 -> n1z0v1c0; 177776
d=177776 -- !
d=000010 -- ! add 100000,077777 -> n1z0v0c0; 177777
d=177777 -- !
d=000012 -- ! add 000001,077777 -> n1z0v1c0; 100000
d=100000 -- !
d=000001 -- ! add 177777,077777 -> n0z0v0c1; 077776+C
d=077776 -- !
d=000010 -- ! add 077777,100000 -> n1z0v0c1; 177777+C
d=177777 -- !
d=000007 -- ! add 100000,100000 -> n0z1v1c1; 000000+C
d=000000 -- !
d=000003 -- ! add 100001,100000 -> n0z0v1c1; 000001+C
d=000001 -- !
d=000010 -- ! add 000001,100000 -> n1z0v0c0; 100001
d=100001 -- !
d=000003 -- ! add 177777,100000 -> n0z0v1c1; 077777+C
d=077777 -- !
d=000010 -- ! add 000000,177777 -> n1z0v0c0; 177777
d=177777 -- !
d=000005 -- ! add 000001,177777 -> n0z1v0c1; 000000+C
d=000000 -- !
d=000011 -- ! add 177777,177777 -> n1z0v0c1; 177776+C
d=177776 -- !
#--------
C Exec test 46.19r: SUB - reg
#
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
160405 -- iut= sub r4,r5
wr0 177776 -- r0=177776
wr1 000023 -- r1=23 (19.)
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0 (Note: C=1 if src > dst unsigned)
wal 037000 -- check result area (Note: V=1 if s xor d and r eq s)
brm 38
d=000004 -- ! sub 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000011 -- ! sub 000001,000000 -> n1z0v0c1; 177777+C
d=177777 -- !
d=000001 -- ! sub 177777,000000 -> n0z0v0c1; 000001+C
d=000001 -- !
d=000000 -- ! sub 000000,000001 -> n0z0v0c0; 000001
d=000001 -- !
d=000004 -- ! sub 000001,000001 -> n0z1v0c0; 000000
d=000000 -- !
d=000001 -- ! sub 177777,000001 -> n0z0v0c1; 000002+C
d=000002 -- !
d=000000 -- ! sub 077776,077777 -> n0z0v0c0; 000001
d=000001 -- !
d=000004 -- ! sub 077777,077777 -> n0z1v0c0; 000000
d=000000 -- !
d=000013 -- ! sub 100000,077777 -> n1z0v1c1; 177777+C
d=177777 -- !
d=000000 -- ! sub 000001,077777 -> n0z0v0c0; 077776
d=077776 -- !
d=000013 -- ! sub 177777,077777 -> n1z0v1c1; 100000+C
d=100000 -- !
d=000002 -- ! sub 077777,100000 -> n0z0v1c0; 000001
d=000001 -- !
d=000004 -- ! sub 100000,100000 -> n0z1v0c0; 000000
d=000000 -- !
d=000011 -- ! sub 100001,100000 -> n1z0v0c1; 177777+C
d=177777 -- !
d=000002 -- ! sub 000001,100000 -> n0z0v1c0; 077777
d=077777 -- !
d=000011 -- ! sub 177777,100000 -> n1z0v0c1: 100001+C
d=100001 -- !
d=000010 -- ! sub 000000,177777 -> n1z0v0c0; 177777
d=177777 -- !
d=000010 -- ! sub 000001,177777 -> n1z0v0c0; 177776
d=177776 -- !
d=000004 -- ! sub 177777,177777 -> n0z1v0c0; 000000
d=000000 -- !
#
C Exec test 46.20r: SWAP - reg
#
wal 036000 -- setup test vector: for swap
bwm 9
000000 -- swap 000000
000001 -- swap 000001
000200 -- swap 000200
000400 -- swap 000400
100000 -- swap 100000
000401 -- swap 000401
000600 -- swap 000600
100001 -- swap 100001
100200 -- swap 100200
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
000305 -- iut= swap r5
wr0 177776 -- r0=177776
wr1 000011 -- r1=11 (9.)
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: N,Z from lsb of result)
brm 18
d=000004 -- ! swap 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000004 -- ! swap 000001 -> n0z1v0c0; 000400
d=000400 -- !
d=000004 -- ! swap 000200 -> n0z1v0c0; 100000
d=100000 -- !
d=000000 -- ! swap 000400 -> n0z0v0c0; 000001
d=000001 -- !
d=000010 -- ! swap 100000 -> n1z0v0c0; 000200
d=000200 -- !
d=000000 -- ! swap 000401 -> n0z0v0c0; 000401
d=000401 -- !
d=000000 -- ! swap 000600 -> n0z0v0c0; 100001
d=100001 -- !
d=000010 -- ! swap 100001 -> n1z0v0c0; 000600
d=000600 -- !
d=000010 -- ! swap 100200 -> n1z0v0c0; 100200
d=100200 -- !
#--------
C Exec code 46 pass 2 (systematic result+cc test of 1+2op instructions; byte)
C Exec test 46.1br: COMB - reg
#
wal 036000 -- setup test vector: for com,inc,dec,neg,adc,sbc,tst (b)
bwm 5
000000 -- comb 000000
000001 -- comb 000001
000177 -- comb 000177
000200 -- comb 000200
000377 -- comb 000377
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
105105 -- iut= comb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000011 -- ! comb 000000 -> n1z0v0c1; 000377
d=000377 -- !
d=000011 -- ! comb 000001 -> n1z0v0c1; 000376
d=000376 -- !
d=000011 -- ! comb 000177 -> n1z0v0c1; 000200
d=000200 -- !
d=000001 -- ! comb 000200 -> n0z0v0c1; 000177
d=000177 -- !
d=000005 -- ! comb 000377 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.1bm: COMB - mem
#
wal 013224 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
105115 -- iut= comb (r5)
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
stapc 013220 -- start @ 13220 (1op mem)
wtgo
rpc d=013240 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000011 -- ! comb 000000 -> n1z0v0c1; 000377
d=000377 -- !
d=000011 -- ! comb 000001 -> n1z0v0c1; 000376
d=000376 -- !
d=000011 -- ! comb 000177 -> n1z0v0c1; 000200
d=000200 -- !
d=000001 -- ! comb 000200 -> n0z0v0c1; 000177
d=000177 -- !
d=000005 -- ! comb 000377 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.2brc0: INCB - reg,C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
105205 -- iut= incb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000000 -- ! incb 000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! incb 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000012 -- ! incb 000177 -> n1z0v1c0; 000200
d=000200 -- !
d=000010 -- ! incb 000200 -> n1z0v0c0; 000201
d=000201 -- !
d=000004 -- ! incb 000377 -> n0z1v0c0; 000000
d=000000 -- !
#--------
C Exec test 46.2brc1: INCB - reg,C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
105205 -- iut= incb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000001 -- ! incb 000000 -> n0z0v0c1; 000001
d=000001 -- !
d=000001 -- ! incb 000001 -> n0z0v0c1; 000002
d=000002 -- !
d=000013 -- ! incb 000177 -> n1z0v1c1; 000200
d=000200 -- !
d=000011 -- ! incb 000200 -> n1z0v0c1; 000201
d=000201 -- !
d=000005 -- ! incb 000377 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.3brc0: DECB - reg,C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
105305 -- iut= decb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000010 -- ! decb 000000 -> n1z0v0c0; 000377
d=000377 -- !
d=000004 -- ! decb 000001 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! decb 000177 -> n0z0v0c0; 000176
d=000176 -- !
d=000002 -- ! decb 000200 -> n0z0v1c0; 000177
d=000177 -- !
d=000010 -- ! decb 000377 -> n1z0v0c0; 000376
d=000376 -- !
#--------
C Exec test 46.3brc1: DECB - reg,C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
105305 -- iut= decb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000011 -- ! decb 000000 -> n1z0v0c1; 000377
d=000377 -- !
d=000005 -- ! decb 000001 -> n0z1v0c1; 000000
d=000000 -- !
d=000001 -- ! decb 000177 -> n0z0v0c1; 000176
d=000176 -- !
d=000003 -- ! decb 000200 -> n0z0v1c1; 000177
d=000177 -- !
d=000011 -- ! decb 000377 -> n1z0v0c1; 000376
d=000376 -- !
#--------
C Exec test 46.4br: NEGB - reg
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
105405 -- iut= negb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! negb 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000011 -- ! negb 000001 -> n1z0v0c1; 000377
d=000377 -- !
d=000011 -- ! negb 000177 -> n1z0v0c1; 000201
d=000201 -- !
d=000013 -- ! negb 000200 -> n1z0v1c1; 000200
d=000200 -- !
d=000001 -- ! negb 000377 -> n0z0v0c1; 000001
d=000001 -- !
#--------
C Exec test 46.5brc0: ADCB - reg,C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
105505 -- iut= adcb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! adcb 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! adcb 000001 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! adcb 000177 -> n0z0v0c0; 000177
d=000177 -- !
d=000010 -- ! adcb 000200 -> n1z0v0c0; 000200
d=000200 -- !
d=000010 -- ! adcb 000377 -> n1z0v0c0; 000377
d=000377 -- !
#--------
C Exec test 46.5brc1: ADCB - reg,C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
105505 -- iut= adcb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000000 -- ! adcb 000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! adcb 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000012 -- ! adcb 000177 -> n1z0v1c0; 000200
d=000200 -- !
d=000010 -- ! adcb 000200 -> n1z0v0c0; 000201
d=000201 -- !
d=000005 -- ! adcb 000377 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.6brc0: SBCB - reg,C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
105605 -- iut= sbcb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! sbcb 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! sbcb 000001 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! sbcb 000177 -> n0z0v0c0; 000177
d=000177 -- !
d=000010 -- ! sbcb 000200 -> n1z0v0c0; 000200
d=000200 -- !
d=000010 -- ! sbcb 000377 -> n1z0v0c0; 000377
d=000377 -- !
#--------
C Exec test 46.6brc1: SBCB - reg,C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
105605 -- iut= sbcb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000011 -- ! sbcb 000000 -> n1z0v0c1; 000377
d=000377 -- !
d=000004 -- ! sbcb 000001 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! sbcb 000177 -> n0z0v0c0; 000176
d=000176 -- !
d=000002 -- ! sbcb 000200 -> n0z0v1c0; 000177
d=000177 -- !
d=000010 -- ! sbcb 000377 -> n1z0v0c0; 000376
d=000376 -- !
#--------
C Exec test 46.7br: TSTB - reg
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
105705 -- iut= tstb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! tstb 000000 -> n0z1v0c0;
d=000000 -- !
d=000000 -- ! tstb 000001 -> n0z0v0c0;
d=000001 -- !
d=000000 -- ! tstb 000177 -> n0z0v0c0;
d=000177 -- !
d=000010 -- ! tstb 000200 -> n1z0v0c0;
d=000200 -- !
d=000010 -- ! tstb 000377 -> n1z0v0c0;
d=000377 -- !
#--------
C Exec test 46.7bm: TSTB - mem
#
wal 013224 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
105715 -- iut= tstb (r5)
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
stapc 013220 -- start @ 13220 (1op mem)
wtgo
rpc d=013240 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! tstb 000000 -> n0z1v0c0;
d=000000 -- !
d=000000 -- ! tstb 000001 -> n0z0v0c0;
d=000001 -- !
d=000000 -- ! tstb 000177 -> n0z0v0c0;
d=000177 -- !
d=000010 -- ! tstb 000200 -> n1z0v0c0;
d=000200 -- !
d=000010 -- ! tstb 000377 -> n1z0v0c0;
d=000377 -- !
#--------
C Exec test 46.8brc0: RORB - reg, C=0
#
wal 036000 -- setup test vector: for ror,rol,ars,asl (b)
bwm 7
000000 -- ror 000000
000001 -- ror 000001
000200 -- ror 000200
000010 -- ror 000010
000011 -- ror 000011
000110 -- ror 000110
000210 -- ror 000210
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
106005 -- iut= rorb r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! rorb 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000007 -- ! rorb 000001 -> n0z1v1c1; 000000
d=000000 -- !
d=000000 -- ! rorb 000200 -> n0z0v0c0; 000100
d=000100 -- !
d=000000 -- ! rorb 000010 -> n0z0v0c0; 000004
d=000004 -- !
d=000003 -- ! rorb 000011 -> n0z0v1c1; 000004
d=000004 -- !
d=000000 -- ! rorb 000110 -> n0z0v0c0; 000044
d=000044 -- !
d=000000 -- ! rorb 000210 -> n0z0v0c0; 000104
d=000104 -- !
#--------
C Exec test 46.8brc1: RORB - reg, C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
106005 -- iut= rorb r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000012 -- ! rorb 000000 -> n1z0v1c0; 000200
d=000200 -- !
d=000011 -- ! rorb 000001 -> n1z0v0c1; 000200
d=000200 -- !
d=000012 -- ! rorb 000200 -> n1z0v1c0; 000300
d=000300 -- !
d=000012 -- ! rorb 000010 -> n1z0v1c0; 000204
d=000204 -- !
d=000011 -- ! rorb 000011 -> n1z0v0c1; 000204
d=000204 -- !
d=000012 -- ! rorb 000110 -> n1z0v1c0; 000244
d=000244 -- !
d=000012 -- ! rorb 000210 -> n1z0v1c0; 000304
d=000304 -- !
#--------
C Exec test 46.9brc0: ROLB - reg, C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
106105 -- iut= rolb r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! rolb 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! rolb 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000007 -- ! rolb 000200 -> n0z1v1c1; 000000
d=000000 -- !
d=000000 -- ! rolb 000010 -> n0z0v0c0; 000020
d=000020 -- !
d=000000 -- ! rolb 000011 -> n0z0v0c0; 000022
d=000022 -- !
d=000012 -- ! rolb 000110 -> n1z0v1c0; 000220
d=000220 -- !
d=000003 -- ! rolb 000210 -> n0z0v1c1; 000020
d=000020 -- !
#--------
C Exec test 46.9brc1: ROLB - reg, C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
106105 -- iut= rolb r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000000 -- ! rolb 000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! rolb 000001 -> n0z0v0c0; 000003
d=000003 -- !
d=000003 -- ! rolb 000200 -> n0z0v1c1; 000001
d=000001 -- !
d=000000 -- ! rolb 000010 -> n0z0v0c0; 000021
d=000021 -- !
d=000000 -- ! rolb 000011 -> n0z0v0c0; 000023
d=000023 -- !
d=000012 -- ! rolb 000110 -> n1z0v1c0; 000221
d=000221 -- !
d=000003 -- ! rolb 000210 -> n0z0v1c1; 000021
d=000021 -- !
#--------
C Exec test 46.10brc0: ASRB - reg, C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
106205 -- iut= asrb r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! asrb 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000007 -- ! asrb 000001 -> n0z1v1c1; 000000
d=000000 -- !
d=000012 -- ! asrb 000200 -> n1z0v1c0; 000300
d=000300 -- !
d=000000 -- ! asrb 000010 -> n0z0v0c0; 000004
d=000004 -- !
d=000003 -- ! asrb 000011 -> n0z0v1c1; 000004
d=000004 -- !
d=000000 -- ! asrb 000110 -> n0z0v0c0; 000044
d=000044 -- !
d=000012 -- ! asrb 000210 -> n1z0v1c0; 000304
d=000304 -- !
#--------
C Exec test 46.10brc1: ASRB - reg, C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
106205 -- iut= asrb r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! asrb 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000007 -- ! asrb 000001 -> n0z1v1c1; 000000
d=000000 -- !
d=000012 -- ! asrb 000200 -> n1z0v1c0; 000300
d=000300 -- !
d=000000 -- ! asrb 000010 -> n0z0v0c0; 000004
d=000004 -- !
d=000003 -- ! asrb 000011 -> n0z0v1c1; 000004
d=000004 -- !
d=000000 -- ! asrb 000110 -> n0z0v0c0; 000044
d=000044 -- !
d=000012 -- ! asrb 000210 -> n1z0v1c0; 000304
d=000304 -- !
#--------
C Exec test 46.11brc0: ASLB - reg, C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
106305 -- iut= aslb r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! aslb 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! aslb 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000007 -- ! aslb 000200 -> n0z1v1c1; 000000
d=000000 -- !
d=000000 -- ! aslb 000010 -> n0z0v0c0; 000020
d=000020 -- !
d=000000 -- ! aslb 000011 -> n0z0v0c0; 000022
d=000022 -- !
d=000012 -- ! aslb 000110 -> n1z0v1c0; 000220
d=000220 -- !
d=000003 -- ! aslb 000210 -> n0z0v1c1; 000020
d=000020 -- !
#--------
C Exec test 46.11brc1: ASLB - reg, C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
106305 -- iut= aslb r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! aslb 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! aslb 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000007 -- ! aslb 000200 -> n0z1v1c1; 000000
d=000000 -- !
d=000000 -- ! aslb 000010 -> n0z0v0c0; 000020
d=000020 -- !
d=000000 -- ! aslb 000011 -> n0z0v0c0; 000022
d=000022 -- !
d=000012 -- ! aslb 000110 -> n1z0v1c0; 000220
d=000220 -- !
d=000003 -- ! aslb 000210 -> n0z0v1c1; 000020
d=000020 -- !
#--------
C Exec test 46.12brc0: MOVB - reg, C=0
#
wal 036000 -- setup test vector: for mov
bwm 6
000000 -- movb 000000,000000
000000 --
000001 -- movb 000001,000000
000000 --
000200 -- movb 000200,000000
000000 --
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
110405 -- iut= movb r4,r5
wr0 177776 -- r0=177776
wr1 000003 -- r1=3
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 6
d=000004 -- ! movb 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! movb 000001,000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000010 -- ! movb 000200,000000 -> n1z0v0c0; 177600
d=177600 -- !
#--------
C Exec test 46.12brc1: MOVB - reg, C=1
#
wal 013246 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
110405 -- iut= movb r4,r5
wr0 177776 -- r0=177776
wr1 000003 -- r1=3
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 6
d=000005 -- ! movb 000000,000000 -> n0z1v0c1; 000000
d=000000 -- !
d=000001 -- ! movb 000001,000000 -> n0z0v0c1; 000001
d=000001 -- !
d=000011 -- ! movb 000200,000000 -> n1z0v0c1; 177600
d=177600 -- !
#--------
C Exec test 46.12bmc0: MOVB - mem, C=0
#
wal 013276 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
111415 -- iut= movb (r4),(r5)
wr0 177776 -- r0=177776
wr1 000003 -- r1=3
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
stapc 013270 -- start @ 13270 (2op mem)
wtgo
rpc d=013312 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 6
d=000004 -- ! movb 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! movb 000001,000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000010 -- ! movb 000200,000000 -> n1z0v0c0; 000200
d=000200 -- !
#--------
C Exec test 46.13brc0: BITB - reg, C=0
#
wal 036000 -- setup test vector: for bit,bic,bis (b)
bwm 12
000000 -- bitb 000000,000000
000000 --
000003 -- bitb 000003,000000
000000 --
000003 -- bitb 000003,000006
000006 --
000003 -- bitb 000003,000014
000014 --
000300 -- bitb 000300,000140
000140 --
000300 -- bitb 000300,000300
000300 --
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
130405 -- iut= bitb r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bitb 000000,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000004 -- ! bitb 000003,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000000 -- ! bitb 000003,000006 -> n0z0v0c0; (000002)
d=000006 -- !
d=000004 -- ! bitb 000003,000014 -> n0z1v0c0; (000000)
d=000014 -- !
d=000000 -- ! bitb 000300,000140 -> n0z0v0c0; (000100)
d=000140 -- !
d=000010 -- ! bitb 000300,000300 -> n1z0v0c0; (000300)
d=000300 -- !
#--------
C Exec test 46.13brc1: BITB - reg, C=1
#
wal 013246 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
130405 -- iut= bitb r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000005 -- ! bitb 000000,000000 -> n0z1v0c1; (000000)
d=000000 -- !
d=000005 -- ! bitb 000003,000000 -> n0z1v0c1; (000000)
d=000000 -- !
d=000001 -- ! bitb 000003,000006 -> n0z0v0c1; (000002)
d=000006 -- !
d=000005 -- ! bitb 000003,000014 -> n0z1v0c1; (000000)
d=000014 -- !
d=000001 -- ! bitb 000300,000140 -> n0z0v0c1; (000100)
d=000140 -- !
d=000011 -- ! bitb 000300,000300 -> n1z0v0c1; (000300)
d=000300 -- !
#--------
C Exec test 46.13bmc0: BITB - mem, C=0
#
wal 013276 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
131415 -- iut= bitb (r4),(r5)
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
stapc 013270 -- start @ 13270 (2op mem)
wtgo
rpc d=013312 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bitb 000000,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000004 -- ! bitb 000003,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000000 -- ! bitb 000003,000006 -> n0z0v0c0; (000002)
d=000006 -- !
d=000004 -- ! bitb 000003,000014 -> n0z1v0c0; (000000)
d=000014 -- !
d=000000 -- ! bitb 000300,000140 -> n0z0v0c0; (000100)
d=000140 -- !
d=000010 -- ! bitb 000300,000300 -> n1z0v0c0; (000300)
d=000300 -- !
#--------
C Exec test 46.14brc0: BICB - reg, C=0
#
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
140405 -- iut= bicb r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bicb 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000004 -- ! bicb 000003,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! bicb 000003,000006 -> n0z0v0c0; 000004
d=000004 -- !
d=000000 -- ! bicb 000003,000014 -> n0z0v0c0; 000014
d=000014 -- !
d=000000 -- ! bicb 000300,000140 -> n0z0v0c0; 000040
d=000040 -- !
d=000004 -- ! bicb 000300,000300 -> n0z1v0c0; 000000
d=000000 -- !
#--------
C Exec test 46.14brc1: BICB - reg, C=1
#
wal 013246 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
140405 -- iut= bicb r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000005 -- ! bicb 000000,000000 -> n0z1v0c1; 000000
d=000000 -- !
d=000005 -- ! bicb 000003,000000 -> n0z1v0c1; 000000
d=000000 -- !
d=000001 -- ! bicb 000003,000006 -> n0z0v0c1; 000004
d=000004 -- !
d=000001 -- ! bicb 000003,000014 -> n0z0v0c1; 000014
d=000014 -- !
d=000001 -- ! bicb 000300,000140 -> n0z0v0c1; 000040
d=000040 -- !
d=000005 -- ! bicb 000300,000300 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.14bmrc0: BICB - mem, C=0
#
wal 013276 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
141415 -- iut= bicb (r4),(r5)
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
stapc 013270 -- start @ 13270 (2op mem)
wtgo
rpc d=013312 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bicb 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000004 -- ! bicb 000003,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! bicb 000003,000006 -> n0z0v0c0; 000004
d=000004 -- !
d=000000 -- ! bicb 000003,000014 -> n0z0v0c0; 000014
d=000014 -- !
d=000000 -- ! bicb 000300,000140 -> n0z0v0c0; 000040
d=000040 -- !
d=000004 -- ! bicb 000300,000300 -> n0z1v0c0; 000000
d=000000 -- !
#--------
C Exec test 46.15brc0: BISB - reg, C=0
#
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
150405 -- iut= bisb r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bisb 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! bisb 000003,000000 -> n0z0v0c0; 000003
d=000003 -- !
d=000000 -- ! bisb 000003,000006 -> n0z0v0c0; 000007
d=000007 -- !
d=000000 -- ! bisb 000003,000014 -> n0z0v0c0; 000017
d=000017 -- !
d=000010 -- ! bisb 000300,000140 -> n1z0v0c0; 000340
d=000340 -- !
d=000010 -- ! bisb 000300,000300 -> n1z0v0c0; 000300
d=000300 -- !
#--------
C Exec test 46.15brc1: BISB - reg, C=1
#
wal 013246 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
150405 -- iut= bisb r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000005 -- ! bisb 000000,000000 -> n0z1v0c1; 000000
d=000000 -- !
d=000001 -- ! bisb 000003,000000 -> n0z0v0c1; 000003
d=000003 -- !
d=000001 -- ! bisb 000003,000006 -> n0z0v0c1; 000007
d=000007 -- !
d=000001 -- ! bisb 000003,000014 -> n0z0v0c1; 000017
d=000017 -- !
d=000011 -- ! bisb 000300,000140 -> n1z0v0c1; 000340
d=000340 -- !
d=000011 -- ! bisb 000300,000300 -> n1z0v0c1; 000300
d=000300 -- !
#--------
C Exec test 46.17br: CMPB - reg
#
wal 036000 -- setup test vector: for cmp (b)
bwm 38
000000 -- cmpb 000000,000000
000000 --
000001 -- cmpb 000001,000000
000000 --
000377 -- cmpb 000377,000000
000000 --
000000 -- cmpb 000000,000001
000001 --
000001 -- cmpb 000001,000001
000001 --
000377 -- cmpb 000377,000001
000001 --
000176 -- cmpb 000176,000177
000177 --
000177 -- cmpb 000177,000177
000177 --
000200 -- cmpb 000200,000177
000177 --
000001 -- cmpb 000001,000177
000177 --
000377 -- cmpb 000377,000177
000177 --
000177 -- cmpb 000177,000200
000200 --
000200 -- cmpb 000200,000200
000200 --
000201 -- cmpb 000201,000200
000200 --
000001 -- cmpb 000001,000200
000200 --
000377 -- cmpb 000377,000200
000200 --
000000 -- cmpb 000000,000377
000377 --
000001 -- cmpb 000001,000377
000377 --
000377 -- cmpb 000377,000377
000377 --
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
120405 -- iut= cmpb r4,r5
wr0 177776 -- r0=177776
wr1 000023 -- r1=23 (19.)
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0 (Note: C=1 if dst > src unsigned)
wal 037000 -- check result area (Note: V=1 if s xor d and r eq d)
brm 38
d=000004 -- ! cmpb 000000,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000000 -- ! cmpb 000001,000000 -> n0z0v0c0; (000001)
d=000000 -- !
d=000010 -- ! cmpb 000377,000000 -> n1z0v0c0; (000377)
d=000000 -- !
d=000011 -- ! cmpb 000000,000001 -> n1z0v0c1; (000377+C)
d=000001 -- !
d=000004 -- ! cmpb 000001,000001 -> n0z1v0c0; (000000)
d=000001 -- !
d=000010 -- ! cmpb 000377,000001 -> n1z0v0c0; (000376)
d=000001 -- !
d=000011 -- ! cmpb 000176,000177 -> n1z0v0c1; (000377+C)
d=000177 -- !
d=000004 -- ! cmpb 000177,000177 -> n0z1v0c0; (000000)
d=000177 -- !
d=000002 -- ! cmpb 000200,000177 -> n0z0v1c0; (000001)
d=000177 -- !
d=000011 -- ! cmpb 000001,000177 -> n1z0v0c1; (000202+C)
d=000177 -- !
d=000010 -- ! cmpb 000377,000177 -> n1z0v0c0; (000200)
d=000177 -- !
d=000013 -- ! cmpb 000177,000200 -> n1z0v1c1; (000377+C)
d=000200 -- !
d=000004 -- ! cmpb 000200,000200 -> n0z1v0c0; (000000)
d=000200 -- !
d=000000 -- ! cmpb 000201,000200 -> n0z0v0c0; (000001)
d=000200 -- !
d=000013 -- ! cmpb 000001,000200 -> n1z0v1c1; (000201+C)
d=000200 -- !
d=000000 -- ! cmpb 000377,000200 -> n0z0v0c0; (000177)
d=000200 -- !
d=000001 -- ! cmpb 000000,000377 -> n0z0v0c1; (000001+C)
d=000377 -- !
d=000001 -- ! cmpb 000001,000377 -> n0z0v0c1; (000002+C)
d=000377 -- !
d=000004 -- ! cmpb 000377,000377 -> n0z1v0c0; (000000)
d=000377 -- !
#-----------------------------------------------------------------------------
C Setup code 47 [base 13400] (pipeline torture tests)
#
wal 013400 -- data:
wmi 000077 -- marker
wal 013402 -- code 1:
bwm 13
016727 -- mov -6(pc),(pc)+ ;
177772
000000 -- halt ; will be overwritten
016737 -- mov -10(pc),@(pc)+ ;
177770
013400
005200 -- inc r0 ;
#13420
010317 -- mov r3,(pc) ; will overwrite next instruction
000000 -- halt ; will be overwritten
005200 -- inc r0 ;
010447 -- mov r4,-(pc) ; will overwrite itself
005200 -- inc r0 ;
000000 -- halt ;
#
wal 013440 -- code 2: (pipeline tester adapted from KDJ11A.MAC)
bwm 15
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop
000240 -- nop
000111 -- jmp (r1)
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop
000240 -- nop
000111 -- jmp (r1)
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop
000240 -- nop
#13460
000111 -- jmp (r1)
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop
000240 -- nop
000111 -- jmp (r1)
000000 -- halt ; should halt here !
000000 -- halt ;
000000 -- halt ; should not jmp here !
#
C Exec code 47 (pipeline torture tests)
C Exec test 47.1 (some self-modifying code, use (pc)+, (pc), -(pc)):
#
wr0 000000 -- r0=0
wr1 000000 -- r1=0
wr2 000000 -- r2=0
wr3 005201 -- r3= inc r1
wr4 005202 -- r4= inc r2
stapc 013402 -- start @ 13402
wtgo
rpc d=013434 -- ! pc
rr0 d=000003 -- ! r0
rr1 d=000001 -- ! r1
rr2 d=000001 -- ! r2
rr3 d=005201 -- ! r3
rr4 d=005202 -- ! r4
#
wal 013400 -- check data area:
rmi d=177772 -- ! new marker ; written by mov -10(pc),@(pc)+
wal 013402 -- check code area:
brm 13
d=016727 -- ! mov -6(pc),(pc)+ ;
d=177772 -- !
d=000077 -- ! ; written by mov -6(pc),(pc)+
d=016737 -- ! mov -10(pc),@(pc)+;
d=177770 -- !
d=013400 -- !
d=005200 -- ! inc r0 ;
#13320
d=010317 -- ! mov r3,(pc) ;
d=005201 -- ! inc r1 ; written by mov r3,(pc); executed
d=005200 -- ! inc r0 ;
d=005202 -- ! inc r2 ; written by mov r4,-(pc); executed
d=005200 -- ! inc r0 ;
d=000000 -- ! halt ;
#
C Exec test 47.1 (pipeline tester adapted from KDJ11A.MAC, test 121, p. 70)
#
wr1 013474 -- r1=13474 (alternate halt)
stapc 013440 -- start @ 13440
wtgo
rpc d=013472 -- ! pc
wal 013440 -- check code area:
brm 13
d=012717 -- ! mov (pc)+,(pc) ;
d=000240 -- ! nop
d=000240 -- ! nop ; written; executed
d=012717 -- ! mov (pc)+,(pc) ;
d=000240 -- ! nop
d=000240 -- ! nop ; written; executed
d=012717 -- ! mov (pc)+,(pc) ;
d=000240 -- ! nop
#13360
d=000240 -- ! nop ; written; executed
d=012717 -- ! mov (pc)+,(pc) ;
d=000240 -- ! nop
d=000240 -- ! nop ; written; executed
d=000000 -- ! halt ;
#-----------------------------------------------------------------------------
C Setup code 50 [base 13500] (check that all reserved instructions trap to 10)
#
wal 013500 -- code (to be single stepped...)
bwm 17
000007 -- 000007
000010 -- 000010-000077
000077 --
000210 -- 000210-000227
000227 --
007000 -- 007000-007777
007777 --
075000 -- 075000-076777
#13420
076777 --
106400 -- 106400-106477
106477 --
106700 -- 106700-106777
106777 --
107000 -- 107000-107777
107777 --
170000 -- 170000-177777 (no FPU)
#13440
177777 --
#
C Exec code 50 (check that all reserved instructions trap to 10)
C Test odd address abort
#
rst -- console reset
wps 000000 -- clear psw
wal 001374 -- clean stack
bwm 2
000000 --
000000 --
wsp 001400 -- sp=1400
wpc 013500 -- pc=13500
step -- step (000007): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013502 -- pc=13502
step -- step (000010): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013504 -- pc=13504
step -- step (000077): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013506 -- pc=13506
step -- step (000210): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013510 -- pc=13510
step -- step (000227): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013512 -- pc=13512
step -- step (007000): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013514 -- pc=13514
step -- step (007777): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013516 -- pc=13516
step -- step (075000): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013520 -- pc=13520
step -- step (076777): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013522 -- pc=13522
step -- step (106400): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013524 -- pc=13524
step -- step (106477): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013526 -- pc=13526
step -- step (106700): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013530 -- pc=13530
step -- step (106777): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013532 -- pc=13532
step -- step (107000): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013534 -- pc=13534
step -- step (107777): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013536 -- pc=13536
step -- step (170000): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013540 -- pc=13540
step -- step (177777): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#-----------------------------------------------------------------------------
#
C Verify trap catchers integrity
#
wal 000004 -- vectors: 4...34 (trap catcher)
brm 14
d=000006 -- ! PC:06 ; vector 4
d=000000 -- ! PS:0
d=000012 -- ! PC:12 ; vector 10
d=000000 -- ! PS:0
d=000016 -- ! PC:16 ; vector 14 (T bit; BPT)
d=000000 -- ! PS:0
d=000022 -- ! PC:22 ; vector 20 (IOT)
d=000000 -- ! PS:0
d=000026 -- ! PC:26 ; vector 24 (Power fail, not used)
d=000000 -- ! PS:0
d=000032 -- ! PC:32 ; vector 30 (EMT)
d=000000 -- ! PS:0
d=000036 -- ! PC:36 ; vector 34 (TRAP)
d=000000 -- ! PS:0
wal 000240 -- vectors: 240,244,250 (trap catcher)
brm 6
d=000242 -- ! PC:242 ; vector 240 (PIRQ)
d=000000 -- ! PS:0
d=000246 -- ! PC:246 ; vector 244 (FPU)
d=000000 -- ! PS:0
d=000252 -- ! PC:252 ; vector 250 (MMU)
d=000000 -- ! PS:0
#
C Verify setup MMU
# to avoid seeing AIB bits:
# 1. check ARs; 2. re-write ARs to clear AIBs in DRs; 3. check DRs
#
wal 172340 -- kernel I space AR
brm 8
d=000000 -- ! 0
d=000200 -- ! 200 020000 base
d=000400 -- ! 400 040000 base
d=000600 -- ! 600 060000 base
d=001000 -- ! 1000 100000 base
d=001200 -- ! 1200 120000 base
d=001400 -- ! 1400 140000 base
d=177600 -- !176000 (map to I/O page)
#
wal 172340 -- kernel I space AR
bwm 8
000000 -- 0
000200 -- 200 020000 base
000400 -- 400 040000 base
000600 -- 600 060000 base
001000 -- 1000 100000 base
001200 -- 1200 120000 base
001400 -- 1400 140000 base
177600 -- 176000 (map to I/O page)
#
wal 172300 -- kernel I space DR
brm 8
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
#
wal 000000 -- last cmd shouldn't be 21 or 23 ...
/rtl/w11a/tb/tbd_pdp11core.vhd
0,0 → 1,224
-- $Id: tbd_pdp11core.vhd 351 2010-12-30 21:50:54Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_pdp11core - syn
-- Description: Wrapper for pdp11_core to avoid records. It has a port
-- interface which will not be modified by xst synthesis
-- (no records, no generic port).
--
-- Dependencies: genlib/clkdivce
-- pdp11_core
-- pdp11_bram
-- ibus/ibdr_minisys
-- pdp11_tmu_sb [sim only]
--
-- To test: pdp11_core
--
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-06-13 305 11.4 L68 xc3s1000-4 601 2504 206 1428 s 18.6
-- 2008-03-01 120 8.2.03 I34 xc3s1000-4 679 2562 206 1465 s 18.5
-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 605 2324 164 1297 s 18.7
-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 536 2119 119 1184 s 19.3
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 INTERNAL_ERROR -> blog_webpack
-- 2007-10-27 92 9.1 J30 xc3s1000-4 503 2021 119 - t 18.7
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 534 2091 119 1170 s 19.3
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 557 2186 119 - s 18.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-30 351 1.5 rename tbd_pdp11_core -> tbd_pdp11core
-- 2010-10-23 335 1.4.2 rename RRI_LAM->RB_LAM;
-- 2010-06-20 307 1.4.1 add CP_ADDR_racc, CP_ADDR_be port
-- 2010-06-13 305 1.4 add CP_ADDR_... in ports; add CP_CNTL_rnum in port
-- 2010-06-11 303 1.3.9 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.3.8 adapt to ibdr_minisys interface changes
-- 2009-05-10 214 1.3.7 use pdp11_tmu_sb instead of pdp11_tmu
-- 2008-08-22 161 1.3.6 use iblib, ibdlib
-- 2008-05-03 143 1.3.5 rename _cpursta->_cpurust
-- 2008-04-27 140 1.3.4 use cpursta interface, remove cpufail
-- 2008-04-19 137 1.3.3 add DM_STAT_(DP|VM|CO|SY) signals, add pdp11_tmu
-- 2008-04-18 136 1.3.2 add RESET for ibdr_minisys
-- 2008-02-23 118 1.3.1 use sys_conf for bram size
-- 2008-02-17 117 1.3 adapt to em_ core interface; use pdp11_bram
-- 2008-01-20 112 1.2.1 rename clkgen->clkdivce; use ibdr_minisys, BRESET;
-- 2008-01-06 111 1.2 add some external devices: KW11L, DL11, RK11
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port
-- 2007-09-23 85 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
use work.genlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
 
entity tbd_pdp11core is -- full core [no records]
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CP_CNTL_req : in slbit; -- console control port
CP_CNTL_func : in slv5; -- console control port
CP_CNTL_rnum : in slv3; -- console control port
CP_ADDR_addr : in slv22_1; -- console address port
CP_ADDR_racc : in slbit; -- console address port
CP_ADDR_be : in slv2; -- console address port
CP_ADDR_ena_22bit : in slbit; -- console address port
CP_ADDR_ena_ubmap : in slbit; -- console address port
CP_DIN : in slv16; -- console data in
CP_STAT_cmdbusy : out slbit; -- console status port
CP_STAT_cmdack : out slbit; -- console status port
CP_STAT_cmderr : out slbit; -- console status port
CP_STAT_cmdmerr : out slbit; -- console status port
CP_STAT_cpugo : out slbit; -- console status port
CP_STAT_cpuhalt : out slbit; -- console status port
CP_STAT_cpustep : out slbit; -- console status port
CP_STAT_cpurust : out slv4; -- console status port
CP_DOUT : out slv16 -- console data out
);
end tbd_pdp11core;
 
 
architecture syn of tbd_pdp11core is
signal CE_USEC : slbit := '0';
 
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
 
signal CP_CNTL : cp_cntl_type := cp_cntl_init;
signal CP_ADDR : cp_addr_type := cp_addr_init;
signal CP_STAT : cp_stat_type := cp_stat_init;
 
signal EM_MREQ : em_mreq_type := em_mreq_init;
signal EM_SRES : em_sres_type := em_sres_init;
signal BRESET : slbit := '0';
signal IB_MREQ_M : ib_mreq_type := ib_mreq_init;
signal IB_SRES_M : ib_sres_type := ib_sres_init;
 
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;
 
begin
 
CP_CNTL.req <= CP_CNTL_req;
CP_CNTL.func <= CP_CNTL_func;
CP_CNTL.rnum <= CP_CNTL_rnum;
 
CP_ADDR.addr <= CP_ADDR_addr;
CP_ADDR.racc <= CP_ADDR_racc;
CP_ADDR.be <= CP_ADDR_be;
CP_ADDR.ena_22bit <= CP_ADDR_ena_22bit;
CP_ADDR.ena_ubmap <= CP_ADDR_ena_ubmap;
 
CP_STAT_cmdbusy <= CP_STAT.cmdbusy;
CP_STAT_cmdack <= CP_STAT.cmdack;
CP_STAT_cmderr <= CP_STAT.cmderr;
CP_STAT_cmdmerr <= CP_STAT.cmdmerr;
CP_STAT_cpugo <= CP_STAT.cpugo;
CP_STAT_cpuhalt <= CP_STAT.cpuhalt;
CP_STAT_cpustep <= CP_STAT.cpustep;
CP_STAT_cpurust <= CP_STAT.cpurust;
 
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => open
);
 
PDP11 : pdp11_core
port map (
CLK => CLK,
RESET => RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
BRESET => BRESET,
IB_MREQ_M => IB_MREQ_M,
IB_SRES_M => IB_SRES_M,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO
);
MEM : pdp11_bram
generic map (
AWIDTH => sys_conf_bram_awidth)
port map (
CLK => CLK,
GRESET => RESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES
);
IBDR_SYS : ibdr_minisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_USEC, -- !! in test benches msec = usec !!
RESET => RESET,
BRESET => BRESET,
RB_LAM => open,
IB_MREQ => IB_MREQ_M,
IB_SRES => IB_SRES_M,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => open
);
 
-- synthesis translate_off
 
DM_STAT_SY.emmreq <= EM_MREQ;
DM_STAT_SY.emsres <= EM_SRES;
DM_STAT_SY.chit <= '0';
TMU : pdp11_tmu_sb
generic map (
ENAPIN => 13)
port map (
CLK => CLK,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
DM_STAT_SY => DM_STAT_SY
);
-- synthesis translate_on
end syn;
/rtl/w11a/tb/tbd_pdp11core.vbom
0,0 → 1,15
# libs
../../vlib/slvtypes.vhd
../../vlib/genlib/genlib.vhd
../../ibus/iblib.vhd
../../ibus/ibdlib.vhd
../pdp11.vbom
sys_conf : ../sys_conf.vhd
# components
../../vlib/genlib/clkdivce.vbom
../pdp11_core.vbom
../pdp11_bram.vbom
../../ibus/ibdr_minisys.vbom
[ghdl,isim]../pdp11_tmu_sb.vbom
# design
tbd_pdp11core.vhd
/rtl/w11a/tb/.cvsignore
1,22 → 1,12
tb_pdp11_core
tb_pdp11_core_stim
tb_pdp11_core_[sft]sim
tb_pdp11_core_ISim
tb_pdp11_core_ISim_[sft]sim
tb_rritba_pdp11core
tb_rritba_pdp11core_[sft]sim
tb_rritba_pdp11core_ISim
tb_rritba_pdp11core_ISim_[sft]sim
tb_rritba_stim
tb_rripdp_pdp11core
tb_rripdp_pdp11core_[sft]sim
tb_rripdp_pdp11core_ISim
tb_rripdp_pdp11core_ISim_[sft]sim
tb_rripdp_stim
tb_rriext_pdp11core
tb_rriext_pdp11core_[sft]sim
tb_rriext_fifo_rx
tb_rriext_fifo_tx
tb_rriext_conf
tb_pdp11_core_stim.scmd
tb_pdp11core
tb_pdp11core_stim
tb_pdp11core_[sft]sim
tb_pdp11core_ISim
tb_pdp11core_ISim_[sft]sim
tb_rlink_tba_pdp11core
tb_rlink_tba_pdp11core_[sft]sim
tb_rlink_tba_pdp11core_ISim
tb_rlink_tba_pdp11core_ISim_[sft]sim
tb_rlink_tba_stim
tb_pdp11core_stim.scmd
tmu_ofile
/rtl/w11a/tb/Makefile
1,14 → 1,14
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 351 2010-12-30 21:50:54Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2010-12-30 351 1.3 retire tb_rripdp_pdp11core tb_rriext_pdp11core
# 2009-11-22 252 1.2 add ISim support
# 2007-09-16 83 1.1.1 add include *.o.dep_ghdl
# 2007-07-06 64 1.1 use vbom's
# 2007-06-17 58 1.0 Initial version
#
EXE_all = tb_pdp11_core tb_rritba_pdp11core tb_rripdp_pdp11core \
tb_rriext_pdp11core
EXE_all = tb_pdp11core tb_rlink_tba_pdp11core
#
#
.phony : all all_ssim all_tsim clean
40,18 → 40,18
simdat_check $*.simh_raw_log > $*.simh_log
grep FAIL $*.simh_log
 
check_dsim: tb_pdp11_core tb_pdp11_core_stim.dat
time tbw tb_pdp11_core |\
tee tb_pdp11_core_dsim.log |\
check_dsim: tb_pdp11core tb_pdp11core_stim.dat
time tbw tb_pdp11core |\
tee tb_pdp11core_dsim.log |\
egrep "(FAIL|DONE)" || true
@ echo "# diff to reference"
diff tb_pdp11_core_out_ref.dat tb_pdp11_core_dsim.log
diff tb_pdp11core_out_ref.dat tb_pdp11core_dsim.log
 
check_ssim: tb_pdp11_core_ssim tb_pdp11_core_stim.dat
time tbw tb_pdp11_core_ssim |\
tee tb_pdp11_core_ssim.log |\
check_ssim: tb_pdp11core_ssim tb_pdp11core_stim.dat
time tbw tb_pdp11core_ssim |\
tee tb_pdp11core_ssim.log |\
egrep "(FAIL|DONE)" || true
@ echo "# diff to reference"
diff tb_pdp11_core_out_ref.dat tb_pdp11_core_ssim.log
diff tb_pdp11core_out_ref.dat tb_pdp11core_ssim.log
 
check_simh: tb_pdp11_core_stim.simh_log
check_simh: tb_pdp11core_stim.simh_log
/rtl/w11a/tb
rtl/w11a/tb Property changes : Modified: svn:ignore ## -30,25 +30,15 ## *_svn.log *_sum.log *_[dsft]sim.log -tb_pdp11_core -tb_pdp11_core_stim -tb_pdp11_core_[sft]sim -tb_pdp11_core_ISim -tb_pdp11_core_ISim_[sft]sim -tb_rritba_pdp11core -tb_rritba_pdp11core_[sft]sim -tb_rritba_pdp11core_ISim -tb_rritba_pdp11core_ISim_[sft]sim -tb_rritba_stim -tb_rripdp_pdp11core -tb_rripdp_pdp11core_[sft]sim -tb_rripdp_pdp11core_ISim -tb_rripdp_pdp11core_ISim_[sft]sim -tb_rripdp_stim -tb_rriext_pdp11core -tb_rriext_pdp11core_[sft]sim -tb_rriext_fifo_rx -tb_rriext_fifo_tx -tb_rriext_conf -tb_pdp11_core_stim.scmd +tb_pdp11core +tb_pdp11core_stim +tb_pdp11core_[sft]sim +tb_pdp11core_ISim +tb_pdp11core_ISim_[sft]sim +tb_rlink_tba_pdp11core +tb_rlink_tba_pdp11core_[sft]sim +tb_rlink_tba_pdp11core_ISim +tb_rlink_tba_pdp11core_ISim_[sft]sim +tb_rlink_tba_stim +tb_pdp11core_stim.scmd tmu_ofile Index: rtl/w11a/pdp11_core_rbus.vhd =================================================================== --- rtl/w11a/pdp11_core_rbus.vhd (nonexistent) +++ rtl/w11a/pdp11_core_rbus.vhd (revision 9) @@ -0,0 +1,417 @@ +-- $Id: pdp11_core_rbus.vhd 352 2011-01-02 13:01:37Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: pdp11_core_rbus - syn +-- Description: pdp11: core to rbus interface +-- +-- Dependencies: - +-- Test bench: tb/tb_rlink_tba_pdp11core +-- +-- Target Devices: generic +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.26 +-- Revision History: - +-- Date Rev Version Comment +-- 2010-12-29 351 1.1 renamed from pdp11_core_rri; ported to rbv3 +-- 2010-10-23 335 1.2.3 rename RRI_LAM->RB_LAM; +-- 2010-06-20 308 1.2.2 use c_ibrb_ibf_ def's +-- 2010-06-18 306 1.2.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS; +-- add ibrb register and ibr window logic +-- 2010-06-13 305 1.2 add CP_ADDR in port; mostly rewritten for new +-- rri <-> cp mapping +-- 2010-06-03 299 1.1.2 correct rbus init logic (use we, din, RB_ADDR) +-- 2010-05-02 287 1.1.1 rename RP_STAT->RB_STAT; remove unneeded unsigned() +-- 2010-05-01 285 1.1 port to rri V2 interface, add RB_ADDR generic; +-- rename c_rp_addr_* -> c_rb_addr_* +-- 2008-05-03 143 1.0.8 rename _cpursta->_cpurust +-- 2008-04-27 140 1.0.7 use cpursta interface, remove cpufail +-- 2008-03-02 121 1.0.6 set RP_ERR when cmderr or cmdmerr status seen +-- 2008-02-24 119 1.0.5 support lah,rps,wps cp commands +-- 2008-01-20 113 1.0.4 use single LAM; change to RRI_LAM interface +-- 2007-10-12 88 1.0.3 avoid ieee.std_logic_unsigned, use cast to unsigned +-- 2007-08-16 74 1.0.2 add AP_LAM interface to pdp11_core_rri +-- 2007-08-12 73 1.0.1 use def's; add stat command; wait for step complete +-- 2007-07-08 65 1.0 Initial version +------------------------------------------------------------------------------ +-- +-- rbus registers: +-- +-- Address Bits Name r/w/i Function +-- +-- bbb00000 conf r/w/- cpu configuration (e.g. cpu type) +-- (currently unused, all bits MBZ) +-- bbb00001 cntl -/f/- cpu control +-- 3:0 func function code +-- 0000: noop +-- 0001: start +-- 0010: stop +-- 0011: continue +-- 0100: step +-- 1111: reset (soft) +-- bbb00010 stat r/-/- cpu status +-- 7:04 cpurust r/-/- cp_stat: cpurust +-- 3 cpuhalt r/-/- cp_stat: cpuhalt +-- 2 cpugo r/-/- cp_stat: cpugo +-- 1 cmdmerr r/-/- cp_stat: cmdmerr +-- 0 cmderr r/-/- cp_stat: cmderr +-- bbb00011 psw r/w/- processor status word access +-- bbb00100 al r/w/- address register, low +-- bbb00101 ah r/w/- address register, high +-- bbb00110 mem r/w/- memory access +-- bbb00111 memi r/w/- memory access, inc address +-- bbb01rrr gpr[] r/w/- general purpose regs +-- bbb10000 ibrb r/w/- ibr base address +-- 12:06 base r/w/- ibr window base address +-- 1:00 we r/w/- byte enables (00 equivalent to 11) +-- www----- ibr[] r/w/- ibr window (32 words) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.slvtypes.all; +use work.rblib.all; +use work.pdp11.all; + +-- ---------------------------------------------------------------------------- + +entity pdp11_core_rbus is -- core to rbus interface + generic ( + RB_ADDR_CORE : slv8 := conv_std_logic_vector(2#00000000#,8); + RB_ADDR_IBUS : slv8 := conv_std_logic_vector(2#10000000#,8)); + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + RB_STAT : out slv3; -- rbus: status flags + RB_LAM : out slbit; -- remote attention + CPU_RESET : out slbit; -- cpu master reset + CP_CNTL : out cp_cntl_type; -- console control port + CP_ADDR : out cp_addr_type; -- console address port + CP_DIN : out slv16; -- console data in + CP_STAT : in cp_stat_type; -- console status port + CP_DOUT : in slv16 -- console data out + ); +end pdp11_core_rbus; + + +architecture syn of pdp11_core_rbus is + + type state_type is ( + s_idle, -- s_idle: wait for rp access + s_cpwait, -- s_cpwait: wait for cp port ack + s_cpstep -- s_cpstep: wait for cpustep done + ); + + type regs_type is record + state : state_type; -- state + rbselc : slbit; -- rbus select for core + rbseli : slbit; -- rbus select for ibus + cpreq : slbit; -- cp request flag + cpfunc : slv5; -- cp function + cpugo_1 : slbit; -- prev cycle cpugo + addr : slv22_1; -- address register + ena_22bit : slbit; -- 22bit enable + ena_ubmap : slbit; -- ubmap enable + ibrbase : slv(c_ibrb_ibf_base); -- ibr base address + ibrbe : slv2; -- ibr byte enables + ibrberet : slv2; -- ibr byte enables (for readback) + doinc : slbit; -- at cmdack: do addr reg inc + waitstep : slbit; -- at cmdack: wait for cpu step complete + end record regs_type; + + constant regs_init : regs_type := ( + s_idle, -- state + '0','0', -- rbselc,rbseli + '0', -- cpreq + (others=>'0'), -- cpfunc + '0', -- cpugo_1 + (others=>'0'), -- addr + '0','0', -- ena_22bit, ena_ubmap + (others=>'0'),"00","00", -- ibrbase, ibrbe, ibrberet + '0','0' -- doinc, waitstep + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + begin + + proc_regs: process (CLK) + begin + + if CLK'event and CLK='1' then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, RB_MREQ, CP_STAT, CP_DOUT) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable irb_ack : slbit := '0'; + variable irb_busy : slbit := '0'; + variable irb_err : slbit := '0'; + variable irb_dout : slv16 := (others=>'0'); + variable irb_lam : slbit := '0'; + variable irbena : slbit := '0'; + + variable icpreq : slbit := '0'; + variable icpureset : slbit := '0'; + variable icpaddr : cp_addr_type := cp_addr_init; + + begin + + r := R_REGS; + n := R_REGS; + + irb_ack := '0'; + irb_busy := '0'; + irb_err := '0'; + irb_dout := (others=>'0'); + irb_lam := '0'; + + irbena := RB_MREQ.re or RB_MREQ.we; + + icpreq := '0'; + icpureset := '0'; + + -- look for init's against the rbus base address, generate subsystem resets + if RB_MREQ.init='1' and RB_MREQ.we='1' and RB_MREQ.addr=RB_ADDR_CORE then + icpureset := RB_MREQ.din(0); + end if; + + -- rbus address decoder + n.rbseli := '0'; + n.rbselc := '0'; + if RB_MREQ.aval='1' then + if RB_MREQ.addr(7 downto 5)=RB_ADDR_CORE(7 downto 5) then + n.rbselc := '1'; + end if; + if RB_MREQ.addr(7 downto 5)=RB_ADDR_IBUS(7 downto 5) then + n.rbseli := '1'; + end if; + end if; + + if (r.rbselc='1' or r.rbseli='1') and irbena='1' then + irb_ack := '1'; -- ack all (maybe rejected later) + end if; + + case r.state is + + when s_idle => -- s_idle: wait for rbus access ------ + + n.doinc := '0'; + n.waitstep := '0'; + + if r.rbseli = '1' then + if irbena = '1' then + n.cpfunc := c_cpfunc_rmem; + n.cpfunc(0) := RB_MREQ.we; + icpreq := '1'; + end if; + + elsif r.rbselc = '1' then + + case RB_MREQ.addr(4 downto 0) is + + when c_rbaddr_conf => -- conf ------------------------- + null; -- currently no action + + when c_rbaddr_cntl => -- cntl ------------------------- + if irbena = '1' then + n.cpfunc := RB_MREQ.din(n.cpfunc'range); + end if; + if RB_MREQ.we = '1' then + icpreq := '1'; + if RB_MREQ.din(3 downto 0) = c_cpfunc_step(3 downto 0) then + n.waitstep := '1'; + end if; + end if; + + when c_rbaddr_stat => -- stat ------------------------- + irb_dout(c_stat_rbf_cmderr) := CP_STAT.cmderr; + irb_dout(c_stat_rbf_cmdmerr) := CP_STAT.cmdmerr; + irb_dout(c_stat_rbf_cpugo) := CP_STAT.cpugo; + irb_dout(c_stat_rbf_cpuhalt) := CP_STAT.cpuhalt; + irb_dout(c_stat_rbf_cpurust) := CP_STAT.cpurust; + + when c_rbaddr_psw => -- psw -------------------------- + if irbena = '1' then + n.cpfunc := c_cpfunc_rpsw; + n.cpfunc(0) := RB_MREQ.we; + icpreq := '1'; + end if; + + when c_rbaddr_al => -- al --------------------------- + irb_dout(c_al_rbf_addr) := r.addr(c_al_rbf_addr); + if RB_MREQ.we = '1' then + n.addr := (others=>'0'); -- write to al clears ah !! + n.ena_22bit := '0'; + n.ena_ubmap := '0'; + n.addr(c_al_rbf_addr) := RB_MREQ.din(c_al_rbf_addr); + end if; + + when c_rbaddr_ah => -- ah --------------------------- + irb_dout(c_ah_rbf_ena_ubmap) := r.ena_ubmap; + irb_dout(c_ah_rbf_ena_22bit) := r.ena_22bit; + irb_dout(c_ah_rbf_addr) := r.addr(21 downto 16); + if RB_MREQ.we = '1' then + n.addr(21 downto 16) := RB_MREQ.din(c_ah_rbf_addr); + n.ena_22bit := RB_MREQ.din(c_ah_rbf_ena_22bit); + n.ena_ubmap := RB_MREQ.din(c_ah_rbf_ena_ubmap); + end if; + + when c_rbaddr_mem => -- mem ----------------- + if irbena = '1' then + n.cpfunc := c_cpfunc_rmem; + n.cpfunc(0) := RB_MREQ.we; + icpreq := '1'; + end if; + + when c_rbaddr_memi => -- memi ---------------- + if irbena = '1' then + n.cpfunc := c_cpfunc_rmem; + n.cpfunc(0) := RB_MREQ.we; + n.doinc := '1'; + icpreq := '1'; + end if; + + when c_rbaddr_r0 | c_rbaddr_r1 | + c_rbaddr_r2 | c_rbaddr_r3 | + c_rbaddr_r4 | c_rbaddr_r5 | + c_rbaddr_sp | c_rbaddr_pc => -- r* ------------------ + if irbena = '1' then + n.cpfunc := c_cpfunc_rreg; + n.cpfunc(0) := RB_MREQ.we; + icpreq := '1'; + end if; + + when c_rbaddr_ibrb => -- ibrb ---------------- + irb_dout(c_ibrb_ibf_base) := r.ibrbase; + irb_dout(c_ibrb_ibf_be) := r.ibrberet; + if RB_MREQ.we = '1' then + n.ibrbase := RB_MREQ.din(c_ibrb_ibf_base); + n.ibrberet := RB_MREQ.din(c_ibrb_ibf_be); + if RB_MREQ.din(c_ibrb_ibf_be) = "00" then -- both be=0 ? + n.ibrbe := "11"; + else -- otherwise take 2 LSB's + n.ibrbe := RB_MREQ.din(c_ibrb_ibf_be); + end if; + end if; + + when others => + irb_ack := '0'; + + end case; + + end if; + + if icpreq = '1' then + irb_busy := '1'; + n.cpreq := '1'; + n.state := s_cpwait; + end if; + + when s_cpwait => -- s_cpwait: wait for cp port ack ---- + n.cpreq := '0'; -- cpreq only for 1 cycle + + if (r.rbselc or r.rbseli)='0' or irbena='0' then -- rbus cycle abort + n.state := s_idle; -- quit + else + irb_dout := CP_DOUT; + irb_err := CP_STAT.cmderr or CP_STAT.cmdmerr; + if CP_STAT.cmdack = '1' then -- normal cycle end + if r.doinc = '1' then + n.addr := unsigned(r.addr) + 1; + end if; + if r.waitstep = '1' then + irb_busy := '1'; + n.state := s_cpstep; + else + n.state := s_idle; + end if; + else + irb_busy := '1'; + end if; + end if; + + when s_cpstep => -- s_cpstep: wait for cpustep done --- + if r.rbselc='0' or irbena='0' then -- rbus cycle abort + n.state := s_idle; -- quit + else + if CP_STAT.cpustep = '0' then -- cpustep done + n.state := s_idle; + else + irb_busy := '1'; + end if; + end if; + + when others => null; + end case; + + icpaddr := cp_addr_init; + icpaddr.addr := r.addr; + icpaddr.racc := '0'; + icpaddr.be := "11"; + icpaddr.ena_22bit := r.ena_22bit; + icpaddr.ena_ubmap := r.ena_ubmap; + + if r.rbseli = '1' and irbena = '1' then + icpaddr.addr(15 downto 13) := "111"; + icpaddr.addr(c_ibrb_ibf_base) := r.ibrbase; + icpaddr.addr(5 downto 1) := RB_MREQ.addr(4 downto 0); + icpaddr.racc := '1'; + icpaddr.be := r.ibrbe; + icpaddr.ena_22bit := '0'; + icpaddr.ena_ubmap := '0'; + end if; + + n.cpugo_1 := CP_STAT.cpugo; -- delay cpugo + if CP_STAT.cpugo='0' and r.cpugo_1='1' then -- cpugo 1 -> 0 transition ? + irb_lam := '1'; + end if; + + N_REGS <= n; + + RB_SRES.ack <= irb_ack; + RB_SRES.err <= irb_err; + RB_SRES.busy <= irb_busy; + RB_SRES.dout <= irb_dout; + + RB_STAT(0) <= CP_STAT.cpugo; + RB_STAT(1) <= CP_STAT.cpuhalt or CP_STAT.cpurust(CP_STAT.cpurust'left); + RB_STAT(2) <= CP_STAT.cmderr or CP_STAT.cmdmerr; + + RB_LAM <= irb_lam; + + CPU_RESET <= icpureset; + + CP_CNTL.req <= r.cpreq; + CP_CNTL.func <= r.cpfunc; + CP_CNTL.rnum <= RB_MREQ.addr(2 downto 0); + + CP_ADDR <= icpaddr; + CP_DIN <= RB_MREQ.din; + + end process proc_next; + +end syn; Index: rtl/w11a/pdp11_core.vhd =================================================================== --- rtl/w11a/pdp11_core.vhd (revision 8) +++ rtl/w11a/pdp11_core.vhd (revision 9) @@ -1,4 +1,4 @@ --- $Id: pdp11_core.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: pdp11_core.vhd 351 2010-12-30 21:50:54Z mueller $ -- -- Copyright 2006-2010 by Walter F.J. Mueller -- @@ -23,13 +23,11 @@ -- pdp11_sys70 -- ibus/ib_sres_or_4 -- --- Test bench: tb/tb_pdp11_core --- tb/tb_rritba_pdp11core --- tb/tb_rripdp_pdp11core --- tb/tb_rriext_pdp11core +-- Test bench: tb/tb_pdp11core +-- tb/tb_rlink_tba_pdp11core -- -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment -- 2010-06-13 305 1.3 add CP_ADDR in port; drop R_CPDIN, R_CPOUT; _vmbox Index: rtl/w11a/pdp11.vhd =================================================================== --- rtl/w11a/pdp11.vhd (revision 8) +++ rtl/w11a/pdp11.vhd (revision 9) @@ -1,4 +1,4 @@ --- $Id: pdp11.vhd 335 2010-10-24 22:24:23Z mueller $ +-- $Id: pdp11.vhd 351 2010-12-30 21:50:54Z mueller $ -- -- Copyright 2006-2010 by Walter F.J. Mueller -- @@ -16,9 +16,10 @@ -- Description: Definitions for pdp11 components -- -- Dependencies: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2010-12-30 351 1.4.7 rename pdp11_core_rri->pdp11_core_rbus; use rblib -- 2010-10-23 335 1.4.6 rename RRI_LAM->RB_LAM; -- 2010-10-16 332 1.4.5 renames of pdp11_du_drv port names -- 2010-09-18 330 1.4.4 rename (adlm)box->(oalm)unit @@ -84,7 +85,7 @@ use work.slvtypes.all; use work.iblib.all; -use work.rrilib.all; +use work.rblib.all; package pdp11 is @@ -1067,7 +1068,7 @@ ); end component; -component pdp11_core_rri is -- core to rri reg port interface +component pdp11_core_rbus is -- core to rbus interface generic ( RB_ADDR_CORE : slv8 := conv_std_logic_vector(2#00000000#,8); RB_ADDR_IBUS : slv8 := conv_std_logic_vector(2#10000000#,8));
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rtl/vlib/rri/tb Property changes : Deleted: svn:ignore ## -1,51 +0,0 ## -*.dep_ghdl -*.dep_isim -*.dep_xst -work-obj93.cf -*.vcd -*.ghw -*.sav -*.tmp -*.exe -ise -xflow.his -*.ngc -*.ncd -*.pcf -*.bit -*.msk -isim -isim.log -isim.wdb -fuse.log -*_[sft]sim.vhd -*_tsim.sdf -*_xst.log -*_tra.log -*_twr.log -*_map.log -*_par.log -*_pad.log -*_bgn.log -*_svn.log -*_sum.log -*_[dsft]sim.log -tb_rri_stim -tb_rri_core -tb_rri_core_[sft]sim -tb_rri_core_ISim -tb_rri_core_ISim_[sft]sim -tb_rri_serport -tb_rri_serport_[sft]sim -tb_rri_serport_ISim -tb_rri_serport_ISim_[sft]sim -tb_rritba_stim -tb_rritba_ttcombo -tb_rritba_ttcombo_[sft]sim -tb_rritba_ttcombo_ISim -tb_rritba_ttcombo_ISim_[sft]sim -tb_rriext_ttcombo -tb_rriext_ttcombo_[sft]sim -tb_rriext_fifo_rx -tb_rriext_fifo_tx -tb_rriext_conf Index: rtl/vlib/rri/rri_core.vbom =================================================================== --- rtl/vlib/rri/rri_core.vbom (revision 8) +++ rtl/vlib/rri/rri_core.vbom (nonexistent) @@ -1,8 +0,0 @@ -# libs -../slvtypes.vhd -../comlib/comlib.vhd -rrilib.vhd -# components -../comlib/crc8.vbom -# design -rri_core.vhd Index: rtl/vlib/rri/rri_serport.vhd =================================================================== --- rtl/vlib/rri/rri_serport.vhd (revision 8) +++ rtl/vlib/rri/rri_serport.vhd (nonexistent) @@ -1,201 +0,0 @@ --- $Id: rri_serport.vhd 314 2010-07-09 17:38:41Z mueller $ --- --- Copyright 2007-2010 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: rri_serport - syn --- Description: rri: serport adapter --- --- Dependencies: serport/serport_uart_rxtx_ab --- comlib/byte2cdata --- comlib/cdata2byte --- memlib/fifo_1c_dram --- --- Test bench: tb/tb_rri_serport --- --- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 --- Revision History: --- Date Rev Version Comment --- 2010-06-06 301 2.3 use NCOMM=4 (new eop,nak commas) --- 2010-06-03 300 2.2.1 use FAWIDTH=5 --- 2010-05-02 287 2.2 drop RTSFLUSH generic --- 2010-04-18 279 2.1 rewrite flow control, drop RTSFBUF generic --- 2010-04-03 274 2.0 flow control interfaces: RTSFLUSH, CTS_N, RTS_N --- 2007-06-24 60 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -use work.slvtypes.all; -use work.genlib.all; -use work.memlib.all; -use work.comlib.all; -use work.serport.all; -use work.rrilib.all; - -entity rri_serport is -- rri serport adapter - generic ( - CPREF : slv4 := "1000"; -- comma prefix - FAWIDTH : positive := 5; -- rx fifo address port width - CDWIDTH : positive := 13; -- clk divider width - CDINIT : natural := 15); -- clk divider initial/reset setting - port ( - CLK : in slbit; -- clock - CE_USEC : in slbit; -- 1 usec clock enable - CE_MSEC : in slbit; -- 1 msec clock enable - RESET : in slbit; -- reset - RXSD : in slbit; -- receive serial data (board view) - TXSD : out slbit; -- transmit serial data (board view) - CTS_N : in slbit := '0'; -- clear to send (act.low, board view) - RTS_N : out slbit; -- request to send (act.low, board view) - CP_DI : out slv9; -- comm port: data in - CP_ENA : out slbit; -- comm port: data enable - CP_BUSY : in slbit; -- comm port: data busy - CP_DO : in slv9; -- comm port: data out - CP_VAL : in slbit; -- comm port: data valid - CP_HOLD : out slbit; -- comm port: data hold - CP_FLUSH : in slbit := '0' -- comm port: data flush - ); -end rri_serport; - - -architecture syn of rri_serport is - - signal LRESET : slbit := '0'; - signal RXDATA : slv8 := (others=>'0'); - signal RXVAL : slbit := '0'; - signal TXDATA : slv8 := (others=>'0'); - signal TXENA : slbit := '0'; - signal TXBUSY : slbit := '0'; - signal ABACT : slbit := '0'; - signal FIFO_DI : slv9 := (others=>'0'); - signal FIFO_ENA : slbit := '0'; - signal FIFO_BUSY : slbit := '0'; - signal FIFO_SIZE : slv(FAWIDTH downto 0) := (others=>'0'); - signal CD2B_HOLD : slbit := '0'; - - signal R_FIFOBLOCK : slbit := '0'; -- fifo block flag - signal FLUSH_PULSE : slbit := '0'; -- rri flush as 2-3 usec pulse - - constant NCOMM : positive := 4; - -begin - - UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo - generic map ( - CDWIDTH => CDWIDTH, - CDINIT => CDINIT) - port map ( - CLK => CLK, - CE_MSEC => CE_MSEC, - RESET => RESET, - RXSD => RXSD, - RXDATA => RXDATA, - RXVAL => RXVAL, - RXERR => open, - RXACT => open, - TXSD => TXSD, - TXDATA => TXDATA, - TXENA => TXENA, - TXBUSY => TXBUSY, - ABACT => ABACT, - ABDONE => open - ); - - LRESET <= RESET or ABACT; - - B2CD : byte2cdata -- byte stream -> 9bit comma,data - generic map ( - CPREF => CPREF, - NCOMM => NCOMM) - port map ( - CLK => CLK, - RESET => LRESET, - DI => RXDATA, - ENA => RXVAL, - BUSY => open, - DO => FIFO_DI, - VAL => FIFO_ENA, - HOLD => FIFO_BUSY - ); - - CD2B : cdata2byte -- 9bit comma,data -> byte stream - generic map ( - CPREF => CPREF, - NCOMM => NCOMM) - port map ( - CLK => CLK, - RESET => LRESET, - DI => CP_DO, - ENA => CP_VAL, - BUSY => CP_HOLD, - DO => TXDATA, - VAL => TXENA, - HOLD => CD2B_HOLD - ); - - FIFO : fifo_1c_dram -- fifo, 1 clock, dram based - generic map ( - AWIDTH => FAWIDTH, - DWIDTH => 9) - port map ( - CLK => CLK, - RESET => LRESET, - DI => FIFO_DI, - ENA => FIFO_ENA, - BUSY => FIFO_BUSY, - DO => CP_DI, - VAL => CP_ENA, - HOLD => CP_BUSY, - SIZE => FIFO_SIZE - ); - --- re-write later, use RB_MREQ internal init to set parameters which --- control the flush logic. --- ---DOFLUSH: if RTSFLUSH generate --- --- PGEN : timer --- generic map ( --- TWIDTH => 1, --- RETRIG => true) --- port map ( --- CLK => CLK, --- CE => CE_USEC, --- DELAY => "1", --- START => CP_FLUSH, --- STOP => RESET, --- BUSY => FLUSH_PULSE --- ); ---end generate DOFLUSH; - - proc_fifoblock: process (CLK) - begin - - if CLK'event and CLK='1' then - if unsigned(FIFO_SIZE) >= 3*2**(FAWIDTH-2) then -- more than 3/4 full - R_FIFOBLOCK <= '1'; -- block - elsif unsigned(FIFO_SIZE) < 2**(FAWIDTH-1) then -- less than 1/2 full - R_FIFOBLOCK <= '0'; -- unblock - end if; - end if; - - end process proc_fifoblock; - - RTS_N <= R_FIFOBLOCK or FLUSH_PULSE; - - CD2B_HOLD <= TXBUSY or CTS_N; - -end syn; Index: rtl/vlib/rri/rri_serport.vbom =================================================================== --- rtl/vlib/rri/rri_serport.vbom (revision 8) +++ rtl/vlib/rri/rri_serport.vbom (nonexistent) @@ -1,14 +0,0 @@ -# libs -../slvtypes.vhd -../genlib/genlib.vhd -../memlib/memlib.vhd -../comlib/comlib.vhd -../serport/serport.vhd -rrilib.vhd -# components -../serport/serport_uart_rxtx_ab.vbom -../comlib/byte2cdata.vbom -../comlib/cdata2byte.vbom -../memlib/fifo_1c_dram.vbom -# design -rri_serport.vhd Index: rtl/vlib/rri/Makefile =================================================================== --- rtl/vlib/rri/Makefile (revision 8) +++ rtl/vlib/rri/Makefile (nonexistent) @@ -1,22 +0,0 @@ -# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $ -# -# Revision History: -# Date Rev Version Comment -# 2007-12-09 100 1.0.1 drop ISE_p definition -# 2007-07-06 64 1.0 Initial version -# -VBOM_all = $(wildcard *.vbom) -NGC_all = $(VBOM_all:.vbom=.ngc) -# -.phony : all clean -# -all : $(NGC_all) -# -clean : ise_clean -# -#---- -# -include $(RETROBASE)/rtl/vlib/Makefile.xflow -# -include $(VBOM_all:.vbom=.dep_xst) -# Index: rtl/vlib/rri/rb_sres_or_2.vhd =================================================================== --- rtl/vlib/rri/rb_sres_or_2.vhd (revision 8) +++ rtl/vlib/rri/rb_sres_or_2.vhd (nonexistent) @@ -1,76 +0,0 @@ --- $Id: rb_sres_or_2.vhd 314 2010-07-09 17:38:41Z mueller $ --- --- Copyright 2008-2010 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: rb_sres_or_2 - syn --- Description: rribus result or, 2 input --- --- Dependencies: rritb_sres_or_mon [sim only] --- Test bench: - --- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.29 --- Revision History: --- Date Rev Version Comment --- 2010-06-26 309 1.1 add rritb_sres_or_mon --- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_ --- 2008-01-20 113 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.slvtypes.all; -use work.rrilib.all; --- synthesis translate_off -use work.rritblib.all; --- synthesis translate_on - --- ---------------------------------------------------------------------------- - -entity rb_sres_or_2 is -- rribus result or, 2 input - port ( - RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 - RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2 - RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output - ); -end rb_sres_or_2; - -architecture syn of rb_sres_or_2 is - -begin - - proc_comb : process (RB_SRES_1, RB_SRES_2) - begin - - RB_SRES_OR.ack <= RB_SRES_1.ack or - RB_SRES_2.ack; - RB_SRES_OR.busy <= RB_SRES_1.busy or - RB_SRES_2.busy; - RB_SRES_OR.err <= RB_SRES_1.err or - RB_SRES_2.err; - RB_SRES_OR.dout <= RB_SRES_1.dout or - RB_SRES_2.dout; - - end process proc_comb; - --- synthesis translate_off - ORMON : rritb_sres_or_mon - port map ( - RB_SRES_1 => RB_SRES_1, - RB_SRES_2 => RB_SRES_2, - RB_SRES_3 => rb_sres_init, - RB_SRES_4 => rb_sres_init - ); --- synthesis translate_on - -end syn; Index: rtl/vlib/rri/rb_sres_or_3.vhd =================================================================== --- rtl/vlib/rri/rb_sres_or_3.vhd (revision 8) +++ rtl/vlib/rri/rb_sres_or_3.vhd (nonexistent) @@ -1,81 +0,0 @@ --- $Id: rb_sres_or_3.vhd 314 2010-07-09 17:38:41Z mueller $ --- --- Copyright 2008-2010 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: rb_sres_or_3 - syn --- Description: rribus result or, 3 input --- --- Dependencies: rritb_sres_or_mon [sim only] --- Test bench: - --- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.29 --- Revision History: --- Date Rev Version Comment --- 2010-06-26 309 1.1 add rritb_sres_or_mon --- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_ --- 2008-01-20 113 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.slvtypes.all; -use work.rrilib.all; --- synthesis translate_off -use work.rritblib.all; --- synthesis translate_on - --- ---------------------------------------------------------------------------- - -entity rb_sres_or_3 is -- rribus result or, 3 input - port ( - RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 - RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2 - RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 - RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output - ); -end rb_sres_or_3; - -architecture syn of rb_sres_or_3 is - -begin - - proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3) - begin - - RB_SRES_OR.ack <= RB_SRES_1.ack or - RB_SRES_2.ack or - RB_SRES_3.ack; - RB_SRES_OR.busy <= RB_SRES_1.busy or - RB_SRES_2.busy or - RB_SRES_3.busy; - RB_SRES_OR.err <= RB_SRES_1.err or - RB_SRES_2.err or - RB_SRES_3.err; - RB_SRES_OR.dout <= RB_SRES_1.dout or - RB_SRES_2.dout or - RB_SRES_3.dout; - - end process proc_comb; - --- synthesis translate_off - ORMON : rritb_sres_or_mon - port map ( - RB_SRES_1 => RB_SRES_1, - RB_SRES_2 => RB_SRES_2, - RB_SRES_3 => RB_SRES_3, - RB_SRES_4 => rb_sres_init - ); --- synthesis translate_on - -end syn; Index: rtl/vlib/rri/rb_sres_or_2.vbom =================================================================== --- rtl/vlib/rri/rb_sres_or_2.vbom (revision 8) +++ rtl/vlib/rri/rb_sres_or_2.vbom (nonexistent) @@ -1,8 +0,0 @@ -# libs -../slvtypes.vhd -rrilib.vhd -[ghdl,isim]tb/rritblib.vhd -# components -[ghdl,isim]tb/rritb_sres_or_mon.vbom -# design -rb_sres_or_2.vhd Index: rtl/vlib/rri/rri_core_serport.vhd =================================================================== --- rtl/vlib/rri/rri_core_serport.vhd (revision 8) +++ rtl/vlib/rri/rri_core_serport.vhd (nonexistent) @@ -1,170 +0,0 @@ --- $Id: rri_core_serport.vhd 314 2010-07-09 17:38:41Z mueller $ --- --- Copyright 2010- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: rri_core_serport - syn --- Description: rri: core + serport combo, with cpmon and rbmon --- --- Dependencies: rri_serport --- rri_core --- rritb_cpmon_sb [sim only] --- rritb_rbmon_sb [sim only] --- --- Test bench: - --- --- Target Devices: generic --- Tool versions: xst 11.4; ghdl 0.26 --- --- Synthesized (xst): --- Date Rev ise Target flop lutl lutm slic t peri --- 2010-04-03 275 11.4 L68 xc3s1000-4 280 600 18 375 s 9.8 --- --- Revision History: --- Date Rev Version Comment --- 2010-06-05 301 1.2.2 renamed _rpmon -> _rbmon --- 2010-06-03 300 1.2.1 use FAWIDTH=5 --- 2010-05-02 287 1.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM --- drop RP_IINT from interfaces; drop RTSFLUSH generic --- 2010-04-18 279 1.1 drop RTSFBUF generic --- 2010-04-10 275 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -use work.slvtypes.all; -use work.rrilib.all; --- synthesis translate_off -use work.rritblib.all; --- synthesis translate_on - -entity rri_core_serport is -- rri, core+serport with cpmon+rbmon - generic ( - ATOWIDTH : positive := 5; -- access timeout counter width - ITOWIDTH : positive := 6; -- idle timeout counter width - FAWIDTH : positive := 5; -- rx fifo address port width - CDWIDTH : positive := 13; -- clk divider width - CDINIT : natural := 15); -- clk divider initial/reset setting - port ( - CLK : in slbit; -- clock - CE_USEC : in slbit; -- 1 usec clock enable - CE_MSEC : in slbit; -- 1 msec clock enable - CE_INT : in slbit := '0'; -- rri ito time unit clock enable - RESET : in slbit; -- reset - RXSD : in slbit; -- receive serial data (board view) - TXSD : out slbit; -- transmit serial data (board view) - CTS_N : in slbit := '0'; -- clear to send (act.low, board view) - RTS_N : out slbit; -- request to send (act.low, board view) - RB_MREQ : out rb_mreq_type; -- rbus: request - RB_SRES : in rb_sres_type; -- rbus: response - RB_LAM : in slv16; -- rbus: look at me - RB_STAT : in slv3 -- rbus: status flags - ); -end entity rri_core_serport; - - -architecture syn of rri_core_serport is - - signal CP_DI : slv9 := (others=>'0'); - signal CP_ENA : slbit := '0'; - signal CP_BUSY : slbit := '0'; - signal CP_DO : slv9 := (others=>'0'); - signal CP_VAL : slbit := '0'; - signal CP_HOLD : slbit := '0'; - signal CP_FLUSH : slbit := '0'; - - signal RB_MREQ_L : rb_mreq_type := rb_mreq_init; -- local, readable RB_MREQ - -begin - - SER2RRI : rri_serport - generic map ( - CPREF => "1000", - FAWIDTH => FAWIDTH, - CDWIDTH => CDWIDTH, - CDINIT => CDINIT) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC, - RESET => RESET, - RXSD => RXSD, - TXSD => TXSD, - CTS_N => CTS_N, - RTS_N => RTS_N, - CP_DI => CP_DI, - CP_ENA => CP_ENA, - CP_BUSY => CP_BUSY, - CP_DO => CP_DO, - CP_VAL => CP_VAL, - CP_HOLD => CP_HOLD, - CP_FLUSH => CP_FLUSH - ); - - RRI : rri_core - generic map ( - ATOWIDTH => ATOWIDTH, - ITOWIDTH => ITOWIDTH) - port map ( - CLK => CLK, - CE_INT => CE_INT, - RESET => RESET, - CP_DI => CP_DI, - CP_ENA => CP_ENA, - CP_BUSY => CP_BUSY, - CP_DO => CP_DO, - CP_VAL => CP_VAL, - CP_HOLD => CP_HOLD, - CP_FLUSH => CP_FLUSH, - RB_MREQ => RB_MREQ_L, - RB_SRES => RB_SRES, - RB_LAM => RB_LAM, - RB_STAT => RB_STAT - ); - - -- vhdl'93 unfortunately doesn't allow to read a signal bound to an out port - -- because RB_MREQ is read by the monitors, an extra internal - -- signal must be used. This will not be needed with vhdl'2000 anymore - - RB_MREQ <= RB_MREQ_L; - --- synthesis translate_off - CPMON : rritb_cpmon_sb - generic map ( - DWIDTH => CP_DI'length, - ENAPIN => 15) - port map ( - CLK => CLK, - CP_DI => CP_DI, - CP_ENA => CP_ENA, - CP_BUSY => CP_BUSY, - CP_DO => CP_DO, - CP_VAL => CP_VAL, - CP_HOLD => CP_HOLD - ); - - RBMON : rritb_rbmon_sb - generic map ( - DBASE => 8, - ENAPIN => 14) - port map ( - CLK => CLK, - RB_MREQ => RB_MREQ_L, - RB_SRES => RB_SRES, - RB_LAM => RB_LAM, - RB_STAT => RB_STAT - ); --- synthesis translate_on - -end syn; Index: rtl/vlib/rri/rrilib.vhd =================================================================== --- rtl/vlib/rri/rrilib.vhd (revision 8) +++ rtl/vlib/rri/rrilib.vhd (nonexistent) @@ -1,259 +0,0 @@ --- $Id: rrilib.vhd 314 2010-07-09 17:38:41Z mueller $ --- --- Copyright 2007-2010 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Package Name: rrilib --- Description: Remote Register Interface components --- --- Dependencies: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 --- Revision History: --- Date Rev Version Comment --- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_ --- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining --- 2010-06-03 300 2.1.5 use FAWIDTH=5 for rri_serport --- 2010-05-02 287 2.1.4 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM --- drop RP_IINT from interfaces; drop RTSFLUSH generic --- 2010-05-01 285 2.1.3 remove rri_rb_rpcompat, now obsolete --- 2010-04-18 279 2.1.2 rri_core_serport: drop RTSFBUF generic --- 2010-04-10 275 2.1.1 add rri_core_serport --- 2010-04-03 274 2.1 add CP_FLUSH for rri_core, rri_serport; --- CE_USEC, RTSFLUSH, CTS_N, RTS_N for rri_serport --- 2008-08-24 162 2.0 all with new rb_mreq/rb_sres interface --- 2008-08-22 161 1.3 renamed rri_rbres_ -> rb_sres_; drop rri_[24]rp --- 2008-02-16 116 1.2.1 added rri_wreg(rw|w|r)_3 --- 2008-01-20 113 1.2 added rb_[mreq|sres]; _rbres_or_*; _rb_rpcompat --- 2007-11-24 98 1.1 added RP_IINT for rri_core. --- 2007-09-09 81 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.slvtypes.all; - -package rrilib is - -constant c_rri_dat_idle : slv9 := "100000000"; -constant c_rri_dat_sop : slv9 := "100000001"; -constant c_rri_dat_eop : slv9 := "100000010"; -constant c_rri_dat_nak : slv9 := "100000011"; -constant c_rri_dat_attn : slv9 := "100000100"; - -constant c_rri_cmd_rreg : slv3 := "000"; -constant c_rri_cmd_rblk : slv3 := "001"; -constant c_rri_cmd_wreg : slv3 := "010"; -constant c_rri_cmd_wblk : slv3 := "011"; -constant c_rri_cmd_stat : slv3 := "100"; -constant c_rri_cmd_attn : slv3 := "101"; -constant c_rri_cmd_init : slv3 := "110"; - -constant c_rri_iint_rbf_anena: integer := 15; -- anena flag -constant c_rri_iint_rbf_itoena: integer := 14; -- itoena flag -subtype c_rri_iint_rbf_itoval is integer range 7 downto 0; -- command code - -subtype c_rri_cmd_rbf_seq is integer range 7 downto 3; -- sequence number -subtype c_rri_cmd_rbf_code is integer range 2 downto 0; -- command code - -subtype c_rri_stat_rbf_stat is integer range 7 downto 5; -- ext status bits -constant c_rri_stat_rbf_attn: integer := 4; -- attention flags set -constant c_rri_stat_rbf_ccrc: integer := 3; -- command crc error -constant c_rri_stat_rbf_dcrc: integer := 2; -- data crc error -constant c_rri_stat_rbf_ioto: integer := 1; -- i/o time out -constant c_rri_stat_rbf_ioerr: integer := 0; -- i/o error - -type rb_mreq_type is record -- rribus - master request - req : slbit; -- request - we : slbit; -- write enable - init : slbit; -- init - addr : slv8; -- address - din : slv16; -- data (input to slave) -end record rb_mreq_type; - -constant rb_mreq_init : rb_mreq_type := - ('0','0','0', -- req, we, init - (others=>'0'), -- addr - (others=>'0')); -- din - -type rb_sres_type is record -- rribus - slave response - ack : slbit; -- acknowledge - busy : slbit; -- busy - err : slbit; -- error - dout : slv16; -- data (output from slave) -end record rb_sres_type; - -constant rb_sres_init : rb_sres_type := - ('0','0','0', -- ack, busy, err - (others=>'0')); -- dout - -component rri_core is -- rri, core interface - generic ( - ATOWIDTH : positive := 5; -- access timeout counter width - ITOWIDTH : positive := 6); -- idle timeout counter width - port ( - CLK : in slbit; -- clock - CE_INT : in slbit := '0'; -- rri ito time unit clock enable - RESET : in slbit; -- reset - CP_DI : in slv9; -- comm port: data in - CP_ENA : in slbit; -- comm port: data enable - CP_BUSY : out slbit; -- comm port: data busy - CP_DO : out slv9; -- comm port: data out - CP_VAL : out slbit; -- comm port: data valid - CP_HOLD : in slbit; -- comm port: data hold - CP_FLUSH : out slbit; -- comm port: data flush - RB_MREQ : out rb_mreq_type; -- rbus: request - RB_SRES : in rb_sres_type; -- rbus: response - RB_LAM : in slv16; -- rbus: look at me - RB_STAT : in slv3 -- rbus: status flags - ); -end component; - -component rricp_aif is -- rri comm port, abstract interface - port ( - CLK : in slbit; -- clock - CE_INT : in slbit := '0'; -- rri ito time unit clock enable - RESET : in slbit :='0'; -- reset - CP_DI : in slv9; -- comm port: data in - CP_ENA : in slbit; -- comm port: data enable - CP_BUSY : out slbit; -- comm port: data busy - CP_DO : out slv9; -- comm port: data out - CP_VAL : out slbit; -- comm port: data valid - CP_HOLD : in slbit := '0' -- comm port: data hold - ); -end component; - -component rrirp_aif is -- rri reg port, abstract interface - port ( - CLK : in slbit; -- clock - RESET : in slbit := '0'; -- reset - RB_MREQ : in rb_mreq_type; -- rbus: request - RB_SRES : out rb_sres_type; -- rbus: response - RB_LAM : out slv16; -- rbus: look at me - RB_STAT : out slv3 -- rbus: status flags - ); -end component; - -component rri_serport is -- rri serport adapter - generic ( - CPREF : slv4 := "1000"; -- comma prefix - FAWIDTH : positive := 5; -- rx fifo address port width - CDWIDTH : positive := 13; -- clk divider width - CDINIT : natural := 15); -- clk divider initial/reset setting - port ( - CLK : in slbit; -- clock - CE_USEC : in slbit; -- 1 usec clock enable - CE_MSEC : in slbit; -- 1 msec clock enable - RESET : in slbit; -- reset - RXSD : in slbit; -- receive serial data (board view) - TXSD : out slbit; -- transmit serial data (board view) - CTS_N : in slbit := '0'; -- clear to send (act.low, board view) - RTS_N : out slbit; -- request to send (act.low, board view) - CP_DI : out slv9; -- comm port: data in - CP_ENA : out slbit; -- comm port: data enable - CP_BUSY : in slbit; -- comm port: data busy - CP_DO : in slv9; -- comm port: data out - CP_VAL : in slbit; -- comm port: data valid - CP_HOLD : out slbit; -- comm port: data hold - CP_FLUSH : in slbit := '0' -- comm port: data flush - ); -end component; - -component rri_core_serport is -- rri, core+serport with cpmon+rbmon - generic ( - ATOWIDTH : positive := 5; -- access timeout counter width - ITOWIDTH : positive := 6; -- idle timeout counter width - FAWIDTH : positive := 5; -- rx fifo address port width - CDWIDTH : positive := 13; -- clk divider width - CDINIT : natural := 15); -- clk divider initial/reset setting - port ( - CLK : in slbit; -- clock - CE_USEC : in slbit; -- 1 usec clock enable - CE_MSEC : in slbit; -- 1 msec clock enable - CE_INT : in slbit := '0'; -- rri ito time unit clock enable - RESET : in slbit; -- reset - RXSD : in slbit; -- receive serial data (board view) - TXSD : out slbit; -- transmit serial data (board view) - CTS_N : in slbit := '0'; -- clear to send (act.low, board view) - RTS_N : out slbit; -- request to send (act.low, board view) - RB_MREQ : out rb_mreq_type; -- rbus: request - RB_SRES : in rb_sres_type; -- rbus: response - RB_LAM : in slv16; -- rbus: look at me - RB_STAT : in slv3 -- rbus: status flags - ); -end component; - -component rb_sres_or_2 is -- rribus result or, 2 input - port ( - RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 - RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2 - RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output - ); -end component; -component rb_sres_or_3 is -- rribus result or, 3 input - port ( - RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 - RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2 - RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 - RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output - ); -end component; -component rb_sres_or_4 is -- rribus result or, 4 input - port ( - RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 - RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2 - RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 - RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4 - RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output - ); -end component; - -component rri_wreg_rw_3 is -- rri: wide register r/w 3 bit select - generic ( - DWIDTH : positive := 16); - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - FADDR : slv3; -- field address - SEL : slbit; -- select - DATA : out slv(DWIDTH-1 downto 0); -- data - RB_MREQ : in rb_mreq_type; -- rribus request - RB_SRES : out rb_sres_type -- rribus response - ); -end component; - -component rri_wreg_w_3 is -- rri: wide register w-o 3 bit select - generic ( - DWIDTH : positive := 16); - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - FADDR : slv3; -- field address - SEL : slbit; -- select - DATA : out slv(DWIDTH-1 downto 0); -- data - RB_MREQ : in rb_mreq_type; -- rribus request - RB_SRES : out rb_sres_type -- rribus response - ); -end component; - -component rri_wreg_r_3 is -- rri: wide register r-o 3 bit select - generic ( - DWIDTH : positive := 16); - port ( - FADDR : slv3; -- field address - SEL : slbit; -- select - DATA : in slv(DWIDTH-1 downto 0); -- data - RB_SRES : out rb_sres_type -- rribus response - ); -end component; - -end rrilib; Index: rtl/vlib/rri/rb_sres_or_3.vbom =================================================================== --- rtl/vlib/rri/rb_sres_or_3.vbom (revision 8) +++ rtl/vlib/rri/rb_sres_or_3.vbom (nonexistent) @@ -1,8 +0,0 @@ -# libs -../slvtypes.vhd -rrilib.vhd -[ghdl,isim]tb/rritblib.vhd -# components -[ghdl,isim]tb/rritb_sres_or_mon.vbom -# design -rb_sres_or_3.vhd Index: rtl/vlib/rri/rri_core.vhd =================================================================== --- rtl/vlib/rri/rri_core.vhd (revision 8) +++ rtl/vlib/rri/rri_core.vhd (nonexistent) @@ -1,809 +0,0 @@ --- $Id: rri_core.vhd 314 2010-07-09 17:38:41Z mueller $ --- --- Copyright 2007-2010 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: rri_core - syn --- Description: rri: core interface --- --- Dependencies: comlib/crc8 --- --- Test bench: tb/tb_rri_core --- tb/tb_rritba_ttcombo --- tb/tb_rriext_ttcombo --- --- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 --- --- Synthesized (xst): --- Date Rev ise Target flop lutl lutm slic t peri --- 2010-06-06 302 11.4 L68 xc3s1000-4 151 323 0 197 s 8.9 --- 2010-04-03 274 11.4 L68 xc3s1000-4 148 313 0 190 s 8.0 --- 2009-07-11 232 10.1.03 K39 xc3s1000-4 147 321 0 197 s 8.3 --- --- Revision History: --- Date Rev Version Comment --- 2010-06-20 308 2.6 use rbinit,rbreq,rbwe state flops to drive rb_mreq; --- now nak on reserved cmd 111; use do_comma_abort(); --- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_ --- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining --- 2010-06-03 299 2.1.2 drop unneeded unsigned casts; change init encoding --- 2010-05-02 287 2.1.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM --- drop RP_IINT signal from interfaces --- 2010-04-03 274 2.1 add CP_FLUSH output --- 2009-07-12 233 2.0.1 remove snoopers --- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface --- 2008-03-02 121 1.1.1 comment out snoopers --- 2007-11-24 98 1.1 new internal init handling (addr=11111111) --- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned --- 2007-09-15 82 1.0 Initial version, fully functional --- 2007-06-17 58 0.5 First preliminary version ------------------------------------------------------------------------------- --- --- Overall protocol: --- _idle : expect --- sop -> _txsop (echo sop, , to _txsop, _rxcmd) --- eop -> _txeop (send nak,eop , to _txnak, _txeop, _idle) --- nak -> _txnak (silently ignore nak) --- attn -> _txito (send ito , to _idle) --- data -> _idle (silently ignore data) --- _error: expect --- sop -> _txnak (send nak , to _txnak, _error) --- eop -> _txeop (echo eop , to _txeop, _idle) --- nak -> _txnak (echo nak , to _txnak, _error) --- attn -> _txito (silently ignore attn) --- data -> _idle (silently ignore data) --- _rxcmd: expect --- sop -> _txnak (send nak , to _txnak, _error) --- eop -> _txeop (echo eop , to _txeop, _idle) --- nak -> _txnak (echo nak , to _txnak, _error) --- attn -> _txito (silently ignore attn) --- data -> _idle (decode command) --- _rx...: expect --- sop -> _txnak (send nak , to _txnak, _error) --- eop -> _txnak (send nak,eop , to _txnak, _txeop, _idle) --- nak -> _txnak (echo nak , to _txnak, _error) --- attn -> _txito (silently ignore attn) --- data -> _idle (decode data) --- --- 7 supported commands: --- --- 000 read reg (rreg): --- rx: cmd addr ccrc --- tx: cmd dl dh stat crc --- seq: _rxcmd _rxaddr _rxccrc (_txcmd|_txnak) --- _rreg _txdatl _txdath _txstat _txcrc (_rxcmd|_idle) --- --- 001 read blk (rblk): --- rx: cmd addr cnt ccrc --- tx: cmd cnt dl dh ... stat crc --- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak) _txcnt --- {_rreg _txdatl _txdath _blk}* _txstat _txcrc (_rxcmd|_idle) --- --- 010 write reg (wreg): --- rx: cmd addr dl dh ccrc --- tx: cmd stat crc --- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak) --- seq: _wreg _txstat _txcrc (_rxcmd|_idle) --- --- 011 write blk (wblk): --- rx: cmd addr cnt ccrc dl dh ... dcrc --- tx: cmd stat crc --- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak) --- {_rxdatl _rxdath _wreg _blk}* _rxdcrc _txstat _txcrc (_rxcmd|_idle) --- --- 100 read stat (stat): --- rx: cmd ccrc --- tx: cmd ccmd dl dh stat crc --- seq: _rxcmd _rxccrc (_txcmd|_txnak) --- _txccmd _txdatl _txdath _txstat _txcrc (_rxcmd|_idle) --- --- 101 read attn (attn): --- rx: cmd ccrc --- tx: cmd dl dh stat crc --- seq: _rxcmd _rxccrc (_txcmd|_txnak) --- _attn _txdatl _txdath _txstat _txcrc (_rxcmd|_idle) --- --- 110 write init (init): --- rx: cmd addr dl dh ccrc --- tx: cmd stat crc --- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak) --- seq: _txstat _txcrc (_rxcmd|_idle) --- like wreg, but no rp_we - rp_hold, just a 1 cycle rp_init pulse --- --- 111 is currently not a legal command and causes a nak --- seq: _txnak --- --- The different rbus cycle types are encoded as: --- --- init ack we --- 0 0 0 idle --- 0 0 1 idle --- 0 1 0 read --- 0 1 1 write --- 1 0 0 internal init --- 1 0 1 external init --- 1 1 0 not allowed --- 1 1 1 not allowed --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -use work.slvtypes.all; -use work.comlib.all; -use work.rrilib.all; - -entity rri_core is -- rri, core interface - generic ( - ATOWIDTH : positive := 5; -- access timeout counter width - ITOWIDTH : positive := 6); -- idle timeout counter width - port ( - CLK : in slbit; -- clock - CE_INT : in slbit := '0'; -- rri ito time unit clock enable - RESET : in slbit; -- reset - CP_DI : in slv9; -- comm port: data in - CP_ENA : in slbit; -- comm port: data enable - CP_BUSY : out slbit; -- comm port: data busy - CP_DO : out slv9; -- comm port: data out - CP_VAL : out slbit; -- comm port: data valid - CP_HOLD : in slbit; -- comm port: data hold - CP_FLUSH : out slbit; -- comm port: data flush - RB_MREQ : out rb_mreq_type; -- rbus: request - RB_SRES : in rb_sres_type; -- rbus: response - RB_LAM : in slv16; -- rbus: look at me - RB_STAT : in slv3 -- rbus: status flags - ); -end entity rri_core; - - -architecture syn of rri_core is - - type state_type is ( - s_idle, -- s_idle: wait for sop - s_txito, -- s_txito: send timeout symbol - s_txsop, -- s_txsop: send sop - s_txnak, -- s_txnak: send nak - s_txeop, -- s_txeop: send eop - s_error, -- s_error: wait for eop - s_rxcmd, -- s_rxcmd: wait for cmd - s_rxaddr, -- s_rxaddr: wait for addr - s_rxdatl, -- s_rxdatl: wait for data low - s_rxdath, -- s_rxdath: wait for data high - s_rxcnt, -- s_rxcnt: wait for count - s_rxccrc, -- s_rxccrc: wait for command crc - s_txcmd, -- s_txcmd: send cmd - s_txcnt, -- s_txcnt: send cnt - s_rreg, -- s_rreg: reg or blk read - s_txdatl, -- s_txdatl: send data low - s_txdath, -- s_txdath: send data high - s_wreg, -- s_wreg: reg or blk write - s_blk, -- s_blk: block count handling - s_rxdcrc, -- s_rxdcrc: wait for data crc - s_attn, -- s_attn: handle attention flags - s_txccmd, -- s_txccmd: send last command - s_txstat, -- s_txstat: send status - s_txcrc -- s_txcrc: send crc - ); - - type regs_type is record - state : state_type; -- state - rcmd : slv8; -- received command - ccmd : slv8; -- current command - addr : slv8; -- register address - dil : slv8; -- input data, lsb - dih : slv8; -- input data, msb - dol : slv8; -- output data, lsb - doh : slv8; -- output data, msb - cnt : slv8; -- block transfer count - attn : slv16; -- attn mask - atocnt : slv(ATOWIDTH-1 downto 0); -- access timeout counter - itocnt : slv(ITOWIDTH-1 downto 0); -- idle timeout counter - itoval : slv(ITOWIDTH-1 downto 0); -- idle timeout value - itoena : slbit; -- idle timeout enable flag - anena : slbit; -- attn notification enable flag - andone : slbit; -- attn notification done - ccrc : slbit; -- stat: command crc error - dcrc : slbit; -- stat: data crc error - ioto : slbit; -- stat: i/o time out - ioerr : slbit; -- stat: i/o time error - nakeop : slbit; -- send eop after nak - rbinit : slbit; -- rbus init signal - rbreq : slbit; -- rbus req signal - rbwe : slbit; -- rbus we signal - flush : slbit; -- flush pulse - stat : slv3; -- external status flags - end record regs_type; - - constant atocnt_init : slv(ATOWIDTH-1 downto 0) := (others=>'1'); - constant itocnt_init : slv(ITOWIDTH-1 downto 0) := (others=>'0'); - - constant c_idle : slv4 := "0000"; - constant c_sop : slv4 := "0001"; - constant c_eop : slv4 := "0010"; - constant c_nak : slv4 := "0011"; - constant c_attn : slv4 := "0100"; - - constant regs_init : regs_type := ( - s_idle, -- - (others=>'0'), -- rcmd - (others=>'0'), -- ccmd - (others=>'0'), -- addr - (others=>'0'), -- dil - (others=>'0'), -- dih - (others=>'0'), -- dol - (others=>'0'), -- doh - (others=>'0'), -- cnt - (others=>'0'), -- attn - atocnt_init, -- atocnt - itocnt_init, -- itocnt - itocnt_init, -- itoval - '0', -- itoena - '0','0', -- anena, andone - '0','0','0','0', -- stat flags - '0', -- nakeop - '0','0','0', -- rbinit,rbreq,rbwe - '0', -- flush - (others=>'0') -- stat - ); - - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs - - signal CRC_RESET : slbit := '0'; - signal ICRC_ENA : slbit := '0'; - signal OCRC_ENA : slbit := '0'; - signal ICRC_OUT : slv8 := (others=>'0'); - signal OCRC_OUT : slv8 := (others=>'0'); - signal OCRC_IN : slv8 := (others=>'0'); - -begin - - assert ITOWIDTH<=8 - report "assert(ITOWIDTH<=8): max byte size ITO counter supported" - severity failure; - - ICRC : crc8 -- crc generator for input data - port map ( - CLK => CLK, - RESET => CRC_RESET, - ENA => ICRC_ENA, - DI => CP_DI(7 downto 0), - CRC => ICRC_OUT - ); - - OCRC : crc8 -- crc generator for output data - port map ( - CLK => CLK, - RESET => CRC_RESET, - ENA => OCRC_ENA, - DI => OCRC_IN, - CRC => OCRC_OUT - ); - - proc_regs: process (CLK) - begin - - if CLK'event and CLK='1' then - if RESET = '1' then - R_REGS <= regs_init; - else - R_REGS <= N_REGS; - end if; - end if; - - end process proc_regs; - - proc_next: process (R_REGS, CE_INT, CP_DI, CP_ENA, CP_HOLD, RB_LAM, - RB_SRES, RB_STAT, ICRC_OUT, OCRC_OUT) - - variable r : regs_type := regs_init; - variable n : regs_type := regs_init; - - variable ival : slbit := '0'; - variable ibusy : slbit := '0'; - variable ido : slv9 := (others=>'0'); - variable ato_go : slbit := '0'; - variable ato_end : slbit := '0'; - variable ito_go : slbit := '0'; - variable ito_end : slbit := '0'; - variable crcreset : slbit := '0'; - variable icrcena : slbit := '0'; - variable ocrcena : slbit := '0'; - variable has_attn : slbit := '0'; - variable idi8 : slv8 := (others=>'0'); - variable is_comma : slbit := '0'; - variable comma_typ : slv4 := "0000"; - - procedure do_comma_abort(nstate : inout state_type; - nnakeop : inout slbit; - comma_typ : in slv4) is - begin - if comma_typ=c_sop or comma_typ=c_eop or comma_typ=c_nak then - if comma_typ = c_eop then - nnakeop := '1'; - end if; - nstate := s_txnak; -- next: send nak - end if; - end procedure do_comma_abort; - - begin - - r := R_REGS; - n := R_REGS; - - idi8 := CP_DI(7 downto 0); -- get data part of CP_DI - is_comma := CP_DI(8); -- get comma marker - comma_typ := CP_DI(3 downto 0); -- get comma type - - n.rbinit := '0'; -- clear rbinit,rbreq,rbwe by default - n.rbreq := '0'; -- they must always be set by the - n.rbwe := '0'; -- 'previous state' - - n.flush := '0'; -- dito for flush - - ibusy := '1'; -- default is to hold input - ival := '0'; - ido := (others=>'0'); - - crcreset := '0'; - icrcena := '0'; - ocrcena := '0'; - - for i in RB_LAM'range loop -- handle attention "LAM's" - if RB_LAM(i) = '1' then -- if LAM bit set - n.attn(i) := '1'; -- set attention bit - end if; - end loop; - - has_attn := '0'; - if unsigned(r.attn) /= 0 then -- is any of the attn bits set ? - has_attn := '1'; - end if; - - ato_go := '0'; -- default: keep access timeout in reset - ato_end := '0'; - if unsigned(r.atocnt) = 0 then -- if access timeout count at zero - ato_end := '1'; -- signal expiration - end if; - - ito_go := '0'; -- default: keep idle timeout in reset - ito_end := '0'; - if unsigned(r.itocnt) = 0 then -- if idle timeout count at zero - ito_end := '1'; -- signal expiration - end if; - - case r.state is - when s_idle => -- s_idle: wait for sop -------------- - ito_go := '1'; -- idle timeout active - if (r.anena='1' and -- if attn notification to send - has_attn='1' and r.andone='0') then - n.state := s_txito; -- next send ito byte - else - ibusy := '0'; -- accept input - if CP_ENA = '1' then -- if input - if is_comma = '1' then -- if comma - case comma_typ is - when c_sop => -- if sop - crcreset := '1'; -- reset crc generators - n.state := s_txsop; -- next: echo it - when c_eop => -- if eop (unexpected) - n.nakeop := '1'; -- send nak,eop - n.state := s_txnak; -- next: send nak - when c_attn => -- if attn - n.state := s_txito; -- next: send ito byte - when others => null; -- other commas: silently ignore - end case; - else -- if normal data - n.state := s_idle; -- silently dropped - end if; - elsif (r.itoena='1' and -- if ito enable, expired and XSEC - ito_end='1' and CE_INT='1') then - n.state := s_txito; -- next: send ito byte - end if; - end if; - - when s_txito => -- s_txito: send timeout symbol ------ - if has_attn = '1' then - ido := c_rri_dat_attn; -- if attn pending: send attn symbol - n.andone := '1'; - else - ido := c_rri_dat_idle; -- otherwise: send idle symbol - end if; - ival := '1'; - if CP_HOLD = '0' then -- wait for accept - n.state := s_idle; -- next: wait for sop - end if; - - when s_txsop => -- s_txsop: send sop ----------------- - ido := c_rri_dat_sop; -- send sop character - ival := '1'; - if CP_HOLD = '0' then -- wait for accept - n.state := s_rxcmd; -- next: read first command - end if; - - when s_txnak => -- s_txnak: send nak ----------------- - ido := c_rri_dat_nak; -- send nak character - ival := '1'; - if CP_HOLD = '0' then -- wait for accept - n.nakeop := '0'; - if r.nakeop = '1' then -- if eop after nak requested - n.state := s_txeop; -- next: send eop - else - n.state := s_error; -- next: error state, wait for eop - end if; - end if; - - when s_txeop => -- s_txeop: send eop ----------------- - ido := c_rri_dat_eop; -- send eop character - ival := '1'; - if CP_HOLD = '0' then -- wait for accept - n.flush := '1'; -- send flush pulse - n.state := s_idle; -- next: idle state, wait for sop - end if; - - when s_error => -- s_error: wait for eop ------------- - ibusy := '0'; -- accept input - if CP_ENA = '1' then - if is_comma = '1' then -- if comma - case comma_typ is - when c_sop => -- if sop (unexpected) - n.state := s_txnak; -- next: send nak - when c_eop => -- if eop - n.state := s_txeop; -- next: echo eop - when c_nak => -- if nak - n.state := s_txnak; -- next: echo nak - when others => null; -- other commas: silently ignore - end case; - else -- if normal data - n.state := s_error; -- silently dropped - end if; - end if; - - when s_rxcmd => -- s_rxcmd: wait for cmd ------------- - ibusy := '0'; -- accept input - if CP_ENA = '1' then - if is_comma = '1' then -- if comma - case comma_typ is - when c_sop => -- if sop (unexpected) - n.state := s_txnak; -- next: send nak - when c_eop => -- if eop - n.state := s_txeop; -- next: echo eop - when c_nak => -- if nak - n.state := s_txnak; -- next: echo nak - when others => null; --other commas: silently ignore - end case; - else - icrcena := '1'; -- update input crc - n.rcmd := idi8; -- latch read command code - case CP_DI(c_rri_cmd_rbf_code) is - when c_rri_cmd_rreg | c_rri_cmd_rblk | - c_rri_cmd_wreg | c_rri_cmd_wblk | - c_rri_cmd_init => -- for commands needing addr(data) - n.state := s_rxaddr; -- next: read address - when c_rri_cmd_stat | c_rri_cmd_attn => -- stat and attn commands - n.state := s_rxccrc; -- next: read command crc - when others => - n.state := s_idle; -- if bad command abort here - end case; -- rcmd,ccmd always hold good cmd - end if; - end if; - - when s_rxaddr => -- s_rxaddr: wait for addr ----------- - ibusy := '0'; -- accept input - if CP_ENA = '1' then - if is_comma = '1' then -- if comma - do_comma_abort(n.state, n.nakeop, comma_typ); - else - icrcena := '1'; -- update input crc - n.addr := idi8; -- latch read address - case r.rcmd(c_rri_cmd_rbf_code) is - when c_rri_cmd_rreg => -- for rreg command - n.state := s_rxccrc; -- next: read command crc - when c_rri_cmd_wreg | c_rri_cmd_init => -- for wreg, init command - n.state := s_rxdatl; -- next: read data lsb - when others => -- for rblk or wblk - n.state := s_rxcnt; -- next: read count - end case; - end if; - end if; - - when s_rxdatl => -- s_rxdatl: wait for data low ------- - ibusy := '0'; -- accept input - if CP_ENA = '1' then - if is_comma = '1' then -- if comma - do_comma_abort(n.state, n.nakeop, comma_typ); - else - icrcena := '1'; -- update input crc - n.dil := idi8; -- latch data lsb part - n.state := s_rxdath; -- next: read data msb - end if; - end if; - - when s_rxdath => -- s_rxdath: wait for data high ------ - ibusy := '0'; -- accept input - if CP_ENA = '1' then - if is_comma = '1' then -- if comma - do_comma_abort(n.state, n.nakeop, comma_typ); - else - icrcena := '1'; -- update input crc - n.dih := idi8; -- latch data msb part - if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_wblk then -- if wblk - n.rbreq := '1'; - n.rbwe := '1'; - n.state := s_wreg; -- next: write reg - else -- otherwise - n.state := s_rxccrc; -- next: read command crc - end if; - end if; - end if; - - when s_rxcnt => -- s_rxcnt: wait for count ----------- - ibusy := '0'; -- accept input - if CP_ENA = '1' then - if is_comma = '1' then -- if comma - do_comma_abort(n.state, n.nakeop, comma_typ); - else - icrcena := '1'; -- update input crc - n.cnt := idi8; -- latch count - n.state := s_rxccrc; -- next: read command crc - end if; - end if; - - when s_rxccrc => -- s_rxccrc: wait for command crc ---- - ibusy := '0'; -- accept input - if CP_ENA = '1' then - if is_comma = '1' then -- if comma - do_comma_abort(n.state, n.nakeop, comma_typ); - else - if idi8 /= ICRC_OUT then -- if crc error - n.ccrc := '1'; -- set command crc error flag - n.state := s_txnak; -- next: send nak - else -- if crc ok - n.state := s_txcmd; -- next: echo command - end if; - end if; - end if; - - when s_txcmd => -- s_txcmd: send cmd ----------------- - ido := '0' & r.rcmd; -- send read command - ival := '1'; - if CP_HOLD = '0' then -- wait for accept - ocrcena := '1'; -- update output crc - if r.rcmd(c_rri_cmd_rbf_code) /= c_rri_cmd_stat then -- unless stat - n.ccmd := r.rcmd; -- latch read command in ccmd - n.stat := RB_STAT; -- latch external status bits - n.ccrc := '0'; - n.dcrc := '0'; - n.ioto := '0'; - n.ioerr := '0'; - end if; - case r.rcmd(c_rri_cmd_rbf_code) is -- main command dispatcher - when c_rri_cmd_rreg => -- rreg ---------------- - n.rbreq := '1'; - n.state := s_rreg; - when c_rri_cmd_rblk => -- rblk ---------------- - n.state := s_txcnt; - when c_rri_cmd_wreg => -- wreg ---------------- - n.rbreq := '1'; - n.rbwe := '1'; - n.state := s_wreg; - when c_rri_cmd_wblk => -- wblk ---------------- - n.state := s_rxdatl; - when c_rri_cmd_stat => -- stat ---------------- - n.state := s_txccmd; - when c_rri_cmd_attn => -- attn ---------------- - n.state := s_attn; - - when c_rri_cmd_init => -- init ---------------- - n.rbinit := '1'; -- send init pulse - if r.addr(7 downto 3) = "11111" then -- is internal init - if r.addr(2 downto 0) = "111" then -- is rri init - n.anena := r.dih(c_rri_iint_rbf_anena - 8); - n.itoena := r.dih(c_rri_iint_rbf_itoena - 8); - n.itoval := r.dil(ITOWIDTH-1 downto 0); - -- note: itocnt will load in next - -- cycle because ito_go=0, so no - -- action required here - - end if; - else -- is external init - n.rbwe := '1'; -- send init with we - end if; - n.state := s_txstat; - - when others => -- '111' --------------- - n.state := s_txnak; -- send NAK on reserved command - end case; - end if; - - when s_txcnt => -- s_txcnt: send cnt ----------------- - ido := '0' & r.cnt; -- send cnt - ival := '1'; - if CP_HOLD = '0' then -- wait for accept - ocrcena := '1'; -- update output crc - n.rbreq := '1'; - n.state := s_rreg; -- next: first read reg - end if; - - when s_rreg => -- s_rreg: reg or blk read ----------- - -- this state handles all rbus reads. Expects that previous state - -- sets n.rbreq := '1' to start an rbus read cycle - ato_go := '1'; -- activate timeout counter - if RB_SRES.err = '1' then -- latch error flag - n.ioerr := '1'; - end if; - n.doh := RB_SRES.dout(15 downto 8); -- latch data - n.dol := RB_SRES.dout( 7 downto 0); - n.stat := RB_STAT; -- latch external status bits - if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout - if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy - n.ioto := '1'; -- set timeout flag - elsif RB_SRES.ack = '0' then -- if non-busy and no ack - n.ioto := '1'; -- set timeout flag - end if; - n.state := s_txdatl; -- next: send data lsb - else -- otherwise rbus read continues - n.rbreq := '1'; -- extend req - end if; - - when s_txdatl => -- s_txdatl: send data low ----------- - ido := '0' & r.dol; -- send data - ival := '1'; - if CP_HOLD = '0' then -- wait for accept - ocrcena := '1'; -- update output crc - n.state := s_txdath; -- next: send data msb - end if; - - when s_txdath => -- s_txdath: send data high - ido := '0' & r.doh; -- send data - ival := '1'; - if CP_HOLD = '0' then -- wait for accept - ocrcena := '1'; -- update output crc - if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_rblk then -- if rblk - n.state := s_blk; -- next: block count handling - else -- otherwise - n.state := s_txstat; -- next: send stat - end if; - end if; - - when s_wreg => -- s_wreg: reg or blk write ---------- - -- this state handles all rbus writes. Expects that previous state - -- sets n.rbreq := '1' and n.rbwe := '1' to start an rbus write cycle - ato_go := '1'; -- activate timeout counter - if RB_SRES.err = '1' then -- latch error flag - n.ioerr := '1'; - end if; - n.stat := RB_STAT; -- latch external status bits - if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout - if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy - n.ioto := '1'; -- set timeout flag - elsif RB_SRES.ack='0' then -- if non-busy and no ack - n.ioto := '1'; -- set timeout flag - end if; - if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_wblk then -- if wblk - n.state := s_blk; -- next: block count handling - else -- otherwise - n.state := s_txstat; -- next: send stat - end if; - else -- otherwise rbus write continues - n.rbreq := '1'; -- extend req - n.rbwe := '1'; -- extend we - end if; - - when s_blk => -- s_blk: block count handling ------- - n.cnt := unsigned(r.cnt) - 1; -- decrement transfer count - if unsigned(r.cnt) = 0 then -- if last transfer - if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_rblk then -- if rblk - n.state := s_txstat; -- next: send stat - else -- otherwise - n.state := s_rxdcrc; -- next: read data crc - end if; - - else -- otherwise more to transfer - if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_rblk then -- if rblk - n.rbreq := '1'; - n.state := s_rreg; -- next: read blk - else -- otherwise - n.state := s_rxdatl; -- next: read data - end if; - end if; - - when s_rxdcrc => -- s_rxdcrc: wait for data crc ------- - ibusy := '0'; -- accept input - if CP_ENA = '1' then - if is_comma = '1' then -- if comma - do_comma_abort(n.state, n.nakeop, comma_typ); - else - if idi8 /= ICRC_OUT then -- if crc error - n.dcrc := '1'; -- set data crc error flag - end if; - n.state := s_txstat; -- next: echo command - end if; - end if; - - when s_attn => -- s_attn: handle attention flags ---- - n.dol := r.attn(7 downto 0); -- move attention flags to do buffer - n.doh := r.attn(15 downto 8); - n.attn := RB_LAM; -- LAM in current cycle send next time - n.andone := '0'; -- reenable attn nofification - n.state := s_txdatl; -- next: send data lsb - - when s_txccmd => -- s_txccmd: send last command - ido := '0' & r.ccmd; -- send last accepted command - ival := '1'; - if CP_HOLD = '0' then -- wait for accept - ocrcena := '1'; -- update output crc - n.state := s_txdatl; -- next: send last data lsb - end if; - - when s_txstat => -- s_txstat: send status ------------- - ido := (others=>'0'); - ido(c_rri_stat_rbf_stat) := r.stat; - ido(c_rri_stat_rbf_attn) := has_attn; - ido(c_rri_stat_rbf_ccrc) := r.ccrc; - ido(c_rri_stat_rbf_dcrc) := r.dcrc; - ido(c_rri_stat_rbf_ioto) := r.ioto; - ido(c_rri_stat_rbf_ioerr) := r.ioerr; - ival := '1'; - if CP_HOLD ='0' then -- wait for accept - ocrcena := '1'; -- update output crc - n.state := s_txcrc; -- next: send crc - end if; - - when s_txcrc => -- s_txcrc: send crc ----------------- - ido := "0" & OCRC_OUT; -- send crc code - ival := '1'; - if CP_HOLD = '0' then -- wait for accept - n.state := s_rxcmd; -- next: read command or eop - end if; - - when others => null; -- <> -------------------------------- - end case; - - if ato_go = '0' then -- handle access timeout counter - n.atocnt := atocnt_init; -- if ato_go=0, keep in reset - else - n.atocnt := unsigned(r.atocnt) - 1;-- otherwise count down - end if; - - if ito_go = '0' then -- handle idle timeout counter - n.itocnt := r.itoval; -- if ito_go=0, keep at start value - else - if CE_INT = '1' then - n.itocnt := unsigned(r.itocnt) - 1;-- otherwise count down every CE_INT - end if; - end if; - - N_REGS <= n; - - CP_BUSY <= ibusy; - CP_DO <= ido; - CP_VAL <= ival; - CP_FLUSH <= r.flush; - - RB_MREQ <= rb_mreq_init; - RB_MREQ.req <= r.rbreq; - RB_MREQ.we <= r.rbwe; - RB_MREQ.init <= r.rbinit; - RB_MREQ.addr <= r.addr; - RB_MREQ.din <= r.dih & r.dil; - - CRC_RESET <= crcreset; - ICRC_ENA <= icrcena; - OCRC_ENA <= ocrcena; - OCRC_IN <= ido(7 downto 0); - - end process proc_next; - -end syn; Index: rtl/vlib/rri/rri_core_serport.vbom =================================================================== --- rtl/vlib/rri/rri_core_serport.vbom (revision 8) +++ rtl/vlib/rri/rri_core_serport.vbom (nonexistent) @@ -1,11 +0,0 @@ -# libs -../slvtypes.vhd -rrilib.vhd -[ghdl,isim]tb/rritblib.vhd -# components -rri_serport.vbom -rri_core.vbom -[ghdl,isim]tb/rritb_cpmon_sb.vbom -[ghdl,isim]tb/rritb_rbmon_sb.vbom -# design -rri_core_serport.vhd Index: rtl/vlib/rri =================================================================== --- rtl/vlib/rri (revision 8) +++ rtl/vlib/rri (nonexistent)
rtl/vlib/rri Property changes : Deleted: svn:ignore ## -1,32 +0,0 ## -*.dep_ghdl -*.dep_isim -*.dep_xst -work-obj93.cf -*.vcd -*.ghw -*.sav -*.tmp -*.exe -ise -xflow.his -*.ngc -*.ncd -*.pcf -*.bit -*.msk -isim -isim.log -isim.wdb -fuse.log -*_[sft]sim.vhd -*_tsim.sdf -*_xst.log -*_tra.log -*_twr.log -*_map.log -*_par.log -*_pad.log -*_bgn.log -*_svn.log -*_sum.log -*_[dsft]sim.log Index: rtl/vlib/rlink/rlinklib.vhd =================================================================== --- rtl/vlib/rlink/rlinklib.vhd (nonexistent) +++ rtl/vlib/rlink/rlinklib.vhd (revision 9) @@ -0,0 +1,308 @@ +-- $Id: rlinklib.vhd 348 2010-12-26 15:23:44Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: rlinklib +-- Description: Definitions for rlink interface and bus entities +-- +-- Dependencies: - +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core; +-- new rlink_serport interface; +-- rename rlink_core_serport->rlink_base_serport +-- 2010-12-24 347 3.1.1 rename: CP_*->RL->* +-- 2010-12-22 346 3.1 rename: [cd]crc->[cd]err, ioto->rbnak, ioerr->rberr +-- 2010-12-04 343 3.0 move rbus components to rbus/rblib; renames +-- rri_ -> rlink and c_rri -> c_rlink; +-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_ +-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining +-- 2010-06-03 300 2.1.5 use FAWIDTH=5 for rri_serport +-- 2010-05-02 287 2.1.4 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM +-- drop RP_IINT from interfaces; drop RTSFLUSH generic +-- 2010-05-01 285 2.1.3 remove rri_rb_rpcompat, now obsolete +-- 2010-04-18 279 2.1.2 rri_core_serport: drop RTSFBUF generic +-- 2010-04-10 275 2.1.1 add rri_core_serport +-- 2010-04-03 274 2.1 add CP_FLUSH for rri_core, rri_serport; +-- CE_USEC, RTSFLUSH, CTS_N, RTS_N for rri_serport +-- 2008-08-24 162 2.0 all with new rb_mreq/rb_sres interface +-- 2008-08-22 161 1.3 renamed rri_rbres_ -> rb_sres_; drop rri_[24]rp +-- 2008-02-16 116 1.2.1 added rri_wreg(rw|w|r)_3 +-- 2008-01-20 113 1.2 added rb_[mreq|sres]; _rbres_or_*; _rb_rpcompat +-- 2007-11-24 98 1.1 added RP_IINT for rri_core. +-- 2007-09-09 81 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.slvtypes.all; +use work.rblib.all; + +package rlinklib is + +constant c_rlink_cpref : slv4 := "1000"; -- default comma prefix +constant c_rlink_ncomm : positive := 4; -- number commas (sop,eop,nak,attn) + +constant c_rlink_dat_idle : slv9 := "100000000"; +constant c_rlink_dat_sop : slv9 := "100000001"; +constant c_rlink_dat_eop : slv9 := "100000010"; +constant c_rlink_dat_nak : slv9 := "100000011"; +constant c_rlink_dat_attn : slv9 := "100000100"; + +constant c_rlink_cmd_rreg : slv3 := "000"; +constant c_rlink_cmd_rblk : slv3 := "001"; +constant c_rlink_cmd_wreg : slv3 := "010"; +constant c_rlink_cmd_wblk : slv3 := "011"; +constant c_rlink_cmd_stat : slv3 := "100"; +constant c_rlink_cmd_attn : slv3 := "101"; +constant c_rlink_cmd_init : slv3 := "110"; + +constant c_rlink_iint_rbf_anena: integer := 15; -- anena flag +constant c_rlink_iint_rbf_itoena: integer := 14; -- itoena flag +subtype c_rlink_iint_rbf_itoval is integer range 7 downto 0; -- command code + +subtype c_rlink_cmd_rbf_seq is integer range 7 downto 3; -- sequence number +subtype c_rlink_cmd_rbf_code is integer range 2 downto 0; -- command code + +subtype c_rlink_stat_rbf_stat is integer range 7 downto 5; -- ext status bits +constant c_rlink_stat_rbf_attn: integer := 4; -- attention flags set +constant c_rlink_stat_rbf_cerr: integer := 3; -- command error +constant c_rlink_stat_rbf_derr: integer := 2; -- data error +constant c_rlink_stat_rbf_rbnak: integer := 1; -- rbus no ack or timeout +constant c_rlink_stat_rbf_rberr: integer := 0; -- rbus err bit set + +type rl_moni_type is record -- rlink_core monitor port + eop : slbit; -- eop send in last cycle + attn : slbit; -- attn send in last cycle + lamp : slbit; -- attn (lam) pending +end record rl_moni_type; + +constant rl_moni_init : rl_moni_type := + ('0','0','0'); -- eop,attn,lamp + +component rlink_core is -- rlink core with 9bit iface + generic ( + ATOWIDTH : positive := 5; -- access timeout counter width + ITOWIDTH : positive := 6); -- idle timeout counter width + port ( + CLK : in slbit; -- clock + CE_INT : in slbit := '0'; -- rlink ito time unit clock enable + RESET : in slbit; -- reset + RL_DI : in slv9; -- rlink 9b: data in + RL_ENA : in slbit; -- rlink 9b: data enable + RL_BUSY : out slbit; -- rlink 9b: data busy + RL_DO : out slv9; -- rlink 9b: data out + RL_VAL : out slbit; -- rlink 9b: data valid + RL_HOLD : in slbit; -- rlink 9b: data hold + RL_MONI : out rl_moni_type; -- rlink: monitor port + RB_MREQ : out rb_mreq_type; -- rbus: request + RB_SRES : in rb_sres_type; -- rbus: response + RB_LAM : in slv16; -- rbus: look at me + RB_STAT : in slv3 -- rbus: status flags + ); +end component; + +component rlink_aif is -- rlink, abstract interface + port ( + CLK : in slbit; -- clock + CE_INT : in slbit := '0'; -- rlink ito time unit clock enable + RESET : in slbit :='0'; -- reset + RL_DI : in slv9; -- rlink 9b: data in + RL_ENA : in slbit; -- rlink 9b: data enable + RL_BUSY : out slbit; -- rlink 9b: data busy + RL_DO : out slv9; -- rlink 9b: data out + RL_VAL : out slbit; -- rlink 9b: data valid + RL_HOLD : in slbit := '0' -- rlink 9b: data hold + ); +end component; + +component rlink_rlb2rl is -- rlink 8 bit(rlb) to 9 bit(rl) adapter + generic ( + CPREF : slv4 := c_rlink_cpref; -- comma prefix + IFAWIDTH : natural := 5; -- input fifo address width (0=none) + OFAWIDTH : natural := 5); -- output fifo address width (0=none) + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + RLB_DI : in slv8; -- rlink 8b: data in + RLB_ENA : in slbit; -- rlink 8b: data enable + RLB_BUSY : out slbit; -- rlink 8b: data busy + RLB_DO : out slv8; -- rlink 8b: data out + RLB_VAL : out slbit; -- rlink 8b: data valid + RLB_HOLD : in slbit; -- rlink 8b: data hold + IFIFO_SIZE : out slv4; -- input fifo size (4 msb's) + OFIFO_SIZE : out slv4; -- output fifo fill (4 msb's) + RL_DI : out slv9; -- rlink 9b: data in + RL_ENA : out slbit; -- rlink 9b: data enable + RL_BUSY : in slbit; -- rlink 9b: data busy + RL_DO : in slv9; -- rlink 9b: data out + RL_VAL : in slbit; -- rlink 9b: data valid + RL_HOLD : out slbit -- rlink 9b: data hold + ); +end component; + +-- this definition logically belongs into the 'for test benches' section' +-- must be here because it is needed as generic default in rlink_base +-- simbus sb_cntl field usage for rlink + constant sbcntl_sbf_rlmon : integer := 15; + +component rlink_base is -- rlink base: core+rl2rlb+rlmon+rbmon + -- with buffered 8bit interface + generic ( + ATOWIDTH : positive := 5; -- access timeout counter width + ITOWIDTH : positive := 6; -- idle timeout counter width + CPREF : slv4 := c_rlink_cpref; -- comma prefix + IFAWIDTH : natural := 5; -- input fifo address width (0=none) + OFAWIDTH : natural := 5; -- output fifo address width (0=none) + ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none) + ENAPIN_RBMON : integer := sbcntl_sbf_rbmon); -- SB_CNTL for rbmon (-1=none) + port ( + CLK : in slbit; -- clock + CE_INT : in slbit := '0'; -- rlink ito time unit clock enable + RESET : in slbit; -- reset + RLB_DI : in slv8; -- rlink 8b: data in + RLB_ENA : in slbit; -- rlink 8b: data enable + RLB_BUSY : out slbit; -- rlink 8b: data busy + RLB_DO : out slv8; -- rlink 8b: data out + RLB_VAL : out slbit; -- rlink 8b: data valid + RLB_HOLD : in slbit; -- rlink 8b: data hold + IFIFO_SIZE : out slv4; -- input fifo size (4 msb's) + OFIFO_SIZE : out slv4; -- output fifo fill (4 msb's) + RL_MONI : out rl_moni_type; -- rlink: monitor port + RB_MREQ : out rb_mreq_type; -- rbus: request + RB_SRES : in rb_sres_type; -- rbus: response + RB_LAM : in slv16; -- rbus: look at me + RB_STAT : in slv3 -- rbus: status flags + ); +end component; + +type rl_ser_moni_type is record -- rlink_serport monitor port + rxerr : slbit; -- rx err + rxdrop : slbit; -- rx drop + rxact : slbit; -- rx active + txact : slbit; -- tx active + abact : slbit; -- ab active + abdone : slbit; -- ab done + clkdiv : slv16; -- clock divider +end record rl_ser_moni_type; + +constant rl_ser_moni_init : rl_ser_moni_type := + ('0','0', -- rxerr,rxdrop + '0','0', -- rxact,txact + '0','0', -- abact,abdone + (others=>'0')); -- clkdiv + +constant c_rlink_serport_rbf_fena: integer := 12; -- +subtype c_rlink_serport_rbf_fwidth is integer range 11 downto 9; -- +subtype c_rlink_serport_rbf_fdelay is integer range 8 downto 6; -- +subtype c_rlink_serport_rbf_rtsoff is integer range 5 downto 3; -- +subtype c_rlink_serport_rbf_rtson is integer range 2 downto 0; -- + +component rlink_serport is -- rlink serport adapter + generic ( + RB_ADDR : slv8 := conv_std_logic_vector(2#11111110#,8); + CDWIDTH : positive := 13; -- clk divider width + CDINIT : natural := 15); -- clk divider initial/reset setting + port ( + CLK : in slbit; -- clock + CE_USEC : in slbit; -- 1 usec clock enable + CE_MSEC : in slbit; -- 1 msec clock enable + RESET : in slbit; -- reset + RXSD : in slbit; -- receive serial data (board view) + TXSD : out slbit; -- transmit serial data (board view) + CTS_N : in slbit := '0'; -- clear to send (act.low, board view) + RTS_N : out slbit; -- request to send (act.low, board view) + RLB_DI : out slv8; -- rlink 8b: data in + RLB_ENA : out slbit; -- rlink 8b: data enable + RLB_BUSY : in slbit; -- rlink 8b: data busy + RLB_DO : in slv8; -- rlink 8b: data out + RLB_VAL : in slbit; -- rlink 8b: data valid + RLB_HOLD : out slbit; -- rlink 8b: data hold + RB_MREQ : in rb_mreq_type; -- rbus: request (for inits only) + IFIFO_SIZE : in slv4; -- rlink_rlb2rb: input fifo size + RL_MONI : in rl_moni_type; -- rlink_core: monitor port + RL_SER_MONI : out rl_ser_moni_type -- rlink_serport: monitor port + ); +end component; + +component rlink_base_serport is -- rlink base+serport combo + generic ( + ATOWIDTH : positive := 5; -- access timeout counter width + ITOWIDTH : positive := 6; -- idle timeout counter width + CPREF : slv4 := c_rlink_cpref; -- comma prefix + IFAWIDTH : natural := 5; -- input fifo address width (0=none) + OFAWIDTH : natural := 5; -- output fifo address width (0=none) + ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none) + ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none) + RB_ADDR : slv8 := conv_std_logic_vector(2#11111110#,8); + CDWIDTH : positive := 13; -- clk divider width + CDINIT : natural := 15); -- clk divider initial/reset setting + port ( + CLK : in slbit; -- clock + CE_USEC : in slbit; -- 1 usec clock enable + CE_MSEC : in slbit; -- 1 msec clock enable + CE_INT : in slbit := '0'; -- rri ito time unit clock enable + RESET : in slbit; -- reset + RXSD : in slbit; -- receive serial data (board view) + TXSD : out slbit; -- transmit serial data (board view) + CTS_N : in slbit := '0'; -- clear to send (act.low, board view) + RTS_N : out slbit; -- request to send (act.low, board view) + RB_MREQ : out rb_mreq_type; -- rbus: request + RB_SRES : in rb_sres_type; -- rbus: response + RB_LAM : in slv16; -- rbus: look at me + RB_STAT : in slv3; -- rbus: status flags + RL_MONI : out rl_moni_type; -- rlink_core: monitor port + RL_SER_MONI : out rl_ser_moni_type -- rlink_serport: monitor port + ); +end component; + +-- +-- components for use in test benches (not synthesizable) +-- + +component rlink_mon is -- rlink monitor + generic ( + DWIDTH : positive := 9); -- data port width (8 or 9) + port ( + CLK : in slbit; -- clock + CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number + ENA : in slbit := '1'; -- enable monitor output + RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in + RL_ENA : in slbit; -- rlink: data enable + RL_BUSY : in slbit; -- rlink: data busy + RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out + RL_VAL : in slbit; -- rlink: data valid + RL_HOLD : in slbit -- rlink: data hold + ); +end component; + +component rlink_mon_sb is -- simbus wrap for rlink monitor + generic ( + DWIDTH : positive := 9; -- data port width (8 or 9) + ENAPIN : integer := sbcntl_sbf_rlmon); -- SB_CNTL signal to use for enable + port ( + CLK : in slbit; -- clock + RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in + RL_ENA : in slbit; -- rlink: data enable + RL_BUSY : in slbit; -- rlink: data busy + RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out + RL_VAL : in slbit; -- rlink: data valid + RL_HOLD : in slbit -- rlink: data hold + ); +end component; + +end rlinklib; Index: rtl/vlib/rlink/rlink_base.vhd =================================================================== --- rtl/vlib/rlink/rlink_base.vhd (nonexistent) +++ rtl/vlib/rlink/rlink_base.vhd (revision 9) @@ -0,0 +1,174 @@ +-- $Id: rlink_base.vhd 350 2010-12-28 16:40:11Z mueller $ +-- +-- Copyright 2010- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rlink_base - syn +-- Description: rlink base: core+rl2rlb+rlmon+rbmon - w/ buffered 8bit iface +-- +-- Dependencies: rlink_core +-- rlink_rlb2rl +-- rlink_mon_sb [sim only] +-- rbus/rb_mon_sb [sim only] +-- +-- Test bench: tb/tb_rlink_serport +-- tb/tb_rlink_tba_ttcombo +-- +-- Target Devices: generic +-- Tool versions: xst 12.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa +-- 2010-12-25 348 12.1 M53d xc3s1000-4 206 451 72 304 s 10.5 5 5 +-- 2010-12-25 348 12.1 M53d xc3s1000-4 194 407 36 262 s 10.4 5 0 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-25 348 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.slvtypes.all; +use work.rblib.all; +use work.rlinklib.all; + +entity rlink_base is -- rlink base: core+rlb2rl+rlmon+rbmon + -- with buffered 8bit interface + generic ( + ATOWIDTH : positive := 5; -- access timeout counter width + ITOWIDTH : positive := 6; -- idle timeout counter width + CPREF : slv4 := c_rlink_cpref; -- comma prefix + IFAWIDTH : natural := 5; -- input fifo address width (0=none) + OFAWIDTH : natural := 5; -- output fifo address width (0=none) + ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none) + ENAPIN_RBMON : integer := sbcntl_sbf_rbmon); -- SB_CNTL for rbmon (-1=none) + port ( + CLK : in slbit; -- clock + CE_INT : in slbit := '0'; -- rlink ito time unit clock enable + RESET : in slbit; -- reset + RLB_DI : in slv8; -- rlink 8b: data in + RLB_ENA : in slbit; -- rlink 8b: data enable + RLB_BUSY : out slbit; -- rlink 8b: data busy + RLB_DO : out slv8; -- rlink 8b: data out + RLB_VAL : out slbit; -- rlink 8b: data valid + RLB_HOLD : in slbit; -- rlink 8b: data hold + IFIFO_SIZE : out slv4; -- input fifo size (4 msb's) + OFIFO_SIZE : out slv4; -- output fifo fill (4 msb's) + RL_MONI : out rl_moni_type; -- rlink: monitor port + RB_MREQ : out rb_mreq_type; -- rbus: request + RB_SRES : in rb_sres_type; -- rbus: response + RB_LAM : in slv16; -- rbus: look at me + RB_STAT : in slv3 -- rbus: status flags + ); +end entity rlink_base; + + +architecture syn of rlink_base is + + signal RL_DI : slv9 := (others=>'0'); + signal RL_ENA : slbit := '0'; + signal RL_BUSY : slbit := '0'; + signal RL_DO : slv9 := (others=>'0'); + signal RL_VAL : slbit := '0'; + signal RL_HOLD : slbit := '0'; + signal RB_MREQ_L : rb_mreq_type := rb_mreq_init; -- local, readable RB_MREQ + +begin + + RL : rlink_core + generic map ( + ATOWIDTH => ATOWIDTH, + ITOWIDTH => ITOWIDTH) + port map ( + CLK => CLK, + CE_INT => CE_INT, + RESET => RESET, + RL_DI => RL_DI, + RL_ENA => RL_ENA, + RL_BUSY => RL_BUSY, + RL_DO => RL_DO, + RL_VAL => RL_VAL, + RL_HOLD => RL_HOLD, + RL_MONI => RL_MONI, + RB_MREQ => RB_MREQ_L, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT + ); + -- vhdl'93 unfortunately doesn't allow to read a signal bound to an out port + -- because RB_MREQ is read by the monitors, an extra internal + -- signal must be used. This will not be needed with vhdl'2000 anymore + + RB_MREQ <= RB_MREQ_L; + + RLB2RL : rlink_rlb2rl + generic map ( + CPREF => CPREF, + IFAWIDTH => IFAWIDTH, + OFAWIDTH => OFAWIDTH) + port map ( + CLK => CLK, + RESET => RESET, + RLB_DI => RLB_DI, + RLB_ENA => RLB_ENA, + RLB_BUSY => RLB_BUSY, + RLB_DO => RLB_DO, + RLB_VAL => RLB_VAL, + RLB_HOLD => RLB_HOLD, + IFIFO_SIZE => IFIFO_SIZE, + OFIFO_SIZE => OFIFO_SIZE, + RL_DI => RL_DI, + RL_ENA => RL_ENA, + RL_BUSY => RL_BUSY, + RL_DO => RL_DO, + RL_VAL => RL_VAL, + RL_HOLD => RL_HOLD + ); + +-- synthesis translate_off + + RLMON: if ENAPIN_RLMON >= 0 generate + MON : rlink_mon_sb + generic map ( + DWIDTH => RL_DI'length, + ENAPIN => ENAPIN_RLMON) + port map ( + CLK => CLK, + RL_DI => RL_DI, + RL_ENA => RL_ENA, + RL_BUSY => RL_BUSY, + RL_DO => RL_DO, + RL_VAL => RL_VAL, + RL_HOLD => RL_HOLD + ); + end generate RLMON; + + RBMON: if ENAPIN_RBMON >= 0 generate + MON : rb_mon_sb + generic map ( + DBASE => 8, + ENAPIN => ENAPIN_RBMON) + port map ( + CLK => CLK, + RB_MREQ => RB_MREQ_L, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT + ); + end generate RBMON; + +-- synthesis translate_on + +end syn; Index: rtl/vlib/rlink/rlink_base_serport.vbom =================================================================== --- rtl/vlib/rlink/rlink_base_serport.vbom (nonexistent) +++ rtl/vlib/rlink/rlink_base_serport.vbom (revision 9) @@ -0,0 +1,9 @@ +# libs +../slvtypes.vhd +../rbus/rblib.vhd +rlinklib.vbom +# components +rlink_base.vbom +rlink_serport.vbom +# design +rlink_base_serport.vhd Index: rtl/vlib/rlink/rlink_core.vbom =================================================================== --- rtl/vlib/rlink/rlink_core.vbom (nonexistent) +++ rtl/vlib/rlink/rlink_core.vbom (revision 9) @@ -0,0 +1,9 @@ +# libs +../slvtypes.vhd +../comlib/comlib.vhd +../rbus/rblib.vhd +rlinklib.vbom +# components +../comlib/crc8.vbom +# design +rlink_core.vhd Index: rtl/vlib/rlink/rlink_mon.vbom =================================================================== --- rtl/vlib/rlink/rlink_mon.vbom (nonexistent) +++ rtl/vlib/rlink/rlink_mon.vbom (revision 9) @@ -0,0 +1,7 @@ +# libs +../slvtypes.vhd +../simlib/simlib.vhd +rlinklib.vbom +# components +# design +rlink_mon.vhd Index: rtl/vlib/rlink/rlink_mon_sb.vhd =================================================================== --- rtl/vlib/rlink/rlink_mon_sb.vhd (nonexistent) +++ rtl/vlib/rlink/rlink_mon_sb.vhd (revision 9) @@ -0,0 +1,80 @@ +-- $Id: rlink_mon_sb.vhd 347 2010-12-24 12:10:42Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rlink_mon_sb - sim +-- Description: simbus wrapper for rlink monitor +-- +-- Dependencies: simbus +-- Test bench: - +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-24 347 3.0.1 rename: CP_*->RL->* +-- 2010-12-22 346 3.0 renamed rritb_cpmon_sb -> rlink_mon_sb +-- 2010-05-02 287 1.0.1 use sbcntl_sbf_cpmon def +-- 2007-08-25 75 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.simlib.all; +use work.simbus.all; +use work.rlinklib.all; + +entity rlink_mon_sb is -- simbus wrap for rlink monitor + generic ( + DWIDTH : positive := 9; -- data port width (8 or 9) + ENAPIN : integer := sbcntl_sbf_rlmon); -- SB_CNTL signal to use for enable + port ( + CLK : in slbit; -- clock + RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in + RL_ENA : in slbit; -- rlink: data enable + RL_BUSY : in slbit; -- rlink: data busy + RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out + RL_VAL : in slbit; -- rlink: data valid + RL_HOLD : in slbit -- rlink: data hold + ); +end rlink_mon_sb; + + +architecture sim of rlink_mon_sb is + + signal ENA : slbit := '0'; + +begin + + assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high + report "assert(ENAPIN in SB_CNTL'range)" severity failure; + + ENA <= to_x01(SB_CNTL(ENAPIN)); + + CPMON : rlink_mon + generic map ( + DWIDTH => DWIDTH) + port map ( + CLK => CLK, + CLK_CYCLE => SB_CLKCYCLE, + ENA => ENA, + RL_DI => RL_DI, + RL_ENA => RL_ENA, + RL_BUSY => RL_BUSY, + RL_DO => RL_DO, + RL_VAL => RL_VAL, + RL_HOLD => RL_HOLD + ); + +end sim; Index: rtl/vlib/rlink/rlink_serport.vbom =================================================================== --- rtl/vlib/rlink/rlink_serport.vbom (nonexistent) +++ rtl/vlib/rlink/rlink_serport.vbom (revision 9) @@ -0,0 +1,9 @@ +# libs +../slvtypes.vhd +../serport/serport.vhd +../rbus/rblib.vhd +rlinklib.vbom +# components +../serport/serport_uart_rxtx_ab.vbom +# design +rlink_serport.vhd Index: rtl/vlib/rlink/rlink_rlb2rl.vbom =================================================================== --- rtl/vlib/rlink/rlink_rlb2rl.vbom (nonexistent) +++ rtl/vlib/rlink/rlink_rlb2rl.vbom (revision 9) @@ -0,0 +1,11 @@ +# libs +../slvtypes.vhd +../comlib/comlib.vhd +../memlib/memlib.vhd +rlinklib.vbom +# components +../comlib/byte2cdata.vbom +../comlib/cdata2byte.vbom +../memlib/fifo_1c_dram.vbom +# design +rlink_rlb2rl.vhd Index: rtl/vlib/rlink/tb/tb_rlink_serport_ssim.vbom =================================================================== --- rtl/vlib/rlink/tb/tb_rlink_serport_ssim.vbom (nonexistent) +++ rtl/vlib/rlink/tb/tb_rlink_serport_ssim.vbom (revision 9) @@ -0,0 +1,5 @@ +# configure tb_rlink with tbd_rlink_serport wrapper; _*sim case +tbd_rlink_gen = tbd_rlink_serport.vbom +tbu_rlink_serport = tbu_rlink_serport_ssim.vhd +tb_rlink_serport.vbom +@top:tb_rlink_serport Index: rtl/vlib/rlink/tb/tbcore_rlink.vbom =================================================================== --- rtl/vlib/rlink/tb/tbcore_rlink.vbom (nonexistent) +++ rtl/vlib/rlink/tb/tbcore_rlink.vbom (revision 9) @@ -0,0 +1,14 @@ +# libs +../../slvtypes.vhd +../../simlib/simlib.vhd +../../simlib/simbus.vhd +../../rbus/rblib.vhd +../rlinklib.vbom +rlinktblib.vhd +rlink_cext_vhpi.vhd +# components +../../simlib/simclk.vbom +# vhpi +rlink_cext.c +# design +tbcore_rlink.vhd Index: rtl/vlib/rlink/tb/tbcore_rlink_dcm.vhd =================================================================== --- rtl/vlib/rlink/tb/tbcore_rlink_dcm.vhd (nonexistent) +++ rtl/vlib/rlink/tb/tbcore_rlink_dcm.vhd (revision 9) @@ -0,0 +1,286 @@ +-- $Id: tbcore_rlink_dcm.vhd 351 2010-12-30 21:50:54Z mueller $ +-- +-- Copyright 2010- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tbcore_rlink_dcm - sim +-- Description: DCM aware core for a rlink_cext based test bench +-- +-- Dependencies: simlib/simclk +-- simlib/simclkcnt +-- +-- To test: generic, any rlink_cext based target +-- +-- Target Devices: generic +-- Tool versions: 11.4-12.1; ghdl 0.26-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-29 351 3.0 rename rritb_core_dcm->tbcore_rlink_dcm; rbv3 names +-- 2010-11-13 338 1.1 First DCM aware version, cloned from rritb_core +-- 2010-06-05 301 1.1.2 renamed .rpmon -> .rbmon +-- 2010-05-02 287 1.1.1 rename config command .sdata -> .sinit; +-- use sbcntl_sbf_(cp|rp)mon defs, use rritblib; +-- 2010-04-25 283 1.1 new clk handling in proc_stim, wait period-setup +-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.simlib.all; +use work.simbus.all; +use work.rblib.all; +use work.rlinklib.all; +use work.rlinktblib.all; +use work.rlink_cext_vhpi.all; + +entity tbcore_rlink_dcm is -- dcm aware core of rlink_cext based tb + generic ( + CLKOSC_PERIOD : time := 20 ns; -- clock osc period + CLKOSC_OFFSET : time := 200 ns; -- clock osc offset (time to start clk) + SETUP_TIME : time := 5 ns; -- setup time + C2OUT_TIME : time := 10 ns); -- clock to output time + port ( + CLKOSC : out slbit; -- clock osc + CLKSYS : in slbit; -- DCM derived system clock + RX_DATA : out slv8; -- read data (data ext->tb) + RX_VAL : out slbit; -- read data valid (data ext->tb) + RX_HOLD : in slbit; -- read data hold (data ext->tb) + TX_DATA : in slv8; -- write data (data tb->ext) + TX_ENA : in slbit -- write data enable (data tb->ext) + ); +end tbcore_rlink_dcm; + +architecture sim of tbcore_rlink_dcm is + + signal CLK_STOP : slbit := '0'; + +begin + + CLKGEN : simclk + generic map ( + PERIOD => CLKOSC_PERIOD, + OFFSET => CLKOSC_OFFSET) + port map ( + CLK => CLKOSC, + CLK_CYCLE => open, + CLK_STOP => CLK_STOP + ); + + CLKCNT : simclkcnt + port map ( + CLK => CLKSYS, + CLK_CYCLE => SB_CLKCYCLE + ); + + proc_conf: process + file fconf : text open read_mode is "rlink_cext_conf"; + variable iline : line; + variable oline : line; + variable ok : boolean; + variable dname : string(1 to 6) := (others=>' '); + variable ien : slbit := '0'; + variable ibit : integer := 0; + variable iaddr : slv8 := (others=>'0'); + variable idata : slv16 := (others=>'0'); + begin + + SB_CNTL <= (others=>'L'); + SB_VAL <= 'L'; + SB_ADDR <= (others=>'L'); + SB_DATA <= (others=>'L'); + + file_loop: while not endfile(fconf) loop + + readline (fconf, iline); + readcomment(iline, ok); + next file_loop when ok; + readword(iline, dname, ok); + + if ok then + case dname is + + when ".scntl" => -- .scntl + read_ea(iline, ibit); + read_ea(iline, ien); + assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high) + report "assert bit number in range of SB_CNTL" + severity failure; + if ien = '1' then + SB_CNTL(ibit) <= 'H'; + else + SB_CNTL(ibit) <= 'L'; + end if; + + when ".rlmon" => -- .rlmon + read_ea(iline, ien); + if ien = '1' then + SB_CNTL(sbcntl_sbf_rlmon) <= 'H'; + else + SB_CNTL(sbcntl_sbf_rlmon) <= 'L'; + end if; + + when ".rbmon" => -- .rbmon + read_ea(iline, ien); + if ien = '1' then + SB_CNTL(sbcntl_sbf_rbmon) <= 'H'; + else + SB_CNTL(sbcntl_sbf_rbmon) <= 'L'; + end if; + + when ".sinit" => -- .sinit + readgen_ea(iline, iaddr, 8); + readgen_ea(iline, idata, 8); + SB_ADDR <= iaddr; + SB_DATA <= idata; + SB_VAL <= 'H'; + wait for 0 ns; + SB_VAL <= 'L'; + SB_ADDR <= (others=>'L'); + SB_DATA <= (others=>'L'); + wait for 0 ns; + + when others => -- bad command + write(oline, string'("?? unknown command: ")); + write(oline, dname); + writeline(output, oline); + report "aborting" severity failure; + end case; + else + report "failed to find command" severity failure; + end if; + + testempty_ea(iline); + + end loop; -- file_loop: + + wait; -- halt process here + + end process proc_conf; + + proc_stim: process + variable t_lastclksys : time := 0 ns; + variable clksys_period : time := 0 ns; + variable icycle : integer := 0; + variable irxint : integer := 0; + variable irxslv : slv24 := (others=>'0'); + variable ibit : integer := 0; + variable oline : line; + variable r_sb_cntl : slv16 := (others=>'Z'); + variable iaddr : slv8 := (others=>'0'); + variable idata : slv16 := (others=>'0'); + begin + + -- just wait for 10 CLKSYS cycles + for i in 1 to 10 loop + wait until CLKSYS'event and CLKSYS='1'; + clksys_period := now - t_lastclksys; + t_lastclksys := now; + end loop; -- i + + stim_loop: loop + + wait until CLKSYS'event and CLKSYS='1'; + clksys_period := now - t_lastclksys; + t_lastclksys := now; + + wait for clksys_period-SETUP_TIME; + + SB_ADDR <= (others=>'Z'); + SB_DATA <= (others=>'Z'); + + icycle := conv_integer(unsigned(SB_CLKCYCLE)); + RX_VAL <= '0'; + + if RX_HOLD = '0' then + irxint := rlink_cext_getbyte(icycle); + if irxint >= 0 then + if irxint <= 16#ff# then -- normal data byte + RX_DATA <= conv_std_logic_vector(irxint, 8); + RX_VAL <= '1'; + elsif irxint >= 16#1000000# then -- out-of-band message + irxslv := conv_std_logic_vector(irxint, 24); + iaddr := irxslv(23 downto 16); + idata := irxslv(15 downto 0); + writetimestamp(oline, SB_CLKCYCLE, ": OOB-MSG"); + write(oline, irxslv(23 downto 16), right, 9); + write(oline, irxslv(15 downto 8), right, 9); + write(oline, irxslv( 7 downto 0), right, 9); + write(oline, string'(" : ")); + writeoct(oline, iaddr, right, 3); + writeoct(oline, idata, right, 7); + writeline(output, oline); + if unsigned(iaddr) = 0 then + ibit := conv_integer(unsigned(idata(15 downto 8))); + r_sb_cntl(ibit) := idata(0); + else + SB_ADDR <= iaddr; + SB_DATA <= idata; + SB_VAL <= '1'; + wait for 0 ns; + SB_VAL <= 'Z'; + wait for 0 ns; + end if; + end if; + elsif irxint = -1 then -- end-of-file seen + exit stim_loop; + else + report "rlink_cext_getbyte error: " & integer'image(-irxint) + severity failure; + end if; + end if; + + SB_CNTL <= r_sb_cntl; + + end loop; + + -- just wait for 50 CLKSYS cycles + for i in 1 to 50 loop + wait until CLKSYS'event and CLKSYS='1'; + end loop; -- i + CLK_STOP <= '1'; + + writetimestamp(oline, SB_CLKCYCLE, ": DONE "); + writeline(output, oline); + + wait; -- suspend proc_stim forever + -- clock is stopped, sim will end + + end process proc_stim; + + proc_moni: process + variable itxdata : integer := 0; + variable itxrc : integer := 0; + variable oline : line; + begin + + loop + wait until CLKSYS'event and CLKSYS='1'; + wait for C2OUT_TIME; + if TX_ENA = '1' then + itxdata := conv_integer(unsigned(TX_DATA)); + itxrc := rlink_cext_putbyte(itxdata); + assert itxrc=0 + report "rlink_cext_putbyte error: " & integer'image(itxrc) + severity failure; + end if; + + end loop; + + end process proc_moni; + +end sim; Index: rtl/vlib/rlink/tb/tbd_rlink_direct.vhd =================================================================== --- rtl/vlib/rlink/tb/tbd_rlink_direct.vhd (nonexistent) +++ rtl/vlib/rlink/tb/tbd_rlink_direct.vhd (revision 9) @@ -0,0 +1,133 @@ +-- $Id: tbd_rlink_direct.vhd 348 2010-12-26 15:23:44Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tbd_rlink_direct - syn +-- Description: Wrapper for rlink_core to avoid records. It has a port +-- interface which will not be modified by xst synthesis +-- (no records, no generic port). +-- +-- Dependencies: rlink_core +-- +-- To test: rlink_core +-- +-- Target Devices: generic +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2007-11-24 92 8.1.03 I27 xc3s1000-4 143 309 0 166 s 7.64 +-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 148 320 0 - t 8.34 +-- 2007-10-27 92 9.1 J30 xc3s1000-4 148 315 0 - t 8.34 +-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 153 302 0 162 s 7.65 +-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 138 306 0 - s 7.64 +-- +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-25 348 3.0.2 drop RL_FLUSH, add RL_MONI for rlink_core +-- 2010-12-24 347 3.0.1 rename: CP_*->RL->* +-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol; +-- 2010-05-02 287 2.2.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM +-- drop RP_IINT signal from interfaces +-- 2010-04-03 274 2.2 add CP_FLUSH for rri_core, add CE_USEC +-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage +-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface +-- 2007-11-25 98 1.1 added RP_IINT support; use entity rather arch +-- name to switch core/serport +-- 2007-07-02 63 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.slvtypes.all; +use work.rblib.all; +use work.rlinklib.all; + +entity tbd_rlink_direct is -- rlink_core only tb design + -- generic: ATOWIDTH=5; ITOWIDTH=6 + -- implements tbd_rlink_gen + port ( + CLK : in slbit; -- clock + CE_INT : in slbit; -- rlink ito time unit clock enable + CE_USEC : in slbit; -- 1 usec clock enable + RESET : in slbit; -- reset + RL_DI : in slv9; -- rlink: data in + RL_ENA : in slbit; -- rlink: data enable + RL_BUSY : out slbit; -- rlink: data busy + RL_DO : out slv9; -- rlink: data out + RL_VAL : out slbit; -- rlink: data valid + RL_HOLD : in slbit; -- rlink: data hold + RB_MREQ_aval : out slbit; -- rbus: request - aval + RB_MREQ_re : out slbit; -- rbus: request - re + RB_MREQ_we : out slbit; -- rbus: request - we + RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll + RB_MREQ_addr : out slv8; -- rbus: request - addr + RB_MREQ_din : out slv16; -- rbus: request - din + RB_SRES_ack : in slbit; -- rbus: response - ack + RB_SRES_busy : in slbit; -- rbus: response - busy + RB_SRES_err : in slbit; -- rbus: response - err + RB_SRES_dout : in slv16; -- rbus: response - dout + RB_LAM : in slv16; -- rbus: look at me + RB_STAT : in slv3; -- rbus: status flags + TXRXACT : out slbit -- txrx active flag + ); +end entity tbd_rlink_direct; + + +architecture syn of tbd_rlink_direct is + + signal RL_MONI : rl_moni_type := rl_moni_init; + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + +begin + + RB_MREQ_aval <= RB_MREQ.aval; + RB_MREQ_re <= RB_MREQ.re; + RB_MREQ_we <= RB_MREQ.we; + RB_MREQ_initt<= RB_MREQ.init; + RB_MREQ_addr <= RB_MREQ.addr; + RB_MREQ_din <= RB_MREQ.din; + + RB_SRES.ack <= RB_SRES_ack; + RB_SRES.busy <= RB_SRES_busy; + RB_SRES.err <= RB_SRES_err; + RB_SRES.dout <= RB_SRES_dout; + + UUT : rlink_core + generic map ( + ATOWIDTH => 5, + ITOWIDTH => 6) + port map ( + CLK => CLK, + CE_INT => CE_INT, + RESET => RESET, + RL_DI => RL_DI, + RL_ENA => RL_ENA, + RL_BUSY => RL_BUSY, + RL_DO => RL_DO, + RL_VAL => RL_VAL, + RL_HOLD => RL_HOLD, + RL_MONI => RL_MONI, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT + ); + + TXRXACT <= '0'; + +end syn; Index: rtl/vlib/rlink/tb/rlink_cext.c =================================================================== --- rtl/vlib/rlink/tb/rlink_cext.c (nonexistent) +++ rtl/vlib/rlink/tb/rlink_cext.c (revision 9) @@ -0,0 +1,218 @@ +/* $Id: rlink_cext.c 351 2010-12-30 21:50:54Z mueller $ + * + * Copyright 2007-2010 by Walter F.J. Mueller + * + * This program is free software; you may redistribute and/or modify it under + * the terms of the GNU General Public License as published by the Free + * Software Foundation, either version 2, or at your option any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for complete details. + * + * Revision History: + * Date Rev Vers Comment + * 2010-12-29 351 1.3 rename cext_rriext -> rlink_cext; rename functions + * cext_* -> rlink_cext_* and fifo file names + * tb_cext_* -> rlink_cext_* + * 2007-11-18 96 1.2 add 'read before write' logic to avoid deadlocks + * under cygwin broken fifo (size=1 !) implementation + * 2007-10-19 90 1.1 add trace option, controlled by setting an + * the environment variable CEXT_RRIEXT_TRACE=1 + * 2007-09-23 84 1.0 Initial version + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CPREF 0x80 +#define CESC (CPREF|0x0f) +#define QRBUFSIZE 1024 + +static int fd_rx = -1; +static int fd_tx = -1; + +static int io_trace = 0; + +static char qr_buf[QRBUFSIZE]; +static int qr_pr = 0; +static int qr_pw = 0; +static int qr_nb = 0; +static int qr_eof = 0; +static int qr_err = EAGAIN; + +/* returns: + * <0 if error + * >=0 <=0xff normal data + * == 0x100 idle + * 0x1aahhll if side band message seen + * + */ + +/* returns + 0 if EGAIN or + */ + +static void rlink_cext_dotrace(const char *text, int dat) +{ + int i; + int mask = 0x80; + printf("rlink_cext-I: %s ", text); + for (i=0; i<8; i++) { + printf("%c", (dat&mask)?'1':'0' ); + mask >>= 1; + } + printf("\n"); +} + +static void rlink_cext_doread() +{ + char buf[1]; + ssize_t nbyte; + nbyte = read(fd_rx, buf, 1); + if (nbyte < 0) { + qr_err = errno; + } else if (nbyte == 0) { + qr_err = EAGAIN; + qr_eof = 1; + } else { + qr_err = EAGAIN; + if (qr_nb < QRBUFSIZE) { + if (io_trace) rlink_cext_dotrace("rcv8", (unsigned char) buf[0]); + qr_buf[qr_pw++] = buf[0]; + if (qr_pw >= QRBUFSIZE) qr_pw = 0; + qr_nb += 1; + } else { + printf("Buffer overflow\n"); /* FIXME: better error handling */ + } + } +} + +int rlink_cext_getbyte(int clk) +{ + char buf[1]; + ssize_t nbyte; + int irc; + int tdat; + char* env_val; + + static int odat; + static int nidle = 0; + static int ncesc = 0; + static int nside = -1; + + if (fd_rx < 0) { /* fifo's not yet opened */ + fd_rx = open("rlink_cext_fifo_rx", O_RDONLY|O_NONBLOCK); + if (fd_rx <= 0) { + perror("rlink_cext-E: failed to open rlink_cext_fifo_rx"); + return -2; + } + printf("rlink_cext-I: connected to rlink_cext_fifo_rx\n"); + fd_tx = open("rlink_cext_fifo_tx", O_WRONLY); + if (fd_tx <= 0) { + perror("rlink_cext-E: failed to open rlink_cext_fifo_tx"); + return -2; + } + printf("rlink_cext-I: connected to rlink_cext_fifo_tx\n"); + nidle = 0; + ncesc = 0; + nside = -1; + + io_trace = 0; + env_val = getenv("RLINK_CEXT_TRACE"); + if (env_val && strcmp(env_val, "1") == 0) { + io_trace = 1; + } + + } + + rlink_cext_doread(); + + if (qr_nb == 0) { /* no character to be processed */ + if (qr_eof != 0) { /* EOF seen */ + if (ncesc >= 2) { /* two+ CESC seen ? */ + printf("rlink_cext-I: seen EOF, wait for reconnect\n"); + close(fd_rx); + close(fd_tx); + fd_rx = -1; + fd_tx = -1; + usleep(500000); /* wait 0.5 sec */ + return 0x100; /* return idle, will reconnect */ + } + + printf("rlink_cext-I: seen EOF, schedule clock stop and exit\n"); + return -1; /* signal EOF seen */ + } else if (qr_err == EAGAIN) { /* nothing read, return idle */ + if (nidle < 8 || (nidle%1024)==0) { + irc = sched_yield(); + if (irc < 0) perror("rlink_cext-W: sched_yield failed"); + } + nidle += 1; + return 0x100; + } else { /* must be a read error */ + errno = qr_err; + perror("rlink_cext-E: read error on rlink_cext_fifo_rx"); + return -3; + } + } + + nidle = 0; + tdat = (unsigned char) qr_buf[qr_pr++]; + if (qr_pr >= QRBUFSIZE) qr_pr = 0; + qr_nb -= 1; + + if (tdat == CESC) { + ncesc += 1; + if (ncesc == 2) nside = 0; + } else { + ncesc = 0; + } + + switch (nside) { + case -1: /* normal data */ + return tdat; + case 0: /* 2nd CESC, return it */ + nside += 1; + return tdat; + case 1: /* get ADDR byte */ + nside += 1; + odat = 0x1000000 | (tdat<<16); + return 0x100; + case 2: /* get DL byte */ + nside += 1; + odat |= tdat; + return 0x100; + case 3: /* get DH byte */ + nside = -1; + odat |= tdat<<8; + return odat; + } +} + +int rlink_cext_putbyte(int dat) +{ + char buf[1]; + ssize_t nbyte; + + rlink_cext_doread(); + + if (io_trace) rlink_cext_dotrace("snd8", dat); + + buf[0] = (unsigned char) dat; + nbyte = write(fd_tx, buf, 1); + + if (nbyte < 0) { + perror("rlink_cext-E: write error on rlink_cext_fifo_tx"); + return -3; + } + + return 0; +} Index: rtl/vlib/rlink/tb/tb_rlink.vhd =================================================================== --- rtl/vlib/rlink/tb/tb_rlink.vhd (nonexistent) +++ rtl/vlib/rlink/tb/tb_rlink.vhd (revision 9) @@ -0,0 +1,674 @@ +-- $Id: tb_rlink.vhd 351 2010-12-30 21:50:54Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_rlink - sim +-- Description: Test bench for rlink_core +-- +-- Dependencies: simlib/simclk +-- genlib/clkdivce +-- rbus/tbd_tester +-- rbus/rb_mon +-- rlink/rlink_mon +-- tbd_rlink_gen [UUT] +-- +-- To test: rlink_core (via tbd_rlink_direct) +-- rlink_base (via tbd_rlink_serport) +-- rlink_serport (via tbd_rlink_serport) +-- +-- Target Devices: generic +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-29 351 3.0.6 use new rbd_tester addr 111100xx (from 111101xx) +-- 2010-12-26 348 3.0.5 use simbus to export clkcycle (for tbd_..serport) +-- 2010-12-23 347 3.0.4 use rb_mon, rlink_mon directly; rename CP_*->RL_* +-- 2010-12-22 346 3.0.3 add .rlmon and .rbmon commands +-- 2010-12-21 345 3.0.2 rename commands .[rt]x... to [rt]x...; +-- add .[rt]x(idle|attn) cmds; remove 'bbbbbbbb' cmd +-- 2010-12-12 344 3.0.1 add .attn again; add .txbad, .txoof; ren oob->oof +-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol; +-- use rbd_tester instead of sim target; +-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining +-- 2010-06-03 299 2.2.2 new init encoding (WE=0/1 int/ext);use sv_ prefix +-- for shared variables +-- 2010-05-02 287 2.2.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM +-- drop RP_IINT signal from interfaces +-- 2010-04-03 274 2.2 add CE_USEC in tbd_rri_gen interface +-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage +-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface +-- 2008-03-24 129 1.1.2 CLK_CYCLE now 31 bits +-- 2008-01-20 112 1.1.1 rename clkgen->clkdivce +-- 2007-11-24 98 1.1 add RP_IINT support, add checkmiss_tx to test +-- for missing responses +-- 2007-10-26 92 1.0.2 add DONE timestamp at end of execution +-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned +-- 2007-09-09 81 1.0 Initial version +------------------------------------------------------------------------------ +-- command set: +-- .reset assert RESET for 1 clk +-- .rlmon ien enable rlink monitor +-- .rbmon ien enable rbus monitor +-- .wait n wait n clks +-- .iowt n wait n clks for rlink i/o; auto-extend +-- .attn dat(16) pulse attn lines with dat +-- txsop send +-- txeop send +-- txnak send +-- txidle send +-- txattn send +-- tx8 dat(8) send 8 bit value +-- tx16 dat(16) send 16 bit value +-- txcrc send crc +-- txbad send bad (inverted) crc +-- txc cmd(8) send cmd - crc +-- txca cmd(8) addr(8) send cmd - addr - crc +-- txcad cmd(8) addr(8) dat(16) send cmd - addr - dl dh - crc +-- txcac cmd(8) addr(8) cnt(8) send cmd - addr - cnt - crc +-- txoof dat(9) send out-of-frame symbol +-- rxsop reset rx list; expect sop +-- rxeop expect +-- rxnak expect +-- rxidle expect +-- rxattn expect +-- rx8 dat(8) expect 8 bit value +-- rx16 dat(16) expect 16 bit value +-- rxcrc expect crc +-- rxcs cmd(8) stat(8) expect cmd - stat - crc +-- rxcds cmd(8) dat(16) stat(8) expect cmd - dl dh - stat - crc +-- rxccd cmd(8) ccmd(8) dat(16) stat(8) expect cmd - ccmd - dl dh - stat - crc +-- rxoof dat(9) expect out-of-frame symbol +-- +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.comlib.all; +use work.rblib.all; +use work.rbdlib.all; +use work.rlinklib.all; +use work.simlib.all; +use work.simbus.all; + +entity tb_rlink is +end tb_rlink; + +architecture sim of tb_rlink is + + signal CLK : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + signal RESET : slbit := '0'; + signal RL_DI : slv9 := (others=>'0'); + signal RL_ENA : slbit := '0'; + signal RL_BUSY : slbit := '0'; + signal RL_DO : slv9 := (others=>'0'); + signal RL_VAL : slbit := '0'; + signal RL_HOLD : slbit := '0'; + signal RB_MREQ_aval : slbit := '0'; + signal RB_MREQ_re : slbit := '0'; + signal RB_MREQ_we : slbit := '0'; + signal RB_MREQ_initt: slbit := '0'; + signal RB_MREQ_addr : slv8 := (others=>'0'); + signal RB_MREQ_din : slv16 := (others=>'0'); + signal RB_SRES_ack : slbit := '0'; + signal RB_SRES_busy : slbit := '0'; + signal RB_SRES_err : slbit := '0'; + signal RB_SRES_dout : slv16 := (others=>'0'); + signal RB_LAM_TBENCH : slv16 := (others=>'0'); + signal RB_LAM_TESTER : slv16 := (others=>'0'); + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv3 := (others=>'0'); + signal TXRXACT : slbit := '0'; + + signal RLMON_EN : slbit := '0'; + signal RBMON_EN : slbit := '0'; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + + signal CLK_STOP : slbit := '0'; + + constant slv9_zero : slv9 := (others=>'0'); + constant slv16_zero : slv16 := (others=>'0'); + + type slv9_array_type is array (0 to 255) of slv9; + type slv16_array_type is array (0 to 255) of slv16; + + shared variable sv_rxlist : slv9_array_type := (others=>slv9_zero); + shared variable sv_nrxlist : natural := 0; + shared variable sv_rxind : natural := 0; + + constant clock_period : time := 20 ns; + constant clock_offset : time := 200 ns; + constant setup_time : time := 5 ns; + constant c2out_time : time := 10 ns; + +component tbd_rlink_gen is -- rlink, generic tb design interface + port ( + CLK : in slbit; -- clock + CE_INT : in slbit; -- rlink ito time unit clock enable + CE_USEC : in slbit; -- 1 usec clock enable + RESET : in slbit; -- reset + RL_DI : in slv9; -- rlink: data in + RL_ENA : in slbit; -- rlink: data enable + RL_BUSY : out slbit; -- rlink: data busy + RL_DO : out slv9; -- rlink: data out + RL_VAL : out slbit; -- rlink: data valid + RL_HOLD : in slbit; -- rlink: data hold + RB_MREQ_aval : out slbit; -- rbus: request - aval + RB_MREQ_re : out slbit; -- rbus: request - re + RB_MREQ_we : out slbit; -- rbus: request - we + RB_MREQ_initt: out slbit; -- rbus: request - init; avoid name coll + RB_MREQ_addr : out slv8; -- rbus: request - addr + RB_MREQ_din : out slv16; -- rbus: request - din + RB_SRES_ack : in slbit; -- rbus: response - ack + RB_SRES_busy : in slbit; -- rbus: response - busy + RB_SRES_err : in slbit; -- rbus: response - err + RB_SRES_dout : in slv16; -- rbus: response - dout + RB_LAM : in slv16; -- rbus: look at me + RB_STAT : in slv3; -- rbus: status flags + TXRXACT : out slbit -- txrx active flag + ); +end component; + +begin + + SYSCLK : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK, + CLK_CYCLE => SB_CLKCYCLE, + CLK_STOP => CLK_STOP + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 6, + USECDIV => 4, + MSECDIV => 5 + ) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + RB_MREQ.aval <= RB_MREQ_aval; + RB_MREQ.re <= RB_MREQ_re; + RB_MREQ.we <= RB_MREQ_we; + RB_MREQ.init <= RB_MREQ_initt; + RB_MREQ.addr <= RB_MREQ_addr; + RB_MREQ.din <= RB_MREQ_din; + + RB_SRES_ack <= RB_SRES.ack; + RB_SRES_busy <= RB_SRES.busy; + RB_SRES_err <= RB_SRES.err; + RB_SRES_dout <= RB_SRES.dout; + + RBTEST : rbd_tester + generic map ( + RB_ADDR => conv_std_logic_vector(2#11110000#,8)) + port map ( + CLK => CLK, + RESET => '0', + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM_TESTER, + RB_STAT => RB_STAT + ); + + RB_LAM <= RB_LAM_TESTER or RB_LAM_TBENCH; + + RLMON : rlink_mon + generic map ( + DWIDTH => RL_DI'length) + port map ( + CLK => CLK, + CLK_CYCLE => SB_CLKCYCLE, + ENA => RLMON_EN, + RL_DI => RL_DI, + RL_ENA => RL_ENA, + RL_BUSY => RL_BUSY, + RL_DO => RL_DO, + RL_VAL => RL_VAL, + RL_HOLD => RL_HOLD + ); + + RBMON : rb_mon + generic map ( + DBASE => 2) + port map ( + CLK => CLK, + CLK_CYCLE => SB_CLKCYCLE, + ENA => RBMON_EN, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT + ); + + UUT : tbd_rlink_gen + port map ( + CLK => CLK, + CE_INT => CE_MSEC, + CE_USEC => CE_USEC, + RESET => RESET, + RL_DI => RL_DI, + RL_ENA => RL_ENA, + RL_BUSY => RL_BUSY, + RL_DO => RL_DO, + RL_VAL => RL_VAL, + RL_HOLD => RL_HOLD, + RB_MREQ_aval => RB_MREQ_aval, + RB_MREQ_re => RB_MREQ_re, + RB_MREQ_we => RB_MREQ_we, + RB_MREQ_initt=> RB_MREQ_initt, + RB_MREQ_addr => RB_MREQ_addr, + RB_MREQ_din => RB_MREQ_din, + RB_SRES_ack => RB_SRES_ack, + RB_SRES_busy => RB_SRES_busy, + RB_SRES_err => RB_SRES_err, + RB_SRES_dout => RB_SRES_dout, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + TXRXACT => TXRXACT + ); + + proc_stim: process + file fstim : text open read_mode is "tb_rlink_stim"; + variable iline : line; + variable oline : line; + variable ien : slbit := '0'; + variable icmd : slv8 := (others=>'0'); + variable iaddr : slv8 := (others=>'0'); + variable icnt : slv8 := (others=>'0'); + variable istat : slv3 := (others=>'0'); + variable iattn : slv16 := (others=>'0'); + variable idata : slv16 := (others=>'0'); + variable ioof : slv9 := (others=>'0'); + variable ok : boolean; + variable dname : string(1 to 6) := (others=>' '); + variable idelta : integer := 0; + variable iowait : integer := 0; + variable txcrc,rxcrc : slv8 := (others=>'0'); + variable txlist : slv9_array_type := (others=>slv9_zero); + variable ntxlist : natural := 0; + + procedure do_tx8 (data : inout slv8) is + begin + txlist(ntxlist) := '0' & data; + ntxlist := ntxlist + 1; + crc8_update_tbl(txcrc, data); + end procedure do_tx8; + + procedure do_tx16 (data : inout slv16) is + begin + do_tx8(data( 7 downto 0)); + do_tx8(data(15 downto 8)); + end procedure do_tx16; + + procedure do_rx8 (data : inout slv8) is + begin + sv_rxlist(sv_nrxlist) := '0' & data; + sv_nrxlist := sv_nrxlist + 1; + crc8_update_tbl(rxcrc, data); + end procedure do_rx8; + + procedure do_rx16 (data : inout slv16) is + begin + do_rx8(data( 7 downto 0)); + do_rx8(data(15 downto 8)); + end procedure do_rx16; + + procedure checkmiss_rx is + begin + if sv_rxind < sv_nrxlist then + for i in sv_rxind to sv_nrxlist-1 loop + writetimestamp(oline, SB_CLKCYCLE, ": moni "); + write(oline, string'(" FAIL MISSING DATA=")); + write(oline, sv_rxlist(i)(8)); + write(oline, string'(" ")); + write(oline, sv_rxlist(i)(7 downto 0)); + writeline(output, oline); + end loop; + + end if; + end procedure checkmiss_rx; + + begin + + wait for clock_offset - setup_time; + + file_loop: while not endfile(fstim) loop + + readline (fstim, iline); + + readcomment(iline, ok); + next file_loop when ok; + + readword(iline, dname, ok); + + if ok then + case dname is + when ".reset" => -- .reset + write(oline, string'(".reset")); + writeline(output, oline); + RESET <= '1'; + wait for clock_period; + RESET <= '0'; + wait for 9*clock_period; + + when ".rlmon" => -- .rlmon + read_ea(iline, ien); + RLMON_EN <= ien; + wait for 2*clock_period; -- wait for monitor to start + + when ".rbmon" => -- .rbmon + read_ea(iline, ien); + RBMON_EN <= ien; + wait for 2*clock_period; -- wait for monitor to start + + when ".wait " => -- .wait + read_ea(iline, idelta); + wait for idelta*clock_period; + + when ".iowt " => -- .iowt + read_ea(iline, iowait); + idelta := iowait; + while idelta > 0 loop -- until time has expired + if TXRXACT = '1' then -- if any io activity + idelta := iowait; -- restart timer + else + idelta := idelta - 1; -- otherwise count down time + end if; + wait for clock_period; + end loop; + + when ".attn " => -- .attn + read_ea(iline, iattn); + RB_LAM_TBENCH <= iattn; -- pulse attn lines + wait for clock_period; -- for 1 clock + RB_LAM_TBENCH <= (others=>'0'); + + when "txsop " => -- txsop send sop + txlist(0) := c_rlink_dat_sop; + ntxlist := 1; + txcrc := (others=>'0'); + when "txeop " => -- txeop send eop + txlist(0) := c_rlink_dat_eop; + ntxlist := 1; + txcrc := (others=>'0'); + + when "txnak " => -- txnak send nak + txlist(0) := c_rlink_dat_nak; + ntxlist := 1; + txcrc := (others=>'0'); + + when "txidle" => -- txidle send idle + txlist(0) := c_rlink_dat_idle; + ntxlist := 1; + when "txattn" => -- txattn send attn + txlist(0) := c_rlink_dat_attn; + ntxlist := 1; + + when "tx8 " => -- tx8 send 8 bit value + read_ea(iline, iaddr); + ntxlist := 0; + do_tx8(iaddr); + when "tx16 " => -- tx16 send 16 bit value + read_ea(iline, idata); + ntxlist := 0; + do_tx16(idata); + + when "txcrc " => -- txcrc send crc + txlist(0) := '0' & txcrc; + ntxlist := 1; + + when "txbad " => -- txbad send bad crc + txlist(0) := '0' & (not txcrc); + ntxlist := 1; + + when "txc " => -- txc send: cmd crc + read_ea(iline, icmd); + ntxlist := 0; + do_tx8(icmd); + txlist(ntxlist) := '0' & txcrc; + ntxlist := ntxlist + 1; + + when "txca " => -- txc send: cmd addr crc + read_ea(iline, icmd); + read_ea(iline, iaddr); + ntxlist := 0; + do_tx8(icmd); + do_tx8(iaddr); + txlist(ntxlist) := '0' & txcrc; + ntxlist := ntxlist + 1; + + when "txcad " => -- txc send: cmd addr data crc + read_ea(iline, icmd); + read_ea(iline, iaddr); + read_ea(iline, idata); + ntxlist := 0; + do_tx8(icmd); + do_tx8(iaddr); + do_tx16(idata); + txlist(ntxlist) := '0' & txcrc; + ntxlist := ntxlist + 1; + + when "txcac " => -- txc send: cmd addr cnt crc + read_ea(iline, icmd); + read_ea(iline, iaddr); + read_ea(iline, icnt); + ntxlist := 0; + do_tx8(icmd); + do_tx8(iaddr); + do_tx8(icnt); + txlist(ntxlist) := '0' & txcrc; + ntxlist := ntxlist + 1; + + when "txoof " => -- txoof send out-of-frame symbol + read_ea(iline, txlist(0)); + ntxlist := 1; + + when "rxsop " => -- rxsop expect sop + checkmiss_rx; + sv_rxlist(0) := c_rlink_dat_sop; + sv_nrxlist := 1; + sv_rxind := 0; + rxcrc := (others=>'0'); + when "rxeop " => -- rxeop expect eop + sv_rxlist(sv_nrxlist) := c_rlink_dat_eop; + sv_nrxlist := sv_nrxlist + 1; + + when "rxnak " => -- rxnak expect nak + sv_rxlist(sv_nrxlist) := c_rlink_dat_nak; + sv_nrxlist := sv_nrxlist + 1; + when "rxidle" => -- rxidle expect idle + sv_rxlist(sv_nrxlist) := c_rlink_dat_idle; + sv_nrxlist := sv_nrxlist + 1; + when "rxattn" => -- rxattn expect attn + sv_rxlist(sv_nrxlist) := c_rlink_dat_attn; + sv_nrxlist := sv_nrxlist + 1; + + when "rx8 " => -- rx8 expect 8 bit value + read_ea(iline, iaddr); + do_rx8(iaddr); + when "rx16 " => -- rx16 expect 16 bit value + read_ea(iline, idata); + do_rx16(idata); + + when "rxcrc " => -- rxcrc expect crc + sv_rxlist(sv_nrxlist) := '0' & rxcrc; + sv_nrxlist := sv_nrxlist+1; + + when "rxcs " => -- rxcs expect: cmd stat crc + read_ea(iline, icmd); + read_ea(iline, iaddr); + do_rx8(icmd); + do_rx8(iaddr); + sv_rxlist(sv_nrxlist) := '0' & rxcrc; + sv_nrxlist := sv_nrxlist + 1; + + when "rxcds " => -- rxcsd expect: cmd data stat crc + read_ea(iline, icmd); + read_ea(iline, idata); + read_ea(iline, iaddr); + do_rx8(icmd); + do_rx16(idata); + do_rx8(iaddr); + sv_rxlist(sv_nrxlist) := '0' & rxcrc; + sv_nrxlist := sv_nrxlist + 1; + + when "rxccd " => -- rxccd expect: cmd ccmd dat stat crc + read_ea(iline, icmd); + read_ea(iline, icnt); + read_ea(iline, idata); + read_ea(iline, iaddr); + do_rx8(icmd); + do_rx8(icnt); + do_rx16(idata); + do_rx8(iaddr); + sv_rxlist(sv_nrxlist) := '0' & rxcrc; + sv_nrxlist := sv_nrxlist + 1; + + when "rxoof " => -- rxoof expect: out-of-frame symbol + read_ea(iline, ioof); + sv_rxlist(sv_nrxlist) := ioof; + sv_nrxlist := sv_nrxlist + 1; + + when others => -- bad command + write(oline, string'("?? unknown command: ")); + write(oline, dname); + writeline(output, oline); + report "aborting" severity failure; + end case; + + else + report "failed to find command" severity failure; + end if; + + next file_loop when ntxlist=0; + + for i in 0 to ntxlist-1 loop + + RL_DI <= txlist(i); + RL_ENA <= '1'; + + writetimestamp(oline, SB_CLKCYCLE, ": stim"); + write(oline, txlist(i)(8), right, 3); + write(oline, txlist(i)(7 downto 0), right, 9); + if txlist(i)(8) = '1' then + case txlist(i) is + when c_rlink_dat_idle => + write(oline, string'(" (idle)")); + when c_rlink_dat_sop => + write(oline, string'(" (sop) ")); + when c_rlink_dat_eop => + write(oline, string'(" (eop) ")); + when c_rlink_dat_nak => + write(oline, string'(" (nak) ")); + when c_rlink_dat_attn => + write(oline, string'(" (attn)")); + when others => + write(oline, string'(" (????)")); + end case; + end if; + writeline(output, oline); + + wait for clock_period; + while RL_BUSY = '1' loop + wait for clock_period; + end loop; + RL_ENA <= '0'; + + end loop; -- i + + ntxlist := 0; + + end loop; -- file fstim + + wait for 50*clock_period; + + checkmiss_rx; + writetimestamp(oline, SB_CLKCYCLE, ": DONE "); + writeline(output, oline); + + CLK_STOP <= '1'; + + wait; -- suspend proc_stim forever + -- clock is stopped, sim will end + + end process proc_stim; + + + proc_moni: process + variable oline : line; + begin + + loop + wait until CLK'event and CLK='1'; + wait for c2out_time; + + if RL_VAL = '1' then + writetimestamp(oline, SB_CLKCYCLE, ": moni"); + write(oline, RL_DO(8), right, 3); + write(oline, RL_DO(7 downto 0), right, 9); + if RL_DO(8) = '1' then + case RL_DO is + when c_rlink_dat_idle => + write(oline, string'(" (idle)")); + when c_rlink_dat_sop => + write(oline, string'(" (sop) ")); + when c_rlink_dat_eop => + write(oline, string'(" (eop) ")); + when c_rlink_dat_nak => + write(oline, string'(" (nak) ")); + when c_rlink_dat_attn => + write(oline, string'(" (attn)")); + when others => + write(oline, string'(" (????)")); + end case; + end if; + if sv_nrxlist > 0 then + write(oline, string'(" CHECK")); + if sv_rxind < sv_nrxlist then + if RL_DO = sv_rxlist(sv_rxind) then + write(oline, string'(" OK")); + else + write(oline, string'(" FAIL, exp=")); + write(oline, sv_rxlist(sv_rxind)(8), right, 2); + write(oline, sv_rxlist(sv_rxind)(7 downto 0), right, 9); + end if; + sv_rxind := sv_rxind + 1; + else + write(oline, string'(" FAIL, UNEXPECTED")); + end if; + end if; + writeline(output, oline); + end if; + + end loop; + + end process proc_moni; + +end sim; Index: rtl/vlib/rlink/tb/tb_rlink_serport.vbom =================================================================== --- rtl/vlib/rlink/tb/tb_rlink_serport.vbom (nonexistent) +++ rtl/vlib/rlink/tb/tb_rlink_serport.vbom (revision 9) @@ -0,0 +1,6 @@ +# configure tb_rlink with tbd_rlink_serport wrapper; +# use vhdl configure file (tb_rlink_serport.vhd) to allow +# that all configurations will co-exist in work library +tbd_rlink_gen = tbd_rlink_serport.vbom +tb_rlink.vbom +tb_rlink_serport.vhd Index: rtl/vlib/rlink/tb/tb_rlink_serport_stim.dat =================================================================== --- rtl/vlib/rlink/tb/tb_rlink_serport_stim.dat (nonexistent) +++ rtl/vlib/rlink/tb/tb_rlink_serport_stim.dat (revision 9) @@ -0,0 +1,312 @@ +# $Id: tb_rlink_serport_stim.dat 351 2010-12-30 21:50:54Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2010-12-29 351 1.0.1 use new rbd_tester addr 111100xx (from 111101xx) +# 2010-12-26 348 1.0 Initial version (Test 3 from tb_rlink_stim.dat) +# +#--------------------------------------- +# rbus address mapping +# 11110000 rbd_tester cntl +# 11110001 rbd_tester data +# 11110010 rbd_tester fifo +# 11110011 rbd_tester attn +# +.rlmon 0 +.rbmon 1 +# +C ----------------------------------------------------------------------------- +C Test 1: wreg(data) +C data := 0011001111001100 +C ==> shows that rlink can write a register +C +C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop +C rx: sop - cmd(010) stat crc - eop +# +rxsop +rxcs 00001010 00000000 +rxeop +# +txsop +txcad 00001010 11110001 0011001111001100 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 2: rreg(data) +C data -> 0011001111001100 +C ==> shows that rlink can read back a register +C +C rreg: tx: sop - cmd(00001,000) addr(0001) ccrc - eop +C rx: sop - cmd(000) dl dh stat crc - eop +# +rxsop +rxcds 00001000 0011001111001100 00000000 +rxeop +# +txsop +txca 00001000 11110001 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 3: Test comma escapes +C Assumes CPREF=1000, covers 11111111:10000111 and 10001101:10010000 +C +C data := 1000000011111111 ,... +C data -> 1000000011111111 +C data := 1000001010000001 , +C data -> 1000001010000001 +C data := 1000010010000011 , +C data -> 1000010010000011 +C data := 1000011010000101 6,5 +C data -> 1000011010000101 +C data := 1000100010000111 8,7 +C data -> 1000100010000111 +C data := 1000111010001101 14,13 +C data -> 1000111010001101 +C data := 1001000010001111 .., +C data -> 1001000010001111 +C +C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(00010,000) addr(0001) ccrc +C wreg: tx: - cmd(00011,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(00100,000) addr(0001) ccrc +C wreg: tx: - cmd(00101,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(00110,000) addr(0001) ccrc +C wreg: tx: - cmd(00111,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(01000,000) addr(0001) ccrc +C wreg: tx: - cmd(01001,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(01010,000) addr(0001) ccrc +C wreg: tx: - cmd(01011,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(01100,000) addr(0001) ccrc +C wreg: tx: - cmd(01101,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(01110,000) addr(0001) ccrc +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - eop +# +rxsop +rxcs 00001010 00000000 +rxcds 00010000 1000000011111111 00000000 +rxcs 00011010 00000000 +rxcds 00100000 1000001010000001 00000000 +rxcs 00101010 00000000 +rxcds 00110000 1000010010000011 00000000 +rxcs 00111010 00000000 +rxcds 01000000 1000011010000101 00000000 +rxcs 01001010 00000000 +rxcds 01010000 1000100010000111 00000000 +rxcs 01011010 00000000 +rxcds 01100000 1000111010001101 00000000 +rxcs 01101010 00000000 +rxcds 01110000 1001000010001111 00000000 +rxeop +# +txsop +txcad 00001010 11110001 1000000011111111 +txca 00010000 11110001 +txcad 00011010 11110001 1000001010000001 +txca 00100000 11110001 +txcad 00101010 11110001 1000010010000011 +txca 00110000 11110001 +txcad 00111010 11110001 1000011010000101 +txca 01000000 11110001 +txcad 01001010 11110001 1000100010000111 +txca 01010000 11110001 +txcad 01011010 11110001 1000111010001101 +txca 01100000 11110001 +txcad 01101010 11110001 1001000010001111 +txca 01110000 11110001 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 4: Test RTS throttling via wreg/rreg +C Note: RTS_N response is *not* selfchecking, look into log and check +C for 'RTS_N' lines. +C +C init (11111110:0000000000001000) fena(0),fwth(0),fdly(0),rtsoff(1),rtson(0) +C fifo := 1000000010000000 +C fifo := 1000000010000001 +C fifo := 1000000010000010 +C fifo := 1000000010000011 +C fifo := 1000000110000000 +C fifo := 1000000110000001 +C fifo := 1000000110000010 +C fifo := 1000000110000011 +C fifo -> 8 read (will produce escapes for dl and dh, thus slow down a bit) +C +C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc +C wreg: tx: - cmd(00001,010) addr(0010) dl dh ccrc +C wreg: .... +C wreg: tx: - cmd(01000,010) addr(0010) dl dh ccrc +C rreg: tx: - cmd(10001,000) addr(0010) ccrc +C .... +C rreg: tx: - cmd(11000,000) addr(0010) ccrc +C tx: - eop +C rx: sop - cmd(110) stat crc +C rx: - cmd(010) stat crc +C ... +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C ... +C rx: - cmd(000) dl dh stat crc +C rx: - eop +C +# +rxsop +rxcs 11110110 00000000 +rxcs 00001010 00000000 +rxcs 00010010 00000000 +rxcs 00011010 00000000 +rxcs 00100010 00000000 +rxcs 00101010 00000000 +rxcs 00110010 00000000 +rxcs 00111010 00000000 +rxcs 01000010 00000000 +rxcds 10001000 1000000010000000 00000000 +rxcds 10010000 1000000010000001 00000000 +rxcds 10011000 1000000010000010 00000000 +rxcds 10100000 1000000010000011 00000000 +rxcds 10101000 1000000110000000 00000000 +rxcds 10110000 1000000110000001 00000000 +rxcds 10111000 1000000110000010 00000000 +rxcds 11000000 1000000110000011 00000000 +rxeop +# +txsop +txcad 11110110 11111110 0000000000001000 +txcad 00001010 11110010 1000000010000000 +txcad 00010010 11110010 1000000010000001 +txcad 00011010 11110010 1000000010000010 +txcad 00100010 11110010 1000000010000011 +txcad 00101010 11110010 1000000110000000 +txcad 00110010 11110010 1000000110000001 +txcad 00111010 11110010 1000000110000010 +txcad 01000010 11110010 1000000110000011 +txca 10001000 11110010 +txca 10010000 11110010 +txca 10011000 11110010 +txca 10100000 11110010 +txca 10101000 11110010 +txca 10110000 11110010 +txca 10111000 11110010 +txca 11000000 11110010 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 5: Test RTS flush pulse +C Note: RTS_N response is *not* selfchecking, look into log and check +C for 'RTS_N' lines. +C +C 1a. setup width=1, delay=1 +C +C init (11111110:0001001001111110) fena(1),fwth(1),fdly(1),rtsoff(7),rtson(6) +C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc - eop +# +rxsop +rxcs 11110110 00000000 +rxeop +txsop +txcad 11110110 11111110 0001001001111110 +txeop +.iowt 10 +.wait 50 +C +C 1b. test with wreg sequence +C data := 0000000000000001 +C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop +C rx: sop - cmd(010) stat crc - eop +C +# +rxsop +rxcs 00001010 00000000 +rxeop +txsop +txcad 00001010 11110001 0000000000000001 +txeop +.iowt 10 +.wait 50 +C +C 2a. setup width=3, delay=1 +C +C init (11111110:0001011001111110) fena(1),fwth(3),fdly(1),rtsoff(7),rtson(6) +C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc - eop +# +rxsop +rxcs 11110110 00000000 +rxeop +txsop +txcad 11110110 11111110 0001011001111110 +txeop +.iowt 10 +.wait 50 +C +C 2b. test with wreg sequence +C data := 0000000000000001 +C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop +C rx: sop - cmd(010) stat crc - eop +# +rxsop +rxcs 00001010 00000000 +rxeop +txsop +txcad 00001010 11110001 0000000000000001 +txeop +.iowt 10 +.wait 50 +# +C +C 3a. setup width=7, delay=7 +C +C init (11111110:0001111111111110) fena(1),fwth(7),fdly(7),rtsoff(7),rtson(6) +C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc - eop +# +rxsop +rxcs 11110110 00000000 +rxeop +txsop +txcad 11110110 11111110 0001111111111110 +txeop +.iowt 10 +.wait 50 +C +C 3b. test with wreg sequence +C data := 0000000000000001 +C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop +C rx: sop - cmd(010) stat crc - eop +# +rxsop +rxcs 00001010 00000000 +rxeop +txsop +txcad 00001010 11110001 0000000000000001 +txeop +.iowt 10 +.wait 50 +# +#============================================================================== +# +C ----------------------------------------------------------------------------- +C Run down and Finish +.iowt 10 +.wait 100 Index: rtl/vlib/rlink/tb/tbu_rlink_serport.vhd =================================================================== --- rtl/vlib/rlink/tb/tbu_rlink_serport.vhd (nonexistent) +++ rtl/vlib/rlink/tb/tbu_rlink_serport.vhd (revision 9) @@ -0,0 +1,174 @@ +-- $Id: tbu_rlink_serport.vhd 350 2010-12-28 16:40:11Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tbu_rlink_serport - syn +-- Description: Wrapper for rlink_base plus rlink_serport to avoid records. +-- It has a port interface which will not be modified by xst +-- synthesis (no records, no generic port). +-- +-- Dependencies: rlink_base +-- rlink_serport +-- +-- To test: rlink_serport +-- +-- Target Devices: generic +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2010-04-03 274 11.4 L68 xc3s1000-4 278 588 18 366 s 9.83 +-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 273 547 18 - t 9.65 +-- 2007-10-27 92 9.1 J30 xc3s1000-4 273 545 18 - t 9.65 +-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 283 594 18 323 s 10.3 +-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 285 596 18 - s 9.32 +-- +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-28 350 3.1.1 use CLKDIV/CDINIT=0; +-- 2010-12-26 348 3.1 use rlink_base now; add RTS/CTS ports +-- 2010-12-24 347 3.0.1 rename: CP_*->RL->* +-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol; +-- 2010-06-03 300 2.2.3 use default FAWIDTH for rri_core_serport +-- 2010-05-02 287 2.2.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM +-- drop RP_IINT from interfaces; drop RTSFLUSH generic +-- 2010-04-18 279 2.2.1 drop RTSFBUF generic for rri_serport +-- 2010-04-03 274 2.2 add CP_FLUSH, add rri_serport handshake logic +-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage +-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface +-- 2007-11-24 98 1.1 added RP_IINT support +-- 2007-07-02 63 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.slvtypes.all; +use work.rblib.all; +use work.rlinklib.all; + +entity tbu_rlink_serport is -- rlink core+serport combo + port ( + CLK : in slbit; -- clock + CE_INT : in slbit; -- rlink ito time unit clock enable + CE_USEC : in slbit; -- 1 usec clock enable + CE_MSEC : in slbit; -- 1 msec clock enable + RESET : in slbit; -- reset + RXSD : in slbit; -- receive serial data (board view) + TXSD : out slbit; -- transmit serial data (board view) + CTS_N : in slbit; -- clear to send (act.low, board view) + RTS_N : out slbit; -- request to send (act.low, board view) + RB_MREQ_aval : out slbit; -- rbus: request - aval + RB_MREQ_re : out slbit; -- rbus: request - re + RB_MREQ_we : out slbit; -- rbus: request - we + RB_MREQ_initt: out slbit; -- rbus: request - init; avoid name coll + RB_MREQ_addr : out slv8; -- rbus: request - addr + RB_MREQ_din : out slv16; -- rbus: request - din + RB_SRES_ack : in slbit; -- rbus: response - ack + RB_SRES_busy : in slbit; -- rbus: response - busy + RB_SRES_err : in slbit; -- rbus: response - err + RB_SRES_dout : in slv16; -- rbus: response - dout + RB_LAM : in slv16; -- rbus: look at me + RB_STAT : in slv3 -- rbus: status flags + ); +end entity tbu_rlink_serport; + + +architecture syn of tbu_rlink_serport is + + constant CDWIDTH : positive := 13; + constant c_cdinit : natural := 0; -- NOTE: change in tbd_rlink_serport !! + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + + signal RLB_DI : slv8 := (others=>'0'); + signal RLB_ENA : slbit := '0'; + signal RLB_BUSY : slbit := '0'; + signal RLB_DO : slv8 := (others=>'0'); + signal RLB_VAL : slbit := '0'; + signal RLB_HOLD : slbit := '0'; + signal IFIFO_SIZE : slv4 := (others=>'0'); + signal RL_MONI : rl_moni_type := rl_moni_init; + +begin + + RB_MREQ_aval <= RB_MREQ.aval; + RB_MREQ_re <= RB_MREQ.re; + RB_MREQ_we <= RB_MREQ.we; + RB_MREQ_initt<= RB_MREQ.init; + RB_MREQ_addr <= RB_MREQ.addr; + RB_MREQ_din <= RB_MREQ.din; + + RB_SRES.ack <= RB_SRES_ack; + RB_SRES.busy <= RB_SRES_busy; + RB_SRES.err <= RB_SRES_err; + RB_SRES.dout <= RB_SRES_dout; + + BASE : rlink_base + generic map ( + ATOWIDTH => 5, + ITOWIDTH => 6, + CPREF => c_rlink_cpref, + IFAWIDTH => 5, + OFAWIDTH => 0, -- no output fifo + ENAPIN_RLMON => -1, -- no monitors (both are instantiated in + ENAPIN_RBMON => -1) -- tbd_rlink_serport for ssim avail.) + port map ( + CLK => CLK, + CE_INT => CE_INT, + RESET => RESET, + RLB_DI => RLB_DI, + RLB_ENA => RLB_ENA, + RLB_BUSY => RLB_BUSY, + RLB_DO => RLB_DO, + RLB_VAL => RLB_VAL, + RLB_HOLD => RLB_HOLD, + IFIFO_SIZE => IFIFO_SIZE, + OFIFO_SIZE => open, + RL_MONI => RL_MONI, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT + ); + + SERPORT : rlink_serport + generic map ( + RB_ADDR => conv_std_logic_vector(2#11111110#,8), + CDWIDTH => CDWIDTH, + CDINIT => c_cdinit) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => RESET, + RXSD => RXSD, + TXSD => TXSD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RLB_DI => RLB_DI, + RLB_ENA => RLB_ENA, + RLB_BUSY => RLB_BUSY, + RLB_DO => RLB_DO, + RLB_VAL => RLB_VAL, + RLB_HOLD => RLB_HOLD, + RB_MREQ => RB_MREQ, + IFIFO_SIZE => IFIFO_SIZE, + RL_MONI => RL_MONI, + RL_SER_MONI=> open + ); + +end syn; Index: rtl/vlib/rlink/tb/tbd_rlink_serport.vbom =================================================================== --- rtl/vlib/rlink/tb/tbd_rlink_serport.vbom (nonexistent) +++ rtl/vlib/rlink/tb/tbd_rlink_serport.vbom (revision 9) @@ -0,0 +1,16 @@ +# libs +../../slvtypes.vhd +../../comlib/comlib.vhd +../../serport/serport.vhd +../../rbus/rblib.vhd +../rlinklib.vbom +../../simlib/simlib.vhd +../../simlib/simbus.vhd +# components +tbu_rlink_serport : tbu_rlink_serport.vbom +../../serport/serport_uart_tx.vbom +../../serport/serport_uart_rx.vbom +../../comlib/byte2cdata.vbom +../../comlib/cdata2byte.vbom +# design +tbd_rlink_serport.vhd Index: rtl/vlib/rlink/tb/tb_rlink_direct_ssim.vbom =================================================================== --- rtl/vlib/rlink/tb/tb_rlink_direct_ssim.vbom (nonexistent) +++ rtl/vlib/rlink/tb/tb_rlink_direct_ssim.vbom (revision 9) @@ -0,0 +1,4 @@ +# configure tb_rlink with tbd_rlink_direct wrapper; _*sim case +tbd_rlink_gen = tbd_rlink_direct_ssim.vhd +tb_rlink_direct.vbom +@top : tb_rlink_direct Index: rtl/vlib/rlink/tb/tbcore_rlink.vhd =================================================================== --- rtl/vlib/rlink/tb/tbcore_rlink.vhd (nonexistent) +++ rtl/vlib/rlink/tb/tbcore_rlink.vhd (revision 9) @@ -0,0 +1,267 @@ +-- $Id: tbcore_rlink.vhd 351 2010-12-30 21:50:54Z mueller $ +-- +-- Copyright 2010- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tbcore_rlink - sim +-- Description: Core for a rlink_cext based test bench +-- +-- Dependencies: simlib/simclk +-- +-- To test: generic, any rlink_cext based target +-- +-- Target Devices: generic +-- Tool versions: xst 11.4; ghdl 0.26 +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-29 351 3.0 rename rritb_core->tbcore_rlink; use rbv3 naming +-- 2010-06-05 301 1.1.2 rename .rpmon -> .rbmon +-- 2010-05-02 287 1.1.1 rename config command .sdata -> .sinit; +-- use sbcntl_sbf_(cp|rp)mon defs, use rritblib; +-- 2010-04-25 283 1.1 new clk handling in proc_stim, wait period-setup +-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.simlib.all; +use work.simbus.all; +use work.rblib.all; +use work.rlinklib.all; +use work.rlinktblib.all; +use work.rlink_cext_vhpi.all; + +entity tbcore_rlink is -- core of rlink_cext based test bench + generic ( + CLK_PERIOD : time := 20 ns; -- clock period + CLK_OFFSET : time := 200 ns; -- clock offset (time to start clock) + SETUP_TIME : time := 5 ns; -- setup time + C2OUT_TIME : time := 10 ns); -- clock to output time + port ( + CLK : out slbit; -- main clock + RX_DATA : out slv8; -- read data (data ext->tb) + RX_VAL : out slbit; -- read data valid (data ext->tb) + RX_HOLD : in slbit; -- read data hold (data ext->tb) + TX_DATA : in slv8; -- write data (data tb->ext) + TX_ENA : in slbit -- write data enable (data tb->ext) + ); +end tbcore_rlink; + +architecture sim of tbcore_rlink is + + signal CLK_L : slbit := '0'; + signal CLK_STOP : slbit := '0'; + +begin + + SYSCLK : simclk + generic map ( + PERIOD => CLK_PERIOD, + OFFSET => CLK_OFFSET) + port map ( + CLK => CLK_L, + CLK_CYCLE => SB_CLKCYCLE, + CLK_STOP => CLK_STOP + ); + + CLK <= CLK_L; + + proc_conf: process + file fconf : text open read_mode is "rlink_cext_conf"; + variable iline : line; + variable oline : line; + variable ok : boolean; + variable dname : string(1 to 6) := (others=>' '); + variable ien : slbit := '0'; + variable ibit : integer := 0; + variable iaddr : slv8 := (others=>'0'); + variable idata : slv16 := (others=>'0'); + begin + + SB_CNTL <= (others=>'L'); + SB_VAL <= 'L'; + SB_ADDR <= (others=>'L'); + SB_DATA <= (others=>'L'); + + file_loop: while not endfile(fconf) loop + + readline (fconf, iline); + readcomment(iline, ok); + next file_loop when ok; + readword(iline, dname, ok); + + if ok then + case dname is + + when ".scntl" => -- .scntl + read_ea(iline, ibit); + read_ea(iline, ien); + assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high) + report "assert bit number in range of SB_CNTL" + severity failure; + if ien = '1' then + SB_CNTL(ibit) <= 'H'; + else + SB_CNTL(ibit) <= 'L'; + end if; + + when ".rlmon" => -- .rlmon + read_ea(iline, ien); + if ien = '1' then + SB_CNTL(sbcntl_sbf_rlmon) <= 'H'; + else + SB_CNTL(sbcntl_sbf_rlmon) <= 'L'; + end if; + + when ".rbmon" => -- .rbmon + read_ea(iline, ien); + if ien = '1' then + SB_CNTL(sbcntl_sbf_rbmon) <= 'H'; + else + SB_CNTL(sbcntl_sbf_rbmon) <= 'L'; + end if; + + when ".sinit" => -- .sinit + readgen_ea(iline, iaddr, 8); + readgen_ea(iline, idata, 8); + SB_ADDR <= iaddr; + SB_DATA <= idata; + SB_VAL <= 'H'; + wait for 0 ns; + SB_VAL <= 'L'; + SB_ADDR <= (others=>'L'); + SB_DATA <= (others=>'L'); + wait for 0 ns; + + when others => -- bad command + write(oline, string'("?? unknown command: ")); + write(oline, dname); + writeline(output, oline); + report "aborting" severity failure; + end case; + else + report "failed to find command" severity failure; + end if; + + testempty_ea(iline); + + end loop; -- file_loop: + + wait; -- halt process here + + end process proc_conf; + + proc_stim: process + variable icycle : integer := 0; + variable irxint : integer := 0; + variable irxslv : slv24 := (others=>'0'); + variable ibit : integer := 0; + variable oline : line; + variable r_sb_cntl : slv16 := (others=>'Z'); + variable iaddr : slv8 := (others=>'0'); + variable idata : slv16 := (others=>'0'); + begin + + wait for CLK_OFFSET; + wait for 10*CLK_PERIOD; + + stim_loop: loop + + wait until CLK_L'event and CLK_L='1'; + wait for CLK_PERIOD-SETUP_TIME; + + SB_ADDR <= (others=>'Z'); + SB_DATA <= (others=>'Z'); + + icycle := conv_integer(unsigned(SB_CLKCYCLE)); + RX_VAL <= '0'; + + if RX_HOLD = '0' then + irxint := rlink_cext_getbyte(icycle); + if irxint >= 0 then + if irxint <= 16#ff# then -- normal data byte + RX_DATA <= conv_std_logic_vector(irxint, 8); + RX_VAL <= '1'; + elsif irxint >= 16#1000000# then -- out-of-band message + irxslv := conv_std_logic_vector(irxint, 24); + iaddr := irxslv(23 downto 16); + idata := irxslv(15 downto 0); + writetimestamp(oline, SB_CLKCYCLE, ": OOB-MSG"); + write(oline, irxslv(23 downto 16), right, 9); + write(oline, irxslv(15 downto 8), right, 9); + write(oline, irxslv( 7 downto 0), right, 9); + write(oline, string'(" : ")); + writeoct(oline, iaddr, right, 3); + writeoct(oline, idata, right, 7); + writeline(output, oline); + if unsigned(iaddr) = 0 then + ibit := conv_integer(unsigned(idata(15 downto 8))); + r_sb_cntl(ibit) := idata(0); + else + SB_ADDR <= iaddr; + SB_DATA <= idata; + SB_VAL <= '1'; + wait for 0 ns; + SB_VAL <= 'Z'; + wait for 0 ns; + end if; + end if; + elsif irxint = -1 then -- end-of-file seen + exit stim_loop; + else + report "rlink_cext_getbyte error: " & integer'image(-irxint) + severity failure; + end if; + end if; + + SB_CNTL <= r_sb_cntl; + + end loop; + + wait for 50*CLK_PERIOD; + CLK_STOP <= '1'; + + writetimestamp(oline, SB_CLKCYCLE, ": DONE "); + writeline(output, oline); + + wait; -- suspend proc_stim forever + -- clock is stopped, sim will end + + end process proc_stim; + + proc_moni: process + variable itxdata : integer := 0; + variable itxrc : integer := 0; + variable oline : line; + begin + + loop + wait until CLK_L'event and CLK_L='1'; + wait for C2OUT_TIME; + if TX_ENA = '1' then + itxdata := conv_integer(unsigned(TX_DATA)); + itxrc := rlink_cext_putbyte(itxdata); + assert itxrc=0 + report "rlink_cext_putbyte error: " & integer'image(itxrc) + severity failure; + end if; + + end loop; + + end process proc_moni; + +end sim; Index: rtl/vlib/rlink/tb/tb_rlink_direct.vbom =================================================================== --- rtl/vlib/rlink/tb/tb_rlink_direct.vbom (nonexistent) +++ rtl/vlib/rlink/tb/tb_rlink_direct.vbom (revision 9) @@ -0,0 +1,6 @@ +# configure tb_rlink with tbd_rlink_direct wrapper +# use vhdl configure file (tb_rlink_direct.vhd) at allow +# that all configurations will co-exist in work library +tbd_rlink_gen = tbd_rlink_direct.vbom +tb_rlink.vbom +tb_rlink_direct.vhd Index: rtl/vlib/rlink/tb/tb_rlink_serport.vhd =================================================================== --- rtl/vlib/rlink/tb/tb_rlink_serport.vhd (nonexistent) +++ rtl/vlib/rlink/tb/tb_rlink_serport.vhd (revision 9) @@ -0,0 +1,45 @@ +-- $Id: tb_rlink_serport.vhd 343 2010-12-05 21:24:38Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_rlink_serport +-- Description: Configuration for tb_rlink_serport for tb_rlink. +-- +-- Dependencies: tbd_rlink_gen +-- +-- To test: rlink_serport +-- rlink_core +-- +-- Target Devices: generic +-- +-- Verified (with tb_rlink_stim.dat): +-- Date Rev Code ghdl ise Target Comment +-- 2007-10-12 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (Test 15 fails) +-- 2007-10-12 88 - 0.26 - - c:ok (Test 15 fails) +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-05 343 3.0 rri->rlink renames +-- 2007-11-25 98 1.0.1 use entity rather arch name to switch core/serport +-- 2007-07-08 65 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_rlink_serport of tb_rlink is + + for sim + for all : tbd_rlink_gen + use entity work.tbd_rlink_serport; + end for; + end for; + +end tb_rlink_serport; Index: rtl/vlib/rlink/tb/tbcore_rlink_dcm.vbom =================================================================== --- rtl/vlib/rlink/tb/tbcore_rlink_dcm.vbom (nonexistent) +++ rtl/vlib/rlink/tb/tbcore_rlink_dcm.vbom (revision 9) @@ -0,0 +1,15 @@ +# libs +../../slvtypes.vhd +../../simlib/simlib.vhd +../../simlib/simbus.vhd +../../rbus/rblib.vhd +../rlinklib.vbom +rlinktblib.vhd +rlink_cext_vhpi.vhd +# components +../../simlib/simclk.vbom +../../simlib/simclkcnt.vbom +# vhpi +rlink_cext.c +# design +tbcore_rlink_dcm.vhd Index: rtl/vlib/rlink/tb/tbw.dat =================================================================== --- rtl/vlib/rlink/tb/tbw.dat (nonexistent) +++ rtl/vlib/rlink/tb/tbw.dat (revision 9) @@ -0,0 +1,10 @@ +# $Id: tbw.dat 349 2010-12-28 14:02:13Z mueller $ +# +[tb_rlink_direct] +tb_rlink_stim = tb_rlink_stim.dat +[tb_rlink_serport] +tb_rlink_stim = tb_rlink_stim.dat +[tb_rlink_tba_ttcombo] +tb_rlink_tba_stim = tb_rlink_tba_ttcombo_stim.dat +[tb_rlink_tba_eyemon] +tb_rlink_tba_stim = tb_rlink_tba_eyemon_stim.dat Index: rtl/vlib/rlink/tb/tbd_rlink_direct.vbom =================================================================== --- rtl/vlib/rlink/tb/tbd_rlink_direct.vbom (nonexistent) +++ rtl/vlib/rlink/tb/tbd_rlink_direct.vbom (revision 9) @@ -0,0 +1,8 @@ +# libs +../../slvtypes.vhd +../../rbus/rblib.vhd +../rlinklib.vbom +# components +../rlink_core.vbom +# design +tbd_rlink_direct.vhd Index: rtl/vlib/rlink/tb/tb_rlink.vbom =================================================================== --- rtl/vlib/rlink/tb/tb_rlink.vbom (nonexistent) +++ rtl/vlib/rlink/tb/tb_rlink.vbom (revision 9) @@ -0,0 +1,23 @@ +# Not meant for direct top level usage. Used with +# tb_rlink_(direct|serport|...)[_ssim].vbom and config +# lines to generate the different cases. +# +# libs +../../slvtypes.vhd +../../genlib/genlib.vhd +../../comlib/comlib.vhd +../../rbus/rblib.vhd +../../rbus/rbdlib.vhd +../rlinklib.vbom +../../simlib/simlib.vhd +../../simlib/simbus.vhd +# components +../../simlib/simclk.vbom +../../genlib/clkdivce.vbom +../../rbus/rbd_tester.vbom +../../rbus/rb_mon.vbom +../rlink_mon.vbom +tbd_rlink_gen : tbd_rlink_direct.vbom +# design +tb_rlink.vhd +@top:tb_rlink Index: rtl/vlib/rlink/tb/tbd_rlink_serport.vhd =================================================================== --- rtl/vlib/rlink/tb/tbd_rlink_serport.vhd (nonexistent) +++ rtl/vlib/rlink/tb/tbd_rlink_serport.vhd (revision 9) @@ -0,0 +1,248 @@ +-- $Id: tbd_rlink_serport.vhd 350 2010-12-28 16:40:11Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tbd_rlink_serport - syn +-- Description: Wrapper for rlink_core plus rlink_serport with an interface +-- compatible to the rlink_core only module. +-- NOTE: this implementation is a hack, should be redone +-- using configurations. +-- +-- Dependencies: tbu_rlink_serport [UUT] +-- serport_uart_tx +-- serport_uart_rx +-- byte2cdata +-- cdata2byte +-- +-- To test: rlink_serport +-- +-- Target Devices: generic +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-28 350 3.0.4 use CLKDIV/CDINIT=0; +-- 2010-12-26 348 3.0.3 add RTS/CTS ports for tbu_; +-- 2010-12-24 347 3.0.2 rename: CP_*->RL->* +-- 2010-12-22 346 3.0.1 removed proc_moni, use .rlmon cmd in test bench +-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol; +-- 2010-06-06 301 2.3 use NCOMM=4 (new eop,nak commas) +-- 2010-05-02 287 2.2.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM +-- drop RP_IINT signal from interfaces +-- 2010-04-24 281 2.2.1 use serport_uart_[tr]x directly again +-- 2010-04-03 274 2.2 add CE_USEC +-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage +-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface +-- 2007-11-25 98 1.1 added RP_IINT support; use entity rather arch +-- name to switch core/serport; +-- use serport_uart_[tr]x_tb to allow that UUT is a +-- [sft]sim model compiled with keep hierarchy +-- 2007-07-02 63 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.rlinklib.all; +use work.comlib.all; +use work.serport.all; +use work.simlib.all; +use work.simbus.all; + +entity tbd_rlink_serport is -- rlink_core+rlink_serport tb design + -- implements tbd_rlink_gen + port ( + CLK : in slbit; -- clock + CE_INT : in slbit; -- rlink ito time unit clock enable + CE_USEC : in slbit; -- 1 usec clock enable + RESET : in slbit; -- reset + RL_DI : in slv9; -- rlink: data in + RL_ENA : in slbit; -- rlink: data enable + RL_BUSY : out slbit; -- rlink: data busy + RL_DO : out slv9; -- rlink: data out + RL_VAL : out slbit; -- rlink: data valid + RL_HOLD : in slbit; -- rlink: data hold + RB_MREQ_aval : out slbit; -- rbus: request - aval + RB_MREQ_re : out slbit; -- rbus: request - re + RB_MREQ_we : out slbit; -- rbus: request - we + RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll + RB_MREQ_addr : out slv8; -- rbus: request - addr + RB_MREQ_din : out slv16; -- rbus: request - din + RB_SRES_ack : in slbit; -- rbus: response - ack + RB_SRES_busy : in slbit; -- rbus: response - busy + RB_SRES_err : in slbit; -- rbus: response - err + RB_SRES_dout : in slv16; -- rbus: response - dout + RB_LAM : in slv16; -- rbus: look at me + RB_STAT : in slv3; -- rbus: status flags + TXRXACT : out slbit -- txrx active flag + ); +end entity tbd_rlink_serport; + + +architecture syn of tbd_rlink_serport is + + constant CDWIDTH : positive := 13; + constant c_cdinit : natural := 0; -- NOTE: change in tbu_rlink_serport !! + + signal RRI_RXSD : slbit := '0'; + signal RRI_TXSD : slbit := '0'; + signal RTS_N : slbit := '0'; + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXACT : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + signal CLKDIV : slv13 := conv_std_logic_vector(c_cdinit,CDWIDTH); + +component tbu_rlink_serport is -- rlink core+serport combo + port ( + CLK : in slbit; -- clock + CE_INT : in slbit; -- rlink ito time unit clock enable + CE_USEC : in slbit; -- 1 usec clock enable + CE_MSEC : in slbit; -- 1 msec clock enable + RESET : in slbit; -- reset + RXSD : in slbit; -- receive serial data (board view) + TXSD : out slbit; -- transmit serial data (board view) + CTS_N : in slbit; -- clear to send (act.low, board view) + RTS_N : out slbit; -- request to send (act.low, board view) + RB_MREQ_aval : out slbit; -- rbus: request - aval + RB_MREQ_re : out slbit; -- rbus: request - re + RB_MREQ_we : out slbit; -- rbus: request - we + RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll + RB_MREQ_addr : out slv8; -- rbus: request - addr + RB_MREQ_din : out slv16; -- rbus: request - din + RB_SRES_ack : in slbit; -- rbus: response - ack + RB_SRES_busy : in slbit; -- rbus: response - busy + RB_SRES_err : in slbit; -- rbus: response - err + RB_SRES_dout : in slv16; -- rbus: response - dout + RB_LAM : in slv16; -- rbus: look at me + RB_STAT : in slv3 -- rbus: status flags + ); +end component; + +begin + + UUT : tbu_rlink_serport + port map ( + CLK => CLK, + CE_INT => CE_INT, + CE_USEC => CE_USEC, + CE_MSEC => '1', + RESET => RESET, + RXSD => RRI_RXSD, + TXSD => RRI_TXSD, + CTS_N => '0', + RTS_N => RTS_N, + RB_MREQ_aval => RB_MREQ_aval, + RB_MREQ_re => RB_MREQ_re, + RB_MREQ_we => RB_MREQ_we, + RB_MREQ_initt=> RB_MREQ_initt, + RB_MREQ_addr => RB_MREQ_addr, + RB_MREQ_din => RB_MREQ_din, + RB_SRES_ack => RB_SRES_ack, + RB_SRES_busy => RB_SRES_busy, + RB_SRES_err => RB_SRES_err, + RB_SRES_dout => RB_SRES_dout, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT + ); + + UARTRX : serport_uart_rx + generic map ( + CDWIDTH => CDWIDTH) + port map ( + CLK => CLK, + RESET => RESET, + CLKDIV => CLKDIV, + RXSD => RRI_TXSD, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => open, + RXACT => RXACT + ); + + UARTTX : serport_uart_tx + generic map ( + CDWIDTH => CDWIDTH) + port map ( + CLK => CLK, + RESET => RESET, + CLKDIV => CLKDIV, + TXSD => RRI_RXSD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + TXRXACT <= RXACT or TXBUSY; + + B2CD : byte2cdata -- byte stream -> 9bit comma,data + generic map ( + CPREF => c_rlink_cpref, + NCOMM => c_rlink_ncomm) + port map ( + CLK => CLK, + RESET => RESET, + DI => RXDATA, + ENA => RXVAL, + BUSY => open, + DO => RL_DO, + VAL => RL_VAL, + HOLD => RL_HOLD + ); + + CD2B : cdata2byte -- 9bit comma,data -> byte stream + generic map ( + CPREF => c_rlink_cpref, + NCOMM => c_rlink_ncomm) + port map ( + CLK => CLK, + RESET => RESET, + DI => RL_DI, + ENA => RL_ENA, + BUSY => RL_BUSY, + DO => TXDATA, + VAL => TXENA, + HOLD => TXBUSY + ); + + proc_moni: process + variable oline : line; + variable rts_last : slbit := '0'; + variable ncycle : integer := 0; + begin + loop + wait until CLK'event and CLK='1'; -- check at end of clock cycle + if RTS_N /= rts_last then + writetimestamp(oline, SB_CLKCYCLE, ": rts "); + write(oline, string'(" RTS_N ")); + write(oline, rts_last, right, 1); + write(oline, string'(" -> ")); + write(oline, RTS_N, right, 1); + write(oline, string'(" after ")); + write(oline, ncycle, right, 5); + write(oline, string'(" cycles")); + writeline(output, oline); + rts_last := RTS_N; + ncycle := 0; + end if; + ncycle := ncycle + 1; + end loop; + end process proc_moni; + +end syn; Index: rtl/vlib/rlink/tb/tb_rlink_stim.dat =================================================================== --- rtl/vlib/rlink/tb/tb_rlink_stim.dat (nonexistent) +++ rtl/vlib/rlink/tb/tb_rlink_stim.dat (revision 9) @@ -0,0 +1,3110 @@ +# $Id: tb_rlink_stim.dat 351 2010-12-30 21:50:54Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2010-12-29 351 3.0.6 use new rbd_tester addr 111100xx (from 111101xx) +# 2010-12-28 350 3.3.2 adapt for cdinit=0 in tbd/tbu(some .iowt 10->20) +# 2010-12-25 348 3.3.1 Test 3b moved to tb_rlink_serport_stim.dat +# 2010-12-22 346 3.3 Test 7: check dcrc sends nak and ends in s_error +# Test 20: check that '111' ends in s_error +# Test 21*: now covers eop aborts of all commands +# 2010-12-21 345 3.2 rename .[rt]x... -> [rt]x...; use .[rt]x(idle|attn) +# 2010-12-12 344 3.1 now almost complete test coverage +# 2010-12-05 343 3.0 re-write for usage with tbd_tester +# 2010-06-06 302 2.0 use sop/eop framing instead of soc+chaining +# 2007-11-24 98 1.2 adapt to new internal init handling +# 2007-11-04 95 1.1 add .iowt's in Test 15 to get serport timing right +# 2007-06-17 58 1.0 Initial version +# +#--------------------------------------- +# test coverage table +# rlink_core +# command function and attribute matrix +# cmd function rberr rbnak- rbnak- rbnak- busy cerr derr idle eop +# nak dnak time +# rreg 2,3a 4a 8a 12a 10 10 6a n/a 18a 21b +# wreg 1,3a 4b 8a 12a 10 10 6b n/a 18a 21a +# rblk 4a 4b,7 8b 12b 11 11 6c n/a 18b 21d +# wblk 4a 4b 8b 12b 11 11 6c 7 18b 21c +# stat 5,6*,7 n/a n/a n/a n/a n/a 6c n/a 18c 21e +# attn 13* n/a n/a n/a n/a n/a 16 n/a 18c 21f +# init 9,15a n/a n/a n/a n/a n/a 16 n/a 18c 21g +# +# cmd rreg +# cmd wreg +# cmd rblk +# cmd wblk +# cmd stat +# returns last command status -> 5 +# returns cerr error flag -> 6a,6b +# returns derr error flag -> 7 +# cmd attn +# cmd init +# generates external init -> 9 +# generates internal init -> 15a +# drop cmd after ccrc -> 6b +# attn poll -> 14 +# attn notification -> 15a,15b +# idle timeout -> 17 +# idle insertion at any state -> 18a,18b,18c +# sop-eop framing -> 19 +# unused command code 111 gives nak -> 20 +# eop aborts (all commands) -> 21* +# nak aborts (only wreg) -> 21 +# +# tbd_tester +# reg cntl +# nofifo: read/write, disable fifo-> 8a,8b +# nofifo: clear fifo on 1->0 -> 8a +# stat: write and RB_STAT connect -> 3 +# stat: read -> 3 +# nbusy: controls # of busy cycles-> 10 +# cleared by init (..001) -> 9 +# reg data +# write -> 1,3,5 +# read -> 2,3,5 +# cleared by init (..010) -> 9 +# reg fifo +# write/read normal -> 4a +# read: rberr on EMPTY -> 4a,4b,8a +# write: rberr on FULL -> 4b +# cleared by nofifo 1->0 -> 8a +# cleared by init (..100) -> 9 +# reg attn +# returns cycle length on read -> 10 +# write tickles RB_LAM -> 13b +# +#--------------------------------------- +# rbus address mapping +# 11110000 rbd_tester cntl +# 11110001 rbd_tester data +# 11110010 rbd_tester fifo +# 11110011 rbd_tester attn +# +.rlmon 0 +.rbmon 0 +# +.wait 5 +C some non frame data first +tx8 00000000 +.wait 5 +tx8 00000001 +.wait 5 +tx8 00000010 +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 1: wreg(data) +C data := 0011001111001100 +C ==> shows that rlink can write a register +C +C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop +C rx: sop - cmd(010) stat crc - eop +# +rxsop +rxcs 00001010 00000000 +rxeop +# +txsop +txcad 00001010 11110001 0011001111001100 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 2: rreg(data) +C data -> 0011001111001100 +C ==> shows that rlink can read back a register +C +C rreg: tx: sop - cmd(00001,000) addr(0001) ccrc - eop +C rx: sop - cmd(000) dl dh stat crc - eop +# +rxsop +rxcds 00001000 0011001111001100 00000000 +rxeop +# +txsop +txca 00001000 11110001 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 3: chained wreg(cntl) - wreg(data) - rreg(cntl) - rreg(data) +C cntl := 0111000000000000 (nf=0,stat=111,nbusy=0) +C data := 1100110000110011 --> stat=111 ! +C cntl -> 0111000000000000 --> stat=111 ! +C data -> 1100110000110011 --> stat=111 ! +C ==> shows that rlink can properly address two registers +C ==> shows that tbd_tester cntl can set RB_STAT +C +C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc +C wreg: tx: - cmd(00010,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(00011,000) addr(0000) ccrc +C rreg: tx: - cmd(00100,000) addr(0001) ccrc +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - eop +# +rxsop +rxcs 00001010 00000000 +rxcs 00010010 11100000 +rxcds 00011000 0111000000000000 11100000 +rxcds 00100000 1100110000110011 11100000 +rxeop +# +txsop +txcad 00001010 11110000 0111000000000000 +txcad 00010010 11110001 1100110000110011 +txca 00011000 11110000 +txca 00100000 11110001 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 4a: wblk - rblk (normal) +C write 8 words to fifo with wblk +C read back 8 words from fifo with rblk +C read back 9'th word from fifo with rreg (fails with err) +C ==> shows that block write/read work +C ==> shows that RB_SRES.err works with rreg +C +C wblk: tx: sop - cmd(10110,011) addr(0010) cnt(8->111) ccrc dl dh .. dcrc +C tx: - eop +C rx: sop - cmd(011) stat crc +C rx: - eop +# +rxsop +rxcs 10110011 11100000 +rxeop +# +txsop +txcac 10110011 11110010 00000111 +tx16 0000000001000000 +tx16 0000000001000001 +tx16 0000000001000010 +tx16 0000000001000011 +tx16 0000000001000100 +tx16 0000000001000101 +tx16 0000000001000110 +tx16 0000000001000111 +txcrc +txeop +# +.iowt 10 +# +C rblk: tx: sop - cmd(10111,001) addr(0010) cnt(8->111) ccrc - eop +C rx: sop - cmd(001) cnt dl dh ... stat crc - eop +# +rxsop +rx8 10111001 +rx8 00000111 +rx16 0000000001000000 +rx16 0000000001000001 +rx16 0000000001000010 +rx16 0000000001000011 +rx16 0000000001000100 +rx16 0000000001000101 +rx16 0000000001000110 +rx16 0000000001000111 +rx8 11100000 +rxcrc +rxeop +# +txsop +txcac 10111001 11110010 00000111 +txeop +# +.iowt 10 +# +C rreg: tx: sop - cmd(11000,000) addr(0010) ccrc - eop +C rx: sop - cmd(000) dl dh stat crc - eop +C +C stat: stat(111),attn(0),cerr(0),derr(0),rbnak(0),rberr(1) -> 11100001 +C Note: returns 0101... empty pattern +# +rxsop +rxcds 11000000 0101010101010101 11100001 +rxeop +# +txsop +txca 11000000 11110010 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 4b: wblk - rblk (rberr response) +C write 17 words to fifo with wblk +C write 18'th word to fifo with wreg +C read back 17 words from fifo with rblk +C ==> shows that RB_SRES.err works with wblk,wreg,rblk +C +C wblk: tx: sop - cmd(00001,011) addr(0010) cnt(17->10000) ccrc dl dh .. dcrc +C wreg: tx: - cmd(00010,010) addr(0010) dl dh ccrc +C rblk: tx: - cmd(00011,001) addr(0010) cnt(18->10001) ccrc +C tx: - eop +C rx: sop - cmd(011) stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(001) cnt dl dh ... stat crc +C rx: - eop +C +C stat: stat(111),attn(0),cerr(0),derr(0),rbnak(0),rberr(1) -> 11100001 +# +rxsop +rxcs 00001011 11100001 +rxcs 00010010 11100001 +rx8 00011001 +rx8 00010001 +rx16 0000001111000000 +rx16 0000001111000001 +rx16 0000001111000010 +rx16 0000001111000011 +rx16 0000001111000100 +rx16 0000001111000101 +rx16 0000001111000110 +rx16 0000001111000111 +rx16 0000001111001000 +rx16 0000001111001001 +rx16 0000001111001010 +rx16 0000001111001011 +rx16 0000001111001100 +rx16 0000001111001101 +rx16 0000001111001110 +rx16 0000001111001111 +rx16 0101010101010101 +rx16 0101010101010101 +rx8 11100001 +rxcrc +rxeop +# +txsop +txcac 00001011 11110010 00010000 +tx16 0000001111000000 +tx16 0000001111000001 +tx16 0000001111000010 +tx16 0000001111000011 +tx16 0000001111000100 +tx16 0000001111000101 +tx16 0000001111000110 +tx16 0000001111000111 +tx16 0000001111001000 +tx16 0000001111001001 +tx16 0000001111001010 +tx16 0000001111001011 +tx16 0000001111001100 +tx16 0000001111001101 +tx16 0000001111001110 +tx16 0000001111001111 +tx16 0000001111010000 +txcrc +txcad 00010010 11110010 0000001111010001 +txcac 00011001 11110010 00010001 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 5: stat (in non-error case) re-read last cmd twice, shouldn't change +C cntl := 0000000000000000 (nf=0,stat=000,nbusy=0) --> stat=111 +C data := 1010101010101010 --> stat=000 +C cntl -> 0000000000000000 --> stat=000 +C data -> 1010101010101010 --> stat=000 +C use 'stat' twice, should give cmd and data of last 'read data' +C ==> shows that stat command works properly +C +C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc +C wreg: tx: - cmd(00010,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(00011,000) addr(0000) ccrc +C rreg: tx: - cmd(00100,000) addr(0001) ccrc +C stat: tx: - cmd(00101,100) ccrc +C stat: tx: - cmd(00110,100) ccrc +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(100) ccmd(000) dl dh stat crc +C rx: - cmd(100) ccmd(000) dl dh stat crc +C rx: - eop +# +rxsop +rxcs 00001010 11100000 +rxcs 00010010 00000000 +rxcds 00011000 0000000000000000 00000000 +rxcds 00100000 1010101010101010 00000000 +rxccd 00101100 00100000 1010101010101010 00000000 +rxccd 00110100 00100000 1010101010101010 00000000 +rxeop +# +txsop +txcad 00001010 11110000 0000000000000000 +txcad 00010010 11110001 1010101010101010 +txca 00011000 11110000 +txca 00100000 11110001 +txc 00101100 +txc 00110100 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 6a: ccrc error abort for rreg, last command in packet fails +C cntl := 0101000000000000 (nf=0,stat=101,nbusy=0) --> stat=000 +C data := 1100110011001100 --> stat=101 +C cntl -> 0101000000000000 --> stat=101 +C data -> 1100110011001100 *send with bad CCRC*, will fail +C ==> shows command ccrc check works properly +C +C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc +C wreg: tx: - cmd(00010,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(00011,000) addr(0000) ccrc +C rreg: tx: - cmd(00100,000) addr(0001) *BAD CCRC* +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - nak *ABORT* +C rx: - eop +# +rxsop +rxcs 00001010 00000000 +rxcs 00010010 10100000 +rxcds 00011000 0101000000000000 10100000 +rxnak +rxeop +# +txsop +txcad 00001010 11110000 0101000000000000 +txcad 00010010 11110001 1100110011001100 +txca 00011000 11110000 +tx8 00100000 +tx8 11110001 +txbad +txeop +# +.iowt 10 +# +C +C now check that stat reflects last successfull rreg; re-read cerr=1 sticks ! +C ==> shows command stat allows to deterine last successful (non-stat) command +C +C stat: tx: sop - cmd(00101,100) ccrc +C stat: tx: - cmd(00110,100) ccrc +C tx: - eop +C rx: - cmd(100) ccmd(000) dl dh stat crc +C rx: - cmd(100) ccmd(000) dl dh stat crc +C rx: - eop +C +C stat: stat(101),attn(0),cerr(1),derr(0),rbnak(0),rberr(0) -> 10101000 +rxsop +rxccd 00101100 00011000 0101000000000000 10101000 +rxccd 00110100 00011000 0101000000000000 10101000 +rxeop +# +txsop +txc 00101100 +txc 00110100 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 6b: ccrc error abort for wreg, failure inside packet +C cntl := 0000000000000000 (nf=0,stat=000,nbusy=0) +C cntl := 0111000000000000 (nf=0,stat=111,nbusy=0) *send with bad CCRC* +C data := 0011001100110011 *will be ignored* +C ==> shows commands after a ccrc fail are ignored +C +C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc +C wreg: tx: - cmd(00010,010) addr(0000) dl dh *BAD CCRC* +C wreg: tx: - cmd(00011,010) addr(0001) dl dh ccrc +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: - nak *ABORT* +C rx: - eop +C +rxsop +rxcs 00001010 10100000 +rxnak +rxeop +# +txsop +txcad 00001010 11110000 0000000000000000 +tx8 00010010 +tx8 11110000 +tx8 00000000 +tx8 01110000 +txbad +txcad 00011010 11110001 0011001100110011 +txeop +# +.iowt 10 +# +C +C now check that stat reflects first successfull wreg; re-read cerr=1 sticks ! +C ==> shows command stat allows to deterine last successful (non-stat) command +C +C stat: tx: sop - cmd(00101,100) ccrc +C stat: tx: - cmd(00110,100) ccrc +C tx: - eop +C rx: - cmd(100) ccmd (000) dl dh stat crc +C rx: - cmd(100) ccmd (000) dl dh stat crc +C rx: - eop +C +C stat: stat(101),attn(0),cerr(1),derr(0),rbnak(0),rberr(0) -> 10101000 +rxsop +rxccd 00101100 00001010 0101000000000000 10101000 +rxccd 00110100 00001010 0101000000000000 10101000 +rxeop +# +txsop +txc 00101100 +txc 00110100 +txeop +# +.iowt 10 +# +C +C finally check that cntl register was really written by first wreg +C cntl -> 0000000000000000 +C +C rreg: tx: sop - cmd(01000,000) addr(0000) ccrc - eop +C rx: sop - cmd(000) dl dh stat crc - eop +# +rxsop +rxcds 01000000 0000000000000000 00000000 +rxeop +# +txsop +txca 01000000 11110000 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 6c: ccrc error abort for wblk,rblk and stat +C write 2 words to fifo with bad CCRC -> nak +C read 2 words from fifo with bad CCRC -> nak +C cmd stat with bad CCRC -> nak +C finally stat, will return last successfull read from Test 6b +C +C wblk: tx: sop - cmd(00001,011) addr(0010) cnt(2->001) *BAD CCRC* dl dh .. dcrc +C - eop +C rx: sop - nak - eop +C +rxsop +rxnak +rxeop +# +txsop +tx8 00001011 +tx8 11110010 +tx8 00000001 +txbad +tx16 1010101010101010 +tx16 0101010101010101 +txcrc +txeop +# +.iowt 10 +# +C +C rblk: tx: sop - cmd(00010,001) addr(0010) cnt(2->001) *BAD CCRC* - eop +C rx: sop - nak - eop +C +rxsop +rxnak +rxeop +# +txsop +tx8 00010001 +tx8 11110010 +tx8 00000001 +txbad +txeop +# +.iowt 10 +# +C +C stat: tx: sop - cmd(00011,100) *BAD CCRC* - eop +C rx: sop - nak - eop +C +rxsop +rxnak +rxeop +# +txsop +tx8 00011100 +txbad +txeop +# +.iowt 10 +# +C +C stat: tx: sop - cmd(00100,100) ccrc - eop +C rx: sop - cmd(100) ccmd (000) dl dh stat crc - eop +C +C stat: stat(000),attn(0),cerr(1),derr(0),rbnak(0),rberr(0) -> 00001000 +C +rxsop +rxccd 00100100 01000000 0000000000000000 00001000 +rxeop +# +txsop +txc 00100100 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 7: dcrc error condition in wblk +C write 4 words to fifo with wblk and bad DCRC, will cause a dcrc fail +C ==> shows that data dcrc works in wblk, aborts with +C ==> shows that commands after a dcrc failed wblk are discarded +C +C wblk: tx: sop - cmd(00001,011) addr(0010) cnt(4->011) ccrc dl dh .. +C *BAD DCRC* +C cmd(00010,000) addr(0001) ccrc +C - eop +C rx: sop - cmd(011) stat crc +C rx: - nak eop +C +C stat: stat(000),attn(0),cerr(0),derr(1),rbnak(0),rberr(0) -> 00000100 +# +rxsop +rxcs 00001011 00000100 +rxnak +rxeop +# +txsop +txcac 00001011 11110010 00000011 +tx16 0001000001000000 +tx16 0001000001000001 +tx16 0001000001000010 +tx16 0001000001000011 +txbad +txca 00010000 11110001 +txeop +# +.iowt 10 +# +C +C now check that stat reflects bad dcrc: re-read derr=1 sticks ! +C stat: tx: sop - cmd(00011,100) ccrc +C stat: tx: - cmd(00100,100) ccrc +C tx: - eop +C rx: - cmd(100) ccmd (000) dl dh stat crc +C rx: - cmd(100) ccmd (000) dl dh stat crc +C rx: - eop +C +C stat: stat(000),attn(0),cerr(0),derr(1),rbnak(0),rberr(0) -> 00000100 +C Note: dl,dh still the last read of Test 6 !! +rxsop +rxccd 00011100 00001011 0000000000000000 00000100 +rxccd 00100100 00001011 0000000000000000 00000100 +rxeop +# +txsop +txc 00011100 +txc 00100100 +txeop +# +.iowt 10 +# +C +C now read 6 words from fifo: first 4 previous data, 2 empty reads and err=1 +C rblk: tx: sop - cmd(00101,001) addr(0010) cnt(6->101) ccrc - eop +C rx: sop - cmd(001) cnt dl dh ... stat crc - eop +C +C stat: stat(000),attn(0),cerr(0),derr(0),rbnak(0),rberr(1) -> 00000001 +# +rxsop +rx8 00101001 +rx8 00000101 +rx16 0001000001000000 +rx16 0001000001000001 +rx16 0001000001000010 +rx16 0001000001000011 +rx16 0101010101010101 +rx16 0101010101010101 +rx8 00000001 +rxcrc +rxeop +# +txsop +txcac 00101001 11110010 00000101 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 8a: rbnak(no ack) condition (rreg/wreg) +C fifo := 1111111100000000 -> rbnak=0 +C cntl := 1000000000000000 (nf=1,stat=000,nbusy=0) --> disable fifo +C fifo := 1111111100001111 -> rbnak=1 +C fifo -> 0101010101010101 -> rbnak=1 +C cntl := 0000000000000000 (nf=0,stat=000,nbusy=0) --> enable and clear fifo +C fifo := 0000000001010101 -> rbnak=0 +C fifo -> 0000000001010101 -> rbnak=0 +C fifo -> 0101010101010101 -> rberr=1 (first fifo write data cleared...) +C ==> shows that missing ack is handled properly and rbnak flag set +C +C wreg: tx: sop - cmd(00001,010) addr(0010) dl dh ccrc +C wreg: tx: - cmd(00010,010) addr(0000) dl dh ccrc +C wreg: tx: - cmd(00011,010) addr(0010) dl dh ccrc +C rreg: tx: - cmd(00100,000) addr(0010) ccrc +C wreg: tx: - cmd(00101,010) addr(0000) dl dh ccrc +C wreg: tx: - cmd(00110,010) addr(0010) dl dh ccrc +C rreg: tx: - cmd(00111,000) addr(0010) ccrc +C rreg: tx: - cmd(01000,000) addr(0010) ccrc +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - eop +C +C stat-3: stat(000),attn(0),cerr(0),derr(0),rbnak(1),rberr(0) -> 00000010 +C stat-8: stat(000),attn(0),cerr(0),derr(0),rbnak(0),rberr(1) -> 00000001 +C Note: fifo will nak when nofifo flag set in cntl +C Note: tb returns 0000000000000000 for access to bad addresses +# +rxsop +rxcs 00001010 00000000 +rxcs 00010010 00000000 +rxcs 00011010 00000010 +rxcds 00100000 0000000000000000 00000010 +rxcs 00101010 00000000 +rxcs 00110010 00000000 +rxcds 00111000 0000000010101010 00000000 +rxcds 01000000 0101010101010101 00000001 +rxeop +# +txsop +txcad 00001010 11110010 1111111100000000 +txcad 00010010 11110000 1000000000000000 +txcad 00011010 11110010 1111111100001111 +txca 00100000 11110010 +txcad 00101010 11110000 0000000000000000 +txcad 00110010 11110010 0000000010101010 +txca 00111000 11110010 +txca 01000000 11110010 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 8b: rbnak(no ack) condition (rblk/wblk) +C cntl := 1000000000000000 (nf=1,stat=000,nbusy=0) --> disable fifo +C write 2 words to fifo -> rbnak=1 +C read 2 words from fifo -> rbnak=1 +C cntl := 0000000000000000 (nf=0,stat=000,nbusy=0) --> enable and clear fifo +C ==> shows that missing ack is handled properly and rbnak flag set +C +C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc +C wblk: tx: - cmd(00010,011) addr(0010) cnt(2->001) ccrc dl dh .. dcrc +C rblk: tx: - cmd(00011,001) addr(0010) cnt(2->001) ccrc +C wreg: tx: - cmd(00100,010) addr(0000) dl dh ccrc +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: - cmd(011) stat crc +C rx: - cmd(001) cnt dl dh ... stat crc - eop +C rx: - cmd(010) stat crc +C rx: - eop +C +C stat: stat(000),attn(0),cerr(0),derr(0),rbnak(1),rberr(0) -> 00000010 +C Note: fifo will nak when nofifo flag set in cntl +C Note: tb returns 0000000000000000 for access to bad addresses +# +rxsop +rxcs 00001010 00000000 +rxcs 00010011 00000010 +rx8 00011001 +rx8 00000001 +rx16 0000000000000000 +rx16 0000000000000000 +rx8 00000010 +rxcrc +rxcs 00100010 00000000 +rxeop +# +txsop +txcad 00001010 11110000 1000000000000000 +txcac 00010011 11110010 00000001 +tx16 0011110000000000 +tx16 0011110000000001 +txcrc +txcac 00011001 11110010 00000001 +txcad 00100010 11110000 0000000000000000 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 9: init +C cntl := 0010000000000000 (nf=0,stat=010,nbusy=0) +C data := 1100110000000000 +C fifo := 1100110011000000 +C fifo := 1100110011000001 +C fifo := 1100110011000010 +C fifo := 1100110011000011 +C init (11110000:0000000000000000) noop +C cntl -> 0010000000000000 +C data -> 1100110000000000 +C fifo -> 1100110011000000 +C init (11110000:0000000000000001) clear cntl +C cntl -> 0000000000000000 +C data -> 1100110000000000 +C fifo -> 1100110011000001 +C init (11110000:0000000000000010) clear data +C data -> 0000000000000000 +C fifo -> 1100110011000010 +C init (11110000:0000000000000100) clear fifo +C fifo -> 0101010101010101 ierr=1 +C ==> shows that init is issued and properly decoded +C +C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc +C wreg: tx: - cmd(00010,010) addr(0001) dl dh ccrc +C wreg: tx: - cmd(00011,010) addr(0010) dl dh ccrc +C wreg: tx: - cmd(00100,010) addr(0010) dl dh ccrc +C wreg: tx: - cmd(00101,010) addr(0010) dl dh ccrc +C wreg: tx: - cmd(00110,010) addr(0010) dl dh ccrc +C init: tx: - cmd(00111,110) addr(0000) dl dh ccrc +C rreg: tx: - cmd(01000,000) addr(0000) ccrc +C rreg: tx: - cmd(01001,000) addr(0001) ccrc +C rreg: tx: - cmd(01010,000) addr(0010) ccrc +C init: tx: - cmd(01011,110) addr(0000) dl dh ccrc +C rreg: tx: - cmd(01100,000) addr(0000) ccrc +C rreg: tx: - cmd(01101,000) addr(0001) ccrc +C rreg: tx: - cmd(01110,000) addr(0010) ccrc +C init: tx: - cmd(01111,110) addr(0000) dl dh ccrc +C rreg: tx: - cmd(10000,000) addr(0001) ccrc +C rreg: tx: - cmd(10001,000) addr(0010) ccrc +C init: tx: - cmd(10010,110) addr(0000) dl dh ccrc +C rreg: tx: - cmd(10011,000) addr(0010) ccrc +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(110) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(110) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(110) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(110) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - eop +C +# +rxsop +rxcs 00001010 00000000 +rxcs 00010010 01000000 +rxcs 00011010 01000000 +rxcs 00100010 01000000 +rxcs 00101010 01000000 +rxcs 00110010 01000000 +rxcs 00111110 01000000 +rxcds 01000000 0010000000000000 01000000 +rxcds 01001000 1100110000000000 01000000 +rxcds 01010000 1100110011000000 01000000 +rxcs 01011110 01000000 +rxcds 01100000 0000000000000000 00000000 +rxcds 01101000 1100110000000000 00000000 +rxcds 01110000 1100110011000001 00000000 +rxcs 01111110 00000000 +rxcds 10000000 0000000000000000 00000000 +rxcds 10001000 1100110011000010 00000000 +rxcs 10010110 00000000 +rxcds 10011000 0101010101010101 00000001 +rxeop +# +txsop +txcad 00001010 11110000 0010000000000000 +txcad 00010010 11110001 1100110000000000 +txcad 00011010 11110010 1100110011000000 +txcad 00100010 11110010 1100110011000001 +txcad 00101010 11110010 1100110011000010 +txcad 00110010 11110010 1100110011000011 +txcad 00111110 11110000 0000000000000000 +txca 01000000 11110000 +txca 01001000 11110001 +txca 01010000 11110010 +txcad 01011110 11110000 0000000000000001 +txca 01100000 11110000 +txca 01101000 11110001 +txca 01110000 11110010 +txcad 01111110 11110000 0000000000000010 +txca 10000000 11110001 +txca 10001000 11110010 +txcad 10010110 11110000 0000000000000100 +txca 10011000 11110010 +txeop +# +.iowt 10 +# +C +C cntl := 1111001111111111 (nf=1,stat=111,nbusy=1023) +C cntl -> 1111001111111111 +C init (11110000:0000000000000001) clear cntl +C cntl -> 0000000000000000 +C ==> shows that init completely clears cntl +C +C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc +C rreg: tx: - cmd(00010,000) addr(0000) ccrc +C init: tx: - cmd(00011,110) addr(0000) dl dh ccrc +C rreg: tx: - cmd(00100,000) addr(0000) ccrc +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(110) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - eop +# +rxsop +rxcs 00001010 00000000 +rxcds 00010000 1111001111111111 11100000 +rxcs 00011110 11100000 +rxcds 00100000 0000000000000000 00000000 +rxeop +# +txsop +txcad 00001010 11110000 1111001111111111 +txca 00010000 11110000 +txcad 00011110 11110000 0000000000000001 +txca 00100000 11110000 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 10: rbus busy handling (wreg/rreg via data) +C cntl := 0000000000000000 (nf=0,stat=000,nbusy=0) +C cntl -> 0000000000000000 +C data := 0011001100000000 -> ncyc=1 +C attn -> 0000000000000001 +C data -> 0011001100000000 -> ncyc=1 +C attn -> 0000000000000001 +C ==> shows that reading register attn returns proper ncyc if no busy +C +C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc +C rreg: tx: - cmd(00010,000) addr(0000) ccrc +C wreg: tx: - cmd(00011,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(00100,000) addr(0011) ccrc +C rreg: tx: - cmd(00101,000) addr(0001) ccrc +C rreg: tx: - cmd(00110,000) addr(0011) ccrc +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - eop +C +# +rxsop +rxcs 00001010 00000000 +rxcds 00010000 0000000000000000 00000000 +rxcs 00011010 00000000 +rxcds 00100000 0000000000000001 00000000 +rxcds 00101000 0011001100000000 00000000 +rxcds 00110000 0000000000000001 00000000 +rxeop +# +txsop +txcad 00001010 11110000 0000000000000000 +txca 00010000 11110000 +txcad 00011010 11110001 0011001100000000 +txca 00100000 11110011 +txca 00101000 11110001 +txca 00110000 11110011 +txeop +# +.iowt 10 +# +C +C - now with nbusy=1 +C cntl := 0000000000000001 (nf=0,stat=000,nbusy=1) +C cntl -> 0000000000000001 +C data := 0011001100000001 -> ncyc=2 +C attn -> 0000000000000010 +C data -> 0011001100000001 -> ncyc=2 +C attn -> 0000000000000010 +C ==> shows that wreg/rreg strech cycle; attn returns proper ncyc +C +# +rxsop +rxcs 00001010 00000000 +rxcds 00010000 0000000000000001 00000000 +rxcs 00011010 00000000 +rxcds 00100000 0000000000000010 00000000 +rxcds 00101000 0011001100000001 00000000 +rxcds 00110000 0000000000000010 00000000 +rxeop +# +txsop +txcad 00001010 11110000 0000000000000001 +txca 00010000 11110000 +txcad 00011010 11110001 0011001100000001 +txca 00100000 11110011 +txca 00101000 11110001 +txca 00110000 11110011 +txeop +# +.iowt 10 +# +C +C - now with nbusy=2 +C cntl := 0000000000000010 (nf=0,stat=000,nbusy=2) +C cntl -> 0000000000000010 +C data := 0011001100000010 -> ncyc=3 +C attn -> 0000000000000011 +C data -> 0011001100000010 -> ncyc=3 +C attn -> 0000000000000011 +C +# +rxsop +rxcs 00001010 00000000 +rxcds 00010000 0000000000000010 00000000 +rxcs 00011010 00000000 +rxcds 00100000 0000000000000011 00000000 +rxcds 00101000 0011001100000010 00000000 +rxcds 00110000 0000000000000011 00000000 +rxeop +# +txsop +txcad 00001010 11110000 0000000000000010 +txca 00010000 11110000 +txcad 00011010 11110001 0011001100000010 +txca 00100000 11110011 +txca 00101000 11110001 +txca 00110000 11110011 +txeop +# +.iowt 10 +# +C +C - now with nbusy=31 (still succeeds) +C cntl := 0000000000011111 (nf=0,stat=000,nbusy=31) +C cntl -> 0000000000011111 +C data := 0011001100011111 -> ncyc=32 +C attn -> 0000000000100000 +C data -> 0011001100011111 -> ncyc=32 +C attn -> 0000000000100000 +C +# +rxsop +rxcs 00001010 00000000 +rxcds 00010000 0000000000011111 00000000 +rxcs 00011010 00000000 +rxcds 00100000 0000000000100000 00000000 +rxcds 00101000 0011001100011111 00000000 +rxcds 00110000 0000000000100000 00000000 +rxeop +# +txsop +txcad 00001010 11110000 0000000000011111 +txca 00010000 11110000 +txcad 00011010 11110001 0011001100011111 +txca 00100000 11110011 +txca 00101000 11110001 +txca 00110000 11110011 +txeop +# +.iowt 20 +# +C +C - now with nbusy=32 (fails with rbnak=1) +C cntl := 0000000000100000 (nf=0,stat=000,nbusy=32) +C cntl -> 0000000000100000 +C data := 0011001100100000 -> ncyc=32, rbnak=1 +C attn -> 0000000000100000 +C data -> 0011001100100000 -> ncyc=32, rbnak=1 +C attn -> 0000000000100000 +C +C stat: stat(000),attn(0),cerr(0),derr(0),rbnak(1),rberr(0) -> 00000010 +C ==> shows that timeout abort works +C +# +rxsop +rxcs 00001010 00000000 +rxcds 00010000 0000000000100000 00000000 +rxcs 00011010 00000010 +rxcds 00100000 0000000000100000 00000000 +rxcds 00101000 0101010101010101 00000010 +rxcds 00110000 0000000000100000 00000000 +rxeop +# +txsop +txcad 00001010 11110000 0000000000100000 +txca 00010000 11110000 +txcad 00011010 11110001 0011001100100000 +txca 00100000 11110011 +txca 00101000 11110001 +txca 00110000 11110011 +txeop +# +.iowt 20 +# +C +C - now with nbusy=1023 +C cntl := 0000001111111111 (nf=0,stat=000,nbusy=1023) +C cntl -> 0000001111111111 +C data := 0011001111111111 -> ncyc=32,rbnak=1 +C attn -> 0000000000100000 +C data -> 0101010101010101 -> ncyc=32,rbnak=1 +C attn -> 0000000000100000 +C +C stat: stat(000),attn(0),cerr(0),derr(0),rbnak(1),rberr(0) -> 00000010 +C +# +rxsop +rxcs 00001010 00000000 +rxcds 00010000 0000001111111111 00000000 +rxcs 00011010 00000010 +rxcds 00100000 0000000000100000 00000000 +rxcds 00101000 0101010101010101 00000010 +rxcds 00110000 0000000000100000 00000000 +rxeop +# +txsop +txcad 00001010 11110000 0000001111111111 +txca 00010000 11110000 +txcad 00011010 11110001 0011001111111111 +txca 00100000 11110011 +txca 00101000 11110001 +txca 00110000 11110011 +txeop +# +.iowt 20 +# +C ----------------------------------------------------------------------------- +C Test 11: rbus busy handling (wblk/rblk via fifo) +C cntl := 0000000000000000 (nf=0,stat=000,nbusy=0) +C cntl -> 0000000000000000 +C write 2 words to fifo -> ncyc=1 +C attn -> 0000000000000001 +C read 2 words from fifo -> ncyc=1 +C attn -> 0000000000000001 +C +C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc +C rreg: tx: - cmd(00010,000) addr(0000) ccrc +C wblk: tx: - cmd(00011,011) addr(0010) cnt(2->001) ccrc dl dh .. dcrc +C rreg: tx: - cmd(00100,000) addr(0011) ccrc +C rblk: tx: - cmd(00101,001) addr(0010) cnt(2->001) ccrc +C rreg: tx: - cmd(00110,000) addr(0011) ccrc +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(011) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(001) cnt dl dh ... stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - eop +C +rxsop +rxcs 00001010 00000000 +rxcds 00010000 0000000000000000 00000000 +rxcs 00011011 00000000 +rxcds 00100000 0000000000000001 00000000 +rx8 00101001 +rx8 00000001 +rx16 0011001100000000 +rx16 0011001100000001 +rx8 00000000 +rxcrc +rxcds 00110000 0000000000000001 00000000 +rxeop +# +txsop +txcad 00001010 11110000 0000000000000000 +txca 00010000 11110000 +txcac 00011011 11110010 00000001 +tx16 0011001100000000 +tx16 0011001100000001 +txcrc +txca 00100000 11110011 +txcac 00101001 11110010 00000001 +txca 00110000 11110011 +txeop +# +.iowt 10 +# +C +C - now with nbusy=1 +C cntl := 0000000000000001 (nf=0,stat=000,nbusy=1) +C cntl -> 0000000000000001 +C write 2 words to fifo -> ncyc=2 +C attn -> 0000000000000010 +C read 2 words from fifo -> ncyc=2 +C attn -> 0000000000000010 +C +rxsop +rxcs 00001010 00000000 +rxcds 00010000 0000000000000001 00000000 +rxcs 00011011 00000000 +rxcds 00100000 0000000000000010 00000000 +rx8 00101001 +rx8 00000001 +rx16 0011001100000000 +rx16 0011001100000001 +rx8 00000000 +rxcrc +rxcds 00110000 0000000000000010 00000000 +rxeop +# +txsop +txcad 00001010 11110000 0000000000000001 +txca 00010000 11110000 +txcac 00011011 11110010 00000001 +tx16 0011001100000000 +tx16 0011001100000001 +txcrc +txca 00100000 11110011 +txcac 00101001 11110010 00000001 +txca 00110000 11110011 +txeop +# +.iowt 10 +# +C +C - now with nbusy=31 (still succeeds) +C cntl := 0000000000011111 (nf=0,stat=000,nbusy=31) +C cntl -> 0000000000011111 +C write 2 words to fifo -> ncyc=32 +C attn -> 0000000000100000 +C read 2 words from fifo -> ncyc=32 +C attn -> 0000000000100000 +C +rxsop +rxcs 00001010 00000000 +rxcds 00010000 0000000000011111 00000000 +rxcs 00011011 00000000 +rxcds 00100000 0000000000100000 00000000 +rx8 00101001 +rx8 00000001 +rx16 0011001100000000 +rx16 0011001100000001 +rx8 00000000 +rxcrc +rxcds 00110000 0000000000100000 00000000 +rxeop +# +txsop +txcad 00001010 11110000 0000000000011111 +txca 00010000 11110000 +txcac 00011011 11110010 00000001 +tx16 0011001100000000 +tx16 0011001100000001 +txcrc +txca 00100000 11110011 +txcac 00101001 11110010 00000001 +txca 00110000 11110011 +txeop +# +.iowt 20 +# +C +C - now with nbusy=32 (fails with rbnak=1) +C cntl := 0000000000100000 (nf=0,stat=000,nbusy=32) +C cntl -> 0000000000100000 +C write 2 words to fifo -> ncyc=32,rbnak=1 +C attn -> 0000000000100000 +C read 2 words from fifo -> ncyc=32,rbnak=1 +C attn -> 0000000000100000 +C +C stat: stat(000),attn(0),cerr(0),derr(0),rbnak(1),rberr(0) -> 00000010 +C +rxsop +rxcs 00001010 00000000 +rxcds 00010000 0000000000100000 00000000 +rxcs 00011011 00000010 +rxcds 00100000 0000000000100000 00000000 +rx8 00101001 +rx8 00000001 +rx16 0101010101010101 +rx16 0101010101010101 +rx8 00000010 +rxcrc +rxcds 00110000 0000000000100000 00000000 +rxeop +# +txsop +txcad 00001010 11110000 0000000000100000 +txca 00010000 11110000 +txcac 00011011 11110010 00000001 +tx16 0011001100000000 +tx16 0011001100000001 +txcrc +txca 00100000 11110011 +txcac 00101001 11110010 00000001 +txca 00110000 11110011 +txeop +# +.iowt 20 +# +C ----------------------------------------------------------------------------- +C Test 12a: rbus delay non-ack handling (wreg/rreg via disabled fifo) +C cntl := 1000000000000011 (nf=1,stat=000,nbusy=3) +C cntl -> 1000000000000011 +C data := 1111000000000011 -> ncyc=4,rbnak=1 +C attn -> 0000000000000100 +C data -> 0000000000000000 -> ncyc=4,rbnak=1 +C attn -> 0000000000000100 +C init (11110000:0000000000000111) clear all +C +C stat: stat(000),attn(0),cerr(0),derr(0),rbnak(1),rberr(0) -> 00000010 +C ==> shows that cycle can be first stretched and than aborted +C +C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc +C rreg: tx: - cmd(00010,000) addr(0000) ccrc +C wreg: tx: - cmd(00011,010) addr(0010) dl dh ccrc +C rreg: tx: - cmd(00100,000) addr(0011) ccrc +C rreg: tx: - cmd(00101,000) addr(0010) ccrc +C rreg: tx: - cmd(00110,000) addr(0011) ccrc +C init: tx: - cmd(00111,110) addr(0000) dl dh ccrc +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(110) stat crc +C rx: - eop +C +# +rxsop +rxcs 00001010 00000000 +rxcds 00010000 1000000000000011 00000000 +rxcs 00011010 00000010 +rxcds 00100000 0000000000000100 00000000 +rxcds 00101000 0000000000000000 00000010 +rxcds 00110000 0000000000000100 00000000 +rxcs 00111110 00000000 +rxeop +# +txsop +txcad 00001010 11110000 1000000000000011 +txca 00010000 11110000 +txcad 00011010 11110010 1111000000000011 +txca 00100000 11110011 +txca 00101000 11110010 +txca 00110000 11110011 +txcad 00111110 11110000 0000000000000111 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 12b: rbus delay non-ack handling (wbk/rblk via disabled fifo) +C cntl := 1000000000000011 (nf=1,stat=000,nbusy=3) +C cntl -> 1000000000000011 +C write 2 words to fifo -> ncyc=3,rbnak=1 +C attn -> 0000000000000100 +C read 2 words from fifo -> ncyc=3,rbnak=1 +C attn -> 0000000000000100 +C init (11110000:0000000000000111) clear all +C +C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc +C rreg: tx: - cmd(00010,000) addr(0000) ccrc +C wblk: tx: - cmd(00011,011) addr(0010) cnt(2->001) ccrc dl dh .. dcrc +C rreg: tx: - cmd(00100,000) addr(0011) ccrc +C rblk: tx: - cmd(00101,001) addr(0010) cnt(2->001) ccrc +C rreg: tx: - cmd(00110,000) addr(0011) ccrc +C init: tx: - cmd(00111,110) addr(0000) dl dh ccrc +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(011) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(001) cnt dl dh ... stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(110) stat crc +C rx: - eop +C +rxsop +rxcs 00001010 00000000 +rxcds 00010000 1000000000000011 00000000 +rxcs 00011011 00000010 +rxcds 00100000 0000000000000100 00000000 +rx8 00101001 +rx8 00000001 +rx16 0000000000000000 +rx16 0000000000000000 +rx8 00000010 +rxcrc +rxcds 00110000 0000000000000100 00000000 +rxcs 00111110 00000000 +rxeop +# +txsop +txcad 00001010 11110000 1000000000000011 +txca 00010000 11110000 +txcac 00011011 11110010 00000001 +tx16 1111000000000000 +tx16 1111000000000001 +txcrc +txca 00100000 11110011 +txcac 00101001 11110010 00000001 +txca 00110000 11110011 +txcad 00111110 11110000 0000000000000111 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 13a: attention logic (via asynchronous LAM from test bench) +C .attn 0000000000000000 +C cmd attn returns 0000000000000000, stat=00000000 +C .attn 1000000000000000 +C cmd attn returns 1000000000000000, stat=00000000 +C cmd attn returns 0000000000000000, stat=00000000 +C .attn 0100000000000000 +C .attn 0010000000000000 +C cmd attn returns 0110000000000000, stat=00000000 +C cmd attn returns 0000000000000000, stat=00000000 +C +C ==> shows that attn command works properly +C +C .attn 0000000000000000 +C attn: tx: sop - cmd(00001,101) ccrc - eop +C rx: sop - cmd(101) dl dh stat crc - eop +# +.attn 0000000000000000 +rxsop +rxcds 00001101 0000000000000000 00000000 +rxeop +txsop +txc 00001101 +txeop +.iowt 10 +C +C .attn 1000000000000000 +C attn: tx: sop - cmd(00010,101) ccrc +C attn: tx: - cmd(00011,101) ccrc - eop +C rx: sop - cmd(101) dl dh stat crc +C rx: - cmd(101) dl dh stat crc - eop +# +.attn 1000000000000000 +rxsop +rxcds 00010101 1000000000000000 00000000 +rxcds 00011101 0000000000000000 00000000 +rxeop +txsop +txc 00010101 +txc 00011101 +txeop +.iowt 10 +C +C .attn 0100000000000000 +C .attn 0110000000000000 +C attn: tx: sop - cmd(00100,101) ccrc +C attn: tx: - cmd(00101,101) ccrc - eop +C rx: sop - cmd(101) dl dh stat crc +C rx: - cmd(101) dl dh stat crc - eop +C +# +.attn 0100000000000000 +.attn 0010000000000000 +rxsop +rxcds 00100101 0110000000000000 00000000 +rxcds 00101101 0000000000000000 00000000 +rxeop +txsop +txc 00100101 +txc 00101101 +txeop +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 13b: attention logic (via synchronous LAM from rbd_tester) +C attn := 0000000000000000 stat=00000000 +C cmd attn returns 0000000000000000, stat=00000000 +C attn := 0000000000000001 stat=00010000 +C cmd attn returns 0000000000000001, stat=00000000 +C cmd attn returns 0000000000000000, stat=00000000 +C attn := 0000000000000010 stat=00010000 +C attn := 0000000000000100 stat=00010000 +C cmd attn returns 0000000000000110, stat=00000000 +C cmd attn returns 0000000000000000, stat=00000000 +C +C stat: stat(000),attn(1),cerr(0),derr(0),rbnak(0),rberr(0) -> 00010000 +C ==> shows that attn command works properly +C ==> shows that attn register in tb_rlink triggers RB_LAM +C +C wreg: tx: sop - cmd(00001,010) addr(0011) dl dh ccrc +C attn: tx: - cmd(00010,101) ccrc +C wreg: tx: - cmd(00011,010) addr(0011) dl dh ccrc +C attn: tx: - cmd(00100,101) ccrc +C attn: tx: - cmd(00101,101) ccrc +C wreg: tx: - cmd(00110,010) addr(0011) dl dh ccrc +C wreg: tx: - cmd(00111,010) addr(0011) dl dh ccrc +C attn: tx: - cmd(01000,101) ccrc +C attn: tx: - cmd(01001,101) ccrc +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: - cmd(101) dl dh stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(101) dl dh stat crc +C rx: - cmd(101) dl dh stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(010) stat crc +C rx: - cmd(101) dl dh stat crc +C rx: - cmd(101) dl dh stat crc +C rx: - eop +C +# +rxsop +rxcs 00001010 00000000 +rxcds 00010101 0000000000000000 00000000 +rxcs 00011010 00010000 +rxcds 00100101 0000000000000001 00000000 +rxcds 00101101 0000000000000000 00000000 +rxcs 00110010 00010000 +rxcs 00111010 00010000 +rxcds 01000101 0000000000000110 00000000 +rxcds 01001101 0000000000000000 00000000 +rxeop +# +txsop +txcad 00001010 11110011 0000000000000000 +txc 00010101 +txcad 00011010 11110011 0000000000000001 +txc 00100101 +txc 00101101 +txcad 00110010 11110011 0000000000000010 +txcad 00111010 11110011 0000000000000100 +txc 01000101 +txc 01001101 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 14: attn poll +C send 2 attn commas, get 2 idle chars +C attn := 0000000000001000 stat=00010000 +C send 2 attn commas, get 2 attn chars +C cmd attn returns 0000000000001000, stat=00010000 +C send 2 attn commas, get 2 idle chars +C +C send 2 , expect two back +C +C oof: tx: attn - attn +C rx: idle - idle +C +rxidle +rxidle +txattn +txattn +.iowt 10 +C +C write attn register, set attn bit and flag +C +C wreg: tx: sop - cmd(00001,010) addr(0011) dl dh ccrc - eop +C rx: sop - cmd(010) stat crc - eop +C +rxsop +rxcs 00001010 00010000 +rxeop +txsop +txcad 00001010 11110011 0000000000001000 +txeop +.iowt 10 +C +C send 2 , expect two back +C +C oof: tx: attn - attn +C rx: attn - attn +C +rxattn +rxattn +txattn +txattn +.iowt 10 +C +C send attn cmd, read and clear attn bits and flag +C +C attn: tx: - cmd(00010,101) ccrc - eop +C rx: - cmd(101) dl dh stat crc - eop +C +rxsop +rxcds 00010101 0000000000001000 00000000 +rxeop +txsop +txc 00010101 +txeop +.iowt 10 +C +C send 2 , expect two back +C +C oof: tx: attn - attn +C rx: idle - idle +C +rxidle +rxidle +txattn +txattn +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 15a: enable and test asynchronous attn notification (when idle) +C init (11111111:1000000000000000) noop +C anena(1), itoena(0), ito(0) -> 11111111,1000000000000000 +C .attn 0001000000000000 +C --> will be send +C cmd attn returns 0001000000000000, stat=00000000 +C +C ==> shows that internal init works +C ==> shows asynchronous attn notification works +C +C init: tx: sob - cmd(00001,110) addr(11111111) dl dh ccrc - eop +C rx: sob - cmd(110) stat crc - eop +C +rxsop +rxcs 00001110 00000000 +rxeop +txsop +txcad 00001110 11111111 1000000000000000 +txeop +.iowt 10 +C +C now ping an attention line, expect out-of-frame attn symbol +C .attn 0001000000000000 +C rx: attn +C +.wait 20 +rxattn +.attn 0001000000000000 +.wait 20 +.iowt 10 +C +C attn: tx: - cmd(00010,101) ccrc - eop +C rx: - cmd(101) dl dh stat crc - eop +C +rxsop +rxcds 00010101 0001000000000000 00000000 +rxeop +txsop +txc 00010101 +txeop +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 15b: enable and test asynchronous attn notification (when in packet) +C attn := 0000000000010000 stat=00010000 +C --> will be send after eop +C cmd attn returns 0000000000010000, stat=00000000 +C +C ==> shows asynchronous attn notification comes after eop +C +C write attn register, set attn bit and flag, expect comma after +C +C wreg: tx: sop - cmd(00001,010) addr(0011) dl dh ccrc - eop +C rx: sop - cmd(010) stat crc - eop +C rx: attn +C +rxsop +rxcs 00001010 00010000 +rxeop +rxattn +txsop +txcad 00001010 11110011 0000000000010000 +txeop +.iowt 10 +C +C send attn cmd, read and clear attn bits and flag +C +C attn: tx: - cmd(00010,101) ccrc - eop +C rx: - cmd(101) dl dh stat crc - eop +C +rxsop +rxcds 00010101 0000000000010000 00000000 +rxeop +txsop +txc 00010101 +txeop +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 16: ccrc error abort for attn,init +C +C attn: tx: sop - cmd(00001,101) *BAD CRC - eop +C rx: sop - nak - eop +C +rxsop +rxnak +rxeop +# +txsop +tx8 00001101 +txbad +txeop +# +.iowt 10 +# +C +C init: tx: - cmd(00010,110) addr(0000) dl dh ccrc +C rx: sop - nak - eop +C +rxsop +rxnak +rxeop +# +txsop +tx8 00010110 +tx8 11110000 +tx8 00000000 +tx8 00000000 +txbad +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 17: enable and test idle timeout +C init (11111111:1100000000001001) +C anena(1), itoena(1), ito(9) -> 11111111,1100000000001001 +C ito=9 --> divider=10; ce_xsec div is 1:20 --> total every 200 cycles +C --> send every 200 cycles +C .attn 0000100000000000 +C --> send every 200 cycles +C cmd attn returns 0000100000000000, stat=00000000 +C --> send every 200 cycles +C init (11111111:0000000000000000) +C +C first init (11111111:1100000000001001) -> enable idle timeout +C +C init: tx: sob - cmd(00001,110) addr(00000011) dl dh ccrc - eop +C rx: sob - cmd(110) stat crc - eop +C rx: idle (every 200 cycles) +C .attn 0000100000000000 +C rx: attn (every 200 cycles) +C +rxsop +rxcs 00001110 00000000 +rxeop +rxidle +rxidle +txsop +txcad 00001110 11111111 1100000000001001 +txeop +.iowt 10 +.wait 500 +C +C set attn bits, now send (1 prompt, 2 more every 200 cycles) +C +rxattn +rxattn +rxattn +.attn 0000100000000000 +.wait 500 +C +C send attn cmd, read and clear attn bits and flag +C +C attn: tx: - cmd(00010,101) ccrc - eop +C rx: - cmd(101) dl dh stat crc - eop +C rx: idle (every 200 cycles) +C +rxsop +rxcds 00010101 0000100000000000 00000000 +rxeop +rxidle +rxidle +txsop +txc 00010101 +txeop +.iowt 10 +.wait 500 +C +C second init (11111111:0000000000000000) -> disable idle timeout +C +C init: tx: sob - cmd(00011,110) addr(00000011) dl dh ccrc - eop +C rx: sob - cmd(110) stat crc - eop +C +rxsop +rxcs 00001110 00000000 +rxeop +txsop +txcad 00001110 11111111 0000000000000000 +txeop +.iowt 10 +C +C wait to be sure there are no more or comming +C +.wait 300 +# +C ----------------------------------------------------------------------------- +C Test 18a: verify that commas are tolerated at any state: wreg/rreg +C do wreg+rreg, with between all command bytes send +C use as data 1000000 and 10000001 to force escaping here +C +C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(00010,000) addr(0001) ccrc +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - eop +# +rxsop +rxcs 00001010 00000000 +rxcds 00010000 1000000010000001 00000000 +rxeop +# +txidle +txsop +txidle +tx8 00001010 +txidle +tx8 11110001 +txidle +tx8 10000001 +txidle +txidle +tx8 10000000 +txidle +txcrc +txidle +tx8 00010000 +txidle +txidle +txidle +tx8 11110001 +txidle +txcrc +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 18b: verify that commas are tolerated at any state: wblk/rblk +C do wblk+rblk, with between all command bytes send +C use as data 1000000 to 10000011 to force escaping here +C +C wblk: tx: sop - cmd(00001,011) addr(0010) cnt(2->001) ccrc dl dh .. dcrc +C rblk: tx: - cmd(00010,001) addr(0010) cnt(2->001) ccrc +C tx: - eop +C rx: sop - cmd(011) stat crc +C rx: - cmd(001) cnt dl dh ... stat crc +C rx: - eop +# +rxsop +rxcs 00001011 00000000 +rx8 00010001 +rx8 00000001 +rx16 1000000010000001 +rx16 1000001010000011 +rx8 00000000 +rxcrc +rxeop +# +# wblk +txidle +txsop +txidle +tx8 00001011 +txidle +tx8 11110010 +txidle +tx8 00000001 +txidle +txcrc +txidle +tx8 10000001 +txidle +tx8 10000000 +txidle +tx8 10000011 +txidle +tx8 10000010 +txidle +txcrc +# rblk +txidle +tx8 00010001 +txidle +tx8 11110010 +txidle +tx8 00000001 +txidle +txcrc +txidle +txeop +txidle +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 18c: verify that commas are tolerated at any state: stat,attn,init +C cntl := 0000000000001111 +C cntl -> 0000000000001111 +C cmd stat +C cmd attn +C cmd init (11110000:0000000000000001) clear cntl +C cntl -> 0000000000000000 +C +C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc +C rreg: tx: - cmd(00010,000) addr(0000) ccrc +C stat: tx: - cmd(00011,100) ccrc +C attn: tx: - cmd(00100,101) ccrc +C init: tx: - cmd(00101,110) addr(0000) dl dh ccrc +C rreg: tx: - cmd(00110,000) addr(0000) ccrc +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - cmd(100) ccmd(010) dl dh stat crc +C rx: - cmd(101) dl dh stat crc +C rx: - cmd(110) stat crc +C rx: - cmd(000) dl dh stat crc +C rx: - eop +C +# +rxsop +rxcs 00001010 00000000 +rxcds 00010000 0000000000001111 00000000 +rxccd 00011100 00010000 0000000000001111 00000000 +rxcds 00100101 0000000000000000 00000000 +rxcs 00101110 00000000 +rxcds 00110000 0000000000000000 00000000 +rxeop +# +txsop +# wreg +txidle +txcad 00001010 11110000 0000000000001111 +# rreg +txidle +txca 00010000 11110000 +txidle +# stat +tx8 00011100 +txidle +txcrc +# attn +txidle +tx8 00100101 +txidle +txcrc +# init +txidle +tx8 00101110 +txidle +tx8 11110000 +txidle +tx8 00000001 +txidle +tx8 00000000 +txidle +txcrc +# rreg +txidle +txca 00110000 11110000 +txidle +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 19: sop - eop framing +C test all sequences of sop and eop and nak +C +C 1. sop-eop ==> sop-eop (empty packet) +C tx: sop - eop +C rx: sop - eop +C +rxsop +rxeop +# +txsop +txeop +.iowt 10 +C +C 2. eop ==> nak-eop (out-of-order eop, gives nak) +C tx: eop +C rx: nak - eop +C tx: sop - eop +C rx: sop - eop +C +rxnak +rxeop +txeop +# +.iowt 10 +rxsop +rxeop +txsop +txeop +.iowt 10 +C +C 3. sop - sop - eop ==> sop-nak-eop (out-of-order sop, gives nak) +C tx: sop - sop - eop +C rx: sop - nak - eop +C +rxsop +rxnak +rxeop +# (use txoof for 2nd sop to avoid the side effects of txsop ) +txsop +txoof 100000001 +txeop +.iowt 10 +C +C 4. sop - nak - eop ==> sop-nak-eop (nak is echoed) +C tx: sop - nak - eop +C rx: sop - nak - eop +C +rxsop +rxnak +rxeop +# +txsop +txoof 100000011 +txeop +.iowt 10 +C +C 5. nak ==> {ignored} (out-of-order nak is ignored) +C tx: nak +C tx: sop - eop +C rx: sop - eop +C +rxsop +rxeop +# +txoof 100000011 +txsop +txeop +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 20: unused command code '111' gives a nak and transits to error state +C 1. do '111' command (will abort with nak) +C 2. do rreg command (will be ignored) +C +C 111: tx: sop - '111' +C rreg: tx: - cmd(00010,000) addr(0001) ccrc +C tx: - eop +C rx: sop - nak +C rx: - eop +C +rxsop +rxnak +rxeop +# +txsop +tx8 00000111 +txca 00010000 11110001 +txeop +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 21a: eop aborts of wreg +C +C 0. write all-1s to data register and read back to initialize context +C wreg: tx: sop - cmd(11110,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(11111,000) addr(0001) ccrc +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: sop - cmd(000) dl dh stat crc +C rx: - eop +# +rxsop +rxcs 11110010 00000000 +rxcds 11111000 1111111111111111 00000000 +rxeop +# +txsop +txcad 11110010 11110001 1111111111111111 +txca 11111000 11110001 +txeop +# +.iowt 10 +# +C +C 1a. abort after cmd +C wreg: tx: sop - cmd(00001,010) [[addr(0001) dl dh ccrc]] - eop +C rx: sop - nak - eop +C +# +rxsop +rxnak +rxeop +# +txsop +tx8 00100010 +txeop +.iowt 10 +C +C 1b. check stat +C stat: stat(000),attn(0),cerr(1),derr(0),rbnak(0),rberr(0) -> 00001000 +C stat: tx: sop - cmd(00110,100) ccrc - eop +C rx: sop - cmd(100) ccmd(000) dl dh stat crc - eop +C +# +rxsop +rxccd 00110100 11111000 1111111111111111 00001000 +rxeop +txsop +txc 00110100 +txeop +.iowt 10 +C +C 2a. abort after addr +C wreg: tx: sop - cmd(00001,010) addr(0001) [[dl dh ccrc]] - eop +C rx: sop - nak - eop +C +# +rxsop +rxnak +rxeop +# +txsop +tx8 00001010 +tx8 11110001 +txeop +.iowt 10 +C +C 2b. check stat (stat as for 1a.) +C +# +rxsop +rxccd 00110100 11111000 1111111111111111 00001000 +rxeop +txsop +txc 00110100 +txeop +.iowt 10 +C +C 3a. abort after dl +C wreg: tx: sop - cmd(00001,010) addr(0001) dl [[dh ccrc]] - eop +C rx: sop - nak - eop +C +# +rxsop +rxnak +rxeop +# +txsop +tx8 00001010 +tx8 11110001 +tx8 00000011 +txeop +.iowt 10 +C +C 3b. check stat (stat as for 1a.) +C +# +rxsop +rxccd 00110100 11111000 1111111111111111 00001000 +rxeop +txsop +txc 00110100 +txeop +.iowt 10 +C +C 4a. abort after dh +C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh [[ccrc]] - eop +C rx: sop - nak - eop +C +# +rxsop +rxnak +rxeop +# +txsop +tx8 00001010 +tx8 11110001 +tx8 00000011 +tx8 11000000 +txeop +.iowt 10 +C +C 4b. check stat (stat as for 1a.) +C +# +rxsop +rxccd 00110100 11111000 1111111111111111 00001000 +rxeop +txsop +txc 00110100 +txeop +.iowt 10 +C +C 5a. finally just normal wreg to data register +C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop +C rx: sop - cmd(010) stat crc - eop +C +# +rxsop +rxcs 00001010 00000000 +rxeop +# +txsop +tx8 00001010 +tx8 11110001 +tx8 00000011 +tx8 11000000 +txcrc +txeop +.iowt 10 +C +C 5b. check stat (now cerr=0 again) +C +# +rxsop +rxccd 00110100 00001010 1111111111111111 00000000 +rxeop +txsop +txc 00110100 +txeop +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 21b: eop aborts of rreg +C +C 1a. abort after cmd +C rreg: tx: sop - cmd(00001,000) [[addr(0001) ccrc]] - eop +C rx: sop - nak - eop +C +# +rxsop +rxnak +rxeop +# +txsop +tx8 00001000 +txeop +.iowt 10 +C +C 1b. check stat (cerr=1, last successfull command in Test 21a/5a) +C +# +rxsop +rxccd 00110100 00001010 1111111111111111 00001000 +rxeop +txsop +txc 00110100 +txeop +.iowt 10 +# +C +C 2a. abort after addr +C rreg: tx: sop - cmd(00001,000) addr(0001) [[ccrc]] - eop +C rx: sop - nak - eop +C +# +rxsop +rxnak +rxeop +# +txsop +tx8 00001000 +tx8 11110001 +txeop +.iowt 10 +C +C 2b. check stat (cerr=1) +C +# +rxsop +rxccd 00110100 00001010 1111111111111111 00001000 +rxeop +txsop +txc 00110100 +txeop +.iowt 10 +C +C 3a. finally just normal rreg from data register +C rreg: tx: sop - cmd(00001,000) addr(0001) ccrc - eop +C rx: sop - cmd(000) dl dh stat crc - eop +C +# +rxsop +rxcds 00001000 1100000000000011 00000000 +rxeop +# +txsop +tx8 00001000 +tx8 11110001 +txcrc +txeop +.iowt 10 +C +C 3b. check stat (cerr=0 again) +C +# +rxsop +rxccd 00110100 00001000 1100000000000011 00000000 +rxeop +txsop +txc 00110100 +txeop +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 21c: eop aborts of wblk (with cnt=2) +C +C 1a. abort after cmd +C wreg: tx: sop - cmd(00001,011) [[addr cnt(2->001) ccrc dl dh dl dh dcrc]] -eop +C rx: sop - nak - eop +C +# +rxsop +rxnak +rxeop +# +txsop +tx8 00001011 +txeop +.iowt 10 +C +C 1b. check stat (cerr=1) +C stat: stat(000),attn(0),cerr(1),derr(0),rbnak(0),rberr(0) -> 00001000 +C +# +rxsop +rxccd 00110100 00001000 1100000000000011 00001000 +rxeop +txsop +txc 00110100 +txeop +.iowt 10 +C +C 2a. abort after addr +C wreg: tx: sop - cmd(00001,011) addr [[cnt(2->001) ccrc dl dh dl dh dcrc]] -eop +C rx: sop - nak - eop +C +# +rxsop +rxnak +rxeop +# +txsop +tx8 00001011 +tx8 11110010 +txeop +.iowt 10 +C +C 2b. check stat (cerr=1) +C +# +rxsop +rxccd 11110100 00001000 1100000000000011 00001000 +rxeop +txsop +txc 11110100 +txeop +.iowt 10 +C +C 3a. abort after cnt +C wreg: tx: sop - cmd(00001,011) addr cnt(2->001) [[ccrc dl dh dl dh dcrc]] -eop +C rx: sop - nak - eop +C +# +rxsop +rxnak +rxeop +# +txsop +tx8 00001011 +tx8 11110010 +tx8 00000001 +txeop +.iowt 10 +C +C 3b. check stat (cerr=1) +C +# +rxsop +rxccd 11110100 00001000 1100000000000011 00001000 +rxeop +txsop +txc 11110100 +txeop +.iowt 10 +C +C 4a. abort after ccrc +C wreg: tx: sop - cmd(00001,011) addr cnt(2->001) ccrc [[dl dh dl dh dcrc]] -eop +C rx: sop - cmd(011) - nak - eop +C +# +rxsop +rx8 00001011 +rxnak +rxeop +# +txsop +tx8 00001011 +tx8 11110010 +tx8 00000001 +txcrc +txeop +.iowt 10 +C +C 4b. check stat (ccmd is wblk now; cerr=0,derr=1) +C stat: stat(000),attn(0),cerr(0),derr(1),rbnak(0),rberr(0) -> 00000100 +C +# +rxsop +rxccd 11110100 00001011 1100000000000011 00000100 +rxeop +txsop +txc 11110100 +txeop +.iowt 10 +C +C 5a. abort after 1st dl +C wreg: tx: sop - cmd(00010,011) addr cnt(2->001) ccrc dl [[dh dl dh dcrc]] -eop +C rx: sop - cmd(011) - nak - eop +C +# +rxsop +rx8 00010011 +rxnak +rxeop +# +txsop +tx8 00010011 +tx8 11110010 +tx8 00000001 +txcrc +tx8 00000001 +txeop +.iowt 10 +C +C 5b. check stat (ccmd is wblk now; cerr=0,derr=1) +C +# +rxsop +rxccd 11110100 00010011 1100000000000011 00000100 +rxeop +txsop +txc 11110100 +txeop +.iowt 10 +C +C 6a. abort after 1st dh +C wreg: tx: sop - cmd(00011,011) addr cnt(2->001) ccrc dl dh [[dl dh dcrc]] -eop +C rx: sop - cmd(011) - nak - eop +C +# +rxsop +rx8 00011011 +rxnak +rxeop +# +txsop +tx8 00011011 +tx8 11110010 +tx8 00000001 +txcrc +tx8 00000001 +tx8 00011011 +txeop +.iowt 10 +C +C 6b. check stat (ccmd is wblk now; cerr=0,derr=1) +C +# +rxsop +rxccd 11110100 00011011 1100000000000011 00000100 +rxeop +txsop +txc 11110100 +txeop +.iowt 10 +C +C 7a. abort after 2nd dl +C wreg: tx: sop - cmd(00100,011) addr cnt(2->001) ccrc dl dh dl [[dh dcrc]] -eop +C rx: sop - cmd(011) - nak - eop +C +# +rxsop +rx8 00100011 +rxnak +rxeop +# +txsop +tx8 00100011 +tx8 11110010 +tx8 00000001 +txcrc +tx8 00000001 +tx8 00100011 +tx8 00000010 +txeop +.iowt 10 +C +C 7b. check stat (ccmd is wblk now; cerr=0,derr=1) +C +# +rxsop +rxccd 11110100 00100011 1100000000000011 00000100 +rxeop +txsop +txc 11110100 +txeop +.iowt 10 +C +C 8a. abort after 2nd dh +C wreg: tx: sop - cmd(00101,011) addr cnt(2->001) ccrc dl dh dl dh [[dcrc]] -eop +C rx: sop - cmd(011) - nak - eop +C +# +rxsop +rx8 00101011 +rxnak +rxeop +# +txsop +tx8 00101011 +tx8 11110010 +tx8 00000001 +txcrc +tx8 00000001 +tx8 00101011 +tx8 00000010 +tx8 00101011 +txeop +.iowt 10 +C +C 8b. check stat (ccmd is wblk now; cerr=0,derr=1) +C +# +rxsop +rxccd 11110100 00101011 1100000000000011 00000100 +rxeop +txsop +txc 11110100 +txeop +.iowt 10 +C +C 9a. finally complete wblk without about, for a change +C wreg: tx: sop - cmd(00110,011) addr cnt(2->001) ccrc dl dh dl dh dcrc - eop +C rx: sop - cmd(011) stat crc - eop +C +# +rxsop +rx8 00101011 +rx8 00000000 +rxcrc +rxeop +# +txsop +tx8 00101011 +tx8 11110010 +tx8 00000001 +txcrc +tx8 00000001 +tx8 00110011 +tx8 00000010 +tx8 00110011 +txcrc +txeop +.iowt 10 +C +C 10. now read back fifo, it will contain data from partially done wblk's +C 6a: 00011011 00000001 +C 7a: 00100011 00000001 +C 8a: 00101011 00000001 +C 00101011 00000010 +C 9a: 00110011 00000001 +C 00110011 00000010 +C --> read back 7 words, gives the above 6 plus '0101...' and a rberr=1 +C +C rblk: tx: sop - cmd(00111,001) addr(0010) cnt(7->110) ccrc - eop +C rx: sop - cmd(001) cnt dl dh ... stat crc - eop +C +C stat: stat(000),attn(0),cerr(0),derr(0),rbnak(0),rberr(1) -> 00000001 +C +rxsop +rx8 00111001 +rx8 00000110 +rx16 0001101100000001 +rx16 0010001100000001 +rx16 0010101100000001 +rx16 0010101100000010 +rx16 0011001100000001 +rx16 0011001100000010 +rx16 0101010101010101 +rx8 00000001 +rxcrc +rxeop +# +txsop +txcac 00111001 11110010 00000110 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 21d: eop aborts of rblk (with cnt=2) +C +C 1. to prepare write 2 words into fifo +C wreg: tx: sop - cmd(00001,011) addr cnt(2->001) ccrc dl dh dl dh dcrc - eop +C rx: sop - cmd(011) stat crc - eop +C +# +rxsop +rxcs 00001011 00000000 +rxeop +# +txsop +txcac 00001011 11110010 00000001 +tx16 1111111100000000 +tx16 1111111100000001 +txcrc +txeop +.iowt 10 +# +C +C 2a. abort after cmd +C rblk: tx: sop - cmd(00010,001) [[addr(0010) cnt(2->001) ccrc]] - eop +C rx: sop - nak - eop +C +rxsop +rxnak +rxeop +# +txsop +tx8 00010001 +txeop +.iowt 10 +# +C +C 2b. check stat (cerr=1) +C +# +rxsop +rxccd 11110100 00001011 0101010101010101 00001000 +rxeop +txsop +txc 11110100 +txeop +.iowt 10 +# +C +C 3a. abort after addr +C rblk: tx: sop - cmd(00011,001) addr(0010) [[cnt(2->001) ccrc]] - eop +C rx: sop - nak - eop +C +rxsop +rxnak +rxeop +# +txsop +tx8 00011001 +tx8 11110010 +txeop +.iowt 10 +# +C +C 3b. check stat (cerr=1) +C +# +rxsop +rxccd 11110100 00001011 0101010101010101 00001000 +rxeop +txsop +txc 11110100 +txeop +.iowt 10 +C +C 4a. abort after cnt +C rblk: tx: sop - cmd(00100,001) addr(0010) cnt(2->001) [[ccrc]] - eop +C rx: sop - nak - eop +C +rxsop +rxnak +rxeop +# +txsop +tx8 00100001 +tx8 11110010 +tx8 00000001 +txeop +.iowt 10 +# +C +C 4b. check stat (cerr=1) +C +# +rxsop +rxccd 11110100 00001011 0101010101010101 00001000 +rxeop +txsop +txc 11110100 +txeop +.iowt 10 +# +C +C 5a. finally do successful rblk +C rblk: tx: sop - cmd(00101,001) addr(0010) cnt(2->001) ccrc - eop +C rx: sop - cmd(001) cnt dl dh ... stat crc - eop +C +rxsop +rx8 00101001 +rx8 00000001 +rx16 1111111100000000 +rx16 1111111100000001 +rx8 00000000 +rxcrc +rxeop +# +txsop +tx8 00101001 +tx8 11110010 +tx8 00000001 +txcrc +txeop +.iowt 10 +# +C +C 5b. check stat (cerr=0) +C +# +rxsop +rxccd 11110100 00101001 1111111100000001 00000000 +rxeop +txsop +txc 11110100 +txeop +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 21e: eop aborts of stat +C +C 1. abort after cmd +C rblk: tx: sop - cmd(00001,100) [[ccrc]] - eop +C rx: sop - nak - eop +C +rxsop +rxnak +rxeop +# +txsop +tx8 00001100 +txeop +.iowt 10 +# +C +C 2. normal stat, finally +C rblk: tx: sop - cmd(00010,100) [[ccrc]] - eop +C rx: sop - cmd(100) ccmd(001) dl dh stat crc +C +C stat: stat(000),attn(0),cerr(0),derr(0),rbnak(0),rberr(0) -> 00000000 +C --> Note: stat commands don't the status +C --> no cerr bit set here, despite the failed stat above !! +C +rxsop +rx8 00010100 +rx8 00101001 +rx16 1111111100000001 +rx8 00000000 +rxcrc +rxeop +# +txsop +tx8 00010100 +txcrc +txeop +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 21f: eop aborts of attn +C +C 0. prepare, set 1 attn flag +C +.attn 0000000100000000 +C +C 1a. abort after cmd +C rblk: tx: sop - cmd(00001,101) [[ccrc]] - eop +C rx: sop - nak - eop +C +rxsop +rxnak +rxeop +# +txsop +tx8 00001101 +txeop +.iowt 10 +C +C 1b. check stat +C stat: stat(000),attn(1),cerr(1),derr(0),rbnak(0),rberr(0) -> 00011000 +C +# +rxsop +rxccd 11110100 00101001 1111111100000001 00011000 +rxeop +txsop +txc 11110100 +txeop +.iowt 10 +# +C +C 2. normal attn, finally +C rblk: tx: sop - cmd(00001,101) ccrc - eop +C rx: sop - cmd(101) dl dh stat crc - eop +C +rxsop +rx8 00001101 +rx16 0000000100000000 +rx8 00000000 +rxcrc +rxeop +# +txsop +tx8 00001101 +txcrc +txeop +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 21g: eop aborts of init +C +C 0. prepare, set data register +C data := 0000000000000001 +C +rxsop +rxcs 00001010 00000000 +rxeop +txsop +txcad 00001010 11110001 0000000000000001 +txeop +.iowt 10 +# +C +C 1a. abort after cmd +C rblk: tx: sop - cmd(00010,110) [[addr(0000) dl dh ccrc]] - eop +C rx: sop - nak - eop +C +rxsop +rxnak +rxeop +# +txsop +tx8 00010110 +txeop +.iowt 10 +C +C 1b. check stat +C stat: stat(000),attn(0),cerr(1),derr(0),rbnak(0),rberr(0) -> 00001000 +C +# +rxsop +rxccd 11110100 00001010 0000000100000000 00001000 +rxeop +txsop +txc 11110100 +txeop +.iowt 10 +C +C 2a. abort after addr +C rblk: tx: sop - cmd(00010,110) addr(0000) [[dl dh ccrc]] - eop +C rx: sop - nak - eop +C +rxsop +rxnak +rxeop +# +txsop +tx8 00010110 +tx8 11110000 +txeop +.iowt 10 +C +C 2b. check stat +C +# +rxsop +rxccd 11110100 00001010 0000000100000000 00001000 +rxeop +txsop +txc 11110100 +txeop +.iowt 10 +C +C 3a. abort after dl +C rblk: tx: sop - cmd(00010,110) addr(0000) dl [[dh ccrc]] - eop +C rx: sop - nak - eop +C +rxsop +rxnak +rxeop +# +txsop +tx8 00010110 +tx8 11110000 +tx8 00000010 +txeop +.iowt 10 +C +C 3b. check stat +C +# +rxsop +rxccd 11110100 00001010 0000000100000000 00001000 +rxeop +txsop +txc 11110100 +txeop +.iowt 10 +C +C 4a. abort after dh +C rblk: tx: sop - cmd(00010,110) addr(0000) dl dh [[ccrc]] - eop +C rx: sop - nak - eop +C +rxsop +rxnak +rxeop +# +txsop +tx8 00010110 +tx8 11110000 +tx8 00000010 +tx8 00000000 +txeop +.iowt 10 +C +C 4b. check stat +C +# +rxsop +rxccd 11110100 00001010 0000000100000000 00001000 +rxeop +txsop +txc 11110100 +txeop +.iowt 10 +# +C +C 5a. normal init, finally +C rblk: tx: sop - cmd(00010,110) addr(0000) dl dh ccrc - eop +C rx: sop - cmd(110) stat crc - eop +C +rxsop +rx8 00010110 +rx8 00000000 +rxcrc +rxeop +# +txsop +tx8 00010110 +tx8 11110000 +tx8 00000010 +tx8 00000000 +txcrc +txeop +.iowt 10 +C +C 5b. check that data register cleared +C data -> 0000000000000000 +C +C rreg: tx: sop - cmd(00001,000) addr(0001) ccrc - eop +C rx: sop - cmd(000) dl dh stat crc - eop +# +rxsop +rxcds 00001000 0000000000000000 00000000 +rxeop +# +txsop +txca 00001000 11110001 +txeop +# +.iowt 10 +# +C ----------------------------------------------------------------------------- +C Test 22: nak aborts of wreg +C Note: nak aborts only tested for wreg ! +C sufficient because implementation is internally common for eop and +C nak aborts and all eop aborts are tested above in Test 21*. +C +C 0. write all-1s to data register and read back to initialize context +C wreg: tx: sop - cmd(11110,010) addr(0001) dl dh ccrc +C rreg: tx: - cmd(11111,000) addr(0001) ccrc +C tx: - eop +C rx: sop - cmd(010) stat crc +C rx: sop - cmd(000) dl dh stat crc +C rx: - eop +# +rxsop +rxcs 11110010 00000000 +rxcds 11111000 1111111111111111 00000000 +rxeop +# +txsop +txcad 11110010 11110001 1111111111111111 +txca 11111000 11110001 +txeop +# +.iowt 10 +# +C +C 1a. abort after cmd +C wreg: tx: sop - cmd(00001,010) nak - eop +C rx: sop - nak - eop +C +# +rxsop +rxnak +rxeop +# +txsop +tx8 00100010 +txnak +txeop +.iowt 10 +C +C 1b. check stat +C stat: stat(000),attn(0),cerr(1),derr(0),rbnak(0),rberr(0) -> 00001000 +C stat: tx: sop - cmd(00110,100) ccrc - eop +C rx: sop - cmd(100) ccmd(000) dl dh stat crc - eop +C +# +rxsop +rxccd 00110100 11111000 1111111111111111 00001000 +rxeop +txsop +txc 00110100 +txeop +.iowt 10 +C +C 2a. abort after addr +C wreg: tx: sop - cmd(00001,010) addr(0001) nak - eop +C rx: sop - nak - eop +C +# +rxsop +rxnak +rxeop +# +txsop +tx8 00001010 +tx8 11110001 +txnak +txeop +.iowt 10 +C +C 2b. check stat (stat as for 1a.) +C +# +rxsop +rxccd 00110100 11111000 1111111111111111 00001000 +rxeop +txsop +txc 00110100 +txeop +.iowt 10 +C +C 3a. abort after dl +C wreg: tx: sop - cmd(00001,010) addr(0001) dl nak - eop +C rx: sop - nak - eop +C +# +rxsop +rxnak +rxeop +# +txsop +tx8 00001010 +tx8 11110001 +tx8 00000011 +txnak +txeop +.iowt 10 +C +C 3b. check stat (stat as for 1a.) +C +# +rxsop +rxccd 00110100 11111000 1111111111111111 00001000 +rxeop +txsop +txc 00110100 +txeop +.iowt 10 +C +C 4a. abort after dh +C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh nak - eop +C rx: sop - nak - eop +C +# +rxsop +rxnak +rxeop +# +txsop +tx8 00001010 +tx8 11110001 +tx8 00000011 +tx8 11000000 +txnak +txeop +.iowt 10 +C +C 4b. check stat (stat as for 1a.) +C +# +rxsop +rxccd 00110100 11111000 1111111111111111 00001000 +rxeop +txsop +txc 00110100 +txeop +.iowt 10 +C +C 5a. finally just normal wreg to data register +C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop +C rx: sop - cmd(010) stat crc - eop +C +# +rxsop +rxcs 00001010 00000000 +rxeop +# +txsop +tx8 00001010 +tx8 11110001 +tx8 00000011 +tx8 11000000 +txcrc +txeop +.iowt 10 +C +C 5b. check stat (now cerr=0 again) +C +# +rxsop +rxccd 00110100 00001010 1111111111111111 00000000 +rxeop +txsop +txc 00110100 +txeop +.iowt 10 +# +#============================================================================== +# +C ----------------------------------------------------------------------------- +C Run down and Finish +.iowt 10 +.wait 10 Index: rtl/vlib/rlink/tb/rlink_cext_vhpi.vhd =================================================================== --- rtl/vlib/rlink/tb/rlink_cext_vhpi.vhd (nonexistent) +++ rtl/vlib/rlink/tb/rlink_cext_vhpi.vhd (revision 9) @@ -0,0 +1,58 @@ +-- $Id: rlink_cext_vhpi.vhd 351 2010-12-30 21:50:54Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: rlink_cext_vhpi +-- Description: VHDL procedural interface: VHDL declaration side +-- +-- Dependencies: - +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-29 351 1.1 rename vhpi_rriext->rlink_cext_vhpi; new rbv3 names +-- 2007-08-26 76 1.0 Initial version +------------------------------------------------------------------------------ + +package rlink_cext_vhpi is + + impure function rlink_cext_getbyte ( + clk : integer) -- clock cycle + return integer; + attribute foreign of rlink_cext_getbyte : + function is "VHPIDIRECT rlink_cext_getbyte"; + + impure function rlink_cext_putbyte ( + dat : integer) -- data byte + return integer; + attribute foreign of rlink_cext_putbyte : + function is "VHPIDIRECT rlink_cext_putbyte"; + +end rlink_cext_vhpi; + +package body rlink_cext_vhpi is + + impure function rlink_cext_getbyte ( + clk : integer) -- clock cycle + return integer is + begin + report "rlink_cext_getbyte not vhpi'ed" severity failure; + end rlink_cext_getbyte; + + impure function rlink_cext_putbyte ( + dat : integer) -- data byte + return integer is + begin + report "rlink_cext_getbyte not vhpi'ed" severity failure; + end rlink_cext_putbyte; + +end rlink_cext_vhpi; Index: rtl/vlib/rlink/tb/tbu_rlink_serport.vbom =================================================================== --- rtl/vlib/rlink/tb/tbu_rlink_serport.vbom (nonexistent) +++ rtl/vlib/rlink/tb/tbu_rlink_serport.vbom (revision 9) @@ -0,0 +1,9 @@ +# libs +../../slvtypes.vhd +../../rbus/rblib.vhd +../rlinklib.vbom +# components +../rlink_base.vbom +../rlink_serport.vbom +# design +tbu_rlink_serport.vhd Index: rtl/vlib/rlink/tb/rlinktblib.vhd =================================================================== --- rtl/vlib/rlink/tb/rlinktblib.vhd (nonexistent) +++ rtl/vlib/rlink/tb/rlinktblib.vhd (revision 9) @@ -0,0 +1,177 @@ +-- $Id: rlinktblib.vhd 351 2010-12-30 21:50:54Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: rlinktblib +-- Description: rlink test environment components +-- +-- Dependencies: - +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-29 351 3.0.1 add rbtba_aif; +-- 2010-12-24 347 3.0 rename rritblib->rlinktblib, CP_*->RL_*; +-- many rri->rlink renames; drop rbus parts; +-- 2010-11-13 338 2.5.2 add rritb_core_dcm +-- 2010-06-26 309 2.5.1 add rritb_sres_or_mon +-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining +-- 2010-06-05 301 2.1.2 renamed _rpmon -> _rbmon +-- 2010-05-02 287 2.1.1 rename CE_XSEC->CE_INT,RP_STAT->RB_STAT +-- drop RP_IINT signal from interfaces +-- add sbcntl_sbf_(cp|rp)mon defs +-- 2010-04-24 282 2.1 add rritb_core +-- 2008-08-24 162 2.0 all with new rb_mreq/rb_sres interface +-- 2008-03-24 129 1.1.5 CLK_CYCLE now 31 bits +-- 2007-12-23 105 1.1.4 add AP_LAM for rritb_rpmon(_sb) +-- 2007-11-24 98 1.1.3 add RP_IINT for rritb_rpmon(_sb) +-- 2007-09-01 78 1.1.2 add rricp_rp +-- 2007-08-25 75 1.1.1 add rritb_cpmon_sb, rritb_rpmon_sb +-- 2007-08-16 74 1.1 remove rritb_tt* component; some interface changes +-- 2007-08-03 71 1.0.2 use rrirp_acif; change generics for rritb_[cr]pmon +-- 2007-07-22 68 1.0.1 add rritb_cpmon rritb_rpmon monitors +-- 2007-07-15 66 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.rlinklib.all; + +package rlinktblib is + +type rlink_tba_cntl_type is record -- rlink_tba control + cmd : slv3; -- command code + ena : slbit; -- command enable + addr : slv8; -- address + cnt : slv8; -- block size + eop : slbit; -- end packet after current command +end record rlink_tba_cntl_type; + +constant rlink_tba_cntl_init : rlink_tba_cntl_type := ( + (others=>'0'), -- cmd + '0', -- ena + (others=>'0'), -- addr + (others=>'0'), -- cnt + '0'); -- eop + +type rlink_tba_stat_type is record -- rlink_tba status + busy : slbit; -- command busy + ack : slbit; -- command acknowledge + err : slbit; -- command error flag + stat : slv8; -- status flags + braddr : slv8; -- block read address (for wblk) + bre : slbit; -- block read enable (for wblk) + bwaddr : slv8; -- block write address (for rblk) + bwe : slbit; -- block write enable (for rblk) + attnpend : slbit; -- attn pending + attnint : slbit; -- attn interrupt +end record rlink_tba_stat_type; + +constant rlink_tba_stat_init : rlink_tba_stat_type := ( + '0','0','0', -- busy, ack, err + (others=>'0'), -- stat + (others=>'0'), -- braddr + '0', -- bre + (others=>'0'), -- bwaddr + '0', -- bwe + '0','0'); -- attnpend, attnint + +component rlink_tba is -- rlink test bench adapter + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CNTL : in rlink_tba_cntl_type; -- control port + DI : in slv16; -- input data + STAT : out rlink_tba_stat_type; -- status port + DO : out slv16; -- output data + RL_DI : out slv9; -- rlink: data in + RL_ENA : out slbit; -- rlink: data enable + RL_BUSY : in slbit; -- rlink: data busy + RL_DO : in slv9; -- rlink: data out + RL_VAL : in slbit; -- rlink: data valid + RL_HOLD : out slbit -- rlink: data hold + ); +end component; + +component rbtba_aif is -- rbus tba, abstract interface + -- no generics, no records + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RB_MREQ_aval : in slbit; -- rbus: request - aval + RB_MREQ_re : in slbit; -- rbus: request - re + RB_MREQ_we : in slbit; -- rbus: request - we + RB_MREQ_initt : in slbit; -- rbus: request - init; avoid name coll + RB_MREQ_addr : in slv8; -- rbus: request - addr + RB_MREQ_din : in slv16; -- rbus: request - din + RB_SRES_ack : out slbit; -- rbus: response - ack + RB_SRES_busy : out slbit; -- rbus: response - busy + RB_SRES_err : out slbit; -- rbus: response - err + RB_SRES_dout : out slv16; -- rbus: response - dout + RB_LAM : out slv16; -- rbus: look at me + RB_STAT : out slv3 -- rbus: status flags + ); +end component; + +component tbcore_rlink is -- core of vhpi_cext based test bench + generic ( + CLK_PERIOD : time := 20 ns; -- clock period + CLK_OFFSET : time := 200 ns; -- clock offset (time to start clock) + SETUP_TIME : time := 5 ns; -- setup time + C2OUT_TIME : time := 10 ns); -- clock to output time + port ( + CLK : out slbit; -- main clock + RX_DATA : out slv8; -- read data (data ext->tb) + RX_VAL : out slbit; -- read data valid (data ext->tb) + RX_HOLD : in slbit; -- read data hold (data ext->tb) + TX_DATA : in slv8; -- write data (data tb->ext) + TX_ENA : in slbit -- write data enable (data tb->ext) + ); +end component; + +component tbcore_rlink_dcm is -- dcm aware core of vhpi_cext based tb + generic ( + CLKOSC_PERIOD : time := 20 ns; -- clock osc period + CLKOSC_OFFSET : time := 200 ns; -- clock osc offset (time to start clk) + SETUP_TIME : time := 5 ns; -- setup time + C2OUT_TIME : time := 10 ns); -- clock to output time + port ( + CLKOSC : out slbit; -- clock osc + CLKSYS : in slbit; -- DCM derived system clock + RX_DATA : out slv8; -- read data (data ext->tb) + RX_VAL : out slbit; -- read data valid (data ext->tb) + RX_HOLD : in slbit; -- read data hold (data ext->tb) + TX_DATA : in slv8; -- write data (data tb->ext) + TX_ENA : in slbit -- write data enable (data tb->ext) + ); +end component; + +-- FIXME after this point !! + +component rricp_rp is -- rri comm->reg port aif forwarder + -- implements rricp_aif, uses rrirp_aif + port ( + CLK : in slbit; -- clock + CE_INT : in slbit := '0'; -- rri ito time unit clock enable + RESET : in slbit :='0'; -- reset + RL_DI : in slv9; -- rlink: data in + RL_ENA : in slbit; -- rlink: data enable + RL_BUSY : out slbit; -- rlink: data busy + RL_DO : out slv9; -- rlink: data out + RL_VAL : out slbit; -- rlink: data valid + RL_HOLD : in slbit := '0' -- rlink: data hold + ); +end component; + +end rlinktblib; Index: rtl/vlib/rlink/tb/Makefile =================================================================== --- rtl/vlib/rlink/tb/Makefile (nonexistent) +++ rtl/vlib/rlink/tb/Makefile (revision 9) @@ -0,0 +1,37 @@ +# $Id: Makefile 349 2010-12-28 14:02:13Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2010-12-28 349 1.3.1 add tb_rlink_tba_eyemon +# 2010-12-05 343 1.3 rri->rlink renames +# 2009-11-21 252 1.2 add ISim support +# 2007-11-03 95 1.1.2 use .log rather .dat output in check_dsim +# 2007-09-16 83 1.1.1 add include *.o.dep_ghdl +# 2007-06-29 61 1.1 add clean and all +# 2007-06-10 51 1.0 Initial version +# +EXE_all = tb_rlink_direct tb_rlink_serport \ + tb_rlink_tba_ttcombo tb_rlink_tba_eyemon +# +# +.phony : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean isim_clean +# +#----- +# +include $(RETROBASE)/rtl/vlib/Makefile.ghdl +include $(RETROBASE)/rtl/vlib/Makefile.isim +include $(RETROBASE)/rtl/vlib/Makefile.xflow +# +VBOM_all = $(wildcard *.vbom) +# +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_isim) +include $(wildcard *.o.dep_ghdl) +# Index: rtl/vlib/rlink/tb/.cvsignore =================================================================== --- rtl/vlib/rlink/tb/.cvsignore (nonexistent) +++ rtl/vlib/rlink/tb/.cvsignore (revision 9) @@ -0,0 +1,18 @@ +tb_rlink_stim +tb_rlink_direct +tb_rlink_direct_[sft]sim +tb_rlink_direct_ISim +tb_rlink_direct_ISim_[sft]sim +tb_rlink_serport +tb_rlink_serport_[sft]sim +tb_rlink_serport_ISim +tb_rlink_serport_ISim_[sft]sim +tb_rlink_tba_stim +tb_rlink_tba_ttcombo +tb_rlink_tba_ttcombo_[sft]sim +tb_rlink_tba_ttcombo_ISim +tb_rlink_tba_ttcombo_ISim_[sft]sim +tb_rlink_tba_eyemon +tb_rlink_tba_eyemon_[sft]sim +tb_rlink_tba_eyemon_ISim +tb_rlink_tba_eyemon_ISim_[sft]sim Index: rtl/vlib/rlink/tb/tb_rlink_direct.vhd =================================================================== --- rtl/vlib/rlink/tb/tb_rlink_direct.vhd (nonexistent) +++ rtl/vlib/rlink/tb/tb_rlink_direct.vhd (revision 9) @@ -0,0 +1,44 @@ +-- $Id: tb_rlink_direct.vhd 343 2010-12-05 21:24:38Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_rlink_direct +-- Description: Configuration for tb_rlink_direct for tb_rlink. +-- +-- Dependencies: tbd_rlink_gen +-- +-- To test: rlink_core +-- +-- Target Devices: generic +-- +-- Verified (with tb_rlink_stim.dat): +-- Date Rev Code ghdl ise Target Comment +-- 2007-11-02 93 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok +-- 2007-10-12 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok +-- 2007-10-12 88 - 0.26 - - c:ok +-- +-- Revision History: +-- Date Rev Version Comment +-- 2007-11-25 98 1.0.1 use entity rather arch name to switch core/serport +-- 2007-07-08 65 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_rlink_direct of tb_rlink is + + for sim + for all : tbd_rlink_gen + use entity work.tbd_rlink_direct; + end for; + end for; + +end tb_rlink_direct; Index: rtl/vlib/rlink/tb =================================================================== --- rtl/vlib/rlink/tb (nonexistent) +++ rtl/vlib/rlink/tb (revision 9)
rtl/vlib/rlink/tb Property changes : Added: svn:ignore ## -0,0 +1,50 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_rlink_stim +tb_rlink_direct +tb_rlink_direct_[sft]sim +tb_rlink_direct_ISim +tb_rlink_direct_ISim_[sft]sim +tb_rlink_serport +tb_rlink_serport_[sft]sim +tb_rlink_serport_ISim +tb_rlink_serport_ISim_[sft]sim +tb_rlink_tba_stim +tb_rlink_tba_ttcombo +tb_rlink_tba_ttcombo_[sft]sim +tb_rlink_tba_ttcombo_ISim +tb_rlink_tba_ttcombo_ISim_[sft]sim +tb_rlink_tba_eyemon +tb_rlink_tba_eyemon_[sft]sim +tb_rlink_tba_eyemon_ISim +tb_rlink_tba_eyemon_ISim_[sft]sim Index: rtl/vlib/rlink/rlink_base_serport.vhd =================================================================== --- rtl/vlib/rlink/rlink_base_serport.vhd (nonexistent) +++ rtl/vlib/rlink/rlink_base_serport.vhd (revision 9) @@ -0,0 +1,158 @@ +-- $Id: rlink_base_serport.vhd 350 2010-12-28 16:40:11Z mueller $ +-- +-- Copyright 2010- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rlink_base_serport - syn +-- Description: rlink base + serport combo +-- +-- Dependencies: rlink_base +-- rlink_serport +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa +-- 2010-12-26 348 12.1 M53d xc3s1000-4 332 687 72 463 s 10.2 5 5 +-- 2010-12-26 348 12.1 M53d xc3s1000-4 320 651 36 425 s 10.2 5 0 +-- 2010-12-26 301 12.1 M53d xc3s1000-4 289 619 36 394 s 9.9 - - +-- 2010-04-03 275 11.4 L68 xc3s1000-4 280 600 18 375 s 8.9 - - +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-26 348 3.1 rename from rlink_core_serport, use now rlink_base +-- 2010-12-24 347 3.0.1 rename: CP_*->RL->* +-- 2010-12-04 343 3.0 renamed rri_ -> rlink_ +-- 2010-06-05 301 1.2.2 renamed _rpmon -> _rbmon +-- 2010-06-03 300 1.2.1 use FAWIDTH=5 +-- 2010-05-02 287 1.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM +-- drop RP_IINT from interfaces; drop RTSFLUSH generic +-- 2010-04-18 279 1.1 drop RTSFBUF generic +-- 2010-04-10 275 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.slvtypes.all; +use work.rblib.all; +use work.rlinklib.all; + +entity rlink_base_serport is -- rlink base+serport combo + generic ( + ATOWIDTH : positive := 5; -- access timeout counter width + ITOWIDTH : positive := 6; -- idle timeout counter width + CPREF : slv4 := c_rlink_cpref; -- comma prefix + IFAWIDTH : natural := 5; -- input fifo address width (0=none) + OFAWIDTH : natural := 5; -- output fifo address width (0=none) + ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none) + ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none) + RB_ADDR : slv8 := conv_std_logic_vector(2#11111110#,8); + CDWIDTH : positive := 13; -- clk divider width + CDINIT : natural := 15); -- clk divider initial/reset setting + port ( + CLK : in slbit; -- clock + CE_USEC : in slbit; -- 1 usec clock enable + CE_MSEC : in slbit; -- 1 msec clock enable + CE_INT : in slbit := '0'; -- rlink ito time unit clock enable + RESET : in slbit; -- reset + RXSD : in slbit; -- receive serial data (board view) + TXSD : out slbit; -- transmit serial data (board view) + CTS_N : in slbit := '0'; -- clear to send (act.low, board view) + RTS_N : out slbit; -- request to send (act.low, board view) + RB_MREQ : out rb_mreq_type; -- rbus: request + RB_SRES : in rb_sres_type; -- rbus: response + RB_LAM : in slv16; -- rbus: look at me + RB_STAT : in slv3; -- rbus: status flags + RL_MONI : out rl_moni_type; -- rlink_core: monitor port + RL_SER_MONI : out rl_ser_moni_type -- rlink_serport: monitor port + ); +end entity rlink_base_serport; + + +architecture syn of rlink_base_serport is + + signal RLB_DI : slv8 := (others=>'0'); + signal RLB_ENA : slbit := '0'; + signal RLB_BUSY : slbit := '0'; + signal RLB_DO : slv8 := (others=>'0'); + signal RLB_VAL : slbit := '0'; + signal RLB_HOLD : slbit := '0'; + signal IFIFO_SIZE : slv4 := (others=>'0'); + + signal RL_MONI_L : rl_moni_type := rl_moni_init; -- local, readable RL_MONI + signal RB_MREQ_L : rb_mreq_type := rb_mreq_init; -- local, readable RB_MREQ + +begin + + BASE : rlink_base + generic map ( + ATOWIDTH => ATOWIDTH, + ITOWIDTH => ITOWIDTH, + CPREF => CPREF, + IFAWIDTH => IFAWIDTH, + OFAWIDTH => OFAWIDTH, + ENAPIN_RLMON => ENAPIN_RLMON, + ENAPIN_RBMON => ENAPIN_RBMON) + port map ( + CLK => CLK, + CE_INT => CE_INT, + RESET => RESET, + RLB_DI => RLB_DI, + RLB_ENA => RLB_ENA, + RLB_BUSY => RLB_BUSY, + RLB_DO => RLB_DO, + RLB_VAL => RLB_VAL, + RLB_HOLD => RLB_HOLD, + IFIFO_SIZE => IFIFO_SIZE, + OFIFO_SIZE => open, + RL_MONI => RL_MONI_L, + RB_MREQ => RB_MREQ_L, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT + ); + + RL_MONI <= RL_MONI_L; + RB_MREQ <= RB_MREQ_L; + + SERPORT : rlink_serport + generic map ( + RB_ADDR => RB_ADDR, + CDWIDTH => CDWIDTH, + CDINIT => CDINIT) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => RESET, + RXSD => RXSD, + TXSD => TXSD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RLB_DI => RLB_DI, + RLB_ENA => RLB_ENA, + RLB_BUSY => RLB_BUSY, + RLB_DO => RLB_DO, + RLB_VAL => RLB_VAL, + RLB_HOLD => RLB_HOLD, + RB_MREQ => RB_MREQ_L, + IFIFO_SIZE => IFIFO_SIZE, + RL_MONI => RL_MONI_L, + RL_SER_MONI=> RL_SER_MONI + ); + +end syn; Index: rtl/vlib/rlink/rlink_core.vhd =================================================================== --- rtl/vlib/rlink/rlink_core.vhd (nonexistent) +++ rtl/vlib/rlink/rlink_core.vhd (revision 9) @@ -0,0 +1,891 @@ +-- $Id: rlink_core.vhd 350 2010-12-28 16:40:11Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rlink_core - syn +-- Description: rlink core with 9bit interface +-- +-- Dependencies: comlib/crc8 +-- +-- Test bench: tb/tb_rlink_direct +-- tb/tb_rlink_serport +-- tb/tb_rlink_tba_ttcombo +-- +-- Target Devices: generic +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2010-12-04 343 12.1 M53d xc3s1000-4 155 322 0 199 s 8.9 +-- 2010-06-06 302 11.4 L68 xc3s1000-4 151 323 0 197 s 8.9 +-- 2010-04-03 274 11.4 L68 xc3s1000-4 148 313 0 190 s 8.0 +-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 147 321 0 197 s 8.3 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core; +-- 2010-12-24 347 3.1.1 rename: CP_*->RL->* +-- 2010-12-22 346 3.1 wblk dcrc error: send nak, transit to s_error now; +-- rename stat flags: [cd]crc->[cd]err, ioto->rbnak, +-- ioerr->rberr; '111' cmd now aborts via s_txnak and +-- sets cerr flag; set [cd]err on eop/nak aborts; +-- 2010-12-04 343 3.0 renamed rri_ -> rlink_; rbus V3 interface: use now +-- aval,re,we; add new states: s_rstart, s_wstart +-- 2010-06-20 308 2.6 use rbinit,rbreq,rbwe state flops to drive rb_mreq; +-- now nak on reserved cmd 111; use do_comma_abort(); +-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_ +-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining +-- 2010-06-03 299 2.1.2 drop unneeded unsigned casts; change init encoding +-- 2010-05-02 287 2.1.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM +-- drop RP_IINT signal from interfaces +-- 2010-04-03 274 2.1 add CP_FLUSH output +-- 2009-07-12 233 2.0.1 remove snoopers +-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface +-- 2008-03-02 121 1.1.1 comment out snoopers +-- 2007-11-24 98 1.1 new internal init handling (addr=11111111) +-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned +-- 2007-09-15 82 1.0 Initial version, fully functional +-- 2007-06-17 58 0.5 First preliminary version +------------------------------------------------------------------------------ +-- +-- Overall protocol: +-- _idle : expect +-- sop -> _txsop (echo sop, , to _txsop, _rxcmd) +-- eop -> _txeop (send nak,eop , to _txnak, _txeop, _idle) +-- nak -> _txnak (silently ignore nak) +-- attn -> _txito (send ito , to _idle) +-- data -> _idle (silently ignore data) +-- _error: expect +-- sop -> _txnak (send nak , to _txnak, _error) +-- eop -> _txeop (echo eop , to _txeop, _idle) +-- nak -> _txnak (echo nak , to _txnak, _error) +-- attn -> _txito (silently ignore attn) +-- data -> _idle (silently ignore data) +-- _rxcmd: expect +-- sop -> _txnak (send nak , to _txnak, _error) +-- eop -> _txeop (echo eop , to _txeop, _idle) +-- nak -> _txnak (echo nak , to _txnak, _error) +-- attn -> _txito (silently ignore attn) +-- data -> _idle (decode command) +-- _rx...: expect +-- sop -> _txnak (send nak , to _txnak, _error) +-- eop -> _txnak (send nak,eop , to _txnak, _txeop, _idle) +-- nak -> _txnak (echo nak , to _txnak, _error) +-- attn -> _txito (silently ignore attn) +-- data -> _idle (decode data) +-- +-- 7 supported commands: +-- +-- 000 read reg (rreg): +-- rx: cmd addr ccrc +-- tx: cmd dl dh stat crc +-- seq: _rxcmd _rxaddr _rxccrc (_txcmd|_txnak) +-- _rstart _rreg _txdatl _txdath _txstat _txcrc -> _rxcmd +-- +-- 001 read blk (rblk): +-- rx: cmd addr cnt ccrc +-- tx: cmd cnt dl dh ... stat crc +-- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak) _txcnt +-- {_rstart _rreg _txdatl _txdath _blk}* +-- _txstat _txcrc -> _rxcmd +-- +-- 010 write reg (wreg): +-- rx: cmd addr dl dh ccrc +-- tx: cmd stat crc +-- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak) +-- _wstart _wreg _txstat _txcrc -> _rxcmd +-- +-- 011 write blk (wblk): +-- rx: cmd addr cnt ccrc dl dh ... dcrc +-- tx: cmd stat crc +-- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak) +-- {_rxdatl _rxdath _wstart _wreg _blk}* +-- _rxdcrc _txstat _txcrc -> (_rxcmd|_txnak) +-- +-- 100 read stat (stat): +-- rx: cmd ccrc +-- tx: cmd ccmd dl dh stat crc +-- seq: _rxcmd _rxccrc (_txcmd|_txnak) +-- _txccmd _txdatl _txdath _txstat _txcrc -> _rxcmd +-- +-- 101 read attn (attn): +-- rx: cmd ccrc +-- tx: cmd dl dh stat crc +-- seq: _rxcmd _rxccrc (_txcmd|_txnak) +-- _attn _txdatl _txdath _txstat _txcrc -> _rxcmd +-- +-- 110 write init (init): +-- rx: cmd addr dl dh ccrc +-- tx: cmd stat crc +-- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak) +-- _txstat _txcrc -> _rxcmd +-- like wreg, but no rp_we - rp_hold, just a 1 cycle rp_init pulse +-- +-- 111 is currently not a legal command and causes a nak +-- seq: _txnak +-- +-- The state bits nakcerr and nakderr determine whether cerr/derr is set +-- when s_txnak is entered. cerr is '1' during command receive, derr is '1' +-- during data wblk data receive phase: +-- nakcerr set in s_rxcmd (when command received, unless it's stat) +-- clr in s_txcmd (when wblk) +-- clr in s_txnak +-- clr in s_txcrc (for sucessful completion) +-- nakderr set in s_txcmd (when wblk) +-- clr in s_txnak +-- clr in s_txcrc (for sucessful completion) +-- +-- The different rbus cycle types are encoded as: +-- +-- init aval re we +-- 0 0 0 0 idle +-- 0 0 1 0 not allowed +-- 0 0 0 1 not allowed +-- 0 1 1 0 read +-- 0 1 0 1 write +-- 1 0 0 0 internal init +-- 1 0 0 1 external init +-- 1 0 1 0 not allowed +-- * * 1 1 not allowed +-- 1 1 * * not allowed +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.slvtypes.all; +use work.comlib.all; +use work.rblib.all; +use work.rlinklib.all; + +entity rlink_core is -- rlink core with 9bit interface + generic ( + ATOWIDTH : positive := 5; -- access timeout counter width + ITOWIDTH : positive := 6); -- idle timeout counter width + port ( + CLK : in slbit; -- clock + CE_INT : in slbit := '0'; -- rri ito time unit clock enable + RESET : in slbit; -- reset + RL_DI : in slv9; -- rlink 9b: data in + RL_ENA : in slbit; -- rlink 9b: data enable + RL_BUSY : out slbit; -- rlink 9b: data busy + RL_DO : out slv9; -- rlink 9b: data out + RL_VAL : out slbit; -- rlink 9b: data valid + RL_HOLD : in slbit; -- rlink 9b: data hold + RL_MONI : out rl_moni_type; -- rlink: monitor port + RB_MREQ : out rb_mreq_type; -- rbus: request + RB_SRES : in rb_sres_type; -- rbus: response + RB_LAM : in slv16; -- rbus: look at me + RB_STAT : in slv3 -- rbus: status flags + ); +end entity rlink_core; + + +architecture syn of rlink_core is + + type state_type is ( + s_idle, -- s_idle: wait for sop + s_txito, -- s_txito: send timeout symbol + s_txsop, -- s_txsop: send sop + s_txnak, -- s_txnak: send nak + s_txeop, -- s_txeop: send eop + s_error, -- s_error: wait for eop + s_rxcmd, -- s_rxcmd: wait for cmd + s_rxaddr, -- s_rxaddr: wait for addr + s_rxdatl, -- s_rxdatl: wait for data low + s_rxdath, -- s_rxdath: wait for data high + s_rxcnt, -- s_rxcnt: wait for count + s_rxccrc, -- s_rxccrc: wait for command crc + s_txcmd, -- s_txcmd: send cmd + s_txcnt, -- s_txcnt: send cnt + s_rstart, -- s_rstart: start reg or blk read + s_rreg, -- s_rreg: do reg or blk read + s_txdatl, -- s_txdatl: send data low + s_txdath, -- s_txdath: send data high + s_wstart, -- s_wstart: start reg or blk write + s_wreg, -- s_wreg: do reg or blk write + s_blk, -- s_blk: block count handling + s_rxdcrc, -- s_rxdcrc: wait for data crc + s_attn, -- s_attn: handle attention flags + s_txccmd, -- s_txccmd: send last command + s_txstat, -- s_txstat: send status + s_txcrc -- s_txcrc: send crc + ); + + type regs_type is record + state : state_type; -- state + rcmd : slv8; -- received command + ccmd : slv8; -- current command + addr : slv8; -- register address + dil : slv8; -- input data, lsb + dih : slv8; -- input data, msb + dol : slv8; -- output data, lsb + doh : slv8; -- output data, msb + cnt : slv8; -- block transfer count + attn : slv16; -- attn mask + atocnt : slv(ATOWIDTH-1 downto 0); -- access timeout counter + itocnt : slv(ITOWIDTH-1 downto 0); -- idle timeout counter + itoval : slv(ITOWIDTH-1 downto 0); -- idle timeout value + itoena : slbit; -- idle timeout enable flag + anena : slbit; -- attn notification enable flag + andone : slbit; -- attn notification done + cerr : slbit; -- stat: command error + derr : slbit; -- stat: data error + rbnak: slbit; -- stat: rbus no ack or timeout + rberr : slbit; -- stat: rbus err bit set + nakeop : slbit; -- send eop after nak + nakcerr : slbit; -- set cerr after nak + nakderr : slbit; -- set derr after nak + rbinit : slbit; -- rbus init signal + rbaval : slbit; -- rbus aval signal + rbre : slbit; -- rbus re signal + rbwe : slbit; -- rbus we signal + moneop : slbit; -- rl_moni: eop send pulse + monattn : slbit; -- rl_moni: attn send pulse + monlamp : slbit; -- rl_moni: attn pending state + stat : slv3; -- external status flags + end record regs_type; + + constant atocnt_init : slv(ATOWIDTH-1 downto 0) := (others=>'1'); + constant itocnt_init : slv(ITOWIDTH-1 downto 0) := (others=>'0'); + + constant c_idle : slv4 := "0000"; + constant c_sop : slv4 := "0001"; + constant c_eop : slv4 := "0010"; + constant c_nak : slv4 := "0011"; + constant c_attn : slv4 := "0100"; + + constant regs_init : regs_type := ( + s_idle, -- + (others=>'0'), -- rcmd + (others=>'0'), -- ccmd + (others=>'0'), -- addr + (others=>'0'), -- dil + (others=>'0'), -- dih + (others=>'0'), -- dol + (others=>'0'), -- doh + (others=>'0'), -- cnt + (others=>'0'), -- attn + atocnt_init, -- atocnt + itocnt_init, -- itocnt + itocnt_init, -- itoval + '0', -- itoena + '0','0', -- anena, andone + '0','0','0','0', -- stat flags + '0','0','0', -- nakeop,nakcerr,nakderr + '0','0','0','0', -- rbinit,rbaval,rbre,rbwe + '0','0','0', -- moneop,monattn,monlamp + (others=>'0') -- stat + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + signal CRC_RESET : slbit := '0'; + signal ICRC_ENA : slbit := '0'; + signal OCRC_ENA : slbit := '0'; + signal ICRC_OUT : slv8 := (others=>'0'); + signal OCRC_OUT : slv8 := (others=>'0'); + signal OCRC_IN : slv8 := (others=>'0'); + +begin + + assert ITOWIDTH<=8 + report "assert(ITOWIDTH<=8): max byte size ITO counter supported" + severity failure; + + ICRC : crc8 -- crc generator for input data + port map ( + CLK => CLK, + RESET => CRC_RESET, + ENA => ICRC_ENA, + DI => RL_DI(7 downto 0), + CRC => ICRC_OUT + ); + + OCRC : crc8 -- crc generator for output data + port map ( + CLK => CLK, + RESET => CRC_RESET, + ENA => OCRC_ENA, + DI => OCRC_IN, + CRC => OCRC_OUT + ); + + proc_regs: process (CLK) + begin + + if CLK'event and CLK='1' then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, CE_INT, RL_DI, RL_ENA, RL_HOLD, RB_LAM, + RB_SRES, RB_STAT, ICRC_OUT, OCRC_OUT) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable ival : slbit := '0'; + variable ibusy : slbit := '0'; + variable ido : slv9 := (others=>'0'); + variable ato_go : slbit := '0'; + variable ato_end : slbit := '0'; + variable ito_go : slbit := '0'; + variable ito_end : slbit := '0'; + variable crcreset : slbit := '0'; + variable icrcena : slbit := '0'; + variable ocrcena : slbit := '0'; + variable has_attn : slbit := '0'; + variable snd_attn : slbit := '0'; + variable idi8 : slv8 := (others=>'0'); + variable is_comma : slbit := '0'; + variable comma_typ : slv4 := "0000"; + + procedure do_comma_abort(nstate : inout state_type; + nnakeop : inout slbit; + comma_typ : in slv4) is + begin + if comma_typ=c_sop or comma_typ=c_eop or comma_typ=c_nak then + if comma_typ = c_eop then + nnakeop := '1'; + end if; + nstate := s_txnak; -- next: send nak + end if; + end procedure do_comma_abort; + + begin + + r := R_REGS; + n := R_REGS; + + idi8 := RL_DI(7 downto 0); -- get data part of RL_DI + is_comma := RL_DI(8); -- get comma marker + comma_typ := RL_DI(3 downto 0); -- get comma type + + n.rbinit := '0'; -- clear rb(init|aval|re|we) by default + n.rbaval := '0'; -- they must always be set by the + n.rbre := '0'; -- 'previous state' + n.rbwe := '0'; -- + + n.moneop := '0'; -- default '0', only set by states + n.monattn := '0'; -- " + n.monlamp := '0'; -- + + ibusy := '1'; -- default is to hold input + ival := '0'; + ido := (others=>'0'); + + crcreset := '0'; + icrcena := '0'; + ocrcena := '0'; + + for i in RB_LAM'range loop -- handle attention "LAM's" + if RB_LAM(i) = '1' then -- if LAM bit set + n.attn(i) := '1'; -- set attention bit + end if; + end loop; + + has_attn := '0'; + snd_attn := '0'; + + if unsigned(r.attn) /= 0 then -- is any of the attn bits set ? + has_attn := '1'; + if r.anena='1' and r.andone='0' then -- is attn notification to be send ? + snd_attn := '1'; + n.monlamp := '1'; -- set lamp flag in rl_moni + end if; + end if; + + ato_go := '0'; -- default: keep access timeout in reset + ato_end := '0'; + if unsigned(r.atocnt) = 0 then -- if access timeout count at zero + ato_end := '1'; -- signal expiration + end if; + + ito_go := '0'; -- default: keep idle timeout in reset + ito_end := '0'; + if unsigned(r.itocnt) = 0 then -- if idle timeout count at zero + ito_end := '1'; -- signal expiration + end if; + + case r.state is + when s_idle => -- s_idle: wait for sop -------------- + ito_go := '1'; -- idle timeout active + if snd_attn = '1' then -- if attn notification to be send + n.state := s_txito; -- next: send ito byte + else + ibusy := '0'; -- accept input + if RL_ENA = '1' then -- if input + if is_comma = '1' then -- if comma + case comma_typ is + when c_sop => -- if sop + crcreset := '1'; -- reset crc generators + n.state := s_txsop; -- next: echo it + when c_eop => -- if eop (unexpected) + n.nakeop := '1'; -- send nak,eop + n.state := s_txnak; -- next: send nak + when c_attn => -- if attn + n.state := s_txito; -- next: send ito byte + when others => null; -- other commas: silently ignore + end case; + else -- if normal data + n.state := s_idle; -- silently dropped + end if; + elsif (r.itoena='1' and -- if ito enable, expired and XSEC + ito_end='1' and CE_INT='1') then + n.state := s_txito; -- next: send ito byte + end if; + end if; + + when s_txito => -- s_txito: send timeout symbol ------ + if has_attn = '1' then + ido := c_rlink_dat_attn; -- if attn pending: send attn symbol + n.andone := '1'; + else + ido := c_rlink_dat_idle; -- otherwise: send idle symbol + end if; + ival := '1'; + if RL_HOLD = '0' then -- wait for accept + n.monattn := has_attn; -- signal on rl_moni + n.state := s_idle; -- next: wait for sop + end if; + + when s_txsop => -- s_txsop: send sop ----------------- + ido := c_rlink_dat_sop; -- send sop character + ival := '1'; + if RL_HOLD = '0' then -- wait for accept + n.state := s_rxcmd; -- next: read first command + end if; + + when s_txnak => -- s_txnak: send nak ----------------- + ido := c_rlink_dat_nak; -- send nak character + ival := '1'; + if RL_HOLD = '0' then -- wait for accept + n.nakeop := '0'; -- clear all 'do on nak' state flags + n.nakcerr := '0'; + n.nakderr := '0'; + if r.nakcerr = '1' then -- if setting cerr requested + n.cerr := '1'; -- do it + end if; + if r.nakderr = '1' then -- if settung derr requested + n.derr := '1'; -- do it + end if; + if r.nakeop = '1' then -- if eop after nak requested + n.state := s_txeop; -- next: send eop + else + n.state := s_error; -- next: error state, wait for eop + end if; + end if; + + when s_txeop => -- s_txeop: send eop ----------------- + ido := c_rlink_dat_eop; -- send eop character + ival := '1'; + if RL_HOLD = '0' then -- wait for accept + n.moneop := '1'; -- signal on rl_moni + n.state := s_idle; -- next: idle state, wait for sop + end if; + + when s_error => -- s_error: wait for eop ------------- + ibusy := '0'; -- accept input + if RL_ENA = '1' then + if is_comma = '1' then -- if comma + case comma_typ is + when c_sop => -- if sop (unexpected) + n.state := s_txnak; -- next: send nak + when c_eop => -- if eop + n.state := s_txeop; -- next: echo eop + when c_nak => -- if nak + n.state := s_txnak; -- next: echo nak + when others => null; -- other commas: silently ignore + end case; + else -- if normal data + n.state := s_error; -- silently dropped + end if; + end if; + + when s_rxcmd => -- s_rxcmd: wait for cmd ------------- + ibusy := '0'; -- accept input + if RL_ENA = '1' then + if is_comma = '1' then -- if comma + case comma_typ is + when c_sop => -- if sop (unexpected) + n.state := s_txnak; -- next: send nak + when c_eop => -- if eop + n.state := s_txeop; -- next: echo eop + when c_nak => -- if nak + n.state := s_txnak; -- next: echo nak + when others => null; --other commas: silently ignore + end case; + else -- if not comma + icrcena := '1'; -- update input crc + n.rcmd := idi8; -- latch received command code + -- unless the command is stat + if RL_DI(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then + n.nakcerr := '1'; -- set cerr on eop/nak abort + end if; + case RL_DI(c_rlink_cmd_rbf_code) is + when c_rlink_cmd_rreg | + c_rlink_cmd_rblk | + c_rlink_cmd_wreg | + c_rlink_cmd_wblk | + c_rlink_cmd_init => -- for commands needing addr(data) + n.state := s_rxaddr; -- next: read address + when c_rlink_cmd_stat | + c_rlink_cmd_attn => -- stat and attn commands + n.state := s_rxccrc; -- next: read command crc + when others => + n.state := s_txnak; -- next: send nak + end case; -- rcmd,ccmd always hold good cmd + end if; + end if; + + when s_rxaddr => -- s_rxaddr: wait for addr ----------- + ibusy := '0'; -- accept input + if RL_ENA = '1' then + if is_comma = '1' then -- if comma + do_comma_abort(n.state, n.nakeop, comma_typ); + else + icrcena := '1'; -- update input crc + n.addr := idi8; -- latch read address + case r.rcmd(c_rlink_cmd_rbf_code) is + when c_rlink_cmd_rreg => -- for rreg command + n.state := s_rxccrc; -- next: read command crc + when c_rlink_cmd_wreg | + c_rlink_cmd_init => -- for wreg, init command + n.state := s_rxdatl; -- next: read data lsb + when others => -- for rblk or wblk + n.state := s_rxcnt; -- next: read count + end case; + end if; + end if; + + when s_rxdatl => -- s_rxdatl: wait for data low ------- + ibusy := '0'; -- accept input + if RL_ENA = '1' then + if is_comma = '1' then -- if comma + do_comma_abort(n.state, n.nakeop, comma_typ); + else + icrcena := '1'; -- update input crc + n.dil := idi8; -- latch data lsb part + n.state := s_rxdath; -- next: read data msb + end if; + end if; + + when s_rxdath => -- s_rxdath: wait for data high ------ + ibusy := '0'; -- accept input + if RL_ENA = '1' then + if is_comma = '1' then -- if comma + do_comma_abort(n.state, n.nakeop, comma_typ); + else + icrcena := '1'; -- update input crc + n.dih := idi8; -- latch data msb part + if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_wblk then -- if wblk + n.rbaval := '1'; -- prepare rbus cycle + n.state := s_wstart; -- next: start write reg + else -- otherwise + n.state := s_rxccrc; -- next: read command crc + end if; + end if; + end if; + + when s_rxcnt => -- s_rxcnt: wait for count ----------- + ibusy := '0'; -- accept input + if RL_ENA = '1' then + if is_comma = '1' then -- if comma + do_comma_abort(n.state, n.nakeop, comma_typ); + else + icrcena := '1'; -- update input crc + n.cnt := idi8; -- latch count + n.state := s_rxccrc; -- next: read command crc + end if; + end if; + + when s_rxccrc => -- s_rxccrc: wait for command crc ---- + ibusy := '0'; -- accept input + if RL_ENA = '1' then + if is_comma = '1' then -- if comma + do_comma_abort(n.state, n.nakeop, comma_typ); + else + if idi8 /= ICRC_OUT then -- if crc error + -- unless the command is stat + if r.rcmd(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then + n.cerr := '1'; -- set command error flag + end if; + n.state := s_txnak; -- next: send nak + else -- if crc ok + n.state := s_txcmd; -- next: echo command + end if; + end if; + end if; + + when s_txcmd => -- s_txcmd: send cmd ----------------- + ido := '0' & r.rcmd; -- send read command + ival := '1'; + if RL_HOLD = '0' then -- wait for accept + ocrcena := '1'; -- update output crc + if r.rcmd(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then --unless stat + n.ccmd := r.rcmd; -- latch current command in ccmd + n.stat := RB_STAT; -- latch external status bits + n.cerr := '0'; + n.derr := '0'; + n.rbnak := '0'; + n.rberr := '0'; + end if; + n.nakcerr := '0'; -- all command rx done up to here + + case r.rcmd(c_rlink_cmd_rbf_code) is -- main command dispatcher + when c_rlink_cmd_rreg => -- rreg ---------------- + n.rbaval := '1'; -- prepare rbus cycle + n.state := s_rstart; -- next: start read reg + when c_rlink_cmd_rblk => -- rblk ---------------- + n.state := s_txcnt; + when c_rlink_cmd_wreg => -- wreg ---------------- + n.rbaval := '1'; -- prepare rbus cycle + n.state := s_wstart; -- next: start write reg + when c_rlink_cmd_wblk => -- wblk ---------------- + n.nakderr := '1'; -- set derr on eop/nak abort + n.state := s_rxdatl; + when c_rlink_cmd_stat => -- stat ---------------- + n.state := s_txccmd; + when c_rlink_cmd_attn => -- attn ---------------- + n.state := s_attn; + + when c_rlink_cmd_init => -- init ---------------- + n.rbinit := '1'; -- send init pulse + if r.addr(7 downto 3) = "11111" then -- is internal init + if r.addr(2 downto 0) = "111" then -- is rri init + n.anena := r.dih(c_rlink_iint_rbf_anena - 8); + n.itoena := r.dih(c_rlink_iint_rbf_itoena - 8); + n.itoval := r.dil(ITOWIDTH-1 downto 0); + -- note: itocnt will load in next + -- cycle because ito_go=0, so no + -- action required here + + end if; + else -- is external init + n.rbwe := '1'; -- send init with we + end if; + n.state := s_txstat; + + when others => -- '111' --------------- + n.state := s_txnak; -- send NAK on reserved command + end case; + end if; + + when s_txcnt => -- s_txcnt: send cnt ----------------- + ido := '0' & r.cnt; -- send cnt + ival := '1'; + if RL_HOLD = '0' then -- wait for accept + ocrcena := '1'; -- update output crc + n.rbaval := '1'; -- prepare rbus cycle + n.state := s_rstart; -- next: start first read reg + end if; + + when s_rstart => -- s_rstart: start reg or blk read --- + n.rbaval := '1'; -- start actual read cycle + n.rbre := '1'; + n.state := s_rreg; -- next: reg read + + when s_rreg => -- s_rreg: do reg or blk read -------- + -- this state handles all rbus reads + ato_go := '1'; -- activate timeout counter + if RB_SRES.err = '1' then -- latch rbus error flag + n.rberr := '1'; + end if; + n.doh := RB_SRES.dout(15 downto 8); -- latch data + n.dol := RB_SRES.dout( 7 downto 0); + n.stat := RB_STAT; -- latch external status bits + if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout + if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy + n.rbnak := '1'; -- set rbus nak flag + elsif RB_SRES.ack = '0' then -- if non-busy and no ack + n.rbnak := '1'; -- set rbus nak flag + end if; + n.state := s_txdatl; -- next: send data lsb + else -- otherwise rbus read continues + n.rbaval := '1'; -- extend cycle + n.rbre := '1'; + end if; + + when s_txdatl => -- s_txdatl: send data low ----------- + ido := '0' & r.dol; -- send data + ival := '1'; + if RL_HOLD = '0' then -- wait for accept + ocrcena := '1'; -- update output crc + n.state := s_txdath; -- next: send data msb + end if; + + when s_txdath => -- s_txdath: send data high + ido := '0' & r.doh; -- send data + ival := '1'; + if RL_HOLD = '0' then -- wait for accept + ocrcena := '1'; -- update output crc + if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk + n.state := s_blk; -- next: block count handling + else -- otherwise + n.state := s_txstat; -- next: send stat + end if; + end if; + + when s_wstart => -- s_wstart: start reg or blk write -- + n.rbaval := '1'; -- start actual write cycle + n.rbwe := '1'; + n.state := s_wreg; -- next: reg write + + when s_wreg => -- s_wreg: do reg or blk write ------- + -- this state handles all rbus writes + ato_go := '1'; -- activate timeout counter + if RB_SRES.err = '1' then -- latch rbus error flag + n.rberr := '1'; + end if; + n.stat := RB_STAT; -- latch external status bits + if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout + if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy + n.rbnak := '1'; -- set rbus nak flag + elsif RB_SRES.ack='0' then -- if non-busy and no ack + n.rbnak := '1'; -- set rbus nak flag + end if; + if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_wblk then -- if wblk + n.state := s_blk; -- next: block count handling + else -- otherwise + n.state := s_txstat; -- next: send stat + end if; + else -- otherwise rbus write continues + n.rbaval := '1'; -- extend cycle + n.rbwe := '1'; + end if; + + when s_blk => -- s_blk: block count handling ------- + n.cnt := unsigned(r.cnt) - 1; -- decrement transfer count + if unsigned(r.cnt) = 0 then -- if last transfer + if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk + n.state := s_txstat; -- next: send stat + else -- otherwise + n.state := s_rxdcrc; -- next: read data crc + end if; + + else -- otherwise more to transfer + if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk + n.rbaval := '1'; -- prepare rbus cycle + n.state := s_rstart; -- next: start read blk + else -- otherwise + n.state := s_rxdatl; -- next: read data + end if; + end if; + + when s_rxdcrc => -- s_rxdcrc: wait for data crc ------- + ibusy := '0'; -- accept input + if RL_ENA = '1' then + if is_comma = '1' then -- if comma + do_comma_abort(n.state, n.nakeop, comma_typ); + else + if idi8 /= ICRC_OUT then -- if crc error + n.derr := '1'; -- set data error flag + end if; + n.state := s_txstat; -- next: echo command + end if; + end if; + + when s_attn => -- s_attn: handle attention flags ---- + n.dol := r.attn(7 downto 0); -- move attention flags to do buffer + n.doh := r.attn(15 downto 8); + n.attn := RB_LAM; -- LAM in current cycle send next time + n.andone := '0'; -- reenable attn nofification + n.state := s_txdatl; -- next: send data lsb + + when s_txccmd => -- s_txccmd: send last command + ido := '0' & r.ccmd; -- send last accepted command + ival := '1'; + if RL_HOLD = '0' then -- wait for accept + ocrcena := '1'; -- update output crc + n.state := s_txdatl; -- next: send last data lsb + end if; + + when s_txstat => -- s_txstat: send status ------------- + ido := (others=>'0'); + ido(c_rlink_stat_rbf_stat) := r.stat; + ido(c_rlink_stat_rbf_attn) := has_attn; + ido(c_rlink_stat_rbf_cerr) := r.cerr; + ido(c_rlink_stat_rbf_derr) := r.derr; + ido(c_rlink_stat_rbf_rbnak) := r.rbnak; + ido(c_rlink_stat_rbf_rberr) := r.rberr; + ival := '1'; + if RL_HOLD ='0' then -- wait for accept + ocrcena := '1'; -- update output crc + n.state := s_txcrc; -- next: send crc + end if; + + when s_txcrc => -- s_txcrc: send crc ----------------- + ido := "0" & OCRC_OUT; -- send crc code + ival := '1'; + if RL_HOLD = '0' then -- wait for accept + -- if dcrc seen in wblk + if r.rcmd(c_rlink_cmd_rbf_code)=c_rlink_cmd_wblk and r.derr='1' then + n.state := s_txnak; -- next: send nak + else -- otherwise + n.nakcerr := '0'; -- clear 'set on nak' requests + n.nakderr := '0'; + n.state := s_rxcmd; -- next: read command or eop + end if; + end if; + + when others => null; -- <> -------------------------------- + end case; + + if ato_go = '0' then -- handle access timeout counter + n.atocnt := atocnt_init; -- if ato_go=0, keep in reset + else + n.atocnt := unsigned(r.atocnt) - 1;-- otherwise count down + end if; + + if ito_go = '0' then -- handle idle timeout counter + n.itocnt := r.itoval; -- if ito_go=0, keep at start value + else + if CE_INT = '1' then + n.itocnt := unsigned(r.itocnt) - 1;-- otherwise count down every CE_INT + end if; + end if; + + N_REGS <= n; + + RL_BUSY <= ibusy; + RL_DO <= ido; + RL_VAL <= ival; + + RL_MONI.eop <= r.moneop; + RL_MONI.attn <= r.monattn; + RL_MONI.lamp <= r.monlamp; + + RB_MREQ <= rb_mreq_init; + RB_MREQ.aval <= r.rbaval; + RB_MREQ.re <= r.rbre; + RB_MREQ.we <= r.rbwe; + RB_MREQ.init <= r.rbinit; + RB_MREQ.addr <= r.addr; + RB_MREQ.din <= r.dih & r.dil; + + CRC_RESET <= crcreset; + ICRC_ENA <= icrcena; + OCRC_ENA <= ocrcena; + OCRC_IN <= ido(7 downto 0); + + end process proc_next; + +end syn; Index: rtl/vlib/rlink/rlink_mon.vhd =================================================================== --- rtl/vlib/rlink/rlink_mon.vhd (nonexistent) +++ rtl/vlib/rlink/rlink_mon.vhd (revision 9) @@ -0,0 +1,147 @@ +-- $Id: rlink_mon.vhd 348 2010-12-26 15:23:44Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rlink_mon - sim +-- Description: rlink monitor (for tb's) +-- +-- Dependencies: - +-- Test bench: - +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-24 347 3.0.1 rename: CP_*->RL->* +-- 2010-12-22 346 3.0 renamed rritb_cpmon -> rlink_mon +-- 2010-06-11 303 2.5.1 fix data9 assignment, always proper width now +-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining +-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits +-- 2007-09-09 81 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.simlib.all; +use work.rlinklib.all; + +entity rlink_mon is -- rlink monitor + generic ( + DWIDTH : positive := 9); -- data port width (8 or 9) + port ( + CLK : in slbit; -- clock + CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number + ENA : in slbit := '1'; -- enable monitor output + RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in + RL_ENA : in slbit; -- rlink: data enable + RL_BUSY : in slbit; -- rlink: data busy + RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out + RL_VAL : in slbit; -- rlink: data valid + RL_HOLD : in slbit -- rlink: data hold + ); +end rlink_mon; + + +architecture sim of rlink_mon is + +begin + + assert DWIDTH=8 or DWIDTH=9 + report "assert(DWIDTH=8 or DWIDTH=9)" severity failure; + + proc_moni: process + variable oline : line; + variable nbusy : integer := 0; + variable nhold : integer := 0; + + procedure write_val(L: inout line; + data: in slv(DWIDTH-1 downto 0); + nwait: in integer; + txt1: in string; + txt2: in string) is + variable data9 : slv9 := (others=>'0'); + begin + + writetimestamp(L, CLK_CYCLE, txt1); + + if DWIDTH = 9 then + write(L, data(data'left), right, 1); + else + write(L, string'(" ")); + end if; + + write(L, data(7 downto 0), right, 9); + if nwait > 0 then + write(L, txt2); + write(L, nwait); + end if; + + if DWIDTH=9 and data(data'left)='1' then + -- a copy to data9 needed to allow following case construct + -- using data directly gives a 'subtype is not locally static' error + data9 := (others=>'0'); + data9(data'range) := data; + write(L, string'(" comma")); + case data9 is + when c_rlink_dat_idle => write(L, string'(" idle")); + when c_rlink_dat_sop => write(L, string'(" sop")); + when c_rlink_dat_eop => write(L, string'(" eop")); + when c_rlink_dat_nak => write(L, string'(" nak")); + when c_rlink_dat_attn => write(L, string'(" attn")); + when others => null; + end case; + end if; + + writeline(output, L); + end procedure write_val; + + begin + + loop + + if ENA='0' then -- if disabled + wait until ENA='1'; -- stall process till enabled + end if; + + wait until CLK'event and CLK='1'; -- check at end of clock cycle + + if RL_ENA = '1' then + if RL_BUSY = '1' then + nbusy := nbusy + 1; + else + write_val(oline, RL_DI, nbusy, ": rlrx ", " nbusy="); + nbusy := 0; + end if; + else + nbusy := 0; + end if; + + if RL_VAL = '1' then + if RL_HOLD = '1' then + nhold := nhold + 1; + else + write_val(oline, RL_DO, nhold, ": rltx ", " nhold="); + nhold := 0; + end if; + else + nhold := 0; + end if; + + end loop; + end process proc_moni; + +end sim; Index: rtl/vlib/rlink/rlinklib.vbom =================================================================== --- rtl/vlib/rlink/rlinklib.vbom (nonexistent) +++ rtl/vlib/rlink/rlinklib.vbom (revision 9) @@ -0,0 +1,4 @@ +# libs +../slvtypes.vhd +../rbus/rblib.vhd +rlinklib.vhd Index: rtl/vlib/rlink/rlink_base.vbom =================================================================== --- rtl/vlib/rlink/rlink_base.vbom (nonexistent) +++ rtl/vlib/rlink/rlink_base.vbom (revision 9) @@ -0,0 +1,11 @@ +# libs +../slvtypes.vhd +../rbus/rblib.vhd +rlinklib.vbom +# components +rlink_core.vbom +rlink_rlb2rl.vbom +[ghdl,isim]rlink_mon_sb.vbom +[ghdl,isim]../rbus/rb_mon_sb.vbom +# design +rlink_base.vhd Index: rtl/vlib/rlink/Makefile =================================================================== --- rtl/vlib/rlink/Makefile (nonexistent) +++ rtl/vlib/rlink/Makefile (revision 9) @@ -0,0 +1,22 @@ +# $Id: Makefile 343 2010-12-05 21:24:38Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2007-12-09 100 1.0.1 drop ISE_p definition +# 2007-07-06 64 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +.phony : all clean +# +all : $(NGC_all) +# +clean : ise_clean +# +#---- +# +include $(RETROBASE)/rtl/vlib/Makefile.xflow +# +include $(VBOM_all:.vbom=.dep_xst) +# Index: rtl/vlib/rlink/rlink_serport.vhd =================================================================== --- rtl/vlib/rlink/rlink_serport.vhd (nonexistent) +++ rtl/vlib/rlink/rlink_serport.vhd (revision 9) @@ -0,0 +1,235 @@ +-- $Id: rlink_serport.vhd 350 2010-12-28 16:40:11Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rlink_serport - syn +-- Description: rlink: serport adapter (serial to rlink_base) +-- +-- Dependencies: serport/serport_uart_rxtx_ab +-- +-- Test bench: tb/tb_rlink_serport +-- +-- Target Devices: generic +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2010-12-26 348 12.1 M53d xc3s1000-4 122 227 - 152 s 9.8 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-25 348 3.1 re-written, is now a serial to rlink_base adapter +-- 2010-12-24 347 3.0.1 rename: CP_*->RL->* +-- 2010-12-04 343 3.0 renamed rri_ -> rlink_ +-- 2010-06-06 301 2.3 use NCOMM=4 (new eop,nak commas) +-- 2010-06-03 300 2.2.1 use FAWIDTH=5 +-- 2010-05-02 287 2.2 drop RTSFLUSH generic +-- 2010-04-18 279 2.1 rewrite flow control, drop RTSFBUF generic +-- 2010-04-03 274 2.0 flow control interfaces: RTSFLUSH, CTS_N, RTS_N +-- 2007-06-24 60 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.slvtypes.all; +use work.serport.all; +use work.rblib.all; +use work.rlinklib.all; + +entity rlink_serport is -- rlink serport adapter + generic ( + RB_ADDR : slv8 := conv_std_logic_vector(2#11111110#,8); + CDWIDTH : positive := 13; -- clk divider width + CDINIT : natural := 15); -- clk divider initial/reset setting + port ( + CLK : in slbit; -- clock + CE_USEC : in slbit; -- 1 usec clock enable + CE_MSEC : in slbit; -- 1 msec clock enable + RESET : in slbit; -- reset + RXSD : in slbit; -- receive serial data (board view) + TXSD : out slbit; -- transmit serial data (board view) + CTS_N : in slbit := '0'; -- clear to send (act.low, board view) + RTS_N : out slbit; -- request to send (act.low, board view) + RLB_DI : out slv8; -- rlink 8b: data in + RLB_ENA : out slbit; -- rlink 8b: data enable + RLB_BUSY : in slbit; -- rlink 8b: data busy + RLB_DO : in slv8; -- rlink 8b: data out + RLB_VAL : in slbit; -- rlink 8b: data valid + RLB_HOLD : out slbit; -- rlink 8b: data hold + RB_MREQ : in rb_mreq_type; -- rbus: request (for inits only) + IFIFO_SIZE : in slv4; -- rlink_rlb2rb: input fifo size + RL_MONI : in rl_moni_type; -- rlink_core: monitor port + RL_SER_MONI : out rl_ser_moni_type -- rlink_serport: monitor port + ); +end rlink_serport; + + +architecture syn of rlink_serport is + + type regs_type is record + flpend : slbit; -- flush pending + fldbusy : slbit; -- flush delay busy + fldcnt : slv3; -- flush delay counter + flpbusy : slbit; -- flush pulse busy + flpcnt : slv3; -- flush pulse counter + ffblock : slbit; -- fifo block + fena : slbit; -- flush enable + fwidth : slv3; -- flush pulse width + fdelay : slv3; -- flush pulse delay + rtsoff : slv3; -- rts off level (fifo high water) + rtson : slv3; -- rts on level (fifo low water) + end record regs_type; + + constant regs_init : regs_type := ( + '0','0',"000", -- flpend,fldbusy,fldcnt + '0',"000", -- flpbusy,flpcnt + '0', -- ffblock + '0', -- fena + "000","000", -- fwidth,fdelay + "111","110" -- rtsoff,rtson + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + signal RXVAL : slbit := '0'; + signal RXERR : slbit := '0'; + signal RXACT : slbit := '0'; + signal TXBUSY : slbit := '0'; + signal ABACT : slbit := '0'; + signal ABDONE : slbit := '0'; + signal ABCLKDIV : slv16 := (others=>'0'); + +begin + + assert CDWIDTH<=16 + report "assert(CDWIDTH<=16): max width of UART clock divider" + severity failure; + + UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo + generic map ( + CDWIDTH => CDWIDTH, + CDINIT => CDINIT) + port map ( + CLK => CLK, + CE_MSEC => CE_MSEC, + RESET => RESET, + RXSD => RXSD, + RXDATA => RLB_DI, + RXVAL => RXVAL, + RXERR => RXERR, + RXACT => RXACT, + TXSD => TXSD, + TXDATA => RLB_DO, + TXENA => RLB_VAL, + TXBUSY => TXBUSY, + ABACT => ABACT, + ABDONE => ABDONE, + ABCLKDIV => ABCLKDIV(CDWIDTH-1 downto 0) + ); + + proc_regs: process (CLK) + begin + + if CLK'event and CLK='1' then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, RB_MREQ, IFIFO_SIZE, RL_MONI, TXBUSY, CE_USEC) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + begin + + r := R_REGS; + n := R_REGS; + + -- handle init + if RB_MREQ.init='1' and RB_MREQ.we='0' and RB_MREQ.addr=RB_ADDR then + n.fena := RB_MREQ.din(c_rlink_serport_rbf_fena); + n.fwidth := RB_MREQ.din(c_rlink_serport_rbf_fwidth); + n.fdelay := RB_MREQ.din(c_rlink_serport_rbf_fdelay); + n.rtsoff := RB_MREQ.din(c_rlink_serport_rbf_rtsoff); + n.rtson := RB_MREQ.din(c_rlink_serport_rbf_rtson); + end if; + + -- fifo back preasure + if IFIFO_SIZE(3)='1' or + unsigned(IFIFO_SIZE(2 downto 0))>unsigned(r.rtsoff) then + n.ffblock := '1'; + elsif unsigned(IFIFO_SIZE(2 downto 0)) <= unsigned(r.rtson) then + n.ffblock := '0'; + end if; + + -- send flush pulse if + -- eop send unless a pending attn + -- or an attn was send + + if (RL_MONI.eop='1' and RL_MONI.lamp='0') or RL_MONI.attn='1' then + n.flpend := r.fena; + end if; + + -- flush pulse logic + -- start delay when flpend is set + -- re-start delay when TXBUSY=1 + -- when timer expires, clear flpend, start pulse + + if r.flpend='1' and (r.fldbusy='0' or TXBUSY='1') then + n.fldbusy := '1'; + n.fldcnt := r.fdelay; + elsif CE_USEC='1' and r.fldbusy='1' then + if unsigned(r.fldcnt) = 0 then + n.flpend := '0'; + n.fldbusy := '0'; + n.flpbusy := '1'; + n.flpcnt := r.fwidth; + else + n.fldcnt := unsigned(r.fldcnt) - 1; + end if; + end if; + + if CE_USEC='1' and r.flpbusy='1' then + if unsigned(r.flpcnt) = 0 then + n.flpbusy := '0'; + else + n.flpcnt := unsigned(r.flpcnt) - 1; + end if; + end if; + + N_REGS <= n; + + end process proc_next; + + RTS_N <= R_REGS.ffblock or R_REGS.flpbusy; + + RLB_ENA <= RXVAL; + RLB_HOLD <= TXBUSY or CTS_N; + + RL_SER_MONI.rxerr <= RXERR; + RL_SER_MONI.rxdrop <= RXVAL and RLB_BUSY; + RL_SER_MONI.rxact <= RXACT; + RL_SER_MONI.txact <= TXBUSY; + RL_SER_MONI.abact <= ABACT; + RL_SER_MONI.abdone <= ABDONE; + RL_SER_MONI.clkdiv <= ABCLKDIV; + +end syn; Index: rtl/vlib/rlink/rlink_rlb2rl.vhd =================================================================== --- rtl/vlib/rlink/rlink_rlb2rl.vhd (nonexistent) +++ rtl/vlib/rlink/rlink_rlb2rl.vhd (revision 9) @@ -0,0 +1,209 @@ +-- $Id: rlink_rlb2rl.vhd 350 2010-12-28 16:40:11Z mueller $ +-- +-- Copyright 2010- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rlink_rlb2rl - syn +-- Description: rlink 8 bit(rlb) to 9 bit(rl) adapter +-- +-- Dependencies: comlib/byte2cdata +-- comlib/cdata2byte +-- memlib/fifo_1c_dram +-- +-- Test bench: tb/rb_rlink_serport +-- +-- Target Devices: generic +-- Tool versions: xst 12.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa +-- 2010-12-25 348 12.1 M53d xc3s1000-4 61 121 72 114 s 8.3 5 5 +-- 2010-12-25 348 12.1 M53d xc3s1000-4 41 84 36 73 s 8.3 5 0 +-- 2010-12-25 348 12.1 M53d xc3s1000-4 22 50 - 30 s 4.5 0 0 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-24 348 1.0 Initial version +------------------------------------------------------------------------------ +-- +-- byte2cdata fifo_1c_dram +-- +--------------+ +--------------+ +-- | | | | +-- RLB_DI ->| DI DO |--->| DI DO |-> RL_DI +-- | | | | +-- RLB_ENA ->| ENA VAL |--->| ENA VAL |-> RL_ENA +-- | | | | +-- RLB_BUSY <-| BUSY HOLD |<---| BUSY HOLD |<- RL_BUSY +-- | | | | +-- +--------------+ | | +-- | | +-- +---+ | | +-- IFIFO_FILL <------------|map|<---| SIZE | +-- +---+ +--------------+ +-- +-- +-- cdata2byte fifo_1c_dram +-- +--------------+ +--------------+ +-- | | | | +-- RLB_DO <-| DO DI |<---| DO DI |<- RL_DO +-- | | | | +-- RLB_VAL <-| VAL ENA |<---| VAL ENA |<- RL_VAL +-- | | | | +-- RLB_HOLD ->| HOLD BUSY |--->| HOLD BUSY |-> RL_HOLD +-- | | | | +-- +--------------+ | | +-- | | +-- +---+ | | +-- OFIFO_FILL <------------|map|<---| SIZE | +-- +---+ +--------------+ +-- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.slvtypes.all; +use work.comlib.all; +use work.memlib.all; +use work.rlinklib.all; + +entity rlink_rlb2rl is -- rlink 8 bit(rlb) to 9 bit(rl) adapter + generic ( + CPREF : slv4 := "1000"; -- comma prefix + IFAWIDTH : natural := 5; -- input fifo address width (0=none) + OFAWIDTH : natural := 5); -- output fifo address width (0=none) + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + RLB_DI : in slv8; -- rlink 8bit: data in + RLB_ENA : in slbit; -- rlink 8bit: data enable + RLB_BUSY : out slbit; -- rlink 8bit: data busy + RLB_DO : out slv8; -- rlink 8bit: data out + RLB_VAL : out slbit; -- rlink 8bit: data valid + RLB_HOLD : in slbit; -- rlink 8bit: data hold + IFIFO_SIZE : out slv4; -- input fifo size (4 msb's) + OFIFO_SIZE : out slv4; -- output fifo fill (4 msb's) + RL_DI : out slv9; -- rlink 9bit: data in + RL_ENA : out slbit; -- rlink 9bit: data enable + RL_BUSY : in slbit; -- rlink 9bit: data busy + RL_DO : in slv9; -- rlink 9bit: data out + RL_VAL : in slbit; -- rlink 9bit: data valid + RL_HOLD : out slbit -- rlink 9bit: data hold + ); +end rlink_rlb2rl; + +architecture syn of rlink_rlb2rl is + + signal RLB_BUSY_L : slbit := '0'; + signal IFIFO_DI : slv9 := (others=>'0'); + signal IFIFO_ENA : slbit := '0'; + signal IFIFO_BUSY : slbit := '0'; + signal OFIFO_DO : slv9 := (others=>'0'); + signal OFIFO_VAL : slbit := '0'; + signal OFIFO_HOLD : slbit := '0'; + +begin + +-- RLB -> RL converter (DI handling) ------------- + + B2CD : byte2cdata -- byte stream -> 9bit comma,data + generic map ( + CPREF => CPREF, + NCOMM => c_rlink_ncomm) + port map ( + CLK => CLK, + RESET => RESET, + DI => RLB_DI, + ENA => RLB_ENA, + BUSY => RLB_BUSY_L, + DO => IFIFO_DI, + VAL => IFIFO_ENA, + HOLD => IFIFO_BUSY + ); + + DOIFIFO: if IFAWIDTH > 0 generate + signal SIZE: slv(IFAWIDTH downto 0) := (others=>'0'); + begin + IFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based + generic map ( + AWIDTH => IFAWIDTH, + DWIDTH => 9) + port map ( + CLK => CLK, + RESET => RESET, + DI => IFIFO_DI, + ENA => IFIFO_ENA, + BUSY => IFIFO_BUSY, + DO => RL_DI, + VAL => RL_ENA, + HOLD => RL_BUSY, + SIZE => SIZE + ); + IFIFO_SIZE <= SIZE(IFAWIDTH downto IFAWIDTH-3); + end generate DOIFIFO; + + NOIFIFO: if IFAWIDTH = 0 generate + RL_DI <= IFIFO_DI; + RL_ENA <= IFIFO_ENA; + IFIFO_BUSY <= RL_BUSY; + IFIFO_SIZE <= RLB_BUSY_L & "000"; + end generate NOIFIFO; + + RLB_BUSY <= RLB_BUSY_L; + +-- RL -> RLB converter (DO handling) ------------- + + CD2B : cdata2byte -- 9bit comma,data -> byte stream + generic map ( + CPREF => CPREF, + NCOMM => c_rlink_ncomm) + port map ( + CLK => CLK, + RESET => RESET, + DI => OFIFO_DO, + ENA => OFIFO_VAL, + BUSY => OFIFO_HOLD, + DO => RLB_DO, + VAL => RLB_VAL, + HOLD => RLB_HOLD + ); + + DOOFIFO: if OFAWIDTH > 0 generate + signal SIZE : slv(OFAWIDTH downto 0) := (others=>'0'); + begin + OFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based + generic map ( + AWIDTH => OFAWIDTH, + DWIDTH => 9) + port map ( + CLK => CLK, + RESET => RESET, + DI => RL_DO, + ENA => RL_VAL, + BUSY => RL_HOLD, + DO => OFIFO_DO, + VAL => OFIFO_VAL, + HOLD => OFIFO_HOLD, + SIZE => SIZE + ); + OFIFO_SIZE <= SIZE(OFAWIDTH downto OFAWIDTH-3); + end generate DOOFIFO; + + NOOFIFO: if OFAWIDTH = 0 generate + OFIFO_DO <= RL_DO; + OFIFO_VAL <= RL_VAL; + RL_HOLD <= OFIFO_HOLD; + OFIFO_SIZE <= OFIFO_HOLD & "000"; + end generate NOOFIFO; + +end syn; Index: rtl/vlib/rlink/rlink_mon_sb.vbom =================================================================== --- rtl/vlib/rlink/rlink_mon_sb.vbom (nonexistent) +++ rtl/vlib/rlink/rlink_mon_sb.vbom (revision 9) @@ -0,0 +1,9 @@ +# libs +../slvtypes.vhd +../simlib/simlib.vhd +../simlib/simbus.vhd +rlinklib.vbom +# components +rlink_mon.vbom +# design +rlink_mon_sb.vhd Index: rtl/vlib/rlink =================================================================== --- rtl/vlib/rlink (nonexistent) +++ rtl/vlib/rlink (revision 9)
rtl/vlib/rlink Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: rtl/vlib/simlib/simlib.vhd =================================================================== --- rtl/vlib/simlib/simlib.vhd (revision 8) +++ rtl/vlib/simlib/simlib.vhd (revision 9) @@ -1,4 +1,4 @@ --- $Id: simlib.vhd 338 2010-11-13 22:19:25Z mueller $ +-- $Id: simlib.vhd 346 2010-12-22 22:59:26Z mueller $ -- -- Copyright 2006-2010 by Walter F.J. Mueller -- @@ -22,6 +22,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2010-12-22 346 1.3.7 rename readcommand -> readdotcomm -- 2010-11-13 338 1.3.6 add simclkcnt; xx.x ns time in writetimestamp() -- 2008-03-24 129 1.3.5 CLK_CYCLE now 31 bits -- 2008-03-02 121 1.3.4 added readempty (to discard rest of line) @@ -76,7 +77,7 @@ L: inout line; good: out boolean); -procedure readcommand( +procedure readdotcomm( L: inout line; name: out string; good: out boolean); @@ -471,7 +472,7 @@ -- ------------------------------------- -procedure readcommand( +procedure readdotcomm( L: inout line; name: out string; good: out boolean) is @@ -486,7 +487,7 @@ readword(L, name, good); end if; -end procedure readcommand; +end procedure readdotcomm; -- -------------------------------------
/rtl/vlib/serport/serport_uart_rxtx_ab.vhd
1,6 → 1,6
-- $Id: serport_uart_rxtx_ab.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: serport_uart_rxtx_ab.vhd 350 2010-12-28 16:40:11Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
19,9 → 19,15
-- serport_uart_rxtx
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-25 348 12.1 M53d xc3s1000-4 99 197 - 124 s 9.8
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-26 348 1.1 add ABCLKDIV port for clock divider setting
-- 2007-06-24 60 1.0 Initial version
------------------------------------------------------------------------------
 
50,7 → 56,8
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid
ABDONE : out slbit -- autobaud resync done
ABDONE : out slbit; -- autobaud resync done
ABCLKDIV : out slv(CDWIDTH-1 downto 0) -- autobaud clock divider setting
);
end serport_uart_rxtx_ab;
 
78,6 → 85,7
 
UART_RESET <= ABACT_L or RESET;
ABACT <= ABACT_L;
ABCLKDIV <= CLKDIV;
RXTX : serport_uart_rxtx
generic map (
/rtl/vlib/serport/serport.vhd
1,4 → 1,4
-- $Id: serport.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: serport.vhd 348 2010-12-26 15:23:44Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
16,9 → 16,11
-- Description: serial port interface components
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-26 348 1.2.1 add ABCLKDIV to serport_uart_rxtx_ab
-- 2010-04-10 276 1.2 add clock divider constant defs
-- 2007-10-22 88 1.1 renames (in prev revs); remove std_logic_unsigned
-- 2007-06-03 45 1.0 Initial version
112,7 → 114,8
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid
ABDONE : out slbit -- autobaud resync done
ABDONE : out slbit; -- autobaud resync done
ABCLKDIV : out slv(CDWIDTH-1 downto 0) -- autobaud clock divider setting
);
end component;
 
/rtl/vlib/comlib/byte2cdata.vhd
1,4 → 1,4
-- $Id: byte2cdata.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: byte2cdata.vhd 348 2010-12-26 15:23:44Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
18,7 → 18,8
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
41,7 → 42,7
DI : in slv8; -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv9; -- output data; bit 8 = komma flag
DO : out slv9; -- output data; bit 8 = comma flag
VAL : out slbit; -- read valid
HOLD : in slbit -- read hold
);
/rtl/vlib/comlib/cdata2byte.vhd
1,4 → 1,4
-- $Id: cdata2byte.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: cdata2byte.vhd 348 2010-12-26 15:23:44Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
18,7 → 18,8
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
38,7 → 39,7
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv9; -- input data; bit 8 = komma flag
DI : in slv9; -- input data; bit 8 = comma flag
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv8; -- output data
/rtl/vlib/rbus/rbd_tester.vbom
0,0 → 1,8
# libs
../slvtypes.vhd
../memlib/memlib.vhd
rblib.vhd
# components
../memlib/fifo_1c_dram_raw.vbom
# design
rbd_tester.vhd
/rtl/vlib/rbus/rb_mon_sb.vhd
0,0 → 1,81
-- $Id: rb_mon_sb.vhd 346 2010-12-22 22:59:26Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rb_mon_sb - sim
-- Description: simbus wrapper for rbus monitor (for tb's)
--
-- Dependencies: simbus
-- Test bench: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-22 346 3.0 renamed rritb_rbmon_sb -> rb_mon_sb
-- 2010-06-05 301 2.0.2 renamed _rpmon -> _rbmon
-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- use sbcntl_sbf_cpmon def
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2007-12-23 105 1.2 added AP_LAM display
-- 2007-11-24 98 1.1 added RP_IINT support
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.rblib.all;
 
entity rb_mon_sb is -- simbus wrapper for rbus monitor
generic (
DBASE : positive := 2; -- base for writing data values
ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end rb_mon_sb;
 
 
architecture sim of rb_mon_sb is
 
signal ENA : slbit := '0';
begin
 
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
report "assert(ENAPIN in SB_CNTL'range)" severity failure;
 
ENA <= to_x01(SB_CNTL(ENAPIN));
RBMON : rb_mon
generic map (
DBASE => DBASE)
port map (
CLK => CLK,
CLK_CYCLE => SB_CLKCYCLE,
ENA => ENA,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
end sim;
/rtl/vlib/rbus/rb_sres_or_2.vhd
0,0 → 1,75
-- $Id: rb_sres_or_2.vhd 343 2010-12-05 21:24:38Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rb_sres_or_2 - syn
-- Description: rbus result or, 2 input
--
-- Dependencies: rb_sres_or_mon [sim only]
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-04 343 1.1.1 use now rb_sres_or_mon
-- 2010-06-26 309 1.1 add rritb_sres_or_mon
-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_
-- 2008-01-20 113 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.rblib.all;
 
-- ----------------------------------------------------------------------------
 
entity rb_sres_or_2 is -- rbus result or, 2 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end rb_sres_or_2;
 
architecture syn of rb_sres_or_2 is
begin
 
proc_comb : process (RB_SRES_1, RB_SRES_2)
begin
 
RB_SRES_OR.ack <= RB_SRES_1.ack or
RB_SRES_2.ack;
RB_SRES_OR.busy <= RB_SRES_1.busy or
RB_SRES_2.busy;
RB_SRES_OR.err <= RB_SRES_1.err or
RB_SRES_2.err;
RB_SRES_OR.dout <= RB_SRES_1.dout or
RB_SRES_2.dout;
end process proc_comb;
 
-- synthesis translate_off
ORMON : rb_sres_or_mon
port map (
RB_SRES_1 => RB_SRES_1,
RB_SRES_2 => RB_SRES_2,
RB_SRES_3 => rb_sres_init,
RB_SRES_4 => rb_sres_init
);
-- synthesis translate_on
end syn;
/rtl/vlib/rbus/rb_sres_or_3.vhd
0,0 → 1,80
-- $Id: rb_sres_or_3.vhd 343 2010-12-05 21:24:38Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rb_sres_or_3 - syn
-- Description: rbus result or, 3 input
--
-- Dependencies: rb_sres_or_mon [sim only]
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-04 343 1.1.1 use now rb_sres_or_mon
-- 2010-06-26 309 1.1 add rritb_sres_or_mon
-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_
-- 2008-01-20 113 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.rblib.all;
 
-- ----------------------------------------------------------------------------
 
entity rb_sres_or_3 is -- rbus result or, 3 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end rb_sres_or_3;
 
architecture syn of rb_sres_or_3 is
begin
 
proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3)
begin
 
RB_SRES_OR.ack <= RB_SRES_1.ack or
RB_SRES_2.ack or
RB_SRES_3.ack;
RB_SRES_OR.busy <= RB_SRES_1.busy or
RB_SRES_2.busy or
RB_SRES_3.busy;
RB_SRES_OR.err <= RB_SRES_1.err or
RB_SRES_2.err or
RB_SRES_3.err;
RB_SRES_OR.dout <= RB_SRES_1.dout or
RB_SRES_2.dout or
RB_SRES_3.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : rb_sres_or_mon
port map (
RB_SRES_1 => RB_SRES_1,
RB_SRES_2 => RB_SRES_2,
RB_SRES_3 => RB_SRES_3,
RB_SRES_4 => rb_sres_init
);
-- synthesis translate_on
 
end syn;
/rtl/vlib/rbus/rb_mon_sb.vbom
0,0 → 1,9
# libs
../slvtypes.vhd
../simlib/simlib.vhd
../simlib/simbus.vhd
rblib.vhd
# components
rb_mon.vbom
# design
rb_mon_sb.vhd
/rtl/vlib/rbus/rb_sres_or_2.vbom
0,0 → 1,7
# libs
../slvtypes.vhd
rblib.vhd
# components
[ghdl,isim]rb_sres_or_mon.vbom
# design
rb_sres_or_2.vhd
/rtl/vlib/rbus/rb_sres_or_3.vbom
0,0 → 1,7
# libs
../slvtypes.vhd
rblib.vhd
# components
[ghdl,isim]rb_sres_or_mon.vbom
# design
rb_sres_or_3.vhd
/rtl/vlib/rbus/rb_sres_or_mon.vhd
0,0 → 1,111
-- $Id: rb_sres_or_mon.vhd 347 2010-12-24 12:10:42Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rb_sres_or_mon - sim
-- Description: rbus result or monitor
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-23 347 3.0 rename rritb_sres_or_mon->rb_sres_or_mon
-- 2010-10-28 336 1.0.1 log errors only if now>0ns (drop startup glitches)
-- 2010-06-26 309 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.rblib.all;
 
-- ----------------------------------------------------------------------------
 
entity rb_sres_or_mon is -- rbus result or monitor
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_4 : in rb_sres_type := rb_sres_init -- rb_sres input 4
);
end rb_sres_or_mon;
 
architecture sim of rb_sres_or_mon is
begin
 
proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3, RB_SRES_4)
constant dzero : slv16 := (others=>'0');
variable oline : line;
variable nack : integer := 0;
variable nbusy : integer := 0;
variable nerr : integer := 0;
variable ndout : integer := 0;
begin
 
nack := 0;
nbusy := 0;
nerr := 0;
ndout := 0;
if RB_SRES_1.ack /= '0' then nack := nack + 1; end if;
if RB_SRES_2.ack /= '0' then nack := nack + 1; end if;
if RB_SRES_3.ack /= '0' then nack := nack + 1; end if;
if RB_SRES_4.ack /= '0' then nack := nack + 1; end if;
 
if RB_SRES_1.busy /= '0' then nbusy := nbusy + 1; end if;
if RB_SRES_2.busy /= '0' then nbusy := nbusy + 1; end if;
if RB_SRES_3.busy /= '0' then nbusy := nbusy + 1; end if;
if RB_SRES_4.busy /= '0' then nbusy := nbusy + 1; end if;
 
if RB_SRES_1.err /= '0' then nerr := nerr + 1; end if;
if RB_SRES_2.err /= '0' then nerr := nerr + 1; end if;
if RB_SRES_3.err /= '0' then nerr := nerr + 1; end if;
if RB_SRES_4.err /= '0' then nerr := nerr + 1; end if;
 
if RB_SRES_1.dout /= dzero then ndout := ndout + 1; end if;
if RB_SRES_2.dout /= dzero then ndout := ndout + 1; end if;
if RB_SRES_3.dout /= dzero then ndout := ndout + 1; end if;
if RB_SRES_4.dout /= dzero then ndout := ndout + 1; end if;
 
if now > 0 ns and (nack>1 or nbusy>1 or nerr>1 or ndout>1) then
write(oline, now, right, 12);
if nack > 1 then
write(oline, string'(" #ack="));
write(oline, nack);
end if;
if nbusy > 1 then
write(oline, string'(" #busy="));
write(oline, nbusy);
end if;
if nerr > 1 then
write(oline, string'(" #err="));
write(oline, nerr);
end if;
if ndout > 1 then
write(oline, string'(" #dout="));
write(oline, ndout);
end if;
write(oline, string'(" FAIL in "));
write(oline, rb_sres_or_mon'path_name);
writeline(output, oline);
end if;
end process proc_comb;
end sim;
/rtl/vlib/rbus/rb_sres_or_mon.vbom
0,0 → 1,5
# libs
../slvtypes.vhd
rblib.vhd
# design
rb_sres_or_mon.vhd
/rtl/vlib/rbus/rblib.vhd
0,0 → 1,193
-- $Id: rblib.vhd 349 2010-12-28 14:02:13Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: rblib
-- Description: Definitions for rbus interface and bus entities
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-26 349 3.0.2 add rb_sel
-- 2010-12-22 346 3.0.1 add rb_mon and rb_mon_sb;
-- 2010-12-04 343 3.0 extracted from rrilib and rritblib;
-- rbus V3 interface: use aval,re,we
-- ... rrilib history removed ...
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package rblib is
 
type rb_mreq_type is record -- rbus - master request
aval : slbit; -- address valid
re : slbit; -- read enable
we : slbit; -- write enable
init : slbit; -- init
addr : slv8; -- address
din : slv16; -- data (input to slave)
end record rb_mreq_type;
 
constant rb_mreq_init : rb_mreq_type :=
('0','0','0','0', -- aval, re, we, init
(others=>'0'), -- addr
(others=>'0')); -- din
 
type rb_sres_type is record -- rbus - slave response
ack : slbit; -- acknowledge
busy : slbit; -- busy
err : slbit; -- error
dout : slv16; -- data (output from slave)
end record rb_sres_type;
 
constant rb_sres_init : rb_sres_type :=
('0','0','0', -- ack, busy, err
(others=>'0')); -- dout
 
component rb_sel is -- rbus address select logic
generic (
RB_ADDR : slv8; -- rbus address base
SAWIDTH : natural := 0); -- device subaddress space width
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus request
SEL : out slbit -- select state bit
);
end component;
 
component rb_sres_or_2 is -- rbus result or, 2 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end component;
component rb_sres_or_3 is -- rbus result or, 3 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end component;
component rb_sres_or_4 is -- rbus result or, 4 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end component;
 
component rbus_aif is -- rbus, abstract interface
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv3 -- rbus: status flags
);
end component;
 
component rb_wreg_rw_3 is -- rbus: wide register r/w 3 bit select
generic (
DWIDTH : positive := 16);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
FADDR : slv3; -- field address
SEL : slbit; -- select
DATA : out slv(DWIDTH-1 downto 0); -- data
RB_MREQ : in rb_mreq_type; -- rbus request
RB_SRES : out rb_sres_type -- rbus response
);
end component;
 
component rb_wreg_w_3 is -- rbus: wide register w-o 3 bit select
generic (
DWIDTH : positive := 16);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
FADDR : slv3; -- field address
SEL : slbit; -- select
DATA : out slv(DWIDTH-1 downto 0); -- data
RB_MREQ : in rb_mreq_type; -- rbus request
RB_SRES : out rb_sres_type -- rbus response
);
end component;
 
component rb_wreg_r_3 is -- rbus: wide register r-o 3 bit select
generic (
DWIDTH : positive := 16);
port (
FADDR : slv3; -- field address
SEL : slbit; -- select
DATA : in slv(DWIDTH-1 downto 0); -- data
RB_SRES : out rb_sres_type -- rbus response
);
end component;
 
--
-- components for use in test benches (not synthesizable)
--
 
component rb_sres_or_mon is -- rbus result or monitor
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_4 : in rb_sres_type := rb_sres_init -- rb_sres input 4
);
end component;
 
-- simbus sb_cntl field usage for rbus
constant sbcntl_sbf_rbmon : integer := 14;
 
component rb_mon is -- rbus monitor
generic (
DBASE : positive := 2); -- base for writing data values
port (
CLK : in slbit; -- clock
CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end component;
 
component rb_mon_sb is -- simbus wrapper for rbus monitor
generic (
DBASE : positive := 2; -- base for writing data values
ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end component;
 
 
end rblib;
/rtl/vlib/rbus/rb_mon.vhd
0,0 → 1,149
-- $Id: rb_mon.vhd 346 2010-12-22 22:59:26Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rb_mon - sim
-- Description: rbus monitor (for tb's)
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-22 346 3.0 renamed rritb_rbmon -> rb_mon
-- 2010-06-05 301 2.1.1 renamed _rpmon -> _rbmon
-- 2010-06-03 299 2.1 new init encoding (WE=0/1 int/ext)
-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2008-03-24 129 1.2.1 CLK_CYCLE now 31 bits
-- 2007-12-23 105 1.2 added AP_LAM display
-- 2007-11-24 98 1.1 added RP_IINT support
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.simlib.all;
use work.rblib.all;
 
entity rb_mon is -- rbus monitor (for tb's)
generic (
DBASE : positive := 2); -- base for writing data values
port (
CLK : in slbit; -- clock
CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end rb_mon;
 
 
architecture sim of rb_mon is
begin
 
proc_moni: process
variable oline : line;
variable nhold : integer := 0;
variable data : slv16 := (others=>'0');
variable tag : string(1 to 8) := (others=>' ');
variable err : slbit := '0';
 
procedure write_data(L: inout line;
tag: in string;
data: in slv16;
nhold: in integer := 0;
cond: in boolean := false;
ctxt: in string := " ") is
begin
writetimestamp(L, CLK_CYCLE, tag);
write(L, RB_MREQ.addr, right, 10);
write(L, string'(" "));
writegen(L, data, right, 0, DBASE);
write(L, RB_STAT, right, 4);
if nhold > 0 then
write(L, string'(" nhold="));
write(L, nhold);
end if;
if cond then
write(L, ctxt);
end if;
writeline(output, L);
end procedure write_data;
 
begin
loop
 
if ENA = '0' then -- if disabled
wait until ENA='1'; -- stall process till enabled
end if;
 
wait until CLK'event and CLK='1'; -- check at end of clock cycle
 
if RB_MREQ.aval='1' and (RB_MREQ.re='1' or RB_MREQ.we='1') then
if RB_SRES.err = '1' then
err := '1';
end if;
if RB_SRES.busy = '1' then
nhold := nhold + 1;
else
data := (others=>'0');
tag := ": ???? ";
if RB_MREQ.re = '1' then
data := RB_SRES.dout;
tag := ": rbre ";
end if;
if RB_MREQ.we = '1' then
data := RB_MREQ.din;
tag := ": rbwe ";
end if;
 
write_data(oline, tag, data, nhold, err='1', " ERR='1'");
nhold := 0;
end if;
else
if nhold > 0 then
write_data(oline, tag, data, nhold, true, " TIMEOUT");
end if;
nhold := 0;
err := '0';
end if;
 
if RB_MREQ.init = '1' then -- init
if RB_MREQ.we = '1' then
write_data(oline, ": rbini ", RB_MREQ.din); -- external
else
write_data(oline, ": rbint ", RB_MREQ.din); -- internal
end if;
end if;
 
if unsigned(RB_LAM) /= 0 then
write_data(oline, ": rblam ", RB_LAM, 0, true, " RB_LAM active");
end if;
end loop;
end process proc_moni;
end sim;
/rtl/vlib/rbus/Makefile
0,0 → 1,22
# $Id: Makefile 343 2010-12-05 21:24:38Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2007-12-09 100 1.0.1 drop ISE_p definition
# 2007-07-06 64 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
.phony : all clean
#
all : $(NGC_all)
#
clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/vlib/Makefile.xflow
#
include $(VBOM_all:.vbom=.dep_xst)
#
/rtl/vlib/rbus/rbd_tester.vhd
0,0 → 1,337
-- $Id: rbd_tester.vhd 352 2011-01-02 13:01:37Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rbd_tester - syn
-- Description: rbus dev: rbus tester
--
-- Dependencies: memlib/fifo_1c_dram_raw
--
-- Test bench: rlink/tb/tb_rlink (used as test target)
--
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-12 344 12.1 M53d xc3s1000-4 78 204 32 133 s 8.0
-- 2010-12-04 343 12.1 M53d xc3s1000-4 75 214 32 136 s 9.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-31 352 1.0.3 simplify irb_ack logic
-- 2010-12-29 351 1.0.2 default addr 111101xx->111100xx
-- 2010-12-12 344 1.0.1 send 0101.. on busy or err; fix init and busy logic
-- 2010-12-04 343 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Address Bits Name r/w/f Function
-- bbbbbb00 cntl r/w/- Control register
-- 15 nofifo r/w/- a 1 disables fifo, to test delayed aborts
-- 14:12 stat r/w/- echo'ed on RB_STAT
-- 11:00 nbusy r/w/- busy cycles (for data and fifo access)
-- 00 go r/w/- enables monitor
-- bbbbbb01 15:00 data r/w/- Data register (just w/r reg, no function)
-- bbbbbb10 15:00 fifo r/w/- Fifo interface register
-- bbbbbb11 attn r/w/- Attn/Length register
-- 15:00 w: ping RB_LAM lines
-- 9:00 r: return cycle length of last access
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
 
entity rbd_tester is -- rbus dev: rbus tester
-- complete rrirp_aif interface
generic (
RB_ADDR : slv8 := conv_std_logic_vector(2#11110000#,8));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv3 -- rbus: status flags
);
end entity rbd_tester;
 
 
architecture syn of rbd_tester is
 
constant awidth : positive := 4; -- fifo address width
 
constant rbaddr_cntl : slv2 := "00"; -- cntl address offset
constant rbaddr_data : slv2 := "01"; -- data address offset
constant rbaddr_fifo : slv2 := "10"; -- fifo address offset
constant rbaddr_attn : slv2 := "11"; -- attn address offset
 
constant cntl_rbf_nofifo : integer := 15;
subtype cntl_rbf_stat is integer range 14 downto 12;
subtype cntl_rbf_nbusy is integer range 9 downto 0;
 
constant init_rbf_cntl : integer := 0;
constant init_rbf_data : integer := 1;
constant init_rbf_fifo : integer := 2;
type regs_type is record -- state registers
rbsel : slbit; -- rbus select
nofifo : slbit; -- disable fifo flag
stat : slv3; -- stat setting
nbusy : slv10; -- nbusy setting
data : slv16; -- data register
act_1 : slbit; -- rbsel and (re or we) in last cycle
ncyc : slv10; -- cycle length of last access
cntbusy : slv10; -- busy timer
cntcyc : slv10; -- cycle length counter
end record regs_type;
 
constant regs_init : regs_type := (
'0', -- rbsel
'0', -- nofifo
(others=>'0'), -- stat
(others=>'0'), -- nbusy
(others=>'0'), -- data
'0', -- act_1
(others=>'0'), -- ncyc
(others=>'0'), -- cntbusy
(others=>'0') -- cntcyc
);
 
constant cntcyc_max : slv(regs_init.cntcyc'range) := (others=>'1');
 
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal FIFO_RESET : slbit := '0';
signal FIFO_RE : slbit := '0';
signal FIFO_WE : slbit := '0';
signal FIFO_EMPTY : slbit := '0';
signal FIFO_FULL : slbit := '0';
signal FIFO_SIZE : slv(awidth-1 downto 0) := (others=>'0');
signal FIFO_DO : slv16 := (others=>'0');
begin
 
FIFO : fifo_1c_dram_raw
generic map (
AWIDTH => awidth,
DWIDTH => 16)
port map (
CLK => CLK,
RESET => FIFO_RESET,
RE => FIFO_RE,
WE => FIFO_WE,
DI => RB_MREQ.din,
DO => FIFO_DO,
SIZE => FIFO_SIZE,
EMPTY => FIFO_EMPTY,
FULL => FIFO_FULL
);
 
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
 
proc_next : process (R_REGS, RB_MREQ, FIFO_EMPTY, FIFO_FULL, FIFO_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable irblam : slv16 := (others=>'0');
variable ififo_re : slbit := '0';
variable ififo_we : slbit := '0';
variable ififo_reset : slbit := '0';
variable isbusy : slbit := '0';
begin
 
r := R_REGS;
n := R_REGS;
 
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irblam := (others=>'0');
 
irbena := RB_MREQ.re or RB_MREQ.we;
ififo_re := '0';
ififo_we := '0';
ififo_reset := '0';
 
isbusy := '0';
if unsigned(r.cntbusy) /= 0 then
isbusy := '1';
end if;
 
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2) then
 
n.rbsel := '1';
 
if irbena = '0' then -- addr valid and selected, but no req
n.cntbusy := r.nbusy; -- preset busy timer
n.cntcyc := (others=>'0'); -- clear cycle length counter
end if;
 
end if;
 
-- rbus transactions
if r.rbsel = '1' then
if irbena = '1' then -- if request active
if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0
n.cntbusy := unsigned(r.cntbusy) - 1; -- decrement busy timer
end if;
if r.cntcyc /= cntcyc_max then -- if cycle counter < max
n.cntcyc := unsigned(r.cntcyc) + 1; -- increment cycle counter
end if;
end if;
irb_ack := irbena; -- ack all (some rejects later)
 
case RB_MREQ.addr(1 downto 0) is
 
when rbaddr_cntl =>
if RB_MREQ.we='1' then
n.nofifo := RB_MREQ.din(cntl_rbf_nofifo);
n.stat := RB_MREQ.din(cntl_rbf_stat);
n.nbusy := RB_MREQ.din(cntl_rbf_nbusy);
if r.nofifo='1' and RB_MREQ.din(cntl_rbf_nofifo)='0' then
ififo_reset := '1';
end if;
end if;
when rbaddr_data =>
irb_busy := irbena and isbusy;
if RB_MREQ.we='1' and isbusy='0' then
n.data := RB_MREQ.din;
end if;
when rbaddr_fifo =>
if r.nofifo = '0' then -- if fifo enabled
irb_busy := irbena and isbusy;
if RB_MREQ.re='1' and isbusy='0' then
if FIFO_EMPTY = '1' then
irb_err := '1';
else
ififo_re := '1';
end if;
end if;
if RB_MREQ.we='1' and isbusy='0' then
if FIFO_FULL = '1' then
irb_err := '1';
else
ififo_we := '1';
end if;
end if;
 
else -- else: if fifo disabled
irb_ack := '0'; -- nak it
if isbusy = '1' then -- or do a delayed nak
irb_ack := irbena;
irb_busy := irbena;
end if;
end if;
 
when rbaddr_attn =>
if RB_MREQ.we = '1' then
irblam := RB_MREQ.din;
end if;
when others => null;
end case;
end if;
 
-- rbus output driver
-- send a '0101...' pattern when selected and busy or err
-- send data only when busy=0 and err=0
-- this extra logic allows to debug rlink state machine
if r.rbsel = '1' then
if RB_MREQ.re='1' and irb_busy='0' and irb_err='0' then
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
irb_dout(cntl_rbf_stat) := r.stat;
irb_dout(cntl_rbf_nofifo) := r.nofifo;
irb_dout(cntl_rbf_nbusy) := r.nbusy;
when rbaddr_data =>
irb_dout := r.data;
when rbaddr_fifo =>
if r.nofifo='0' and FIFO_EMPTY = '0' then
irb_dout := FIFO_DO;
end if;
when rbaddr_attn =>
irb_dout(r.cntcyc'range) := r.ncyc;
when others => null;
end case;
else
irb_dout := "0101010101010101";
end if;
end if;
 
-- init transactions
if RB_MREQ.init='1' and RB_MREQ.we='1' and RB_MREQ.addr=RB_ADDR then
if RB_MREQ.din(init_rbf_cntl) = '1' then
n.nofifo := '0';
n.stat := (others=>'0');
n.nbusy := (others=>'0');
end if;
if RB_MREQ.din(init_rbf_data) = '1' then
n.data := (others=>'0');
end if;
if RB_MREQ.din(init_rbf_fifo) = '1' then
ififo_reset := '1';
end if;
end if;
-- other transactions
if irbena='0' and r.act_1='1' then
n.ncyc := r.cntcyc;
end if;
n.act_1 := irbena;
N_REGS <= n;
 
FIFO_RE <= ififo_re;
FIFO_WE <= ififo_we;
FIFO_RESET <= ififo_reset;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
 
RB_LAM <= irblam;
RB_STAT <= r.stat;
end process proc_next;
 
end syn;
/rtl/vlib/rbus/rb_mon.vbom
0,0 → 1,7
# libs
../slvtypes.vhd
../simlib/simlib.vhd
rblib.vhd
# components
# design
rb_mon.vhd
/rtl/vlib/rbus/rbdlib.vhd
0,0 → 1,114
-- $Id: rbdlib.vhd 351 2010-12-30 21:50:54Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: rbdlib
-- Description: Definitions for rbus devices
--
-- Dependencies: -
-- Tool versions: xst 12.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 1.2 new address layout; add rbd_timer
-- 2010-12-27 349 1.1 now correct defs for _rbmon and _eyemon
-- 2010-12-04 343 1.0 Initial version
------------------------------------------------------------------------------
--
-- base addresses of some standard rbus devices
--
-- rbd_rbmon 111111xx -++-- these three used as monitors
-- rbd_eyemon 111110xx /
-- rbd_rlstat 1111011x /
-- rbd_bram 1111010x \
-- rbd_tester 111100xx +- all five used in test benchs
--
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
use work.rblib.all;
 
package rbdlib is
 
component rbd_tester is -- rbus dev: rbus tester
-- complete rbus_aif interface
generic (
RB_ADDR : slv8 := conv_std_logic_vector(2#11110000#,8));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv3 -- rbus: status flags
);
end component;
 
component rbd_bram is -- rbus dev: bram test target
-- incomplete rbus_aif interface
generic (
RB_ADDR : slv8 := conv_std_logic_vector(2#11110100#,8));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type -- rbus: response
);
end component;
 
component rbd_rbmon is -- rbus dev: rbus monitor
generic (
RB_ADDR : slv8 := conv_std_logic_vector(2#11111100#,8);
AWIDTH : positive := 9);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_SRES_SUM : in rb_sres_type -- rbus: response (sum for monitor)
);
end component;
 
component rbd_eyemon is -- rbus dev: eye monitor for serport's
generic (
RB_ADDR : slv8 := conv_std_logic_vector(2#11111000#,8);
RDIV : slv8 := conv_std_logic_vector(0,8));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RXSD : in slbit; -- rx: serial data
RXACT : in slbit -- rx: active (start seen)
);
end component;
 
component rbd_timer is -- rbus dev: usec precision timer
generic (
RB_ADDR : slv8 := conv_std_logic_vector(2#00000000#,8));
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DONE : out slbit; -- mark last timer cycle
BUSY : out slbit -- timer running
);
end component;
 
end package rbdlib;
/rtl/vlib/rbus
rtl/vlib/rbus Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: doc/w11a_tb_guide.txt =================================================================== --- doc/w11a_tb_guide.txt (revision 8) +++ doc/w11a_tb_guide.txt (revision 9) @@ -1,4 +1,4 @@ -# $Id: w11a_tb_guide.txt 317 2010-07-22 19:36:56Z mueller $ +# $Id: w11a_tb_guide.txt 352 2011-01-02 13:01:37Z mueller $ Guide to running w11a test benches @@ -65,53 +65,62 @@ make tb_serport_uart_rx time tbw tb_serport_uart_rx |\ tee tb_serport_uart_rx_dsim.log | egrep "(FAIL|DONE)" - -> 1269955 ns 63488: DONE + -> 1269955.0 ns 63488: DONE + -> real 0m1.178s user 0m1.172s sys 0m0.020s + - serport receiver/transmitter test make tb_serport_uart_rxtx time tbw tb_serport_uart_rxtx |\ tee tb_serport_uart_rxtx_dsim.log | egrep "(FAIL|DONE)" - -> 52335 ns 2607: DONE + -> 52335.0 ns 2607: DONE + -> real 0m0.094s user 0m0.092s sys 0m0.008s - serport autobauder test make tb_serport_autobaud time tbw tb_serport_autobaud |\ tee tb_serport_autobaud_dsim.log | egrep "(FAIL|DONE)" - -> 367475 ns 18364: DONE + -> 367475.0 ns 18364: DONE + -> real 0m0.610s user 0m0.612s sys 0m0.004s - - rri core test + - rlink core test - cd $RETROBASE/rtl/vlib/rri/tb - make tb_rri_core - time tbw tb_rri_core |\ - tee tb_rri_core_dsim.log | egrep "(FAIL|DONE)" - -> 61855 ns 3083: DONE - -> real 0m0.163s user 0m0.128s sys 0m0.020s + cd $RETROBASE/rtl/vlib/rlink/tb + make tb_rlink_direct + time tbw tb_rlink_direct |\ + tee tb_rlink_direct_dsim.log | egrep "(FAIL|DONE)" + -> 142355.0 ns 7108: DONE + -> real 0m0.317s user 0m0.324s sys 0m0.028s - - rri core test via serial port interface + - rlink core test via serial port interface - make tb_rri_serport - time tbw tb_rri_serport |\ - tee tb_rri_serport_dsim.log | egrep "(FAIL|DONE)" - -> 273355 ns 13658: DONE - -> real 0m0.939s user 0m0.924s sys 0m0.008s + make tb_rlink_serport + time tbw tb_rlink_serport tb_rlink_serport_stim.dat |\ + tee tb_rlink_serport_stim2_dsim.log | egrep "(FAIL|DONE)" + -> 72735.0 ns 3627: DONE + -> real 0m0.266s user 0m0.264s sys 0m0.008s + time tbw tb_rlink_serport tb_rlink_stim.dat |\ + tee tb_rlink_serport_dsim.log | egrep "(FAIL|DONE)" + -> 536155.0 ns 26798: DONE + -> real 0m1.714s user 0m1.704s sys 0m0.044s + - w11a core test (using behavioural model) cd $RETROBASE/rtl/w11a/tb - make tb_pdp11_core - time tbw tb_pdp11_core |\ - tee tb_pdp11_core_dsim.log | egrep "(FAIL|DONE)" - -> 1220255 ns 61003: DONE - -> real 0m14.964s user 0m14.977s sys 0m0.108s + make tb_pdp11core + time tbw tb_pdp11core |\ + tee tb_pdp11core_dsim.log | egrep "(FAIL|DONE)" + -> 1220255.0 ns 61003: DONE + -> real 0m10.736s user 0m10.713s sys 0m0.060s - w11a core test (using post-synthesis model) - make ghdl_tmp_clean tb_pdp11_core_ssim - time tbw tb_pdp11_core_ssim |\ - tee tb_pdp11_core_ssim.log | egrep "(FAIL|DONE)" - -> 1220255 ns 61003: DONE - -> real 1m8.230s user 1m8.144s sys 0m0.124s + make ghdl_tmp_clean tb_pdp11core_ssim + time tbw tb_pdp11core_ssim |\ + tee tb_pdp11core_ssim.log | egrep "(FAIL|DONE)" + -> 1220255.0 ns 61003: DONE + -> real 1m9.738s user 1m9.588s sys 0m0.096s 3. System tests benches --------------------------------------------------- @@ -118,13 +127,13 @@ The system tests allow to verify to verify the full 11/70 SoC design. In this case vhdl test bench code contains - (simple) models of the memories used on the FPGA boards - - drivers for the rri connection (currently just serialport) - - code to interface the rri data stream to a UNIX 'named pipe', + - drivers for the rlink connection (currently just serialport) + - code to interface the rlink data stream to a UNIX 'named pipe', implemented with a C routine which is called via VHPI from VHDL. This way the whole ghdl simulation can be controlled via a di-directional byte stream. - The rri backend process, currently a perl script named pi_rri, can connect + The rlink backend process, currently a perl script named pi_rri, can connect either via a named pipe to a ghdl simulation, or via a serial port to a FPGA board. This way the same tests can be executed in simulation and on real hardware. @@ -134,7 +143,7 @@ The stimulus file used in the w11a core test can be executed in the full system context (both s3board and nexys2 versions) with the following commands. Note that the cycle number printed in the DONE - line can now vary slightly because the response time of the rri + line can now vary slightly because the response time of the rlink backend process and thus scheduling of backend vs. ghdl process can affect the result. @@ -144,10 +153,10 @@ make tb_w11a_s3 time pi_rri --fifo --timeout=40. --cmax=3 \ --run="tbw tb_w11a_s3" -- \ - @../../../../w11a/tb/tb_pdp11_core_stim.dat |\ + @../../../../w11a/tb/tb_pdp11core_stim.dat |\ tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)" - -> 7766215 ns 388301: DONE - -> real 0m51.300s user 0m51.711s sys 0m0.772s + -> 7757655.0 ns 387873: DONE + -> real 0m49.835s user 0m50.203s sys 0m0.696s - sys_w11a_n2 system test @@ -155,7 +164,7 @@ make tb_w11a_n2 time pi_rri --fifo --timeout=40. --cmax=3 \ --run="tbw tb_w11a_n2" -- \ - @../../../../w11a/tb/tb_pdp11_core_stim.dat |\ + @../../../../w11a/tb/tb_pdp11core_stim.dat |\ tee tb_w11a_n2_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)" - -> 7766855 ns 388333: DONE - -> real 0m51.243s user 0m51.647s sys 0m0.776s + -> 6673237.2 ns 387035: DONE + -> real 0m56.173s user 0m56.612s sys 0m0.604s
/doc/README.txt
1,4 → 1,4
# $Id: README.txt 341 2010-11-27 23:05:43Z mueller $
# $Id: README.txt 351 2010-12-30 21:50:54Z mueller $
 
Release notes for w11a
 
9,7 → 9,7
3. Change Log
 
 
1. Documentation ----------------------------------------------------------
1. Documentation -------------------------------------------------------------
 
More detailed information on installation, build and test can be found
in the doc directory, specifically
20,7 → 20,7
* w11a_os_guide.txt: booting operating systems
* w11a_known_issues.txt: known differences, limitations and issues
 
2. Files ------------------------------------------------------------------
2. Files ---------------------------------------------------------------------
 
doc Documentation
rtl VHDL sources
38,7 → 38,8
rtl/vlib/comlib - communication
rtl/vlib/genlib - general
rtl/vlib/memlib - memory
rtl/vlib/rri - remote-register-interface
rtl/vlib/rbus - rri: rbus
rtl/vlib/rlink - rri: rlink
rtl/vlib/serport - serial port (UART)
rtl/vlib/simlib - simulation helper lib
rtl/vlib/xlib - Xilinx specific components
46,12 → 47,89
tools helper programs
tools/bin - scripts and binaries
 
3. Change Log -------------------------------------------------------------
3. Change Log ----------------------------------------------------------------
 
- trunk (2010-11-28: svn rev 8(oc) 341(wfjm); untagged w11a_V0.51)
- trunk (2011-01-02: svn rev 9(oc) 352(wfjm); untagged w11a_V0.52) +++++++++
 
- Summary
- Introduced rbus protocol V3
- reorganize rbus and rlink modules, many renames
 
- Changes
- module renames:
- the rri (remote-register-interface) components were re-organized and
cleanly separated into rbus and rlink components:
rri/rb_sres_or_* -> rbus/rb_sres_or_*
rri/rri_core -> rlink/rlink_core
rri/rri_base_serport -> rlink/rlink_base_serport
rri/rrilib -> rbus/rblib
-> rlink/rlinklib
rri/rri_serport -> rlink/rlink_serport
rri/tb/rritb_sres_or_mon -> rbus/rb_sres_or_mon
- the rri test bench monitors were reorganized and renamed
rri/tb/rritb_cpmon -> rlink/rlink_mon
rri/tb/rritb_cpmon_sb -> rlink/rlink_mon_sb
rri/tb/rritb_rbmon -> rbus/rb_mon
rri/tb/rritb_rbmon_sb -> rbus/rb_mon_sb
- the rri low level test bench were also renamed
rri/tb/tb_rri -> rlink/tb/tb_rlink
rri/tb/tb_rri_core -> rlink/tb/tb_rlink_direct
rri/tb/tb_rri_serport -> rlink/tb/tb_rlink_serport
- the base modules for rlink+cext based test benches were renamed
rri/tb/rritb_core_cm -> rlink/tb/tbcore_rlink_dcm
rri/tb/rritb_core -> rlink/tb/tbcore_rlink
rri/tb/vhpi_rriext -> rlink/tb/rlink_cext_vhpi
rri/tb/cext_rriext.c -> rlink/tb/rlink_cext.c
 
- other rri/rbus related renames
bplib/s3board/s3_humanio_rri -> s3_humanio_rbus
w11a/pdp11_core_rri -> pdp11_core_rbus
 
- other renames
w11a/tb/tb_pdp11_core -> tb_pdp11core
 
- signal renames:
- rlink interface (defined in rlink/rlinklib.vhd):
- rename rlink port signals:
CP_* -> RL_*
- rename status bit names to better reflect their usage in v3:
ccrc -> cerr - indicates cmd crc error or other cmd level abort
dcrc -> derr - indicates data crc error or other data level abort
ioto -> rbnak - indicates rbus abort, either no ack or timeout
ioerr -> rberr - indicates that rbus err flag was set
 
- migrate to rbus protocol verion 3
- in rb_mreq use now aval,re,we instead of req,we
- basic rbus transaction now takes 2 cycles, one for address select, one
for data exchange. Same concept and reasoning behind as in ibus V2.
 
- vlib/rlink/rlink_core
- cerr and derr state flags now set on command or data crc errors as well
as on eop/nak aborts when command or wblk data is received.
- has now 'monitor port', RL_MONI.
- RL_FLUSH port removed, the flush logic is now in rlink_serport
 
- restructured rlink modules
- rlink_core is the rlink protocol engine with a 9 bit wide interface
- rlink_rlb2rl (new) is an adapter to a byte wide interface
- rlink_base (new) combines rlink_core and rlink_rlb2rl
- rlink_serport (re-written) is an adapter to a serial interface
- rlink_base_serport (renamed) combines rlink_base and rlink_serport
 
- New features
- vlib/rbus
- added several rbus devices useful for debugging
- rbd_tester: test target, used for example in test benches
 
- trunk (2010-11-28: svn rev 8(oc) 341(wfjm); untagged w11a_V0.51) ++++++++
 
- Summary
- Introduced ibus protocol V2
- Nexys2 systems use DCM
- sys_w11a_n2 now runs with 58 MHz
 
- Changes
- module renames:
- in future 'box' is used for large autonomous blocks, therefore use
the term unit for purely sequential logic modules:
pdp11_abox -> pdp11_ounit
66,7 → 144,7
- migrate to ibus protocol verion 2
- in ib_mreq use now aval,re,we,rmw instead of req,we,dip
- basic ibus transaction now takes 2 cycles, one for address select, one
for data exchange. This avoids too long logic paths in ibus sector.
for data exchange. This avoids too long logic paths in the ibus logic.
 
- New features
- ibus
80,7 → 158,7
- Bug fixes
- rtl/vlib/Makefile.xflow: use default .opt files under rtl/vlib again.
 
- w11a_V0.5 (2010-07-23) -------------------------------------
- w11a_V0.5 (2010-07-23) ++++++++++++++++++++++++++++++++++++++++++++++++++
 
Initial release with
- w11a CPU core
/doc/man/man5
doc/man/man5 Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: doc/man/man1 =================================================================== --- doc/man/man1 (revision 8) +++ doc/man/man1 (revision 9)
doc/man/man1 Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: doc/man =================================================================== --- doc/man (revision 8) +++ doc/man (revision 9)
doc/man Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: doc/w11a_seq_flow.DOT =================================================================== --- doc/w11a_seq_flow.DOT (revision 8) +++ doc/w11a_seq_flow.DOT (revision 9) @@ -1,11 +1,16 @@ -// $Id: w11a_seq_flow.DOT 315 2010-07-11 22:18:39Z mueller $ +// $Id: w11a_seq_flow.DOT 343 2010-12-05 21:24:38Z mueller $ // // The create pdf use // // cpp w11a_seq_flow.DOT w11a_seq_flow.dot -// dot -Tps2 w11a_seq_flow.dot > w11a_seq_flow.ps -// ps2pdf w11a_seq_flow.ps +// dot -Tpdf w11a_seq_flow.dot > w11a_seq_flow.pdf +// xpdf w11a_seq_flow.pdf +// -> gives 30.54 x 43.92 in page size // +// pdflatex w11a_seq_flow_a4wrap.tex +// xpdf w11a_seq_flow_a4wrap.pdf +// --> gives 8.27 x 11.69 in page size (A4) +// #define FORKSTATE #define CLUSTER

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