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URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /xge_mac
    from Rev 16 to Rev 17
    ↔ Reverse comparison
  •

Rev 16 → Rev 17

/trunk/tbench/systemc/sc_cpu_if.h
100,7 → 100,7
scoreboard::sbSourceId sb_id;
 
sc_mutex bus_lock;
sc_event bus_start;
sc_semaphore bus_start;
sc_semaphore bus_done;
 
uint bus_addr;
132,7 → 132,7
void transactor();
void monitor();
 
SC_CTOR(cpu_if): bus_done(0) {
SC_CTOR(cpu_if): bus_start(0), bus_done(0) {
 
SC_CTHREAD (monitor, wb_clk_i.pos());
SC_CTHREAD (transactor, wb_clk_i.pos());
/trunk/tbench/systemc/sc_main.cpp
72,9 → 72,9
 
cout << ("Defining Clocks\n");
 
sc_clock clk_156m25 ("clk_156m25", 10, 0.5, 3, true);
sc_clock clk_wb ("clk_wb", 29, 0.5, 3, true);
sc_clock clk_xgmii ("clk_xgmii", 10, 0.5, 3, true);
sc_clock clk_156m25 ("clk_156m25", 10, SC_NS, 0.5);
sc_clock clk_wb ("clk_wb", 29, SC_NS, 0.5);
sc_clock clk_xgmii ("clk_xgmii", 10, SC_NS, 0.5);
 
sc_signal<bool> pkt_rx_ren;
sc_signal<long unsigned int > pkt_tx_data;
212,13 → 212,13
// SystemC to interconnect everything for testing.
cout <<("Test initialization...\n");
 
sc_start(1);
sc_start(1, SC_NS);
 
reset_156m25_n = 0;
wb_rst_i = 1;
reset_xgmii_n = 0;
 
sc_start(1);
sc_start(1, SC_NS);
 
#if WAVES
cout << "Enabling waves...\n";
247,7 → 247,7
reset_xgmii_n = 1;
}
 
sc_start(1);
sc_start(1, SC_NS);
}
 
top->final();
/trunk/tbench/systemc/sc_testcases.cpp
279,7 → 279,7
tb->sb.clear_stats();
 
tb->pif_gen0.set_pkt_size(1000, 1000);
 
tb->cpu_if0.set_param(cpu_if::TX_ENABLE, 0);
tb->sb.disable_signal_check = true;
 
319,7 → 319,7
// Check errors reported
 
cpu_stats = tb->sb.get_cpu_stats();
 
//---
// Enable traffic
 
359,7 → 359,7
tb->sb.clear_stats();
 
tb->xgm_gen0.set_pkt_size(1000, 1000);
 
tb->pkt_if0.disable_rx = true;
tb->pkt_if0.allow_rx_sop_err = true;
tb->sb.disable_flags_check = true;
741,8 → 741,7
 
//---
// Return parameters to default state
 
tb->sb.disable_signal_check = false;
tb->cpu_if0.set_interrupt_mask(cpu_if::INT_CRC_ERROR, 1);
}
 
/trunk/tbench/systemc/sc_cpu_if.cpp
89,14 → 89,12
bus_lock.lock();
bus_addr = addr;
bus_write = false;
bus_start.notify();
bus_start.post();
 
//--
// Wait for transaction to complete
 
while (bus_done.trywait()) {
wait(10, SC_NS);
};
bus_done.wait();
 
//--
// Get the data, free the bus
117,14 → 115,12
bus_addr = addr;
bus_data = data;
bus_write = true;
bus_start.notify();
bus_start.post();
 
//--
// Wait for transaction to complete
 
while (bus_done.trywait()) {
wait(10, SC_NS);
};
bus_done.wait();
 
//--
// Free the bus
139,7 → 135,7
uint mask;
 
mask = ~((0xffffffff << lbit) & (0xffffffff >> (31-lbit)));
 
data = mask & read(addr);
data = data | ((value << lbit) & ~mask);
 
152,7 → 148,9
while (true) {
 
// Wait for a transaction
wait(bus_start);
while (bus_start.trywait()) {
wait();
}
 
if (!bus_write) {
 
228,7 → 226,7
// Read interrupt register when interrupt signal is asserted
 
data = read(cpu_if::CPUREG_INT_PENDING);
 
cout << "READ INTERRUPTS: 0x" << hex << data << dec << endl;
 
//---
243,7 → 241,7
}
 
if ((data >> cpu_if::INT_LOCAL_FAULT) & 0x1) {
 
data = read(cpu_if::CPUREG_INT_STATUS);
 
if ((data >> cpu_if::INT_LOCAL_FAULT) & 0x1) {
282,6 → 280,6
 
}
 
wait();
wait();
}
};
/trunk/tbench/verilog/tb_xge_mac.sv
67,6 → 67,9
reg pkt_tx_eop;
reg [2:0] pkt_tx_mod;
 
integer tx_count;
integer rx_count;
 
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire pkt_rx_avail; // From dut of xge_mac.v
244,6 → 247,11
assign wb_we_i = 1'b0;
 
 
initial begin
tx_count = 0;
rx_count = 0;
end
 
//---
// XGMII Loopback
// This test is done with loopback on XGMII or using one of the tranceiver examples
370,6 → 378,8
pkt_tx_eop = 1'b0;
pkt_tx_mod = 3'b0;
 
tx_count = tx_count + 1;
 
end
 
endtask
471,6 → 481,8
 
if (pkt_rx_sop) begin
$display("\n\n------------------------");
$display("Received Packet");
$display("------------------------");
end
 
$display("%x", pkt_rx_data);
490,6 → 502,8
 
end
 
rx_count = rx_count + 1;
 
end
endtask
 
498,7 → 512,13
forever begin
 
if (pkt_rx_avail) begin
 
RxPacket();
 
if (rx_count == tx_count) begin
$display("All packets received. Sumulation done!!!\n");
end
 
end
 
@(posedge clk_156m25);
/trunk/sim/verilog/sim.do
42,7 → 42,7
 
 
 
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../tbench/verilog/tb_xge_mac.v
vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../tbench/verilog/tb_xge_mac.sv
 
 
 

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