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URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

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  • This comparison shows the changes necessary to convert path 
    /xge_mac
    from Rev 19 to Rev 20
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  •

Rev 19 → Rev 20

/trunk/rtl/verilog/generic_fifo.v
60,8 → 60,6
parameter DWIDTH = 32;
parameter AWIDTH = 3;
parameter RAM_DEPTH = (1 << AWIDTH);
parameter SYNC_WRITE = 1;
parameter SYNC_READ = 1;
parameter REGISTER_READ = 0;
parameter EARLY_READ = 0;
parameter CLOCK_CROSSING = 1;
96,7 → 94,7
 
 
generic_fifo_ctrl #(.AWIDTH (AWIDTH),
.RAM_DEPTH (RAM_DEPTH),
.RAM_DEPTH (RAM_DEPTH),
.EARLY_READ (EARLY_READ),
.CLOCK_CROSSING (CLOCK_CROSSING),
.ALMOST_EMPTY_THRESH (ALMOST_EMPTY_THRESH),
107,7 → 105,7
.wen (wen),
.wfull (wfull),
.walmost_full (walmost_full),
 
.mem_wen (mem_wen),
.mem_waddr (mem_waddr),
 
128,21 → 126,19
generic_mem_small #(.DWIDTH (DWIDTH),
.AWIDTH (AWIDTH),
.RAM_DEPTH (RAM_DEPTH),
.SYNC_WRITE (SYNC_WRITE),
.SYNC_READ (SYNC_READ),
.REGISTER_READ (REGISTER_READ)
)
mem0(.wclk (wclk),
.wrst_n (wrst_n),
.wen (mem_wen),
.waddr (mem_waddr),
.wen (mem_wen),
.waddr (mem_waddr[AWIDTH-1:0]),
.wdata (wdata),
 
.rclk (rclk),
.rrst_n (rrst_n),
.ren (mem_ren),
.roen (ren),
.raddr (mem_raddr),
.raddr (mem_raddr[AWIDTH-1:0]),
.rdata (rdata)
);
 
153,21 → 149,19
generic_mem_medium #(.DWIDTH (DWIDTH),
.AWIDTH (AWIDTH),
.RAM_DEPTH (RAM_DEPTH),
.SYNC_WRITE (SYNC_WRITE),
.SYNC_READ (SYNC_READ),
.REGISTER_READ (REGISTER_READ)
)
mem0(.wclk (wclk),
.wrst_n (wrst_n),
.wen (mem_wen),
.waddr (mem_waddr),
.wen (mem_wen),
.waddr (mem_waddr[AWIDTH-1:0]),
.wdata (wdata),
 
.rclk (rclk),
.rrst_n (rrst_n),
.ren (mem_ren),
.roen (ren),
.raddr (mem_raddr),
.raddr (mem_raddr[AWIDTH-1:0]),
.rdata (rdata)
);
 
176,6 → 170,3
endgenerate
 
endmodule
 
 
 
/trunk/rtl/verilog/wishbone_if.v
64,7 → 64,7
 
input status_crc_error;
input status_fragment_error;
 
input status_txdfifo_ovflow;
 
input status_txdfifo_udflow;
146,8 → 146,8
 
cpuack <= 1'b0;
 
status_remote_fault_d1 <= status_remote_fault;
status_local_fault_d1 <= status_local_fault;
status_remote_fault_d1 <= 1'b0;
status_local_fault_d1 <= 1'b0;
 
end
else begin
171,7 → 171,7
`CPUREG_CONFIG0: begin
wb_dat_o <= {31'b0, cpureg_config0};
end
 
`CPUREG_INT_PENDING: begin
wb_dat_o <= {23'b0, cpureg_int_pending};
cpureg_int_pending <= int_sources;
203,7 → 203,7
`CPUREG_CONFIG0: begin
cpureg_config0 <= wb_dat_i[0:0];
end
 
`CPUREG_INT_PENDING: begin
cpureg_int_pending <= wb_dat_i[8:0] | cpureg_int_pending | int_sources;
end
224,4 → 224,3
end
 
endmodule
 
/trunk/rtl/verilog/generic_mem_small.v
59,8 → 59,6
parameter DWIDTH = 32;
parameter AWIDTH = 3;
parameter RAM_DEPTH = (1 << AWIDTH);
parameter SYNC_WRITE = 1;
parameter SYNC_READ = 1;
parameter REGISTER_READ = 0;
 
//---
69,7 → 67,7
input wclk;
input wrst_n;
input wen;
input [AWIDTH:0] waddr;
input [AWIDTH-1:0] waddr;
input [DWIDTH-1:0] wdata;
 
input rclk;
76,7 → 74,7
input rrst_n;
input ren;
input roen;
input [AWIDTH:0] raddr;
input [AWIDTH-1:0] raddr;
output [DWIDTH-1:0] rdata;
 
// Registered outputs
103,55 → 101,27
//---
// Memory Write
 
generate
if (SYNC_WRITE) begin
 
// Generate synchronous write
always @(posedge wclk)
begin
if (wen) begin
mem[waddr[AWIDTH-1:0]] <= wdata;
end
end
// Generate synchronous write
always @(posedge wclk)
begin
if (wen) begin
mem[waddr[AWIDTH-1:0]] <= wdata;
end
else begin
end
 
// Generate asynchronous write
always @(wen, waddr, wdata)
begin
if (wen) begin
mem[waddr[AWIDTH-1:0]] = wdata;
end
end
end
endgenerate
 
//---
// Memory Read
 
generate
if (SYNC_READ) begin
 
// Generate registered memory read
always @(posedge rclk or negedge rrst_n)
begin
if (!rrst_n) begin
mem_rdata <= {(DWIDTH){1'b0}};
end else if (ren) begin
mem_rdata <= mem[raddr[AWIDTH-1:0]];
end
end
// Generate registered memory read
always @(posedge rclk or negedge rrst_n)
begin
if (!rrst_n) begin
mem_rdata <= {(DWIDTH){1'b0}};
end else if (ren) begin
mem_rdata <= mem[raddr[AWIDTH-1:0]];
end
else begin
end
 
// Generate unregisters memory read
always @(raddr, rclk)
begin
mem_rdata = mem[raddr[AWIDTH-1:0]];
end
end
endgenerate
 
generate
if (REGISTER_READ) begin
 
178,6 → 148,3
endgenerate
 
endmodule
 
 
 
/trunk/rtl/verilog/xge_mac.v
202,7 → 202,7
.rxdfifo_rempty (rxdfifo_rempty),
.rxdfifo_ralmost_empty(rxdfifo_ralmost_empty),
.pkt_rx_ren (pkt_rx_ren));
 
rx_data_fifo rx_data_fifo0(/*AUTOINST*/
// Outputs
.rxdfifo_wfull (rxdfifo_wfull),
359,10 → 359,10
.status_local_fault_crx(status_local_fault_crx),
.status_remote_fault_crx(status_remote_fault_crx));
 
sync_clk_core sync_clk_core0(/*AUTOINST*/
// Inputs
.clk_xgmii_tx (clk_xgmii_tx),
.reset_xgmii_tx_n (reset_xgmii_tx_n));
//sync_clk_core sync_clk_core0(/*AUTOINST*/
// // Inputs
// .clk_xgmii_tx (clk_xgmii_tx),
// .reset_xgmii_tx_n (reset_xgmii_tx_n));
 
wishbone_if wishbone_if0(/*AUTOINST*/
// Outputs
389,4 → 389,3
.status_remote_fault (status_remote_fault));
 
endmodule
 
/trunk/rtl/verilog/tx_dequeue.v
57,10 → 57,10
input reset_xgmii_tx_n;
 
input ctrl_tx_enable_ctx;
 
input status_local_fault_ctx;
input status_remote_fault_ctx;
 
input [63:0] txdfifo_rdata;
input [7:0] txdfifo_rstatus;
input txdfifo_rempty;
80,7 → 80,7
 
output [63:0] txhfifo_wdata;
output [7:0] txhfifo_wstatus;
output txhfifo_wen;
output txhfifo_wen;
 
output [63:0] xgmii_txd;
output [7:0] xgmii_txc;
157,7 → 157,7
 
reg [63:0] next_txhfifo_wdata;
reg [7:0] next_txhfifo_wstatus;
reg next_txhfifo_wen;
reg next_txhfifo_wen;
 
reg txdfifo_ren_d1;
 
197,7 → 197,7
 
// If local fault detected, send remote fault message to
// link partner
 
xgmii_txd <= {`REMOTE_FAULT, 8'h0, 8'h0, `SEQUENCE,
`REMOTE_FAULT, 8'h0, 8'h0, `SEQUENCE};
xgmii_txc <= {4'b0001, 4'b0001};
206,7 → 206,7
 
// If remote fault detected, inhibit transmission and send
// idle codes
 
xgmii_txd <= {8{`IDLE}};
xgmii_txc <= 8'hff;
end
285,7 → 285,7
 
//---
// FIFO errors, used to generate interrupts.
 
if (txdfifo_ren && txdfifo_rempty) begin
status_txdfifo_udflow_tog <= ~status_txdfifo_udflow_tog;
end
330,7 → 330,7
// are detected.
 
if (ctrl_tx_enable_ctx && frame_available &&
!status_local_fault_ctx && !status_local_fault_ctx) begin
!status_local_fault_ctx && !status_remote_fault_ctx) begin
 
txhfifo_ren = 1'b1;
next_state_enc = SM_PREAMBLE;
371,7 → 371,7
// Depending on deficit idle count calculations, add 4 bytes
// or IFG or not. This will determine on which lane start the
// next frame.
 
if (ifg_4b_add) begin
next_start_on_lane0 = 1'b0;
end
394,7 → 394,7
// transition to next state.
 
if (txhfifo_rstatus[`TXSTATUS_EOP]) begin
 
txhfifo_ren = 1'b0;
next_frame_available = !txhfifo_ralmost_empty;
next_state_enc = SM_EOP;
417,7 → 417,7
next_eop[5] = txhfifo_rstatus[2:0] == 3'd6;
next_eop[6] = txhfifo_rstatus[2:0] == 3'd7;
next_eop[7] = txhfifo_rstatus[2:0] == 3'd0;
 
end
 
SM_EOP:
427,7 → 427,7
// of EOP read from fifo. Also insert CRC read from control fifo.
 
if (eop[0]) begin
next_xgxs_txd = {{2{`IDLE}}, `TERMINATE,
next_xgxs_txd = {{2{`IDLE}}, `TERMINATE,
crc32_tx[31:0], txhfifo_rdata_d1[7:0]};
next_xgxs_txc = 8'b11100000;
end
473,7 → 473,7
// If there is not another frame ready to be transmitted, interface
// will go idle and idle deficit idle count calculation is irrelevant.
// Set deficit to 0.
 
next_ifg_deficit = 3'b0;
 
end
508,7 → 508,7
// IFG and Add columns assume no deficit applied
// IFG+DIC and Add+DIC assume deficit must be applied
//
// Start lane 0 Start lane 4
// Start lane 0 Start lane 4
// EOP Pads IFG IFG+DIC Add Add+DIC Add Add IFG
// 0 3 11 15 8 12 12 16
// 1 2 10 14 8 12 12 16
523,7 → 523,7
 
// If there is not another frame ready to be transmitted, interface
// will go idle and idle deficit idle count calculation is irrelevant.
 
next_ifg_4b_add = 1'b0;
next_ifg_8b_add = 1'b0;
next_ifg_8b2_add = 1'b0;
532,7 → 532,7
else if (next_ifg_deficit[2] == ifg_deficit[2]) begin
 
// Add 4 bytes IFG
 
next_ifg_4b_add = (eop[0] & !start_on_lane0) |
(eop[1] & !start_on_lane0) |
(eop[2] & !start_on_lane0) |
543,7 → 543,7
(eop[7] & !start_on_lane0);
 
// Add 8 bytes IFG
 
next_ifg_8b_add = (eop[0]) |
(eop[1]) |
(eop[2]) |
572,7 → 572,7
(eop[7] & !start_on_lane0);
 
// Add 8 bytes IFG
 
next_ifg_8b_add = (eop[0]) |
(eop[1]) |
(eop[2]) |
701,7 → 701,7
else begin
crc_data = crc32_d64;
end
 
end
 
always @(/*AS*/byte_cnt or curr_state_pad or txdfifo_rdata
758,7 → 758,7
 
// Pad up to LANE3, keep the other 4 bytes for crc that will
// be inserted by dequeue engine.
 
next_txhfifo_wstatus[2:0] = 3'd4;
 
// Pad end bytes with zeros.
776,11 → 776,11
else begin
 
txdfifo_ren = 1'b0;
 
end
 
end
 
end
 
end
795,7 → 795,7
next_txhfifo_wdata = 64'b0;
next_txhfifo_wstatus = `TXSTATUS_NONE;
next_txhfifo_wen = 1'b1;
 
if (byte_cnt == 14'd56) begin
 
 
833,7 → 833,7
 
txhfifo_wdata <= 64'b0;
txhfifo_wstatus <= 8'b0;
txhfifo_wen <= 1'b0;
txhfifo_wen <= 1'b0;
 
byte_cnt <= 14'b0;
 
841,6 → 841,10
shift_crc_eop <= 4'b0;
shift_crc_cnt <= 4'b0;
 
crc32_d64 <= 32'b0;
crc32_d8 <= 32'b0;
crc32_tx <= 32'b0;
 
end
else begin
 
855,7 → 859,7
 
//---
// Reset byte count on SOP
 
if (next_txhfifo_wen) begin
 
if (next_txhfifo_wstatus[`TXSTATUS_SOP]) begin
887,7 → 891,7
 
// Last bytes calculated 8-bit at a time instead of 64-bit. Start
// this process at the end of the frame.
 
crc32_d8 <= crc32_d64;
 
shift_crc_data <= txhfifo_wdata;
910,7 → 914,7
 
shift_crc_data <= {8'b0, shift_crc_data[63:8]};
shift_crc_eop <= shift_crc_eop - 4'd1;
 
end
 
 
918,7 → 922,7
// Update CRC register at the end of calculation. Always update after 8
// cycles for deterministic results, even if a single byte was present in
// last data word.
 
if (shift_crc_cnt == 4'b1) begin
 
crc32_tx <= ~reverse_32b(crc32_d8);
935,4 → 939,3
end
 
endmodule
 
/trunk/rtl/verilog/generic_mem_medium.v
59,8 → 59,6
parameter DWIDTH = 32;
parameter AWIDTH = 3;
parameter RAM_DEPTH = (1 << AWIDTH);
parameter SYNC_WRITE = 1;
parameter SYNC_READ = 1;
parameter REGISTER_READ = 0;
 
//---
69,7 → 67,7
input wclk;
input wrst_n;
input wen;
input [AWIDTH:0] waddr;
input [AWIDTH-1:0] waddr;
input [DWIDTH-1:0] wdata;
 
input rclk;
76,7 → 74,7
input rrst_n;
input ren;
input roen;
input [AWIDTH:0] raddr;
input [AWIDTH-1:0] raddr;
output [DWIDTH-1:0] rdata;
 
// Registered outputs
103,55 → 101,27
//---
// Memory Write
 
generate
if (SYNC_WRITE) begin
 
// Generate synchronous write
always @(posedge wclk)
begin
if (wen) begin
mem[waddr[AWIDTH-1:0]] <= wdata;
end
end
// Generate synchronous write
always @(posedge wclk)
begin
if (wen) begin
mem[waddr[AWIDTH-1:0]] <= wdata;
end
else begin
end
 
// Generate asynchronous write
always @(wen, waddr, wdata)
begin
if (wen) begin
mem[waddr[AWIDTH-1:0]] = wdata;
end
end
end
endgenerate
 
//---
// Memory Read
 
generate
if (SYNC_READ) begin
 
// Generate registered memory read
always @(posedge rclk or negedge rrst_n)
begin
if (!rrst_n) begin
mem_rdata <= {(DWIDTH){1'b0}};
end else if (ren) begin
mem_rdata <= mem[raddr[AWIDTH-1:0]];
end
end
// Generate registered memory read
always @(posedge rclk or negedge rrst_n)
begin
if (!rrst_n) begin
mem_rdata <= {(DWIDTH){1'b0}};
end else if (ren) begin
mem_rdata <= mem[raddr[AWIDTH-1:0]];
end
else begin
end
 
// Generate unregisters memory read
always @(raddr, rclk)
begin
mem_rdata = mem[raddr[AWIDTH-1:0]];
end
end
endgenerate
 
generate
if (REGISTER_READ) begin
 
178,6 → 148,3
endgenerate
 
endmodule
 
 
 
/trunk/rtl/auto_verilog.sh
1,30 → 1,21
 
xemacs -batch verilog/sync_clk_wb.v -l ../custom.el -f verilog-auto -f save-buffer
xemacs -batch verilog/sync_clk_xgmii_tx.v -l ../custom.el -f verilog-auto -f save-buffer
xemacs -batch verilog/sync_clk_core.v -l ../custom.el -f verilog-auto -f save-buffer
emacs -batch verilog/sync_clk_wb.v -l ../custom.el -f verilog-auto -f save-buffer
emacs -batch verilog/sync_clk_xgmii_tx.v -l ../custom.el -f verilog-auto -f save-buffer
emacs -batch verilog/sync_clk_core.v -l ../custom.el -f verilog-auto -f save-buffer
 
xemacs -batch verilog/wishbone_if.v -l ../custom.el -f verilog-auto -f save-buffer
xemacs -batch verilog/fault_sm.v -l ../custom.el -f verilog-auto -f save-buffer
emacs -batch verilog/wishbone_if.v -l ../custom.el -f verilog-auto -f save-buffer
emacs -batch verilog/fault_sm.v -l ../custom.el -f verilog-auto -f save-buffer
 
xemacs -batch verilog/rx_dequeue.v -l ../custom.el -f verilog-auto -f save-buffer
xemacs -batch verilog/rx_enqueue.v -l ../custom.el -f verilog-auto -f save-buffer
xemacs -batch verilog/rx_data_fifo.v -l ../custom.el -f verilog-auto -f save-buffer
xemacs -batch verilog/rx_hold_fifo.v -l ../custom.el -f verilog-auto -f save-buffer
emacs -batch verilog/rx_dequeue.v -l ../custom.el -f verilog-auto -f save-buffer
emacs -batch verilog/rx_enqueue.v -l ../custom.el -f verilog-auto -f save-buffer
emacs -batch verilog/rx_data_fifo.v -l ../custom.el -f verilog-auto -f save-buffer
emacs -batch verilog/rx_hold_fifo.v -l ../custom.el -f verilog-auto -f save-buffer
 
xemacs -batch verilog/tx_dequeue.v -l ../custom.el -f verilog-auto -f save-buffer
xemacs -batch verilog/tx_enqueue.v -l ../custom.el -f verilog-auto -f save-buffer
xemacs -batch verilog/tx_data_fifo.v -l ../custom.el -f verilog-auto -f save-buffer
xemacs -batch verilog/tx_hold_fifo.v -l ../custom.el -f verilog-auto -f save-buffer
emacs -batch verilog/tx_dequeue.v -l ../custom.el -f verilog-auto -f save-buffer
emacs -batch verilog/tx_enqueue.v -l ../custom.el -f verilog-auto -f save-buffer
emacs -batch verilog/tx_data_fifo.v -l ../custom.el -f verilog-auto -f save-buffer
emacs -batch verilog/tx_hold_fifo.v -l ../custom.el -f verilog-auto -f save-buffer
 
xemacs -batch verilog/xge_mac.v -l ../custom.el -f verilog-auto -f save-buffer
emacs -batch verilog/xge_mac.v -l ../custom.el -f verilog-auto -f save-buffer
 
#xemacs -batch verilog/top_altera.v -l ../custom.el -f verilog-auto -f save-buffer
#xemacs -batch verilog/top_altera_loopback.v -l ../custom.el -f verilog-auto -f save-buffer
 
#xemacs -batch verilog/loopback_block.v -l ../custom.el -f verilog-auto -f save-buffer
 
 
#xemacs -batch ../tbench/verilog/tb_altera.v -l ../../rtl/custom.el -f verilog-auto -f save-buffer
#xemacs -batch ../tbench/verilog/tb_altera_loopback.v -l ../../rtl/custom.el -f verilog-auto -f save-buffer
xemacs -batch ../tbench/verilog/tb_xge_mac.v -l ../../rtl/custom.el -f verilog-auto -f save-buffer
 
emacs -batch ../tbench/verilog/tb_xge_mac.v -l ../../rtl/custom.el -f verilog-auto -f save-buffer

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