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URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

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  • This comparison shows the changes necessary to convert path 
    /xge_mac
    from Rev 20 to Rev 21
    ↔ Reverse comparison
  •

Rev 20 → Rev 21

/trunk/rtl/verilog/rx_enqueue.v
57,12 → 57,12
 
input clk_xgmii_rx;
input reset_xgmii_rx_n;
 
input [63:0] xgmii_rxd;
input [7:0] xgmii_rxc;
 
input rxdfifo_wfull;
 
input [63:0] rxhfifo_rdata;
input [7:0] rxhfifo_rstatus;
input rxhfifo_rempty;
70,7 → 70,7
 
output [63:0] rxdfifo_wdata;
output [7:0] rxdfifo_wstatus;
output rxdfifo_wen;
output rxdfifo_wen;
 
output rxhfifo_ren;
 
171,6 → 171,38
SM_IDLE = 3'd0,
SM_RX = 3'd1;
 
// count the number of set bits in a nibble
function [2:0] bit_cnt4;
input [3:0] bits;
begin
case (bits)
0: bit_cnt4 = 0;
1: bit_cnt4 = 1;
2: bit_cnt4 = 1;
3: bit_cnt4 = 2;
4: bit_cnt4 = 1;
5: bit_cnt4 = 2;
6: bit_cnt4 = 2;
7: bit_cnt4 = 3;
8: bit_cnt4 = 1;
9: bit_cnt4 = 2;
10: bit_cnt4 = 2;
11: bit_cnt4 = 3;
12: bit_cnt4 = 2;
13: bit_cnt4 = 3;
14: bit_cnt4 = 3;
15: bit_cnt4 = 4;
endcase
end
endfunction
 
function [3:0] bit_cnt8;
input [7:0] bits;
begin
bit_cnt8 = bit_cnt4(bits[3:0]) + bit_cnt4(bits[7:4]);
end
endfunction
 
always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin
 
if (reset_xgmii_rx_n == 1'b0) begin
213,7 → 245,7
// Look for local/remote messages on lower 4 lanes and upper
// 4 lanes. This is a 64-bit interface but look at each 32-bit
// independantly.
 
local_fault_msg_det[1] <= (xgmii_rxd[63:32] ==
{`LOCAL_FAULT, 8'h0, 8'h0, `SEQUENCE} &&
xgmii_rxc[7:4] == 4'b0001);
240,7 → 272,7
xgmii_rxc_d1[7:4] <= xgmii_rxc[7:4];
 
if (xgmii_rxd[`LANE0] == `START && xgmii_rxc[0]) begin
 
xgxs_rxd_barrel <= xgmii_rxd;
xgxs_rxc_barrel <= xgmii_rxc;
 
323,7 → 355,7
// Per Clause 46. Control code during data must be reported
// as a CRC error. Indicated here by coding_error. Corrupt CRC
// if coding error is detected.
 
if (coding_error || next_coding_error) begin
crc32_d8 <= ~crc32_d64;
end
383,7 → 415,7
end
 
end
 
always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin
 
if (reset_xgmii_rx_n == 1'b0) begin
455,10 → 487,10
crc_clear = 1'b1;
next_coding_error = 1'b0;
next_pause_frame = 1'b0;
 
 
// Detect the start of a frame
 
if (xgxs_rxd_barrel_d1[`LANE0] == `START && xgxs_rxc_barrel_d1[0] &&
xgxs_rxd_barrel_d1[`LANE1] == `PREAMBLE && !xgxs_rxc_barrel_d1[1] &&
xgxs_rxd_barrel_d1[`LANE2] == `PREAMBLE && !xgxs_rxc_barrel_d1[2] &&
477,7 → 509,7
begin
 
// Pause frames are filtered
 
rxhfifo_wen = !pause_frame;
 
 
527,7 → 559,7
 
 
// Control character during data phase, force CRC error
 
if (|(xgxs_rxc_barrel_d1 & datamask)) begin
 
next_coding_error = 1'b1;
541,23 → 573,24
end
 
/* verilator lint_off WIDTH */
next_byte_cnt = curr_byte_cnt +
addmask[0] + addmask[1] + addmask[2] + addmask[3] +
addmask[4] + addmask[5] + addmask[6] + addmask[7];
//next_byte_cnt = curr_byte_cnt +
// addmask[0] + addmask[1] + addmask[2] + addmask[3] +
// addmask[4] + addmask[5] + addmask[6] + addmask[7];
/* verilator lint_on WIDTH */
// don't infer a chain of adders
next_byte_cnt = curr_byte_cnt + {10'b0, bit_cnt8(addmask[7:0])};
 
 
 
// We will not write to the fifo if all is left
// are four or less bytes of crc. We also strip off the
// crc, which requires looking one cycle ahead
// wstatus:
// wstatus:
// [2:0] modulus of packet length
 
// Look one cycle ahead for TERMINATE in lanes 0 to 4
 
if (xgxs_rxd_barrel[`LANE4] == `TERMINATE && xgxs_rxc_barrel[4]) begin
 
rxhfifo_wstatus[`RXSTATUS_EOP] = 1'b1;
rxhfifo_wstatus[2:0] = 3'd0;
 
577,11 → 610,11
crc_start_8b = 1'b1;
next_crc_bytes = 4'd7;
next_crc_rx = {xgxs_rxd_barrel[23:0], xgxs_rxd_barrel_d1[63:56]};
 
next_state = SM_IDLE;
 
end
 
if (xgxs_rxd_barrel[`LANE2] == `TERMINATE && xgxs_rxc_barrel[2]) begin
 
rxhfifo_wstatus[`RXSTATUS_EOP] = 1'b1;
607,7 → 640,7
next_state = SM_IDLE;
 
end
 
if (xgxs_rxd_barrel[`LANE0] == `TERMINATE && xgxs_rxc_barrel[0]) begin
 
rxhfifo_wstatus[`RXSTATUS_EOP] = 1'b1;
636,7 → 669,7
next_state = SM_IDLE;
 
end
 
if (xgxs_rxd_barrel_d1[`LANE6] == `TERMINATE &&
xgxs_rxc_barrel_d1[6]) begin
 
650,7 → 683,7
next_state = SM_IDLE;
 
end
 
if (xgxs_rxd_barrel_d1[`LANE5] == `TERMINATE &&
xgxs_rxc_barrel_d1[5]) begin
 
721,12 → 754,12
 
rxhfifo_ren = !rxhfifo_ralmost_empty_d1 ||
(pkt_pending && !rxhfifo_rstatus[`RXSTATUS_EOP]);
 
 
if (rxhfifo_ren_d1 && rxhfifo_rstatus[`RXSTATUS_SOP]) begin
 
// Reset drop flag on SOP
 
next_drop_data = 1'b0;
 
end
751,7 → 784,7
if (crc_done && !crc_good) begin
 
// Flag packet with error when CRC error is detected
 
rxdfifo_wstatus[`RXSTATUS_ERR] = 1'b1;
 
end
759,4 → 792,3
end
 
endmodule
 
/trunk/rtl/verilog/generic_mem_small.v
87,6 → 87,7
// Registers
 
reg [DWIDTH-1:0] mem_rdata;
reg [AWIDTH-1:0] raddr_d1;
 
 
// Memory
113,6 → 114,31
// Memory Read
 
// Generate registered memory read
 
`ifdef XIL
 
//always @(posedge rclk)
//begin
// if (ren) begin
// raddr_d1 <= raddr;
// end
//end
//always @(raddr_d1, rclk)
//begin
// mem_rdata = mem[raddr_d1[AWIDTH-1:0]];
//end
 
always @(posedge rclk)
begin
if (!rrst_n) begin
mem_rdata <= {(DWIDTH){1'b0}};
end else if (ren) begin
mem_rdata <= mem[raddr[AWIDTH-1:0]];
end
end
 
`else
 
always @(posedge rclk or negedge rrst_n)
begin
if (!rrst_n) begin
122,6 → 148,8
end
end
 
`endif
 
generate
if (REGISTER_READ) begin
 
/trunk/rtl/verilog/tx_dequeue.v
297,8 → 297,8
always @(/*AS*/crc32_tx or ctrl_tx_enable_ctx or curr_state_enc or eop
or frame_available or ifg_4b_add or ifg_8b2_add or ifg_8b_add
or ifg_deficit or start_on_lane0 or status_local_fault_ctx
or txhfifo_ralmost_empty or txhfifo_rdata_d1
or txhfifo_rempty or txhfifo_rstatus) begin
or status_remote_fault_ctx or txhfifo_ralmost_empty
or txhfifo_rdata_d1 or txhfifo_rempty or txhfifo_rstatus) begin
 
next_state_enc = curr_state_enc;
 
/trunk/rtl/verilog/generic_mem_medium.v
87,8 → 87,8
// Registers
 
reg [DWIDTH-1:0] mem_rdata;
reg [AWIDTH-1:0] raddr_d1;
 
 
// Memory
 
reg [DWIDTH-1:0] mem [0:RAM_DEPTH-1];
113,6 → 113,31
// Memory Read
 
// Generate registered memory read
 
`ifdef XIL
 
//always @(posedge rclk)
//begin
// if (ren) begin
// raddr_d1 <= raddr;
// end
//end
//always @(raddr_d1, rclk)
//begin
// mem_rdata = mem[raddr_d1[AWIDTH-1:0]];
//end
 
always @(posedge rclk)
begin
if (!rrst_n) begin
mem_rdata <= {(DWIDTH){1'b0}};
end else if (ren) begin
mem_rdata <= mem[raddr[AWIDTH-1:0]];
end
end
 
`else
 
always @(posedge rclk or negedge rrst_n)
begin
if (!rrst_n) begin
122,6 → 147,8
end
end
 
`endif
 
generate
if (REGISTER_READ) begin
 
/trunk/rtl/auto_verilog.sh
18,4 → 18,6
 
emacs -batch verilog/xge_mac.v -l ../custom.el -f verilog-auto -f save-buffer
 
emacs -batch examples/test_chip.v -l ../custom.el -f verilog-auto -f save-buffer
 
emacs -batch ../tbench/verilog/tb_xge_mac.v -l ../../rtl/custom.el -f verilog-auto -f save-buffer
/trunk/tbench/systemc/sc_testcases.cpp
68,6 → 68,7
 
test_packet_size(50, 90, 50);
test_packet_size(9000, 9020, 20);
test_packet_size(9599, 9601, 10);
 
test_deficit_idle_count();
 
/trunk/tbench/verilog/tb_xge_mac.sv
41,6 → 41,7
 
//`define GXB
//`define XIL
//`define XIL_V10
 
module tb;
 
235,6 → 236,53
glbl glbl();
`endif
 
`ifdef XIL_V10
// Example of transceiver instance
xaui_v10_2_block xaui(// Outputs
.txoutclk (),
.xgmii_rxd (xgmii_rxd[63:0]),
.xgmii_rxc (xgmii_rxc[7:0]),
.xaui_tx_l0_p (xaui_tx_l0_p),
.xaui_tx_l0_n (xaui_tx_l0_n),
.xaui_tx_l1_p (xaui_tx_l1_p),
.xaui_tx_l1_n (xaui_tx_l1_n),
.xaui_tx_l2_p (xaui_tx_l2_p),
.xaui_tx_l2_n (xaui_tx_l2_n),
.xaui_tx_l3_p (xaui_tx_l3_p),
.xaui_tx_l3_n (xaui_tx_l3_n),
.txlock (),
.align_status (),
.sync_status (),
.mgt_tx_ready (),
.drp_o (),
.drp_rdy (),
.status_vector (),
// Inputs
.dclk (clk_156m25),
.clk156 (clk_156m25),
.refclk (clk_156m25),
.reset (~reset_156m25_n),
.reset156 (~reset_156m25_n),
.xgmii_txd (xgmii_txd[63:0]),
.xgmii_txc (xgmii_txc[7:0]),
.xaui_rx_l0_p (xaui_tx_l0_p),
.xaui_rx_l0_n (xaui_tx_l0_n),
.xaui_rx_l1_p (xaui_tx_l1_p),
.xaui_rx_l1_n (xaui_tx_l1_n),
.xaui_rx_l2_p (xaui_tx_l2_p),
.xaui_rx_l2_n (xaui_tx_l2_n),
.xaui_rx_l3_p (xaui_tx_l3_p),
.xaui_rx_l3_n (xaui_tx_l3_n),
.signal_detect (4'b1111),
.drp_addr (9'b0),
.drp_en (4'b0),
.drp_i (16'b0),
.drp_we (4'b0),
.configuration_vector (7'b0));
 
glbl glbl();
`endif
 
//---
// Unused for this testbench
 
258,8 → 306,10
 
`ifndef GXB
`ifndef XIL
assign xgmii_rxc = xgmii_txc;
assign xgmii_rxd = xgmii_txd;
`ifndef XIL_V10
assign xgmii_rxc = xgmii_txc;
assign xgmii_rxd = xgmii_txd;
`endif
`endif
`endif
 
/trunk/README.TXT
59,7 → 59,24
frames from the receive interface (pkt_rx_data) and prints out the results.
 
 
Simulation output:
 
------------------------
Received Packet
------------------------
0000010000010010
9400000288b50001
0203040506070809
0a0b0c0d0e0f1011
1213141516171819
1a1b1c1d1e1f2021
2223242526272829
2a2b2c2d2e2f3031
3233343506b33d40
------------------------
All packets received. Sumulation done!!!
 
 
------------------------
2.2 SystemC Simulation
------------------------
88,7 → 105,7
Simulation output:
 
-----------------------
Packet size
Packet size
-----------------------
SCOREBOARD XGMII INTERFACE TX (60)
SCOREBOARD XGMII INTERFACE TX (60)
98,8 → 115,3
SCOREBOARD XGMII INTERFACE TX (60)
SCOREBOARD PACKET INTERFACE RX (TX SIZE=60 RX SIZE=60)
...
 
 
 
 
 

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