OpenCores
URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /xge_mac
    from Rev 26 to Rev 27
    ↔ Reverse comparison
  •

Rev 26 → Rev 27

/trunk/rtl/verilog/rx_enqueue.v
299,9 → 299,18
end
else if (xgmii_rxd[`LANE4] == `START && xgmii_rxc[4]) begin
 
xgxs_rxd_barrel <= {xgmii_rxd[31:0], xgmii_rxd_d1[63:32]};
xgxs_rxc_barrel <= {xgmii_rxc[3:0], xgmii_rxc_d1[7:4]};
xgxs_rxd_barrel[63:32] <= xgmii_rxd[31:0];
xgxs_rxc_barrel[7:4] <= xgmii_rxc[3:0];
 
if (barrel_shift) begin
xgxs_rxd_barrel[31:0] <= xgmii_rxd_d1[63:32];
xgxs_rxc_barrel[3:0] <= xgmii_rxc_d1[7:4];
end
else begin
xgxs_rxd_barrel[31:0] <= 32'h07070707;
xgxs_rxc_barrel[3:0] <= 4'hf;
end
 
barrel_shift <= 1'b1;
 
end
/trunk/rtl/verilog/wishbone_if.v
40,7 → 40,8
 
module wishbone_if(/*AUTOARG*/
// Outputs
wb_dat_o, wb_ack_o, wb_int_o, ctrl_tx_enable,
wb_dat_o, wb_ack_o, wb_int_o, ctrl_tx_enable, clear_stats_tx_octets,
clear_stats_tx_pkts, clear_stats_rx_octets, clear_stats_rx_pkts,
// Inputs
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_stb_i, wb_cyc_i,
status_crc_error, status_fragment_error, status_txdfifo_ovflow,
87,23 → 88,39
 
output ctrl_tx_enable;
 
output clear_stats_tx_octets;
output clear_stats_tx_pkts;
output clear_stats_rx_octets;
output clear_stats_rx_pkts;
 
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg clear_stats_rx_octets;
reg clear_stats_rx_pkts;
reg clear_stats_tx_octets;
reg clear_stats_tx_pkts;
reg [31:0] wb_dat_o;
reg wb_int_o;
// End of automatics
 
reg [31:0] next_wb_dat_o;
reg next_wb_int_o;
 
reg [0:0] cpureg_config0;
reg [0:0] next_cpureg_config0;
 
reg [8:0] cpureg_int_pending;
reg [8:0] next_cpureg_int_pending;
 
reg [8:0] cpureg_int_mask;
reg [8:0] next_cpureg_int_mask;
 
reg cpuack;
reg next_cpuack;
 
reg status_remote_fault_d1;
reg status_local_fault_d1;
 
 
/*AUTOWIRE*/
 
wire [8:0] int_sources;
133,117 → 150,151
 
assign ctrl_tx_enable = cpureg_config0[0];
 
 
 
//---
// Wishbone signals
 
assign wb_ack_o = cpuack && wb_stb_i;
 
always @(posedge wb_clk_i or posedge wb_rst_i) begin
always @(/*AS*/cpureg_config0 or cpureg_int_mask or cpureg_int_pending
or int_sources or stats_rx_octets or stats_rx_pkts
or stats_tx_octets or stats_tx_pkts or wb_adr_i or wb_cyc_i
or wb_dat_i or wb_dat_o or wb_stb_i or wb_we_i) begin
 
if (wb_rst_i == 1'b1) begin
next_wb_dat_o = wb_dat_o;
 
cpureg_config0 <= 1'h1;
cpureg_int_pending <= 9'b0;
cpureg_int_mask <= 9'b0;
next_wb_int_o = |(cpureg_int_pending & cpureg_int_mask);
 
wb_dat_o <= 32'b0;
wb_int_o <= 1'b0;
next_cpureg_int_pending = cpureg_int_pending | int_sources;
 
cpuack <= 1'b0;
next_cpuack = wb_cyc_i && wb_stb_i;
 
status_remote_fault_d1 <= 1'b0;
status_local_fault_d1 <= 1'b0;
//---
// Registers
 
end
else begin
next_cpureg_config0 = cpureg_config0;
next_cpureg_int_mask = cpureg_int_mask;
 
wb_int_o <= |(cpureg_int_pending & cpureg_int_mask);
//---
// Clear on read signals
 
cpureg_int_pending <= cpureg_int_pending | int_sources;
clear_stats_tx_octets = 1'b0;
clear_stats_tx_pkts = 1'b0;
clear_stats_rx_octets = 1'b0;
clear_stats_rx_pkts = 1'b0;
 
cpuack <= wb_cyc_i && wb_stb_i;
//---
// Read access
 
status_remote_fault_d1 <= status_remote_fault;
status_local_fault_d1 <= status_local_fault;
if (wb_cyc_i && wb_stb_i && !wb_we_i) begin
 
//---
// Read access
case ({wb_adr_i[7:2], 2'b0})
 
if (wb_cyc_i && wb_stb_i && !wb_we_i) begin
`CPUREG_CONFIG0: begin
next_wb_dat_o = {31'b0, cpureg_config0};
end
 
case ({wb_adr_i[7:2], 2'b0})
`CPUREG_INT_PENDING: begin
next_wb_dat_o = {23'b0, cpureg_int_pending};
next_cpureg_int_pending = int_sources;
next_wb_int_o = 1'b0;
end
 
`CPUREG_CONFIG0: begin
wb_dat_o <= {31'b0, cpureg_config0};
end
`CPUREG_INT_STATUS: begin
next_wb_dat_o = {23'b0, int_sources};
end
 
`CPUREG_INT_PENDING: begin
wb_dat_o <= {23'b0, cpureg_int_pending};
cpureg_int_pending <= int_sources;
wb_int_o <= 1'b0;
end
`CPUREG_INT_MASK: begin
next_wb_dat_o = {23'b0, cpureg_int_mask};
end
 
`CPUREG_INT_STATUS: begin
wb_dat_o <= {23'b0, int_sources};
end
`CPUREG_STATSTXOCTETS: begin
next_wb_dat_o = stats_tx_octets;
clear_stats_tx_octets = 1'b1;
end
 
`CPUREG_INT_MASK: begin
wb_dat_o <= {23'b0, cpureg_int_mask};
end
`CPUREG_STATSTXPKTS: begin
next_wb_dat_o = stats_tx_pkts;
clear_stats_tx_pkts = 1'b1;
end
 
`CPUREG_STATSTXOCTETS: begin
wb_dat_o <= stats_tx_octets;
end
`CPUREG_STATSRXOCTETS: begin
next_wb_dat_o = stats_rx_octets;
clear_stats_rx_octets = 1'b1;
end
 
`CPUREG_STATSTXPKTS: begin
wb_dat_o <= stats_tx_pkts;
end
`CPUREG_STATSRXPKTS: begin
next_wb_dat_o = stats_rx_pkts;
clear_stats_rx_pkts = 1'b1;
end
 
`CPUREG_STATSRXOCTETS: begin
wb_dat_o <= stats_rx_octets;
end
default: begin
end
 
`CPUREG_STATSRXPKTS: begin
wb_dat_o <= stats_rx_pkts;
end
endcase
 
default: begin
end
end
 
endcase
//---
// Write access
 
end
if (wb_cyc_i && wb_stb_i && wb_we_i) begin
 
//---
// Write access
case ({wb_adr_i[7:2], 2'b0})
 
if (wb_cyc_i && wb_stb_i && wb_we_i) begin
`CPUREG_CONFIG0: begin
next_cpureg_config0 = wb_dat_i[0:0];
end
 
case ({wb_adr_i[7:2], 2'b0})
`CPUREG_INT_PENDING: begin
next_cpureg_int_pending = wb_dat_i[8:0] | cpureg_int_pending | int_sources;
end
 
`CPUREG_CONFIG0: begin
cpureg_config0 <= wb_dat_i[0:0];
end
`CPUREG_INT_MASK: begin
next_cpureg_int_mask = wb_dat_i[8:0];
end
 
`CPUREG_INT_PENDING: begin
cpureg_int_pending <= wb_dat_i[8:0] | cpureg_int_pending | int_sources;
end
default: begin
end
 
`CPUREG_INT_MASK: begin
cpureg_int_mask <= wb_dat_i[8:0];
end
endcase
 
default: begin
end
end
 
endcase
end
 
end
always @(posedge wb_clk_i or posedge wb_rst_i) begin
 
if (wb_rst_i == 1'b1) begin
 
cpureg_config0 <= 1'h1;
cpureg_int_pending <= 9'b0;
cpureg_int_mask <= 9'b0;
 
wb_dat_o <= 32'b0;
wb_int_o <= 1'b0;
 
cpuack <= 1'b0;
 
status_remote_fault_d1 <= 1'b0;
status_local_fault_d1 <= 1'b0;
 
end
else begin
 
cpureg_config0 <= next_cpureg_config0;
cpureg_int_pending <= next_cpureg_int_pending;
cpureg_int_mask <= next_cpureg_int_mask;
 
wb_dat_o <= next_wb_dat_o;
wb_int_o <= next_wb_int_o;
 
cpuack <= next_cpuack;
 
status_remote_fault_d1 <= status_remote_fault;
status_local_fault_d1 <= status_local_fault;
 
end
 
end
 
endmodule
/trunk/rtl/verilog/stats_sm.v
43,7 → 43,8
stats_tx_octets, stats_tx_pkts, stats_rx_octets, stats_rx_pkts,
// Inputs
wb_clk_i, wb_rst_i, txsfifo_rdata, txsfifo_rempty, rxsfifo_rdata,
rxsfifo_rempty
rxsfifo_rempty, clear_stats_tx_octets, clear_stats_tx_pkts,
clear_stats_rx_octets, clear_stats_rx_pkts
);
 
 
62,6 → 63,11
output [31:0] stats_rx_octets;
output [31:0] stats_rx_pkts;
 
input clear_stats_tx_octets;
input clear_stats_tx_pkts;
input clear_stats_rx_octets;
input clear_stats_rx_pkts;
 
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [31:0] stats_rx_octets;
111,24 → 117,26
 
end
 
always @(/*AS*/rxsfifo_rdata or rxsfifo_rempty_d1 or stats_rx_octets
always @(/*AS*/clear_stats_rx_octets or clear_stats_rx_pkts
or clear_stats_tx_octets or clear_stats_tx_pkts
or rxsfifo_rdata or rxsfifo_rempty_d1 or stats_rx_octets
or stats_rx_pkts or stats_tx_octets or stats_tx_pkts
or txsfifo_rdata or txsfifo_rempty_d1) begin
 
next_stats_tx_octets = stats_tx_octets;
next_stats_tx_pkts = stats_tx_pkts;
next_stats_tx_octets = {32{~clear_stats_tx_octets}} & stats_tx_octets;
next_stats_tx_pkts = {32{~clear_stats_tx_pkts}} & stats_tx_pkts;
 
next_stats_rx_octets = stats_rx_octets;
next_stats_rx_pkts = stats_rx_pkts;
next_stats_rx_octets = {32{~clear_stats_rx_octets}} & stats_rx_octets;
next_stats_rx_pkts = {32{~clear_stats_rx_pkts}} & stats_rx_pkts;
 
if (!txsfifo_rempty_d1) begin
next_stats_tx_octets = stats_tx_octets + {18'b0, txsfifo_rdata};
next_stats_tx_pkts = stats_tx_pkts + 32'b1;
next_stats_tx_octets = next_stats_tx_octets + {18'b0, txsfifo_rdata};
next_stats_tx_pkts = next_stats_tx_pkts + 32'b1;
end
 
if (!rxsfifo_rempty_d1) begin
next_stats_rx_octets = stats_rx_octets + {18'b0, rxsfifo_rdata};
next_stats_rx_pkts = stats_rx_pkts + 32'b1;
next_stats_rx_octets = next_stats_rx_octets + {18'b0, rxsfifo_rdata};
next_stats_rx_pkts = next_stats_rx_pkts + 32'b1;
end
 
end
/trunk/rtl/verilog/stats.v
44,12 → 44,17
// Inputs
wb_rst_i, wb_clk_i, txsfifo_wen, txsfifo_wdata, rxsfifo_wen,
rxsfifo_wdata, reset_xgmii_tx_n, reset_xgmii_rx_n, clk_xgmii_tx,
clk_xgmii_rx
clk_xgmii_rx, clear_stats_tx_pkts, clear_stats_tx_octets,
clear_stats_rx_pkts, clear_stats_rx_octets
);
 
 
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input clear_stats_rx_octets; // To stats_sm0 of stats_sm.v
input clear_stats_rx_pkts; // To stats_sm0 of stats_sm.v
input clear_stats_tx_octets; // To stats_sm0 of stats_sm.v
input clear_stats_tx_pkts; // To stats_sm0 of stats_sm.v
input clk_xgmii_rx; // To rx_stats_fifo0 of rx_stats_fifo.v
input clk_xgmii_tx; // To tx_stats_fifo0 of tx_stats_fifo.v
input reset_xgmii_rx_n; // To rx_stats_fifo0 of rx_stats_fifo.v
114,6 → 119,10
.txsfifo_rdata (txsfifo_rdata[13:0]),
.txsfifo_rempty (txsfifo_rempty),
.rxsfifo_rdata (rxsfifo_rdata[13:0]),
.rxsfifo_rempty (rxsfifo_rempty));
.rxsfifo_rempty (rxsfifo_rempty),
.clear_stats_tx_octets(clear_stats_tx_octets),
.clear_stats_tx_pkts (clear_stats_tx_pkts),
.clear_stats_rx_octets(clear_stats_rx_octets),
.clear_stats_rx_pkts (clear_stats_rx_pkts));
 
endmodule
/trunk/rtl/verilog/xge_mac.v
94,6 → 94,10
 
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire clear_stats_rx_octets; // From wishbone_if0 of wishbone_if.v
wire clear_stats_rx_pkts; // From wishbone_if0 of wishbone_if.v
wire clear_stats_tx_octets; // From wishbone_if0 of wishbone_if.v
wire clear_stats_tx_pkts; // From wishbone_if0 of wishbone_if.v
wire ctrl_tx_enable; // From wishbone_if0 of wishbone_if.v
wire ctrl_tx_enable_ctx; // From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v
wire [1:0] local_fault_msg_det; // From rx_eq0 of rx_enqueue.v
378,6 → 382,10
.stats_tx_octets (stats_tx_octets[31:0]),
.stats_tx_pkts (stats_tx_pkts[31:0]),
// Inputs
.clear_stats_rx_octets (clear_stats_rx_octets),
.clear_stats_rx_pkts (clear_stats_rx_pkts),
.clear_stats_tx_octets (clear_stats_tx_octets),
.clear_stats_tx_pkts (clear_stats_tx_pkts),
.clk_xgmii_rx (clk_xgmii_rx),
.clk_xgmii_tx (clk_xgmii_tx),
.reset_xgmii_rx_n (reset_xgmii_rx_n),
400,6 → 408,10
.wb_ack_o (wb_ack_o),
.wb_int_o (wb_int_o),
.ctrl_tx_enable (ctrl_tx_enable),
.clear_stats_tx_octets (clear_stats_tx_octets),
.clear_stats_tx_pkts (clear_stats_tx_pkts),
.clear_stats_rx_octets (clear_stats_rx_octets),
.clear_stats_rx_pkts (clear_stats_rx_pkts),
// Inputs
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.