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URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

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  • This comparison shows the changes necessary to convert path 
    /xge_mac
    from Rev 27 to Rev 28
    ↔ Reverse comparison
  •

Rev 27 → Rev 28

/trunk/rtl/include/defines.v
40,10 → 40,10
 
// CPU Registers
 
`define CPUREG_CONFIG0 8'h00
`define CPUREG_INT_PENDING 8'h08
`define CPUREG_INT_STATUS 8'h0c
`define CPUREG_INT_MASK 8'h10
`define CPUREG_CONFIG0 8'h00
`define CPUREG_INT_PENDING 8'h08
`define CPUREG_INT_STATUS 8'h0c
`define CPUREG_INT_MASK 8'h10
 
`define CPUREG_STATSTXOCTETS 8'h80
`define CPUREG_STATSTXPKTS 8'h84
123,4 → 123,9
 
// Changed system packet interface to big endian (12/12/2009)
// Comment out to use legacy mode
`define BIGENDIAN
`define BIGENDIAN
 
// MAX FRAME SIZE
// Frames received with longer lenght will be marked as "errored" and the pkt_rx_err
// signal will be assert. Lenght includes CRC.
`define MAX_FRAME_SIZE 14'd16000
/trunk/rtl/verilog/rx_enqueue.v
43,8 → 43,9
rxdfifo_wdata, rxdfifo_wstatus, rxdfifo_wen, rxhfifo_ren,
rxhfifo_wdata, rxhfifo_wstatus, rxhfifo_wen, local_fault_msg_det,
remote_fault_msg_det, status_crc_error_tog,
status_fragment_error_tog, status_rxdfifo_ovflow_tog,
status_pause_frame_rx_tog, rxsfifo_wen, rxsfifo_wdata,
status_fragment_error_tog, status_lenght_error_tog,
status_rxdfifo_ovflow_tog, status_pause_frame_rx_tog, rxsfifo_wen,
rxsfifo_wdata,
// Inputs
clk_xgmii_rx, reset_xgmii_rx_n, xgmii_rxd, xgmii_rxc, rxdfifo_wfull,
rxhfifo_rdata, rxhfifo_rstatus, rxhfifo_rempty,
83,6 → 84,7
 
output status_crc_error_tog;
output status_fragment_error_tog;
output status_lenght_error_tog;
output status_rxdfifo_ovflow_tog;
 
output status_pause_frame_rx_tog;
107,6 → 109,7
reg rxsfifo_wen;
reg status_crc_error_tog;
reg status_fragment_error_tog;
reg status_lenght_error_tog;
reg status_pause_frame_rx_tog;
reg status_rxdfifo_ovflow_tog;
// End of automatics
145,6 → 148,7
 
reg [13:0] curr_byte_cnt;
reg [13:0] next_byte_cnt;
reg [13:0] frame_lenght;
 
reg frame_end_flag;
reg next_frame_end_flag;
155,6 → 159,8
reg fragment_error;
reg rxd_ovflow_error;
 
reg lenght_error;
 
reg coding_error;
reg next_coding_error;
 
243,6 → 249,7
 
status_crc_error_tog <= 1'b0;
status_fragment_error_tog <= 1'b0;
status_lenght_error_tog <= 1'b0;
status_rxdfifo_ovflow_tog <= 1'b0;
 
status_pause_frame_rx_tog <= 1'b0;
252,12 → 259,16
 
datamask <= 8'b0;
 
lenght_error <= 1'b0;
 
end
else begin
 
rxsfifo_wen <= 1'b0;
rxsfifo_wdata <= curr_byte_cnt + {11'b0, frame_end_bytes};
rxsfifo_wdata <= frame_lenght;
 
lenght_error <= 1'b0;
 
//---
// Link status RC layer
// Look for local/remote messages on lower 4 lanes and upper
434,6 → 445,14
rxsfifo_wen <= 1'b1;
end
 
//---
// Check frame lenght
 
if (frame_end_flag && frame_lenght > `MAX_FRAME_SIZE) begin
lenght_error <= 1'b1;
status_lenght_error_tog <= ~status_lenght_error_tog;
end
 
end
 
end
485,8 → 504,8
 
 
always @(/*AS*/coding_error or crc_rx or curr_byte_cnt or curr_state
or datamask or pause_frame or xgxs_rxc_barrel
or xgxs_rxc_barrel_d1 or xgxs_rxd_barrel
or datamask or frame_end_bytes or pause_frame
or xgxs_rxc_barrel or xgxs_rxc_barrel_d1 or xgxs_rxd_barrel
or xgxs_rxd_barrel_d1) begin
 
next_state = curr_state;
506,6 → 525,8
 
fragment_error = 1'b0;
 
frame_lenght = curr_byte_cnt + {11'b0, frame_end_bytes};
 
next_coding_error = coding_error;
next_pause_frame = pause_frame;
 
574,7 → 595,7
end
 
end
else if (curr_byte_cnt > 14'd9900) begin
else if (curr_byte_cnt > 14'd16100) begin
 
// Frame too long, TERMMINATE must have been corrupted.
// Abort transfer, write a fake EOP, report as fragment.
797,9 → 818,9
 
end
 
always @(/*AS*/crc_done or crc_good or drop_data or pkt_pending
or rxdfifo_wfull or rxhfifo_ralmost_empty_d1 or rxhfifo_rdata
or rxhfifo_ren_d1 or rxhfifo_rstatus) begin
always @(/*AS*/crc_done or crc_good or drop_data or lenght_error
or pkt_pending or rxdfifo_wfull or rxhfifo_ralmost_empty_d1
or rxhfifo_rdata or rxhfifo_ren_d1 or rxhfifo_rstatus) begin
 
rxd_ovflow_error = 1'b0;
 
841,7 → 862,7
 
 
 
if (crc_done && !crc_good) begin
if ((crc_done && !crc_good) || lenght_error) begin
 
// Flag packet with error when CRC error is detected
 
/trunk/rtl/verilog/wishbone_if.v
44,10 → 44,11
clear_stats_tx_pkts, clear_stats_rx_octets, clear_stats_rx_pkts,
// Inputs
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_stb_i, wb_cyc_i,
status_crc_error, status_fragment_error, status_txdfifo_ovflow,
status_txdfifo_udflow, status_rxdfifo_ovflow, status_rxdfifo_udflow,
status_pause_frame_rx, status_local_fault, status_remote_fault,
stats_tx_octets, stats_tx_pkts, stats_rx_octets, stats_rx_pkts
status_crc_error, status_fragment_error, status_lenght_error,
status_txdfifo_ovflow, status_txdfifo_udflow, status_rxdfifo_ovflow,
status_rxdfifo_udflow, status_pause_frame_rx, status_local_fault,
status_remote_fault, stats_tx_octets, stats_tx_pkts,
stats_rx_octets, stats_rx_pkts
);
 
 
66,6 → 67,7
 
input status_crc_error;
input status_fragment_error;
input status_lenght_error;
 
input status_txdfifo_ovflow;
 
109,11 → 111,11
reg [0:0] cpureg_config0;
reg [0:0] next_cpureg_config0;
 
reg [8:0] cpureg_int_pending;
reg [8:0] next_cpureg_int_pending;
reg [9:0] cpureg_int_pending;
reg [9:0] next_cpureg_int_pending;
 
reg [8:0] cpureg_int_mask;
reg [8:0] next_cpureg_int_mask;
reg [9:0] cpureg_int_mask;
reg [9:0] next_cpureg_int_mask;
 
reg cpuack;
reg next_cpuack;
123,7 → 125,7
 
/*AUTOWIRE*/
 
wire [8:0] int_sources;
wire [9:0] int_sources;
 
 
//---
131,6 → 133,7
// expect a pulse signal.
 
assign int_sources = {
status_lenght_error,
status_fragment_error,
status_crc_error,
 
194,17 → 197,17
end
 
`CPUREG_INT_PENDING: begin
next_wb_dat_o = {23'b0, cpureg_int_pending};
next_wb_dat_o = {22'b0, cpureg_int_pending};
next_cpureg_int_pending = int_sources;
next_wb_int_o = 1'b0;
end
 
`CPUREG_INT_STATUS: begin
next_wb_dat_o = {23'b0, int_sources};
next_wb_dat_o = {22'b0, int_sources};
end
 
`CPUREG_INT_MASK: begin
next_wb_dat_o = {23'b0, cpureg_int_mask};
next_wb_dat_o = {22'b0, cpureg_int_mask};
end
 
`CPUREG_STATSTXOCTETS: begin
246,11 → 249,11
end
 
`CPUREG_INT_PENDING: begin
next_cpureg_int_pending = wb_dat_i[8:0] | cpureg_int_pending | int_sources;
next_cpureg_int_pending = wb_dat_i[9:0] | cpureg_int_pending | int_sources;
end
 
`CPUREG_INT_MASK: begin
next_cpureg_int_mask = wb_dat_i[8:0];
next_cpureg_int_mask = wb_dat_i[9:0];
end
 
default: begin
267,8 → 270,8
if (wb_rst_i == 1'b1) begin
 
cpureg_config0 <= 1'h1;
cpureg_int_pending <= 9'b0;
cpureg_int_mask <= 9'b0;
cpureg_int_pending <= 10'b0;
cpureg_int_mask <= 10'b0;
 
wb_dat_o <= 32'b0;
wb_int_o <= 1'b0;
/trunk/rtl/verilog/sync_clk_wb.v
40,15 → 40,16
 
module sync_clk_wb(/*AUTOARG*/
// Outputs
status_crc_error, status_fragment_error, status_txdfifo_ovflow,
status_txdfifo_udflow, status_rxdfifo_ovflow, status_rxdfifo_udflow,
status_pause_frame_rx, status_local_fault, status_remote_fault,
status_crc_error, status_fragment_error, status_lenght_error,
status_txdfifo_ovflow, status_txdfifo_udflow, status_rxdfifo_ovflow,
status_rxdfifo_udflow, status_pause_frame_rx, status_local_fault,
status_remote_fault,
// Inputs
wb_clk_i, wb_rst_i, status_crc_error_tog, status_fragment_error_tog,
status_txdfifo_ovflow_tog, status_txdfifo_udflow_tog,
status_rxdfifo_ovflow_tog, status_rxdfifo_udflow_tog,
status_pause_frame_rx_tog, status_local_fault_crx,
status_remote_fault_crx
status_lenght_error_tog, status_txdfifo_ovflow_tog,
status_txdfifo_udflow_tog, status_rxdfifo_ovflow_tog,
status_rxdfifo_udflow_tog, status_pause_frame_rx_tog,
status_local_fault_crx, status_remote_fault_crx
);
 
input wb_clk_i;
56,6 → 57,7
 
input status_crc_error_tog;
input status_fragment_error_tog;
input status_lenght_error_tog;
 
input status_txdfifo_ovflow_tog;
 
72,6 → 74,7
 
output status_crc_error;
output status_fragment_error;
output status_lenght_error;
 
output status_txdfifo_ovflow;
 
90,9 → 93,10
 
/*AUTOWIRE*/
 
wire [6:0] sig_out1;
wire [7:0] sig_out1;
wire [1:0] sig_out2;
 
assign status_lenght_error = sig_out1[7];
assign status_crc_error = sig_out1[6];
assign status_fragment_error = sig_out1[5];
assign status_txdfifo_ovflow = sig_out1[4];
104,7 → 108,7
assign status_local_fault = sig_out2[1];
assign status_remote_fault = sig_out2[0];
 
meta_sync #(.DWIDTH (7), .EDGE_DETECT (1)) meta_sync0 (
meta_sync #(.DWIDTH (8), .EDGE_DETECT (1)) meta_sync0 (
// Outputs
.out (sig_out1),
// Inputs
111,6 → 115,7
.clk (wb_clk_i),
.reset_n (~wb_rst_i),
.in ({
status_lenght_error_tog,
status_crc_error_tog,
status_fragment_error_tog,
status_txdfifo_ovflow_tog,
/trunk/rtl/verilog/xge_mac.v
129,6 → 129,8
wire status_crc_error_tog; // From rx_eq0 of rx_enqueue.v
wire status_fragment_error; // From sync_clk_wb0 of sync_clk_wb.v
wire status_fragment_error_tog;// From rx_eq0 of rx_enqueue.v
wire status_lenght_error; // From sync_clk_wb0 of sync_clk_wb.v
wire status_lenght_error_tog;// From rx_eq0 of rx_enqueue.v
wire status_local_fault; // From sync_clk_wb0 of sync_clk_wb.v
wire status_local_fault_crx; // From fault_sm0 of fault_sm.v
wire status_local_fault_ctx; // From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v
182,6 → 184,7
.remote_fault_msg_det (remote_fault_msg_det[1:0]),
.status_crc_error_tog (status_crc_error_tog),
.status_fragment_error_tog(status_fragment_error_tog),
.status_lenght_error_tog(status_lenght_error_tog),
.status_rxdfifo_ovflow_tog(status_rxdfifo_ovflow_tog),
.status_pause_frame_rx_tog(status_pause_frame_rx_tog),
.rxsfifo_wen (rxsfifo_wen),
343,6 → 346,7
// Outputs
.status_crc_error (status_crc_error),
.status_fragment_error (status_fragment_error),
.status_lenght_error (status_lenght_error),
.status_txdfifo_ovflow (status_txdfifo_ovflow),
.status_txdfifo_udflow (status_txdfifo_udflow),
.status_rxdfifo_ovflow (status_rxdfifo_ovflow),
355,6 → 359,7
.wb_rst_i (wb_rst_i),
.status_crc_error_tog (status_crc_error_tog),
.status_fragment_error_tog(status_fragment_error_tog),
.status_lenght_error_tog(status_lenght_error_tog),
.status_txdfifo_ovflow_tog(status_txdfifo_ovflow_tog),
.status_txdfifo_udflow_tog(status_txdfifo_udflow_tog),
.status_rxdfifo_ovflow_tog(status_rxdfifo_ovflow_tog),
422,6 → 427,7
.wb_cyc_i (wb_cyc_i),
.status_crc_error (status_crc_error),
.status_fragment_error (status_fragment_error),
.status_lenght_error (status_lenght_error),
.status_txdfifo_ovflow (status_txdfifo_ovflow),
.status_txdfifo_udflow (status_txdfifo_udflow),
.status_rxdfifo_ovflow (status_rxdfifo_ovflow),

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