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Rev 1 → Rev 2

/rtl/xtea.vhd
0,0 → 1,109
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity xtea is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic;
block_in : in std_logic_vector(63 downto 0);
key : in std_logic_vector(127 downto 0);
v_0_out : out std_logic_vector(31 downto 0);
v_1_out : out std_logic_vector(31 downto 0));
end xtea;
 
architecture Behavioral of xtea is
 
signal delta_s : unsigned(31 downto 0);
 
component round_f is
port(v_in : in std_logic_vector(31 downto 0);
last_val : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(31 downto 0));
end component;
 
component key_schedule is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (0, enc) (1, dec)
val : in std_logic_vector(1 downto 0);
key : in std_logic_vector(127 downto 0);
subkey : out std_logic_vector(31 downto 0));
end component;
signal subkey_s : std_logic_vector(31 downto 0);
signal cnt_s : unsigned(1 downto 0);
 
signal v_0_s, v_1_s : unsigned(31 downto 0);
signal output_s : std_logic_vector(31 downto 0);
signal input_a_s : std_logic_vector(31 downto 0);
begin
 
KEY_SCHEDULE_0 : key_schedule port map (clk, rst, enc, std_logic_vector(cnt_s), key, subkey_s);
 
pr_cnt : process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
cnt_s <= (others => '0');
else
cnt_s <= cnt_s + 1;
end if;
end if;
end process;
 
ROUND_F_0 : round_f port map (input_a_s, subkey_s, output_s);
 
pr_macc : process(clk, rst, enc, block_in, output_s, cnt_s)
begin
if rising_edge(clk) then
if rst = '1' then
if enc = '0' then
v_1_s <= unsigned(block_in(63 downto 32));
v_0_s <= unsigned(block_in(31 downto 0));
else
v_0_s <= unsigned(block_in(63 downto 32));
v_1_s <= unsigned(block_in(31 downto 0));
end if;
else
if cnt_s = "00" then -- v_0
input_a_s <= std_logic_vector(v_1_s);
elsif cnt_s = "01" then -- v_0
if enc = '0' then
v_0_s <= v_0_s + unsigned(output_s);
else
v_0_s <= v_0_s - unsigned(output_s);
end if;
elsif cnt_s = "10" then -- v_1
input_a_s <= std_logic_vector(v_0_s);
else -- v_1
if enc = '0' then
v_1_s <= v_1_s + unsigned(output_s);
else
v_1_s <= v_1_s - unsigned(output_s);
end if;
end if;
end if;
end if;
end process;
 
v_0_out <= std_logic_vector(v_0_s);
v_1_out <= std_logic_vector(v_1_s);
 
end Behavioral;
 
/rtl/key_schedule.vhd
0,0 → 1,86
 
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity key_schedule is
port (clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (0, enc) (1, dec)
val : in std_logic_vector(1 downto 0);
key : in std_logic_vector(127 downto 0);
subkey : out std_logic_vector(31 downto 0));
end key_schedule;
 
architecture Behavioral of key_schedule is
 
type key_t is array (0 to 3) of unsigned(31 downto 0);
signal k : key_t;
signal sum_s : unsigned(31 downto 0);
signal sum_delay_s : unsigned(31 downto 0);
 
signal key_0_s : unsigned(31 downto 0);
signal key_1_s : unsigned(31 downto 0);
 
signal delta_s : unsigned(31 downto 0);
begin
 
delta_s <= X"9E3779B9";
 
k(3) <= unsigned(key(127 downto 96));
k(2) <= unsigned(key(95 downto 64));
k(1) <= unsigned(key(63 downto 32));
k(0) <= unsigned(key(31 downto 0));
gen_key : process(clk, rst, val, enc, k, sum_s, delta_s)
begin
if rising_edge(clk) then
if rst = '1' then
if enc = '1' then
sum_s <= X"8dde6e40";
else
sum_s <= (others => '0');
end if;
subkey <= (others => '0');
else
if val = "00" then
if enc = '1' then
subkey <= std_logic_vector(sum_s + k(to_integer(("00000000000" & sum_s(31 downto 11)) and x"00000003")));
sum_s <= sum_s - delta_s;
else
subkey <= std_logic_vector(sum_s + k(to_integer(sum_s and x"00000003")));
sum_s <= sum_s + delta_s;
end if;
elsif val = "10" then
if enc = '1' then
subkey <= std_logic_vector(sum_s + k(to_integer(sum_s and x"00000003")));
else
subkey <= std_logic_vector(sum_s + k(to_integer(("00000000000" & sum_s(31 downto 11)) and x"00000003")));
end if;
end if;
end if;
end if;
end process;
end Behavioral;
 
 
 
/rtl/round_f.vhd
0,0 → 1,43
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity round_f is
port(v_in : in std_logic_vector(31 downto 0);
last_val : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(31 downto 0));
end round_f;
 
architecture Behavioral of round_f is
 
signal op_1_s : std_logic_vector(31 downto 0);
signal op_2_s : std_logic_vector(31 downto 0);
signal op_3_s : std_logic_vector(31 downto 0);
signal op_4_s : std_logic_vector(31 downto 0);
 
begin
 
op_1_s <= (v_in(27 downto 0) & "0000");
op_2_s <= "00000"& v_in(31 downto 5);
op_3_s <= op_1_s xor op_2_s;
op_4_s <= std_logic_vector(unsigned(op_3_s ) + unsigned(v_in));
v_out <= op_4_s xor last_val;
 
end Behavioral;
 
/tb/tb_xtea.vhd
0,0 → 1,124
 
-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_xtea IS
END tb_xtea;
ARCHITECTURE behavior OF tb_xtea IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT xtea
PORT(
clk : IN std_logic;
rst : IN std_logic;
enc : in std_logic;
block_in : IN std_logic_vector(63 downto 0);
key : IN std_logic_vector(127 downto 0);
v_0_out : out std_logic_vector(31 downto 0);
v_1_out : out std_logic_vector(31 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enc : std_logic := '0';
signal block_in : std_logic_vector(63 downto 0) := (others => '0');
signal key : std_logic_vector(127 downto 0) := (others => '0');
 
--Outputs
signal v_0_out : std_logic_vector(31 downto 0);
signal v_1_out : std_logic_vector(31 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: xtea PORT MAP (
clk => clk,
rst => rst,
enc => enc,
block_in => block_in,
key => key,
v_0_out => v_0_out,
v_1_out => v_1_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
enc <= '0';
rst <= '1';
block_in <= X"bbbbbbbb" & X"aaaaaaaa" ;
key <= X"44444444" & X"33333333" & X"22222222" & X"11111111";
 
wait for clk_period;
rst <= '0';
 
wait for 4*64*clk_period;
 
assert v_0_out = X"3a53039a"
report "ENCRYPT ERROR (v_0)" severity FAILURE;
wait for clk_period;
 
assert v_1_out = X"fe2d9913"
report "ENCRYPT ERROR (v_1)" severity FAILURE;
 
wait for clk_period*10;
enc <= '1';
rst <= '1';
block_in <= X"fe2d9913" & X"3a53039a" ;
key <= X"44444444" & X"33333333" & X"22222222" & X"11111111";
 
wait for clk_period;
rst <= '0';
 
wait for 4*64*clk_period;
 
assert v_0_out = X"bbbbbbbb"
report "DECRYPT ERROR (v_0)" severity FAILURE;
wait for clk_period;
 
assert v_1_out = X"aaaaaaaa"
report "DECRYPT ERROR (v_1)" severity FAILURE;
 
wait;
end process;
 
END;

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