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https://opencores.org/ocsvn/y80e/y80e/trunk
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/trunk/asm/Tasm80.tab
0,0 → 1,833
"TASM Z80 Assembler. " |
/**************************************************************************** |
/* $Id: Tasm80.tab 5931 2012-03-26 12:25:57Z bsa $ |
/**************************************************************************** |
/* This is the instruction set definition table |
/* for the Z80 version of TASM. |
/* Thomas N. Anderson, Speech Technology Incorporated |
/* This table authored and submitted by Carl A. Wall, VE3APY. |
/* |
/* Class bits assigned as follows: |
/* Bit-0 = Z80 (base instruction set) |
/* Bit-1 = HD64180 (extended instructions) |
/* Bit-2 = eZ80 (short address instructions only) |
/* See TASM manual for info on table structure. |
/* |
/*INSTR ARGS OP BYTES RULE CLASS SHIFT OR */ |
/*-------------------------------------------*/ |
|
ADC A,(HL) 8E 1 NOP 1 |
ADC A,(IX*) 8EDD 3 ZIX 1 |
ADC A,(IY*) 8EFD 3 ZIX 1 |
ADC A,A 8F 1 NOP 1 |
ADC A,B 88 1 NOP 1 |
ADC A,C 89 1 NOP 1 |
ADC A,D 8A 1 NOP 1 |
ADC A,E 8B 1 NOP 1 |
ADC A,H 8C 1 NOP 1 |
ADC A,L 8D 1 NOP 1 |
ADC A,XH 8CDD 2 NOP 1 |
ADC A,XL 8DDD 2 NOP 1 |
ADC A,YH 8CFD 2 NOP 1 |
ADC A,YL 8DFD 2 NOP 1 |
ADC A,* CE 2 NOP 1 |
ADC HL,BC 4AED 2 NOP 1 |
ADC HL,DE 5AED 2 NOP 1 |
ADC HL,HL 6AED 2 NOP 1 |
ADC HL,SP 7AED 2 NOP 1 |
|
ADD A,(HL) 86 1 NOP 1 |
ADD A,(IX*) 86DD 3 ZIX 1 |
ADD A,(IY*) 86FD 3 ZIX 1 |
ADD A,A 87 1 NOP 1 |
ADD A,B 80 1 NOP 1 |
ADD A,C 81 1 NOP 1 |
ADD A,D 82 1 NOP 1 |
ADD A,E 83 1 NOP 1 |
ADD A,H 84 1 NOP 1 |
ADD A,L 85 1 NOP 1 |
ADD A,XH 84DD 2 NOP 1 |
ADD A,XL 85DD 2 NOP 1 |
ADD A,YH 84FD 2 NOP 1 |
ADD A,YL 85FD 2 NOP 1 |
ADD A,* C6 2 NOP 1 |
ADD HL,BC 09 1 NOP 1 |
ADD HL,DE 19 1 NOP 1 |
ADD HL,HL 29 1 NOP 1 |
ADD HL,SP 39 1 NOP 1 |
ADD IX,BC 09DD 2 NOP 1 |
ADD IX,DE 19DD 2 NOP 1 |
ADD IX,IX 29DD 2 NOP 1 |
ADD IX,SP 39DD 2 NOP 1 |
ADD IY,BC 09FD 2 NOP 1 |
ADD IY,DE 19FD 2 NOP 1 |
ADD IY,IY 29FD 2 NOP 1 |
ADD IY,SP 39FD 2 NOP 1 |
|
AND (HL) A6 1 NOP 1 |
AND (IX*) A6DD 3 ZIX 1 |
AND (IY*) A6FD 3 ZIX 1 |
AND A A7 1 NOP 1 |
AND B A0 1 NOP 1 |
AND C A1 1 NOP 1 |
AND D A2 1 NOP 1 |
AND E A3 1 NOP 1 |
AND H A4 1 NOP 1 |
AND L A5 1 NOP 1 |
AND XH A4DD 2 NOP 1 |
AND XL A5DD 2 NOP 1 |
AND YH A4FD 2 NOP 1 |
AND YL A5FD 2 NOP 1 |
AND * E6 2 NOP 1 |
|
BIT *,(HL) 46CB 2 ZBIT 1 |
BIT *,(IX*) CBDD 4 ZBIT 1 0 4600 |
BIT *,(IY*) CBFD 4 ZBIT 1 0 4600 |
BIT *,A 47CB 2 ZBIT 1 |
BIT *,B 40CB 2 ZBIT 1 |
BIT *,C 41CB 2 ZBIT 1 |
BIT *,D 42CB 2 ZBIT 1 |
BIT *,E 43CB 2 ZBIT 1 |
BIT *,H 44CB 2 ZBIT 1 |
BIT *,L 45CB 2 ZBIT 1 |
|
CALL C,* DC 3 NOP 1 |
CALL M,* FC 3 NOP 1 |
CALL NC,* D4 3 NOP 1 |
CALL NZ,* C4 3 NOP 1 |
CALL P,* F4 3 NOP 1 |
CALL PE,* EC 3 NOP 1 |
CALL PO,* E4 3 NOP 1 |
CALL Z,* CC 3 NOP 1 |
CALL * CD 3 NOP 1 |
|
CCF "" 3F 1 NOP 1 |
|
CP (HL) BE 1 NOP 1 |
CP (IX*) BEDD 3 ZIX 1 |
CP (IY*) BEFD 3 ZIX 1 |
CP A BF 1 NOP 1 |
CP B B8 1 NOP 1 |
CP C B9 1 NOP 1 |
CP D BA 1 NOP 1 |
CP E BB 1 NOP 1 |
CP H BC 1 NOP 1 |
CP L BD 1 NOP 1 |
CP XH BCDD 2 NOP 1 |
CP XL BDDD 2 NOP 1 |
CP YH BCFD 2 NOP 1 |
CP YL BDFD 2 NOP 1 |
CP * FE 2 NOP 1 |
CPD "" A9ED 2 NOP 1 |
CPDR "" B9ED 2 NOP 1 |
CPIR "" B1ED 2 NOP 1 |
CPI "" A1ED 2 NOP 1 |
CPL "" 2F 1 NOP 1 |
|
DAA "" 27 1 NOP 1 |
|
DEC (HL) 35 1 NOP 1 |
DEC (IX*) 35DD 3 ZIX 1 |
DEC (IY*) 35FD 3 ZIX 1 |
DEC A 3D 1 NOP 1 |
DEC B 05 1 NOP 1 |
DEC BC 0B 1 NOP 1 |
DEC C 0D 1 NOP 1 |
DEC D 15 1 NOP 1 |
DEC DE 1B 1 NOP 1 |
DEC E 1D 1 NOP 1 |
DEC H 25 1 NOP 1 |
DEC HL 2B 1 NOP 1 |
DEC IX 2BDD 2 NOP 1 |
DEC IY 2BFD 2 NOP 1 |
DEC L 2D 1 NOP 1 |
DEC SP 3B 1 NOP 1 |
DEC XH 25DD 2 NOP 1 |
DEC XL 2DDD 2 NOP 1 |
DEC YH 25FD 2 NOP 1 |
DEC YL 2DFD 2 NOP 1 |
|
DI "" F3 1 NOP 1 |
DJNZ * 10 2 R1 1 |
|
EI "" FB 1 NOP 1 |
EX (SP),HL E3 1 NOP 1 |
EX (SP),IX E3DD 2 NOP 1 |
EX (SP),IY E3FD 2 NOP 1 |
EX AF,AF' 08 1 NOP 1 |
EX DE,HL EB 1 NOP 1 |
EXX "" D9 1 NOP 1 |
HALT "" 76 1 NOP 1 |
|
IM 0 46ED 2 NOP 1 |
IM 1 56ED 2 NOP 1 |
IM 2 5EED 2 NOP 1 |
|
IN A,(C) 78ED 2 NOP 1 |
IN B,(C) 40ED 2 NOP 1 |
IN C,(C) 48ED 2 NOP 1 |
IN D,(C) 50ED 2 NOP 1 |
IN E,(C) 58ED 2 NOP 1 |
IN H,(C) 60ED 2 NOP 1 |
IN L,(C) 68ED 2 NOP 1 |
|
IN A,(*) DB 2 NOP 1 |
|
IN0 A,(*) 38ED 3 NOP 2 |
IN0 B,(*) 00ED 3 NOP 2 |
IN0 C,(*) 08ED 3 NOP 2 |
IN0 D,(*) 10ED 3 NOP 2 |
IN0 E,(*) 18ED 3 NOP 2 |
IN0 H,(*) 20ED 3 NOP 2 |
IN0 L,(*) 28ED 3 NOP 2 |
|
INC (HL) 34 1 NOP 1 |
INC (IX*) 34DD 3 ZIX 1 |
INC (IY*) 34FD 3 ZIX 1 |
INC A 3C 1 NOP 1 |
INC B 04 1 NOP 1 |
INC BC 03 1 NOP 1 |
INC C 0C 1 NOP 1 |
INC D 14 1 NOP 1 |
INC DE 13 1 NOP 1 |
INC E 1C 1 NOP 1 |
INC H 24 1 NOP 1 |
INC HL 23 1 NOP 1 |
INC IX 23DD 2 NOP 1 |
INC IY 23FD 2 NOP 1 |
INC L 2C 1 NOP 1 |
INC SP 33 1 NOP 1 |
INC XH 24DD 2 NOP 1 |
INC XL 2CDD 2 NOP 1 |
INC YH 24FD 2 NOP 1 |
INC YL 2CFD 2 NOP 1 |
|
|
IND "" AAED 2 NOP 1 |
IND2 "" 8CED 2 NOP 4 |
IND2R "" 9CED 2 NOP 4 |
INDM "" 8AED 2 NOP 4 |
INDMR "" 9AED 2 NOP 4 |
INDR "" BAED 2 NOP 1 |
INDRX "" CAED 2 NOP 4 |
INI "" A2ED 2 NOP 1 |
INI2 "" 84ED 2 NOP 4 |
INI2R "" 94ED 2 NOP 4 |
INIM "" 82ED 2 NOP 4 |
INIMR "" 92ED 2 NOP 4 |
INIR "" B2ED 2 NOP 1 |
INIRX "" C2ED 2 NOP 4 |
|
JP (HL) E9 1 NOP 1 |
JP (IX) E9DD 2 NOP 1 |
JP (IY) E9FD 2 NOP 1 |
JP C,* DA 3 NOP 1 |
JP M,* FA 3 NOP 1 |
JP NC,* D2 3 NOP 1 |
JP NZ,* C2 3 NOP 1 |
JP P,* F2 3 NOP 1 |
JP PE,* EA 3 NOP 1 |
JP PO,* E2 3 NOP 1 |
JP Z,* CA 3 NOP 1 |
JP * C3 3 NOP 1 |
|
JR C,* 38 2 R1 1 |
JR NC,* 30 2 R1 1 |
JR NZ,* 20 2 R1 1 |
JR Z,* 28 2 R1 1 |
JR * 18 2 R1 1 |
|
LD (BC),A 02 1 NOP 1 |
LD (DE),A 12 1 NOP 1 |
LD (HL),A 77 1 NOP 1 |
LD (HL),B 70 1 NOP 1 |
LD (HL),BC 0FED 2 NOP 4 |
LD (HL),C 71 1 NOP 1 |
LD (HL),D 72 1 NOP 1 |
LD (HL),DE 1FED 2 NOP 4 |
LD (HL),E 73 1 NOP 1 |
LD (HL),H 74 1 NOP 1 |
LD (HL),HL 2FED 2 NOP 4 |
LD (HL),IX 3FED 2 NOP 4 |
LD (HL),IY 3EED 2 NOP 4 |
LD (HL),L 75 1 NOP 1 |
LD (HL),* 36 2 NOP 1 |
LD (IX*),A 77DD 3 ZIX 1 |
LD (IX*),B 70DD 3 ZIX 1 |
LD (IX*),BC 0FDD 3 ZIX 4 |
LD (IX*),C 71DD 3 ZIX 1 |
LD (IX*),D 72DD 3 ZIX 1 |
LD (IX*),DE 1FDD 3 ZIX 4 |
LD (IX*),E 73DD 3 ZIX 1 |
LD (IX*),H 74DD 3 ZIX 1 |
LD (IX*),HL 2FDD 3 ZIX 4 |
LD (IX*),IX 3FDD 3 ZIX 4 |
LD (IX*),IY 3EDD 3 ZIX 4 |
LD (IX*),L 75DD 3 ZIX 1 |
LD (IX*),* 36DD 4 ZIX 1 |
LD (IY*),A 77FD 3 ZIX 1 |
LD (IY*),B 70FD 3 ZIX 1 |
LD (IY*),BC 0FFD 3 ZIX 4 |
LD (IY*),C 71FD 3 ZIX 1 |
LD (IY*),D 72FD 3 ZIX 1 |
LD (IY*),DE 1FFD 3 ZIX 4 |
LD (IY*),E 73FD 3 ZIX 1 |
LD (IY*),H 74FD 3 ZIX 1 |
LD (IY*),HL 2FFD 3 ZIX 4 |
LD (IY*),IX 3FFD 3 ZIX 4 |
LD (IY*),IY 3EFD 3 ZIX 4 |
LD (IY*),L 75FD 3 ZIX 1 |
LD (IY*),* 36FD 4 ZIX 1 |
LD (*),A 32 3 NOP 1 |
LD (*),BC 43ED 4 NOP 1 |
LD (*),DE 53ED 4 NOP 1 |
LD (*),HL 22 3 NOP 1 |
LD (*),IX 22DD 4 NOP 1 |
LD (*),IY 22FD 4 NOP 1 |
LD (*),SP 73ED 4 NOP 1 |
LD A,(BC) 0A 1 NOP 1 |
LD A,(DE) 1A 1 NOP 1 |
LD A,(HL) 7E 1 NOP 1 |
LD A,(IX*) 7EDD 3 ZIX 1 |
LD A,(IY*) 7EFD 3 ZIX 1 |
LD A,A 7F 1 NOP 1 |
LD A,B 78 1 NOP 1 |
LD A,C 79 1 NOP 1 |
LD A,D 7A 1 NOP 1 |
LD A,E 7B 1 NOP 1 |
LD A,H 7C 1 NOP 1 |
LD A,I 57ED 2 NOP 1 |
LD A,L 7D 1 NOP 1 |
LD A,R 5FED 2 NOP 1 |
LD A,XH 7CDD 2 NOP 1 |
LD A,XL 7DDD 2 NOP 1 |
LD A,YH 7CFD 2 NOP 1 |
LD A,YL 7DFD 2 NOP 1 |
LD A,(*) 3A 3 NOP 1 |
LD A,* 3E 2 NOP 1 |
LD B,(HL) 46 1 NOP 1 |
LD B,(IX*) 46DD 3 ZIX 1 |
LD B,(IY*) 46FD 3 ZIX 1 |
LD B,A 47 1 NOP 1 |
LD B,B 40 1 NOP 1 |
LD B,C 41 1 NOP 1 |
LD B,D 42 1 NOP 1 |
LD B,E 43 1 NOP 1 |
LD B,H 44 1 NOP 1 |
LD B,L 45 1 NOP 1 |
LD B,XH 44DD 2 NOP 1 |
LD B,XL 45DD 2 NOP 1 |
LD B,YH 44FD 2 NOP 1 |
LD B,YL 45FD 2 NOP 1 |
LD B,* 06 2 NOP 1 |
LD BC,(HL) 07ED 2 NOP 4 |
LD BC,(IX*) 07DD 3 ZIX 4 |
LD BC,(IY*) 07FD 3 ZIX 4 |
LD BC,(*) 4BED 4 NOP 1 |
LD BC,* 01 3 NOP 1 |
LD C,(HL) 4E 1 NOP 1 |
LD C,(IX*) 4EDD 3 ZIX 1 |
LD C,(IY*) 4EFD 3 ZIX 1 |
LD C,A 4F 1 NOP 1 |
LD C,B 48 1 NOP 1 |
LD C,C 49 1 NOP 1 |
LD C,D 4A 1 NOP 1 |
LD C,E 4B 1 NOP 1 |
LD C,H 4C 1 NOP 1 |
LD C,L 4D 1 NOP 1 |
LD C,XH 4CDD 2 NOP 1 |
LD C,XL 4DDD 2 NOP 1 |
LD C,YH 4CFD 2 NOP 1 |
LD C,YL 4DFD 2 NOP 1 |
LD C,* 0E 2 NOP 1 |
LD D,(HL) 56 1 NOP 1 |
LD D,(IX*) 56DD 3 ZIX 1 |
LD D,(IY*) 56FD 3 ZIX 1 |
LD D,A 57 1 NOP 1 |
LD D,B 50 1 NOP 1 |
LD D,C 51 1 NOP 1 |
LD D,D 52 1 NOP 1 |
LD D,E 53 1 NOP 1 |
LD D,H 54 1 NOP 1 |
LD D,L 55 1 NOP 1 |
LD D,XH 54DD 2 NOP 1 |
LD D,XL 55DD 2 NOP 1 |
LD D,YH 54FD 2 NOP 1 |
LD D,YL 55FD 2 NOP 1 |
LD D,* 16 2 NOP 1 |
LD DE,(HL) 17ED 2 NOP 4 |
LD DE,(IX*) 17DD 3 ZIX 4 |
LD DE,(IY*) 17FD 3 ZIX 4 |
LD DE,(*) 5BED 4 NOP 1 |
LD DE,* 11 3 NOP 1 |
LD E,(HL) 5E 1 NOP 1 |
LD E,(IX*) 5EDD 3 ZIX 1 |
LD E,(IY*) 5EFD 3 ZIX 1 |
LD E,A 5F 1 NOP 1 |
LD E,B 58 1 NOP 1 |
LD E,C 59 1 NOP 1 |
LD E,D 5A 1 NOP 1 |
LD E,E 5B 1 NOP 1 |
LD E,H 5C 1 NOP 1 |
LD E,L 5D 1 NOP 1 |
LD E,XH 5CDD 2 NOP 1 |
LD E,XL 5DDD 2 NOP 1 |
LD E,YH 5CFD 2 NOP 1 |
LD E,YL 5DFD 2 NOP 1 |
LD E,* 1E 2 NOP 1 |
LD HL,(HL) 27ED 2 NOP 4 |
LD HL,(IX*) 27DD 3 ZIX 4 |
LD HL,(IY*) 27FD 3 ZIX 4 |
LD H,(HL) 66 1 NOP 1 |
LD H,(IX*) 66DD 3 ZIX 1 |
LD H,(IY*) 66FD 3 ZIX 1 |
LD H,A 67 1 NOP 1 |
LD H,B 60 1 NOP 1 |
LD H,C 61 1 NOP 1 |
LD H,D 62 1 NOP 1 |
LD H,E 63 1 NOP 1 |
LD H,H 64 1 NOP 1 |
LD H,L 65 1 NOP 1 |
LD H,* 26 2 NOP 1 |
LD HL,(*) 2A 3 NOP 1 |
LD HL,* 21 3 NOP 1 |
LD I,A 47ED 2 NOP 1 |
LD IX,(HL) 37ED 2 NOP 4 |
LD IX,(IX*) 37DD 3 ZIX 4 |
LD IX,(IY*) 37FD 3 ZIX 4 |
LD IX,(*) 2ADD 4 NOP 1 |
LD IX,* 21DD 4 NOP 1 |
LD IY,(HL) 36ED 2 NOP 4 |
LD IY,(IX*) 31DD 3 ZIX 4 |
LD IY,(IY*) 31FD 3 ZIX 4 |
LD IY,(*) 2AFD 4 NOP 1 |
LD IY,* 21FD 4 NOP 1 |
LD L,(HL) 6E 1 NOP 1 |
LD L,(IX*) 6EDD 3 ZIX 1 |
LD L,(IY*) 6EFD 3 ZIX 1 |
LD L,A 6F 1 NOP 1 |
LD L,B 68 1 NOP 1 |
LD L,C 69 1 NOP 1 |
LD L,D 6A 1 NOP 1 |
LD L,E 6B 1 NOP 1 |
LD L,H 6C 1 NOP 1 |
LD L,L 6D 1 NOP 1 |
LD L,* 2E 2 NOP 1 |
LD R,A 4FED 2 NOP 1 |
LD SP,(*) 7BED 4 NOP 1 |
LD SP,HL F9 1 NOP 1 |
LD SP,IX F9DD 2 NOP 1 |
LD SP,IY F9FD 2 NOP 1 |
LD SP,* 31 3 NOP 1 |
LD XH,A 67DD 2 NOP 1 |
LD XH,B 60DD 2 NOP 1 |
LD XH,C 61DD 2 NOP 1 |
LD XH,D 62DD 2 NOP 1 |
LD XH,E 63DD 2 NOP 1 |
LD XH,XH 64DD 2 NOP 1 |
LD XH,XL 65DD 2 NOP 1 |
LD XH,* 26DD 3 NOP 1 |
LD XL,A 6FDD 2 NOP 1 |
LD XL,B 68DD 2 NOP 1 |
LD XL,C 69DD 2 NOP 1 |
LD XL,D 6ADD 2 NOP 1 |
LD XL,E 6BDD 2 NOP 1 |
LD XL,XH 6CDD 2 NOP 1 |
LD XL,XL 6DDD 2 NOP 1 |
LD XL,* 2EDD 3 NOP 1 |
LD YH,A 67FD 2 NOP 1 |
LD YH,B 60FD 2 NOP 1 |
LD YH,C 61FD 2 NOP 1 |
LD YH,D 62FD 2 NOP 1 |
LD YH,E 63FD 2 NOP 1 |
LD YH,YH 64FD 2 NOP 1 |
LD YH,YL 65FD 2 NOP 1 |
LD YH,* 26FD 3 NOP 1 |
LD YL,A 6FFD 2 NOP 1 |
LD YL,B 68FD 2 NOP 1 |
LD YL,C 69FD 2 NOP 1 |
LD YL,D 6AFD 2 NOP 1 |
LD YL,E 6BFD 2 NOP 1 |
LD YL,YH 6CFD 2 NOP 1 |
LD YL,YL 6DFD 2 NOP 1 |
LD YL,* 2EFD 3 NOP 1 |
|
LDD "" A8ED 2 NOP 1 |
LDDR "" B8ED 2 NOP 1 |
LDI "" A0ED 2 NOP 1 |
LDIR "" B0ED 2 NOP 1 |
|
LEA BC,IX* 02ED 3 ZIX 4 |
LEA BC,IY* 03ED 3 ZIX 4 |
LEA DE,IX* 12ED 3 ZIX 4 |
LEA DE,IY* 13ED 3 ZIX 4 |
LEA HL,IX* 22ED 3 ZIX 4 |
LEA HL,IY* 23ED 3 ZIX 4 |
LEA IX,IX* 32ED 3 ZIX 4 |
LEA IX,IY* 54ED 3 ZIX 4 |
LEA IY,IX* 55ED 3 ZIX 4 |
LEA IY,IY* 33ED 3 ZIX 4 |
|
NEG "" 44ED 2 NOP 1 |
NOP "" 00 1 NOP 1 |
|
MLT BC 4CED 2 NOP 2 |
MLT DE 5CED 2 NOP 2 |
MLT HL 6CED 2 NOP 2 |
MLT SP 7CED 2 NOP 2 |
|
OR (HL) B6 1 NOP 1 |
OR (IX*) B6DD 3 ZIX 1 |
OR (IY*) B6FD 3 ZIX 1 |
OR A B7 1 NOP 1 |
OR B B0 1 NOP 1 |
OR C B1 1 NOP 1 |
OR D B2 1 NOP 1 |
OR E B3 1 NOP 1 |
OR H B4 1 NOP 1 |
OR L B5 1 NOP 1 |
OR XH B4DD 2 NOP 1 |
OR XL B5DD 2 NOP 1 |
OR YH B4FD 2 NOP 1 |
OR YL B5FD 2 NOP 1 |
OR * F6 2 NOP 1 |
|
OTD2 "" ACED 2 NOP 4 |
OTD2R "" BCED 2 NOP 4 |
OTDM "" 8BED 2 NOP 2 |
OTDMR "" 9BED 2 NOP 2 |
OTDR "" BBED 2 NOP 1 |
OTDRX "" CBED 2 NOP 4 |
OTI2 "" A4ED 2 NOP 4 |
OTI2R "" B4ED 2 NOP 4 |
OTIM "" 83ED 2 NOP 2 |
OTIMR "" 93ED 2 NOP 2 |
OTIR "" B3ED 2 NOP 1 |
OTIRX "" C3ED 2 NOP 4 |
|
OUT (C),A 79ED 2 NOP 1 |
OUT (C),B 41ED 2 NOP 1 |
OUT (C),C 49ED 2 NOP 1 |
OUT (C),D 51ED 2 NOP 1 |
OUT (C),E 59ED 2 NOP 1 |
OUT (C),H 61ED 2 NOP 1 |
OUT (C),L 69ED 2 NOP 1 |
OUT (*),A D3 2 NOP 1 |
|
OUT0 (*),A 39ED 3 NOP 2 |
OUT0 (*),B 01ED 3 NOP 2 |
OUT0 (*),C 09ED 3 NOP 2 |
OUT0 (*),D 11ED 3 NOP 2 |
OUT0 (*),E 19ED 3 NOP 2 |
OUT0 (*),H 21ED 3 NOP 2 |
OUT0 (*),L 29ED 3 NOP 2 |
|
OUTD "" ABED 2 NOP 1 |
OUTI "" A3ED 2 NOP 1 |
|
PEA IX* 65ED 3 ZIX 4 |
PEA IY* 66ED 3 ZIX 4 |
|
POP AF F1 1 NOP 1 |
POP BC C1 1 NOP 1 |
POP DE D1 1 NOP 1 |
POP HL E1 1 NOP 1 |
POP IX E1DD 2 NOP 1 |
POP IY E1FD 2 NOP 1 |
|
PUSH AF F5 1 NOP 1 |
PUSH BC C5 1 NOP 1 |
PUSH DE D5 1 NOP 1 |
PUSH HL E5 1 NOP 1 |
PUSH IX E5DD 2 NOP 1 |
PUSH IY E5FD 2 NOP 1 |
|
RES *,(HL) 86CB 2 ZBIT 1 |
RES *,(IX*) CBDD 4 ZBIT 1 0 8600 |
/*RES *,(IX*),A CBDD 4 ZBIT 1 0 8700 |
/*RES *,(IX*),B CBDD 4 ZBIT 1 0 8000 |
/*RES *,(IX*),C CBDD 4 ZBIT 1 0 8100 |
/*RES *,(IX*),D CBDD 4 ZBIT 1 0 8200 |
/*RES *,(IX*),E CBDD 4 ZBIT 1 0 8300 |
/*RES *,(IX*),H CBDD 4 ZBIT 1 0 8400 |
/*RES *,(IX*),L CBDD 4 ZBIT 1 0 8500 |
RES *,(IY*) CBFD 4 ZBIT 1 0 8600 |
/*RES *,(IY*),A CBFD 4 ZBIT 1 0 8700 |
/*RES *,(IY*),B CBFD 4 ZBIT 1 0 8000 |
/*RES *,(IY*),C CBFD 4 ZBIT 1 0 8100 |
/*RES *,(IY*),D CBFD 4 ZBIT 1 0 8200 |
/*RES *,(IY*),E CBFD 4 ZBIT 1 0 8300 |
/*RES *,(IY*),H CBFD 4 ZBIT 1 0 8400 |
/*RES *,(IY*),L CBFD 4 ZBIT 1 0 8500 |
RES *,A 87CB 2 ZBIT 1 |
RES *,B 80CB 2 ZBIT 1 |
RES *,C 81CB 2 ZBIT 1 |
RES *,D 82CB 2 ZBIT 1 |
RES *,E 83CB 2 ZBIT 1 |
RES *,H 84CB 2 ZBIT 1 |
RES *,L 85CB 2 ZBIT 1 |
|
RET "" C9 1 NOP 1 |
RET C D8 1 NOP 1 |
RET M F8 1 NOP 1 |
RET NC D0 1 NOP 1 |
RET NZ C0 1 NOP 1 |
RET P F0 1 NOP 1 |
RET PE E8 1 NOP 1 |
RET PO E0 1 NOP 1 |
RET Z C8 1 NOP 1 |
RETI "" 4DED 2 NOP 1 |
RETN "" 45ED 2 NOP 1 |
|
RL (HL) 16CB 2 NOP 1 |
RL (IX*) CBDD 4 ZIX 1 0 1600 |
/*RL (IX*),A CBDD 4 ZIX 1 0 1700 |
/*RL (IX*),B CBDD 4 ZIX 1 0 1000 |
/*RL (IX*),C CBDD 4 ZIX 1 0 1100 |
/*RL (IX*),D CBDD 4 ZIX 1 0 1200 |
/*RL (IX*),E CBDD 4 ZIX 1 0 1300 |
/*RL (IX*),H CBDD 4 ZIX 1 0 1400 |
/*RL (IX*),L CBDD 4 ZIX 1 0 1500 |
RL (IY*) CBFD 4 ZIX 1 0 1600 |
/*RL (IY*),A CBFD 4 ZIX 1 0 1700 |
/*RL (IY*),B CBFD 4 ZIX 1 0 1000 |
/*RL (IY*),C CBFD 4 ZIX 1 0 1100 |
/*RL (IY*),D CBFD 4 ZIX 1 0 1200 |
/*RL (IY*),E CBFD 4 ZIX 1 0 1300 |
/*RL (IY*),H CBFD 4 ZIX 1 0 1400 |
/*RL (IY*),L CBFD 4 ZIX 1 0 1500 |
RL A 17CB 2 NOP 1 |
RL B 10CB 2 NOP 1 |
RL C 11CB 2 NOP 1 |
RL D 12CB 2 NOP 1 |
RL E 13CB 2 NOP 1 |
RL H 14CB 2 NOP 1 |
RL L 15CB 2 NOP 1 |
RLA "" 17 1 NOP 1 |
|
RLC (HL) 06CB 2 NOP 1 |
RLC (IX*) CBDD 4 ZIX 1 0 0600 |
/*RLC (IX*),A CBDD 4 ZIX 1 0 0700 |
/*RLC (IX*),B CBDD 4 ZIX 1 0 0000 |
/*RLC (IX*),C CBDD 4 ZIX 1 0 0100 |
/*RLC (IX*),D CBDD 4 ZIX 1 0 0200 |
/*RLC (IX*),E CBDD 4 ZIX 1 0 0300 |
/*RLC (IX*),H CBDD 4 ZIX 1 0 0400 |
/*RLC (IX*),L CBDD 4 ZIX 1 0 0500 |
RLC (IY*) CBFD 4 ZIX 1 0 0600 |
/*RLC (IY*),A CBFD 4 ZIX 1 0 0700 |
/*RLC (IY*),B CBFD 4 ZIX 1 0 0000 |
/*RLC (IY*),C CBFD 4 ZIX 1 0 0100 |
/*RLC (IY*),D CBFD 4 ZIX 1 0 0200 |
/*RLC (IY*),E CBFD 4 ZIX 1 0 0300 |
/*RLC (IY*),H CBFD 4 ZIX 1 0 0400 |
/*RLC (IY*),L CBFD 4 ZIX 1 0 0500 |
RLC A 07CB 2 NOP 1 |
RLC B 00CB 2 NOP 1 |
RLC C 01CB 2 NOP 1 |
RLC D 02CB 2 NOP 1 |
RLC E 03CB 2 NOP 1 |
RLC H 04CB 2 NOP 1 |
RLC L 05CB 2 NOP 1 |
RLCA "" 07 1 NOP 1 |
|
RLD "" 6FED 2 NOP 1 |
|
RR (HL) 1ECB 2 NOP 1 |
RR (IX*) CBDD 4 ZIX 1 0 1E00 |
/*RR (IX*),A CBDD 4 ZIX 1 0 1F00 |
/*RR (IX*),B CBDD 4 ZIX 1 0 1800 |
/*RR (IX*),C CBDD 4 ZIX 1 0 1900 |
/*RR (IX*),D CBDD 4 ZIX 1 0 1A00 |
/*RR (IX*),E CBDD 4 ZIX 1 0 1B00 |
/*RR (IX*),H CBDD 4 ZIX 1 0 1C00 |
/*RR (IX*),L CBDD 4 ZIX 1 0 1D00 |
RR (IY*) CBFD 4 ZIX 1 0 1E00 |
/*RR (IY*),A CBFD 4 ZIX 1 0 1F00 |
/*RR (IY*),B CBFD 4 ZIX 1 0 1800 |
/*RR (IY*),C CBFD 4 ZIX 1 0 1900 |
/*RR (IY*),D CBFD 4 ZIX 1 0 1A00 |
/*RR (IY*),E CBFD 4 ZIX 1 0 1B00 |
/*RR (IY*),H CBFD 4 ZIX 1 0 1C00 |
/*RR (IY*),L CBFD 4 ZIX 1 0 1D00 |
RR A 1FCB 2 NOP 1 |
RR B 18CB 2 NOP 1 |
RR C 19CB 2 NOP 1 |
RR D 1ACB 2 NOP 1 |
RR E 1BCB 2 NOP 1 |
RR H 1CCB 2 NOP 1 |
RR L 1DCB 2 NOP 1 |
RRA "" 1F 1 NOP 1 |
|
RRC (HL) 0ECB 2 NOP 1 |
RRC (IX*) CBDD 4 ZIX 1 0 0E00 |
/*RRC (IX*),A CBDD 4 ZIX 1 0 0F00 |
/*RRC (IX*),B CBDD 4 ZIX 1 0 0800 |
/*RRC (IX*),C CBDD 4 ZIX 1 0 0900 |
/*RRC (IX*),D CBDD 4 ZIX 1 0 0A00 |
/*RRC (IX*),E CBDD 4 ZIX 1 0 0B00 |
/*RRC (IX*),H CBDD 4 ZIX 1 0 0C00 |
/*RRC (IX*),L CBDD 4 ZIX 1 0 0D00 |
RRC (IY*) CBFD 4 ZIX 1 0 0E00 |
/*RRC (IY*),A CBFD 4 ZIX 1 0 0F00 |
/*RRC (IY*),B CBFD 4 ZIX 1 0 0800 |
/*RRC (IY*),C CBFD 4 ZIX 1 0 0900 |
/*RRC (IY*),D CBFD 4 ZIX 1 0 0A00 |
/*RRC (IY*),E CBFD 4 ZIX 1 0 0B00 |
/*RRC (IY*),H CBFD 4 ZIX 1 0 0C00 |
/*RRC (IY*),L CBFD 4 ZIX 1 0 0D00 |
RRC A 0FCB 2 NOP 1 |
RRC B 08CB 2 NOP 1 |
RRC C 09CB 2 NOP 1 |
RRC D 0ACB 2 NOP 1 |
RRC E 0BCB 2 NOP 1 |
RRC H 0CCB 2 NOP 1 |
RRC L 0DCB 2 NOP 1 |
RRCA "" 0F 1 NOP 1 |
|
RRD "" 67ED 2 NOP 1 |
|
RST 00H C7 1 NOP 1 |
RST 08H CF 1 NOP 1 |
RST 10H D7 1 NOP 1 |
RST 18H DF 1 NOP 1 |
RST 20H E7 1 NOP 1 |
RST 28H EF 1 NOP 1 |
RST 30H F7 1 NOP 1 |
RST 38H FF 1 NOP 1 |
|
SBC A,(HL) 9E 1 NOP 1 |
SBC A,(IX*) 9EDD 3 ZIX 1 |
SBC A,(IY*) 9EFD 3 ZIX 1 |
SBC A,A 9F 1 NOP 1 |
SBC A,B 98 1 NOP 1 |
SBC A,C 99 1 NOP 1 |
SBC A,D 9A 1 NOP 1 |
SBC A,E 9B 1 NOP 1 |
SBC A,H 9C 1 NOP 1 |
SBC A,L 9D 1 NOP 1 |
SBC A,XH 9CDD 2 NOP 1 |
SBC A,XL 9DDD 2 NOP 1 |
SBC A,YH 9CFD 2 NOP 1 |
SBC A,YL 9DFD 2 NOP 1 |
SBC HL,BC 42ED 2 NOP 1 |
SBC HL,DE 52ED 2 NOP 1 |
SBC HL,HL 62ED 2 NOP 1 |
SBC HL,SP 72ED 2 NOP 1 |
SBC A,* DE 2 NOP 1 |
SCF "" 37 1 NOP 1 |
|
SET *,(HL) C6CB 2 ZBIT 1 |
SET *,(IX*) CBDD 4 ZBIT 1 0 C600 |
/*SET *,(IX*),A CBDD 4 ZBIT 1 0 C700 |
/*SET *,(IX*),B CBDD 4 ZBIT 1 0 C000 |
/*SET *,(IX*),C CBDD 4 ZBIT 1 0 C100 |
/*SET *,(IX*),D CBDD 4 ZBIT 1 0 C200 |
/*SET *,(IX*),E CBDD 4 ZBIT 1 0 C300 |
/*SET *,(IX*),H CBDD 4 ZBIT 1 0 C400 |
/*SET *,(IX*),L CBDD 4 ZBIT 1 0 C500 |
SET *,(IY*) CBFD 4 ZBIT 1 0 C600 |
/*SET *,(IY*),A CBFD 4 ZBIT 1 0 C700 |
/*SET *,(IY*),B CBFD 4 ZBIT 1 0 C000 |
/*SET *,(IY*),C CBFD 4 ZBIT 1 0 C100 |
/*SET *,(IY*),D CBFD 4 ZBIT 1 0 C200 |
/*SET *,(IY*),E CBFD 4 ZBIT 1 0 C300 |
/*SET *,(IY*),H CBFD 4 ZBIT 1 0 C400 |
/*SET *,(IY*),L CBFD 4 ZBIT 1 0 C500 |
SET *,A C7CB 2 ZBIT 1 |
SET *,B C0CB 2 ZBIT 1 |
SET *,C C1CB 2 ZBIT 1 |
SET *,D C2CB 2 ZBIT 1 |
SET *,E C3CB 2 ZBIT 1 |
SET *,H C4CB 2 ZBIT 1 |
SET *,L C5CB 2 ZBIT 1 |
|
SLA (HL) 26CB 2 NOP 1 |
SLA (IX*) CBDD 4 ZIX 1 0 2600 |
SLA (IY*) CBFD 4 ZIX 1 0 2600 |
SLA A 27CB 2 NOP 1 |
SLA B 20CB 2 NOP 1 |
SLA C 21CB 2 NOP 1 |
SLA D 22CB 2 NOP 1 |
SLA E 23CB 2 NOP 1 |
SLA H 24CB 2 NOP 1 |
SLA L 25CB 2 NOP 1 |
|
SLI (HL) 36CB 2 NOP 1 |
SLI (IX*) CBDD 4 ZIX 1 0 3600 |
SLI (IY*) CBFD 4 ZIX 1 0 3600 |
SLI A 37CB 2 NOP 1 |
SLI B 30CB 2 NOP 1 |
SLI C 31CB 2 NOP 1 |
SLI D 32CB 2 NOP 1 |
SLI E 33CB 2 NOP 1 |
SLI H 34CB 2 NOP 1 |
SLI L 35CB 2 NOP 1 |
|
SLP "" 76ED 2 NOP 2 |
|
SRA (HL) 2ECB 2 NOP 1 |
SRA (IX*) CBDD 4 ZIX 1 0 2E00 |
SRA (IY*) CBFD 4 ZIX 1 0 2E00 |
SRA A 2FCB 2 NOP 1 |
SRA B 28CB 2 NOP 1 |
SRA C 29CB 2 NOP 1 |
SRA D 2ACB 2 NOP 1 |
SRA E 2BCB 2 NOP 1 |
SRA H 2CCB 2 NOP 1 |
SRA L 2DCB 2 NOP 1 |
|
SRL (HL) 3ECB 2 NOP 1 |
SRL (IX*) CBDD 4 ZIX 1 0 3E00 |
SRL (IY*) CBFD 4 ZIX 1 0 3E00 |
SRL A 3FCB 2 NOP 1 |
SRL B 38CB 2 NOP 1 |
SRL C 39CB 2 NOP 1 |
SRL D 3ACB 2 NOP 1 |
SRL E 3BCB 2 NOP 1 |
SRL H 3CCB 2 NOP 1 |
SRL L 3DCB 2 NOP 1 |
|
SUB (HL) 96 1 NOP 1 |
SUB (IX*) 96DD 3 ZIX 1 |
SUB (IY*) 96FD 3 ZIX 1 |
SUB A 97 1 NOP 1 |
SUB B 90 1 NOP 1 |
SUB C 91 1 NOP 1 |
SUB D 92 1 NOP 1 |
SUB E 93 1 NOP 1 |
SUB H 94 1 NOP 1 |
SUB L 95 1 NOP 1 |
SUB XH 94DD 2 NOP 1 |
SUB XL 95DD 2 NOP 1 |
SUB YH 94FD 2 NOP 1 |
SUB YL 95FD 2 NOP 1 |
SUB * D6 2 NOP 1 |
|
TST A 3CED 2 NOP 2 |
TST B 04ED 2 NOP 2 |
TST C 0CED 2 NOP 2 |
TST D 14ED 2 NOP 2 |
TST E 1CED 2 NOP 2 |
TST H 24ED 2 NOP 2 |
TST L 2CED 2 NOP 2 |
TST (HL) 34ED 2 NOP 2 |
TST * 64ED 3 NOP 2 |
|
TSTIO * 74ED 3 NOP 2 |
|
XOR (HL) AE 1 NOP 1 |
XOR (IX*) AEDD 3 ZIX 1 |
XOR (IY*) AEFD 3 ZIX 1 |
XOR A AF 1 NOP 1 |
XOR B A8 1 NOP 1 |
XOR C A9 1 NOP 1 |
XOR D AA 1 NOP 1 |
XOR E AB 1 NOP 1 |
XOR H AC 1 NOP 1 |
XOR L AD 1 NOP 1 |
XOR XH ACDD 2 NOP 1 |
XOR XL ADDD 2 NOP 1 |
XOR YH ACFD 2 NOP 1 |
XOR YL ADFD 2 NOP 1 |
XOR * EE 2 NOP 1 |
/trunk/asm/dat_mov.s
314,22 → 314,22
push bc ;0305h @ fcf4h |
push de ;0709h @ fcf2h |
push hl ;0b0dh @ fcf0h |
ld (ix+0ffh), a ; 01h @ 6788h |
ld (ix+0feh), b ; 03h @ 6787h |
ld (ix+0fdh), c ; 05h @ 6786h |
ld (ix+0fch), d ; 07h @ 6785h |
ld (ix+0fbh), e ; 09h @ 6784h |
ld (ix+0fah), h ; 0bh @ 6783h |
ld (ix+0f9h), l ; 0dh @ 6782h |
ld (ix+0f8h), 0fh ;0fh @ 6781h |
ld (iy+0ffh), a ; 01h @ abcch |
ld (iy+0feh), b ; 03h @ abcbh |
ld (iy+0fdh), c ; 05h @ abcah |
ld (iy+0fch), d ; 07h @ abc9h |
ld (iy+0fbh), e ; 09h @ abc8h |
ld (iy+0fah), h ; 0bh @ abc7h |
ld (iy+0f9h), l ; 0dh @ abc6h |
ld (iy+0f8h), 0fh ;0fh @ abc5h |
ld (ix-001h), a ; 01h @ 6788h |
ld (ix-002h), b ; 03h @ 6787h |
ld (ix-003h), c ; 05h @ 6786h |
ld (ix-004h), d ; 07h @ 6785h |
ld (ix-005h), e ; 09h @ 6784h |
ld (ix-006h), h ; 0bh @ 6783h |
ld (ix-007h), l ; 0dh @ 6782h |
ld (ix-008h), 0fh ;0fh @ 6781h |
ld (iy-001h), a ; 01h @ abcch |
ld (iy-002h), b ; 03h @ abcbh |
ld (iy-003h), c ; 05h @ abcah |
ld (iy-004h), d ; 07h @ abc9h |
ld (iy-005h), e ; 09h @ abc8h |
ld (iy-006h), h ; 0bh @ abc7h |
ld (iy-007h), l ; 0dh @ abc6h |
ld (iy-008h), 0fh ;0fh @ abc5h |
xor a |
ld b, a |
ld c, a |
378,7 → 378,109
di |
ld a, i |
push af ;5500h @ fcceh |
;------------- |
xor a |
ld sp, 0fc00h |
ld ix, 00000h |
ld iy, 0ffffh |
ld bc, 0aaaah |
ld de, 05555h |
ld hl, 02222h |
ld xh, 0a5h |
push ix ;a500h @ fbfeh |
ld xl, 057h |
push ix ;a557h @ fbfch |
ld yh, 0beh |
push iy ;beffh @ fbfah |
ld yl, 03dh |
push iy ;be3dh @ fbf8h |
push af ;0044h @ fbf6h |
push bc ;aaaah @ fbf4h |
push de ;5555h @ fbf2h |
push hl ;2222h @ fbf0h |
; |
ld a,xh |
push af ;a544h @ fbeeh |
ld a,xl |
push af ;5744h @ fbech |
ld a,yh |
push af ;be44h @ fbeah |
ld a,yl |
push af ;3d44h @ fbe8h |
; |
ld a,05h |
ld xl,a |
ld a,0feh |
ld yh,a |
ld a,0adh |
ld xh,a |
ld a,7eh |
ld yl,a |
push ix ;ad05h @ fbe6h |
push iy ;fe7eh @ fbe4h |
push af ;7e44h @ fbe2h |
; |
ld b,xh |
ld c,xl |
ld xl,b |
ld xh,c |
push bc ;ad05h @ fbe0h |
push ix ;05adh @ fbdeh |
ld b,yh |
ld c,yl |
ld yl,b |
ld yh,c |
push bc ;fe7eh @ fbdch |
push iy ;7efeh @ fbdah |
ld b,xl |
ld c,xh |
ld xh,b |
ld xl,c |
push bc ;ad05h @ fbd8h |
push ix ;ad05h @ fbd6h |
ld b,yl |
ld c,yh |
ld yh,b |
ld yl,c |
push bc ;fe7eh @ fbd4h |
push iy ;fe7eh @ fbd2h |
push af ;7e44h @ fbd0h |
|
ld e,xh |
ld d,xl |
ld xl,e |
ld xh,d |
push de ;05adh @ fbceh |
push ix ;05adh @ fbcch |
ld d,yh |
ld e,yl |
ld yl,d |
ld yh,e |
push de ;fe7eh @ fbcah |
push iy ;7efeh @ fbc8h |
ld e,xl |
ld d,xh |
ld xh,e |
ld xl,d |
push de ;05adh @ fbc6h |
push ix ;ad05h @ fbc4h |
ld d,yl |
ld e,yh |
ld yh,d |
ld yl,e |
push de ;fe7eh @ fbc2h |
push iy ;fe7eh @ fbc0h |
ld a,xl |
ld xl,xh |
ld xh,a |
push ix ;05adh @ fbbeh |
ld a,yl |
ld yl,yh |
ld yh,a |
push iy ;7efeh @ fbbch |
push bc ;fe7eh @ fbbah |
push hl ;2222h @ fbb8h |
;------------- |
ld hl, 0100h ;init hl for next pattern |
jp 0c0h |
|
434,3 → 536,4
dw 06789h |
dw 0abcdh |
|
end |
/trunk/asm/dat_movd.s
35,6 → 35,17
org 0cc30h |
dw 0cc34h, 00f00h, 0ffffh, 0ffffh ;cc30h |
|
org 0fbb8h |
dw 02222h, 0fe7eh, 07efeh, 005adh ;fbb8h |
dw 0fe7eh, 0fe7eh, 0ad05h, 005adh ;fbc0h |
dw 07efeh, 0fe7eh, 005adh, 005adh ;fbc8h |
dw 07e44h, 0fe7eh, 0fe7eh, 0ad05h ;fbd0h |
dw 0ad05h, 07efeh, 0fe7eh, 005adh ;fbd8h |
dw 0ad05h, 07e44h, 0fe7eh, 0ad05h ;fbe0h |
dw 03d44h, 0be44h, 05744h, 0a544h ;fbe8h |
dw 02222h, 05555h, 0aaaah, 00044h ;fbf0h |
dw 0be3dh, 0beffh, 0a557h, 0a500h ;fbf8h |
|
org 0fcc8h |
dw 0ffffh, 0ffffh, 0ffffh, 05500h ;fcc8h |
dw 05504h, 05500h, 00044h, 00000h ;fcd0h |
72,3 → 83,4
dw 00102h, 00f44h, 05555h, 0aaaah ;fff0h |
dw 01020h, 00408h, 00102h, 00044h ;fff8h |
|
end |
/trunk/asm/alu_ops.s
248,9 → 248,9
; 2fh @ 78cbh write |
dec (ix+10h) ; c0h @ 78cch read |
; bfh @ 78cch write |
inc (iy+0feh) ; f0h @ bc9eh read |
inc (iy-02h) ; f0h @ bc9eh read |
; f1h @ bc9eh write |
dec (iy+0ffh) ; 80h @ bc9fh read |
dec (iy-01h) ; 80h @ bc9fh read |
; 7fh @ bc9fh write |
push af ;7f16h @ febch |
push bc ;5256h @ febah |
991,6 → 991,53
push af ;6a44h @ fc02h |
rra |
push af ;3544h @ fc00h |
ld bc, 05867h |
ld de, 09acbh |
ld hl, 021f0h |
ld sp, 0fd48h |
cp a |
ld a, 35h |
sll a |
push af ;6b00h @ fd46h |
sll a |
push af ;d784h @ fd44h |
sll a |
push af ;af85h @ fd42h |
add a,a ;set H flag |
ld a,0afh |
sll a |
push af ;5f05h @ fd40h |
sll a |
push af ;bf80h @ fd3eh |
push bc ;5867h @ fd3ch |
push de ;9acbh @ fd3ah |
push hl ;21f0h @ fd38h |
sll b |
push bc ;b167h @ fd36h |
sll c |
push bc ;b1cfh @ fd34h |
sll d |
push de ;35cbh @ fd32h |
sll e |
push de ;3597h @ fd30h |
sll h |
push hl ;43f0h @ fd2eh |
sll l |
push hl ;43e1h @ fd2ch |
push af ;bf85h @ fd2ah |
cp a |
ld hl, 03011h |
sll (hl) ; c5h @ 3011h read |
; 8bh @ 3011h write |
push af ;bf85h @ fd28h |
cp a |
sll (ix+0fh) ; 66h @ 100fh read |
; cdh @ 100fh write |
push af ;bf80h @ fd26h |
cp a |
sll (iy+0fh) ; f0h @ 200fh read |
; e1h @ 200fh write |
push af ;bf85h @ fd24h |
ld sp, 0fa00h |
pop af ;9900h @ fa00h |
ld sp, 0fb00h |
1068,23 → 1115,212
rrd ; e3h @ 3010h read |
; 2eh @ 3010h write |
push af ;6304h @ fac8h |
|
;-------- |
ld hl,0aaaah |
ld bc,0bcbch |
ld de,0dedeh |
ld sp,0fc00h |
ld ix, 06030h |
ld iy, 0ae07h |
ld a, 0aah |
adc a,xh |
push af ;0a01h @ fbfeh |
ld a, 0aah |
adc a,xl |
push af ;db80h @ fbfch |
ld a, 0aah |
adc a,yh |
push af ;5815h @ fbfah |
ld a, 0aah |
adc a,yl |
push af ;b290h @ fbf8h |
ld a, 0aah |
add a,xh |
push af ;0a01h @ fbf6h |
ld a, 0aah |
add a,xl |
push af ;da80h @ fbf4h |
ld a, 0aah |
add a,yh |
push af ;5815h @ fbf2h |
ld a, 0aah |
add a,yl |
push af ;b190h @ fbf0h |
ld a,0aah |
and xh |
push af ;2010h @ fbeeh |
ld a,0aah |
and xl |
push af ;2010h @ fbech |
ld a,0aah |
and yh |
push af ;aa94h @ fbeah |
ld a,0aah |
and yl |
push af ;0210h @ fbe8h |
ld a,0aah |
ld ix,0101h |
ld iy,0101h |
scf |
dec xh |
push af ;aa43h @ fbe6h |
ccf |
dec xh |
push af ;aa92h @ fbe4h |
dec xl |
push af ;aa42h @ fbe2h |
scf |
dec xl |
push af ;aa93h @ fbe0h |
dec yh |
push af ;aa43h @ fbdeh |
dec yh |
ccf |
push af ;aa90h @ fbdch |
dec yl |
push af ;aa42h @ fbdah |
dec yl |
push af ;aa92h @ fbd8h |
push ix ;ffffh @ fbd6h |
push iy ;ffffh @ fbd4h |
inc xh |
push af ;aa50h @ fbd2h |
inc xl |
push af ;aa50h @ fbd0h |
scf |
inc yh |
push af ;aa51h @ fbceh |
inc yl |
push af ;aa51h @ fbcch |
inc xh |
push af ;aa01h @ fbcah |
ccf |
inc xl |
push af ;aa00h @ fbc8h |
scf |
inc yh |
push af ;aa01h @ fbc6h |
ccf |
inc yl |
push af ;aa00h @ fbc4h |
push ix ;0101h @ fbc2h |
push iy ;0101h @ fbc0h |
ld ix, 06030h |
ld iy, 0ae07h |
ld a,0aah |
or xh |
push af ;ea80h @ fbbeh |
ld a, 0aah |
scf |
or xl |
push af ;ba80h @ fbbch |
scf |
ld a, 0aah |
or yh |
push af ;ae80h @ fbbah |
ld a, 0aah |
or yl |
push af ;af84h @ fbb8h |
ld a, 0aah |
xor xh |
push af ;ca84h @ fbb6h |
ld a, 0aah |
xor xl |
push af ;9a84h @ fbb4h |
ld a, 0aah |
xor yh |
push af ;0400h @ fbb2h |
ld a, 0aah |
xor yl |
push af ;ad80h @ fbb0h |
ld a, 060h |
cp xh |
push af ;6042h @ fbaeh |
cp xl |
push af ;6002h @ fbach |
cp yh |
push af ;6097h @ fbaah |
cp yl |
push af ;6012h @ fba8h |
ld a, 0aah |
sbc a,xh |
push af ;4a06h @ fba6h |
ld a, 0aah |
sbc a,xl |
push af ;7a06h @ fba4h |
ld a, 0aah |
sbc a,yh |
push af ;fc93h @ fba2h |
ld a, 0aah |
sbc a,yl |
push af ;a282h @ fba0h |
ld a, 0aah |
sub xh |
push af ;4a06h @ fb9eh |
ld a, 0aah |
sub xl |
push af ;7a06h @ fb9ch |
ld a, 0aah |
sub yh |
push af ;fc93h @ fb9ah |
ld a, 0aah |
sub yl |
push af ;a382h @ fb98h |
push bc ;bcbch @ fb96h |
push de ;dedeh @ fb94h |
push hl ;aaaah @ fb92h |
push ix ;6030h @ fb90h |
;-------- |
; ld sp,0fb80h |
; ld ix,04000h |
; ld iy,04100h |
; xor a |
; set 0,(ix+0),a ;a0h @ 4000h read |
; ;a1h @ 4000h write |
; push af ;a140h @ fb7eh |
; and a |
; scf |
; set 1,(iy+0),b ;e0h @ 4100h read |
; ;e2h @ 4100h write |
; set 2,(ix+1),c ;b0h @ 4001h read |
; ;b4h @ 4001h write |
; set 3,(iy+1),d ;f0h @ 4101h read |
; ;f8h @ 4101h write |
; set 4,(ix+2),e ;0ch @ 4002h read |
; ;1ch @ 4002h write |
; set 5,(iy+2),h ;03h @ 4102h read |
; ;23h @ 4102h write |
; set 6,(ix+3),l ;0dh @ 4003h read |
; ;4dh @ 4003h write |
; set 7,(iy+3),a ;05h @ 4103h read |
; ;85h @ 4103h write |
; push af ;8501h @ fb7ch |
; push bc ;e2b4h @ fb7ah |
; push de ;f81ch @ fb78h |
; push hl ;234dh @ fb76h |
;-------- |
ld hl, 0100h |
jp 0c0h |
|
org 1000h |
db 0c7h, 0a2h, 080h, 001h, 001h, 001h, 001h, 001h |
db 067h, 067h, 067h, 067h, 067h, 067h, 067h |
db 067h, 067h, 067h, 067h, 067h, 067h, 067h, 066h |
|
org 2000h |
db 082h, 0abh, 078h, 078h, 060h, 060h, 078h, 060h |
db 0f0h, 0f0h, 0f0h, 0f0h, 0f0h, 0f0h, 0f0h |
db 0f0h, 0f0h, 0f0h, 0f0h, 0f0h, 0f0h, 0f0h, 0f0h |
|
org 3000h |
db 03ch, 055h, 055h, 0ffh, 0aah, 0aah, 0ffh, 0aah |
db 0c5h, 0c5h, 0c5h, 0c4h, 0c5h, 0c5h, 0c5h, 02fh |
db 0e3h |
db 0e3h, 0c5h |
|
; org 4000h |
; db 0a0h, 0b0h, 00ch, 00dh |
|
; org 4100h |
; db 0e0h, 0f0h, 003h, 005h |
|
org 078cbh |
db 02eh, 0c0h |
|
1099,4 → 1335,4
dw 09b00h, 0b110h, 02401h, 01f01h |
dw 00111h, 07702h, 08812h, 07303h |
dw 06613h |
|
end |
/trunk/asm/build.bat
Cannot display: file marked as a binary type.
svn:mime-type = application/x-msdos-program
trunk/asm/build.bat
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/x-msdos-program
\ No newline at end of property
Index: trunk/asm/alu_opsd.s
===================================================================
--- trunk/asm/alu_opsd.s (revision 3)
+++ trunk/asm/alu_opsd.s (revision 4)
@@ -4,10 +4,10 @@
;* *
;**********************************************************************************
org 01008h
- db 0ceh, 0b3h, 0cfh, 033h, 0ceh, 033h, 033h
+ db 0ceh, 0b3h, 0cfh, 033h, 0ceh, 033h, 033h, 0cdh
org 02008h
- db 0e1h, 078h, 0e0h, 0f8h, 0e0h, 0f8h, 078h
+ db 0e1h, 078h, 0e0h, 0f8h, 0e0h, 0f8h, 078h, 0e1h
org 02da8h
dw 0ffffh, 0ffffh, 0ffffh, 03872h ;2da8h
@@ -14,7 +14,13 @@
dw 00000h, 00000h, 0ffffh, 0ffffh ;2db0h
org 03008h
- db 08bh, 0e2h, 08bh, 0e2h, 08ah, 0e2h, 062h, 0f7h, 02eh
+ db 08bh, 0e2h, 08bh, 0e2h, 08ah, 0e2h, 062h, 0f7h, 02eh, 08bh
+
+; org 04000h
+; db 0a1h, 0b4h, 01ch, 04dh
+
+; org 04100h
+; db 0e2h, 0f8h, 023h, 085h
org 078cbh
db 02fh, 0bfh
@@ -34,6 +40,26 @@
dw 08591h, 08485h, 01705h, 00111h ;faf0h
dw 00605h, 07804h, 09094h, 09984h ;faf8h
+; org 0fb76h
+; dw 0234dh
+; dw 0f81ch, 0e2b4h, 08501h, 0a140h ;fb78h
+
+ org 0fb90h
+ dw 06030h, 0aaaah, 0dedeh, 0bcbch ;fb90h
+ dw 0a382h, 0fc93h, 07a06h, 04a06h ;fb98h
+ dw 0a282h, 0fc93h, 07a06h, 04a06h ;fba0h
+ dw 06012h, 06097h, 06002h, 06042h ;fba8h
+ dw 0ad80h, 00400h, 09a84h, 0ca84h ;fbb0h
+ dw 0af84h, 0ae80h, 0ba80h, 0ea80h ;fbb8h
+ dw 00101h, 00101h, 0aa00h, 0aa01h ;fbc0h
+ dw 0aa00h, 0aa01h, 0aa51h, 0aa51h ;fbc8h
+ dw 0aa50h, 0aa50h, 0ffffh, 0ffffh ;fbd0h
+ dw 0aa92h, 0aa42h, 0aa90h, 0aa43h ;fbd8h
+ dw 0aa93h, 0aa42h, 0aa92h, 0aa43h ;fbe0h
+ dw 00210h, 0aa94h, 02010h, 02010h ;fbe8h
+ dw 0b190h, 05815h, 0da80h, 00a01h ;fbf0h
+ dw 0b290h, 05815h, 0db80h, 00a01h ;fbf8h
+
org 0fc00h
dw 03544h, 06a44h, 0d444h, 0a845h ;fc00h
dw 05145h, 0a344h, 05145h, 0a845h ;fc08h
@@ -67,6 +93,13 @@
dw 0d484h, 06a04h, 03504h, 06a04h ;fce8h
dw 0d485h, 0a985h, 05304h, 0a684h ;fcf0h
dw 05305h, 0a985h, 0d484h, 06a04h ;fcf8h
+
+ org 0fd24h
+ dw 0bf85h, 0bf80h ;fd24h
+ dw 0bf85h, 0bf85h, 043e1h, 043f0h ;fd28h
+ dw 03597h, 035cbh, 0b1cfh, 0b167h ;fd30h
+ dw 021f0h, 09acbh, 05867h, 0bf80h ;fd38h
+ dw 05f05h, 0af85h, 0d784h, 06b00h ;fd40h
org 0fd48h
dw 0ffffh, 0ffffh, 00042h, 0ff93h ;fd48h
@@ -151,4 +184,4 @@
dw 0ff93h, 00042h, 08057h, 07f57h ;fff0h
dw 00045h, 00045h, 00054h, 00045h ;fff8h
-
+ end
/trunk/rtl/defines.v
171,41 → 171,47
/* write register control: wr_sel - unencoded */ |
/* */ |
/*****************************************************************************************/ |
`define WREG_IDX 14 |
`define WREG_BB 15'b110000000000000 //Select B to write |
`define WREG_BC 15'b111000000000000 //Select BC to write |
`define WREG_CC 15'b101000000000000 //Select C to write |
`define WREG_DD 15'b100100000000000 //Select D to write |
`define WREG_DE 15'b100110000000000 //Select DE to write |
`define WREG_EE 15'b100010000000000 //Select E to write |
`define WREG_HH 15'b100001000000000 //Select H to write |
`define WREG_HL 15'b100001100000000 //Select HL to write |
`define WREG_LL 15'b100000100000000 //Select L to write |
`define WREG_DEHL 15'b100111100000000 //Select DEHL to write (ex case) |
`define WREG_AA 15'b100000010000000 //Select A to write |
`define WREG_AF 15'b100000011000000 //Select A and F to write |
`define WREG_FF 15'b100000001000000 //Select F to write |
`define WREG_SP 15'b100000000100000 //Select SP to write |
`define WREG_TMP 15'b100000000010000 //Select TMP register to write |
`define WREG_IX 15'b100000000001000 //Select IX to write |
`define WREG_IY 15'b100000000000100 //Select IY to write |
`define WREG_II 15'b100000000000010 //Select I register to write |
`define WREG_RR 15'b100000000000001 //Select R register to write |
`define WREG_NUL 15'b000000000000000 //No register write |
`define WREG_IDX 16 |
`define WREG_BB 17'b11000000000000000 //Select B to write |
`define WREG_BC 17'b11100000000000000 //Select BC to write |
`define WREG_CC 17'b10100000000000000 //Select C to write |
`define WREG_DD 17'b10010000000000000 //Select D to write |
`define WREG_DE 17'b10011000000000000 //Select DE to write |
`define WREG_EE 17'b10001000000000000 //Select E to write |
`define WREG_HH 17'b10000100000000000 //Select H to write |
`define WREG_HL 17'b10000110000000000 //Select HL to write |
`define WREG_LL 17'b10000010000000000 //Select L to write |
`define WREG_DEHL 17'b10011110000000000 //Select DEHL to write (ex case) |
`define WREG_AA 17'b10000001000000000 //Select A to write |
`define WREG_AF 17'b10000001100000000 //Select A and F to write |
`define WREG_FF 17'b10000000100000000 //Select F to write |
`define WREG_SP 17'b10000000010000000 //Select SP to write |
`define WREG_TMP 17'b10000000001000000 //Select TMP register to write |
`define WREG_IXH 17'b10000000000100000 //Select IXH to write |
`define WREG_IX 17'b10000000000110000 //Select IX to write |
`define WREG_IXL 17'b10000000000010000 //Select IXL to write |
`define WREG_IYH 17'b10000000000001000 //Select IYH to write |
`define WREG_IY 17'b10000000000001100 //Select IY to write |
`define WREG_IYL 17'b10000000000000100 //Select IYL to write |
`define WREG_II 17'b10000000000000010 //Select I register to write |
`define WREG_RR 17'b10000000000000001 //Select R register to write |
`define WREG_NUL 17'b00000000000000000 //No register write |
|
`define WR_REG 14 //register write |
`define WR_BB 13 //BB register index |
`define WR_CC 12 //CC register index |
`define WR_DD 11 //DD register index |
`define WR_EE 10 //EE register index |
`define WR_HH 9 //HH register index |
`define WR_LL 8 //LL register index |
`define WR_AA 7 //AA register index |
`define WR_FF 6 //FF register index |
`define WR_SP 5 //SP register index |
`define WR_TMP 4 //TMP register index |
`define WR_IX 3 //IX register index |
`define WR_IY 2 //IY register index |
`define WR_REG 16 //register write |
`define WR_BB 15 //BB register index |
`define WR_CC 14 //CC register index |
`define WR_DD 13 //DD register index |
`define WR_EE 12 //EE register index |
`define WR_HH 11 //HH register index |
`define WR_LL 10 //LL register index |
`define WR_AA 9 //AA register index |
`define WR_FF 8 //FF register index |
`define WR_SP 7 //SP register index |
`define WR_TMP 6 //TMP register index |
`define WR_IXH 5 //IXH register index |
`define WR_IXL 4 //IXL register index |
`define WR_IYH 3 //IYH register index |
`define WR_IYL 2 //IYL register index |
`define WR_II 1 //II register index |
`define WR_RR 0 //RR register index |
|
334,6 → 340,7
`define ALUOP_RRC 8'b10001000 //ALU shft: rotate right circular |
`define ALUOP_RRCA 8'b10001001 //ALU shft: rotate right circular acc |
`define ALUOP_SLA 8'b10010000 //ALU shft: shift left arithmetic |
`define ALUOP_SLL 8'b10011000 //ALU shft: shift left logical (x = (x << 1) | 1) |
`define ALUOP_SRL 8'b10100000 //ALU shft: shift right logical |
`define ALUOP_SRA 8'b10101000 //ALU shft: shift right arithmetic |
|
376,6 → 383,7
`define AOP_RRC 6'b001000 //ALU shft: rotate right circular |
`define AOP_RRCA 6'b001001 //ALU shft: rotate right circular acc |
`define AOP_SLA 6'b010000 //ALU shft: shift left arithmetic |
`define AOP_SLL 6'b011000 //ALU shft: shift left logical |
`define AOP_SRL 6'b100000 //ALU shft: shift right logical |
`define AOP_SRA 6'b101000 //ALU shft: shift right arithmetic |
|
/trunk/rtl/control.v
1,15 → 1,14
/*******************************************************************************************/ |
/** **/ |
/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/ |
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/ |
/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/ |
/** **/ |
/** control module Rev 0.0 05/30/2012 **/ |
/** control module Rev 0.0 08/22/2011 **/ |
/** **/ |
/*******************************************************************************************/ |
module control (add_sel, alua_sel, alub_sel, aluop_sel, cflg_en, di_ctl, do_ctl, ex_af_pls, |
ex_bank_pls, ex_dehl_inst, halt_nxt, hflg_ctl, ief_ctl, if_frst, inta_frst, |
imd_ctl, ld_dmaa, ld_inst, ld_inta, ld_page, ld_wait, nflg_ctl, output_inh, |
page_sel, pc_sel, pflg_ctl, rd_frst, rd_nxt, reti_nxt, sflg_en, state_nxt, |
page_sel, pc_sel, pflg_ctl, rd_frst, rd_nxt, reti_nxt, rreg_en, sflg_en, state_nxt, |
tflg_ctl, tran_sel, wr_addr, wr_frst, zflg_en, carry_bit, dmar_reg, inst_reg, |
intr_reg, page_reg, par_bit, sign_bit, state_reg, tflg_reg, vector_int, |
xhlt_reg, zero_bit); |
42,6 → 41,7
output rd_frst; /* read first cycle */ |
output rd_nxt; /* read cycle identifier */ |
output reti_nxt; /* reti identifier */ |
output rreg_en; /* update refresh register */ |
output sflg_en; /* sign flag control */ |
output wr_frst; /* write first cycle */ |
output zflg_en; /* zero flag control */ |
83,7 → 83,10
reg output_inh; /* disable cpu outputs */ |
reg rd_frst; /* first clock of read */ |
reg rd_nxt; /* read trans next */ |
reg reti_nxt; /* reti trans next */ |
reg reti_nxt; /* reti trans next */ |
`ifdef RREG_EMU |
reg rreg_en; /* update refresh register */ |
`endif |
reg sflg_en; /* sign flag control */ |
reg wr_frst; /* first clock of write */ |
reg zflg_en; /* zero flag control */ |
104,6 → 107,37
reg [`TFLG_IDX:0] tflg_ctl; /* temp flag control */ |
reg [`TTYPE_IDX:0] tran_sel; /* transaction type */ |
reg [`WREG_IDX:0] wr_addr; /* register write address bus */ |
|
/*****************************************************************************************/ |
/* */ |
/* refresh register control */ |
/* */ |
/*****************************************************************************************/ |
`ifdef RREG_EMU |
always @ (inst_reg or page_reg or state_reg or dmar_reg) begin |
casex (state_reg) //sysnopsys parallel_case |
`IF1B, |
`IF2B, |
`IF3B: rreg_en = 1'b1; |
`WR1B, |
`WR2B: begin |
casex ({page_reg, inst_reg}) //sysnopsys parallel_case |
12'b1xxx10111001, |
12'b1xxx10110001, |
12'b1xxx10111010, |
12'b1xxx10110010, |
12'b1xxx10111000, |
12'b1xxx10110000, |
12'b1xxx10111011, |
12'b1xxx10110011, |
12'b0001xxxxxxxx: rreg_en = 1'b1; |
default: rreg_en = 1'b0; |
endcase |
end |
default: rreg_en = 1'b0; |
endcase |
end |
`endif |
|
/*****************************************************************************************/ |
/* */ |
432,7 → 466,8
end |
`IF2B: state_nxt = `sDEC2; |
`DEC2: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b001000110110, |
12'b001000000110, |
12'b001000001110, |
12'b001000010110, |
470,7 → 505,56
12'b1xxx10111000, |
12'b1xxx10111001, |
12'b1xxx10111010, |
12'b1xxx10111011: state_nxt = `sADR2; |
12'b1xxx10111011: state_nxt = `sADR2; |
12'b010010001100, |
12'b010010001101, |
12'b010110001100, |
12'b010110001101, |
12'b010010000100, |
12'b010010000101, |
12'b010110000100, |
12'b010110000101, |
12'b010010100100, |
12'b010010100101, |
12'b010110100100, |
12'b010110100101, |
12'b010010111100, |
12'b010010111101, |
12'b010110111100, |
12'b010110111101, |
12'b010000100101, |
12'b010000101101, |
12'b010100100101, |
12'b010100101101, |
12'b010000100100, |
12'b010000101100, |
12'b010100100100, |
12'b010100101100, |
12'b0100011000xx,12'b01000110010x,12'b010001100111, |
12'b0100011010xx,12'b01000110110x,12'b010001101111, |
12'b0101011000xx,12'b01010110010x,12'b010101100111, |
12'b0101011010xx,12'b01010110110x,12'b010101101111, |
12'b0100010xx100,12'b01000110x100,12'b010001111100, |
12'b0100010xx101,12'b01000110x101,12'b010001111101, |
12'b0101010xx100,12'b01010110x100,12'b010101111100, |
12'b0101010xx101,12'b01010110x101,12'b010101111101, |
12'b010010110100, |
12'b010010110101, |
12'b010110110100, |
12'b010110110101, |
12'b010010011100, |
12'b010010011101, |
12'b010110011100, |
12'b010110011101, |
12'b010010010100, |
12'b010010010101, |
12'b010110010100, |
12'b010110010101, |
12'b010010101100, |
12'b010010101101, |
12'b010110101100, |
12'b010110101101, |
12'b001000110xxx, |
12'b001000000xxx, |
12'b001000001xxx, |
12'b001000010xxx, |
531,8 → 615,12
12'b010110100110, |
12'b010110101110, |
12'b010110110110, |
12'b010110111110: state_nxt = `sADR1; |
12'b0000000xx110,12'b00000010x110,12'b000000111110,//12'b000000rrr110, |
12'b010110111110: state_nxt = `sADR1; |
12'b010000100110, |
12'b010000101110, |
12'b010100100110, |
12'b010100101110, |
12'b0000000xx110,12'b00000010x110,12'b000000111110, |
12'b000011000110, |
12'b000011001110, |
12'b000011010110, |
1167,7 → 1255,7
12'b1xxx10111000, |
12'b1xxx10111001, |
12'b1xxx10111010, |
12'b1xxx10111011: add_sel = `ADD_ALU; |
12'b1xxx10111011: add_sel = `ADD_ALU; |
12'b001000000110, |
12'b001000001110, |
12'b001000010110, |
1174,6 → 1262,7
12'b001000011110, |
12'b001000100110, |
12'b001000101110, |
12'b001000110110, |
12'b001000111110, |
12'b001001xxx110, |
12'b001010xxx110, |
1218,24 → 1307,8
12'b010100110100, |
12'b010100110101, |
12'b010111100011, |
12'b011000000110, |
12'b011000001110, |
12'b011000010110, |
12'b011000011110, |
12'b011000100110, |
12'b011000101110, |
12'b011000111110, |
12'b011010xxx110, |
12'b011011xxx110, |
12'b011100000110, |
12'b011100001110, |
12'b011100010110, |
12'b011100011110, |
12'b011100100110, |
12'b011100101110, |
12'b011100111110, |
12'b011110xxx110, |
12'b011111xxx110, |
12'b011x00xxxxxx, |
12'b011x1xxxxxxx, |
12'b1xxx10100000, |
12'b1xxx10100001, |
12'b1xxx10100010, |
1268,6 → 1341,8
12'b001000100xxx, |
12'b001000101110, |
12'b001000101xxx, |
12'b001000110110, |
12'b001000110xxx, |
12'b001000111110, |
12'b001000111xxx, |
12'b001010xxx110, |
1286,7 → 1361,7
12'b1xxx10100011, |
12'b1xxx10101000, |
12'b1xxx10101010, |
12'b1xxx10101011: add_sel = `ADD_PC; |
12'b1xxx10101011: add_sel = `ADD_PC; |
default: add_sel = `ADD_ALU; |
endcase |
end |
1307,7 → 1382,7
12'b1xxx10110011, |
12'b1xxx10111000, |
12'b1xxx10111010, |
12'b1xxx10111011: add_sel = `ADD_ALU; |
12'b1xxx10111011: add_sel = `ADD_ALU; |
default: add_sel = `ADD_PC; |
endcase |
end |
1314,7 → 1389,7
`BLK1: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b1xxx10110001, |
12'b1xxx10111001: add_sel = `ADD_ALU; |
12'b1xxx10111001: add_sel = `ADD_ALU; |
default: add_sel = `ADD_PC; |
endcase |
end |
1410,7 → 1485,11
endcase |
end |
`DEC2: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b010000100110, |
12'b010000101110, |
12'b010100100110, |
12'b010100101110, |
12'b010011001011, //DD+CB prefix |
12'b010111001011, //FD+CB prefix |
12'b010000100001, |
1447,40 → 1526,69
12'b010110110110, |
12'b010110111110, |
12'b010111101001, |
12'b011000000110, |
12'b011000001110, |
12'b011000010110, |
12'b011000011110, |
12'b011000100110, |
12'b011000101110, |
12'b011000111110, |
12'b011001xxx110, |
12'b011010xxx110, |
12'b011011xxx110, |
12'b011100000110, |
12'b011100001110, |
12'b011100010110, |
12'b011100011110, |
12'b011100100110, |
12'b011100101110, |
12'b011100111110, |
12'b011101xxx110, |
12'b011110xxx110, |
12'b011111xxx110, |
12'b1xxx01000101, |
12'b1xxx01001101, |
12'b1xxx01xx0011, |
12'b1xxx01xx1011: pc_sel = `PC_LD; |
12'b0010000000xx,12'b00100000010x,12'b001000000111,//12'b001000000rrr, |
12'b0010000010xx,12'b00100000110x,12'b001000001111,//12'b001000001rrr, |
12'b0010000100xx,12'b00100001010x,12'b001000010111,//12'b001000010rrr, |
12'b0010000110xx,12'b00100001110x,12'b001000011111,//12'b001000011rrr, |
12'b0010001000xx,12'b00100010010x,12'b001000100111,//12'b001000100rrr, |
12'b0010001010xx,12'b00100010110x,12'b001000101111,//12'b001000101rrr, |
12'b0010001110xx,12'b00100011110x,12'b001000111111,//12'b001000111rrr, |
12'b001001xxx0xx,12'b001001xxx10x,12'b001001xxx111,//12'b001001xxxrrr, |
12'b001010xxx0xx,12'b001010xxx10x,12'b001010xxx111,//12'b001010xxxrrr, |
12'b001011xxx0xx,12'b001011xxx10x,12'b001011xxx111,//12'b001011xxxrrr, |
12'b1xxx01xx1011: pc_sel = `PC_LD; |
12'b010010001100, |
12'b010010001101, |
12'b010110001100, |
12'b010110001101, |
12'b010010000100, |
12'b010010000101, |
12'b010110000100, |
12'b010110000101, |
12'b010010100100, |
12'b010010100101, |
12'b010110100100, |
12'b010110100101, |
12'b010010111100, |
12'b010010111101, |
12'b010110111100, |
12'b010110111101, |
12'b010000100101, |
12'b010000101101, |
12'b010100100101, |
12'b010100101101, |
12'b010000100100, |
12'b010000101100, |
12'b010100100100, |
12'b010100101100, |
12'b0100011000xx,12'b01000110010x,12'b010001100111, |
12'b0100011010xx,12'b01000110110x,12'b010001101111, |
12'b0101011000xx,12'b01010110010x,12'b010101100111, |
12'b0101011010xx,12'b01010110110x,12'b010101101111, |
12'b0100010xx100,12'b01000110x100,12'b010001111100, |
12'b0100010xx101,12'b01000110x101,12'b010001111101, |
12'b0101010xx100,12'b01010110x100,12'b010101111100, |
12'b0101010xx101,12'b01010110x101,12'b010101111101, |
12'b010010110100, |
12'b010010110101, |
12'b010110110100, |
12'b010110110101, |
12'b010010011100, |
12'b010010011101, |
12'b010110011100, |
12'b010110011101, |
12'b010010010100, |
12'b010010010101, |
12'b010110010100, |
12'b010110010101, |
12'b010010101100, |
12'b010010101101, |
12'b010110101100, |
12'b010110101101, |
12'b0010000000xx,12'b00100000010x,12'b001000000111, |
12'b0010000010xx,12'b00100000110x,12'b001000001111, |
12'b0010000100xx,12'b00100001010x,12'b001000010111, |
12'b0010000110xx,12'b00100001110x,12'b001000011111, |
12'b0010001000xx,12'b00100010010x,12'b001000100111, |
12'b0010001010xx,12'b00100010110x,12'b001000101111, |
12'b0010001100xx,12'b00100011010x,12'b001000110111, |
12'b0010001110xx,12'b00100011110x,12'b001000111111, |
12'b001001xxx0xx,12'b001001xxx10x,12'b001001xxx111, |
12'b001010xxx0xx,12'b001010xxx10x,12'b001010xxx111, |
12'b001011xxx0xx,12'b001011xxx10x,12'b001011xxx111, |
12'b010000100011, |
12'b010000101011, |
12'b010000xx1001, |
1541,7 → 1649,6
default: pc_sel = `PC_NUL; |
endcase |
end |
// `ADR1: pc_sel = `PC_NUL; |
`RD1B, |
`RD2B: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
1558,7 → 1665,7
end |
`PCA: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b000000010000: pc_sel = (tflg_reg) ? `PC_NUL : `PC_LD; |
12'b000000010000: pc_sel = (tflg_reg) ? `PC_NUL : `PC_LD; |
12'b000000011000, |
12'b0000001xx000, |
12'b000011000011, |
1582,7 → 1689,7
12'b1xxx10111000, |
12'b1xxx10111001, |
12'b1xxx10111010, |
12'b1xxx10111011: pc_sel = `PC_LD; |
12'b1xxx10111011: pc_sel = `PC_LD; |
default: pc_sel = `PC_NUL; |
endcase |
end |
1776,40 → 1883,61
12'b010100100011, |
12'b010100101011, |
12'b010100xx1001, |
12'b010111100101: aluop_sel = `ALUOP_ADD; |
12'b010111100101: aluop_sel = `ALUOP_ADD; |
12'b1xxx01010111, |
12'b1xxx01011111: aluop_sel = `ALUOP_APAS; |
//12'b001001xxx110, |
//12'b001001xxxrrr, |
12'b1xxx01011111: aluop_sel = `ALUOP_APAS; |
12'b010010001100, |
12'b010010001101, |
12'b010110001100, |
12'b010110001101: aluop_sel = `ALUOP_BADC; |
12'b010010000100, |
12'b010010000101, |
12'b010110000100, |
12'b010110000101, |
12'b010000100100, |
12'b010000101100, |
12'b010100100100, |
12'b010100101100: aluop_sel = `ALUOP_BADD; |
12'b010010100100, |
12'b010010100101, |
12'b010110100100, |
12'b010110100101, |
12'b001001xxxxxx, |
//12'b001010xxx110, |
//12'b001010xxxrrr, |
12'b001010xxxxxx: aluop_sel = `ALUOP_BAND; |
//12'b001011xxx110, |
//12'b001011xxxrrr, |
12'b010000100101, |
12'b010000101101, |
12'b010100100101, |
12'b010100101101: aluop_sel = `ALUOP_BDEC; |
12'b010010110100, |
12'b010010110101, |
12'b010110110100, |
12'b010110110101, |
12'b001011xxxxxx: aluop_sel = `ALUOP_BOR; |
12'b010010011100, |
12'b010010011101, |
12'b010110011100, |
12'b010110011101: aluop_sel = `ALUOP_BSBC; |
12'b010010111100, |
12'b010010111101, |
12'b010110111100, |
12'b010110111101, |
12'b010010010100, |
12'b010010010101, |
12'b010110010100, |
12'b010110010101, |
12'b1xxx01000100: aluop_sel = `ALUOP_BSUB; |
//12'b001000010110, |
//12'b001000010rrr, |
12'b010010101100, |
12'b010010101101, |
12'b010110101100, |
12'b010110101101: aluop_sel = `ALUOP_BXOR; |
12'b001000010xxx: aluop_sel = `ALUOP_RL; |
//12'b001000000110, |
//12'b001000000rrr, |
12'b001000000xxx: aluop_sel = `ALUOP_RLC; |
//12'b001000011110, |
//12'b001000011rrr, |
12'b001000011xxx: aluop_sel = `ALUOP_RR; |
//12'b001000001110, |
//12'b001000001rrr, |
12'b001000001xxx: aluop_sel = `ALUOP_RRC; |
12'b1xxx01xx0010: aluop_sel = `ALUOP_SBC; |
//12'b001000100110, |
//12'b001000100rrr, |
12'b001000100xxx: aluop_sel = `ALUOP_SLA; |
//12'b001000101110, |
//12'b001000101rrr, |
12'b001000110xxx: aluop_sel = `ALUOP_SLL; |
12'b001000101xxx: aluop_sel = `ALUOP_SRA; |
//12'b001000111110, |
//12'b001000111rrr, |
12'b001000111xxx: aluop_sel = `ALUOP_SRL; |
default: aluop_sel = `ALUOP_PASS; |
endcase |
1950,12 → 2078,10
end |
`RD2B: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b000000xxx100,//12'b000000110100,12'b000000rrr100, |
12'b000000xxx100, |
12'b010000110100, |
12'b010100110100: aluop_sel = `ALUOP_BADD; |
12'b001010xxxxxx,//12'b001010xxx110,12'b001010xxxrrr, |
12'b011010xxx110, |
12'b011110xxx110, |
12'b0x1x10xxxxxx, |
12'b1xxx10100010, |
12'b1xxx10100011, |
12'b1xxx10101010, |
1964,12 → 2090,10
12'b1xxx10110011, |
12'b1xxx10111010, |
12'b1xxx10111011: aluop_sel = `ALUOP_BAND; |
12'b000000xxx101,//12'b000000110101,12'b000000rrr101, |
12'b000000xxx101, |
12'b010000110101, |
12'b010100110101: aluop_sel = `ALUOP_BDEC; |
12'b001011xxxxxx,//12'b001011xxx110,12'b001011xxxrrr, |
12'b011011xxx110, |
12'b011111xxx110: aluop_sel = `ALUOP_BOR; |
12'b0x1x11xxxxxx: aluop_sel = `ALUOP_BOR; |
12'b1xxx10100001, |
12'b1xxx10101001, |
12'b1xxx10110001, |
1986,29 → 2110,16
12'b1xxx10101000, |
12'b1xxx10110000, |
12'b1xxx10111000: aluop_sel = `ALUOP_PASS; |
12'b001000010xxx,//12'b001000010110,12'b001000010rrr, |
12'b011000010110, |
12'b011100010110: aluop_sel = `ALUOP_RL; |
12'b001000000xxx,//12'b001000000110,12'b001000000rrr, |
12'b011000000110, |
12'b011100000110: aluop_sel = `ALUOP_RLC; |
12'b1xxx01101111: aluop_sel = `ALUOP_RLD1; |
12'b001000011xxx,//12'b001000011110,12'b001000011rrr, |
12'b011000011110, |
12'b011100011110: aluop_sel = `ALUOP_RR; |
12'b001000001xxx,//12'b001000001110,12'b001000001rrr, |
12'b011000001110, |
12'b011100001110: aluop_sel = `ALUOP_RRC; |
12'b1xxx01100111: aluop_sel = `ALUOP_RRD1; |
12'b001000100xxx,//12'b001000100110,12'b001000100rrr, |
12'b011000100110, |
12'b011100100110: aluop_sel = `ALUOP_SLA; |
12'b001000101xxx,//12'b001000101110,12'b001000101rrr, |
12'b011000101110, |
12'b011100101110: aluop_sel = `ALUOP_SRA; |
12'b001000111xxx,//12'b001000111110,12'b001000111rrr, |
12'b011000111110, |
12'b011100111110: aluop_sel = `ALUOP_SRL; |
12'b0x1x00000xxx: aluop_sel = `ALUOP_RLC; |
12'b0x1x00001xxx: aluop_sel = `ALUOP_RRC; |
12'b0x1x00010xxx: aluop_sel = `ALUOP_RL; |
12'b0x1x00011xxx: aluop_sel = `ALUOP_RR; |
12'b0x1x00100xxx: aluop_sel = `ALUOP_SLA; |
12'b0x1x00101xxx: aluop_sel = `ALUOP_SRA; |
12'b0x1x00110xxx: aluop_sel = `ALUOP_SLL; |
12'b0x1x00111xxx: aluop_sel = `ALUOP_SRL; |
12'b1xxx01101111: aluop_sel = `ALUOP_RLD1; |
12'b1xxx01100111: aluop_sel = `ALUOP_RRD1; |
default: aluop_sel = `ALUOP_ADD; |
endcase |
end |
2066,10 → 2177,6
default: aluop_sel = `ALUOP_ADD; |
endcase |
end |
// `BLK1, |
// `BLK2, |
// `PCA, |
// `PCO: aluop_sel = `ALUOP_ADD; |
`IF1A: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b1xxx10100000, |
2091,9 → 2198,8
12'b1xxx10110011, |
12'b1xxx10111011: aluop_sel = `ALUOP_BADD; |
12'b000010100xxx, |
12'b001001xxxxxx, |
12'b0x1x01xxxxxx, |
12'b010x10100110, |
12'b011x01xxx110, |
12'b000011100110, |
12'b1xxx01xxx000: aluop_sel = `ALUOP_BAND; |
12'b000010110xxx, |
2150,23 → 2256,33
default: alua_sel = `ALUA_ONE; |
endcase |
end |
// `IF2B: alua_sel = `ALUA_ONE; |
`DEC2: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b001001xxxxxx, |
12'b001010xxxxxx, |
12'b001011xxxxxx: alua_sel = `ALUA_BIT; |
12'b1xxx01xx0010, |
12'b1xxx01xx1010: alua_sel = `ALUA_HL; |
12'b1xxx01010111: alua_sel = `ALUA_II; |
12'b010000xx1001: alua_sel = `ALUA_IX; |
12'b010100xx1001: alua_sel = `ALUA_IY; |
12'b010000100101, |
12'b010000101011, |
12'b010000101101, |
12'b010011100101, |
12'b010100100101, |
12'b010100101011, |
12'b010100101101, |
12'b010111100101: alua_sel = `ALUA_M1; |
12'b010000100100, |
12'b010000101100, |
12'b010000100011, |
12'b010100100100, |
12'b010100101100, |
12'b010100100011: alua_sel = `ALUA_ONE; |
12'b1xxx01011111: alua_sel = `ALUA_RR; |
12'b1xxx01000100: alua_sel = `ALUA_ZER; |
default: alua_sel = `ALUA_BIT; |
default: alua_sel = `ALUA_AA; |
endcase |
end |
`OF1B: begin |
2187,11 → 2303,9
default: alua_sel = `ALUA_M1; |
endcase |
end |
// `OF2B: alua_sel = `ALUA_ONE; |
`IF3A: alua_sel = (page_reg[0]) ? `ALUA_IY : `ALUA_IX; |
`ADR1: alua_sel = (page_reg[2]) ? ((page_reg[0]) ? `ALUA_IY : `ALUA_IX) : `ALUA_M1; |
`ADR2: alua_sel = `ALUA_M1; |
// `RD1A: alua_sel = `ALUA_ONE; |
`RD1B: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b1xxx10100001, |
2219,13 → 2333,8
12'b1xxx10101001, |
12'b1xxx10110001, |
12'b1xxx10111001: alua_sel = `ALUA_AA; |
12'b001010xxxxxx,//12'b001010xxx110,12'b001010xxxrrr, |
12'b001011xxxxxx,//12'b001011xxx110,12'b001011xxxrrr, |
12'b011010xxx110, |
12'b011011xxx110, |
12'b011110xxx110, |
12'b011111xxx110: alua_sel = `ALUA_BIT; |
12'b000000xxx101,//12'b000000110101,12'b000000rrr101, |
12'b0x1x1xxxxxxx: alua_sel = `ALUA_BIT; |
12'b000000xxx101, |
12'b010000110101, |
12'b010100110101, |
12'b1xxx10100010, |
2295,31 → 2404,15
endcase |
end |
`BLK1: begin |
/*casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b1xxx10101001, |
12'b1xxx10111001: alua_sel = `ALUA_NEG1; |
12'b1xxx10100001, |
12'b1xxx10110001: alua_sel = `ALUA_ONE; |
default: alua_sel = `ALUA_ONE; |
endcase*/ |
alua_sel = (inst_reg[3]) ? `ALUA_M1 : `ALUA_ONE; |
end |
`BLK2: begin |
/*casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b1xxx10110001, |
12'b1xxx10111001: alua_sel = `ALUA_NEG1; |
12'b1xxx10100001, |
12'b1xxx10101001: alua_sel = `ALUA_ONE; |
default: alua_sel = `ALUA_ONE; |
endcase*/ |
alua_sel = (inst_reg[4]) ? `ALUA_M1 : `ALUA_ONE; |
end |
`PCA: alua_sel = (tflg_reg) ? `ALUA_ZER : `ALUA_M2; |
// `PCO: alua_sel = `ALUA_ONE; |
`IF1A: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b001001xxxxxx, |
12'b011x01xxx110: alua_sel = `ALUA_BIT; |
12'b0x1x01xxxxxx: alua_sel = `ALUA_BIT; |
12'b1xxx01xxx000, |
12'b1xxx10100011, |
12'b1xxx10101000, |
2419,6 → 2512,50
12'b010000101011, |
12'b010011101001, |
12'b010011111001: alub_sel = `ALUB_IX; |
12'b010000100100, |
12'b010000100101, |
12'b0100010xx100,12'b01000110x100,12'b010001111100, |
12'b010010000100, |
12'b010010001100, |
12'b010010010100, |
12'b010010011100, |
12'b010010100100, |
12'b010010101100, |
12'b010010110100, |
12'b010010111100: alub_sel = `ALUB_IXH; |
12'b010100100100, |
12'b010100100101, |
12'b0101010xx100,12'b01010110x100,12'b010101111100, |
12'b010110000100, |
12'b010110001100, |
12'b010110010100, |
12'b010110011100, |
12'b010110100100, |
12'b010110101100, |
12'b010110110100, |
12'b010110111100: alub_sel = `ALUB_IYH; |
12'b010000101100, |
12'b010000101101, |
12'b0100010xx101,12'b01000110x101,12'b010001111101, |
12'b010010000101, |
12'b010010001101, |
12'b010010010101, |
12'b010010011101, |
12'b010010100101, |
12'b010010101101, |
12'b010010110101, |
12'b010010111101: alub_sel = `ALUB_IXL; |
12'b010100101100, |
12'b010100101101, |
12'b0101010xx101,12'b01010110x101,12'b010101111101, |
12'b010110000101, |
12'b010110001101, |
12'b010110010101, |
12'b010110011101, |
12'b010110100101, |
12'b010110101101, |
12'b010110110101, |
12'b010110111101: alub_sel = `ALUB_IYL; |
12'b010100100011, |
12'b010100101011, |
12'b010111101001, |
2425,59 → 2562,27
12'b010111111001: alub_sel = `ALUB_IY; |
12'b1xxx01000101, |
12'b1xxx01001101: alub_sel = `ALUB_PC; |
//12'b001000000110,12'b001000000rrr,12'b001000001110,12'b001000001rrr,12'b001000010110,12'b001000010rrr,12'b001000011110,12'b001000011rrr |
//12'b001000100110,12'b001000100rrr,12'b001000101110,12'b001000101rrr |
//12'b001000111110,12'b001000111rrr |
//12'b001001xxx110,12'b001001xxxrrr |
//12'b001010xxx110,12'b001010xxxrrr,12'b001011xxx110,12'b001011xxxrrr |
12'b0010000xx000, |
12'b00100010x000, |
12'b001000111000, |
12'b001001xxx000, |
12'b00101xxxx000: alub_sel = `ALUB_BB; |
12'b0010000xx001, |
12'b00100010x001, |
12'b001000111001, |
12'b001001xxx001, |
12'b00101xxxx001: alub_sel = `ALUB_CC; |
12'b0010000xx010, |
12'b00100010x010, |
12'b001000111010, |
12'b001001xxx010, |
12'b00101xxxx010: alub_sel = `ALUB_DD; |
12'b0010000xx011, |
12'b00100010x011, |
12'b001000111011, |
12'b001001xxx011, |
12'b00101xxxx011: alub_sel = `ALUB_EE; |
12'b0010000xx100, |
12'b00100010x100, |
12'b001000111100, |
12'b001001xxx100, |
12'b00101xxxx100: alub_sel = `ALUB_HH; |
12'b0010000xx101, |
12'b00100010x101, |
12'b001000111101, |
12'b001001xxx101, |
12'b00101xxxx101: alub_sel = `ALUB_LL; |
12'b0010000xx111, |
12'b00100010x111, |
12'b001000111111, |
12'b001001xxx111, |
12'b00101xxxx111: alub_sel = `ALUB_AA; |
//12'b1xxx01xx0010, |
//12'b1xxx01xx1010: |
12'b010x0110x000, |
12'b0010xxxxx000: alub_sel = `ALUB_BB; |
12'b010x0110x001, |
12'b0010xxxxx001: alub_sel = `ALUB_CC; |
12'b010x0110x010, |
12'b0010xxxxx010: alub_sel = `ALUB_DD; |
12'b010x0110x011, |
12'b0010xxxxx011: alub_sel = `ALUB_EE; |
12'b0010xxxxx100: alub_sel = `ALUB_HH; |
12'b0010xxxxx101: alub_sel = `ALUB_LL; |
12'b010x0110x111, |
12'b0010xxxxx111: alub_sel = `ALUB_AA; |
12'b1xxx0100x010: alub_sel = `ALUB_BC; |
12'b1xxx0101x010: alub_sel = `ALUB_DE; |
//12'b1xxx0110x010: alub_sel = `ALUB_HL; |
12'b1xxx0111x010: alub_sel = `ALUB_SP; |
12'b010011100101, |
12'b010111100101: alub_sel = `ALUB_SP; |
//12'b010000xx1001 |
//12'b010100xx1001 |
12'b010x00001001: alub_sel = `ALUB_BC; |
12'b010x00011001: alub_sel = `ALUB_DE; |
12'b010x00101001: alub_sel = (page_reg[0]) ? `ALUB_IY : `ALUB_IX; |
12'b010000101001: alub_sel = `ALUB_IX; |
12'b010100101001: alub_sel = `ALUB_IY; |
12'b010x00111001: alub_sel = `ALUB_SP; |
default: alub_sel = `ALUB_HL; |
endcase |
2557,16 → 2662,11
12'b1xxx10110001, |
12'b1xxx10111000, |
12'b1xxx10111001: alub_sel = `ALUB_BC; |
//12'b000000100010: alub_sel = `ALUB_HL; |
12'b010000100010: alub_sel = `ALUB_IX; |
12'b010011100101: alub_sel = `ALUB_IXH; |
12'b010100100010: alub_sel = `ALUB_IY; |
12'b010111100101: alub_sel = `ALUB_IYH; |
12'b000011xxx111: alub_sel = `ALUB_PCH; |
//12'b000001110110,12'b000001110rrr, |
//12'b000001rdrrsr,12'b000001rrr110, |
//12'b010001110rrr,12'b010101110rrr, |
//12'b1xxx01rrr001 |
12'b000001xxx000, |
12'b010x01110000, |
12'b1xxx01000001: alub_sel = `ALUB_BB; |
2585,15 → 2685,11
12'b000001xxx101, |
12'b010x01110101, |
12'b1xxx01101001: alub_sel = `ALUB_LL; |
//12'b000001xxx110, |
//12'b010101110110, |
//12'b1xxx01110001: alub_sel = `ALUB_HL; |
12'b000001xxx111, |
12'b010x01110111, |
12'b1xxx01111001: alub_sel = `ALUB_AA; |
12'b1xxx01000011: alub_sel = `ALUB_BC; |
12'b1xxx01010011: alub_sel = `ALUB_DE; |
//12'b1xxx01100011: alub_sel = `ALUB_HL; |
12'b1xxx01110011: alub_sel = `ALUB_SP; |
12'b000011000101: alub_sel = `ALUB_BB; |
12'b000011010101: alub_sel = `ALUB_DD; |
2639,7 → 2735,7
12'b1xxx10101000, |
12'b1xxx10110000, |
12'b1xxx10111000: alub_sel = `ALUB_DE; |
12'b001010xxxxxx,//12'b001010xxx110,12'b001010xxxrrr, |
12'b001010xxxxxx, |
12'b1xxx10100001, |
12'b1xxx10100010, |
12'b1xxx10101001, |
2671,15 → 2767,15
12'b000000011010, |
12'b000000101010, |
12'b000000111010, |
12'b000001xxxxxx,//12'b000001rdrrsr,12'b000001rrr110, |
12'b000010000xxx,//12'b000010000110,12'b000010000rrr, |
12'b000010001xxx,//12'b000010001110,12'b000010001rrr, |
12'b000010010xxx,//12'b000010010110,12'b000010010rrr, |
12'b000010011xxx,//12'b000010011110,12'b000010011rrr, |
12'b000010100xxx,//12'b000010100110,12'b000010100rrr, |
12'b000010101xxx,//12'b000010101110,12'b000010101rrr, |
12'b000010110xxx,//12'b000010110110,12'b000010110rrr, |
12'b000010111xxx,//12'b000010111110,12'b000010111rrr, |
12'b000001xxxxxx, |
12'b000010000xxx, |
12'b000010001xxx, |
12'b000010010xxx, |
12'b000010011xxx, |
12'b000010100xxx, |
12'b000010101xxx, |
12'b000010110xxx, |
12'b000010111xxx, |
12'b000011011011, |
12'b000011xx0001, |
12'b001001xxx110, |
2942,7 → 3038,6
default: wr_addr = `WREG_NUL; |
endcase |
end |
//`WR1A: wr_addr = `WREG_NUL; |
`WR1B: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b1xxx10100000, |
2963,7 → 3058,6
default: wr_addr = `WREG_NUL; |
endcase |
end |
//`WR2A: wr_addr = `WREG_NUL; |
`WR2B: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b1xxx10100000, |
2977,7 → 3071,6
default: wr_addr = `WREG_NUL; |
endcase |
end |
//`BLK1: wr_addr = `WREG_NUL; |
`BLK2: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b1xxx10100001, |
2987,161 → 3080,223
default: wr_addr = `WREG_NUL; |
endcase |
end |
//`PCA: wr_addr = `WREG_NUL; |
//`PCO: wr_addr = `WREG_NUL; |
`IF1B: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b000000000111, |
12'b000000001010, |
12'b000000001111, |
12'b000000010111, |
12'b000000011010, |
12'b000000011111, |
12'b000000100111, |
12'b000000101111, |
12'b000000111010, |
12'b000010000xxx, |
12'b000010001xxx, |
12'b000010010xxx, |
12'b000010011xxx, |
12'b000010100xxx, |
12'b000010101xxx, |
12'b000010110xxx, |
12'b000011000110, |
12'b000011001110, |
12'b000011010110, |
12'b000011011011, |
12'b010x10000110, |
12'b010x10001110, |
12'b010x10010110, |
12'b010x10011110, |
12'b010x10100110, |
12'b010x10101110, |
12'b010x10110110, |
12'b000011011110, |
12'b000011100110, |
12'b1xxx01000100, |
12'b1xxx01010111, |
12'b1xxx01011111, |
12'b1xxx01100111, |
12'b1xxx01101111, |
12'b000011101110, |
12'b000011110110: wr_addr = `WREG_AA; |
12'b000000000111, |
12'b000000001010, |
12'b000000001111, |
12'b000000010111, |
12'b000000011010, |
12'b000000011111, |
12'b000000100111, |
12'b000000101111, |
12'b000000111010, |
12'b00000011110x, |
12'b000000111110, |
12'b000001111xxx, |
12'b000010000xxx, |
12'b000010001xxx, |
12'b000010010xxx, |
12'b000010011xxx, |
12'b000010100xxx, |
12'b000010101xxx, |
12'b000010110xxx, |
12'b000011000110, |
12'b000011001110, |
12'b000011010110, |
12'b000011011011, |
12'b000011011110, |
12'b000011100110, |
12'b000011101110, |
12'b000011110110, |
12'b001000xxx111, |
12'b00101xxxx111, |
//12'b011x00xxx111, |
//12'b011x1xxxx111, |
12'b010010000100, |
12'b010010000101, |
12'b010010000110, |
12'b010010001100, |
12'b010010001101, |
12'b010010001110, |
12'b010010010100, |
12'b010010010101, |
12'b010010010110, |
12'b010010011100, |
12'b010010011101, |
12'b010010011110, |
12'b010010100100, |
12'b010010100101, |
12'b010010100110, |
12'b010010101100, |
12'b010010101101, |
12'b010010101110, |
12'b010010110100, |
12'b010010110101, |
12'b010010110110, |
12'b010110000100, |
12'b010110000101, |
12'b010110000110, |
12'b010110001100, |
12'b010110001101, |
12'b010110001110, |
12'b010110010100, |
12'b010110010101, |
12'b010110010110, |
12'b010110011100, |
12'b010110011101, |
12'b010110011110, |
12'b010110100100, |
12'b010110100101, |
12'b010110100110, |
12'b010110101100, |
12'b010110101101, |
12'b010110101110, |
12'b010110110100, |
12'b010110110101, |
12'b010110110110, |
12'b010x0111110x, |
12'b010x01111110, |
12'b1xxx01000100, |
12'b1xxx01010111, |
12'b1xxx01011111, |
12'b1xxx01100111, |
12'b1xxx01101111, |
12'b1xxx0x111000: wr_addr = `WREG_AA; |
12'b000011110001: wr_addr = `WREG_AF; |
12'b00000000010x, |
12'b000000000110, |
12'b000001000xxx, |
12'b001000xxx000, |
12'b00101xxxx000, |
//12'b011x00xxx000, |
// 12'b011x1xxxx000, |
12'b010x0100010x, |
12'b010x01000110, |
12'b1xxx0x000000, |
12'b1xxx10100011, |
12'b1xxx10101011, |
12'b1xxx10110011, |
12'b1xxx10111011: wr_addr = `WREG_BB; |
12'b000000000001, |
12'b00000000x011, |
12'b000011000001, |
12'b1xxx01001011: wr_addr = `WREG_BC; |
12'b00000000110x, |
12'b000000001110, |
12'b000001001xxx, |
12'b001000xxx001, |
12'b00101xxxx001, |
//12'b011x00xxx001, |
//12'b011x1xxxx001, |
12'b010x0100110x, |
12'b010x01001110, |
12'b1xxx0x001000: wr_addr = `WREG_CC; |
12'b00000001010x, |
12'b000000010110, |
12'b000001010xxx, |
12'b001000xxx010, |
12'b00101xxxx010, |
//12'b011x00xxx010, |
//12'b011x1xxxx010, |
12'b010x0101010x, |
12'b010x01010110, |
12'b1xxx0x010000: wr_addr = `WREG_DD; |
12'b000011010001, |
12'b00000001x011, |
12'b000000010001, |
12'b1xxx01011011: wr_addr = `WREG_DE; |
12'b1xxx01011011, |
12'b1xxx10100000, |
12'b1xxx10101000, |
12'b1xxx10110000, |
12'b1xxx10111000: wr_addr = `WREG_DE; |
12'b000011101011: wr_addr = `WREG_DEHL; |
12'b00000001110x, |
12'b000000011110, |
12'b000001011xxx, |
12'b001000xxx011, |
12'b00101xxxx011, |
//12'b011x00xxx011, |
//12'b011x1xxxx011, |
12'b010x0101110x, |
12'b010x01011110, |
12'b1xxx0x011000: wr_addr = `WREG_EE; |
12'b00000010010x, |
12'b000000100110, |
12'b000001100xxx, |
12'b001000xxx100, |
12'b00101xxxx100, |
//12'b011x00xxx100, |
//12'b011x1xxxx100, |
12'b010x01100110, |
12'b1xxx0x100000: wr_addr = `WREG_HH; |
12'b000000100001, |
12'b1xxx01101011: wr_addr = `WREG_HL; |
12'b000000101010, |
12'b00000010x011, |
12'b000000xx1001, |
12'b000011100001, |
12'b000011100011, |
12'b1xxx01101011, |
12'b1xxx01xx0010, |
12'b1xxx01xx1010, |
12'b1xxx10100010, |
12'b1xxx10101010, |
12'b1xxx10110010, |
12'b1xxx10111010: wr_addr = `WREG_HL; |
12'b1xxx01000111: wr_addr = `WREG_II; |
12'b010000100001, |
12'b010000100011, |
12'b010000101010, |
12'b010000101011, |
12'b010000xx1001, |
12'b010011100001, |
12'b010011100011: wr_addr = `WREG_IX; |
12'b010000100100, |
12'b010000100101, |
12'b010000100110, |
12'b0100011000xx, |
12'b01000110010x, |
12'b010001100111: wr_addr = `WREG_IXH; |
12'b010000101100, |
12'b010000101101, |
12'b010000101110, |
12'b0100011010xx, |
12'b01000110110x, |
12'b010001101111: wr_addr = `WREG_IXL; |
12'b010100100001, |
12'b010100100011, |
12'b010100101010, |
12'b010100101011, |
12'b010100xx1001, |
12'b010111100001, |
12'b010111100011: wr_addr = `WREG_IY; |
12'b010100100100, |
12'b010100100101, |
12'b010100100110, |
12'b0101011000xx, |
12'b01010110010x, |
12'b010101100111: wr_addr = `WREG_IYH; |
12'b010100101100, |
12'b010100101101, |
12'b010100101110, |
12'b0101011010xx, |
12'b01010110110x, |
12'b010101101111: wr_addr = `WREG_IYL; |
12'b00000010110x, |
12'b000000101110, |
12'b000001101xxx, |
12'b001000xxx101, |
12'b00101xxxx101, |
//12'b011x00xxx101, |
//12'b011x1xxxx101, |
12'b010x01101110, |
12'b1xxx0x101000: wr_addr = `WREG_LL; |
12'b1xxx01001111: wr_addr = `WREG_RR; |
12'b000000110001, |
12'b00000011x011, |
12'b000011111001, |
12'b010x11111001, |
12'b1xxx01111011: wr_addr = `WREG_SP; |
12'b1xxx10100000, |
12'b1xxx10101000, |
12'b1xxx10110000, |
12'b1xxx10111000: wr_addr = `WREG_DE; |
12'b000011101011: wr_addr = `WREG_DEHL; |
12'b000000101010, |
12'b000000xx1001, |
12'b000011100011, |
12'b1xxx01xx0010, |
12'b1xxx01xx1010, |
12'b1xxx10100010, |
12'b1xxx10101010, |
12'b1xxx10110010, |
12'b1xxx10111010: wr_addr = `WREG_HL; |
12'b1xxx01000111: wr_addr = `WREG_II; |
12'b010000100001, |
12'b010000100011, |
12'b010000101010, |
12'b010000101011, |
12'b010000xx1001, |
12'b010011100001, |
12'b010011100011: wr_addr = `WREG_IX; |
12'b010100100001, |
12'b010100100011, |
12'b010100101010, |
12'b010100101011, |
12'b010100xx1001, |
12'b010111100001, |
12'b010111100011: wr_addr = `WREG_IY; |
12'b1xxx01001111: wr_addr = `WREG_RR; |
12'b0010000xx000, |
12'b00100010x000, |
12'b001000111000, |
12'b00101xxxx000: wr_addr = `WREG_BB; |
12'b0010000xx001, |
12'b00100010x001, |
12'b001000111001, |
12'b00101xxxx001: wr_addr = `WREG_CC; |
12'b0010000xx010, |
12'b00100010x010, |
12'b001000111010, |
12'b00101xxxx010: wr_addr = `WREG_DD; |
12'b0010000xx011, |
12'b00100010x011, |
12'b001000111011, |
12'b00101xxxx011: wr_addr = `WREG_EE; |
12'b0010000xx100, |
12'b00100010x100, |
12'b001000111100, |
12'b00101xxxx100: wr_addr = `WREG_HH; |
12'b0010000xx101, |
12'b00100010x101, |
12'b001000111101, |
12'b00101xxxx101: wr_addr = `WREG_LL; |
12'b0010000xx111, |
12'b00100010x111, |
12'b001000111111, |
12'b00101xxxx111: wr_addr = `WREG_AA; |
12'b00000000010x, |
12'b000000000110, |
12'b000001000xxx, |
12'b010x01000110, |
12'b1xxx0x000000: wr_addr = `WREG_BB; |
12'b00000000110x, |
12'b000000001110, |
12'b000001001xxx, |
12'b010x01001110, |
12'b1xxx0x001000: wr_addr = `WREG_CC; |
12'b00000001010x, |
12'b000000010110, |
12'b000001010xxx, |
12'b010x01010110, |
12'b1xxx0x010000: wr_addr = `WREG_DD; |
12'b00000001110x, |
12'b000000011110, |
12'b000001011xxx, |
12'b010x01011110, |
12'b1xxx0x011000: wr_addr = `WREG_EE; |
12'b00000010010x, |
12'b000000100110, |
12'b000001100xxx, |
12'b010x01100110, |
12'b1xxx0x100000: wr_addr = `WREG_HH; |
12'b00000010110x, |
12'b000000101110, |
12'b000001101xxx, |
12'b010x01101110, |
12'b1xxx0x101000: wr_addr = `WREG_LL; |
12'b00000011110x, |
12'b000000111110, |
12'b000001111xxx, |
12'b010x01111110, |
12'b1xxx0x111000: wr_addr = `WREG_AA; |
12'b00000000x011: wr_addr = `WREG_BC; |
12'b00000001x011: wr_addr = `WREG_DE; |
12'b00000010x011: wr_addr = `WREG_HL; |
12'b00000011x011: wr_addr = `WREG_SP; |
12'b010x11111001, |
12'b000011111001: wr_addr = `WREG_SP; |
12'b000011000001: wr_addr = `WREG_BC; |
12'b000011010001: wr_addr = `WREG_DE; |
12'b000011100001: wr_addr = `WREG_HL; |
12'b000011110001: wr_addr = `WREG_AF; |
default: wr_addr = `WREG_NUL; |
endcase |
end |
3159,24 → 3314,14
casex (state_reg) //synopsys parallel_case |
`WR2A: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b000000110100, |
12'b000000110101, |
12'b001000000xxx, |
12'b001000001xxx, |
12'b001000010xxx, |
12'b001000011xxx, |
12'b001000100xxx, |
12'b001000101xxx, |
12'b001000111xxx, |
12'b010x00110100, |
12'b010x00110101, |
12'b011x00010110, |
12'b011x00000110, |
12'b011x00011110, |
12'b011x00001110, |
12'b011x00100110, |
12'b011x00101110, |
12'b011x00111110: sflg_en = 1'b1; |
12'b000000110100, |
12'b000000110101, |
12'b001000xxxxxx, |
12'b010000110100, |
12'b010000110101, |
12'b010100110100, |
12'b010100110101, |
12'b011x00xxxxxx: sflg_en = 1'b1; |
default: sflg_en = 1'b0; |
endcase |
end |
3192,62 → 3337,98
`IF1B: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b000000100111, |
12'b0000000xx100,12'b00000010x100,12'b000000111100,//12'b000000rrr100, |
12'b0000000xx101,12'b00000010x101,12'b000000111101,//12'b000000rrr101, |
12'b000010000110, |
12'b000010000xxx, |
12'b000010001110, |
12'b000010001xxx, |
12'b000010010110, |
12'b000010010xxx, |
12'b000010011110, |
12'b000010011xxx, |
12'b000010100110, |
12'b000010100xxx, |
12'b000010101110, |
12'b000010101xxx, |
12'b000010110110, |
12'b000010110xxx, |
12'b000010111110, |
12'b000010111xxx, |
12'b000011000110, |
12'b000011001110, |
12'b000011010110, |
12'b000011011110, |
12'b000011100110, |
12'b000011101110, |
12'b000011110110, |
12'b000011111110, |
12'b0010000000xx,12'b00100000010x,12'b001000000111,//12'b001000000rrr, |
12'b0010000010xx,12'b00100000110x,12'b001000001111,//12'b001000001rrr, |
12'b0010000100xx,12'b00100001010x,12'b001000010111,//12'b001000010rrr, |
12'b0010000110xx,12'b00100001110x,12'b001000011111,//12'b001000011rrr, |
12'b0010001000xx,12'b00100010010x,12'b001000100111,//12'b001000100rrr, |
12'b0010001010xx,12'b00100010110x,12'b001000101111,//12'b001000101rrr, |
12'b0010001110xx,12'b00100011110x,12'b001000111111,//12'b001000111rrr, |
12'b010010000110, |
12'b010010001110, |
12'b010010010110, |
12'b010010011110, |
12'b010010100110, |
12'b010010101110, |
12'b010010110110, |
12'b010010111110, |
12'b010110000110, |
12'b010110001110, |
12'b010110010110, |
12'b010110011110, |
12'b010110100110, |
12'b010110101110, |
12'b010110110110, |
12'b010110111110, |
12'b1xxx01000100, |
12'b1xxx01010111, |
12'b1xxx01011111, |
12'b1xxx01100111, |
12'b1xxx01101111, |
12'b1xxx01xxx000, |
12'b1xxx01xx0010, |
12'b0000000xx100,12'b00000010x100,12'b000000111100, |
12'b0000000xx101,12'b00000010x101,12'b000000111101, |
12'b000010000110, |
12'b000010000xxx, |
12'b000010001110, |
12'b000010001xxx, |
12'b000010010110, |
12'b000010010xxx, |
12'b000010011110, |
12'b000010011xxx, |
12'b000010100110, |
12'b000010100xxx, |
12'b000010101110, |
12'b000010101xxx, |
12'b000010110110, |
12'b000010110xxx, |
12'b000010111110, |
12'b000010111xxx, |
12'b000011000110, |
12'b000011001110, |
12'b000011010110, |
12'b000011011110, |
12'b000011100110, |
12'b000011101110, |
12'b000011110110, |
12'b000011111110, |
12'b001000xxx0xx, |
12'b001000xxx10x, |
12'b001000xxx111, |
12'b010000100100, |
12'b010000100101, |
12'b010000101100, |
12'b010000101101, |
12'b010010000100, |
12'b010010000101, |
12'b010010000110, |
12'b010010001100, |
12'b010010001101, |
12'b010010001110, |
12'b010010010100, |
12'b010010010101, |
12'b010010010110, |
12'b010010011100, |
12'b010010011101, |
12'b010010011110, |
12'b010010100100, |
12'b010010100101, |
12'b010010100110, |
12'b010010101100, |
12'b010010101101, |
12'b010010101110, |
12'b010010110100, |
12'b010010110101, |
12'b010010110110, |
12'b010010111100, |
12'b010010111101, |
12'b010010111110, |
12'b010100100100, |
12'b010100100101, |
12'b010100101100, |
12'b010100101101, |
12'b010110000100, |
12'b010110000101, |
12'b010110000110, |
12'b010110001100, |
12'b010110001101, |
12'b010110001110, |
12'b010110010100, |
12'b010110010101, |
12'b010110010110, |
12'b010110011100, |
12'b010110011101, |
12'b010110011110, |
12'b010110100100, |
12'b010110100101, |
12'b010110100110, |
12'b010110101100, |
12'b010110101101, |
12'b010110101110, |
12'b010110110100, |
12'b010110110101, |
12'b010110110110, |
12'b010110111100, |
12'b010110111101, |
12'b010110111110, |
12'b1xxx01000100, |
12'b1xxx01010111, |
12'b1xxx01011111, |
12'b1xxx01100111, |
12'b1xxx01101111, |
12'b1xxx01xxx000, |
12'b1xxx01xx0010, |
12'b1xxx01xx1010: sflg_en = 1'b1; |
default: sflg_en = 1'b0; |
endcase |
3279,40 → 3460,14
end |
`WR2A: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b000000110100, |
12'b000000110101, |
12'b001000000110, |
12'b001000000xxx, |
12'b001000001110, |
12'b001000001xxx, |
12'b001000010110, |
12'b001000010xxx, |
12'b001000011110, |
12'b001000011xxx, |
12'b001000100110, |
12'b001000100xxx, |
12'b001000101110, |
12'b001000101xxx, |
12'b001000111110, |
12'b001000111xxx, |
12'b010000110100, |
12'b010000110101, |
12'b010100110100, |
12'b010100110101, |
12'b011000000110, |
12'b011000001110, |
12'b011000010110, |
12'b011000011110, |
12'b011000100110, |
12'b011000101110, |
12'b011000111110, |
12'b011100000110, |
12'b011100001110, |
12'b011100010110, |
12'b011100011110, |
12'b011100100110, |
12'b011100101110, |
12'b011100111110: zflg_en = 1'b1; |
12'b000000110100, |
12'b000000110101, |
12'b001000xxxxxx, |
12'b010000110100, |
12'b010000110101, |
12'b010100110100, |
12'b010100110101, |
12'b011x00xxxxxx: zflg_en = 1'b1; |
default: zflg_en = 1'b0; |
endcase |
end |
3328,8 → 3483,8
`IF1B: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b000000100111, |
12'b0000000xx100,12'b00000010x100,12'b000000111100,//12'b000000rrr100, |
12'b0000000xx101,12'b00000010x101,12'b000000111101,//12'b000000rrr101, |
12'b0000000xx100,12'b00000010x100,12'b000000111100, |
12'b0000000xx101,12'b00000010x101,12'b000000111101, |
12'b000010000110, |
12'b000010000xxx, |
12'b000010001110, |
3354,30 → 3509,64
12'b000011101110, |
12'b000011110110, |
12'b000011111110, |
12'b0010000000xx,12'b00100000010x,12'b001000000111,//12'b001000000rrr, |
12'b0010000010xx,12'b00100000110x,12'b001000001111,//12'b001000001rrr, |
12'b0010000100xx,12'b00100001010x,12'b001000010111,//12'b001000010rrr, |
12'b0010000110xx,12'b00100001110x,12'b001000011111,//12'b001000011rrr, |
12'b0010001000xx,12'b00100010010x,12'b001000100111,//12'b001000100rrr, |
12'b0010001010xx,12'b00100010110x,12'b001000101111,//12'b001000101rrr, |
12'b0010001110xx,12'b00100011110x,12'b001000111111,//12'b001000111rrr, |
12'b001000xxx0xx,12'b001000xxx10x,12'b001000xxx111, |
12'b001001xxx110, |
12'b001001xxxxxx, |
12'b010000100100, |
12'b010000100101, |
12'b010000101100, |
12'b010000101101, |
12'b010010000100, |
12'b010010000101, |
12'b010010000110, |
12'b010010001100, |
12'b010010001101, |
12'b010010001110, |
12'b010010010100, |
12'b010010010101, |
12'b010010010110, |
12'b010010011100, |
12'b010010011101, |
12'b010010011110, |
12'b010010100100, |
12'b010010100101, |
12'b010010100110, |
12'b010010101100, |
12'b010010101101, |
12'b010010101110, |
12'b010010110100, |
12'b010010110101, |
12'b010010110110, |
12'b010010111100, |
12'b010010111101, |
12'b010010111110, |
12'b010100100100, |
12'b010100100101, |
12'b010100101100, |
12'b010100101101, |
12'b010110000100, |
12'b010110000101, |
12'b010110000110, |
12'b010110001100, |
12'b010110001101, |
12'b010110001110, |
12'b010110010100, |
12'b010110010101, |
12'b010110010110, |
12'b010110011100, |
12'b010110011101, |
12'b010110011110, |
12'b010110100100, |
12'b010110100101, |
12'b010110100110, |
12'b010110101100, |
12'b010110101101, |
12'b010110101110, |
12'b010110110100, |
12'b010110110101, |
12'b010110110110, |
12'b010110111100, |
12'b010110111101, |
12'b010110111110, |
12'b011001xxx110, |
12'b011101xxx110, |
3409,20 → 3598,8
casex (state_reg) //synopsys parallel_case |
`WR2A: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b001000000xxx, |
12'b001000001xxx, |
12'b001000010xxx, |
12'b001000011xxx, |
12'b001000100xxx, |
12'b001000101xxx, |
12'b001000111xxx, |
12'b011x00010110, |
12'b011x00000110, |
12'b011x00011110, |
12'b011x00001110, |
12'b011x00100110, |
12'b011x00101110, |
12'b011x00111110, |
12'b001000xxxxxx, |
12'b011x00xxxxxx, |
12'b1xxx01100111, |
12'b1xxx01101111: hflg_ctl = `HFLG_0; |
12'b000000110100, |
3443,79 → 3620,120
end |
`IF1B: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b000000000111, |
12'b000000001111, |
12'b000000010111, |
12'b000000011111, |
12'b000000110111, |
12'b000010101110, |
12'b000010101xxx, |
12'b000010110110, |
12'b000010110xxx, |
12'b000011101110, |
12'b000011110110, |
12'b001000000xxx, |
12'b001000001xxx, |
12'b001000010xxx, |
12'b001000011xxx, |
12'b001000100xxx, |
12'b001000101xxx, |
12'b001000111xxx, |
12'b010010101110, |
12'b010010110110, |
12'b010110101110, |
12'b010110110110, |
12'b1xxx01010111, |
12'b1xxx01011111, |
12'b1xxx01xxx000, |
12'b1xxx10100000, |
12'b1xxx10101000, |
12'b1xxx10110000, |
12'b000000000111, |
12'b000000001111, |
12'b000000010111, |
12'b000000011111, |
12'b000000110111, |
12'b000010101110, |
12'b000010101xxx, |
12'b000010110110, |
12'b000010110xxx, |
12'b000011101110, |
12'b000011110110, |
12'b001000000xxx, |
12'b001000001xxx, |
12'b001000010xxx, |
12'b001000011xxx, |
12'b001000100xxx, |
12'b001000101xxx, |
12'b001000110xxx, |
12'b001000111xxx, |
12'b010010101100, |
12'b010010101101, |
12'b010010101110, |
12'b010010110100, |
12'b010010110101, |
12'b010010110110, |
12'b010110101100, |
12'b010110101101, |
12'b010110101110, |
12'b010110110100, |
12'b010110110101, |
12'b010110110110, |
12'b1xxx01010111, |
12'b1xxx01011111, |
12'b1xxx01xxx000, |
12'b1xxx10100000, |
12'b1xxx10101000, |
12'b1xxx10110000, |
12'b1xxx10111000: hflg_ctl = `HFLG_0; |
12'b000000101111, |
12'b000010100110, |
12'b000010100xxx, |
12'b000011100110, |
12'b001001xxx110, |
12'b001001xxxxxx, |
12'b010010100110, |
12'b010110100110, |
12'b011001xxx110, |
12'b000000101111, |
12'b000010100110, |
12'b000010100xxx, |
12'b000011100110, |
12'b001001xxx110, |
12'b001001xxxxxx, |
12'b010010100100, |
12'b010010100101, |
12'b010010100110, |
12'b010110100100, |
12'b010110100101, |
12'b010110100110, |
12'b011001xxx110, |
12'b011101xxx110: hflg_ctl = `HFLG_1; |
12'b000000111111: hflg_ctl = `HFLG_H; |
12'b000000100111, |
12'b0000000xx100,12'b00000010x100,12'b000000111100,//12'b000000rrr100, |
12'b0000000xx101,12'b00000010x101,12'b000000111101,//12'b000000rrr101, |
12'b000000xx1001, |
12'b000010000110, |
12'b000010000xxx, |
12'b000010001110, |
12'b000010001xxx, |
12'b000010010110, |
12'b000010010xxx, |
12'b000010011110, |
12'b000010011xxx, |
12'b000010111110, |
12'b000010111xxx, |
12'b000011000110, |
12'b000011001110, |
12'b000011010110, |
12'b000011011110, |
12'b000011111110, |
12'b010000xx1001, |
12'b010010000110, |
12'b010010001110, |
12'b010010010110, |
12'b010010011110, |
12'b010010111110, |
12'b010100xx1001, |
12'b010110000110, |
12'b010110001110, |
12'b010110010110, |
12'b010110011110, |
12'b010110111110, |
12'b1xxx01000100, |
12'b1xxx01xx0010, |
12'b000000111111, |
12'b000000100111, |
12'b0000000xx100,12'b00000010x100,12'b000000111100, |
12'b0000000xx101,12'b00000010x101,12'b000000111101, |
12'b000000xx1001, |
12'b000010000110, |
12'b000010000xxx, |
12'b000010001110, |
12'b000010001xxx, |
12'b000010010110, |
12'b000010010xxx, |
12'b000010011110, |
12'b000010011xxx, |
12'b000010111110, |
12'b000010111xxx, |
12'b000011000110, |
12'b000011001110, |
12'b000011010110, |
12'b000011011110, |
12'b000011111110, |
12'b010000100100, |
12'b010000100101, |
12'b010000101100, |
12'b010000101101, |
12'b010000xx1001, |
12'b010010000100, |
12'b010010000101, |
12'b010010000110, |
12'b010010001100, |
12'b010010001101, |
12'b010010001110, |
12'b010010010100, |
12'b010010010101, |
12'b010010010110, |
12'b010010011100, |
12'b010010011101, |
12'b010010011110, |
12'b010010111100, |
12'b010010111101, |
12'b010010111110, |
12'b010100100100, |
12'b010100100101, |
12'b010100101100, |
12'b010100101101, |
12'b010100xx1001, |
12'b010110000100, |
12'b010110000101, |
12'b010110000110, |
12'b010110001100, |
12'b010110001101, |
12'b010110001110, |
12'b010110010100, |
12'b010110010101, |
12'b010110010110, |
12'b010110011100, |
12'b010110011101, |
12'b010110011110, |
12'b010110111100, |
12'b010110111101, |
12'b010110111110, |
12'b1xxx01000100, |
12'b1xxx01xx0010, |
12'b1xxx01xx1010: hflg_ctl = `HFLG_H; |
default: hflg_ctl = `HFLG_NUL; |
endcase |
3547,34 → 3765,8
end |
`WR2A: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b001000000110, |
12'b001000000xxx, |
12'b001000001110, |
12'b001000001xxx, |
12'b001000010110, |
12'b001000010xxx, |
12'b001000011110, |
12'b001000011xxx, |
12'b001000100110, |
12'b001000100xxx, |
12'b001000101110, |
12'b001000101xxx, |
12'b001000111110, |
12'b001000111xxx, |
12'b011000000110, |
12'b011000001110, |
12'b011000010110, |
12'b011000011110, |
12'b011000100110, |
12'b011000101110, |
12'b011000111110, |
12'b011100000110, |
12'b011100001110, |
12'b011100010110, |
12'b011100011110, |
12'b011100100110, |
12'b011100101110, |
12'b011100111110: pflg_ctl = `PFLG_P; |
12'b001000xxxxxx, |
12'b011x00xxxxxx: pflg_ctl = `PFLG_P; |
12'b000000110100, |
12'b000000110101, |
12'b010000110100, |
3588,61 → 3780,95
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b1xxx01010111, |
12'b1xxx01011111: pflg_ctl = `PFLG_F; |
12'b000000100111, |
12'b000010100110, |
12'b000010100xxx, |
12'b000010101110, |
12'b000010101xxx, |
12'b000010110110, |
12'b000010110xxx, |
12'b000011100110, |
12'b000011101110, |
12'b000011110110, |
12'b0010000000xx,12'b00100000010x,12'b001000000111,//12'b001000000rrr, |
12'b0010000010xx,12'b00100000110x,12'b001000001111,//12'b001000001rrr, |
12'b0010000100xx,12'b00100001010x,12'b001000010111,//12'b001000010rrr, |
12'b0010000110xx,12'b00100001110x,12'b001000011111,//12'b001000011rrr, |
12'b0010001000xx,12'b00100010010x,12'b001000100111,//12'b001000100rrr, |
12'b0010001010xx,12'b00100010110x,12'b001000101111,//12'b001000101rrr, |
12'b0010001110xx,12'b00100011110x,12'b001000111111,//12'b001000111rrr, |
12'b010010100110, |
12'b010010101110, |
12'b010010110110, |
12'b010110100110, |
12'b010110101110, |
12'b010110110110, |
12'b1xxx01100111, |
12'b1xxx01101111, |
12'b000000100111, |
12'b000010100110, |
12'b000010100xxx, |
12'b000010101110, |
12'b000010101xxx, |
12'b000010110110, |
12'b000010110xxx, |
12'b000011100110, |
12'b000011101110, |
12'b000011110110, |
12'b001000xxx0xx,12'b001000xxx10x,12'b001000xxx111, |
12'b010010100100, |
12'b010010100101, |
12'b010010100110, |
12'b010010101100, |
12'b010010101101, |
12'b010010101110, |
12'b010010110100, |
12'b010010110101, |
12'b010010110110, |
12'b010110100100, |
12'b010110100101, |
12'b010110100110, |
12'b010110101100, |
12'b010110101101, |
12'b010110101110, |
12'b010110110100, |
12'b010110110101, |
12'b010110110110, |
12'b1xxx01100111, |
12'b1xxx01101111, |
12'b1xxx01xxx000: pflg_ctl = `PFLG_P; |
12'b0000000xx100,12'b00000010x100,12'b000000111100,//12'b000000rrr100, |
12'b0000000xx101,12'b00000010x101,12'b000000111101,//12'b000000rrr101, |
12'b000010000110, |
12'b000010000xxx, |
12'b000010001110, |
12'b000010001xxx, |
12'b000010010110, |
12'b000010010xxx, |
12'b000010011110, |
12'b000010011xxx, |
12'b000010111110, |
12'b000010111xxx, |
12'b000011000110, |
12'b000011001110, |
12'b000011010110, |
12'b000011011110, |
12'b000011111110, |
12'b010010000110, |
12'b010010001110, |
12'b010010010110, |
12'b010010011110, |
12'b010010111110, |
12'b010110000110, |
12'b010110001110, |
12'b010110010110, |
12'b010110011110, |
12'b010110111110, |
12'b1xxx01000100, |
12'b1xxx01xx0010, |
12'b0000000xx100,12'b00000010x100,12'b000000111100, |
12'b0000000xx101,12'b00000010x101,12'b000000111101, |
12'b000010000110, |
12'b000010000xxx, |
12'b000010001110, |
12'b000010001xxx, |
12'b000010010110, |
12'b000010010xxx, |
12'b000010011110, |
12'b000010011xxx, |
12'b000010111110, |
12'b000010111xxx, |
12'b000011000110, |
12'b000011001110, |
12'b000011010110, |
12'b000011011110, |
12'b000011111110, |
12'b010000100100, |
12'b010000100101, |
12'b010000101100, |
12'b010000101101, |
12'b010010000100, |
12'b010010000101, |
12'b010010000110, |
12'b010010001100, |
12'b010010001101, |
12'b010010001110, |
12'b010010010100, |
12'b010010010101, |
12'b010010010110, |
12'b010010011100, |
12'b010010011101, |
12'b010010011110, |
12'b010010111100, |
12'b010010111101, |
12'b010010111110, |
12'b010100100100, |
12'b010100100101, |
12'b010100101100, |
12'b010100101101, |
12'b010110000100, |
12'b010110000101, |
12'b010110000110, |
12'b010110001100, |
12'b010110001101, |
12'b010110001110, |
12'b010110010100, |
12'b010110010101, |
12'b010110010110, |
12'b010110011100, |
12'b010110011101, |
12'b010110011110, |
12'b010110111100, |
12'b010110111101, |
12'b010110111110, |
12'b1xxx01000100, |
12'b1xxx01xx0010, |
12'b1xxx01xx1010: pflg_ctl = `PFLG_V; |
default: pflg_ctl = `PFLG_NUL; |
endcase |
3674,111 → 3900,121
end |
`IF1B: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b000000000111, |
12'b000000001111, |
12'b000000010111, |
12'b000000011111, |
12'b000000110100, |
12'b000000110111, |
12'b000000111111, |
12'b0000000xx100,12'b00000010x100,12'b000000111100,//12'b000000rrr100, |
12'b000000xx1001, |
12'b000010000110, |
12'b000010000xxx, |
12'b000010001110, |
12'b000010001xxx, |
12'b000010100110, |
12'b000010100xxx, |
12'b000010101110, |
12'b000010101xxx, |
12'b000010110110, |
12'b000010110xxx, |
12'b000011000110, |
12'b000011001110, |
12'b000011100110, |
12'b000011101110, |
12'b000011110110, |
12'b001000000110, |
12'b001000000xxx, |
12'b001000001110, |
12'b001000001xxx, |
12'b001000010110, |
12'b001000010xxx, |
12'b001000011110, |
12'b001000011xxx, |
12'b001000100110, |
12'b001000100xxx, |
12'b001000101110, |
12'b001000101xxx, |
12'b001000111110, |
12'b001000111xxx, |
12'b001001xxx110, |
12'b001001xxxxxx, |
12'b010000110100, |
12'b010000xx1001, |
12'b010010000110, |
12'b010010001110, |
12'b010010100110, |
12'b010010101110, |
12'b010010110110, |
12'b010100110100, |
12'b010100xx1001, |
12'b010110000110, |
12'b010110001110, |
12'b010110100110, |
12'b010110101110, |
12'b010110110110, |
12'b011000000110, |
12'b011000001110, |
12'b011000010110, |
12'b011000011110, |
12'b011000100110, |
12'b011000101110, |
12'b011000111110, |
12'b011001xxx110, |
12'b011100000110, |
12'b011100001110, |
12'b011100010110, |
12'b011100011110, |
12'b011100100110, |
12'b011100101110, |
12'b011100111110, |
12'b011101xxx110, |
12'b1xxx01010111, |
12'b1xxx01011111, |
12'b1xxx01100111, |
12'b1xxx01101111, |
12'b1xxx01xxx000, |
12'b1xxx01xx1010, |
12'b1xxx10100000, |
12'b1xxx10101000, |
12'b1xxx10110000, |
12'b000000000111, |
12'b000000001111, |
12'b000000010111, |
12'b000000011111, |
12'b000000110100, |
12'b000000110111, |
12'b000000111111, |
12'b000000xxx100, |
12'b000000xx1001, |
12'b000010000110, |
12'b000010000xxx, |
12'b000010001110, |
12'b000010001xxx, |
12'b000010100110, |
12'b000010100xxx, |
12'b000010101110, |
12'b000010101xxx, |
12'b000010110110, |
12'b000010110xxx, |
12'b000011000110, |
12'b000011001110, |
12'b000011100110, |
12'b000011101110, |
12'b000011110110, |
12'b010000100100, |
12'b010000101100, |
12'b010000110100, |
12'b010000xx1001, |
12'b010010000100, |
12'b010010000101, |
12'b010010000110, |
12'b010010001100, |
12'b010010001101, |
12'b010010001110, |
12'b010010100100, |
12'b010010100101, |
12'b010010100110, |
12'b010010101100, |
12'b010010101101, |
12'b010010101110, |
12'b010010110100, |
12'b010010110101, |
12'b010010110110, |
12'b010100100100, |
12'b010100101100, |
12'b010100110100, |
12'b010100xx1001, |
12'b010110000100, |
12'b010110000101, |
12'b010110000110, |
12'b010110001100, |
12'b010110001101, |
12'b010110001110, |
12'b010110100100, |
12'b010110100101, |
12'b010110100110, |
12'b010110101100, |
12'b010110101101, |
12'b010110101110, |
12'b010110110100, |
12'b010110110101, |
12'b010110110110, |
12'b00100xxxxxxx, |
12'b011x0xxxxxxx, |
12'b1xxx01010111, |
12'b1xxx01011111, |
12'b1xxx01100111, |
12'b1xxx01101111, |
12'b1xxx01xxx000, |
12'b1xxx01xx1010, |
12'b1xxx10100000, |
12'b1xxx10101000, |
12'b1xxx10110000, |
12'b1xxx10111000: nflg_ctl = `NFLG_0; |
12'b000000101111, |
12'b000000110101, |
12'b0000000xx101,12'b00000010x101,12'b000000111101,//12'b000000rrr101, |
12'b000010010110, |
12'b000010010xxx, |
12'b000010011110, |
12'b000010011xxx, |
12'b000010111110, |
12'b000010111xxx, |
12'b000011010110, |
12'b000011011110, |
12'b000011111110, |
12'b010000110101, |
12'b010010010110, |
12'b010010011110, |
12'b010010111110, |
12'b010100110101, |
12'b010110010110, |
12'b010110011110, |
12'b010110111110, |
12'b1xxx01000100, |
12'b1xxx01xx0010, |
12'b1xxx10100001, |
12'b1xxx10101001, |
12'b1xxx10110001, |
12'b000000101111, |
12'b000000110101, |
12'b000000xxx101, |
12'b000010010110, |
12'b000010010xxx, |
12'b000010011110, |
12'b000010011xxx, |
12'b000010111110, |
12'b000010111xxx, |
12'b000011010110, |
12'b000011011110, |
12'b000011111110, |
12'b010000100101, |
12'b010000101101, |
12'b010000110101, |
12'b010010010100, |
12'b010010010101, |
12'b010010010110, |
12'b010010011100, |
12'b010010011101, |
12'b010010011110, |
12'b010010111100, |
12'b010010111101, |
12'b010010111110, |
12'b010100100101, |
12'b010100101101, |
12'b010100110101, |
12'b010110010100, |
12'b010110010101, |
12'b010110010110, |
12'b010110011100, |
12'b010110011101, |
12'b010110011110, |
12'b010110111100, |
12'b010110111101, |
12'b010110111110, |
12'b1xxx01000100, |
12'b1xxx01xx0010, |
12'b1xxx10100001, |
12'b1xxx10101001, |
12'b1xxx10110001, |
12'b1xxx10111001: nflg_ctl = `NFLG_1; |
default: nflg_ctl = `NFLG_NUL; |
endcase |
3796,84 → 4032,98
casex (state_reg) //synopsys parallel_case |
`WR2A: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b001000000xxx, |
12'b001000001xxx, |
12'b001000010xxx, |
12'b001000011xxx, |
12'b001000100xxx, |
12'b001000101xxx, |
12'b001000111xxx, |
12'b011x00000110, |
12'b011x00001110, |
12'b011x00010110, |
12'b011x00011110, |
12'b011x00100110, |
12'b011x00101110, |
12'b011x00111110: cflg_en = 1'b1; |
12'b001000xxxxxx, |
12'b011x00xxxxxx: cflg_en = 1'b1; |
default: cflg_en = 1'b0; |
endcase |
end |
`IF1B: begin |
casex ({page_reg, inst_reg}) //synopsys parallel_case |
12'b000010100110, |
12'b000010100xxx, |
12'b000010101110, |
12'b000010101xxx, |
12'b000010110110, |
12'b000010110xxx, |
12'b000011100110, |
12'b000011101110, |
12'b000011110110, |
12'b010010100110, |
12'b010010101110, |
12'b010010110110, |
12'b010110100110, |
12'b010110101110, |
12'b010110110110, |
12'b000000110111, |
12'b000000000111, |
12'b000000001111, |
12'b000000010111, |
12'b000000011111, |
12'b000000100111, |
12'b000000111111, |
12'b000000xx1001, |
12'b000010000110, |
12'b000010000xxx, |
12'b000010001110, |
12'b000010001xxx, |
12'b000010010110, |
12'b000010010xxx, |
12'b000010011110, |
12'b000010011xxx, |
12'b000010111110, |
12'b000010111xxx, |
12'b000011000110, |
12'b000011001110, |
12'b000011010110, |
12'b000011011110, |
12'b000011111110, |
12'b0010000000xx,12'b00100000010x,12'b001000000111,//12'b001000000rrr, |
12'b0010000010xx,12'b00100000110x,12'b001000001111,//12'b001000001rrr, |
12'b0010000100xx,12'b00100001010x,12'b001000010111,//12'b001000010rrr, |
12'b0010000110xx,12'b00100001110x,12'b001000011111,//12'b001000011rrr, |
12'b0010001000xx,12'b00100010010x,12'b001000100111,//12'b001000100rrr, |
12'b0010001010xx,12'b00100010110x,12'b001000101111,//12'b001000101rrr, |
12'b0010001110xx,12'b00100011110x,12'b001000111111,//12'b001000111rrr, |
12'b010000xx1001, |
12'b010010000110, |
12'b010010001110, |
12'b010010010110, |
12'b010010011110, |
12'b010010111110, |
12'b010100xx1001, |
12'b010110000110, |
12'b010110001110, |
12'b010110010110, |
12'b010110011110, |
12'b010110111110, |
12'b1xxx01000100, |
12'b1xxx01xx0010, |
12'b000010100110, |
12'b000010100xxx, |
12'b000010101110, |
12'b000010101xxx, |
12'b000010110110, |
12'b000010110xxx, |
12'b000011100110, |
12'b000011101110, |
12'b000011110110, |
12'b010010100100, |
12'b010010100101, |
12'b010010100110, |
12'b010010101100, |
12'b010010101101, |
12'b010010101110, |
12'b010010110100, |
12'b010010110101, |
12'b010010110110, |
12'b010110100100, |
12'b010110100101, |
12'b010110100110, |
12'b010110101100, |
12'b010110101101, |
12'b010110101110, |
12'b010110110100, |
12'b010110110101, |
12'b010110110110, |
12'b000000110111, |
12'b000000000111, |
12'b000000001111, |
12'b000000010111, |
12'b000000011111, |
12'b000000100111, |
12'b000000111111, |
12'b000000xx1001, |
12'b000010000110, |
12'b000010000xxx, |
12'b000010001110, |
12'b000010001xxx, |
12'b000010010110, |
12'b000010010xxx, |
12'b000010011110, |
12'b000010011xxx, |
12'b000010111110, |
12'b000010111xxx, |
12'b000011000110, |
12'b000011001110, |
12'b000011010110, |
12'b000011011110, |
12'b000011111110, |
12'b001000xxx0xx,12'b001000xxx10x,12'b001000xxx111, |
12'b010000xx1001, |
12'b010010000100, |
12'b010010000101, |
12'b010010000110, |
12'b010010001100, |
12'b010010001101, |
12'b010010001110, |
12'b010010010100, |
12'b010010010101, |
12'b010010010110, |
12'b010010011100, |
12'b010010011101, |
12'b010010011110, |
12'b010010111100, |
12'b010010111101, |
12'b010010111110, |
12'b010100xx1001, |
12'b010110000100, |
12'b010110000101, |
12'b010110000110, |
12'b010110001100, |
12'b010110001101, |
12'b010110001110, |
12'b010110010100, |
12'b010110010101, |
12'b010110010110, |
12'b010110011100, |
12'b010110011101, |
12'b010110011110, |
12'b010110111100, |
12'b010110111101, |
12'b010110111110, |
12'b1xxx01000100, |
12'b1xxx01xx0010, |
12'b1xxx01xx1010: cflg_en = 1'b1; |
default: cflg_en = 1'b0; |
endcase |
/trunk/rtl/y80_top.v
75,6 → 75,7
wire rd_frst; /* first clock of read */ |
wire rd_nxt; /* read trans next */ |
wire reti_nxt, reti_tran; /* reti transaction */ |
wire rreg_en; /* update refresh register */ |
wire sflg_en; /* sign flag control */ |
wire sign_bit; /* sign flag */ |
wire tflg_reg; /* temporary flag */ |
158,7 → 159,7
.ld_inta(ld_inta), .ld_page(ld_page), .ld_wait(ld_wait), |
.nflg_ctl(nflg_ctl), .output_inh(output_inh), .page_sel(page_sel), |
.pc_sel(pc_sel), .pflg_ctl(pflg_ctl), .rd_frst(rd_frst), |
.rd_nxt(rd_nxt), .reti_nxt(reti_nxt), .sflg_en(sflg_en), |
.rd_nxt(rd_nxt), .reti_nxt(reti_nxt), .rreg_en(rreg_en), .sflg_en(sflg_en), |
.state_nxt(state_nxt), .tflg_ctl(tflg_ctl), .tran_sel(tran_sel), |
.wr_addr(wr_addr), .wr_frst(wr_frst), .zflg_en(zflg_en), |
.carry_bit(carry_bit), .dmar_reg(dmar_reg), .inst_reg(inst_reg), |
184,7 → 185,7
.imd_ctl(imd_ctl), .int_req(int_req), .ivec_rd(ivec_rd), |
.ld_ctrl(ld_ctrl), .ld_inst(ld_inst), .ld_page(ld_page), |
.nflg_ctl(nflg_ctl), .nmi_req(nmi_req), .page_sel(page_sel), |
.pc_sel(pc_sel), .pflg_ctl(pflg_ctl), .resetb(resetb), |
.pc_sel(pc_sel), .pflg_ctl(pflg_ctl), .resetb(resetb), .rreg_en(rreg_en), |
.sflg_en(sflg_en), .tflg_ctl(tflg_ctl), .wait_st(wait_st), |
.wr_addr(wr_addr), .zflg_en(zflg_en) ); |
|
/trunk/rtl/alu_shft.v
36,6 → 36,7
`AOP_RRA: shft_c = alub_in[0]; |
`AOP_RRC, |
`AOP_RRCA: shft_c = alub_in[0]; |
`AOP_SLL, |
`AOP_SLA: shft_c = alub_in[7]; |
`AOP_SRA: shft_c = alub_in[0]; |
`AOP_SRL: shft_c = alub_in[0]; |
54,6 → 55,7
`AOP_RRC, |
`AOP_RRCA: shft_out = {alub_in[0], alub_in[7:1]}; |
`AOP_SLA: shft_out = {alub_in[6:0], 1'b0}; |
`AOP_SLL: shft_out = {alub_in[6:0], 1'b1}; |
`AOP_SRA: shft_out = {alub_in[7], alub_in[7:1]}; |
`AOP_SRL: shft_out = {1'b0, alub_in[7:1]}; |
default: shft_out = 8'h00; |
/trunk/rtl/version.v
14,6 → 14,13
|
/*******************************************************************************************/ |
/* */ |
/* enable/disable refresh register emulation (if enabled then breaks testbench) */ |
/* */ |
/*******************************************************************************************/ |
// `define RREG_EMU /* enable emulation */ |
|
/*******************************************************************************************/ |
/* */ |
/* select CPU or MPU */ |
/* */ |
/*******************************************************************************************/ |
/trunk/rtl/datapath.v
11,7 → 11,7
data_in, di_ctl, dma_req, do_ctl, ex_af_pls, ex_bank_pls, ex_dehl_inst, |
hflg_ctl, ief_ctl, imd_ctl, int_req, ivec_rd, ld_ctrl, ld_inst, ld_page, |
nflg_ctl, nmi_req, page_sel, pc_sel, pflg_ctl, resetb, sflg_en, tflg_ctl, |
wait_st, wr_addr, zflg_en); |
wait_st, wr_addr, zflg_en, rreg_en); |
|
input cflg_en; /* carry flag control */ |
input clearb; /* master (testing) reset */ |
27,6 → 27,7
input ld_page; /* load page register */ |
input nmi_req; /* nmi request */ |
input resetb; /* internal (user) reset */ |
input rreg_en; /* update R register */ |
input sflg_en; /* sign flag control */ |
input wait_st; /* wait state identifier */ |
input zflg_en; /* zero flag control */ |
91,7 → 92,8
wire ld_m_dd, ld_m_ee, ld_m_hh, ld_m_ll; |
wire ld_a_aa, ld_a_ff, ld_a_bb, ld_a_cc; |
wire ld_a_dd, ld_a_ee, ld_a_hh, ld_a_ll; |
wire ld_sp, ld_ix, ld_iy; |
wire ld_sp; |
wire ld_ixh, ld_ixl, ld_iyh, ld_iyl; |
wire ld_ii, ld_rr, ld_tmp; |
wire ld_dout_io, ld_dout_mem; /* load data out */ |
wire ld_flag; /* load flags */ |
305,8 → 307,10
assign ld_a_hh = ld_regf && wr_addr[`WR_HH] && alt_bnk_reg; |
assign ld_a_ll = ld_regf && wr_addr[`WR_LL] && alt_bnk_reg; |
assign ld_sp = ld_regf && wr_addr[`WR_SP]; |
assign ld_ix = ld_regf && wr_addr[`WR_IX]; |
assign ld_iy = ld_regf && wr_addr[`WR_IY]; |
assign ld_ixh = ld_regf && wr_addr[`WR_IXH]; |
assign ld_ixl = ld_regf && wr_addr[`WR_IXL]; |
assign ld_iyh = ld_regf && wr_addr[`WR_IYH]; |
assign ld_iyl = ld_regf && wr_addr[`WR_IYL]; |
assign ld_ii = ld_regf && wr_addr[`WR_II]; |
assign ld_rr = ld_regf && wr_addr[`WR_RR]; |
assign ld_tmp = ld_regf && wr_addr[`WR_TMP]; |
325,6 → 329,8
(wr_addr[`WR_BB] && !wr_addr[`WR_CC]) || |
(wr_addr[`WR_DD] && !wr_addr[`WR_EE]) || |
(wr_addr[`WR_HH] && !wr_addr[`WR_LL]) || |
(wr_addr[`WR_IXH]&& !wr_addr[`WR_IXL]) || |
(wr_addr[`WR_IYH]&& !wr_addr[`WR_IYL]) || |
wr_addr[`WR_II] || wr_addr[`WR_RR]; |
|
/*****************************************************************************************/ |
370,8 → 376,10
if (ld_a_ee) a_ee_reg <= de_reg_in[7:0]; |
if (ld_a_hh) a_hh_reg <= data_bus[15:8]; |
if (ld_a_ll) a_ll_reg <= data_bus[7:0]; |
if (ld_ix) ix_reg <= data_bus; |
if (ld_iy) iy_reg <= data_bus; |
if (ld_ixh) ix_reg[15:8] <= data_bus[15:8]; |
if (ld_ixl) ix_reg[7:0] <= data_bus[7:0]; |
if (ld_iyh) iy_reg[15:8] <= data_bus[15:8]; |
if (ld_iyl) iy_reg[7:0] <= data_bus[7:0]; |
end |
end |
|
386,7 → 394,12
else begin |
if (ld_ii) ii_reg <= data_bus[15:8]; |
if (ld_pc) pc_reg <= data_bus; |
if (ld_rr) rr_reg <= data_bus[15:8]; |
if (ld_rr) |
rr_reg <= data_bus[15:8]; |
`ifdef RREG_EMU |
else |
rr_reg[6:0] <= rr_reg[6:0] + {6'h0, rreg_en && !dmar_reg && !wait_st}; |
`endif |
if (ld_sp) sp_reg <= data_bus; |
if (ld_tmp) tmp_reg <= (ivec_rd) ? {ii_reg, data_in} : data_bus; |
end |
/trunk/doc/execute.ods
Cannot display: file marked as a binary type.
svn:mime-type = application/vnd.oasis.opendocument.spreadsheet
trunk/doc/execute.ods
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/vnd.oasis.opendocument.spreadsheet
\ No newline at end of property
Index: trunk/mem/alu_ops.vm
===================================================================
--- trunk/mem/alu_ops.vm (revision 3)
+++ trunk/mem/alu_ops.vm (revision 4)
@@ -43,15 +43,25 @@
@0600 23 CB 2E F5 23 CB 3E F5 DD CB 08 06 F5 DD CB 09 0E F5 DD CB 0A 16 F5 DD CB 0B 1E F5 DD CB 0C 26
@0620 F5 DD CB 0D 2E F5 DD CB 0E 3E F5 FD CB 08 06 F5 FD CB 09 0E F5 FD CB 0A 16 F5 FD CB 0B 1E F5 FD
@0640 CB 0C 26 F5 FD CB 0D 2E F5 FD CB 0E 3E F5 AF 47 4F 57 5F 67 6F 3E 35 07 F5 07 F5 07 F5 07 F5 07
-@0660 F5 0F F5 0F F5 0F F5 0F F5 0F F5 17 F5 17 F5 17 F5 17 F5 17 F5 1F F5 1F F5 1F F5 1F F5 1F F5 31
-@0680 00 FA F1 31 00 FB 27 F5 31 02 FA F1 31 FE FA 27 F5 31 04 FA F1 31 FC FA 27 F5 31 06 FA F1 31 FA
-@06A0 FA 27 F5 31 08 FA F1 31 F8 FA 27 F5 31 0A FA F1 31 F6 FA 27 F5 31 0C FA F1 31 F4 FA 27 F5 31 0E
-@06C0 FA F1 31 F2 FA 27 F5 31 10 FA F1 31 F0 FA 27 F5 31 12 FA F1 31 EE FA 27 F5 31 14 FA F1 31 EC FA
-@06E0 27 F5 31 16 FA F1 31 EA FA 27 F5 31 18 FA F1 31 E8 FA 27 F5 AF 31 CC FA 21 0F 30 3E 67 ED 6F F5
-@0700 23 ED 67 F5 21 00 01 C3 C0 00
-@1000 C7 A2 80 01 01 01 01 01 67 67 67 67 67 67 67
-@2000 82 AB 78 78 60 60 78 60 F0 F0 F0 F0 F0 F0 F0
-@3000 3C 55 55 FF AA AA FF AA C5 C5 C5 C4 C5 C5 C5 2F E3
+@0660 F5 0F F5 0F F5 0F F5 0F F5 0F F5 17 F5 17 F5 17 F5 17 F5 17 F5 1F F5 1F F5 1F F5 1F F5 1F F5 01
+@0680 67 58 11 CB 9A 21 F0 21 31 48 FD BF 3E 35 CB 37 F5 CB 37 F5 CB 37 F5 CB 37 F5 CB 37 F5 C5 D5 E5
+@06A0 CB 30 C5 CB 31 C5 CB 32 D5 CB 33 D5 CB 34 E5 CB 35 E5 F5 BF 21 11 30 CB 36 F5 BF DD CB 0F 36 F5
+@06C0 BF FD CB 0F 36 F5 31 00 FA F1 31 00 FB 27 F5 31 02 FA F1 31 FE FA 27 F5 31 04 FA F1 31 FC FA 27
+@06E0 F5 31 06 FA F1 31 FA FA 27 F5 31 08 FA F1 31 F8 FA 27 F5 31 0A FA F1 31 F6 FA 27 F5 31 0C FA F1
+@0700 31 F4 FA 27 F5 31 0E FA F1 31 F2 FA 27 F5 31 10 FA F1 31 F0 FA 27 F5 31 12 FA F1 31 EE FA 27 F5
+@0720 31 14 FA F1 31 EC FA 27 F5 31 16 FA F1 31 EA FA 27 F5 31 18 FA F1 31 E8 FA 27 F5 AF 31 CC FA 21
+@0740 0F 30 3E 67 ED 6F F5 23 ED 67 F5 21 AA AA 01 BC BC 11 DE DE 31 00 FC DD 21 30 60 FD 21 07 AE 3E
+@0760 AA DD 8C F5 3E AA DD 8D F5 3E AA FD 8C F5 3E AA FD 8D F5 3E AA DD 84 F5 3E AA DD 85 F5 3E AA FD
+@0780 84 F5 3E AA FD 85 F5 3E AA DD A4 F5 3E AA DD A5 F5 3E AA FD A4 F5 3E AA FD A5 F5 3E AA DD 21 01
+@07A0 01 FD 21 01 01 37 DD 25 F5 3F DD 25 F5 DD 2D F5 37 DD 2D F5 FD 25 F5 FD 25 3F F5 FD 2D F5 FD 2D
+@07C0 F5 DD E5 FD E5 DD 24 F5 DD 2C F5 37 FD 24 F5 FD 2C F5 DD 24 F5 3F DD 2C F5 37 FD 24 F5 3F FD 2C
+@07E0 F5 DD E5 FD E5 DD 21 30 60 FD 21 07 AE 3E AA DD B4 F5 3E AA 37 DD B5 F5 37 3E AA FD B4 F5 3E AA
+@0800 FD B5 F5 3E AA DD AC F5 3E AA DD AD F5 3E AA FD AC F5 3E AA FD AD F5 3E 60 DD BC F5 DD BD F5 FD
+@0820 BC F5 FD BD F5 3E AA DD 9C F5 3E AA DD 9D F5 3E AA FD 9C F5 3E AA FD 9D F5 3E AA DD 94 F5 3E AA
+@0840 DD 95 F5 3E AA FD 94 F5 3E AA FD 95 F5 C5 D5 E5 DD E5 21 00 01 C3 C0 00
+@1000 C7 A2 80 01 01 01 01 01 67 67 67 67 67 67 67 66
+@2000 82 AB 78 78 60 60 78 60 F0 F0 F0 F0 F0 F0 F0 F0
+@3000 3C 55 55 FF AA AA FF AA C5 C5 C5 C4 C5 C5 C5 2F E3 C5
@78CB 2E C0
@BC9E F0 80
@CA02 1F 00
Index: trunk/mem/alu_opsd.vm
===================================================================
--- trunk/mem/alu_opsd.vm (revision 3)
+++ trunk/mem/alu_opsd.vm (revision 4)
@@ -1,26 +1,31 @@
-@1008 CE B3 CF 33 CE 33 33
-@2008 E1 78 E0 F8 E0 F8 78
+@1008 CE B3 CF 33 CE 33 33 CD
+@2008 E1 78 E0 F8 E0 F8 78 E1
@2DA8 FF FF FF FF FF FF 72 38 00 00 00 00 FF FF FF FF
-@3008 8B E2 8B E2 8A E2 62 F7 2E
+@3008 8B E2 8B E2 8A E2 62 F7 2E 8B
@78CB 2F BF
@BC9E F1 7F
@CA02 20 FF
@FAC8 04 63 00 62 72 38 F0 0F 72 38 01 3F FF 00 01 FE 00 00 01 FF 01 FE 00 00 01 FF FF FF 00 00 57 00
@FAE8 03 13 96 82 06 77 01 67 91 85 85 84 05 17 11 01 05 06 04 78 94 90 84 99
-@FC00 44 35 44 6A 44 D4 45 A8 45 51 44 A3 45 51 45 A8 44 D4 44 6A 44 35 44 6A 45 D4 45 A9 44 53 44 A6
-@FC20 45 53 45 A9 44 D4 44 6A 04 00 80 00 81 00 80 00 81 00 04 00 85 00 05 00 05 00 80 00 05 00 84 00
-@FC40 81 00 80 00 01 00 85 00 81 00 84 00 85 00 85 00 85 00 04 00 78 10 F0 10 65 4D CB 4D 33 2C 67 2C
-@FC60 80 00 F8 10 F0 10 E5 CD CB CD 33 2C 67 2C 81 00 E0 42 F0 42 96 34 CB 34 CE B0 67 B0 80 00 F8 90
-@FC80 F0 90 65 CD CB CD 33 AC 67 AC 81 00 E0 43 F0 43 97 34 CB 34 CE B0 67 B0 04 00 78 90 F0 90 E5 4D
-@FCA0 CB 4D B3 2C 67 2C 85 00 E1 42 F0 42 97 35 CB 35 CE B0 67 B0 00 00 00 00 00 00 05 21 00 43 05 06
-@FCC0 00 0D 01 1A 85 E1 84 C3 05 06 00 0D 01 1A 84 A0 05 50 81 A8 84 D4 04 6A 04 35 04 6A 84 D4 81 A8
-@FCE0 01 51 84 A3 01 51 81 A8 84 D4 04 6A 04 35 04 6A 85 D4 85 A9 04 53 84 A6 05 53 85 A9 84 D4 04 6A
-@FD48 FF FF FF FF 42 00 93 FF 42 00 81 C1 80 E0 84 E0 10 70 42 38 10 38 44 00 83 C0 02 0E 42 00 16 5E
-@FD68 83 B4 06 55 82 A2 93 FC 06 7A 06 49 84 98 10 11 91 A9 80 F6 91 A0 80 FF 90 B2 15 58 80 DB 01 0B
-@FD88 83 20 02 0F 42 AA 16 B4 83 AA 06 AA 82 AA 93 AA 06 AA 06 AA 83 C0 02 0E 42 00 16 5F 83 B4 06 55
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-@FDC8 80 DF 04 55 44 00 84 FF 84 AF 80 AE 80 BA 80 EA 00 01 00 5D 84 FF 80 DF 00 20 44 00 80 AD 00 04
-@FDE8 84 9A 84 CA 94 82 54 00 14 28 14 0A 90 8A 54 00 10 02 10 08 10 20 90 80
+@FB90 30 60 AA AA DE DE BC BC 82 A3 93 FC 06 7A 06 4A 82 A2 93 FC 06 7A 06 4A 12 60 97 60 02 60 42 60
+@FBB0 80 AD 00 04 84 9A 84 CA 84 AF 80 AE 80 BA 80 EA 01 01 01 01 00 AA 01 AA 00 AA 01 AA 51 AA 51 AA
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+@FC30 81 00 04 00 85 00 05 00 05 00 80 00 05 00 84 00 81 00 80 00 01 00 85 00 81 00 84 00 85 00 85 00
+@FC50 85 00 04 00 78 10 F0 10 65 4D CB 4D 33 2C 67 2C 80 00 F8 10 F0 10 E5 CD CB CD 33 2C 67 2C 81 00
+@FC70 E0 42 F0 42 96 34 CB 34 CE B0 67 B0 80 00 F8 90 F0 90 65 CD CB CD 33 AC 67 AC 81 00 E0 43 F0 43
+@FC90 97 34 CB 34 CE B0 67 B0 04 00 78 90 F0 90 E5 4D CB 4D B3 2C 67 2C 85 00 E1 42 F0 42 97 35 CB 35
+@FCB0 CE B0 67 B0 00 00 00 00 00 00 05 21 00 43 05 06 00 0D 01 1A 85 E1 84 C3 05 06 00 0D 01 1A 84 A0
+@FCD0 05 50 81 A8 84 D4 04 6A 04 35 04 6A 84 D4 81 A8 01 51 84 A3 01 51 81 A8 84 D4 04 6A 04 35 04 6A
+@FCF0 85 D4 85 A9 04 53 84 A6 05 53 85 A9 84 D4 04 6A
+@FD24 85 BF 80 BF 85 BF 85 BF E1 43 F0 43 97 35 CB 35 CF B1 67 B1 F0 21 CB 9A 67 58 80 BF 05 5F 85 AF
+@FD44 84 D7 00 6B FF FF FF FF 42 00 93 FF 42 00 81 C1 80 E0 84 E0 10 70 42 38 10 38 44 00 83 C0 02 0E
+@FD64 42 00 16 5E 83 B4 06 55 82 A2 93 FC 06 7A 06 49 84 98 10 11 91 A9 80 F6 91 A0 80 FF 90 B2 15 58
+@FD84 80 DB 01 0B 83 20 02 0F 42 AA 16 B4 83 AA 06 AA 82 AA 93 AA 06 AA 06 AA 83 C0 02 0E 42 00 16 5F
+@FDA4 83 B4 06 55 82 A3 93 FC 06 7A 06 4A 84 98 10 10 91 A9 80 F5 91 A0 80 FF 90 B1 15 58 80 DA 01 0A
+@FDC4 04 78 80 8F 80 DF 04 55 44 00 84 FF 84 AF 80 AE 80 BA 80 EA 00 01 00 5D 84 FF 80 DF 00 20 44 00
+@FDE4 80 AD 00 04 84 9A 84 CA 94 82 54 00 14 28 14 0A 90 8A 54 00 10 02 10 08 10 20 90 80
@FE30 FF FF FF FF 34 12 56 52 93 00 00 00 34 12 56 52 42 00 AF 83 34 12 56 52 93 00 FA 81 34 12 56 52
@FE50 93 00 4C 80 34 12 56 52 82 00 81 92 34 12 56 52 82 00 B5 A4 34 12 56 52 82 00 0C F7 34 12 56 52
@FE70 83 00 62 49 34 12 56 52 11 00 E7 4A 34 12 56 52 11 00 65 4C 34 12 56 52 00 00 32 26 34 12 56 52
Index: trunk/mem/dat_mov.vm
===================================================================
--- trunk/mem/dat_mov.vm (revision 3)
+++ trunk/mem/dat_mov.vm (revision 4)
@@ -1,40 +1,29 @@
@0000 C3 00 01
@00C0 00 18 FD
-@0100 31 00 00 3E FF AF 06 01 0E 02 16 04 1E 08 26 10
-@0110 2E 20 DD 21 AA AA FD 21 55 55 F5 C5 D5 E5 DD E5
-@0120 FD E5 3E F0 02 3E 0F 12 77 23 70 23 71 23 72 23
-@0130 73 23 74 23 75 23 36 3C 21 20 10 F5 C5 D5 E5 3E
-@0140 00 08 3E FF B7 D9 01 FD FE 11 F7 FB 21 DF EF F5
-@0150 C5 D5 E5 D9 F5 C5 D5 E5 EB F5 C5 D5 E5 D9 F5 C5
-@0160 D5 E5 EB F5 C5 D5 E5 D9 F5 C5 D5 E5 EB F5 C5 D5
-@0170 E5 D9 F5 C5 D5 E5 EB F5 C5 D5 E5 D9 40 49 52 64
-@0180 6D 7F F5 C5 D5 E5 78 41 4A 53 5C 65 6F F5 C5 D5
-@0190 E5 AF 06 01 0E 02 16 04 1E 08 26 10 2E 20 79 42
-@01A0 4B 54 5D 67 68 F5 C5 D5 E5 AF 06 01 0E 02 16 04
-@01B0 1E 08 26 10 2E 20 7A 43 4C 55 5F 60 69 F5 C5 D5
-@01C0 E5 AF 06 01 0E 02 16 04 1E 08 26 10 2E 20 7B 44
-@01D0 4D 57 58 61 6A F5 C5 D5 E5 AF 06 01 0E 02 16 04
-@01E0 1E 08 26 10 2E 20 7C 45 4F 50 59 62 6B F5 C5 D5
-@01F0 E5 AF 06 01 0E 02 16 04 1E 08 26 10 2E 20 7D 47
-@0200 48 51 5A 63 6C F5 C5 D5 E5 46 23 4E 23 56 23 5E
-@0210 23 F5 C5 D5 E5 66 E5 26 20 23 6E E5 0A F5 1A F5
-@0220 3A 88 78 F5 ED 4B 89 78 ED 5B 8B 78 2A 8D 78 DD
-@0230 2A 8F 78 FD 2A 91 78 ED 7B 93 78 32 95 78 ED 43
-@0240 96 78 ED 53 98 78 22 9A 78 DD 22 9C 78 FD 22 9E
-@0250 78 ED 73 A0 78 31 00 F0 F1 C1 D1 E1 DD E1 FD E1
-@0260 31 00 FE F5 C5 D5 E5 DD E5 FD E5 23 F9 F5 E5 DD
-@0270 F9 F5 DD E5 FD 23 FD F9 F5 FD E5 31 00 FD E3 33
-@0280 33 DD E3 33 33 FD E3 DD 7E 00 DD 46 01 DD 4E 02
-@0290 DD 56 03 DD 5E 04 DD 66 05 DD 6E 06 31 00 FD F5
-@02A0 C5 D5 E5 FD 7E 00 FD 46 01 FD 4E 02 FD 56 03 FD
-@02B0 5E 04 FD 66 05 FD 6E 06 F5 C5 D5 E5 DD 77 FF DD
-@02C0 70 FE DD 71 FD DD 72 FC DD 73 FB DD 74 FA DD 75
-@02D0 F9 DD 36 F8 0F FD 77 FF FD 70 FE FD 71 FD FD 72
-@02E0 FC FD 73 FB FD 74 FA FD 75 F9 FD 36 F8 0F AF 47
-@02F0 4F 57 5F 67 6F D9 47 4F 57 5F 67 6F D9 08 AF 3E
-@0300 FF ED 4F F5 C5 D5 E5 AF F5 ED 5F F5 C5 D5 E5 AF
-@0310 ED 4F 3E 55 ED 47 F5 C5 D5 E5 AF F5 ED 57 F5 FB
-@0320 ED 57 F5 F3 ED 57 F5 21 00 01 C3 C0 00
+@0100 31 00 00 3E FF AF 06 01 0E 02 16 04 1E 08 26 10 2E 20 DD 21 AA AA FD 21 55 55 F5 C5 D5 E5 DD E5
+@0120 FD E5 3E F0 02 3E 0F 12 77 23 70 23 71 23 72 23 73 23 74 23 75 23 36 3C 21 20 10 F5 C5 D5 E5 3E
+@0140 00 08 3E FF B7 D9 01 FD FE 11 F7 FB 21 DF EF F5 C5 D5 E5 D9 F5 C5 D5 E5 EB F5 C5 D5 E5 D9 F5 C5
+@0160 D5 E5 EB F5 C5 D5 E5 D9 F5 C5 D5 E5 EB F5 C5 D5 E5 D9 F5 C5 D5 E5 EB F5 C5 D5 E5 D9 40 49 52 64
+@0180 6D 7F F5 C5 D5 E5 78 41 4A 53 5C 65 6F F5 C5 D5 E5 AF 06 01 0E 02 16 04 1E 08 26 10 2E 20 79 42
+@01A0 4B 54 5D 67 68 F5 C5 D5 E5 AF 06 01 0E 02 16 04 1E 08 26 10 2E 20 7A 43 4C 55 5F 60 69 F5 C5 D5
+@01C0 E5 AF 06 01 0E 02 16 04 1E 08 26 10 2E 20 7B 44 4D 57 58 61 6A F5 C5 D5 E5 AF 06 01 0E 02 16 04
+@01E0 1E 08 26 10 2E 20 7C 45 4F 50 59 62 6B F5 C5 D5 E5 AF 06 01 0E 02 16 04 1E 08 26 10 2E 20 7D 47
+@0200 48 51 5A 63 6C F5 C5 D5 E5 46 23 4E 23 56 23 5E 23 F5 C5 D5 E5 66 E5 26 20 23 6E E5 0A F5 1A F5
+@0220 3A 88 78 F5 ED 4B 89 78 ED 5B 8B 78 2A 8D 78 DD 2A 8F 78 FD 2A 91 78 ED 7B 93 78 32 95 78 ED 43
+@0240 96 78 ED 53 98 78 22 9A 78 DD 22 9C 78 FD 22 9E 78 ED 73 A0 78 31 00 F0 F1 C1 D1 E1 DD E1 FD E1
+@0260 31 00 FE F5 C5 D5 E5 DD E5 FD E5 23 F9 F5 E5 DD F9 F5 DD E5 FD 23 FD F9 F5 FD E5 31 00 FD E3 33
+@0280 33 DD E3 33 33 FD E3 DD 7E 00 DD 46 01 DD 4E 02 DD 56 03 DD 5E 04 DD 66 05 DD 6E 06 31 00 FD F5
+@02A0 C5 D5 E5 FD 7E 00 FD 46 01 FD 4E 02 FD 56 03 FD 5E 04 FD 66 05 FD 6E 06 F5 C5 D5 E5 DD 77 FF DD
+@02C0 70 FE DD 71 FD DD 72 FC DD 73 FB DD 74 FA DD 75 F9 DD 36 F8 0F FD 77 FF FD 70 FE FD 71 FD FD 72
+@02E0 FC FD 73 FB FD 74 FA FD 75 F9 FD 36 F8 0F AF 47 4F 57 5F 67 6F D9 47 4F 57 5F 67 6F D9 08 AF 3E
+@0300 FF ED 4F F5 C5 D5 E5 AF F5 ED 5F F5 C5 D5 E5 AF ED 4F 3E 55 ED 47 F5 C5 D5 E5 AF F5 ED 57 F5 FB
+@0320 ED 57 F5 F3 ED 57 F5 AF 31 00 FC DD 21 00 00 FD 21 FF FF 01 AA AA 11 55 55 21 22 22 DD 26 A5 DD
+@0340 E5 DD 2E 57 DD E5 FD 26 BE FD E5 FD 2E 3D FD E5 F5 C5 D5 E5 DD 7C F5 DD 7D F5 FD 7C F5 FD 7D F5
+@0360 3E 05 DD 6F 3E FE FD 67 3E AD DD 67 3E 7E FD 6F DD E5 FD E5 F5 DD 44 DD 4D DD 68 DD 61 C5 DD E5
+@0380 FD 44 FD 4D FD 68 FD 61 C5 FD E5 DD 45 DD 4C DD 60 DD 69 C5 DD E5 FD 45 FD 4C FD 60 FD 69 C5 FD
+@03A0 E5 F5 DD 5C DD 55 DD 6B DD 62 D5 DD E5 FD 54 FD 5D FD 6A FD 63 D5 FD E5 DD 5D DD 54 DD 63 DD 6A
+@03C0 D5 DD E5 FD 55 FD 5C FD 62 FD 6B D5 FD E5 DD 7D DD 6C DD 67 DD E5 FD 7D FD 6C FD 67 FD E5 C5 E5
+@03E0 21 00 01 C3 C0 00
@2020 5A 69 78 87 96 A5
@5A69 B4
@6789 FF FD FB F9 F7 F5 F3
Index: trunk/mem/dat_movd.vm
===================================================================
--- trunk/mem/dat_movd.vm (revision 3)
+++ trunk/mem/dat_movd.vm (revision 4)
@@ -7,20 +7,16 @@
@ABC0 FF FF FF FF FF 0F 0D 0B 09 07 05 03 01
@BB40 44 BB 00 0F FF FF FF FF
@CC30 34 CC 00 0F FF FF FF FF
-@FCC8 FF FF FF FF FF FF 00 55 04 55 00 55 44 00 00 00
-@FCD8 00 00 00 00 44 55 00 00 00 00 00 00 80 FF 44 00
-@FCE8 00 00 00 00 00 00 44 FF 0D 0B 09 07 05 03 00 01
-@FCF8 F3 F5 F7 F9 FB FD 00 FF 34 CC 44 BB 56 AA FF FF
+@FBB8 22 22 7E FE FE 7E AD 05 7E FE 7E FE 05 AD AD 05 FE 7E 7E FE AD 05 AD 05 44 7E 7E FE 7E FE 05 AD
+@FBD8 05 AD FE 7E 7E FE AD 05 05 AD 44 7E 7E FE 05 AD 44 3D 44 BE 44 57 44 A5 22 22 55 55 AA AA 44 00
+@FBF8 3D BE FF BE 57 A5 00 A5
+@FCC8 FF FF FF FF FF FF 00 55 04 55 00 55 44 00 00 00 00 00 00 00 44 55 00 00 00 00 00 00 80 FF 44 00
+@FCE8 00 00 00 00 00 00 44 FF 0D 0B 09 07 05 03 00 01 F3 F5 F7 F9 FB FD 00 FF 34 CC 44 BB 56 AA FF FF
@FDF0 FF FF FF FF 55 AA 44 BB 33 CC 22 DD 11 EE 00 0F
-@FF58 FF FF 44 D2 44 C3 44 B4 A5 20 24 96 24 20 87 78
-@FF68 69 5A 44 20 20 20 20 20 20 20 44 20 10 20 10 20
-@FF78 10 20 44 10 08 20 10 08 20 10 44 08 10 08 04 20
-@FF88 10 08 44 04 04 02 20 10 08 04 44 02 01 20 10 08
-@FF98 04 02 84 01 20 10 08 04 02 01 84 FF DF EF F7 FB
-@FFA8 FD FE 84 FF F7 FB DF EF FD FE 84 FF 20 10 08 04
-@FFB8 02 01 84 FF 08 04 20 10 02 01 84 FF F7 FB DF EF
-@FFC8 FD FE 84 FF DF EF F7 FB FD FE 84 FF 08 04 20 10
-@FFD8 02 01 84 FF 20 10 08 04 02 01 84 FF DF EF F7 FB
-@FFE8 FD FE 84 FF 20 10 08 04 02 01 44 0F 55 55 AA AA
+@FF58 FF FF 44 D2 44 C3 44 B4 A5 20 24 96 24 20 87 78 69 5A 44 20 20 20 20 20 20 20 44 20 10 20 10 20
+@FF78 10 20 44 10 08 20 10 08 20 10 44 08 10 08 04 20 10 08 44 04 04 02 20 10 08 04 44 02 01 20 10 08
+@FF98 04 02 84 01 20 10 08 04 02 01 84 FF DF EF F7 FB FD FE 84 FF F7 FB DF EF FD FE 84 FF 20 10 08 04
+@FFB8 02 01 84 FF 08 04 20 10 02 01 84 FF F7 FB DF EF FD FE 84 FF DF EF F7 FB FD FE 84 FF 08 04 20 10
+@FFD8 02 01 84 FF 20 10 08 04 02 01 84 FF DF EF F7 FB FD FE 84 FF 20 10 08 04 02 01 44 0F 55 55 AA AA
@FFF8 20 10 08 04 02 01 44 00