OpenCores
URL https://opencores.org/ocsvn/y80e/y80e/trunk

Subversion Repositories y80e

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    /y80e
    from Rev 7 to Rev 8
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  •

Rev 7 → Rev 8

/trunk/asm/Tasm80.tab
274,8 → 274,8
LD (IY*),E 73FD 3 ZIX 1
LD (IY*),H 74FD 3 ZIX 1
LD (IY*),HL 2FFD 3 ZIX 4
LD (IY*),IX 3FFD 3 ZIX 4
LD (IY*),IY 3EFD 3 ZIX 4
LD (IY*),IX 3EFD 3 ZIX 4
LD (IY*),IY 3FFD 3 ZIX 4
LD (IY*),L 75FD 3 ZIX 1
LD (IY*),* 36FD 4 ZIX 1
LD (*),A 32 3 NOP 1
394,12 → 394,12
LD I,A 47ED 2 NOP 1
LD IX,(HL) 37ED 2 NOP 4
LD IX,(IX*) 37DD 3 ZIX 4
LD IX,(IY*) 37FD 3 ZIX 4
LD IX,(IY*) 31FD 3 ZIX 4
LD IX,(*) 2ADD 4 NOP 1
LD IX,* 21DD 4 NOP 1
LD IY,(HL) 36ED 2 NOP 4
LD IY,(IX*) 31DD 3 ZIX 4
LD IY,(IY*) 31FD 3 ZIX 4
LD IY,(IY*) 37FD 3 ZIX 4
LD IY,(*) 2AFD 4 NOP 1
LD IY,* 21FD 4 NOP 1
LD L,(HL) 6E 1 NOP 1
492,13 → 492,13
OR YL B5FD 2 NOP 1
OR * F6 2 NOP 1
 
OTD2 "" ACED 2 NOP 4
OUTD2 "" ACED 2 NOP 4
OTD2R "" BCED 2 NOP 4
OTDM "" 8BED 2 NOP 2
OTDMR "" 9BED 2 NOP 2
OTDR "" BBED 2 NOP 1
OTDRX "" CBED 2 NOP 4
OTI2 "" A4ED 2 NOP 4
OUTI2 "" A4ED 2 NOP 4
OTI2R "" B4ED 2 NOP 4
OTIM "" 83ED 2 NOP 2
OTIMR "" 93ED 2 NOP 2
/trunk/asm/ez8_ops.s
0,0 → 1,504
;**********************************************************************************
;* *
;* checks ez80 specific instructions *
;* *
;**********************************************************************************
aseg
 
org 00h
jp 01000h
 
org 038h
jp (hl)
org 066h
jp (ix)
org 80h
db 00h, 01h, 2dh, 03h, 04h, 05h, 06h, 07h
db 0fh, 1eh, 02h, 3ch, 4bh, 5ah, 69h, 78h
 
org 0c0h ;pattern finish location
nop
jr 0c0h
 
org 0d0h
db 071h, 018h, 006h, 005h, 002h, 003h, 004h, 0aah
 
org 0e0h
dw 0abcdh, 0fe10h, 03254h, 07698h
 
org 00140h
db 061h
 
org 00241h
db 002h
 
org 00342h
db 033h
 
org 00443h
db 0f4h
 
org 00544h
db 0e5h
 
org 00645h
db 0a6h
 
org 00165h
db 061h
 
org 00264h
db 002h
 
org 00363h
db 033h
 
org 00462h
db 0f4h
 
org 00561h
db 0e5h
 
org 00660h
db 0a6h
 
org 01000h
di
xor a
ld sp, 00000h
ld bc, 00123h
ld de, 04567h
ld hl, 0d000h
ld ix, 089abh
ld iy, 0cdefh
 
ld (hl),bc ;0123h @ d000h
inc hl
inc hl
ld (hl),de ;4567h @ d002h
inc hl
inc hl
ld (hl),hl ;d004h @ d004h
inc hl
inc hl
ld (hl),ix ;89abh @ d006h
inc hl
inc hl
ld (hl),iy ;cdefh @ d008h
 
pea ix+055h ;8a00h @ fffeh
pea iy-055h ;cd9ah @ fffch
push ix ;89abh @ fffah
push iy ;cdefh @ fff8h
 
ld ix, 0e080h
ld iy, 0dff0h
ld (ix-040h),bc ;0123h @ e040h
ld (ix-03eh),de ;4567h @ e042h
ld (ix-03ch),hl ;d008h @ e044h
ld (ix-03ah),ix ;e080h @ e046h
ld (ix-038h),iy ;dff0h @ e048h
ld (iy+050h),bc ;0123h @ e040h
ld (iy+052h),de ;4567h @ e042h
ld (iy+054h),hl ;d008h @ e044h
ld (iy+056h),ix ;e080h @ e046h
ld (iy+058h),iy ;dff0h @ e048h
 
ld ix,02004h
ld bc,(ix-04h)
ld de,(ix-02h)
ld hl,(ix+00h)
ld iy,(ix+02h)
ld ix,(ix+04h)
push bc ;dbach @ fff6h
push de ;5183h @ fff4h
push hl ;e800h @ fff2h
push iy ;7e4dh @ fff0h
push ix ;9a1fh @ ffeeh
 
ld bc,(hl)
inc hl
inc hl
ld de,(hl)
inc hl
inc hl
ld ix,(hl)
inc hl
inc hl
ld iy,(hl)
inc hl
inc hl
ld hl,(hl)
push bc ;0123h @ ffech
push de ;4567h @ ffeah
push hl ;cdefh @ ffe8h
push ix ;89abh @ ffe6h
push iy ;2006h @ ffe4h
 
ld bc,(iy-06h)
ld de,(iy-04h)
ld hl,(iy-02h)
ld ix,(iy+00h)
ld iy,(iy+02h)
push bc ;dbach @ ffe2h
push de ;5183h @ ffe0h
push hl ;e800h @ ffdeh
push ix ;7e4dh @ ffdch
push iy ;9a1fh @ ffdah
 
lea bc,ix-2
lea de,ix-1
lea hl,ix+0
lea iy,ix+1
lea ix,ix+2
push bc ;7e4bh @ ffd8h
push de ;7e4ch @ ffd6h
push hl ;7e4dh @ ffd4h
push ix ;7e4fh @ ffd2h
push iy ;7e4eh @ ffd0h
 
ld iy, 0aa00h
 
lea bc,iy-2
lea de,iy-1
lea hl,iy+0
lea ix,iy+1
lea iy,iy+2
push bc ;a9feh @ ffceh
push de ;a9ffh @ ffcah
push hl ;aa00h @ ffcch
push ix ;aa01h @ ffc8h
push iy ;aa02h @ ffc6h
push af ;0044h @ ffc4h
 
;---------
 
ld sp,0ff00h
xor a
ld hl, 0d700h
ld de, 00304h
ld bc, 006d0h
jp 011feh
org 011feh
inim ;read 71h @ 00d0h
;write 71h @ d700h
push af ;0006h @ fefeh
push bc ;05d1h @ fefch
push hl ;d701h @ fefah
jp 012feh
org 012feh
inimr ;read 18h @ 00d1h
;write 18h @ d701h
;read 06h @ 00d2h
;write 06h @ d702h
;read 05h @ 00d3h
;write 05h @ d703h
;read 02h @ 00d4h
;write 02h @ d704h
;read 03h @ 00d5h
;write 03h @ d705h
push af ;0046h @ fef8h
push bc ;00d6h @ fef6h
push hl ;d706h @ fef4h
ld b,1
jp 013ffh
org 013ffh
inimr ;read 04h @ 00d6h
;write 04h @ d706h
push af ;0046h @ fef2h
push bc ;00d7h @ fef0h
push hl ;d707h @ feeeh
inc b
jp 014ffh
org 014ffh
inim ;read aah @ 00d7h
;write aah @ d707h
push af ;0042h @ feech
push bc ;00d8h @ feeah
push hl ;d708h @ fee8h
ld hl, 0d707h
ld bc, 006d7h
jp 015feh
org 015feh
indm ;read aah @ 0037h
;write aah @ d707h
push af ;0002h @ fee6h
push bc ;05d6h @ fee4h
push hl ;d706h @ fee2h
jp 016feh
org 016feh
indmr ;read 04h @ 00d6h
;write 04h @ d706h
;read 03h @ 00d5h
;write 03h @ d705h
;read 02h @ 00d4h
;write 02h @ d704h
;read 05h @ 00d3h
;write 05h @ d703h
;read 06h @ 00d2h
;write 06h @ d702h
push af ;0042h @ fee0h
push bc ;00d1h @ fedeh
push hl ;d701h @ fedch
inc b
xor 0aah
jp 017ffh
org 017ffh
indmr ;read 18h @ 00d1h
;write 18h @ d701h
push af ;aac6h @ fedah
push bc ;00d0h @ fed8h
push hl ;d700h @ fed6h
inc b
jp 018ffh
org 018ffh
indm ;read 71h @ 00d0h
;write 71h @ d700h
push af ;aa42h @ fed4h
push bc ;00cfh @ fed2h
push de ;0304h @ fed0h
push hl ;d6ffh @ feceh
 
;---------
ld sp, 0fe00h
xor a
ld hl, 0d901h
ld bc, 00241h
jp 019feh
org 019feh
ind2 ;read 60h @ 0041h
;write 60h @ d901h
push af ;0006h @ fdfeh
push bc ;01d0h @ fdfch
push hl ;d900h @ fdfah
ld a, 055h
jp 01affh
org 01affh
ind2 ;read 02h @ 0040h
;write 02h @ d900h
push af ;5546h @ fdf8h
push bc ;00cfh @ fdf6h
push hl ;d8ffh @ fdf4h
 
xor a
ld hl,0d804h
ld bc,00264h
jp 01bfeh
org 01bfeh
ini2 ;read 02h @ 0064h
;write 02h @ d804h
push af ;0006h @ fdf2h
push bc ;0165h @ fdf0h
push hl ;d805h @ fdeeh
xor 0aah
jp 01cffh
org 01cffh
ini2 ;read 61h @ 0065h
;write 61h @ d805h
push af ;aac6h @ fdech
push bc ;0066h @ fdeah
push hl ;d806h @ fde8h
push de ;0304h @ fde6h
ld bc, 0003h
ld hl, 0a001h
ld de, 05002h
jp 01dfeh
org 01dfeh
ini2r ;read 01h @ 5002h
;write 01h @ a001h
;read 02h @ 5003h
;write 02h @ a002h
;read 03h @ 5004h
;write 03h @ a003h
push af ;aac6h @ fde4h
push bc ;0000h @ fde2h
push hl ;a004h @ fde0h
push de ;5005h @ fddeh
ld bc, 0004h
ld hl, 09ffeh
ld de, 04ffdh
jp 01efeh
org 01efeh
ind2r ;read 04h @ 4ffdh
;write 04h @ 9ffeh
;read 05h @ 4ffch
;write 05h @ 9ffdh
;read 06h @ 4ffbh
;write 06h @ 9ffch
;read 07h @ 4ffah
;write 07h @ 9ffbh
push af ;aac6h @ fddch
push bc ;0000h @ fddah
push hl ;9ffah @ fdd8h
push de ;4ff9h @ fdd6h
 
 
;---------
ld sp, 0fd00h
xor a
ld hl, 04901h
ld bc, 00231h
outd2 ;read 02h @ 4901h
;write 02h @ 0231h
push af ;0006h @ fcfeh
push bc ;0130h @ fcfch
push hl ;4900h @ fcfah
ld a, 055h
outd2 ;read 61h @ 4900h
;write 61h @ 0130h
push af ;5546h @ fcf8h
push bc ;002fh @ fcf6h
push hl ;48ffh @ fcf4h
 
xor a
ld hl,04804h
ld bc,00274h
outi2 ;read 02h @ 4804h
;write 02h @ 0274h
push af ;0006h @ fcf2h
push bc ;0175h @ fcf0h
push hl ;4805h @ fceeh
xor 0aah
outi2 ;read 61h @ 4805h
;write 61h @ 0175h
push af ;aac6h @ fcech
push bc ;0076h @ fceah
push hl ;4806h @ fce8h
push de ;4ff9h @ fce6h
ld bc, 0003h
ld de, 0a001h
ld hl, 05002h
oti2r ;read 01h @ 5002h
;write 01h @ a001h
;read 02h @ 5003h
;write 02h @ a002h
;read 03h @ 5004h
;write 03h @ a003h
push af ;aac6h @ fce4h
push bc ;0000h @ fce2h
push de ;a004h @ fce0h
push hl ;5005h @ fcdeh
ld bc, 0004h
ld de, 09ffeh
ld hl, 04ffdh
otd2r ;read 04h @ 4ffdh
;write 04h @ 9ffeh
;read 05h @ 4ffch
;write 05h @ 9ffdh
;read 06h @ 4ffbh
;write 06h @ 9ffch
;read 07h @ 4ffah
;write 07h @ 9ffbh
push af ;aac6h @ fcdch
push bc ;0000h @ fcdah
push de ;9ffah @ fcd8h
push hl ;4ff9h @ fcd6h
 
;---------
 
ld sp, 0fc00h
and a ;AF = aa94h
ld de, 0da15h
ld hl, 049feh + 3
ld bc, 4
otdrx ;read eeh @ 4a01h
;write eeh @ da15h
;read eeh @ 4a00h
;write eeh @ da15h
;read eeh @ 49ffh
;write eeh @ da15h
;read eeh @ 49feh
;write eeh @ da15h
push af ;aad6h @ fbfeh
push bc ;0000h @ fbfch
push de ;da15h @ fbfah
push hl ;49fdh @ fbf8h
 
inc de
inc a ;a = abh
ld hl, 04afeh
ld bc, 4
otirx ;read 11h @ 4afeh
;write 11h @ da16h
;read 11h @ 4affh
;write 11h @ da16h
;read 11h @ 4b00h
;write 11h @ da16h
;read 11h @ 4b01h
;write 11h @ da16h
push af ;abc2h @ fbf6h
push bc ;0000h @ fbf4h
push de ;da16h @ fbf2h
push hl ;4b02h @ fbf0h
 
and a
ld hl, 09dfeh + 3
ld de, 0e732h
ld bc, 4
indrx ;read 77h @ e732h
;write 77h @ 9e01h
;read 77h @ e732h
;write 77h @ 9e00h
;read 77h @ e732h
;write 77h @ 9dffh
;read 77h @ e732h
;write 77h @ 9dfeh
push af ;abd2h @ fbeeh
push bc ;0000h @ fbech
push de ;e732h @ fbeah
push hl ;9dfdh @ fbe8h
 
inc de
dec a ;A = aah
ld hl, 09efeh
ld bc, 4
inirx ;read cch @ e733h
;write cch @ 9efeh
;read cch @ e733h
;write cch @ 9effh
;read cch @ e733h
;write cch @ 9f00h
;read cch @ e733h
;write cch @ 9f01h
push af ;aac2h @ fbe6h
push bc ;0000h @ fbe4h
push de ;e733h @ fbe2h
push hl ;9f02h @ fbe0h
 
ld hl,0100h
jp 0c0h
 
org 02000h
dw 0dbach, 05183h, 0e800h, 07e4dh, 09a1fh
 
org 04800h
db 0a6h, 0a5h, 0f4h, 022h, 002h, 061h ;for ini2
 
org 04900h
db 061h, 002h, 022h, 0f4h, 0a5h, 0a6h ;for ind2
org 049feh
db 0eeh, 0eeh, 0eeh, 0eeh
org 04afeh
db 011h, 011h, 011h, 011h
 
org 04fe8h
db 0ffh, 0ffh, 0a8h, 027h, 026h, 01ch, 01bh, 01ah
db 019h, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 043h, 00ah
db 009h, 008h, 007h, 006h, 005h, 004h, 0ffh, 0aah
db 055h, 0ffh, 001h, 002h, 003h, 00bh, 00ch, 00dh
db 00eh, 00fh, 0ffh, 0ffh, 0ffh, 0ffh, 01dh, 01eh
db 01fh, 020h, 0a1h, 022h, 023h, 022h, 025h, 0ffh
 
org 0e732h
db 077h, 0cch
 
org 0e800h
dw 00123h, 04567h, 089abh, 02006h, 0cdefh
 
end
/trunk/asm/180_ops.s
97,11 → 97,15
xor a
ld hl, 02000h
ld bc, 00630h
jp 001feh
org 001feh
otim ;read 71h @ 2000h
;write 71h @ 0030h
push af ;0006h @ fcd0h
push bc ;0531h @ fcceh
push hl ;2001h @ fccch
jp 002feh
org 002feh
otimr ;read 18h @ 2001h
;write 18h @ 0031h
;read 06h @ 2002h
116,6 → 120,8
push bc ;0036h @ fcc8h
push hl ;2006h @ fcc6h
ld b,1
jp 003ffh
org 003ffh
otimr ;read 04h @ 2006h
;write 04h @ 0036h
push af ;0046h @ fcc4h
122,6 → 128,8
push bc ;0037h @ fcc2h
push hl ;2007h @ fcc0h
inc b
jp 004ffh
org 004ffh
otim ;read aah @ 2007h
;write aah @ 0037h
push af ;0042h @ fcbeh
129,11 → 137,15
push hl ;2008h @ fcbah
ld hl, 02007h
ld bc, 00637h
jp 005feh
org 005feh
otdm ;read aah @ 2007h
;write aah @ 0037h
push af ;0002h @ fcb8h
push bc ;0536h @ fcb6h
push hl ;2006h @ fcb4h
jp 006feh
org 006feh
otdmr ;read 04h @ 2006h
;write 04h @ 0036h
;read 03h @ 2005h
149,6 → 161,8
push hl ;2001h @ fcaeh
inc b
xor 0aah
jp 007ffh
org 007ffh
otdmr ;read 18h @ 2001h
;write 18h @ 0031h
push af ;aac6h @ fcach
155,6 → 169,8
push bc ;0030h @ fcaah
push hl ;2000h @ fca8h
inc b
jp 008ffh
org 008ffh
otdm ;read 71h @ 2000h
;write 71h @ 0030h
push af ;aa42h @ fca6h
/trunk/asm/ez8_opsd.s
0,0 → 1,112
;**********************************************************************************
;* *
;* ez8_ops compare data *
;* *
;**********************************************************************************
org 00130h
db 061h
 
org 00231h
db 002h
 
org 00332h
db 033h
 
org 00433h
db 0f4h
 
org 00534h
db 0e5h
 
org 00635h
db 0a6h
 
org 00175h
db 061h
 
org 00274h
db 002h
 
org 00373h
db 033h
 
org 00472h
db 0f4h
 
org 00571h
db 0e5h
 
org 00670h
db 0a6h
 
org 09dfeh
db 077h, 077h, 077h, 077h ;09f00h
org 09efeh
db 0cch, 0cch, 0cch, 0cch ;09f04h
 
org 09ff8h
db 0ffh, 0ffh, 0ffh, 007h, 006h, 005h, 004h, 0aah ;09ff8h
db 055h, 001h, 002h, 003h, 0ffh, 0ffh, 0ffh, 0ffh ;0a000h
 
 
org 0d000h
dw 00123h, 04567h, 0d004h, 089abh, 0cdefh
 
org 0d700h
db 071h, 018h, 006h, 005h, 002h, 003h, 004h, 0aah ;for inim/indm/inimr/indmr
 
org 0d800h
db 0a6h, 0a5h, 0f4h, 022h, 002h, 061h ;for ini2
 
org 0d900h
db 061h, 002h, 022h, 0f4h, 0a5h, 0a6h ;for ind2
org 0da15h
db 0eeh, 011h
 
org 0e040h
dw 00123h, 04567h, 0d008h, 0e080h, 0dff0h
 
org 0fbe0h
dw 09f02h, 0e733h, 00000h, 0aac2h ;fbe0h
dw 09dfdh, 0e732h, 00000h, 0abd2h ;fbe8h
dw 04b02h, 0da16h, 00000h, 0abc2h ;fbf0h
dw 049fdh, 0da15h, 00000h, 0aad6h ;fbf8h
 
org 0fcd6h
dw 04ff9h
dw 09ffah, 00000h, 0aac6h, 05005h ;fcd8h
dw 0a004h, 00000h, 0aac6h, 04ff9h ;fce0h
dw 04806h, 00076h, 0aac6h, 04805h ;fce8h
dw 00175h, 00006h, 048ffh, 0002fh ;fcf0h
dw 05546h, 04900h, 00130h, 00006h ;fcf8h
 
org 0fdd6h
dw 04ff9h
dw 09ffah, 00000h, 0aac6h, 05005h ;fdd8h
dw 0a004h, 00000h, 0aac6h, 00304h ;fde0h
dw 0d806h, 00066h, 0aac6h, 0d805h ;fde8h
dw 00165h, 00006h, 0d8ffh, 0003fh ;fdf0h
dw 05546h, 0d900h, 00140h, 00006h ;fdf8h
 
org 0feceh
dw 0d6ffh
dw 00304h, 000cfh, 0aa42h, 0d700h ;fed0h
dw 000d0h, 0aac6h, 0d701h, 000d1h ;fed8h
dw 00042h, 0d706h, 005d6h, 00002h ;fee0h
dw 0d708h, 000d8h, 00042h, 0d707h ;fee8h
dw 000d7h, 00046h, 0d706h, 000d6h ;fef0h
dw 00046h, 0d701h, 005d1h, 00006h ;fef8h
 
org 0ffc4h
dw 00044h, 0aa02h
dw 0aa01h, 0aa00h, 0a9ffh, 0a9feh ;ffc8h
dw 07e4eh, 07e4fh, 07e4dh, 07e4ch ;ffd0h
dw 07e4bh, 09a1fh, 07e4dh, 0e800h ;ffd8h
dw 05183h, 0dbach, 02006h, 089abh ;ffe0h
dw 0cdefh, 04567h, 00123h, 09a1fh ;ffe8h
dw 07e4dh, 0e800h, 05183h, 0dbach ;fff0h
dw 0cdefh, 089abh, 0cd9ah, 08a00h ;fff8h
end
/trunk/asm/build.bat Cannot display: file marked as a binary type. svn:mime-type = application/x-msdos-program
/trunk/rtl/defines.v
3,7 → 3,7
/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
/** **/
/** define file to make the code more readable Rev 0.0 06/13/2012 **/
/** define file to make the code more readable Rev 0.0 06/18/2012 **/
/** **/
/*******************************************************************************************/
 
288,6 → 288,7
`define ALUB_DINH 13'h0101 //Select data input register high byte
`define ALUB_IO 13'h0200 //Select i/o address
`define ALUB_TMP 13'h0400 //Select TMP register
`define ALUB_TMPH 13'h0401 //Select TMP register high byte
`define ALUB_PC 13'h1800 //Select PC register
`define ALUB_PCH 13'h1801 //Select PC register high byte
 
/trunk/rtl/control.v
3,7 → 3,7
/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
/** **/
/** control module Rev 0.0 06/13/2012 **/
/** control module Rev 0.0 06/18/2012 **/
/** **/
/*******************************************************************************************/
module control (add_sel, alua_sel, alub_sel, aluop_sel, cflg_en, di_ctl, do_ctl, ex_af_pls,
109,7 → 109,7
reg [`TFLG_IDX:0] tflg_ctl; /* temp flag control */
reg [`TTYPE_IDX:0] tran_sel; /* transaction type */
reg [`WREG_IDX:0] wr_addr; /* register write address bus */
 
/*****************************************************************************************/
/* */
/* refresh register control */
474,129 → 474,147
`IF2B: state_nxt = `sDEC2;
`DEC2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b001000110110,
12'b001000000110,
12'b001000001110,
12'b001000010110,
12'b001000011110,
12'b001000100110,
12'b001000101110,
12'b001000111110,
12'b001001xxx110,
12'b001010xxx110,
12'b001011xxx110,
12'b010011100001,
12'b010011100011,
12'b010011100101,
12'b010111100001,
12'b010111100011,
12'b010111100101,
12'b1xxx00110100,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01100111,
12'b1xxx01101111,
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx10000011,
12'b1xxx10001011,
12'b1xxx10010011,
12'b1xxx10011011,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011: state_nxt = `sADR2;
12'b010010001100,
12'b010010001101,
12'b010110001100,
12'b010110001101,
12'b010010000100,
12'b010010000101,
12'b010110000100,
12'b010110000101,
12'b010010100100,
12'b010010100101,
12'b010110100100,
12'b010110100101,
12'b010010111100,
12'b010010111101,
12'b010110111100,
12'b010110111101,
12'b010000100101,
12'b010000101101,
12'b010100100101,
12'b010100101101,
12'b010000100100,
12'b010000101100,
12'b010100100100,
12'b010100101100,
12'b0100011000xx,12'b01000110010x,12'b010001100111,
12'b0100011010xx,12'b01000110110x,12'b010001101111,
12'b0101011000xx,12'b01010110010x,12'b010101100111,
12'b0101011010xx,12'b01010110110x,12'b010101101111,
12'b0100010xx100,12'b01000110x100,12'b010001111100,
12'b0100010xx101,12'b01000110x101,12'b010001111101,
12'b0101010xx100,12'b01010110x100,12'b010101111100,
12'b0101010xx101,12'b01010110x101,12'b010101111101,
12'b010010110100,
12'b010010110101,
12'b010110110100,
12'b010110110101,
12'b010010011100,
12'b010010011101,
12'b010110011100,
12'b010110011101,
12'b010010010100,
12'b010010010101,
12'b010110010100,
12'b010110010101,
12'b010010101100,
12'b010010101101,
12'b010110101100,
12'b010110101101,
12'b001000110xxx,
12'b001000000xxx,
12'b001000001xxx,
12'b001000010xxx,
12'b001000011xxx,
12'b001000100xxx,
12'b001000101xxx,
12'b001000111xxx,
12'b001001xxxxxx,
12'b001010xxxxxx,
12'b001011xxxxxx,
12'b010000100011,
12'b010000101011,
12'b010000xx1001,
12'b010011111001,
12'b010100100011,
12'b010100101011,
12'b010100xx1001,
12'b010111111001,
12'b1xxx000xx100,12'b1xxx0010x100,12'b1xxx00111100,
12'b1xxx01000100,
12'b1xxx01000110,
12'b1xxx01000111,
12'b1xxx01001111,
12'b1xxx01010110,
12'b1xxx01010111,
12'b1xxx01011110,
12'b1xxx01011111,
12'b1xxx01xx0010,
12'b1xxx01xx1010,
12'b1xxx01xx1100: state_nxt = `sIF1B;
12'b001000000110,
12'b001000001110,
12'b001000010110,
12'b001000011110,
12'b001000100110,
12'b001000101110,
12'b001000110110,
12'b001000111110,
12'b001001xxx110,
12'b001010xxx110,
12'b001011xxx110,
12'b010011100001,
12'b010011100011,
12'b010011100101,
12'b010111100001,
12'b010111100011,
12'b010111100101,
12'b1xxx00110100,
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00111110,
12'b1xxx00111111,
12'b1xxx00xx0111,
12'b1xxx00xx1111,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01100111,
12'b1xxx01101111,
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: state_nxt = `sADR2;
12'b001000000xxx,
12'b001000001xxx,
12'b001000010xxx,
12'b001000011xxx,
12'b001000100xxx,
12'b001000101xxx,
12'b001000110xxx,
12'b001000111xxx,
12'b001001xxxxxx,
12'b001010xxxxxx,
12'b001011xxxxxx,
12'b010000100011,
12'b010000100100,
12'b010000100101,
12'b010000101011,
12'b010000101100,
12'b010000101101,
12'b010000xx1001,
12'b01000110x0xx,12'b01000110x10x,12'b01000110x111,
12'b0100010xx10x,12'b01000110x10x,12'b01000111110x,
12'b010010000100,
12'b010010000101,
12'b010010001100,
12'b010010001101,
12'b010010010100,
12'b010010010101,
12'b010010011100,
12'b010010011101,
12'b010010100100,
12'b010010100101,
12'b010010101100,
12'b010010101101,
12'b010010110100,
12'b010010110101,
12'b010010111100,
12'b010010111101,
12'b010011111001,
12'b010100100011,
12'b010100100100,
12'b010100100101,
12'b010100101011,
12'b010100101100,
12'b010100101101,
12'b010100xx1001,
12'b01010110x0xx,12'b01010110x10x,12'b01010110x111,
12'b0101010xx10x,12'b01010110x10x,12'b01010111110x,
12'b010110000100,
12'b010110000101,
12'b010110001100,
12'b010110001101,
12'b010110010100,
12'b010110010101,
12'b010110011100,
12'b010110011101,
12'b010110100100,
12'b010110100101,
12'b010110101100,
12'b010110101101,
12'b010110110100,
12'b010110110101,
12'b010110111100,
12'b010110111101,
12'b010111111001,
12'b1xxx00xxx100,
12'b1xxx01000100,
12'b1xxx01000110,
12'b1xxx01000111,
12'b1xxx01001111,
12'b1xxx01010110,
12'b1xxx01010111,
12'b1xxx01011110,
12'b1xxx01011111,
12'b1xxx01xx1100,
12'b1xxx01xx0010,
12'b1xxx01xx1010: state_nxt = `sIF1B;
12'b010011101001,
12'b010111101001,
12'b1xxx01110110: state_nxt = `sPCO;
605,76 → 623,54
end
`OF1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011010011,
12'b000011011011,
12'b010000110100,
12'b010000110101,
12'b010001110xxx,
12'b010001xxx110,
12'b010010000110,
12'b010010001110,
12'b010010010110,
12'b010010011110,
12'b010010100110,
12'b010010101110,
12'b010010110110,
12'b010010111110,
12'b010100110100,
12'b010100110101,
12'b010101110xxx,
12'b010101xxx110,
12'b010110000110,
12'b010110001110,
12'b010110010110,
12'b010110011110,
12'b010110100110,
12'b010110101110,
12'b010110110110,
12'b010110111110,
12'b1xxx00xxx000,
12'b1xxx00xxx001,
12'b1xxx01110100: state_nxt = `sADR1;
12'b010000100110,
12'b010000101110,
12'b010100100110,
12'b010100101110,
12'b0000000xx110,12'b00000010x110,12'b000000111110,
12'b000011000110,
12'b000011001110,
12'b000011010110,
12'b000011011110,
12'b000011100110,
12'b000011101110,
12'b000011110110,
12'b000011111110,
12'b0000000xx110,12'b00000010x110,12'b000000111110,
12'b000011000110,
12'b000011001110,
12'b000011010110,
12'b000011011110,
12'b000011100110,
12'b000011101110,
12'b000011110110,
12'b000011111110,
12'b010000100110,
12'b010000101110,
12'b010100100110,
12'b010100101110,
12'b1xxx00110010,
12'b1xxx00110011,
12'b1xxx00xx0010,
12'b1xxx00xx0011,
12'b1xxx01010100,
12'b1xxx01010101,
12'b1xxx01100100: state_nxt = `sIF1A;
12'b000000100000: state_nxt = ( !zero_bit) ? `sPCA : `sIF1A;
12'b000000101000: state_nxt = ( zero_bit) ? `sPCA : `sIF1A;
12'b000000110000: state_nxt = (!carry_bit) ? `sPCA : `sIF1A;
12'b000000111000: state_nxt = ( carry_bit) ? `sPCA : `sIF1A;
12'b000000100010,
12'b000000101010,
12'b000000110010,
12'b000000111010,
12'b000000xx0001,
12'b000011000011,
12'b000011001101,
12'b000011xxx010,
12'b000011xxx100,
12'b010000100001,
12'b010000100010,
12'b010000101010,
12'b010000110110,
12'b010100100001,
12'b010100100010,
12'b010100101010,
12'b010100110110,
12'b1xxx01xx0011,
12'b011xxxxxxxxx: state_nxt = `sIF3A; //DD/FD + CB
12'b000000100010,
12'b000000101010,
12'b000000110010,
12'b000000111010,
12'b000000xx0001,
12'b000011000011,
12'b000011001101,
12'b000011xxx010,
12'b000011xxx100,
12'b010000100001,
12'b010000100010,
12'b010000101010,
12'b010000110110,
12'b010100100001,
12'b010100100010,
12'b010100101010,
12'b010100110110,
12'b1xxx01xx0011,
12'b1xxx01xx1011: state_nxt = `sOF2A;
12'b000000010000,
12'b000000011000: state_nxt = `sPCA;
12'b000000110110: state_nxt = `sWR2A;
default: state_nxt = `sIF3A;
default: state_nxt = `sADR1;
endcase
end
`OF2A: state_nxt = `sOF2B;
711,45 → 707,84
`ADR1: state_nxt = `sADR2;
`ADR2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000101010,
12'b000011001001,
12'b000011100011,
12'b000011xxx000,
12'b000011xx0001,
12'b0001xxxxxxxx,
12'b010000101010,
12'b010011100001,
12'b010011100011,
12'b010100101010,
12'b010111100001,
12'b010111100011,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01xx1011,
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011: state_nxt = `sRD1A;
12'b000000100010,
12'b000011xxx111,
12'b000011xx0101,
12'b010000100010,
12'b010011100101,
12'b010100100010,
12'b010111100101,
12'b000000101010,
12'b000011001001,
12'b000011100011,
12'b000011xxx000,
12'b000011xx0001,
12'b0001xxxxxxxx,
12'b010000101010,
12'b010000110001,
12'b010000110111,
12'b010000xx0111,
12'b010011100001,
12'b010011100011,
12'b010100101010,
12'b010100110001,
12'b010100110111,
12'b010100xx0111,
12'b010111100001,
12'b010111100011,
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00xx0111,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01xx1011,
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: state_nxt = `sRD1A;
12'b000000100010,
12'b000011xxx111,
12'b000011xx0101,
12'b010000100010,
12'b010000111110,
12'b010000111111,
12'b010000xx1111,
12'b010011100101,
12'b010100100010,
12'b010100111110,
12'b010100111111,
12'b010100xx1111,
12'b010111100101,
12'b1xxx00111110,
12'b1xxx00111111,
12'b1xxx00xx1111,
12'b1xxx01100101,
12'b1xxx01100110,
12'b1xxx01xx0011: state_nxt = `sWR1A;
12'b000000000010,
12'b000000010010,
770,19 → 805,38
12'b1xxx10101001,
12'b1xxx10110001,
12'b1xxx10111001: state_nxt = `sBLK1;
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011: state_nxt = `sWR1A;
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: state_nxt = `sWR1A;
default: state_nxt = `sRD2A;
endcase
end
793,56 → 847,67
12'b1xxx10101001,
12'b1xxx10110001,
12'b1xxx10111001: state_nxt = `sBLK1;
12'b000000001010,
12'b000000011010,
12'b000000101010,
12'b000000111010,
12'b000001xxxxxx,
12'b000001xxx110,
12'b000010000110,
12'b000010000xxx,
12'b000010001110,
12'b000010001xxx,
12'b000010010110,
12'b000010011110,
12'b000010100110,
12'b000010100xxx,
12'b000010101110,
12'b000010110110,
12'b000010110xxx,
12'b000010111110,
12'b000010111xxx,
12'b000011011011,
12'b000011xx0001,
12'b001001xxx110,
12'b001001xxxxxx,
12'b010000101010,
12'b010001xxx110,
12'b010010000110,
12'b010010001110,
12'b010010010110,
12'b010010011110,
12'b010010100110,
12'b010010101110,
12'b010010110110,
12'b010010111110,
12'b010011100001,
12'b010100101010,
12'b010101xxx110,
12'b010110000110,
12'b010110001110,
12'b010110010110,
12'b010110011110,
12'b010110100110,
12'b010110101110,
12'b010110110110,
12'b010110111110,
12'b010111100001,
12'b011001xxx110,
12'b011101xxx110,
12'b1xxx00xxx000,
12'b1xxx0x110100,
12'b1xxx01xxx000,
12'b000000001010,
12'b000000011010,
12'b000000101010,
12'b000000111010,
12'b000001xxxxxx,
12'b000001xxx110,
12'b000010000110,
12'b000010000xxx,
12'b000010001110,
12'b000010001xxx,
12'b000010010110,
12'b000010011110,
12'b000010100110,
12'b000010100xxx,
12'b000010101110,
12'b000010110110,
12'b000010110xxx,
12'b000010111110,
12'b000010111xxx,
12'b000011011011,
12'b000011xx0001,
12'b001001xxx110,
12'b001001xxxxxx,
12'b010000101010,
12'b010000110001,
12'b010000110111,
12'b010000xx0111,
12'b010001xxx110,
12'b010010000110,
12'b010010001110,
12'b010010010110,
12'b010010011110,
12'b010010100110,
12'b010010101110,
12'b010010110110,
12'b010010111110,
12'b010011100001,
12'b010100101010,
12'b010100110001,
12'b010100110111,
12'b010100xx0111,
12'b010101xxx110,
12'b010110000110,
12'b010110001110,
12'b010110010110,
12'b010110011110,
12'b010110100110,
12'b010110101110,
12'b010110110110,
12'b010110111110,
12'b010111100001,
12'b011001xxx110,
12'b011101xxx110,
12'b1xxx00110100,
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00xx0111,
12'b1xxx00xxx000,
12'b1xxx00xxx100,
12'b1xxx01110100,
12'b1xxx01xxx000,
12'b1xxx01xx1011: state_nxt = `sIF1A;
12'b000011001001,
12'b000011xxx000,
858,20 → 923,38
`WR1A: state_nxt = `sWR1B;
`WR1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx1000x011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011: state_nxt = `sIF1A;
12'b1xxx1001x011,
12'b1xxx10110010,
12'b1xxx10111010,
12'b1xxx10110011,
12'b1xxx10111011,
12'b1xxx10110000,
12'b1xxx10111000: state_nxt = (tflg_reg || intr_reg || dmar_reg) ? `sPCA : `sRD2A;
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10101100: state_nxt = `sIF1A;
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: state_nxt = (tflg_reg || intr_reg || dmar_reg) ? `sPCA : `sRD2A;
default: state_nxt = `sWR2A;
endcase
end
878,13 → 961,30
`WR2A: state_nxt = `sWR2B;
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx1001x011,
12'b1xxx10110010,
12'b1xxx10111010,
12'b1xxx10110011,
12'b1xxx10111011,
12'b1xxx10110000,
12'b1xxx10111000: state_nxt = (tflg_reg || intr_reg || dmar_reg) ? `sPCA : `sRD2A;
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: state_nxt = (tflg_reg || intr_reg || dmar_reg) ? `sPCA : `sRD2A;
default: state_nxt = `sIF1A;
endcase
end
899,7 → 999,7
`PCA: state_nxt = `sPCO;
`PCO: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000001110110: state_nxt = `sHLTA;
12'b000001110110,
12'b1xxx01110110: state_nxt = `sHLTA;
default: state_nxt = `sIF1A;
endcase
928,26 → 1028,54
`IF2B: tran_sel = `TRAN_IF;
`OF1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000010000,
12'b000000011000,
12'b000011010011,
12'b000011011011,
12'b010x00110100,
12'b010x00110101,
12'b010x011100xx,
12'b010x0111010x,
12'b010x01110111,
12'b010x010xx110,
12'b010x0110x110,
12'b010x01111110,
12'b010x10000110,
12'b010x10001110,
12'b010x10010110,
12'b010x10011110,
12'b010x10100110,
12'b010x10101110,
12'b010x10110110,
12'b010x10111110: tran_sel = `TRAN_IDL;
12'b000000010000,
12'b000000011000,
12'b000011010011,
12'b000011011011,
12'b010000110001,
12'b010000110100,
12'b010000110101,
12'b010000110111,
12'b010000111110,
12'b010000111111,
12'b010000xx0111,
12'b010000xx1111,
12'b010001110xxx,
12'b010001xxx110,
12'b010010000110,
12'b010010001110,
12'b010010010110,
12'b010010011110,
12'b010010100110,
12'b010010101110,
12'b010010110110,
12'b010010111110,
12'b010100110001,
12'b010100110100,
12'b010100110101,
12'b010100110111,
12'b010100111110,
12'b010100111111,
12'b010100xx0111,
12'b010100xx1111,
12'b010101110xxx,
12'b010101xxx110,
12'b010110000110,
12'b010110001110,
12'b010110010110,
12'b010110011110,
12'b010110100110,
12'b010110101110,
12'b010110110110,
12'b010110111110,
12'b1xxx00110010,
12'b1xxx00110011,
12'b1xxx00xx0010,
12'b1xxx00xx0011,
12'b1xxx01010100,
12'b1xxx01010101,
12'b1xxx01100101,
12'b1xxx01100110: tran_sel = `TRAN_IDL;
12'b000000100000: tran_sel = ( zero_bit) ? `TRAN_IF : `TRAN_IDL;
12'b000000101000: tran_sel = ( !zero_bit) ? `TRAN_IF : `TRAN_IDL;
12'b000000110000: tran_sel = ( carry_bit) ? `TRAN_IF : `TRAN_IDL;
986,28 → 1114,40
`IF3B: tran_sel = `TRAN_MEM;
`ADR2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011010011,
12'b000011011011,
12'b1xxx00xxx000,
12'b1xxx00xxx001,
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx01110100,
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010: tran_sel = `TRAN_IO;
12'b000011001001,
12'b000011xxx000,
12'b000011xxx111,
12'b000011xx0001,
12'b000011xx0101,
12'b010011100001,
12'b010011100101,
12'b010111100001,
12'b010111100101,
12'b1xxx01000101,
12'b1xxx01001101: tran_sel = `TRAN_STK;
12'b000011010011,
12'b000011011011,
12'b1xxx00xxx000,
12'b1xxx00xxx001,
12'b1xxx01110100,
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010,
12'b1xxx11000010,
12'b1xxx11001010: tran_sel = `TRAN_IO;
12'b000011001001,
12'b000011xxx000,
12'b000011xxx111,
12'b000011xx0001,
12'b000011xx0101,
12'b010011100001,
12'b010011100101,
12'b010111100001,
12'b010111100101,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01100101,
12'b1xxx01100110: tran_sel = `TRAN_STK;
default: tran_sel = `TRAN_MEM;
endcase
end
1017,17 → 1157,26
12'b1xxx10101001,
12'b1xxx10110001,
12'b1xxx10111001: tran_sel = `TRAN_IDL;
12'b1xxx100xx011,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10111011: tran_sel = `TRAN_IO;
12'b000011001001,
12'b000011xxx000,
12'b000011xx0001,
12'b010011100001,
12'b010111100001,
12'b1xxx01000101,
12'b1xxx10000011,
12'b1xxx10001011,
12'b1xxx10010011,
12'b1xxx10011011,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011: tran_sel = `TRAN_IO;
12'b000011001001,
12'b000011xxx000,
12'b000011xx0001,
12'b010011100001,
12'b010111100001,
12'b1xxx01000101,
12'b1xxx01001101: tran_sel = `TRAN_STK;
default: tran_sel = `TRAN_MEM;
endcase
1042,54 → 1191,73
12'b1xxx10101001,
12'b1xxx10110001,
12'b1xxx10111001: tran_sel = `TRAN_IDL;
12'b000000001010,
12'b000000011010,
12'b000000101010,
12'b000000111010,
12'b000001xxx110,
12'b000010000110,
12'b000010001110,
12'b000010010110,
12'b000010011110,
12'b000010100110,
12'b000010101110,
12'b000010110110,
12'b000010111110,
12'b000011011011,
12'b000011xx0001,
12'b001001xxx110,
12'b010000101010,
12'b010001xxx110,
12'b010010000110,
12'b010010001110,
12'b010010010110,
12'b010010011110,
12'b010010100110,
12'b010010101110,
12'b010010110110,
12'b010010111110,
12'b010011100001,
12'b010100101010,
12'b010101xxx110,
12'b010110000110,
12'b010110001110,
12'b010110010110,
12'b010110011110,
12'b010110100110,
12'b010110101110,
12'b010110110110,
12'b010110111110,
12'b010111100001,
12'b011001xxx110,
12'b011101xxx110,
12'b1xxx01110100,
12'b1xxx01xxx000,
12'b000000001010,
12'b000000011010,
12'b000000101010,
12'b000000111010,
12'b000001xxx110,
12'b000010000110,
12'b000010001110,
12'b000010010110,
12'b000010011110,
12'b000010100110,
12'b000010101110,
12'b000010110110,
12'b000010111110,
12'b000011011011,
12'b000011xx0001,
12'b001001xxx110,
12'b010000101010,
12'b010000110001,
12'b010000110111,
12'b010000xx0111,
12'b010001xxx110,
12'b010010000110,
12'b010010001110,
12'b010010010110,
12'b010010011110,
12'b010010100110,
12'b010010101110,
12'b010010110110,
12'b010010111110,
12'b010011100001,
12'b010100101010,
12'b010100110001,
12'b010100110111,
12'b010100xx0111,
12'b010101xxx110,
12'b010110000110,
12'b010110001110,
12'b010110010110,
12'b010110011110,
12'b010110100110,
12'b010110101110,
12'b010110110110,
12'b010110111110,
12'b010111100001,
12'b011001xxx110,
12'b011101xxx110,
12'b1xxx00110100,
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00xx0111,
12'b1xxx00xxx000,
12'b1xxx01xxx000,
12'b1xxx01xx1011: tran_sel = `TRAN_IF;
12'b1xxx100xx011,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10111011: tran_sel = `TRAN_IO;
12'b1xxx10000011,
12'b1xxx10001011,
12'b1xxx10010011,
12'b1xxx10011011,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011: tran_sel = `TRAN_IO;
12'b000011100011,
12'b0001xxxxxxxx,
12'b010011100011,
1099,35 → 1267,72
end
`WR1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10110010,
12'b1xxx10111010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
12'b1xxx1001x011,
12'b1xxx10110000,
12'b1xxx10111000,
12'b1xxx10110011,
12'b1xxx10111011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011: tran_sel = `TRAN_IF;
12'b000000100010,
12'b010000100010,
12'b010100100010,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10110010,
12'b1xxx10111010,
12'b1xxx11000010,
12'b1xxx11001010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
12'b1xxx10010011,
12'b1xxx10011011,
12'b1xxx10110000,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
12'b000000100010,
12'b010000100010,
12'b010000111110,
12'b010000111111,
12'b010000xx1111,
12'b010100100010,
12'b010100111110,
12'b010100111111,
12'b010100xx1111,
12'b1xxx00111110,
12'b1xxx00111111,
12'b1xxx00xx1111,
12'b1xxx01xx0011: tran_sel = `TRAN_MEM;
default: tran_sel = `TRAN_STK;
12'b000011001101,
12'b000011100011,
12'b000011xxx100,
12'b000011xxx111,
12'b000011xx0101,
12'b0001xxxxxxxx,
12'b010011100011,
12'b010011100101,
12'b010111100011,
12'b010111100101,
12'b1xxx01100101,
12'b1xxx01100110: tran_sel = `TRAN_STK;
default: tran_sel = `TRAN_IF;
endcase
end
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10110010,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10110010,
12'b1xxx11000010,
12'b1xxx11001010,
12'b1xxx10111010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
12'b1xxx1001x011,
12'b1xxx10110000,
12'b1xxx10111000,
12'b1xxx10110011,
12'b1xxx10111011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
12'b1xxx10010011,
12'b1xxx10011011,
12'b1xxx10110000,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
default: tran_sel = `TRAN_IF;
endcase
end
1273,42 → 1478,67
end
`DEC2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b010011100101,
12'b010011101001,
12'b010111100101,
12'b010111101001,
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011: add_sel = `ADD_ALU;
12'b001000000110,
12'b001000001110,
12'b001000010110,
12'b001000011110,
12'b001000100110,
12'b001000101110,
12'b001000110110,
12'b001000111110,
12'b001001xxx110,
12'b001010xxx110,
12'b001011xxx110,
12'b1xxx00110100,
12'b1xxx01100111,
12'b010011100101,
12'b010011101001,
12'b010111100101,
12'b010111101001,
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: add_sel = `ADD_ALU;
12'b1xxx10000010,
12'b1xxx10001010,
12'b1xxx10010010,
12'b1xxx10011010: add_sel = `ADD_ALU8;
12'b001000000110,
12'b001000001110,
12'b001000010110,
12'b001000011110,
12'b001000100110,
12'b001000101110,
12'b001000110110,
12'b001000111110,
12'b001001xxx110,
12'b001010xxx110,
12'b001011xxx110,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx00110100,
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00111110,
12'b1xxx00111111,
12'b1xxx00xx0111,
12'b1xxx00xx1111,
12'b1xxx01100111,
12'b1xxx01101111: add_sel = `ADD_HL;
12'b010011100001,
12'b010011100011,
1352,59 → 1582,88
end
`RD2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011100011,
12'b0001xxxxxxxx,
12'b010000110100,
12'b010000110101,
12'b010011100011,
12'b010100110100,
12'b010100110101,
12'b010111100011,
12'b011x00xxxxxx,
12'b011x1xxxxxxx,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011: add_sel = `ADD_ALU;
//12'b1xxx01110100,
12'b000011100011,
12'b0001xxxxxxxx,
12'b010000110100,
12'b010000110101,
12'b010011100011,
12'b010100110100,
12'b010100110101,
12'b010111100011,
12'b011000000110,
12'b011000001110,
12'b011000010110,
12'b011000011110,
12'b011000100110,
12'b011000101110,
12'b011000110110,
12'b011000111110,
12'b011010xxx110,
12'b011011xxx110,
12'b011100000110,
12'b011100001110,
12'b011100010110,
12'b011100011110,
12'b011100100110,
12'b011100101110,
12'b011100110110,
12'b011100111110,
12'b011110xxx110,
12'b011111xxx110,
12'b1xxx10000010,
12'b1xxx10001010,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: add_sel = `ADD_ALU;
12'b1xxx100xx011: add_sel = `ADD_ALU8;
12'b000000110100,
12'b000000110101,
12'b000000xxx100,
12'b000000xxx101,
12'b001000000110,
12'b001000000xxx,
12'b001000001110,
12'b001000001xxx,
12'b001000010110,
12'b001000010xxx,
12'b001000011110,
12'b001000011xxx,
12'b001000100110,
12'b001000100xxx,
12'b001000101110,
12'b001000101xxx,
12'b001000110110,
12'b001000110xxx,
12'b001000111110,
12'b001000111xxx,
12'b001010xxx110,
12'b001010xxxxxx,
12'b001011xxx110,
12'b001011xxxxxx,
12'b1xxx01100111,
12'b000000110100,
12'b000000110101,
12'b000000xxx100,
12'b000000xxx101,
12'b001000000110,
12'b001000000xxx,
12'b001000001110,
12'b001000001xxx,
12'b001000010110,
12'b001000010xxx,
12'b001000011110,
12'b001000011xxx,
12'b001000100110,
12'b001000100xxx,
12'b001000101110,
12'b001000101xxx,
12'b001000110110,
12'b001000110xxx,
12'b001000111110,
12'b001000111xxx,
12'b001010xxx110,
12'b001010xxxxxx,
12'b001011xxx110,
12'b001011xxxxxx,
12'b1xxx01100111,
12'b1xxx01101111: add_sel = `ADD_HL;
default: add_sel = `ADD_PC;
endcase
1411,35 → 1670,59
end
`WR1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx1000x011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011: add_sel = `ADD_PC;
12'b1xxx10010010,
12'b1xxx10011010: add_sel = `ADD_ALU8;
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10101100: add_sel = `ADD_PC;
default: add_sel = `ADD_ALU;
endcase
end
`WR2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011001101,
12'b000011xxx100,
12'b000011xxx111,
12'b0001xxxxxxxx,
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011: add_sel = `ADD_ALU;
12'b000011001101,
12'b000011xxx100,
12'b000011xxx111,
12'b0001xxxxxxxx,
12'b1xxx10000011,
12'b1xxx10001011,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: add_sel = `ADD_ALU;
12'b1xxx10000010,
12'b1xxx10001010,
12'b1xxx10010010,
12'b1xxx10011010: add_sel = `ADD_ALU8;
default: add_sel = `ADD_PC;
endcase
end
1544,181 → 1827,146
end
`DEC2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b010000100110,
12'b010000101110,
12'b010100100110,
12'b010100101110,
12'b010011001011, //DD+CB prefix
12'b010111001011, //FD+CB prefix
12'b010000100001,
12'b010000100010,
12'b010000101010,
12'b010000110100,
12'b010000110101,
12'b010000110110,
12'b010001110xxx,
12'b010001xxx110,
12'b010010000110,
12'b010010001110,
12'b010010010110,
12'b010010011110,
12'b010010100110,
12'b010010101110,
12'b010010110110,
12'b010010111110,
12'b010011101001,
12'b010100100001,
12'b010100100010,
12'b010100101010,
12'b010100110100,
12'b010100110101,
12'b010100110110,
12'b010101110xxx,
12'b010101xxx110,
12'b010110000110,
12'b010110001110,
12'b010110010110,
12'b010110011110,
12'b010110100110,
12'b010110101110,
12'b010110110110,
12'b010110111110,
12'b010111101001,
12'b1xxx00xxx000,
12'b1xxx00xxx001,
12'b1xxx01100100,
12'b1xxx01110100,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01xx0011,
12'b1xxx01xx1011: pc_sel = `PC_LD;
12'b010010001100,
12'b010010001101,
12'b010110001100,
12'b010110001101,
12'b010010000100,
12'b010010000101,
12'b010110000100,
12'b010110000101,
12'b010010100100,
12'b010010100101,
12'b010110100100,
12'b010110100101,
12'b010010111100,
12'b010010111101,
12'b010110111100,
12'b010110111101,
12'b010000100101,
12'b010000101101,
12'b010100100101,
12'b010100101101,
12'b010000100100,
12'b010000101100,
12'b010100100100,
12'b010100101100,
12'b0100011000xx,12'b01000110010x,12'b010001100111,
12'b0100011010xx,12'b01000110110x,12'b010001101111,
12'b0101011000xx,12'b01010110010x,12'b010101100111,
12'b0101011010xx,12'b01010110110x,12'b010101101111,
12'b0100010xx100,12'b01000110x100,12'b010001111100,
12'b0100010xx101,12'b01000110x101,12'b010001111101,
12'b0101010xx100,12'b01010110x100,12'b010101111100,
12'b0101010xx101,12'b01010110x101,12'b010101111101,
12'b010010110100,
12'b010010110101,
12'b010110110100,
12'b010110110101,
12'b010010011100,
12'b010010011101,
12'b010110011100,
12'b010110011101,
12'b010010010100,
12'b010010010101,
12'b010110010100,
12'b010110010101,
12'b010010101100,
12'b010010101101,
12'b010110101100,
12'b010110101101,
12'b0010000000xx,12'b00100000010x,12'b001000000111,
12'b0010000010xx,12'b00100000110x,12'b001000001111,
12'b0010000100xx,12'b00100001010x,12'b001000010111,
12'b0010000110xx,12'b00100001110x,12'b001000011111,
12'b0010001000xx,12'b00100010010x,12'b001000100111,
12'b0010001010xx,12'b00100010110x,12'b001000101111,
12'b0010001100xx,12'b00100011010x,12'b001000110111,
12'b0010001110xx,12'b00100011110x,12'b001000111111,
12'b001001xxx0xx,12'b001001xxx10x,12'b001001xxx111,
12'b001010xxx0xx,12'b001010xxx10x,12'b001010xxx111,
12'b001011xxx0xx,12'b001011xxx10x,12'b001011xxx111,
12'b010000100011,
12'b010000101011,
12'b010000xx1001,
12'b010011111001,
12'b010100100011,
12'b010100101011,
12'b010100xx1001,
12'b010111111001,
12'b1xxx000xx100,12'b1xxx0010x100,12'b1xxx00111100,
12'b1xxx01xx1100,
12'b1xxx01000100,
12'b1xxx01000110,
12'b1xxx01000111,
12'b1xxx01001111,
12'b1xxx01010110,
12'b1xxx01010111,
12'b1xxx01011110,
12'b1xxx01011111,
12'b1xxx01xx0010,
12'b1xxx01xx1010: pc_sel = `PC_NILD;
default: pc_sel = `PC_NUL;
12'b001000000110,
12'b001000001110,
12'b001000010110,
12'b001000011110,
12'b001000100110,
12'b001000101110,
12'b001000110110,
12'b001000111110,
12'b001001xxx110,
12'b001010xxx110,
12'b001011xxx110,
12'b010011100001,
12'b010011100011,
12'b010011100101,
12'b010111100001,
12'b010111100011,
12'b010111100101,
12'b1xxx00110100,
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00111110,
12'b1xxx00111111,
12'b1xxx00xx0111,
12'b1xxx00xx1111,
12'b1xxx01100111,
12'b1xxx01101111,
12'b1xxx01110110,
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: pc_sel = `PC_NUL;
12'b010000100001,
12'b010000100010,
12'b010000100110,
12'b010000101010,
12'b010000101110,
12'b010000110001,
12'b010000110100,
12'b010000110101,
12'b010000110110,
12'b010000110111,
12'b010000111110,
12'b010000111111,
12'b010000xx0111,
12'b010000xx1111,
12'b010001110xxx,
12'b010001xxx110,
12'b010010000110,
12'b010010001110,
12'b010010010110,
12'b010010011110,
12'b010010100110,
12'b010010101110,
12'b010010110110,
12'b010010111110,
12'b010011101001,
12'b010100100001,
12'b010100100010,
12'b010100100110,
12'b010100101010,
12'b010100101110,
12'b010100110001,
12'b010100110100,
12'b010100110101,
12'b010100110110,
12'b010100110111,
12'b010100111110,
12'b010100111111,
12'b010100xx0111,
12'b010100xx1111,
12'b010101110xxx,
12'b010101xxx110,
12'b010110000110,
12'b010110001110,
12'b010110010110,
12'b010110011110,
12'b010110100110,
12'b010110101110,
12'b010110110110,
12'b010110111110,
12'b010111101001,
12'b010011001011, //DD+CB prefix
12'b010111001011, //FD+CB prefix
12'b1xxx00110010,
12'b1xxx00110011,
12'b1xxx00xx0010,
12'b1xxx00xx0011,
12'b1xxx00xxx000,
12'b1xxx00xxx001,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01010100,
12'b1xxx01010101,
12'b1xxx01100100,
12'b1xxx01100101,
12'b1xxx01100110,
12'b1xxx01110100,
12'b1xxx01xx1011,
12'b1xxx01xx0011: pc_sel = `PC_LD;
default: pc_sel = `PC_NILD;
endcase
end
`OF2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000100010,
12'b000000101010,
12'b000000110010,
12'b000000111010,
12'b000000xx0001,
12'b000011000011,
12'b000011001101,
12'b000011xxx010,
12'b000011xxx100,
12'b010000100001,
12'b010000100010,
12'b010000101010,
12'b010000110110,
12'b010100100001,
12'b010100100010,
12'b010100101010,
12'b010100110110,
12'b1xxx01xx0011,
12'b1xxx01xx1011: pc_sel = `PC_LD;
default: pc_sel = `PC_NUL;
endcase
end
`IF3A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b01xx11001011: pc_sel = `PC_LD;
default: pc_sel = `PC_NUL;
endcase
end
`OF2A,
`IF3A: pc_sel = `PC_LD;
`RD1B,
`RD2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx1001x011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011: pc_sel = `PC_INT;
default: pc_sel = `PC_NUL;
endcase
end
`RD2B: pc_sel = `PC_INT;
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011001101,
1744,35 → 1992,57
end
`PCO: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011101001,
12'b010011101001,
12'b010111101001,
12'b1xxx1001x011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011: pc_sel = `PC_LD;
12'b000011101001,
12'b010011101001,
12'b010111101001,
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: pc_sel = `PC_LD;
default: pc_sel = `PC_NUL;
endcase
end
`IF1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b0001xxxxxxxx,
12'b1xxx01000101,
12'b1xxx01001101,
12'b0001xxxxxxxx: pc_sel = `PC_LD;
12'b1xxx1001x011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011: pc_sel = `PC_NILD2;
12'b1xxx01001101: pc_sel = `PC_LD;
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: pc_sel = `PC_NILD2;
default: pc_sel = `PC_NILD;
endcase
end
1837,18 → 2107,30
`RD1B: di_ctl = `DI_DI0;
`RD2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000101010,
12'b000011001001,
12'b010x00101010,
12'b010x11100001,
12'b010x11100011,
12'b000011100011,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01xx1011,
12'b000011xxx000,
12'b000011xx0001,
12'b0001xxxxxxxx: di_ctl = `DI_DI1;
12'b000000101010,
12'b000011001001,
12'b000011100011,
12'b000011xxx000,
12'b000011xx0001,
12'b0001xxxxxxxx,
12'b010000101010,
12'b010000110001,
12'b010000110111,
12'b010000xx0111,
12'b010011100001,
12'b010011100011,
12'b010100101010,
12'b010100110001,
12'b010100110111,
12'b010100xx0111,
12'b010111100001,
12'b010111100011,
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00xx0111,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01xx1011: di_ctl = `DI_DI1;
default: di_ctl = `DI_DI0;
endcase
end
1866,33 → 2148,64
casex (state_reg) //synopsys parallel_case
`WR1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011001101,
12'b010x11100101,
12'b000011xxx100,
12'b000011xx0101,
12'b000011xxx111,
12'b0001xxxxxxxx: do_ctl = `DO_MSB;
12'b1xxx100xx011,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10111011: do_ctl = `DO_IO;
12'b000011001101,
12'b000011xxx100,
12'b000011xx0101,
12'b000011xxx111,
12'b0001xxxxxxxx,
12'b010011100101,
12'b010111100101,
12'b1xxx01100101,
12'b1xxx01100110: do_ctl = `DO_MSB;
12'b1xxx10000011,
12'b1xxx10001011,
12'b1xxx10010011,
12'b1xxx10011011,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011: do_ctl = `DO_IO;
default: do_ctl = `DO_LSB;
endcase
end
`WR2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000100010,
12'b010x00100010,
12'b010x11100011,
12'b000011100011,
12'b000000100010,
12'b000011100011,
12'b010000100010,
12'b010000111110,
12'b010000111111,
12'b010000xx1111,
12'b010011100011,
12'b010100100010,
12'b010100111110,
12'b010100111111,
12'b010100xx1111,
12'b010111100011,
12'b1xxx00111110,
12'b1xxx00111111,
12'b1xxx00xx1111,
12'b1xxx01xx0011: do_ctl = `DO_MSB;
12'b000011010011,
12'b1xxx0xxxx001,
12'b1xxx100xx011,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
12'b000011010011,
12'b1xxx00xxx001,
12'b1xxx01xxx001,
12'b1xxx10000011,
12'b1xxx10001011,
12'b1xxx10010011,
12'b1xxx10011011,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011,
12'b1xxx10111011: do_ctl = `DO_IO;
default: do_ctl = `DO_LSB;
endcase
1943,6 → 2256,8
`DEC2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx01xx1010: aluop_sel = `ALUOP_ADC;
12'b1xxx10100100,
12'b1xxx10101100,
12'b010000100011,
12'b010000101011,
12'b010000xx1001,
2058,40 → 2373,63
`IF3A: aluop_sel = `ALUOP_ADS;
`ADR1: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx00xxx00x,
12'b000000100010,
12'b000000101010,
12'b000000110010,
12'b000000111010,
12'b000011010011,
12'b000011011011,
12'b0001xxxxxxxx,
12'b010000100010,
12'b010000101010,
12'b010100100010,
12'b010100101010,
12'b1xxx01100100,
12'b1xxx01110100,
12'b1xxx01xx0011,
12'b1xxx01xx1011: aluop_sel = `ALUOP_PASS;
12'b1xxx01100101,
12'b1xxx01100110: aluop_sel = `ALUOP_ADD;
12'b000000100010,
12'b000000101010,
12'b000000110010,
12'b000000111010,
12'b000011010011,
12'b000011011011,
12'b0001xxxxxxxx,
12'b010000100010,
12'b010000101010,
12'b010100100010,
12'b010100101010,
12'b1xxx00xxx000,
12'b1xxx00xxx001,
12'b1xxx01110100,
12'b1xxx01xx1011,
12'b1xxx01xx0011: aluop_sel = `ALUOP_PASS;
default: aluop_sel = `ALUOP_ADS;
endcase
end
`ADR2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10111000,
12'b1xxx10111001: aluop_sel = `ALUOP_ADD;
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10101000,
12'b1xxx10101001,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: aluop_sel = `ALUOP_ADD;
12'b1xxx01100101,
12'b1xxx01100110: aluop_sel = `ALUOP_ADS;
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010: aluop_sel = `ALUOP_BADD;
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
2101,94 → 2439,151
end
`RD1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011: aluop_sel = `ALUOP_PASS;
default: aluop_sel = `ALUOP_ADD;
12'b000000101010,
12'b000011001001,
12'b000011100011,
12'b000011xxx000,
12'b000011xx0001,
12'b0001xxxxxxxx,
12'b010000101010,
12'b010000110001,
12'b010000110111,
12'b010000xx0111,
12'b010011100001,
12'b010011100011,
12'b010100101010,
12'b010100110001,
12'b010100110111,
12'b010100xx0111,
12'b010111100001,
12'b010111100011,
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00xx0111,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01xx1011: aluop_sel = `ALUOP_ADD;
default: aluop_sel = `ALUOP_PASS;
endcase
end
`RD1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111010,
12'b1xxx10111011: aluop_sel = `ALUOP_BAND;
12'b1xxx10100001,
12'b1xxx10101001,
12'b1xxx10110001,
12'b1xxx10111001: aluop_sel = `ALUOP_BSUB;
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
12'b1xxx10111000: aluop_sel = `ALUOP_PASS;
default: aluop_sel = `ALUOP_BAND;
default: aluop_sel = `ALUOP_PASS;
endcase
end
`RD2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011001001,
12'b000011xxx000,
12'b000011xx0001,
12'b0001xxxxxxxx,
12'b010011100001,
12'b010111100001,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10111000,
12'b1xxx10111010: aluop_sel = `ALUOP_ADD;
12'b1xxx100xx011: aluop_sel = `ALUOP_BADD;
12'b000011001001,
12'b000011xxx000,
12'b000011xx0001,
12'b0001xxxxxxxx,
12'b010011100001,
12'b010111100001,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101100,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11001010: aluop_sel = `ALUOP_ADD;
12'b1xxx10000011,
12'b1xxx10001011,
12'b1xxx10010011,
12'b1xxx10011011: aluop_sel = `ALUOP_BADD;
default: aluop_sel = `ALUOP_PASS;
endcase
end
`RD2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000xxx100,
12'b010000110100,
12'b000000110100,
12'b000000xxx100,
12'b010000110100,
12'b010100110100: aluop_sel = `ALUOP_BADD;
12'b0x1x10xxxxxx,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111010,
12'b001010xxx110,
12'b001010xxxxxx,
12'b011010xxx110,
12'b011110xxx110,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111010,
12'b1xxx10111011: aluop_sel = `ALUOP_BAND;
12'b000000xxx101,
12'b010000110101,
12'b000000110101,
12'b000000xxx101,
12'b010000110101,
12'b010100110101: aluop_sel = `ALUOP_BDEC;
12'b0x1x11xxxxxx: aluop_sel = `ALUOP_BOR;
12'b1xxx10100001,
12'b1xxx10101001,
12'b1xxx10110001,
12'b001011xxx110,
12'b001011xxxxxx,
12'b011011xxx110,
12'b011111xxx110: aluop_sel = `ALUOP_BOR;
12'b1xxx10100001,
12'b1xxx10101001,
12'b1xxx10110001,
12'b1xxx10111001: aluop_sel = `ALUOP_BSUB;
12'b000011001001,
12'b000011100011,
12'b000011xxx000,
12'b0001xxxxxxxx,
12'b010011100011,
12'b010111100011,
12'b1xxx01000101,
12'b1xxx01001101,
//12'b1xxx01110100,
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
12'b1xxx10111000: aluop_sel = `ALUOP_PASS;
12'b000011001001,
12'b000011100011,
12'b000011xxx000,
12'b0001xxxxxxxx,
12'b010011100011,
12'b010111100011,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101100,
12'b1xxx10110000,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: aluop_sel = `ALUOP_PASS;
12'b0x1x00000xxx: aluop_sel = `ALUOP_RLC;
12'b0x1x00001xxx: aluop_sel = `ALUOP_RRC;
12'b0x1x00010xxx: aluop_sel = `ALUOP_RL;
2207,12 → 2602,30
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010: aluop_sel = `ALUOP_PASS;
12'b1xxx10111010,
12'b1xxx11000010,
12'b1xxx11001010: aluop_sel = `ALUOP_PASS;
12'b1xxx10100100,
12'b1xxx10101100: aluop_sel = `ALUOP_BADD;
default: aluop_sel = `ALUOP_ADD;
endcase
end
`WR1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10011011,
12'b1xxx10010011,
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
2220,8 → 2633,13
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx10111000: aluop_sel = `ALUOP_ADD;
12'b1xxx100xx011,
12'b1xxx10001011,
12'b1xxx10000011,
12'b1xxx10010010,
12'b1xxx10011010,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111010,
2232,6 → 2650,12
`WR2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011,
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011,
12'b1xxx10100000,
12'b1xxx10100011,
12'b1xxx10101000,
2242,6 → 2666,14
12'b1xxx10111011: aluop_sel = `ALUOP_ADD;
12'b000011xxx111,
12'b0001xxxxxxxx: aluop_sel = `ALUOP_APAS;
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10011010,
12'b1xxx10100100,
12'b1xxx10101100: aluop_sel = `ALUOP_BADD;
default: aluop_sel = `ALUOP_PASS;
endcase
end
2248,6 → 2680,14
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011,
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10011010,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101010,
2259,8 → 2699,18
default: aluop_sel = `ALUOP_ADD;
endcase
end
`PCA,
`PCO: aluop_sel = `ALUOP_ADD;
`IF1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10101000,
2267,8 → 2717,21
12'b1xxx10101010,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111010: aluop_sel = `ALUOP_ADD;
12'b1xxx10111010,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: aluop_sel = `ALUOP_ADD;
12'b1xxx00011010,
12'b1xxx01010100,
12'b1xxx01010101,
12'b1xxx00110010,
12'b1xxx00110011,
12'b1xxx00xx0010,
12'b1xxx00xx0011: aluop_sel = `ALUOP_ADS;
12'b000010001xxx,
12'b000011001110,
12'b010x10001110: aluop_sel = `ALUOP_BADC;
2276,6 → 2739,8
12'b000011000110,
12'b010x10000110,
12'b1xxx100xx011,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
2359,7 → 2824,9
12'b010100100101,
12'b010100101011,
12'b010100101101,
12'b1xxx10101100,
12'b010111100101: alua_sel = `ALUA_M1;
12'b1xxx10100100,
12'b010000100100,
12'b010000101100,
12'b010000100011,
2390,8 → 2857,21
endcase
end
`IF3A: alua_sel = (page_reg[0]) ? `ALUA_IY : `ALUA_IX;
`ADR1: alua_sel = (page_reg[2]) ? ((page_reg[0]) ? `ALUA_IY : `ALUA_IX) : `ALUA_M1;
`ADR2: alua_sel = `ALUA_M1;
`ADR1: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011010011: alua_sel = `ALUA_M1;
12'b1xxx01100101,
12'b1xxx01100110: alua_sel = `ALUA_M1;
default: alua_sel = (page_reg[0]) ? `ALUA_IY : `ALUA_IX;
endcase
end
`ADR2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx01100101: alua_sel = `ALUA_IX;
12'b1xxx01100110: alua_sel = `ALUA_IY;
default: alua_sel = `ALUA_M1;
endcase
end
`RD1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10100001,
2403,12 → 2883,21
end
`RD2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b0001xxxxxxxx,
12'b1xxx100x1011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10111000,
12'b1xxx10111010: alua_sel = `ALUA_M1;
12'b0001xxxxxxxx,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101100,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111100,
12'b1xxx11001010,
12'b1xxx11001011: alua_sel = `ALUA_M1;
default: alua_sel = `ALUA_ONE;
endcase
end
2437,41 → 2926,69
end
`WR1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000100010,
12'b000011100011,
12'b010000100010,
12'b010011100011,
12'b010100100010,
12'b010111100011,
12'b1xxx01xx0011,
12'b1xxx100x0011,
12'b1xxx10100000,
12'b1xxx10100011,
12'b1xxx10110000,
12'b1xxx10110011: alua_sel = `ALUA_ONE;
default: alua_sel = `ALUA_M1;
12'b000011001101,
12'b000011xxx100,
12'b000011xx0101,
12'b000011xxx111,
12'b0001xxxxxxxx,
12'b010011100101,
12'b010111100101,
12'b1xxx01100101,
12'b1xxx01100110,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10101000,
12'b1xxx10101011,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx10111000,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11001010,
12'b1xxx11001011: alua_sel = `ALUA_M1;
default: alua_sel = `ALUA_ONE;
endcase
end
`WR1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx1001x011,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011: alua_sel = `ALUA_M1;
default: alua_sel = `ALUA_ONE;
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10101100: alua_sel = `ALUA_ONE;
default: alua_sel = `ALUA_M1;
endcase
end
`WR2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b0001xxxxxxxx: alua_sel = `ALUA_INT;
12'b1xxx100x1011,
12'b1xxx10101000,
12'b1xxx10101011,
12'b1xxx10111000,
12'b1xxx10111011: alua_sel = `ALUA_M1;
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10101000,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10111000,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11001010,
12'b1xxx11001011: alua_sel = `ALUA_M1;
12'b000011xxx111: alua_sel = `ALUA_RST;
default: alua_sel = `ALUA_ONE;
endcase
2478,19 → 2995,38
end
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011: alua_sel = `ALUA_M1;
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10100100,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10110100,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011: alua_sel = `ALUA_M1;
default: alua_sel = `ALUA_ONE;
endcase
end
2504,22 → 3040,46
`IF1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b0x1x01xxxxxx: alua_sel = `ALUA_BIT;
12'b1xxx00xxx000,
12'b1xxx01xxx000,
12'b1xxx100x1011,
12'b1xxx00110010,
12'b1xxx00xx0010,
12'b1xxx01010101: alua_sel = `ALUA_IX;
12'b1xxx00110011,
12'b1xxx00xx0011,
12'b1xxx01010100: alua_sel = `ALUA_IY;
12'b1xxx00xxx000,
12'b1xxx01xxx000,
12'b1xxx10001010,
12'b1xxx10001011,
12'b1xxx10001100,
12'b1xxx10011010,
12'b1xxx10011011,
12'b1xxx10011100,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011: alua_sel = `ALUA_M1;
12'b1xxx100x0011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10110000,
12'b1xxx10110010: alua_sel = `ALUA_ONE;
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011,
12'b1xxx10101100,
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011,
12'b1xxx10111100,
12'b1xxx11001010,
12'b1xxx11001011: alua_sel = `ALUA_M1;
12'b1xxx10000010,
12'b1xxx10000011,
12'b1xxx10000100,
12'b1xxx10010010,
12'b1xxx10010011,
12'b1xxx10010100,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100100,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110100,
12'b1xxx11000010,
12'b1xxx11000011: alua_sel = `ALUA_ONE;
12'b1xxx01110100: alua_sel = `ALUA_TMP;
default: alua_sel = `ALUA_AA;
endcase
2599,6 → 3159,8
12'b1xxx01001111: alub_sel = `ALUB_AA;
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx10000100,
12'b1xxx10001100,
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
2662,6 → 3224,10
12'b0010xxxxx000: alub_sel = `ALUB_BB;
12'b010x0110x001,
12'b1xxx00001100,
12'b1xxx10000010,
12'b1xxx10001010,
12'b1xxx10010010,
12'b1xxx10011010,
12'b0010xxxxx001: alub_sel = `ALUB_CC;
12'b010x0110x010,
12'b1xxx00010100,
2685,6 → 3251,10
12'b010011100101,
12'b010111100101: alub_sel = `ALUB_SP;
12'b010x00001001: alub_sel = `ALUB_BC;
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx11000010,
12'b1xxx11001010,
12'b010x00011001: alub_sel = `ALUB_DE;
12'b010000101001: alub_sel = `ALUB_IX;
12'b010100101001: alub_sel = `ALUB_IY;
2742,7 → 3312,9
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx01110100: alub_sel = `ALUB_CC;
12'b000011010011,
12'b000011011011: alub_sel = `ALUB_IO;
12'b000011011011: alub_sel = `ALUB_IO;
12'b1xxx01100101,
12'b1xxx01100110: alub_sel = `ALUB_SP;
12'b0001xxxxxxxx: alub_sel = `ALUB_TMP;
default: alub_sel = `ALUB_DIN;
endcase
2753,6 → 3325,14
12'b000000010010,
12'b000000110010,
12'b000011010011: alub_sel = `ALUB_AA;
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10011010,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10100011,
2762,6 → 3342,12
12'b1xxx10110011,
12'b1xxx10111010,
12'b1xxx10111011: alub_sel = `ALUB_BB;
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10101000,
2768,17 → 3354,30
12'b1xxx10101001,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx10111000,
12'b1xxx10111001: alub_sel = `ALUB_BC;
12'b1xxx01100101,
12'b1xxx01100110: alub_sel = `ALUB_DIN;
12'b010000100010: alub_sel = `ALUB_IX;
12'b010011100101: alub_sel = `ALUB_IXH;
12'b010000111111,
12'b010100111110,
12'b1xxx00111111: alub_sel = `ALUB_IXL;
12'b010100100010: alub_sel = `ALUB_IY;
12'b010111100101: alub_sel = `ALUB_IYH;
12'b010000111110,
12'b010100111111,
12'b1xxx00111110: alub_sel = `ALUB_IYL;
12'b000011xxx111: alub_sel = `ALUB_PCH;
12'b000001xxx000,
12'b010x01110000,
12'b1xxx00000001,
12'b1xxx01000001: alub_sel = `ALUB_BB;
12'b010000001111,
12'b010100001111,
12'b1xxx00001111,
12'b000001xxx001,
12'b010x01110001,
12'b1xxx01110100,
2788,6 → 3387,9
12'b010x01110010,
12'b1xxx00010001,
12'b1xxx01010001: alub_sel = `ALUB_DD;
12'b010000011111,
12'b010100011111,
12'b1xxx00011111,
12'b000001xxx011,
12'b010x01110011,
12'b1xxx00011001,
2796,6 → 3398,9
12'b010x01110100,
12'b1xxx00100001,
12'b1xxx01100001: alub_sel = `ALUB_HH;
12'b010000101111,
12'b010100101111,
12'b1xxx00101111,
12'b000001xxx101,
12'b010x01110101,
12'b1xxx00101001,
2810,21 → 3415,42
12'b000011000101: alub_sel = `ALUB_BB;
12'b000011010101: alub_sel = `ALUB_DD;
12'b000011100101: alub_sel = `ALUB_HH;
12'b000011110101: alub_sel = `ALUB_AA;
12'b000011110101: alub_sel = `ALUB_AA;
12'b1xxx01100101,
12'b1xxx01100110: alub_sel = `ALUB_TMP;
default: alub_sel = `ALUB_HL;
endcase
end
`RD1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10111011: alub_sel = `ALUB_BC;
12'b1xxx100xx011: alub_sel = `ALUB_CC;
12'b1xxx11000011,
12'b1xxx11001011,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx10111000: alub_sel = `ALUB_DE;
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00xx0111,
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx11000010,
12'b1xxx11001010,
12'b1xxx10100001,
12'b1xxx10100010,
12'b1xxx10101001,
2833,6 → 3459,12
12'b1xxx10110010,
12'b1xxx10111001,
12'b1xxx10111010: alub_sel = `ALUB_HL;
12'b010000110001,
12'b010000110111,
12'b010000xx0111,
12'b010100110001,
12'b010100110111,
12'b010100xx0111,
12'b000000101010,
12'b0001xxxxxxxx,
12'b010000101010,
2841,9 → 3473,11
default: alub_sel = `ALUB_SP;
endcase
end
`RD1B: alub_sel = `ALUB_DIN;
`RD1B: alub_sel = `ALUB_DIN;
`RD2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
2850,10 → 3484,24
12'b1xxx10111011: alub_sel = `ALUB_BC;
12'b1xxx01110100,
12'b1xxx100xx011: alub_sel = `ALUB_CC;
12'b1xxx11000011,
12'b1xxx11001011,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx10111000: alub_sel = `ALUB_DE;
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx11000010,
12'b1xxx11001010,
12'b001010xxxxxx,
12'b1xxx10100001,
12'b1xxx10100010,
2882,6 → 3530,15
12'b000011100011: alub_sel = `ALUB_HL;
12'b010011100011: alub_sel = `ALUB_IX;
12'b010111100011: alub_sel = `ALUB_IY;
12'b010000110001,
12'b010000110111,
12'b010000xx0111,
12'b010100110001,
12'b010100110111,
12'b010100xx0111,
12'b1xxx00110110,
12'b1xxx00110111,
12'b1xxx00xx0111,
12'b000000001010,
12'b000000011010,
12'b000000101010,
2934,10 → 3591,31
end
`WR1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10100100,
12'b1xxx10101100: alub_sel = `ALUB_BB;
12'b1xxx10000100,
12'b1xxx10001100,
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010: alub_sel = `ALUB_BC;
12'b1xxx10000010,
12'b1xxx10001010,
12'b1xxx10010010,
12'b1xxx10011010: alub_sel = `ALUB_CC;
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx11000010,
12'b1xxx11001010: alub_sel = `ALUB_DE;
12'b1xxx00111110,
12'b1xxx00111111,
12'b1xxx00xx1111,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011,
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100011,
2947,6 → 3625,12
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111011: alub_sel = `ALUB_HL;
12'b010000111110,
12'b010000111111,
12'b010000xx1111,
12'b010100111110,
12'b010100111111,
12'b010100xx1111,
12'b000000100010,
12'b010000100010,
12'b010100100010,
2956,19 → 3640,44
end
`WR1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10010010,
12'b1xxx10011010,
12'b010000001111,
12'b010100001111,
12'b1xxx00001111,
12'b1xxx1001x011,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111010,
12'b1xxx10111011: alub_sel = `ALUB_BB;
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx10110000,
12'b1xxx10111000: alub_sel = `ALUB_BC;
12'b010000011111,
12'b010100011111,
12'b1xxx00011111: alub_sel = `ALUB_DD;
12'b010000101111,
12'b010100101111,
12'b1xxx00101111,
12'b000000100010,
12'b000011100011: alub_sel = `ALUB_HH;
12'b010011100101: alub_sel = `ALUB_IX;
12'b010000111111,
12'b010100111110,
12'b1xxx00111111,
12'b010000100010,
12'b010011100011: alub_sel = `ALUB_IXH;
12'b010111100101: alub_sel = `ALUB_IY;
12'b010000111110,
12'b010100111111,
12'b1xxx00111110,
12'b010100100010,
12'b010111100011: alub_sel = `ALUB_IYH;
12'b1xxx01000011: alub_sel = `ALUB_BC;
2979,15 → 3688,25
12'b000011010101: alub_sel = `ALUB_DE;
12'b000011100101: alub_sel = `ALUB_HL;
12'b000011110101: alub_sel = `ALUB_AF;
12'b1xxx01100101,
12'b1xxx01100110: alub_sel = `ALUB_TMP;
default: alub_sel = `ALUB_PC;
endcase
end
`WR2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10000010,
12'b1xxx10001010,
12'b1xxx10010010,
12'b1xxx10011010: alub_sel = `ALUB_CC;
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010: alub_sel = `ALUB_BC;
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx11000010,
12'b1xxx11001010: alub_sel = `ALUB_DE;
12'b000011001101,
12'b000011xxx100: alub_sel = `ALUB_DIN;
default: alub_sel = `ALUB_HL;
2995,6 → 3714,14
end
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10011010,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10100011,
3004,6 → 3731,14
12'b1xxx10110011,
12'b1xxx10111010,
12'b1xxx10111011: alub_sel = `ALUB_BB;
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
3021,15 → 3756,31
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10111011: alub_sel = `ALUB_BB;
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx100xx011: alub_sel = `ALUB_CC;
12'b1xxx11000011,
12'b1xxx11001011,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx10110000,
12'b1xxx10111000: alub_sel = `ALUB_DE;
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10101010,
12'b1xxx10111010,
12'b1xxx10100010,
12'b1xxx10110010: alub_sel = `ALUB_HL;
12'b1xxx10110010,
12'b1xxx11000010,
12'b1xxx11001010: alub_sel = `ALUB_HL;
default: alub_sel = `ALUB_DIN;
endcase
end
3076,10 → 3827,26
end
`ADR2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10100100,
12'b1xxx10101100: wr_addr = `WREG_HL;
12'b1xxx01100101,
12'b1xxx01100110,
12'b000011xxx111,
12'b000011xx0101,
12'b010011100101,
12'b010111100101: wr_addr = `WREG_SP;
12'b010000110001,
12'b010000110111,
12'b010000111110,
12'b010000111111,
12'b010000xx0111,
12'b010000xx1111,
12'b010100110001,
12'b010100110111,
12'b010100111110,
12'b010100111111,
12'b010100xx0111,
12'b010100xx1111,
12'b000000100010,
12'b000000101010,
12'b010000100010,
3097,6 → 3864,12
end
`RD1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10011010,
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10100011,
3106,6 → 3879,14
12'b1xxx10110011,
12'b1xxx10111010,
12'b1xxx10111011: wr_addr = `WREG_BB;
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10101000,
3131,6 → 3912,14
end
`RD2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10011010,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10100011,
3140,6 → 3929,14
12'b1xxx10110011,
12'b1xxx10111010,
12'b1xxx10111011: wr_addr = `WREG_BB;
12'b1xxx10010100,
12'b1xxx10011100,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10101000,
3154,14 → 3951,26
`RD2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011: wr_addr = `WREG_CC;
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
12'b1xxx10111000: wr_addr = `WREG_DE;
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010: wr_addr = `WREG_HL;
12'b1xxx10111010,
12'b1xxx11000010,
12'b1xxx11001010: wr_addr = `WREG_HL;
12'b000011001001,
12'b000011xxx000,
12'b000011xx0001,
3172,9 → 3981,30
12'b1xxx01001101: wr_addr = `WREG_SP;
default: wr_addr = `WREG_NUL;
endcase
end
`WR1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx01100101,
12'b1xxx01100110: wr_addr = `WREG_TMP;
default: wr_addr = `WREG_NUL;
endcase
end
`WR1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10100100,
12'b1xxx10101100: wr_addr = `WREG_BB;
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10011010: wr_addr = `WREG_CC;
12'b1xxx10010100,
12'b1xxx10011100: wr_addr = `WREG_DE;
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011,
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100011,
3184,6 → 4014,8
12'b1xxx10110011,
12'b1xxx10111000,
12'b1xxx10111011: wr_addr = `WREG_HL;
12'b1xxx01100101,
12'b1xxx01100110,
12'b000011001101,
12'b000011xxx100,
12'b000011xxx111,
3196,6 → 4028,20
end
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10011010: wr_addr = `WREG_CC;
12'b1xxx10010100,
12'b1xxx10011100: wr_addr = `WREG_DE;
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx11000011,
12'b1xxx11001011,
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100011,
3248,8 → 4094,6
12'b000011110110,
12'b001000xxx111,
12'b00101xxxx111,
//12'b011x00xxx111,
//12'b011x1xxxx111,
12'b010010000100,
12'b010010000101,
12'b010010000110,
3306,8 → 4150,6
12'b000001000xxx,
12'b001000xxx000,
12'b00101xxxx000,
//12'b011x00xxx000,
// 12'b011x1xxxx000,
12'b010x0100010x,
12'b010x01000110,
12'b1xxx0x000000,
3315,18 → 4157,23
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10111011: wr_addr = `WREG_BB;
12'b010000000111,
12'b010100000111,
12'b1xxx00000111,
12'b1xxx00000010,
12'b1xxx00000011,
12'b000000000001,
12'b00000000x011,
12'b000011000001,
12'b1xxx01001100,
12'b1xxx01001011: wr_addr = `WREG_BC;
12'b1xxx10100100,
12'b1xxx10101100,
12'b00000000110x,
12'b000000001110,
12'b000001001xxx,
12'b001000xxx001,
12'b00101xxxx001,
//12'b011x00xxx001,
//12'b011x1xxxx001,
12'b010x0100110x,
12'b010x01001110,
12'b1xxx100xx011,
3336,11 → 4183,16
12'b000001010xxx,
12'b001000xxx010,
12'b00101xxxx010,
//12'b011x00xxx010,
//12'b011x1xxxx010,
12'b010x0101010x,
12'b010x01010110,
12'b1xxx0x010000: wr_addr = `WREG_DD;
12'b010000010111,
12'b010100010111,
12'b1xxx00010111,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx00010010,
12'b1xxx00010011,
12'b000011010001,
12'b00000001x011,
12'b000000010001,
3356,8 → 4208,6
12'b000001011xxx,
12'b001000xxx011,
12'b00101xxxx011,
//12'b011x00xxx011,
//12'b011x1xxxx011,
12'b010x0101110x,
12'b010x01011110,
12'b1xxx0x011000: wr_addr = `WREG_EE;
3366,10 → 4216,21
12'b000001100xxx,
12'b001000xxx100,
12'b00101xxxx100,
//12'b011x00xxx100,
//12'b011x1xxxx100,
12'b010x01100110,
12'b1xxx0x100000: wr_addr = `WREG_HH;
12'b010000100111,
12'b010100100111,
12'b1xxx00100010,
12'b1xxx00100011,
12'b1xxx00100111,
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b000000100001,
12'b000000101010,
12'b00000010x011,
3383,8 → 4244,15
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010: wr_addr = `WREG_HL;
12'b1xxx10111010,
12'b1xxx11000010,
12'b1xxx11001010: wr_addr = `WREG_HL;
12'b1xxx01000111: wr_addr = `WREG_II;
12'b010000110111,
12'b010100110001,
12'b1xxx00110111,
12'b1xxx00110010,
12'b1xxx01010100,
12'b010000100001,
12'b010000100011,
12'b010000101010,
3404,6 → 4272,11
12'b0100011010xx,
12'b01000110110x,
12'b010001101111: wr_addr = `WREG_IXL;
12'b010000110001,
12'b010100110111,
12'b1xxx00110110,
12'b1xxx00110011,
12'b1xxx01010101,
12'b010100100001,
12'b010100100011,
12'b010100101010,
3428,8 → 4301,6
12'b000001101xxx,
12'b001000xxx101,
12'b00101xxxx101,
//12'b011x00xxx101,
//12'b011x1xxxx101,
12'b010x01101110,
12'b1xxx0x101000: wr_addr = `WREG_LL;
12'b1xxx01001111: wr_addr = `WREG_RR;
3592,6 → 4463,20
`RD1A,
`RD2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011,
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10100011,
3604,6 → 4489,13
default: zflg_en = 1'b0;
endcase
end
`WR1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10100100,
12'b1xxx10101100: zflg_en = 1'b1;
default: zflg_en = 1'b0;
endcase
end
`WR2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000110100,
4131,6 → 5023,22
12'b1xxx10101000,
12'b1xxx10110000,
12'b1xxx10111000: nflg_ctl = `NFLG_0;
12'b1xxx10000010,
12'b1xxx10000100,
12'b1xxx10001010,
12'b1xxx10001100,
12'b1xxx10010010,
12'b1xxx10010100,
12'b1xxx10011010,
12'b1xxx10011100,
12'b1xxx10100100,
12'b1xxx10101100,
12'b1xxx10110100,
12'b1xxx10111100,
12'b1xxx11000010,
12'b1xxx11000011,
12'b1xxx11001010,
12'b1xxx11001011,
12'b000000101111,
12'b000000110101,
12'b000000xxx101,
/trunk/rtl/top_levl.v
3,7 → 3,7
/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
/** **/
/** Y80 processor test bench Rev 0.0 06/13/2012 **/
/** Y80e processor test bench Rev 0.0 06/18/2012 **/
/** **/
/*******************************************************************************************/
`timescale 1ns / 10ps /* set time scale */
54,7 → 54,7
reg PAT_DONE; /* pattern done flag */
reg TRIG_INT; /* assert interrupt */
reg TRIG_NMI; /* assert nmi */
reg [2:0] PAT_CNT; /* counter to track patterns */
reg [3:0] PAT_CNT; /* counter to track patterns */
reg [15:0] CMP_ERR_L; /* error counter */
 
reg wait_dly; /* wait request state machine */
340,7 → 340,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h1;
PAT_CNT = 5'h1;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("int_ops.vm", rdmem);
351,7 → 351,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h2;
PAT_CNT = 5'h2;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("alu_ops.vm", rdmem);
360,7 → 360,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h3;
PAT_CNT = 5'h3;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("dat_mov.vm", rdmem);
369,7 → 369,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h4;
PAT_CNT = 5'h4;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("bit_ops.vm", rdmem);
378,7 → 378,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h5;
PAT_CNT = 5'h5;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("jmp_ops.vm", rdmem);
387,7 → 387,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h6;
PAT_CNT = 5'h6;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("io_ops.vm", rdmem);
396,7 → 396,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h7;
PAT_CNT = 5'h7;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("180_ops.vm", rdmem);
403,12 → 403,21
$readmemh("180_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 5'h8;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("ez8_ops.vm", rdmem);
$readmemh("ez8_opsd.vm", wrmem);
wait (PAT_DONE);
 
DISABLE_INT = 0; /* interrupt generator on */
DISABLE_WAIT = 0; /* wait generator on */
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h1;
PAT_CNT = 5'h1;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("int_ops.vm", rdmem);
419,7 → 428,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h2;
PAT_CNT = 5'h2;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("alu_ops.vm", rdmem);
428,7 → 437,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h3;
PAT_CNT = 5'h3;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("dat_mov.vm", rdmem);
437,7 → 446,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h4;
PAT_CNT = 5'h4;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("bit_ops.vm", rdmem);
446,7 → 455,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h5;
PAT_CNT = 5'h5;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("jmp_ops.vm", rdmem);
455,7 → 464,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h6;
PAT_CNT = 5'h6;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("io_ops.vm", rdmem);
464,7 → 473,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h7;
PAT_CNT = 5'h7;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("180_ops.vm", rdmem);
471,6 → 480,15
$readmemh("180_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 5'h8;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("ez8_ops.vm", rdmem);
$readmemh("ez8_opsd.vm", wrmem);
wait (PAT_DONE);
 
DISABLE_INT = 0; /* interrupt generator on */
DISABLE_BREQ = 0; /* bus req generator on */
DISABLE_WAIT = 1; /* wait generator off */
477,7 → 495,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h1;
PAT_CNT = 5'h1;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("int_ops.vm", rdmem);
488,7 → 506,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h2;
PAT_CNT = 5'h2;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("alu_ops.vm", rdmem);
497,7 → 515,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h3;
PAT_CNT = 5'h3;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("dat_mov.vm", rdmem);
506,7 → 524,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h4;
PAT_CNT = 5'h4;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("bit_ops.vm", rdmem);
515,7 → 533,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h5;
PAT_CNT = 5'h5;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("jmp_ops.vm", rdmem);
524,7 → 542,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h6;
PAT_CNT = 5'h6;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("io_ops.vm", rdmem);
533,7 → 551,7
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h7;
PAT_CNT = 5'h7;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("180_ops.vm", rdmem);
540,6 → 558,15
$readmemh("180_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 5'h8;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("ez8_ops.vm", rdmem);
$readmemh("ez8_opsd.vm", wrmem);
wait (PAT_DONE);
 
$stop;
end
 
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