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https://opencores.org/ocsvn/y80e/y80e/trunk
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/tags/ez80-instructions/asm/Tasm80.tab
0,0 → 1,833
"TASM Z80 Assembler. " |
/**************************************************************************** |
/* $Id: Tasm80.tab 5931 2012-03-26 12:25:57Z bsa $ |
/**************************************************************************** |
/* This is the instruction set definition table |
/* for the Z80 version of TASM. |
/* Thomas N. Anderson, Speech Technology Incorporated |
/* This table authored and submitted by Carl A. Wall, VE3APY. |
/* |
/* Class bits assigned as follows: |
/* Bit-0 = Z80 (base instruction set) |
/* Bit-1 = HD64180 (extended instructions) |
/* Bit-2 = eZ80 (short address instructions only) |
/* See TASM manual for info on table structure. |
/* |
/*INSTR ARGS OP BYTES RULE CLASS SHIFT OR */ |
/*-------------------------------------------*/ |
|
ADC A,(HL) 8E 1 NOP 1 |
ADC A,(IX*) 8EDD 3 ZIX 1 |
ADC A,(IY*) 8EFD 3 ZIX 1 |
ADC A,A 8F 1 NOP 1 |
ADC A,B 88 1 NOP 1 |
ADC A,C 89 1 NOP 1 |
ADC A,D 8A 1 NOP 1 |
ADC A,E 8B 1 NOP 1 |
ADC A,H 8C 1 NOP 1 |
ADC A,L 8D 1 NOP 1 |
ADC A,XH 8CDD 2 NOP 1 |
ADC A,XL 8DDD 2 NOP 1 |
ADC A,YH 8CFD 2 NOP 1 |
ADC A,YL 8DFD 2 NOP 1 |
ADC A,* CE 2 NOP 1 |
ADC HL,BC 4AED 2 NOP 1 |
ADC HL,DE 5AED 2 NOP 1 |
ADC HL,HL 6AED 2 NOP 1 |
ADC HL,SP 7AED 2 NOP 1 |
|
ADD A,(HL) 86 1 NOP 1 |
ADD A,(IX*) 86DD 3 ZIX 1 |
ADD A,(IY*) 86FD 3 ZIX 1 |
ADD A,A 87 1 NOP 1 |
ADD A,B 80 1 NOP 1 |
ADD A,C 81 1 NOP 1 |
ADD A,D 82 1 NOP 1 |
ADD A,E 83 1 NOP 1 |
ADD A,H 84 1 NOP 1 |
ADD A,L 85 1 NOP 1 |
ADD A,XH 84DD 2 NOP 1 |
ADD A,XL 85DD 2 NOP 1 |
ADD A,YH 84FD 2 NOP 1 |
ADD A,YL 85FD 2 NOP 1 |
ADD A,* C6 2 NOP 1 |
ADD HL,BC 09 1 NOP 1 |
ADD HL,DE 19 1 NOP 1 |
ADD HL,HL 29 1 NOP 1 |
ADD HL,SP 39 1 NOP 1 |
ADD IX,BC 09DD 2 NOP 1 |
ADD IX,DE 19DD 2 NOP 1 |
ADD IX,IX 29DD 2 NOP 1 |
ADD IX,SP 39DD 2 NOP 1 |
ADD IY,BC 09FD 2 NOP 1 |
ADD IY,DE 19FD 2 NOP 1 |
ADD IY,IY 29FD 2 NOP 1 |
ADD IY,SP 39FD 2 NOP 1 |
|
AND (HL) A6 1 NOP 1 |
AND (IX*) A6DD 3 ZIX 1 |
AND (IY*) A6FD 3 ZIX 1 |
AND A A7 1 NOP 1 |
AND B A0 1 NOP 1 |
AND C A1 1 NOP 1 |
AND D A2 1 NOP 1 |
AND E A3 1 NOP 1 |
AND H A4 1 NOP 1 |
AND L A5 1 NOP 1 |
AND XH A4DD 2 NOP 1 |
AND XL A5DD 2 NOP 1 |
AND YH A4FD 2 NOP 1 |
AND YL A5FD 2 NOP 1 |
AND * E6 2 NOP 1 |
|
BIT *,(HL) 46CB 2 ZBIT 1 |
BIT *,(IX*) CBDD 4 ZBIT 1 0 4600 |
BIT *,(IY*) CBFD 4 ZBIT 1 0 4600 |
BIT *,A 47CB 2 ZBIT 1 |
BIT *,B 40CB 2 ZBIT 1 |
BIT *,C 41CB 2 ZBIT 1 |
BIT *,D 42CB 2 ZBIT 1 |
BIT *,E 43CB 2 ZBIT 1 |
BIT *,H 44CB 2 ZBIT 1 |
BIT *,L 45CB 2 ZBIT 1 |
|
CALL C,* DC 3 NOP 1 |
CALL M,* FC 3 NOP 1 |
CALL NC,* D4 3 NOP 1 |
CALL NZ,* C4 3 NOP 1 |
CALL P,* F4 3 NOP 1 |
CALL PE,* EC 3 NOP 1 |
CALL PO,* E4 3 NOP 1 |
CALL Z,* CC 3 NOP 1 |
CALL * CD 3 NOP 1 |
|
CCF "" 3F 1 NOP 1 |
|
CP (HL) BE 1 NOP 1 |
CP (IX*) BEDD 3 ZIX 1 |
CP (IY*) BEFD 3 ZIX 1 |
CP A BF 1 NOP 1 |
CP B B8 1 NOP 1 |
CP C B9 1 NOP 1 |
CP D BA 1 NOP 1 |
CP E BB 1 NOP 1 |
CP H BC 1 NOP 1 |
CP L BD 1 NOP 1 |
CP XH BCDD 2 NOP 1 |
CP XL BDDD 2 NOP 1 |
CP YH BCFD 2 NOP 1 |
CP YL BDFD 2 NOP 1 |
CP * FE 2 NOP 1 |
CPD "" A9ED 2 NOP 1 |
CPDR "" B9ED 2 NOP 1 |
CPIR "" B1ED 2 NOP 1 |
CPI "" A1ED 2 NOP 1 |
CPL "" 2F 1 NOP 1 |
|
DAA "" 27 1 NOP 1 |
|
DEC (HL) 35 1 NOP 1 |
DEC (IX*) 35DD 3 ZIX 1 |
DEC (IY*) 35FD 3 ZIX 1 |
DEC A 3D 1 NOP 1 |
DEC B 05 1 NOP 1 |
DEC BC 0B 1 NOP 1 |
DEC C 0D 1 NOP 1 |
DEC D 15 1 NOP 1 |
DEC DE 1B 1 NOP 1 |
DEC E 1D 1 NOP 1 |
DEC H 25 1 NOP 1 |
DEC HL 2B 1 NOP 1 |
DEC IX 2BDD 2 NOP 1 |
DEC IY 2BFD 2 NOP 1 |
DEC L 2D 1 NOP 1 |
DEC SP 3B 1 NOP 1 |
DEC XH 25DD 2 NOP 1 |
DEC XL 2DDD 2 NOP 1 |
DEC YH 25FD 2 NOP 1 |
DEC YL 2DFD 2 NOP 1 |
|
DI "" F3 1 NOP 1 |
DJNZ * 10 2 R1 1 |
|
EI "" FB 1 NOP 1 |
EX (SP),HL E3 1 NOP 1 |
EX (SP),IX E3DD 2 NOP 1 |
EX (SP),IY E3FD 2 NOP 1 |
EX AF,AF' 08 1 NOP 1 |
EX DE,HL EB 1 NOP 1 |
EXX "" D9 1 NOP 1 |
HALT "" 76 1 NOP 1 |
|
IM 0 46ED 2 NOP 1 |
IM 1 56ED 2 NOP 1 |
IM 2 5EED 2 NOP 1 |
|
IN A,(C) 78ED 2 NOP 1 |
IN B,(C) 40ED 2 NOP 1 |
IN C,(C) 48ED 2 NOP 1 |
IN D,(C) 50ED 2 NOP 1 |
IN E,(C) 58ED 2 NOP 1 |
IN H,(C) 60ED 2 NOP 1 |
IN L,(C) 68ED 2 NOP 1 |
|
IN A,(*) DB 2 NOP 1 |
|
IN0 A,(*) 38ED 3 NOP 2 |
IN0 B,(*) 00ED 3 NOP 2 |
IN0 C,(*) 08ED 3 NOP 2 |
IN0 D,(*) 10ED 3 NOP 2 |
IN0 E,(*) 18ED 3 NOP 2 |
IN0 H,(*) 20ED 3 NOP 2 |
IN0 L,(*) 28ED 3 NOP 2 |
|
INC (HL) 34 1 NOP 1 |
INC (IX*) 34DD 3 ZIX 1 |
INC (IY*) 34FD 3 ZIX 1 |
INC A 3C 1 NOP 1 |
INC B 04 1 NOP 1 |
INC BC 03 1 NOP 1 |
INC C 0C 1 NOP 1 |
INC D 14 1 NOP 1 |
INC DE 13 1 NOP 1 |
INC E 1C 1 NOP 1 |
INC H 24 1 NOP 1 |
INC HL 23 1 NOP 1 |
INC IX 23DD 2 NOP 1 |
INC IY 23FD 2 NOP 1 |
INC L 2C 1 NOP 1 |
INC SP 33 1 NOP 1 |
INC XH 24DD 2 NOP 1 |
INC XL 2CDD 2 NOP 1 |
INC YH 24FD 2 NOP 1 |
INC YL 2CFD 2 NOP 1 |
|
|
IND "" AAED 2 NOP 1 |
IND2 "" 8CED 2 NOP 4 |
IND2R "" 9CED 2 NOP 4 |
INDM "" 8AED 2 NOP 4 |
INDMR "" 9AED 2 NOP 4 |
INDR "" BAED 2 NOP 1 |
INDRX "" CAED 2 NOP 4 |
INI "" A2ED 2 NOP 1 |
INI2 "" 84ED 2 NOP 4 |
INI2R "" 94ED 2 NOP 4 |
INIM "" 82ED 2 NOP 4 |
INIMR "" 92ED 2 NOP 4 |
INIR "" B2ED 2 NOP 1 |
INIRX "" C2ED 2 NOP 4 |
|
JP (HL) E9 1 NOP 1 |
JP (IX) E9DD 2 NOP 1 |
JP (IY) E9FD 2 NOP 1 |
JP C,* DA 3 NOP 1 |
JP M,* FA 3 NOP 1 |
JP NC,* D2 3 NOP 1 |
JP NZ,* C2 3 NOP 1 |
JP P,* F2 3 NOP 1 |
JP PE,* EA 3 NOP 1 |
JP PO,* E2 3 NOP 1 |
JP Z,* CA 3 NOP 1 |
JP * C3 3 NOP 1 |
|
JR C,* 38 2 R1 1 |
JR NC,* 30 2 R1 1 |
JR NZ,* 20 2 R1 1 |
JR Z,* 28 2 R1 1 |
JR * 18 2 R1 1 |
|
LD (BC),A 02 1 NOP 1 |
LD (DE),A 12 1 NOP 1 |
LD (HL),A 77 1 NOP 1 |
LD (HL),B 70 1 NOP 1 |
LD (HL),BC 0FED 2 NOP 4 |
LD (HL),C 71 1 NOP 1 |
LD (HL),D 72 1 NOP 1 |
LD (HL),DE 1FED 2 NOP 4 |
LD (HL),E 73 1 NOP 1 |
LD (HL),H 74 1 NOP 1 |
LD (HL),HL 2FED 2 NOP 4 |
LD (HL),IX 3FED 2 NOP 4 |
LD (HL),IY 3EED 2 NOP 4 |
LD (HL),L 75 1 NOP 1 |
LD (HL),* 36 2 NOP 1 |
LD (IX*),A 77DD 3 ZIX 1 |
LD (IX*),B 70DD 3 ZIX 1 |
LD (IX*),BC 0FDD 3 ZIX 4 |
LD (IX*),C 71DD 3 ZIX 1 |
LD (IX*),D 72DD 3 ZIX 1 |
LD (IX*),DE 1FDD 3 ZIX 4 |
LD (IX*),E 73DD 3 ZIX 1 |
LD (IX*),H 74DD 3 ZIX 1 |
LD (IX*),HL 2FDD 3 ZIX 4 |
LD (IX*),IX 3FDD 3 ZIX 4 |
LD (IX*),IY 3EDD 3 ZIX 4 |
LD (IX*),L 75DD 3 ZIX 1 |
LD (IX*),* 36DD 4 ZIX 1 |
LD (IY*),A 77FD 3 ZIX 1 |
LD (IY*),B 70FD 3 ZIX 1 |
LD (IY*),BC 0FFD 3 ZIX 4 |
LD (IY*),C 71FD 3 ZIX 1 |
LD (IY*),D 72FD 3 ZIX 1 |
LD (IY*),DE 1FFD 3 ZIX 4 |
LD (IY*),E 73FD 3 ZIX 1 |
LD (IY*),H 74FD 3 ZIX 1 |
LD (IY*),HL 2FFD 3 ZIX 4 |
LD (IY*),IX 3EFD 3 ZIX 4 |
LD (IY*),IY 3FFD 3 ZIX 4 |
LD (IY*),L 75FD 3 ZIX 1 |
LD (IY*),* 36FD 4 ZIX 1 |
LD (*),A 32 3 NOP 1 |
LD (*),BC 43ED 4 NOP 1 |
LD (*),DE 53ED 4 NOP 1 |
LD (*),HL 22 3 NOP 1 |
LD (*),IX 22DD 4 NOP 1 |
LD (*),IY 22FD 4 NOP 1 |
LD (*),SP 73ED 4 NOP 1 |
LD A,(BC) 0A 1 NOP 1 |
LD A,(DE) 1A 1 NOP 1 |
LD A,(HL) 7E 1 NOP 1 |
LD A,(IX*) 7EDD 3 ZIX 1 |
LD A,(IY*) 7EFD 3 ZIX 1 |
LD A,A 7F 1 NOP 1 |
LD A,B 78 1 NOP 1 |
LD A,C 79 1 NOP 1 |
LD A,D 7A 1 NOP 1 |
LD A,E 7B 1 NOP 1 |
LD A,H 7C 1 NOP 1 |
LD A,I 57ED 2 NOP 1 |
LD A,L 7D 1 NOP 1 |
LD A,R 5FED 2 NOP 1 |
LD A,XH 7CDD 2 NOP 1 |
LD A,XL 7DDD 2 NOP 1 |
LD A,YH 7CFD 2 NOP 1 |
LD A,YL 7DFD 2 NOP 1 |
LD A,(*) 3A 3 NOP 1 |
LD A,* 3E 2 NOP 1 |
LD B,(HL) 46 1 NOP 1 |
LD B,(IX*) 46DD 3 ZIX 1 |
LD B,(IY*) 46FD 3 ZIX 1 |
LD B,A 47 1 NOP 1 |
LD B,B 40 1 NOP 1 |
LD B,C 41 1 NOP 1 |
LD B,D 42 1 NOP 1 |
LD B,E 43 1 NOP 1 |
LD B,H 44 1 NOP 1 |
LD B,L 45 1 NOP 1 |
LD B,XH 44DD 2 NOP 1 |
LD B,XL 45DD 2 NOP 1 |
LD B,YH 44FD 2 NOP 1 |
LD B,YL 45FD 2 NOP 1 |
LD B,* 06 2 NOP 1 |
LD BC,(HL) 07ED 2 NOP 4 |
LD BC,(IX*) 07DD 3 ZIX 4 |
LD BC,(IY*) 07FD 3 ZIX 4 |
LD BC,(*) 4BED 4 NOP 1 |
LD BC,* 01 3 NOP 1 |
LD C,(HL) 4E 1 NOP 1 |
LD C,(IX*) 4EDD 3 ZIX 1 |
LD C,(IY*) 4EFD 3 ZIX 1 |
LD C,A 4F 1 NOP 1 |
LD C,B 48 1 NOP 1 |
LD C,C 49 1 NOP 1 |
LD C,D 4A 1 NOP 1 |
LD C,E 4B 1 NOP 1 |
LD C,H 4C 1 NOP 1 |
LD C,L 4D 1 NOP 1 |
LD C,XH 4CDD 2 NOP 1 |
LD C,XL 4DDD 2 NOP 1 |
LD C,YH 4CFD 2 NOP 1 |
LD C,YL 4DFD 2 NOP 1 |
LD C,* 0E 2 NOP 1 |
LD D,(HL) 56 1 NOP 1 |
LD D,(IX*) 56DD 3 ZIX 1 |
LD D,(IY*) 56FD 3 ZIX 1 |
LD D,A 57 1 NOP 1 |
LD D,B 50 1 NOP 1 |
LD D,C 51 1 NOP 1 |
LD D,D 52 1 NOP 1 |
LD D,E 53 1 NOP 1 |
LD D,H 54 1 NOP 1 |
LD D,L 55 1 NOP 1 |
LD D,XH 54DD 2 NOP 1 |
LD D,XL 55DD 2 NOP 1 |
LD D,YH 54FD 2 NOP 1 |
LD D,YL 55FD 2 NOP 1 |
LD D,* 16 2 NOP 1 |
LD DE,(HL) 17ED 2 NOP 4 |
LD DE,(IX*) 17DD 3 ZIX 4 |
LD DE,(IY*) 17FD 3 ZIX 4 |
LD DE,(*) 5BED 4 NOP 1 |
LD DE,* 11 3 NOP 1 |
LD E,(HL) 5E 1 NOP 1 |
LD E,(IX*) 5EDD 3 ZIX 1 |
LD E,(IY*) 5EFD 3 ZIX 1 |
LD E,A 5F 1 NOP 1 |
LD E,B 58 1 NOP 1 |
LD E,C 59 1 NOP 1 |
LD E,D 5A 1 NOP 1 |
LD E,E 5B 1 NOP 1 |
LD E,H 5C 1 NOP 1 |
LD E,L 5D 1 NOP 1 |
LD E,XH 5CDD 2 NOP 1 |
LD E,XL 5DDD 2 NOP 1 |
LD E,YH 5CFD 2 NOP 1 |
LD E,YL 5DFD 2 NOP 1 |
LD E,* 1E 2 NOP 1 |
LD HL,(HL) 27ED 2 NOP 4 |
LD HL,(IX*) 27DD 3 ZIX 4 |
LD HL,(IY*) 27FD 3 ZIX 4 |
LD H,(HL) 66 1 NOP 1 |
LD H,(IX*) 66DD 3 ZIX 1 |
LD H,(IY*) 66FD 3 ZIX 1 |
LD H,A 67 1 NOP 1 |
LD H,B 60 1 NOP 1 |
LD H,C 61 1 NOP 1 |
LD H,D 62 1 NOP 1 |
LD H,E 63 1 NOP 1 |
LD H,H 64 1 NOP 1 |
LD H,L 65 1 NOP 1 |
LD H,* 26 2 NOP 1 |
LD HL,(*) 2A 3 NOP 1 |
LD HL,* 21 3 NOP 1 |
LD I,A 47ED 2 NOP 1 |
LD IX,(HL) 37ED 2 NOP 4 |
LD IX,(IX*) 37DD 3 ZIX 4 |
LD IX,(IY*) 31FD 3 ZIX 4 |
LD IX,(*) 2ADD 4 NOP 1 |
LD IX,* 21DD 4 NOP 1 |
LD IY,(HL) 36ED 2 NOP 4 |
LD IY,(IX*) 31DD 3 ZIX 4 |
LD IY,(IY*) 37FD 3 ZIX 4 |
LD IY,(*) 2AFD 4 NOP 1 |
LD IY,* 21FD 4 NOP 1 |
LD L,(HL) 6E 1 NOP 1 |
LD L,(IX*) 6EDD 3 ZIX 1 |
LD L,(IY*) 6EFD 3 ZIX 1 |
LD L,A 6F 1 NOP 1 |
LD L,B 68 1 NOP 1 |
LD L,C 69 1 NOP 1 |
LD L,D 6A 1 NOP 1 |
LD L,E 6B 1 NOP 1 |
LD L,H 6C 1 NOP 1 |
LD L,L 6D 1 NOP 1 |
LD L,* 2E 2 NOP 1 |
LD R,A 4FED 2 NOP 1 |
LD SP,(*) 7BED 4 NOP 1 |
LD SP,HL F9 1 NOP 1 |
LD SP,IX F9DD 2 NOP 1 |
LD SP,IY F9FD 2 NOP 1 |
LD SP,* 31 3 NOP 1 |
LD XH,A 67DD 2 NOP 1 |
LD XH,B 60DD 2 NOP 1 |
LD XH,C 61DD 2 NOP 1 |
LD XH,D 62DD 2 NOP 1 |
LD XH,E 63DD 2 NOP 1 |
LD XH,XH 64DD 2 NOP 1 |
LD XH,XL 65DD 2 NOP 1 |
LD XH,* 26DD 3 NOP 1 |
LD XL,A 6FDD 2 NOP 1 |
LD XL,B 68DD 2 NOP 1 |
LD XL,C 69DD 2 NOP 1 |
LD XL,D 6ADD 2 NOP 1 |
LD XL,E 6BDD 2 NOP 1 |
LD XL,XH 6CDD 2 NOP 1 |
LD XL,XL 6DDD 2 NOP 1 |
LD XL,* 2EDD 3 NOP 1 |
LD YH,A 67FD 2 NOP 1 |
LD YH,B 60FD 2 NOP 1 |
LD YH,C 61FD 2 NOP 1 |
LD YH,D 62FD 2 NOP 1 |
LD YH,E 63FD 2 NOP 1 |
LD YH,YH 64FD 2 NOP 1 |
LD YH,YL 65FD 2 NOP 1 |
LD YH,* 26FD 3 NOP 1 |
LD YL,A 6FFD 2 NOP 1 |
LD YL,B 68FD 2 NOP 1 |
LD YL,C 69FD 2 NOP 1 |
LD YL,D 6AFD 2 NOP 1 |
LD YL,E 6BFD 2 NOP 1 |
LD YL,YH 6CFD 2 NOP 1 |
LD YL,YL 6DFD 2 NOP 1 |
LD YL,* 2EFD 3 NOP 1 |
|
LDD "" A8ED 2 NOP 1 |
LDDR "" B8ED 2 NOP 1 |
LDI "" A0ED 2 NOP 1 |
LDIR "" B0ED 2 NOP 1 |
|
LEA BC,IX* 02ED 3 ZIX 4 |
LEA BC,IY* 03ED 3 ZIX 4 |
LEA DE,IX* 12ED 3 ZIX 4 |
LEA DE,IY* 13ED 3 ZIX 4 |
LEA HL,IX* 22ED 3 ZIX 4 |
LEA HL,IY* 23ED 3 ZIX 4 |
LEA IX,IX* 32ED 3 ZIX 4 |
LEA IX,IY* 54ED 3 ZIX 4 |
LEA IY,IX* 55ED 3 ZIX 4 |
LEA IY,IY* 33ED 3 ZIX 4 |
|
NEG "" 44ED 2 NOP 1 |
NOP "" 00 1 NOP 1 |
|
MLT BC 4CED 2 NOP 2 |
MLT DE 5CED 2 NOP 2 |
MLT HL 6CED 2 NOP 2 |
MLT SP 7CED 2 NOP 2 |
|
OR (HL) B6 1 NOP 1 |
OR (IX*) B6DD 3 ZIX 1 |
OR (IY*) B6FD 3 ZIX 1 |
OR A B7 1 NOP 1 |
OR B B0 1 NOP 1 |
OR C B1 1 NOP 1 |
OR D B2 1 NOP 1 |
OR E B3 1 NOP 1 |
OR H B4 1 NOP 1 |
OR L B5 1 NOP 1 |
OR XH B4DD 2 NOP 1 |
OR XL B5DD 2 NOP 1 |
OR YH B4FD 2 NOP 1 |
OR YL B5FD 2 NOP 1 |
OR * F6 2 NOP 1 |
|
OUTD2 "" ACED 2 NOP 4 |
OTD2R "" BCED 2 NOP 4 |
OTDM "" 8BED 2 NOP 2 |
OTDMR "" 9BED 2 NOP 2 |
OTDR "" BBED 2 NOP 1 |
OTDRX "" CBED 2 NOP 4 |
OUTI2 "" A4ED 2 NOP 4 |
OTI2R "" B4ED 2 NOP 4 |
OTIM "" 83ED 2 NOP 2 |
OTIMR "" 93ED 2 NOP 2 |
OTIR "" B3ED 2 NOP 1 |
OTIRX "" C3ED 2 NOP 4 |
|
OUT (C),A 79ED 2 NOP 1 |
OUT (C),B 41ED 2 NOP 1 |
OUT (C),C 49ED 2 NOP 1 |
OUT (C),D 51ED 2 NOP 1 |
OUT (C),E 59ED 2 NOP 1 |
OUT (C),H 61ED 2 NOP 1 |
OUT (C),L 69ED 2 NOP 1 |
OUT (*),A D3 2 NOP 1 |
|
OUT0 (*),A 39ED 3 NOP 2 |
OUT0 (*),B 01ED 3 NOP 2 |
OUT0 (*),C 09ED 3 NOP 2 |
OUT0 (*),D 11ED 3 NOP 2 |
OUT0 (*),E 19ED 3 NOP 2 |
OUT0 (*),H 21ED 3 NOP 2 |
OUT0 (*),L 29ED 3 NOP 2 |
|
OUTD "" ABED 2 NOP 1 |
OUTI "" A3ED 2 NOP 1 |
|
PEA IX* 65ED 3 ZIX 4 |
PEA IY* 66ED 3 ZIX 4 |
|
POP AF F1 1 NOP 1 |
POP BC C1 1 NOP 1 |
POP DE D1 1 NOP 1 |
POP HL E1 1 NOP 1 |
POP IX E1DD 2 NOP 1 |
POP IY E1FD 2 NOP 1 |
|
PUSH AF F5 1 NOP 1 |
PUSH BC C5 1 NOP 1 |
PUSH DE D5 1 NOP 1 |
PUSH HL E5 1 NOP 1 |
PUSH IX E5DD 2 NOP 1 |
PUSH IY E5FD 2 NOP 1 |
|
RES *,(HL) 86CB 2 ZBIT 1 |
RES *,(IX*) CBDD 4 ZBIT 1 0 8600 |
/*RES *,(IX*),A CBDD 4 ZBIT 1 0 8700 |
/*RES *,(IX*),B CBDD 4 ZBIT 1 0 8000 |
/*RES *,(IX*),C CBDD 4 ZBIT 1 0 8100 |
/*RES *,(IX*),D CBDD 4 ZBIT 1 0 8200 |
/*RES *,(IX*),E CBDD 4 ZBIT 1 0 8300 |
/*RES *,(IX*),H CBDD 4 ZBIT 1 0 8400 |
/*RES *,(IX*),L CBDD 4 ZBIT 1 0 8500 |
RES *,(IY*) CBFD 4 ZBIT 1 0 8600 |
/*RES *,(IY*),A CBFD 4 ZBIT 1 0 8700 |
/*RES *,(IY*),B CBFD 4 ZBIT 1 0 8000 |
/*RES *,(IY*),C CBFD 4 ZBIT 1 0 8100 |
/*RES *,(IY*),D CBFD 4 ZBIT 1 0 8200 |
/*RES *,(IY*),E CBFD 4 ZBIT 1 0 8300 |
/*RES *,(IY*),H CBFD 4 ZBIT 1 0 8400 |
/*RES *,(IY*),L CBFD 4 ZBIT 1 0 8500 |
RES *,A 87CB 2 ZBIT 1 |
RES *,B 80CB 2 ZBIT 1 |
RES *,C 81CB 2 ZBIT 1 |
RES *,D 82CB 2 ZBIT 1 |
RES *,E 83CB 2 ZBIT 1 |
RES *,H 84CB 2 ZBIT 1 |
RES *,L 85CB 2 ZBIT 1 |
|
RET "" C9 1 NOP 1 |
RET C D8 1 NOP 1 |
RET M F8 1 NOP 1 |
RET NC D0 1 NOP 1 |
RET NZ C0 1 NOP 1 |
RET P F0 1 NOP 1 |
RET PE E8 1 NOP 1 |
RET PO E0 1 NOP 1 |
RET Z C8 1 NOP 1 |
RETI "" 4DED 2 NOP 1 |
RETN "" 45ED 2 NOP 1 |
|
RL (HL) 16CB 2 NOP 1 |
RL (IX*) CBDD 4 ZIX 1 0 1600 |
/*RL (IX*),A CBDD 4 ZIX 1 0 1700 |
/*RL (IX*),B CBDD 4 ZIX 1 0 1000 |
/*RL (IX*),C CBDD 4 ZIX 1 0 1100 |
/*RL (IX*),D CBDD 4 ZIX 1 0 1200 |
/*RL (IX*),E CBDD 4 ZIX 1 0 1300 |
/*RL (IX*),H CBDD 4 ZIX 1 0 1400 |
/*RL (IX*),L CBDD 4 ZIX 1 0 1500 |
RL (IY*) CBFD 4 ZIX 1 0 1600 |
/*RL (IY*),A CBFD 4 ZIX 1 0 1700 |
/*RL (IY*),B CBFD 4 ZIX 1 0 1000 |
/*RL (IY*),C CBFD 4 ZIX 1 0 1100 |
/*RL (IY*),D CBFD 4 ZIX 1 0 1200 |
/*RL (IY*),E CBFD 4 ZIX 1 0 1300 |
/*RL (IY*),H CBFD 4 ZIX 1 0 1400 |
/*RL (IY*),L CBFD 4 ZIX 1 0 1500 |
RL A 17CB 2 NOP 1 |
RL B 10CB 2 NOP 1 |
RL C 11CB 2 NOP 1 |
RL D 12CB 2 NOP 1 |
RL E 13CB 2 NOP 1 |
RL H 14CB 2 NOP 1 |
RL L 15CB 2 NOP 1 |
RLA "" 17 1 NOP 1 |
|
RLC (HL) 06CB 2 NOP 1 |
RLC (IX*) CBDD 4 ZIX 1 0 0600 |
/*RLC (IX*),A CBDD 4 ZIX 1 0 0700 |
/*RLC (IX*),B CBDD 4 ZIX 1 0 0000 |
/*RLC (IX*),C CBDD 4 ZIX 1 0 0100 |
/*RLC (IX*),D CBDD 4 ZIX 1 0 0200 |
/*RLC (IX*),E CBDD 4 ZIX 1 0 0300 |
/*RLC (IX*),H CBDD 4 ZIX 1 0 0400 |
/*RLC (IX*),L CBDD 4 ZIX 1 0 0500 |
RLC (IY*) CBFD 4 ZIX 1 0 0600 |
/*RLC (IY*),A CBFD 4 ZIX 1 0 0700 |
/*RLC (IY*),B CBFD 4 ZIX 1 0 0000 |
/*RLC (IY*),C CBFD 4 ZIX 1 0 0100 |
/*RLC (IY*),D CBFD 4 ZIX 1 0 0200 |
/*RLC (IY*),E CBFD 4 ZIX 1 0 0300 |
/*RLC (IY*),H CBFD 4 ZIX 1 0 0400 |
/*RLC (IY*),L CBFD 4 ZIX 1 0 0500 |
RLC A 07CB 2 NOP 1 |
RLC B 00CB 2 NOP 1 |
RLC C 01CB 2 NOP 1 |
RLC D 02CB 2 NOP 1 |
RLC E 03CB 2 NOP 1 |
RLC H 04CB 2 NOP 1 |
RLC L 05CB 2 NOP 1 |
RLCA "" 07 1 NOP 1 |
|
RLD "" 6FED 2 NOP 1 |
|
RR (HL) 1ECB 2 NOP 1 |
RR (IX*) CBDD 4 ZIX 1 0 1E00 |
/*RR (IX*),A CBDD 4 ZIX 1 0 1F00 |
/*RR (IX*),B CBDD 4 ZIX 1 0 1800 |
/*RR (IX*),C CBDD 4 ZIX 1 0 1900 |
/*RR (IX*),D CBDD 4 ZIX 1 0 1A00 |
/*RR (IX*),E CBDD 4 ZIX 1 0 1B00 |
/*RR (IX*),H CBDD 4 ZIX 1 0 1C00 |
/*RR (IX*),L CBDD 4 ZIX 1 0 1D00 |
RR (IY*) CBFD 4 ZIX 1 0 1E00 |
/*RR (IY*),A CBFD 4 ZIX 1 0 1F00 |
/*RR (IY*),B CBFD 4 ZIX 1 0 1800 |
/*RR (IY*),C CBFD 4 ZIX 1 0 1900 |
/*RR (IY*),D CBFD 4 ZIX 1 0 1A00 |
/*RR (IY*),E CBFD 4 ZIX 1 0 1B00 |
/*RR (IY*),H CBFD 4 ZIX 1 0 1C00 |
/*RR (IY*),L CBFD 4 ZIX 1 0 1D00 |
RR A 1FCB 2 NOP 1 |
RR B 18CB 2 NOP 1 |
RR C 19CB 2 NOP 1 |
RR D 1ACB 2 NOP 1 |
RR E 1BCB 2 NOP 1 |
RR H 1CCB 2 NOP 1 |
RR L 1DCB 2 NOP 1 |
RRA "" 1F 1 NOP 1 |
|
RRC (HL) 0ECB 2 NOP 1 |
RRC (IX*) CBDD 4 ZIX 1 0 0E00 |
/*RRC (IX*),A CBDD 4 ZIX 1 0 0F00 |
/*RRC (IX*),B CBDD 4 ZIX 1 0 0800 |
/*RRC (IX*),C CBDD 4 ZIX 1 0 0900 |
/*RRC (IX*),D CBDD 4 ZIX 1 0 0A00 |
/*RRC (IX*),E CBDD 4 ZIX 1 0 0B00 |
/*RRC (IX*),H CBDD 4 ZIX 1 0 0C00 |
/*RRC (IX*),L CBDD 4 ZIX 1 0 0D00 |
RRC (IY*) CBFD 4 ZIX 1 0 0E00 |
/*RRC (IY*),A CBFD 4 ZIX 1 0 0F00 |
/*RRC (IY*),B CBFD 4 ZIX 1 0 0800 |
/*RRC (IY*),C CBFD 4 ZIX 1 0 0900 |
/*RRC (IY*),D CBFD 4 ZIX 1 0 0A00 |
/*RRC (IY*),E CBFD 4 ZIX 1 0 0B00 |
/*RRC (IY*),H CBFD 4 ZIX 1 0 0C00 |
/*RRC (IY*),L CBFD 4 ZIX 1 0 0D00 |
RRC A 0FCB 2 NOP 1 |
RRC B 08CB 2 NOP 1 |
RRC C 09CB 2 NOP 1 |
RRC D 0ACB 2 NOP 1 |
RRC E 0BCB 2 NOP 1 |
RRC H 0CCB 2 NOP 1 |
RRC L 0DCB 2 NOP 1 |
RRCA "" 0F 1 NOP 1 |
|
RRD "" 67ED 2 NOP 1 |
|
RST 00H C7 1 NOP 1 |
RST 08H CF 1 NOP 1 |
RST 10H D7 1 NOP 1 |
RST 18H DF 1 NOP 1 |
RST 20H E7 1 NOP 1 |
RST 28H EF 1 NOP 1 |
RST 30H F7 1 NOP 1 |
RST 38H FF 1 NOP 1 |
|
SBC A,(HL) 9E 1 NOP 1 |
SBC A,(IX*) 9EDD 3 ZIX 1 |
SBC A,(IY*) 9EFD 3 ZIX 1 |
SBC A,A 9F 1 NOP 1 |
SBC A,B 98 1 NOP 1 |
SBC A,C 99 1 NOP 1 |
SBC A,D 9A 1 NOP 1 |
SBC A,E 9B 1 NOP 1 |
SBC A,H 9C 1 NOP 1 |
SBC A,L 9D 1 NOP 1 |
SBC A,XH 9CDD 2 NOP 1 |
SBC A,XL 9DDD 2 NOP 1 |
SBC A,YH 9CFD 2 NOP 1 |
SBC A,YL 9DFD 2 NOP 1 |
SBC HL,BC 42ED 2 NOP 1 |
SBC HL,DE 52ED 2 NOP 1 |
SBC HL,HL 62ED 2 NOP 1 |
SBC HL,SP 72ED 2 NOP 1 |
SBC A,* DE 2 NOP 1 |
SCF "" 37 1 NOP 1 |
|
SET *,(HL) C6CB 2 ZBIT 1 |
SET *,(IX*) CBDD 4 ZBIT 1 0 C600 |
/*SET *,(IX*),A CBDD 4 ZBIT 1 0 C700 |
/*SET *,(IX*),B CBDD 4 ZBIT 1 0 C000 |
/*SET *,(IX*),C CBDD 4 ZBIT 1 0 C100 |
/*SET *,(IX*),D CBDD 4 ZBIT 1 0 C200 |
/*SET *,(IX*),E CBDD 4 ZBIT 1 0 C300 |
/*SET *,(IX*),H CBDD 4 ZBIT 1 0 C400 |
/*SET *,(IX*),L CBDD 4 ZBIT 1 0 C500 |
SET *,(IY*) CBFD 4 ZBIT 1 0 C600 |
/*SET *,(IY*),A CBFD 4 ZBIT 1 0 C700 |
/*SET *,(IY*),B CBFD 4 ZBIT 1 0 C000 |
/*SET *,(IY*),C CBFD 4 ZBIT 1 0 C100 |
/*SET *,(IY*),D CBFD 4 ZBIT 1 0 C200 |
/*SET *,(IY*),E CBFD 4 ZBIT 1 0 C300 |
/*SET *,(IY*),H CBFD 4 ZBIT 1 0 C400 |
/*SET *,(IY*),L CBFD 4 ZBIT 1 0 C500 |
SET *,A C7CB 2 ZBIT 1 |
SET *,B C0CB 2 ZBIT 1 |
SET *,C C1CB 2 ZBIT 1 |
SET *,D C2CB 2 ZBIT 1 |
SET *,E C3CB 2 ZBIT 1 |
SET *,H C4CB 2 ZBIT 1 |
SET *,L C5CB 2 ZBIT 1 |
|
SLA (HL) 26CB 2 NOP 1 |
SLA (IX*) CBDD 4 ZIX 1 0 2600 |
SLA (IY*) CBFD 4 ZIX 1 0 2600 |
SLA A 27CB 2 NOP 1 |
SLA B 20CB 2 NOP 1 |
SLA C 21CB 2 NOP 1 |
SLA D 22CB 2 NOP 1 |
SLA E 23CB 2 NOP 1 |
SLA H 24CB 2 NOP 1 |
SLA L 25CB 2 NOP 1 |
|
SLI (HL) 36CB 2 NOP 1 |
SLI (IX*) CBDD 4 ZIX 1 0 3600 |
SLI (IY*) CBFD 4 ZIX 1 0 3600 |
SLI A 37CB 2 NOP 1 |
SLI B 30CB 2 NOP 1 |
SLI C 31CB 2 NOP 1 |
SLI D 32CB 2 NOP 1 |
SLI E 33CB 2 NOP 1 |
SLI H 34CB 2 NOP 1 |
SLI L 35CB 2 NOP 1 |
|
SLP "" 76ED 2 NOP 2 |
|
SRA (HL) 2ECB 2 NOP 1 |
SRA (IX*) CBDD 4 ZIX 1 0 2E00 |
SRA (IY*) CBFD 4 ZIX 1 0 2E00 |
SRA A 2FCB 2 NOP 1 |
SRA B 28CB 2 NOP 1 |
SRA C 29CB 2 NOP 1 |
SRA D 2ACB 2 NOP 1 |
SRA E 2BCB 2 NOP 1 |
SRA H 2CCB 2 NOP 1 |
SRA L 2DCB 2 NOP 1 |
|
SRL (HL) 3ECB 2 NOP 1 |
SRL (IX*) CBDD 4 ZIX 1 0 3E00 |
SRL (IY*) CBFD 4 ZIX 1 0 3E00 |
SRL A 3FCB 2 NOP 1 |
SRL B 38CB 2 NOP 1 |
SRL C 39CB 2 NOP 1 |
SRL D 3ACB 2 NOP 1 |
SRL E 3BCB 2 NOP 1 |
SRL H 3CCB 2 NOP 1 |
SRL L 3DCB 2 NOP 1 |
|
SUB (HL) 96 1 NOP 1 |
SUB (IX*) 96DD 3 ZIX 1 |
SUB (IY*) 96FD 3 ZIX 1 |
SUB A 97 1 NOP 1 |
SUB B 90 1 NOP 1 |
SUB C 91 1 NOP 1 |
SUB D 92 1 NOP 1 |
SUB E 93 1 NOP 1 |
SUB H 94 1 NOP 1 |
SUB L 95 1 NOP 1 |
SUB XH 94DD 2 NOP 1 |
SUB XL 95DD 2 NOP 1 |
SUB YH 94FD 2 NOP 1 |
SUB YL 95FD 2 NOP 1 |
SUB * D6 2 NOP 1 |
|
TST A 3CED 2 NOP 2 |
TST B 04ED 2 NOP 2 |
TST C 0CED 2 NOP 2 |
TST D 14ED 2 NOP 2 |
TST E 1CED 2 NOP 2 |
TST H 24ED 2 NOP 2 |
TST L 2CED 2 NOP 2 |
TST (HL) 34ED 2 NOP 2 |
TST * 64ED 3 NOP 2 |
|
TSTIO * 74ED 3 NOP 2 |
|
XOR (HL) AE 1 NOP 1 |
XOR (IX*) AEDD 3 ZIX 1 |
XOR (IY*) AEFD 3 ZIX 1 |
XOR A AF 1 NOP 1 |
XOR B A8 1 NOP 1 |
XOR C A9 1 NOP 1 |
XOR D AA 1 NOP 1 |
XOR E AB 1 NOP 1 |
XOR H AC 1 NOP 1 |
XOR L AD 1 NOP 1 |
XOR XH ACDD 2 NOP 1 |
XOR XL ADDD 2 NOP 1 |
XOR YH ACFD 2 NOP 1 |
XOR YL ADFD 2 NOP 1 |
XOR * EE 2 NOP 1 |
/tags/ez80-instructions/asm/ez8_ops.s
0,0 → 1,504
;********************************************************************************** |
;* * |
;* checks ez80 specific instructions * |
;* * |
;********************************************************************************** |
aseg |
|
org 00h |
jp 01000h |
|
org 038h |
jp (hl) |
|
org 066h |
jp (ix) |
|
org 80h |
db 00h, 01h, 2dh, 03h, 04h, 05h, 06h, 07h |
db 0fh, 1eh, 02h, 3ch, 4bh, 5ah, 69h, 78h |
|
org 0c0h ;pattern finish location |
nop |
jr 0c0h |
|
org 0d0h |
db 071h, 018h, 006h, 005h, 002h, 003h, 004h, 0aah |
|
org 0e0h |
dw 0abcdh, 0fe10h, 03254h, 07698h |
|
org 00140h |
db 061h |
|
org 00241h |
db 002h |
|
org 00342h |
db 033h |
|
org 00443h |
db 0f4h |
|
org 00544h |
db 0e5h |
|
org 00645h |
db 0a6h |
|
org 00165h |
db 061h |
|
org 00264h |
db 002h |
|
org 00363h |
db 033h |
|
org 00462h |
db 0f4h |
|
org 00561h |
db 0e5h |
|
org 00660h |
db 0a6h |
|
org 01000h |
di |
xor a |
ld sp, 00000h |
ld bc, 00123h |
ld de, 04567h |
ld hl, 0d000h |
ld ix, 089abh |
ld iy, 0cdefh |
|
ld (hl),bc ;0123h @ d000h |
inc hl |
inc hl |
ld (hl),de ;4567h @ d002h |
inc hl |
inc hl |
ld (hl),hl ;d004h @ d004h |
inc hl |
inc hl |
ld (hl),ix ;89abh @ d006h |
inc hl |
inc hl |
ld (hl),iy ;cdefh @ d008h |
|
pea ix+055h ;8a00h @ fffeh |
pea iy-055h ;cd9ah @ fffch |
push ix ;89abh @ fffah |
push iy ;cdefh @ fff8h |
|
ld ix, 0e080h |
ld iy, 0dff0h |
ld (ix-040h),bc ;0123h @ e040h |
ld (ix-03eh),de ;4567h @ e042h |
ld (ix-03ch),hl ;d008h @ e044h |
ld (ix-03ah),ix ;e080h @ e046h |
ld (ix-038h),iy ;dff0h @ e048h |
ld (iy+050h),bc ;0123h @ e040h |
ld (iy+052h),de ;4567h @ e042h |
ld (iy+054h),hl ;d008h @ e044h |
ld (iy+056h),ix ;e080h @ e046h |
ld (iy+058h),iy ;dff0h @ e048h |
|
ld ix,02004h |
ld bc,(ix-04h) |
ld de,(ix-02h) |
ld hl,(ix+00h) |
ld iy,(ix+02h) |
ld ix,(ix+04h) |
push bc ;dbach @ fff6h |
push de ;5183h @ fff4h |
push hl ;e800h @ fff2h |
push iy ;7e4dh @ fff0h |
push ix ;9a1fh @ ffeeh |
|
ld bc,(hl) |
inc hl |
inc hl |
ld de,(hl) |
inc hl |
inc hl |
ld ix,(hl) |
inc hl |
inc hl |
ld iy,(hl) |
inc hl |
inc hl |
ld hl,(hl) |
push bc ;0123h @ ffech |
push de ;4567h @ ffeah |
push hl ;cdefh @ ffe8h |
push ix ;89abh @ ffe6h |
push iy ;2006h @ ffe4h |
|
ld bc,(iy-06h) |
ld de,(iy-04h) |
ld hl,(iy-02h) |
ld ix,(iy+00h) |
ld iy,(iy+02h) |
push bc ;dbach @ ffe2h |
push de ;5183h @ ffe0h |
push hl ;e800h @ ffdeh |
push ix ;7e4dh @ ffdch |
push iy ;9a1fh @ ffdah |
|
lea bc,ix-2 |
lea de,ix-1 |
lea hl,ix+0 |
lea iy,ix+1 |
lea ix,ix+2 |
push bc ;7e4bh @ ffd8h |
push de ;7e4ch @ ffd6h |
push hl ;7e4dh @ ffd4h |
push ix ;7e4fh @ ffd2h |
push iy ;7e4eh @ ffd0h |
|
ld iy, 0aa00h |
|
lea bc,iy-2 |
lea de,iy-1 |
lea hl,iy+0 |
lea ix,iy+1 |
lea iy,iy+2 |
push bc ;a9feh @ ffceh |
push de ;a9ffh @ ffcah |
push hl ;aa00h @ ffcch |
push ix ;aa01h @ ffc8h |
push iy ;aa02h @ ffc6h |
push af ;0044h @ ffc4h |
|
;--------- |
|
ld sp,0ff00h |
xor a |
ld hl, 0d700h |
ld de, 00304h |
ld bc, 006d0h |
jp 011feh |
org 011feh |
inim ;read 71h @ 00d0h |
;write 71h @ d700h |
push af ;0006h @ fefeh |
push bc ;05d1h @ fefch |
push hl ;d701h @ fefah |
jp 012feh |
org 012feh |
inimr ;read 18h @ 00d1h |
;write 18h @ d701h |
;read 06h @ 00d2h |
;write 06h @ d702h |
;read 05h @ 00d3h |
;write 05h @ d703h |
;read 02h @ 00d4h |
;write 02h @ d704h |
;read 03h @ 00d5h |
;write 03h @ d705h |
push af ;0046h @ fef8h |
push bc ;00d6h @ fef6h |
push hl ;d706h @ fef4h |
ld b,1 |
jp 013ffh |
org 013ffh |
inimr ;read 04h @ 00d6h |
;write 04h @ d706h |
push af ;0046h @ fef2h |
push bc ;00d7h @ fef0h |
push hl ;d707h @ feeeh |
inc b |
jp 014ffh |
org 014ffh |
inim ;read aah @ 00d7h |
;write aah @ d707h |
push af ;0042h @ feech |
push bc ;00d8h @ feeah |
push hl ;d708h @ fee8h |
ld hl, 0d707h |
ld bc, 006d7h |
jp 015feh |
org 015feh |
indm ;read aah @ 0037h |
;write aah @ d707h |
push af ;0002h @ fee6h |
push bc ;05d6h @ fee4h |
push hl ;d706h @ fee2h |
jp 016feh |
org 016feh |
indmr ;read 04h @ 00d6h |
;write 04h @ d706h |
;read 03h @ 00d5h |
;write 03h @ d705h |
;read 02h @ 00d4h |
;write 02h @ d704h |
;read 05h @ 00d3h |
;write 05h @ d703h |
;read 06h @ 00d2h |
;write 06h @ d702h |
push af ;0042h @ fee0h |
push bc ;00d1h @ fedeh |
push hl ;d701h @ fedch |
inc b |
xor 0aah |
jp 017ffh |
org 017ffh |
indmr ;read 18h @ 00d1h |
;write 18h @ d701h |
push af ;aac6h @ fedah |
push bc ;00d0h @ fed8h |
push hl ;d700h @ fed6h |
inc b |
jp 018ffh |
org 018ffh |
indm ;read 71h @ 00d0h |
;write 71h @ d700h |
push af ;aa42h @ fed4h |
push bc ;00cfh @ fed2h |
push de ;0304h @ fed0h |
push hl ;d6ffh @ feceh |
|
;--------- |
ld sp, 0fe00h |
xor a |
ld hl, 0d901h |
ld bc, 00241h |
jp 019feh |
org 019feh |
ind2 ;read 60h @ 0041h |
;write 60h @ d901h |
push af ;0006h @ fdfeh |
push bc ;01d0h @ fdfch |
push hl ;d900h @ fdfah |
ld a, 055h |
jp 01affh |
org 01affh |
ind2 ;read 02h @ 0040h |
;write 02h @ d900h |
push af ;5546h @ fdf8h |
push bc ;00cfh @ fdf6h |
push hl ;d8ffh @ fdf4h |
|
xor a |
ld hl,0d804h |
ld bc,00264h |
jp 01bfeh |
org 01bfeh |
ini2 ;read 02h @ 0064h |
;write 02h @ d804h |
push af ;0006h @ fdf2h |
push bc ;0165h @ fdf0h |
push hl ;d805h @ fdeeh |
xor 0aah |
jp 01cffh |
org 01cffh |
ini2 ;read 61h @ 0065h |
;write 61h @ d805h |
push af ;aac6h @ fdech |
push bc ;0066h @ fdeah |
push hl ;d806h @ fde8h |
push de ;0304h @ fde6h |
|
ld bc, 0003h |
ld hl, 0a001h |
ld de, 05002h |
jp 01dfeh |
org 01dfeh |
ini2r ;read 01h @ 5002h |
;write 01h @ a001h |
;read 02h @ 5003h |
;write 02h @ a002h |
;read 03h @ 5004h |
;write 03h @ a003h |
push af ;aac6h @ fde4h |
push bc ;0000h @ fde2h |
push hl ;a004h @ fde0h |
push de ;5005h @ fddeh |
ld bc, 0004h |
ld hl, 09ffeh |
ld de, 04ffdh |
jp 01efeh |
org 01efeh |
ind2r ;read 04h @ 4ffdh |
;write 04h @ 9ffeh |
;read 05h @ 4ffch |
;write 05h @ 9ffdh |
;read 06h @ 4ffbh |
;write 06h @ 9ffch |
;read 07h @ 4ffah |
;write 07h @ 9ffbh |
push af ;aac6h @ fddch |
push bc ;0000h @ fddah |
push hl ;9ffah @ fdd8h |
push de ;4ff9h @ fdd6h |
|
|
;--------- |
ld sp, 0fd00h |
xor a |
ld hl, 04901h |
ld bc, 00231h |
outd2 ;read 02h @ 4901h |
;write 02h @ 0231h |
push af ;0006h @ fcfeh |
push bc ;0130h @ fcfch |
push hl ;4900h @ fcfah |
ld a, 055h |
outd2 ;read 61h @ 4900h |
;write 61h @ 0130h |
push af ;5546h @ fcf8h |
push bc ;002fh @ fcf6h |
push hl ;48ffh @ fcf4h |
|
xor a |
ld hl,04804h |
ld bc,00274h |
outi2 ;read 02h @ 4804h |
;write 02h @ 0274h |
push af ;0006h @ fcf2h |
push bc ;0175h @ fcf0h |
push hl ;4805h @ fceeh |
xor 0aah |
outi2 ;read 61h @ 4805h |
;write 61h @ 0175h |
push af ;aac6h @ fcech |
push bc ;0076h @ fceah |
push hl ;4806h @ fce8h |
push de ;4ff9h @ fce6h |
|
ld bc, 0003h |
ld de, 0a001h |
ld hl, 05002h |
oti2r ;read 01h @ 5002h |
;write 01h @ a001h |
;read 02h @ 5003h |
;write 02h @ a002h |
;read 03h @ 5004h |
;write 03h @ a003h |
push af ;aac6h @ fce4h |
push bc ;0000h @ fce2h |
push de ;a004h @ fce0h |
push hl ;5005h @ fcdeh |
ld bc, 0004h |
ld de, 09ffeh |
ld hl, 04ffdh |
otd2r ;read 04h @ 4ffdh |
;write 04h @ 9ffeh |
;read 05h @ 4ffch |
;write 05h @ 9ffdh |
;read 06h @ 4ffbh |
;write 06h @ 9ffch |
;read 07h @ 4ffah |
;write 07h @ 9ffbh |
push af ;aac6h @ fcdch |
push bc ;0000h @ fcdah |
push de ;9ffah @ fcd8h |
push hl ;4ff9h @ fcd6h |
|
;--------- |
|
ld sp, 0fc00h |
and a ;AF = aa94h |
ld de, 0da15h |
ld hl, 049feh + 3 |
ld bc, 4 |
otdrx ;read eeh @ 4a01h |
;write eeh @ da15h |
;read eeh @ 4a00h |
;write eeh @ da15h |
;read eeh @ 49ffh |
;write eeh @ da15h |
;read eeh @ 49feh |
;write eeh @ da15h |
push af ;aad6h @ fbfeh |
push bc ;0000h @ fbfch |
push de ;da15h @ fbfah |
push hl ;49fdh @ fbf8h |
|
inc de |
inc a ;a = abh |
ld hl, 04afeh |
ld bc, 4 |
otirx ;read 11h @ 4afeh |
;write 11h @ da16h |
;read 11h @ 4affh |
;write 11h @ da16h |
;read 11h @ 4b00h |
;write 11h @ da16h |
;read 11h @ 4b01h |
;write 11h @ da16h |
push af ;abc2h @ fbf6h |
push bc ;0000h @ fbf4h |
push de ;da16h @ fbf2h |
push hl ;4b02h @ fbf0h |
|
and a |
ld hl, 09dfeh + 3 |
ld de, 0e732h |
ld bc, 4 |
indrx ;read 77h @ e732h |
;write 77h @ 9e01h |
;read 77h @ e732h |
;write 77h @ 9e00h |
;read 77h @ e732h |
;write 77h @ 9dffh |
;read 77h @ e732h |
;write 77h @ 9dfeh |
push af ;abd2h @ fbeeh |
push bc ;0000h @ fbech |
push de ;e732h @ fbeah |
push hl ;9dfdh @ fbe8h |
|
inc de |
dec a ;A = aah |
ld hl, 09efeh |
ld bc, 4 |
inirx ;read cch @ e733h |
;write cch @ 9efeh |
;read cch @ e733h |
;write cch @ 9effh |
;read cch @ e733h |
;write cch @ 9f00h |
;read cch @ e733h |
;write cch @ 9f01h |
push af ;aac2h @ fbe6h |
push bc ;0000h @ fbe4h |
push de ;e733h @ fbe2h |
push hl ;9f02h @ fbe0h |
|
ld hl,0100h |
jp 0c0h |
|
org 02000h |
dw 0dbach, 05183h, 0e800h, 07e4dh, 09a1fh |
|
org 04800h |
db 0a6h, 0a5h, 0f4h, 022h, 002h, 061h ;for ini2 |
|
org 04900h |
db 061h, 002h, 022h, 0f4h, 0a5h, 0a6h ;for ind2 |
|
org 049feh |
db 0eeh, 0eeh, 0eeh, 0eeh |
|
org 04afeh |
db 011h, 011h, 011h, 011h |
|
org 04fe8h |
db 0ffh, 0ffh, 0a8h, 027h, 026h, 01ch, 01bh, 01ah |
db 019h, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 043h, 00ah |
db 009h, 008h, 007h, 006h, 005h, 004h, 0ffh, 0aah |
db 055h, 0ffh, 001h, 002h, 003h, 00bh, 00ch, 00dh |
db 00eh, 00fh, 0ffh, 0ffh, 0ffh, 0ffh, 01dh, 01eh |
db 01fh, 020h, 0a1h, 022h, 023h, 022h, 025h, 0ffh |
|
org 0e732h |
db 077h, 0cch |
|
org 0e800h |
dw 00123h, 04567h, 089abh, 02006h, 0cdefh |
|
end |
/tags/ez80-instructions/asm/180_ops.s
0,0 → 1,190
;********************************************************************************** |
;* * |
;* checks all z180 instructions * |
;* * |
;********************************************************************************** |
aseg |
|
org 00h |
jp 100h |
|
org 038h |
jp (hl) |
|
org 066h |
jp (ix) |
|
org 80h |
db 00h, 01h, 2dh, 03h, 04h, 05h, 06h, 07h |
db 0fh, 1eh, 02h, 3ch, 4bh, 5ah, 69h, 78h |
|
org 0c0h ;pattern finish location |
nop |
jr 0c0h |
|
org 0100h |
di |
ld sp, 0fffeh ;point sp at result table |
xor a |
ld hl, 01234h |
ld de, 05678h |
ld bc, 09abch |
mlt sp |
push af ;0044h @ fd00h |
mlt hl |
push hl ;03a8h @ fcfeh |
mlt de |
push de ;2850h @ fcfch |
mlt bc |
push bc ;7118h @ fcfah |
push af ;0044h @ fcf8h |
; |
add a,1 |
in0 a,(080h) ;read 00h @ 0080h |
push af ;0044h @ fcf6h |
out0 (030h),b ;071 @ 0030h |
push af ;0044h @ fcf4h |
in0 a,(08ah) ;read 02h @ 008ah |
push af ;0200h @ fcf2h |
out0 (031h),c ;018 @ 0031h |
push af ;0200h @ fcf0h |
in0 b,(81h) |
in0 c,(82h) |
in0 d,(83h) |
in0 e,(84h) |
in0 h,(85h) |
in0 l,(86h) ;read 06h @ 0086h |
push af ;0204h @ fceeh |
push bc ;012dh @ fcech |
push de ;0304h @ fceah |
push hl ;0506h @ fce8h |
; |
out0 (032h),l ;06h @ 0032h |
out0 (033h),h ;05h @ 0033h |
out0 (034h),a ;02h @ 0034h |
out0 (035h),d ;03h @ 0035h |
out0 (036h),e ;04h @ 0036h |
push af ;0204h @ fce6h |
; |
ld a, 0a9h |
tst b ;a9h & 01h = 01h |
push af ;a910h @ fce4h |
tst c ;a9h & 2dh = 29h |
push af ;a910h @ fce2h |
tst d ;a9h & 03h = 01h |
push af ;a910h @ fce0h |
scf |
tst e ;a9h & 04h = 00h |
push af ;a954h @ fcdeh |
tst h ;a9h & 05h = 01h |
push af ;a910h @ fcdch |
ld l, 0f7h |
tst l ;a9h & f7h = a1h |
push af ;a990h @ fcdah |
tst a ;a9h & a9h = a9h |
push af ;a994h @ fcd8h |
scf |
ld hl, 01000h |
tst (hl) ;a9h & b7h = a1h |
push af ;a990h @ fcd6h |
tst 056h ;a9h & 56h = 00h |
push af ;a954h @ fcd4h |
ld c, 08ch |
scf |
tstio 0aah ;a9h & 4bh = 09h |
push af ;a914h @ fcd2h |
; |
xor a |
ld hl, 02000h |
ld bc, 00630h |
jp 001feh |
org 001feh |
otim ;read 71h @ 2000h |
;write 71h @ 0030h |
push af ;0006h @ fcd0h |
push bc ;0531h @ fcceh |
push hl ;2001h @ fccch |
jp 002feh |
org 002feh |
otimr ;read 18h @ 2001h |
;write 18h @ 0031h |
;read 06h @ 2002h |
;write 06h @ 0032h |
;read 05h @ 2003h |
;write 05h @ 0033h |
;read 02h @ 2004h |
;write 02h @ 0034h |
;read 03h @ 2005h |
;write 03h @ 0035h |
push af ;0046h @ fccah |
push bc ;0036h @ fcc8h |
push hl ;2006h @ fcc6h |
ld b,1 |
jp 003ffh |
org 003ffh |
otimr ;read 04h @ 2006h |
;write 04h @ 0036h |
push af ;0046h @ fcc4h |
push bc ;0037h @ fcc2h |
push hl ;2007h @ fcc0h |
inc b |
jp 004ffh |
org 004ffh |
otim ;read aah @ 2007h |
;write aah @ 0037h |
push af ;0042h @ fcbeh |
push bc ;0038h @ fcbch |
push hl ;2008h @ fcbah |
ld hl, 02007h |
ld bc, 00637h |
jp 005feh |
org 005feh |
otdm ;read aah @ 2007h |
;write aah @ 0037h |
push af ;0002h @ fcb8h |
push bc ;0536h @ fcb6h |
push hl ;2006h @ fcb4h |
jp 006feh |
org 006feh |
otdmr ;read 04h @ 2006h |
;write 04h @ 0036h |
;read 03h @ 2005h |
;write 03h @ 0035h |
;read 02h @ 2004h |
;write 02h @ 0034h |
;read 05h @ 2003h |
;write 05h @ 0033h |
;read 06h @ 2002h |
;write 06h @ 0032h |
push af ;0042h @ fcb2h |
push bc ;0031h @ fcb0h |
push hl ;2001h @ fcaeh |
inc b |
xor 0aah |
jp 007ffh |
org 007ffh |
otdmr ;read 18h @ 2001h |
;write 18h @ 0031h |
push af ;aac6h @ fcach |
push bc ;0030h @ fcaah |
push hl ;2000h @ fca8h |
inc b |
jp 008ffh |
org 008ffh |
otdm ;read 71h @ 2000h |
;write 71h @ 0030h |
push af ;aa42h @ fca6h |
push bc ;002fh @ fca4h |
push de ;0304h @ fca2h |
push hl ;1fffh @ fca0h |
; |
ld hl, 00100h |
jp 0c0h |
|
org 01000h |
db 0b7h |
|
org 02000h |
db 071h, 018h, 006h, 005h, 002h, 003h, 004h, 0aah |
|
end |
/tags/ez80-instructions/asm/ez8_opsd.s
0,0 → 1,112
;********************************************************************************** |
;* * |
;* ez8_ops compare data * |
;* * |
;********************************************************************************** |
org 00130h |
db 061h |
|
org 00231h |
db 002h |
|
org 00332h |
db 033h |
|
org 00433h |
db 0f4h |
|
org 00534h |
db 0e5h |
|
org 00635h |
db 0a6h |
|
org 00175h |
db 061h |
|
org 00274h |
db 002h |
|
org 00373h |
db 033h |
|
org 00472h |
db 0f4h |
|
org 00571h |
db 0e5h |
|
org 00670h |
db 0a6h |
|
org 09dfeh |
db 077h, 077h, 077h, 077h ;09f00h |
|
org 09efeh |
db 0cch, 0cch, 0cch, 0cch ;09f04h |
|
org 09ff8h |
db 0ffh, 0ffh, 0ffh, 007h, 006h, 005h, 004h, 0aah ;09ff8h |
db 055h, 001h, 002h, 003h, 0ffh, 0ffh, 0ffh, 0ffh ;0a000h |
|
|
org 0d000h |
dw 00123h, 04567h, 0d004h, 089abh, 0cdefh |
|
org 0d700h |
db 071h, 018h, 006h, 005h, 002h, 003h, 004h, 0aah ;for inim/indm/inimr/indmr |
|
org 0d800h |
db 0a6h, 0a5h, 0f4h, 022h, 002h, 061h ;for ini2 |
|
org 0d900h |
db 061h, 002h, 022h, 0f4h, 0a5h, 0a6h ;for ind2 |
|
org 0da15h |
db 0eeh, 011h |
|
org 0e040h |
dw 00123h, 04567h, 0d008h, 0e080h, 0dff0h |
|
org 0fbe0h |
dw 09f02h, 0e733h, 00000h, 0aac2h ;fbe0h |
dw 09dfdh, 0e732h, 00000h, 0abd2h ;fbe8h |
dw 04b02h, 0da16h, 00000h, 0abc2h ;fbf0h |
dw 049fdh, 0da15h, 00000h, 0aad6h ;fbf8h |
|
org 0fcd6h |
dw 04ff9h |
dw 09ffah, 00000h, 0aac6h, 05005h ;fcd8h |
dw 0a004h, 00000h, 0aac6h, 04ff9h ;fce0h |
dw 04806h, 00076h, 0aac6h, 04805h ;fce8h |
dw 00175h, 00006h, 048ffh, 0002fh ;fcf0h |
dw 05546h, 04900h, 00130h, 00006h ;fcf8h |
|
org 0fdd6h |
dw 04ff9h |
dw 09ffah, 00000h, 0aac6h, 05005h ;fdd8h |
dw 0a004h, 00000h, 0aac6h, 00304h ;fde0h |
dw 0d806h, 00066h, 0aac6h, 0d805h ;fde8h |
dw 00165h, 00006h, 0d8ffh, 0003fh ;fdf0h |
dw 05546h, 0d900h, 00140h, 00006h ;fdf8h |
|
org 0feceh |
dw 0d6ffh |
dw 00304h, 000cfh, 0aa42h, 0d700h ;fed0h |
dw 000d0h, 0aac6h, 0d701h, 000d1h ;fed8h |
dw 00042h, 0d706h, 005d6h, 00002h ;fee0h |
dw 0d708h, 000d8h, 00042h, 0d707h ;fee8h |
dw 000d7h, 00046h, 0d706h, 000d6h ;fef0h |
dw 00046h, 0d701h, 005d1h, 00006h ;fef8h |
|
org 0ffc4h |
dw 00044h, 0aa02h |
dw 0aa01h, 0aa00h, 0a9ffh, 0a9feh ;ffc8h |
dw 07e4eh, 07e4fh, 07e4dh, 07e4ch ;ffd0h |
dw 07e4bh, 09a1fh, 07e4dh, 0e800h ;ffd8h |
dw 05183h, 0dbach, 02006h, 089abh ;ffe0h |
dw 0cdefh, 04567h, 00123h, 09a1fh ;ffe8h |
dw 07e4dh, 0e800h, 05183h, 0dbach ;fff0h |
dw 0cdefh, 089abh, 0cd9ah, 08a00h ;fff8h |
|
end |
/tags/ez80-instructions/asm/build.bat
Cannot display: file marked as a binary type.
svn:mime-type = application/x-msdos-program
tags/ez80-instructions/asm/build.bat
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/x-msdos-program
\ No newline at end of property
Index: tags/ez80-instructions/asm/int_opsd.s
===================================================================
--- tags/ez80-instructions/asm/int_opsd.s (nonexistent)
+++ tags/ez80-instructions/asm/int_opsd.s (revision 9)
@@ -0,0 +1,80 @@
+;**********************************************************************************
+;* *
+;* int_ops compare data *
+;* *
+;**********************************************************************************
+ org 03cc4h
+ db 0c4h
+ db 0c5h
+ db 0c6h
+ db 0c7h
+ db 0c8h
+ db 0c9h
+ db 0cah
+ db 0cbh
+ db 0cch
+ db 0cdh
+ db 0ceh
+ db 0cfh
+ db 0d0h
+ db 0d1h
+ db 0d2h
+ db 0d3h
+ db 0d4h
+
+
+ org 05a3ch
+ db 05ah
+
+
+ org 0966ah
+ db 003h
+ db 005h
+ db 007h
+ db 009h
+ db 00bh
+ db 00dh
+ db 00fh
+ db 011h
+ db 013h
+ db 015h
+ db 017h
+ db 019h
+ db 01bh
+ db 01dh
+ db 01fh
+ db 021h
+ db 023h
+ db 025h
+ db 027h
+ db 029h
+
+
+ org 0ff2eh
+ dw 0d747h, 0d633h, 03cceh ;ff2eh
+ dw 08421h, 0edb7h, 0ff92h, 0d610h, 09678h ;ff34h
+ dw 02e00h, 00100h, 0001fh, 05a44h, 05a44h ;ff3eh
+ dw 06900h, 02e00h, 00100h, 0001fh, 0de00h ;ff48h
+ dw 06900h, 02d00h, 00100h, 0001eh, 0dd00h ;ff52h
+ dw 06900h, 02c00h, 00100h, 0001dh, 0dc01h ;ff5ch
+ dw 06900h, 02b00h, 00100h, 0001ch, 0db01h ;ff66h
+ dw 06916h, 02a00h, 00100h, 0001bh, 0da00h ;ff70h
+ dw 09394h, 02900h, 00100h, 0001ah, 0d900h ;ff7ah
+ dw 06a04h, 02800h, 00100h, 00019h, 0d800h ;ff84h
+ dw 04204h, 02700h, 00100h, 00018h, 0d700h ;ff8eh
+
+ dw 05500h, 02600h, 00100h, 00017h ;ff98h
+ dw 0d512h, 00016h, 0d412h, 00015h ;ffa0h
+ dw 0d311h, 05500h, 05500h, 00014h ;ffa8h
+ dw 0d300h, 00044h, 00044h, 00013h ;ffb0h
+ dw 0d200h, 00012h, 0d104h, 00011h ;ffb8h
+ dw 0d001h, 00010h, 0cf01h, 0000fh ;ffc0h
+ dw 0ce01h, 0000eh, 0ccffh, 0000dh ;ffc8h
+ dw 0cc00h, 0000ch, 0cb00h, 0000bh ;ffd0h
+ dw 0c9ffh, 0000ah, 0c8ffh, 00009h ;ffd8h
+ dw 0c7feh, 00008h, 0c6feh, 00007h ;ffe0h
+ dw 0c601h, 00006h, 0c501h, 00005h ;ffe8h
+ dw 05000h, 00004h, 05000h, 00003h ;fff0h
+ dw 0c202h, 00002h, 0c102h, 00001h ;fff8h
+
+ end
Index: tags/ez80-instructions/asm/180_opsd.s
===================================================================
--- tags/ez80-instructions/asm/180_opsd.s (nonexistent)
+++ tags/ez80-instructions/asm/180_opsd.s (revision 9)
@@ -0,0 +1,24 @@
+;**********************************************************************************
+;* *
+;* 180_ops compare data *
+;* *
+;**********************************************************************************
+ org 030h
+ db 071h, 018h, 006h, 005h, 002h, 003h, 004h, 0aah
+
+ org 0fca0h
+ dw 01fffh, 00304h, 0002fh, 0aa42h ;fca0h
+ dw 02000h, 00030h, 0aac6h, 02001h ;fca8h
+ dw 00031h, 00042h, 02006h, 00536h ;fcb0h
+ dw 00002h, 02008h, 00038h, 00042h ;fcb8h
+ dw 02007h, 00037h, 00046h, 02006h ;fcc0h
+ dw 00036h, 00046h, 02001h, 00531h ;fcc8h
+ dw 00006h, 0a914h, 0a954h, 0a990h ;fcd0h
+ dw 0a994h, 0a990h, 0a910h, 0a954h ;fcd8h
+ dw 0a910h, 0a910h, 0a910h, 00204h ;fce0h
+ dw 00506h, 00304h, 0012dh, 00204h ;fce8h
+ dw 00200h, 00200h, 00044h, 00044h ;fcf0h
+ dw 00044h, 07118h, 02850h, 003a8h ;fcf8h
+ dw 00044h ;fd00h
+
+ end
Index: tags/ez80-instructions/asm/int_opss.s
===================================================================
--- tags/ez80-instructions/asm/int_opss.s (nonexistent)
+++ tags/ez80-instructions/asm/int_opss.s (revision 9)
@@ -0,0 +1,80 @@
+;**********************************************************************************
+;* *
+;* int_ops compare data (for bus request case) *
+;* *
+;**********************************************************************************
+ org 03cc4h
+ db 0c4h
+ db 0c5h
+ db 0c6h
+ db 0c7h
+ db 0c8h
+ db 0c9h
+ db 0cah
+ db 0cbh
+ db 0cch
+ db 0cdh
+ db 0ceh
+ db 0cfh
+ db 0d0h
+ db 0d1h
+ db 0d2h
+ db 0d3h
+ db 0d4h
+
+
+ org 05a3ch
+ db 05ah
+
+
+ org 0966ah
+ db 003h
+ db 005h
+ db 007h
+ db 009h
+ db 00bh
+ db 00dh
+ db 00fh
+ db 011h
+ db 013h
+ db 015h
+ db 017h
+ db 019h
+ db 01bh
+ db 01dh
+ db 01fh
+ db 021h
+ db 023h
+ db 025h
+ db 027h
+ db 029h
+
+
+ org 0ff2eh
+ dw 0d747h, 0d633h, 03cceh ;ff2eh
+ dw 08421h, 0edb7h, 0ff92h, 0d610h, 09678h ;ff34h
+ dw 02e00h, 00100h, 0001fh, 05a44h, 05a44h ;ff3eh
+ dw 06900h, 02e00h, 00100h, 0001fh, 0de00h ;ff48h
+ dw 06900h, 02d00h, 00100h, 0001eh, 0dd00h ;ff52h
+ dw 06900h, 02c00h, 00100h, 0001dh, 0dc01h ;ff5ch
+ dw 06900h, 02b00h, 00100h, 0001ch, 0db01h ;ff66h
+ dw 06916h, 02a00h, 00100h, 0001bh, 0da00h ;ff70h
+ dw 09394h, 02900h, 00100h, 0001ah, 0d900h ;ff7ah
+ dw 06a04h, 02800h, 00100h, 00019h, 0d800h ;ff84h
+ dw 04204h, 02700h, 00100h, 00018h, 0d700h ;ff8eh
+
+ dw 05500h, 02600h, 00100h, 00017h ;ff98h
+ dw 0d512h, 00016h, 0d412h, 00015h ;ffa0h
+ dw 0d311h, 05500h, 05500h, 00014h ;ffa8h
+ dw 0d300h, 00044h, 00044h, 00013h ;ffb0h
+ dw 0d200h, 00012h, 0d103h, 00011h ;ffb8h
+ dw 0d001h, 00010h, 0cf00h, 0000fh ;ffc0h
+ dw 0ce01h, 0000eh, 0ccffh, 0000dh ;ffc8h
+ dw 0cc00h, 0000ch, 0cb00h, 0000bh ;ffd0h
+ dw 0c9ffh, 0000ah, 0c8ffh, 00009h ;ffd8h
+ dw 0c7feh, 00008h, 0c6feh, 00007h ;ffe0h
+ dw 0c601h, 00006h, 0c501h, 00005h ;ffe8h
+ dw 05000h, 00004h, 05000h, 00003h ;fff0h
+ dw 0c202h, 00002h, 0c101h, 00001h ;fff8h
+
+ end
Index: tags/ez80-instructions/asm/ihex2vm.cpp
===================================================================
--- tags/ez80-instructions/asm/ihex2vm.cpp (nonexistent)
+++ tags/ez80-instructions/asm/ihex2vm.cpp (revision 9)
@@ -0,0 +1,94 @@
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+int main(int argc, char *argv[])
+{
+ std::istream *src = &std::cin;
+ std::ostream *dst = &std::cout;
+ std::cerr << "Intel HEX to Verilog readmemh converter" << std::endl;
+ if (argc > 1) {
+ std::fstream *file = new std::fstream(argv[1], std::ios::in);
+ src = file;
+ if (!file->is_open()) {
+ const char *err = strerror(errno);
+ std::cerr << "Failed to open input file: " << err << std::endl;
+ return 1;
+ }
+ if (argc > 2) {
+ file = new std::fstream(argv[2], std::ios::out);
+ dst = file;
+ if (!file->is_open()) {
+ const char *err = strerror(errno);
+ std::cerr << "Failed to open output file: " << err << std::endl;
+ return 1;
+ }
+ }
+ } else
+ std::cerr << "Usage:\n\t" << argv[0] << "[ [
tags/ez80-instructions/asm/ihex2vm.cpp
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/x-c++src
\ No newline at end of property
Index: tags/ez80-instructions/asm/int_ops.s
===================================================================
--- tags/ez80-instructions/asm/int_ops.s (nonexistent)
+++ tags/ez80-instructions/asm/int_ops.s (revision 9)
@@ -0,0 +1,561 @@
+;**********************************************************************************
+;* *
+;* checks interrupt options and conditions *
+;* *
+;**********************************************************************************
+ aseg
+
+ org 00h
+ jp (hl)
+
+ org 38h
+ inc bc
+ exx
+ inc hl
+ ld (hl), l ;write a marker
+ exx
+ jp (hl)
+
+ org 66h
+ inc bc
+ inc ix
+ ld (ix+0), c ;write a marker
+ jp (hl)
+
+ org 0c0h ;pattern finish location
+ nop
+ jr 0c0h
+
+ org 0100h
+ ex af,af'
+ xor a
+ dec a
+ ex af,af'
+ exx
+ ld bc, 0edb7h
+ ld de, 08421h
+ ld hl, 03cc3h
+ exx
+ xor a
+ ld bc, 00001h
+ ld de, 00100h
+ ld hl, 01000h
+ ld ix, 09669h
+ ld iy, 0bffeh
+ jp (hl) ;1000h
+
+ org 1000h
+ push bc ;0001h @ fffeh
+ add hl, de
+ add iy, de
+ jp (iy) ;c0feh
+
+ org 1100h
+ inc bc ;compensate for mode 0
+ push bc ;0002h @ fffah
+ im 2
+ add hl, de
+ im 1 ;toggles back okay
+ add iy, de
+ ei
+ jp (iy) ;c1feh
+
+ org 1200h
+ push bc ;0003h @ fff6h
+ add hl, de
+ add iy, de
+ ei
+ jp (iy) ;c2feh
+
+ org 1300h
+ push bc ;0004h @ fff2h
+ add hl, de
+ add iy, de
+ ei
+ jp (iy) ;c3feh
+
+ org 1400h
+ push bc ;0005h @ ffeeh
+ add hl, de
+ add iy, de
+ ei
+ jp (iy) ;c4feh
+
+ org 1500h
+ push bc ;0006h @ ffeah
+ add hl, de
+ add iy, de
+ ei
+ jp (iy) ;c5feh
+
+ org 1600h
+ push bc ;0007h @ ffe6h
+ add hl, de
+ add iy, de
+ ei
+ jp (iy) ;c6feh
+
+ org 1700h
+ push bc ;0008h @ ffe2h
+ add hl, de
+ add iy, de
+ ei
+ jp (iy) ;c7feh
+
+ org 1800h
+ push bc ;0009h @ ffdeh
+ add hl, de
+ add iy, de
+ ei
+ jp (iy) ;c8feh
+
+ org 1900h
+ push bc ;000ah @ ffdah
+ add hl, de
+ add iy, de
+ ei
+ jp (iy) ;c9feh
+
+ org 1a00h
+ push bc ;000bh @ ffd6h
+ add hl, de
+ add iy, de
+ ei
+ jp (iy) ;cafeh
+
+ org 1b00h
+ push bc ;000ch @ ffd2h
+ add hl, de
+ add iy, de
+ ei
+ jp (iy) ;cbfeh
+
+ org 1c00h
+ push bc ;000dh @ ffceh
+ inc bc ;compensate for cpir
+ add hl, de
+ add iy, de
+ ei
+ jp (iy) ;ccfeh
+
+ org 1d00h
+ db 0ffh ;cpir no match data
+ push bc ;000eh @ ffcah
+ inc bc ;compensate for cpir
+ dec hl ;compensate for cpir
+ add hl, de
+ add iy, de
+ ei
+ jp (iy) ;cdfeh
+
+ org 1e00h
+ db 00h ;cpir match data
+ push bc ;000fh @ ffc6h
+ dec hl ;compensate for cpir
+ add hl, de
+ add iy, de
+ jp (iy) ;cefeh
+
+ org 1f00h
+ push bc ;0010h @ ffc2h
+ add hl, de
+ add iy, de
+ jp (iy) ;cffeh
+
+ org 2000h
+ push bc ;0011h @ ffbeh
+ add hl, de
+ add iy, de
+ im 0 ;no effect
+ ei
+ jp (iy) ;d0feh
+
+ org 2100h
+ inc bc ;compensate for im 0 address
+ push bc ;0012h @ ffbah
+ add hl, de
+ add iy, de
+ ei
+ jp (iy) ;d1feh
+
+ org 2200h
+ push bc ;0013h @ ffb6h
+ add hl, de
+ add iy, de
+ ld a, i
+ push af ;0044h @ ffb4h
+ ld sp, 02250h
+ retn ;2230h @ 2250h read
+ halt ;not executed
+
+ org 2230h
+ ld a, i
+ ld sp, 0ffb4h
+ push af ;0044h @ ffb2h
+ ld a, 055h
+ ld i, a
+ im 2
+ jp (iy) ;d2feh
+
+ org 2250h
+ dw 02230h ;data for retn
+
+ org 2300h
+ inc bc
+ push bc ;0014h @ ffaeh
+ add hl, de
+ add iy, de
+ ld a, i
+ push af ;5500h @ ffach
+ ld sp, 02350h
+ reti ;2330h @ 2350h read
+ halt ;not executed
+
+ org 2330h
+ ld a, i
+ ld sp, 0ffach
+ im 0 ;no effect
+ push af ;5500h @ ffaah
+ ei
+ ld iy, 0d310h
+ jp (iy) ;d310h
+
+ org 2350h
+ dw 02330h ;data for reti
+
+ org 2400h
+ push bc ;0015h @ ffa6h
+ add hl, de
+ add iy, de
+ ld sp, 02450h
+ retn ;2430h @ 2450h read
+ halt ;not executed
+
+ org 2430h
+ ld sp, 0ffa6h
+ jp (iy) ;d410h
+
+ org 2450h
+ dw 02430h ;data for retn
+
+ org 2500h
+ inc bc ;compensate for mode 0
+ push bc ;0016h @ ffa2h
+ add hl, de
+ add iy, de
+ ld sp, 02550h
+ retn ;2530h @ 2550h read
+ halt ;not executed
+
+ org 2530h
+ ld sp, 0ffa2h
+ jp (iy) ;d510h
+
+ org 2550h
+ dw 02530h ;data for retn
+
+
+ org 2600h
+ push bc ;0017h @ ff9eh
+ push de ;0100h @ ff9eh
+ push hl ;2600h @ ff9ch
+ push af ;5500h @ ff98h
+ im 1
+ ld hl, 2700h
+ ld iy, 0d6feh
+ ei
+ jp (iy) ;d6feh
+
+ org 2700h
+ push bc ;0018h @ ff94h
+ push de ;0100h @ ff92h
+ push hl ;2700h @ ff90h
+ push af ;4204h @ ff8eh
+ ld hl, 2800h
+ ld iy, 0d7feh
+ ei
+ jp (iy) ;d7feh
+
+ org 2800h
+ push bc ;0019h @ ff8ah
+ push de ;0100h @ ff88h
+ push hl ;2800h @ ff86h
+ push af ;6a04h @ ff84h
+ ld hl, 2900h
+ ld iy, 0d8feh
+ ei
+ jp (iy) ;d8feh
+
+ org 2900h
+ push bc ;001ah @ ff80h
+ push de ;0100h @ ff7eh
+ push hl ;2900h @ ff7ch
+ push af ;9394h @ ff7ah
+ ld hl, 2a00h
+ ld iy, 0d9feh
+ ei
+ jp (iy) ;d9feh
+
+ org 2a00h
+ push bc ;001bh @ ff76h
+ push de ;0100h @ ff74h
+ push hl ;2a00h @ ff72h
+ push af ;6916h @ ff70h
+ ld hl, 1580h
+ ld iy, 0dafeh
+ ei
+ jp (iy) ;dafeh
+
+ org 2b00h
+ push bc ;001ch @ ff6ch
+ push de ;0100h @ ff6ah
+ push hl ;2b00h @ ff68h
+ push af ;6900h @ ff66h
+ ld hl, 1600h
+ ld iy, 0dbfeh
+ ei
+ jp (iy) ;dbfeh
+
+ org 2c00h
+ push bc ;001dh @ ff62h
+ push de ;0100h @ ff60h
+ push hl ;2c00h @ ff5eh
+ push af ;6900h @ ff5ch
+ ld hl, 2d01h
+ ld iy, 0dcfeh
+ ei
+ jp (iy) ;dcfeh
+
+ org 2d00h
+ push bc ;001eh @ ff58h
+ push de ;0100h @ ff56h
+ push hl ;2d00h @ ff54h
+ push af ;6900h @ ff52h
+ ld hl, 2e01h
+ ld iy, 0ddfeh
+ ei
+ jp (iy) ;ddfeh
+
+ org 2e00h
+ push bc ;001fh @ ff4eh
+ push de ;0100h @ ff4ch
+ push hl ;2e00h @ ff4ah
+ push af ;6900h @ ff48h
+ ld sp, 02e50h
+ retn ;2e30h @ 2e50h read
+ halt ;not executed
+
+ org 2e30h
+ ld sp, 0ff48h
+ ld iy, 0d610h
+ jp (iy) ;d610h
+
+ org 2e50h
+ dw 02e30h
+
+ org 4ce3h
+ db 05ah
+
+ org 5564h
+ dw 02300h
+
+ org 0c0feh
+ dec hl ;int next
+ inc hl
+ ei
+ nop ;c101h @ fffch with busreq
+ jp nc, 5000h ;c102h @ fffch
+ halt ;not executed
+
+ org 0c1feh
+ nop ;nmi next
+ jp c, 5000h ;c202h @ fff8h
+ halt ;not executed
+
+ org 0c2feh
+ nop ;int next
+ jp nc, 5000h ;5000h @ fff4h
+ halt ;not executed
+
+ org 0c3feh
+ nop ;nmi next
+ jp nc, 5000h ;5000h @ fff0h
+ halt ;not executed
+
+ org 0c4feh
+ nop ;int next
+ jr c, 0c4feh ;c501h @ ffech
+ halt ;not executed
+
+ org 0c5feh
+ nop ;nmi next
+ jr c, 0c5feh ;c601h @ ffe8h
+ halt ;not executed
+
+ org 0c6feh
+ nop ;int next
+ jr nc, 0c6feh ;c6feh @ ffe4h
+ halt ;not executed
+
+ org 0c7feh
+ nop ;nmi next
+ jr nc, 0c7feh ;c7feh @ ffe0h
+ halt ;not executed
+
+ org 0c8feh
+ halt ;int next
+ rst 28h ;c8ffh @ ffdch
+
+ org 0c9feh
+ halt ;nmi next
+ rst 28h ;c9ffh @ ffd8h
+ jp 5000h ;not executed
+
+ org 0cafeh
+ nop ;int next
+ halt ;cb00h @ ffd4h
+ jp 5000h ;not executed
+
+ org 0cbfeh
+ nop ;nmi next
+ halt ;cc00h @ ffd0h
+ jp 5000h ;not executed
+
+ org 0ccfeh
+ nop ;int next
+ cpir ;ccffh @ ffcch
+ rst 08h ;not executed
+
+ org 0cdfeh
+ nop ;nmi next
+ cpir ;ce01h @ ffc8h
+ rst 10h ;not executed
+
+ org 0cefeh
+ nop ;int next
+ ei ;cf00h @ ffc4h with busreq
+ nop ;cf01h @ ffc4h
+ rst 18h ;not executed
+
+ org 0cffeh
+ nop ;nmi next
+ di ;d001h @ ffc0h
+ nop
+ rst 28h ;not executed
+
+ org 0d0feh
+ nop ;int next
+ di ;d101h @ ffbch
+ dec hl
+ inc hl
+ ei
+ nop ;d103h @ ffbch with busreq
+ rst 30h ;not executed
+
+ org 0d1feh
+ dec hl ;nmi next
+ inc hl ;d200h @ ffb8h
+ rst 28h ;not executed
+
+ org 0d2feh
+ dec hl ;int next
+ inc hl ;d300h @ ffb0h
+ db 064h ;2300h @ 5564h read - mode 2
+
+ org 0d310h
+ halt ;nmi next
+ rst 30h ;d311h @ ffa8h
+
+ org 0d410h
+ nop ;int next
+ halt ;d412h @ ffa4h
+ jp 5000h ;not executed
+
+ org 0d510h
+ nop ;int next
+ halt ;d512h @ ffa0h
+ jp 5000h ;not executed
+
+ org 0d610h
+ xor a
+ ld a, 04ch
+ in a, (0e3h) ; 5ah @ 4ce3h
+ push af ;5a44h @ ff46h
+ out (3ch), a ; 5ah @ 5a3ch
+ push af
+ push bc
+ push de
+ push hl
+ push ix
+ push iy
+ ex af,af'
+ push af
+ ex af,af'
+ exx
+ push bc
+ push de
+ push hl
+ exx
+
+ di
+ nop
+ slp
+ nop
+
+ ld hl,0d740h
+ ei ;int next
+ slp ;d633h @ ff30h
+ rst 00h ;not executed
+
+ org 0d640h
+ di
+ ld hl, 0100h
+ jp 0c0h
+
+ org 0d6feh
+ nop ;int next
+ xor c ;d700 @ ff96h
+
+ org 0d740h
+ di
+ ld hl,0d640h
+ nop ;nmi next
+ slp ;d747h @ ff2eh
+ rst 00h
+
+ org 0d7feh
+ nop ;nmi next
+ xor h ;d800 @ ff8ch
+ nop
+
+ org 0d8feh
+ nop ;int next
+ adc a,h ;d900 @ ff82h
+ nop
+
+ org 0d9feh
+ nop ;nmi next
+ sbc a,h ;da00 @ ff78h
+ nop
+
+ org 0dafeh
+ nop ;int next
+ adc hl, hl ;db00 @ ff6eh
+ nop
+
+ org 0dbfeh
+ nop ;nmi next
+ adc hl, hl ;dc00 @ ff64h
+ nop
+
+ org 0dcfeh
+ nop ;int next
+ dec hl ;dd00 @ ff5ah
+ nop
+
+ org 0ddfeh
+ nop ;nmi next
+ dec hl ;de00 @ ff50h
+ nop
+
+ end
Index: tags/ez80-instructions/asm/dat_mov.s
===================================================================
--- tags/ez80-instructions/asm/dat_mov.s (nonexistent)
+++ tags/ez80-instructions/asm/dat_mov.s (revision 9)
@@ -0,0 +1,539 @@
+;**********************************************************************************
+;* *
+;* checks all data movement instructions *
+;* *
+;**********************************************************************************
+ aseg
+
+ org 00h
+ jp 100h
+
+ org 0c0h ;pattern finish location
+ nop
+ jr 0c0h
+
+ org 0100h
+ ld sp, 0000h ;point sp at result table
+ ld a, 0ffh ;initialize the main registers
+ xor a ;initialize flags
+ ld b, 01h ;immediate loads
+ ld c, 02h
+ ld d, 04h
+ ld e, 08h
+ ld h, 10h
+ ld l, 20h
+ ld ix, 0aaaah
+ ld iy, 5555h
+ push af ;0044h @ fffeh
+ push bc ;0102h @ fffch
+ push de ;0408h @ fffah
+ push hl ;1020h @ fff8h
+ push ix ;aaaah @ fff6h
+ push iy ;5555h @ fff4h
+ ld a, 0f0h
+ ld (bc), a ; f0h @ 0102h
+ ld a, 0fh
+ ld (de), a ; 0fh @ 0408h
+ ld (hl), a ; 0fh @ 1020h
+ inc hl
+ ld (hl), b ; 01h @ 1021h
+ inc hl
+ ld (hl), c ; 02h @ 1022h
+ inc hl
+ ld (hl), d ; 04h @ 1023h
+ inc hl
+ ld (hl), e ; 08h @ 1024h
+ inc hl
+ ld (hl), h ; 10h @ 1025h
+ inc hl
+ ld (hl), l ; 26h @ 1026h
+ inc hl
+ ld (hl), 3ch ; 3ch @ 1027h
+ ld hl, 1020h
+ push af ;0f44h @ fff2h
+ push bc ;0102h @ fff0h
+ push de ;0408h @ ffeeh
+ push hl ;1020h @ ffech
+ ld a, 00h
+ ex af, af'
+ ld a, 0ffh ;initialize the alternate registers
+ or a
+ exx
+ ld bc, 0fefdh ;immediate loads
+ ld de, 0fbf7h
+ ld hl, 0efdfh
+ push af ;ff84h @ ffeah
+ push bc ;fefdh @ ffe8h
+ push de ;fbf7h @ ffe6h
+ push hl ;efdfh @ ffe4h
+ exx
+ push af ;ff84h @ ffe2h
+ push bc ;0102h @ ffe0h
+ push de ;0408h @ ffdeh
+ push hl ;1020h @ ffdch
+ ex de, hl
+ push af ;ff84h @ ffdah
+ push bc ;0102h @ ffd8h
+ push de ;1020h @ ffd6h
+ push hl ;0408h @ ffd4h
+ exx
+ push af ;ff84h @ ffd2h
+ push bc ;fefdh @ ffd0h
+ push de ;fbf7h @ ffceh
+ push hl ;efdfh @ ffcch
+ ex de, hl
+ push af ;ff84h @ ffcah
+ push bc ;fefdh @ ffc8h
+ push de ;efdfh @ ffc6h
+ push hl ;fbf7h @ ffc4h
+ exx
+ push af ;ff84h @ ffc2h
+ push bc ;0102h @ ffc0h
+ push de ;1020h @ ffbeh
+ push hl ;0408h @ ffbch
+ ex de, hl
+ push af ;ff84h @ ffbah
+ push bc ;0102h @ ffb8h
+ push de ;0408h @ ffb6h
+ push hl ;1020h @ ffb4h
+ exx
+ push af ;ff84h @ ffb2h
+ push bc ;fefdh @ ffb0h
+ push de ;efdfh @ ffaeh
+ push hl ;fbf7h @ ffach
+ ex de, hl
+ push af ;ff84h @ ffaah
+ push bc ;fefdh @ ffa8h
+ push de ;fbf7h @ ffa6h
+ push hl ;efdfh @ ffa4h
+ exx
+ ld b, b
+ ld c, c
+ ld d, d
+ ld h, h
+ ld l, l
+ ld a, a
+ push af ;ff84h @ ffa2h
+ push bc ;0102h @ ffa0h
+ push de ;0408h @ ff9eh
+ push hl ;1020h @ ff9ch
+ ld a, b
+ ld b, c
+ ld c, d
+ ld d, e
+ ld e, h
+ ld h, l
+ ld l, a
+ push af ;0184h @ ff9ah
+ push bc ;0204h @ ff98h
+ push de ;0810h @ ff96h
+ push hl ;2001h @ ff94h
+ xor a
+ ld b, 01h
+ ld c, 02h
+ ld d, 04h
+ ld e, 08h
+ ld h, 10h
+ ld l, 20h
+ ld a, c
+ ld b, d
+ ld c, e
+ ld d, h
+ ld e, l
+ ld h, a
+ ld l, b
+ push af ;0244h @ ff92h
+ push bc ;0408h @ ff90h
+ push de ;1020h @ ff8eh
+ push hl ;0204h @ ff8ch
+ xor a
+ ld b, 01h
+ ld c, 02h
+ ld d, 04h
+ ld e, 08h
+ ld h, 10h
+ ld l, 20h
+ ld a, d
+ ld b, e
+ ld c, h
+ ld d, l
+ ld e, a
+ ld h, b
+ ld l, c
+ push af ;0444h @ ff8ah
+ push bc ;0810h @ ff88h
+ push de ;2004h @ ff86h
+ push hl ;0810h @ ff84h
+ xor a
+ ld b, 01h
+ ld c, 02h
+ ld d, 04h
+ ld e, 08h
+ ld h, 10h
+ ld l, 20h
+ ld a, e
+ ld b, h
+ ld c, l
+ ld d, a
+ ld e, b
+ ld h, c
+ ld l, d
+ push af ;0844h @ ff82h
+ push bc ;1020h @ ff80h
+ push de ;0810h @ ff7eh
+ push hl ;2008h @ ff7ch
+ xor a
+ ld b, 01h
+ ld c, 02h
+ ld d, 04h
+ ld e, 08h
+ ld h, 10h
+ ld l, 20h
+ ld a, h
+ ld b, l
+ ld c, a
+ ld d, b
+ ld e, c
+ ld h, d
+ ld l, e
+ push af ;1044h @ ff7ah
+ push bc ;2010h @ ff78h
+ push de ;2010h @ ff76h
+ push hl ;2010h @ ff74h
+ xor a
+ ld b, 01h
+ ld c, 02h
+ ld d, 04h
+ ld e, 08h
+ ld h, 10h
+ ld l, 20h
+ ld a, l
+ ld b, a
+ ld c, b
+ ld d, c
+ ld e, d
+ ld h, e
+ ld l, h
+ push af ;2044h @ ff72h
+ push bc ;2020h @ ff70h
+ push de ;2020h @ ff6eh
+ push hl ;2020h @ ff6ch
+ ld b, (hl) ; 5ah @ 2020h
+ inc hl
+ ld c, (hl) ; 69h @ 2021h
+ inc hl
+ ld d, (hl) ; 78h @ 2022h
+ inc hl
+ ld e, (hl) ; 87h @ 2023h
+ inc hl
+ push af ;2044h @ ff6ah
+ push bc ;5a69h @ ff68h
+ push de ;7887h @ ff66h
+ push hl ;2024h @ ff64h
+ ld h, (hl) ; 96h @ 2024h
+ push hl ;9624h @ ff62h
+ ld h, 20h
+ inc hl
+ ld l, (hl) ; a5h @ 2025h
+ push hl ;20a5h @ ff60h
+ ld a, (bc) ; b4h @ 5a69h
+ push af ;b444h @ ff5eh
+ ld a, (de) ; c3h @ 7887h
+ push af ;c344h @ ff5ch
+ ld a, (7888h) ; d2h @ 7888h
+ push af ;d244h @ ff5ah
+ ld bc, (7889h) ;e1f0h @ 7889h
+ ld de, (788bh) ;0f1eh @ 788bh
+ ld hl, (788dh) ;2d3ch @ 788dh
+ ld ix, (788fh) ;4b5ah @ 788fh
+ ld iy, (7891h) ;6978h @ 7891h
+ ld sp, (7893h) ;fe00h @ 7893h
+ ld (7895h), a ; d2h @ 7895h
+ ld (7896h), bc ;e1f0h @ 7896h
+ ld (7898h), de ;0f1eh @ 7898h
+ ld (789ah), hl ;2d3ch @ 789ah
+ ld (789ch), ix ;4b5ah @ 789ch
+ ld (789eh), iy ;6978h @ 789eh
+ ld (78a0h), sp ;fe00h @ 78a0h
+ ld sp, 0f000h
+ pop af ;0f00h @ f000h
+ pop bc ;ee11h @ f002h
+ pop de ;dd22h @ f004h
+ pop hl ;cc33h @ f006h
+ pop ix ;bb44h @ f008h
+ pop iy ;aa55h @ f00ah
+ ld sp, 0fe00h
+ push af ;0f00h @ fdfeh
+ push bc ;ee11h @ fdfch
+ push de ;dd22h @ fdfah
+ push hl ;cc33h @ fdf8h
+ push ix ;bb44h @ fdf6h
+ push iy ;aa55h @ fdf4h
+ inc hl
+ ld sp, hl
+ push af ;0f00h @ cc32h
+ push hl ;cc34h @ cc30h
+ ld sp, ix
+ push af ;0f00h @ bb42h
+ push ix ;bb44h @ bb40h
+ inc iy
+ ld sp, iy
+ push af ;0f00h @ aa54h
+ push iy ;aa56h @ aa52h
+ ld sp, 0fd00h
+ ex (sp), hl ;2345h @ fd00h read
+ ;cc34h @ fd00h write
+ inc sp
+ inc sp
+ ex (sp), ix ;6789h @ fd02h read
+ ;bb44h @ fd02h write
+ inc sp
+ inc sp
+ ex (sp), iy ;abcdh @ fd04h read
+ ;aa56h @ fd04h write
+ ld a, (ix+0h) ; ffh @ 6789h
+ ld b, (ix+1h) ; fdh @ 678ah
+ ld c, (ix+2h) ; fbh @ 678bh
+ ld d, (ix+3h) ; f9h @ 678ch
+ ld e, (ix+4h) ; f7h @ 678dh
+ ld h, (ix+5h) ; f5h @ 678eh
+ ld l, (ix+6h) ; f3h @ 678fh
+ ld sp, 0fd00h
+ push af ;ff00h @ fcfeh
+ push bc ;fdfbh @ fcfch
+ push de ;f9f7h @ fcfah
+ push hl ;f5f3h @ fcf8h
+ ld a, (iy+0h) ; 01h @ abcdh
+ ld b, (iy+1h) ; 03h @ abceh
+ ld c, (iy+2h) ; 05h @ abcfh
+ ld d, (iy+3h) ; 07h @ abd0h
+ ld e, (iy+4h) ; 09h @ abd1h
+ ld h, (iy+5h) ; 0bh @ abd2h
+ ld l, (iy+6h) ; 0dh @ abd3h
+ push af ;0100h @ fcf6h
+ push bc ;0305h @ fcf4h
+ push de ;0709h @ fcf2h
+ push hl ;0b0dh @ fcf0h
+ ld (ix-001h), a ; 01h @ 6788h
+ ld (ix-002h), b ; 03h @ 6787h
+ ld (ix-003h), c ; 05h @ 6786h
+ ld (ix-004h), d ; 07h @ 6785h
+ ld (ix-005h), e ; 09h @ 6784h
+ ld (ix-006h), h ; 0bh @ 6783h
+ ld (ix-007h), l ; 0dh @ 6782h
+ ld (ix-008h), 0fh ;0fh @ 6781h
+ ld (iy-001h), a ; 01h @ abcch
+ ld (iy-002h), b ; 03h @ abcbh
+ ld (iy-003h), c ; 05h @ abcah
+ ld (iy-004h), d ; 07h @ abc9h
+ ld (iy-005h), e ; 09h @ abc8h
+ ld (iy-006h), h ; 0bh @ abc7h
+ ld (iy-007h), l ; 0dh @ abc6h
+ ld (iy-008h), 0fh ;0fh @ abc5h
+ xor a
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ exx
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ exx
+ ex af, af'
+ xor a
+ ld a, 0ffh
+ ld r, a
+ push af ;ff44h @ fceeh
+ push bc ;0000h @ fcech
+ push de ;0000h @ fceah
+ push hl ;0000h @ fce8h
+ xor a
+ push af ;0044h @ fce6h
+ ld a, r
+ push af ;ff80h @ fce4h
+ push bc ;0000h @ fce2h
+ push de ;0000h @ fce0h
+ push hl ;0000h @ fcdeh
+ xor a
+ ld r, a
+ ld a, 55h
+ ld i, a
+ push af ;5544h @ fcdch
+ push bc ;0000h @ fcdah
+ push de ;0000h @ fcd8h
+ push hl ;0000h @ fcd6h
+ xor a
+ push af ;0044h @ fcd4h
+ ld a, i
+ push af ;5500h @ fcd2h
+ ei
+ ld a, i
+ push af ;5504h @ fcd0h
+ di
+ ld a, i
+ push af ;5500h @ fcceh
+;-------------
+ xor a
+ ld sp, 0fc00h
+ ld ix, 00000h
+ ld iy, 0ffffh
+ ld bc, 0aaaah
+ ld de, 05555h
+ ld hl, 02222h
+ ld xh, 0a5h
+ push ix ;a500h @ fbfeh
+ ld xl, 057h
+ push ix ;a557h @ fbfch
+ ld yh, 0beh
+ push iy ;beffh @ fbfah
+ ld yl, 03dh
+ push iy ;be3dh @ fbf8h
+ push af ;0044h @ fbf6h
+ push bc ;aaaah @ fbf4h
+ push de ;5555h @ fbf2h
+ push hl ;2222h @ fbf0h
+;
+ ld a,xh
+ push af ;a544h @ fbeeh
+ ld a,xl
+ push af ;5744h @ fbech
+ ld a,yh
+ push af ;be44h @ fbeah
+ ld a,yl
+ push af ;3d44h @ fbe8h
+;
+ ld a,05h
+ ld xl,a
+ ld a,0feh
+ ld yh,a
+ ld a,0adh
+ ld xh,a
+ ld a,7eh
+ ld yl,a
+ push ix ;ad05h @ fbe6h
+ push iy ;fe7eh @ fbe4h
+ push af ;7e44h @ fbe2h
+;
+ ld b,xh
+ ld c,xl
+ ld xl,b
+ ld xh,c
+ push bc ;ad05h @ fbe0h
+ push ix ;05adh @ fbdeh
+ ld b,yh
+ ld c,yl
+ ld yl,b
+ ld yh,c
+ push bc ;fe7eh @ fbdch
+ push iy ;7efeh @ fbdah
+ ld b,xl
+ ld c,xh
+ ld xh,b
+ ld xl,c
+ push bc ;ad05h @ fbd8h
+ push ix ;ad05h @ fbd6h
+ ld b,yl
+ ld c,yh
+ ld yh,b
+ ld yl,c
+ push bc ;fe7eh @ fbd4h
+ push iy ;fe7eh @ fbd2h
+ push af ;7e44h @ fbd0h
+
+ ld e,xh
+ ld d,xl
+ ld xl,e
+ ld xh,d
+ push de ;05adh @ fbceh
+ push ix ;05adh @ fbcch
+ ld d,yh
+ ld e,yl
+ ld yl,d
+ ld yh,e
+ push de ;fe7eh @ fbcah
+ push iy ;7efeh @ fbc8h
+ ld e,xl
+ ld d,xh
+ ld xh,e
+ ld xl,d
+ push de ;05adh @ fbc6h
+ push ix ;ad05h @ fbc4h
+ ld d,yl
+ ld e,yh
+ ld yh,d
+ ld yl,e
+ push de ;fe7eh @ fbc2h
+ push iy ;fe7eh @ fbc0h
+ ld a,xl
+ ld xl,xh
+ ld xh,a
+ push ix ;05adh @ fbbeh
+ ld a,yl
+ ld yl,yh
+ ld yh,a
+ push iy ;7efeh @ fbbch
+ push bc ;fe7eh @ fbbah
+ push hl ;2222h @ fbb8h
+;-------------
+ ld hl, 0100h ;init hl for next pattern
+ jp 0c0h
+
+ org 02020h ;data for ld r,(hl)
+ db 05ah
+ db 069h
+ db 078h
+ db 087h
+ db 096h
+ db 0a5h
+
+ org 05a69h ;data for ld a,(bc)
+ db 0b4h
+
+ org 06789h ;data for ld r,(ix+d)
+ db 0ffh
+ db 0fdh
+ db 0fbh
+ db 0f9h
+ db 0f7h
+ db 0f5h
+ db 0f3h
+
+ org 07887h ;data for ld rr,(mn)
+ db 0c3h
+ db 0d2h
+ dw 0e1f0h
+ dw 00f1eh
+ dw 02d3ch
+ dw 04b5ah
+ dw 06978h
+ dw 0fe00h
+
+ org 0abcdh ;dta for ld r,(iy+d)
+ db 01h
+ db 03h
+ db 05h
+ db 07h
+ db 09h
+ db 0bh
+ db 0dh
+
+ org 0f000h ;data for pop
+ dw 00f00h
+ dw 0ee11h
+ dw 0dd22h
+ dw 0cc33h
+ dw 0bb44h
+ dw 0aa55h
+
+ org 0fd00h ;data for ex (sp),
+ dw 02345h
+ dw 06789h
+ dw 0abcdh
+
+ end
Index: tags/ez80-instructions/asm/dat_movd.s
===================================================================
--- tags/ez80-instructions/asm/dat_movd.s (nonexistent)
+++ tags/ez80-instructions/asm/dat_movd.s (revision 9)
@@ -0,0 +1,86 @@
+;**********************************************************************************
+;* *
+;* dat_mov compare data *
+;* *
+;**********************************************************************************
+ org 0102h
+ db 0f0h
+
+ org 0408h
+ db 00fh
+
+ org 01020h
+ db 00fh, 001h, 002h, 004h, 008h, 010h, 026h, 03ch
+
+ org 6780h
+ db 0ffh, 00fh, 00dh, 00bh, 009h, 007h, 005h, 003h
+ db 001h
+
+ org 07895h
+ db 0d2h ;7895h
+ dw 0e1f0h ;7896h
+ dw 00f1eh, 02d3ch, 04b5ah, 06978h ;7898h
+ dw 0fe00h ;78a0h
+
+ org 0aa50h
+ dw 0ffffh, 0aa56h, 00f00h, 0ffffh ;aa50h
+
+ org 0abc0h
+ db 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 00fh, 00dh, 00bh
+ db 009h, 007h, 005h, 003h, 001h
+
+ org 0bb40h
+ dw 0bb44h, 00f00h, 0ffffh, 0ffffh ;bb40h
+
+ org 0cc30h
+ dw 0cc34h, 00f00h, 0ffffh, 0ffffh ;cc30h
+
+ org 0fbb8h
+ dw 02222h, 0fe7eh, 07efeh, 005adh ;fbb8h
+ dw 0fe7eh, 0fe7eh, 0ad05h, 005adh ;fbc0h
+ dw 07efeh, 0fe7eh, 005adh, 005adh ;fbc8h
+ dw 07e44h, 0fe7eh, 0fe7eh, 0ad05h ;fbd0h
+ dw 0ad05h, 07efeh, 0fe7eh, 005adh ;fbd8h
+ dw 0ad05h, 07e44h, 0fe7eh, 0ad05h ;fbe0h
+ dw 03d44h, 0be44h, 05744h, 0a544h ;fbe8h
+ dw 02222h, 05555h, 0aaaah, 00044h ;fbf0h
+ dw 0be3dh, 0beffh, 0a557h, 0a500h ;fbf8h
+
+ org 0fcc8h
+ dw 0ffffh, 0ffffh, 0ffffh, 05500h ;fcc8h
+ dw 05504h, 05500h, 00044h, 00000h ;fcd0h
+ dw 00000h, 00000h, 05544h, 00000h ;fcd8h
+ dw 00000h, 00000h, 0ff80h, 00044h ;fce0h
+ dw 00000h, 00000h, 00000h, 0ff44h ;fce8h
+ dw 00b0dh, 00709h, 00305h, 00100h ;fcf0h
+ dw 0f5f3h, 0f9f7h, 0fdfbh, 0ff00h ;fcf8h
+ dw 0cc34h, 0bb44h, 0aa56h, 0ffffh ;fd00h
+
+ org 0fdf0h
+ dw 0ffffh, 0ffffh, 0aa55h, 0bb44h ;fdf0h
+ dw 0cc33h, 0dd22h, 0ee11h, 00f00h ;fdf8h
+
+ org 0ff58h
+ dw 0ffffh, 0d244h, 0c344h, 0b444h ;ff58h
+ dw 020a5h, 09624h, 02024h, 07887h ;ff60h
+ dw 05a69h, 02044h, 02020h, 02020h ;ff68h
+ dw 02020h, 02044h, 02010h, 02010h ;ff70h
+ dw 02010h, 01044h, 02008h, 00810h ;ff78h
+ dw 01020h, 00844h, 00810h, 02004h ;ff80h
+ dw 00810h, 00444h, 00204h, 01020h ;ff88h
+ dw 00408h, 00244h, 02001h, 00810h ;ff90h
+ dw 00204h, 00184h, 01020h, 00408h ;ff98h
+ dw 00102h, 0ff84h, 0efdfh, 0fbf7h ;ffa0h
+ dw 0fefdh, 0ff84h, 0fbf7h, 0efdfh ;ffa8h
+ dw 0fefdh, 0ff84h, 01020h, 00408h ;ffb0h
+ dw 00102h, 0ff84h, 00408h, 01020h ;ffb8h
+ dw 00102h, 0ff84h, 0fbf7h, 0efdfh ;ffc0h
+ dw 0fefdh, 0ff84h, 0efdfh, 0fbf7h ;ffc8h
+ dw 0fefdh, 0ff84h, 00408h, 01020h ;ffd0h
+ dw 00102h, 0ff84h, 01020h, 00408h ;ffd8h
+ dw 00102h, 0ff84h, 0efdfh, 0fbf7h ;ffe0h
+ dw 0fefdh, 0ff84h, 01020h, 00408h ;ffe8h
+ dw 00102h, 00f44h, 05555h, 0aaaah ;fff0h
+ dw 01020h, 00408h, 00102h, 00044h ;fff8h
+
+ end
Index: tags/ez80-instructions/asm/alu_ops.s
===================================================================
--- tags/ez80-instructions/asm/alu_ops.s (nonexistent)
+++ tags/ez80-instructions/asm/alu_ops.s (revision 9)
@@ -0,0 +1,1338 @@
+;**********************************************************************************
+;* *
+;* checks all alu operation instructions *
+;* *
+;**********************************************************************************
+ aseg
+
+ org 00h
+ jp 100h
+
+ org 0c0h ;pattern finish location
+ nop
+ jr 0c0h
+
+ org 0100h
+ ld sp, 0000h ;point sp at result table
+ ld a, 0ffh ;initialize the main registers
+ xor a ;initialize flags
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ ld ix, 05678h
+ ld iy, 0789ah
+ ccf
+ push af ;0045h @ fffeh
+ ccf
+ push af ;0044h @ fffch
+ scf
+ push af ;0045h @ fffah
+ scf
+ push af ;0045h @ fff8h
+ ld a, 80h
+ cpl
+ push af ;7f57h @ fff6h
+ cpl
+ push af ;8057h @ fff4h
+ xor a
+ neg
+ push af ;0042h @ fff2h
+ inc a
+ neg
+ push af ;ff93h @ fff0h
+ ld a, 02h
+ neg
+ push af ;fe93h @ ffeeh
+ neg
+ push af ;0213h @ ffech
+ ld a, 80h
+ neg
+ push af ;8087h @ ffeah
+ xor a
+ dec bc
+ push bc ;ffffh @ ffe8h
+ inc bc
+ push bc ;0000h @ ffe6h
+ inc bc
+ push bc ;0001h @ ffe4h
+ dec de
+ push de ;ffffh @ ffe2h
+ inc de
+ push de ;0000h @ ffe0h
+ dec hl
+ push hl ;ffffh @ ffdeh
+ inc hl
+ push hl ;0000h @ ffdch
+ dec ix
+ push ix ;5677h @ ffdah
+ dec iy
+ push iy ;7899h @ ffd8h
+ dec sp
+ dec sp
+ push iy ;7899h @ ffd4h
+ inc ix
+ push ix ;5678h @ ffd2h
+ push iy ;7899h @ ffd0h
+ inc iy
+ push ix ;5678h @ ffceh
+ push iy ;789ah @ ffcch
+ ld sp, 0ffa0h
+ inc sp
+ inc sp
+ push af ;0044h @ ffa0h
+ push bc ;0001h @ ff9eh
+ push de ;0000h @ ff9ch
+ push hl ;0000h @ ff9ah
+ ld bc, 5454h
+ ld de, 1234h
+ ld hl, 0fdb9h
+ add hl, bc
+ push af ;0055h @ ff98h
+ push bc ;5454h @ ff96h
+ push de ;1234h @ ff94h
+ push hl ;520dh @ ff92h
+ add hl, de
+ push af ;0044h @ ff90h
+ push bc ;5454h @ ff8eh
+ push de ;1234h @ ff8ch
+ push hl ;6441h @ ff8ah
+ add hl, hl
+ push af ;0044h @ ff88h
+ push bc ;5454h @ ff86h
+ push de ;1234h @ ff84h
+ push hl ;c882h @ ff82h
+ add hl, sp
+ push af ;0055h @ ff80h
+ push bc ;5454h @ ff7eh
+ push de ;1234h @ ff7ch
+ push hl ;c804h @ ff7ah
+ push ix ;5678h @ ff78h
+ push iy ;789ah @ ff76h
+ add ix, bc
+ push af ;0044h @ ff74h
+ push bc ;5454h @ ff72h
+ push de ;1234h @ ff70h
+ push hl ;c804h @ ff6eh
+ push ix ;aacch @ ff6ch
+ push iy ;789ah @ ff6ah
+ add ix, de
+ push af ;0044h @ ff68h
+ push bc ;5454h @ ff66h
+ push de ;1234h @ ff64h
+ push hl ;c804h @ ff62h
+ push ix ;bd00h @ ff60h
+ push iy ;789ah @ ff5eh
+ add ix, sp
+ push af ;0055h @ ff5ch
+ push bc ;5454h @ ff5ah
+ push de ;1234h @ ff58h
+ push hl ;c804h @ ff56h
+ push ix ;bc5eh @ ff54h
+ push iy ;789ah @ ff52h
+ add ix, ix
+ push af ;0055h @ ff50h
+ push bc ;5454h @ ff4eh
+ push de ;1234h @ ff4ch
+ push hl ;c804h @ ff4ah
+ push ix ;78bch @ ff48h
+ push iy ;789ah @ ff46h
+ add iy, bc
+ push af ;0044h @ ff44h
+ push bc ;5454h @ ff42h
+ push de ;1234h @ ff40h
+ push hl ;c804h @ ff3eh
+ push ix ;78bch @ ff3ch
+ push iy ;cceeh @ ff3ah
+ add iy, de
+ push af ;0044h @ ff38h
+ push bc ;5454h @ ff36h
+ push de ;1234h @ ff34h
+ push hl ;c804h @ ff32h
+ push ix ;78bch @ ff30h
+ push iy ;df22h @ ff2eh
+ add iy, sp
+ push af ;0055h @ ff2ch
+ push bc ;5454h @ ff2ah
+ push de ;1234h @ ff28h
+ push hl ;c804h @ ff26h
+ push ix ;78bch @ ff24h
+ push iy ;de50h @ ff22h
+ add iy, iy
+ push af ;0055h @ ff20h
+ push bc ;5454h @ ff1eh
+ push de ;1234h @ ff1ch
+ push hl ;c804h @ ff1ah
+ push ix ;78bch @ ff18h
+ push iy ;bca0h @ ff16h
+ ld sp, 0ff00h
+ xor a
+ inc a
+ push af ;0100h @ fefeh
+ ld a, 0fh
+ inc a
+ push af ;1010h @ fefch
+ ld a, 7fh
+ inc a
+ push af ;8094h @ fefah
+ ld a, 0ffh
+ inc a
+ push af ;0050h @ fef8h
+ dec a
+ push af ;ff92h @ fef6h
+ dec a
+ push af ;fe82h @ fef4h
+ ld a, 10h
+ dec a
+ push af ;0f12h @ fef2h
+ ld a, 80h
+ dec a
+ push af ;7f16h @ fef0h
+ push bc ;5454h @ feeeh
+ push de ;1234h @ feech
+ push hl ;c804h @ feeah
+ push ix ;78bch @ fee8h
+ push iy ;bca0h @ fee6h
+ inc b
+ inc d
+ inc d
+ inc h
+ inc h
+ inc h
+ push af ;7f80h @ fee4h
+ push bc ;5554h @ fee2h
+ push de ;1434h @ fee0h
+ push hl ;cb04h @ fedeh
+ inc c
+ inc c
+ inc c
+ inc e
+ inc e
+ inc l
+ push af ;7f00h @ fedch
+ push bc ;5557h @ fedah
+ push de ;1436h @ fed8h
+ push hl ;cb05h @ fed6h
+ dec b
+ dec b
+ dec b
+ dec d
+ dec d
+ dec h
+ push af ;7f82h @ fed4h
+ push bc ;5257h @ fed2h
+ push de ;1236h @ fed0h
+ push hl ;ca05h @ feceh
+ dec c
+ dec e
+ dec e
+ dec l
+ dec l
+ dec l
+ push af ;7f02h @ fecch
+ push bc ;5256h @ fecah
+ push de ;1234h @ fec8h
+ push hl ;ca02h @ fec6h
+ push ix ;78bch @ fec4h
+ push iy ;bca0h @ fec2h
+ inc (hl) ; 1fh @ ca02h read
+ ; 20h @ ca02h write
+ push af ;7f10h @ fec0h
+ inc hl
+ dec (hl) ; 00h @ ca03h
+ ; ffh @ ca03h
+ push af ;7f92h @ febeh
+ inc (ix+0fh) ; 2eh @ 78cbh read
+ ; 2fh @ 78cbh write
+ dec (ix+10h) ; c0h @ 78cch read
+ ; bfh @ 78cch write
+ inc (iy-02h) ; f0h @ bc9eh read
+ ; f1h @ bc9eh write
+ dec (iy-01h) ; 80h @ bc9fh read
+ ; 7fh @ bc9fh write
+ push af ;7f16h @ febch
+ push bc ;5256h @ febah
+ push de ;1234h @ feb8h
+ push hl ;ca03h @ feb6h
+ push ix ;78bch @ feb4h
+ push iy ;bca0h @ feb2h
+ xor a
+ adc hl, bc
+ push af ;0001h @ feb0h
+ push bc ;5256h @ feaeh
+ push de ;1234h @ feach
+ push hl ;1c59h @ feaah
+ scf
+ adc hl, bc
+ push af ;0000h @ fea8h
+ push bc ;5256h @ fea6h
+ push de ;1234h @ fea4h
+ push hl ;6eb0h @ fea2h
+ and a
+ adc hl, de
+ push af ;0094h @ fea0h
+ push bc ;5256h @ fe9eh
+ push de ;1234h @ fe9ch
+ push hl ;80e4h @ fe9ah
+ scf
+ adc hl, de
+ push af ;0080h @ fe98h
+ push bc ;5256h @ fe96h
+ push de ;1234h @ fe94h
+ push hl ;9319h @ fe92h
+ and a
+ adc hl, hl
+ push af ;0005h @ fe90h
+ push bc ;5256h @ fe8eh
+ push de ;1234h @ fe8ch
+ push hl ;2632h @ fe8ah
+ scf
+ adc hl, hl
+ push af ;0000h @ fe88h
+ push bc ;5256h @ fe86h
+ push de ;1234h @ fe84h
+ push hl ;4c65h @ fe82h
+ and a
+ adc hl, sp
+ push af ;0011h @ fe80h
+ push bc ;5256h @ fe7eh
+ push de ;1234h @ fe7ch
+ push hl ;4ae7h @ fe7ah
+ scf
+ adc hl, sp
+ push af ;0011h @ fe78h
+ push bc ;5256h @ fe76h
+ push de ;1234h @ fe74h
+ push hl ;4962h @ fe72h
+ and a
+ sbc hl, bc
+ push af ;0083h @ fe70h
+ push bc ;5256h @ fe6eh
+ push de ;1234h @ fe6ch
+ push hl ;f70ch @ fe6ah
+ scf
+ sbc hl, bc
+ push af ;0082h @ fe68h
+ push bc ;5256h @ fe66h
+ push de ;1234h @ fe64h
+ push hl ;a4b5h @ fe62h
+ and a
+ sbc hl, de
+ push af ;0082h @ fe60h
+ push bc ;5256h @ fe5eh
+ push de ;1234h @ fe5ch
+ push hl ;9281h @ fe5ah
+ scf
+ sbc hl, de
+ push af ;0082h @ fe58h
+ push bc ;5256h @ fe56h
+ push de ;1234h @ fe54h
+ push hl ;804ch @ fe52h
+ and a
+ sbc hl, sp
+ push af ;0093h @ fe50h
+ push bc ;5256h @ fe4eh
+ push de ;1234h @ fe4ch
+ push hl ;81fah @ fe4ah
+ scf
+ sbc hl, sp
+ push af ;0093h @ fe48h
+ push bc ;5256h @ fe46h
+ push de ;1234h @ fe44h
+ push hl ;83afh @ fe42h
+ and a
+ sbc hl, hl
+ push af ;0042h @ fe40h
+ push bc ;5256h @ fe3eh
+ push de ;1234h @ fe3ch
+ push hl ;0000h @ fe3ah
+ scf
+ sbc hl, hl
+ push af ;0093h @ fe38h
+ push bc ;5256h @ fe36h
+ push de ;1234h @ fe34h
+ push hl ;ffffh @ fe32h
+ ld sp, 0fe00h
+ ld ix, 01000h
+ ld iy, 02000h
+ xor a
+ scf
+ ld a, 0aah
+ ld b, 0c0h
+ ld c, 030h
+ ld d, 0ch
+ ld e, 03h
+ ld h, 055h
+ ld l, 08ah
+ and b
+ push af ;8090h @ fdfeh
+ ld a, 0aah
+ and c
+ push af ;2010h @ fdfch
+ ld a, 0aah
+ and d
+ push af ;0810h @ fdfah
+ ld a, 0aah
+ and e
+ push af ;0210h @ fdf8h
+ ld a, 0aah
+ and h
+ push af ;0054h @ fdf6h
+ ld a, 0aah
+ and l
+ push af ;8a90h @ fdf4h
+ and 5fh
+ push af ;0a14h @ fdf2h
+ ld hl, 03000h
+ ld a, 0aah
+ and (hl) ; 3ch @ 3000h
+ push af ;2814h @ fdf0h
+ and (ix+0h) ; c7h @ 1000h
+ push af ;0054h @ fdeeh
+ ld a, 0aah
+ and (iy+0h) ; 82h @ 2000h
+ push af ;8294h @ fdech
+ scf
+ ld a, 0aah
+ ld b, 060h
+ ld c, 030h
+ ld d, 0aeh
+ ld e, 07h
+ ld h, 0aah
+ ld l, 08ah
+ xor b
+ push af ;ca84h @ fdeah
+ ld a, 0aah
+ xor c
+ push af ;9a84h @ fde8h
+ ld a, 0aah
+ xor d
+ push af ;0400h @ fde6h
+ ld a, 0aah
+ xor e
+ push af ;ad80h @ fde4h
+ ld a, 0aah
+ xor h
+ push af ;0044h @ fde2h
+ ld a, 0aah
+ xor l
+ push af ;2000h @ fde0h
+ xor 0ffh
+ push af ;df80h @ fddeh
+ ld hl, 03001h
+ ld a, 0aah
+ xor (hl) ; 55h @ 3001h
+ push af ;ff84h @ fddch
+ xor (ix+1h) ; a2h @ 1001h
+ push af ;5d00h @ fddah
+ ld a, 0aah
+ xor (iy+1h) ; abh @ 2001h
+ push af ;0100h @ fdd8h
+ scf
+ ld a, 0aah
+ ld b, 060h
+ ld c, 030h
+ ld d, 0aeh
+ ld e, 07h
+ ld h, 055h
+ ld l, 0h
+ or b
+ push af ;ea80h @ fdd6h
+ ld a, 0aah
+ or c
+ push af ;ba80h @ fdd4h
+ ld a, 0aah
+ or d
+ push af ;ae80h @ fdd2h
+ ld a, 0aah
+ or e
+ push af ;af84h @ fdd0h
+ ld a, 0aah
+ or h
+ push af ;ff84h @ fdceh
+ ld a, 0h
+ or l
+ push af ;0044h @ fdcch
+ or 055h
+ push af ;5504h @ fdcah
+ ld hl, 03002h
+ ld a, 08eh
+ or (hl) ; 55h @ 3002h
+ push af ;df80h @ fdc8h
+ ld a, 0fh
+ or (ix+2h) ; 80h @ 1002h
+ push af ;8f80h @ fdc6h
+ ld a, 20h
+ or (iy+2h) ; 78h @ 2002h
+ push af ;7804h @ fdc4h
+ scf
+ ld a, 0aah
+ ld b, 060h
+ ld c, 030h
+ ld d, 0aeh
+ ld e, 07h
+ ld h, 055h
+ ld l, 0f6h
+ add a, b
+ push af ;0a01h @ fdc2h
+ ld a, 0aah
+ add a, c
+ push af ;da80h @ fdc0h
+ ld a, 0aah
+ add a, d
+ push af ;5815h @ fdbeh
+ ld a, 0aah
+ add a, e
+ push af ;b190h @ fdbch
+ ld a, 0aah
+ add a, h
+ push af ;ff80h @ fdbah
+ ld a, 0aah
+ add a, l
+ push af ;a091h @ fdb8h
+ add a, 055h
+ push af ;f580h @ fdb6h
+ ld hl, 03003h
+ ld a, 0aah
+ add a, (hl) ; ffh @ 3003h
+ push af ;a991h @ fdb4h
+ ld a, 0fh
+ add a, (ix+3h) ; 01h @ 1003h
+ push af ;1010h @ fdb2h
+ ld a, 20h
+ add a, (iy+3h) ; 78h @ 2003h
+ push af ;9884h @ fdb0h
+ scf
+ ld a, 0aah
+ ld b, 060h
+ ld c, 030h
+ ld d, 0aeh
+ ld e, 07h
+ ld h, 055h
+ ld l, 0f6h
+ sub b
+ push af ;4a06h @ fdaeh
+ ld a, 0aah
+ sub c
+ push af ;7a06h @ fdach
+ ld a, 0aah
+ sub d
+ push af ;fc93h @ fdaah
+ ld a, 0aah
+ sub e
+ push af ;a382h @ fda8h
+ ld a, 0aah
+ sub h
+ push af ;5506h @ fda6h
+ ld a, 0aah
+ sub l
+ push af ;b483h @ fda4h
+ sub 055h
+ push af ;5f16h @ fda2h
+ ld hl, 03004h
+ ld a, 0aah
+ sub (hl) ; aah @ 3004h
+ push af ;0042h @ fda0h
+ ld a, 0fh
+ sub (ix+4h) ; 01h @ 1004h
+ push af ;0e02h @ fd9eh
+ ld a, 20h
+ sub (iy+4h) ; 60h @ 2004h
+ push af ;c083h @ fd9ch
+ scf
+ ld a, 0aah
+ ld b, 060h
+ ld c, 030h
+ ld d, 0aeh
+ ld e, 07h
+ ld h, 055h
+ ld l, 0f6h
+ cp b
+ push af ;aa06h @ fd9ah
+ cp c
+ push af ;aa06h @ fd98h
+ cp d
+ push af ;aa93h @ fd96h
+ cp e
+ push af ;aa82h @ fd94h
+ cp h
+ push af ;aa06h @ fd92h
+ cp l
+ push af ;aa83h @ fd90h
+ ld a, 0b4h
+ cp 055h
+ push af ;b416h @ fd8eh
+ ld hl, 03005h
+ ld a, 0aah
+ cp (hl) ; aah @ 3005h
+ push af ;aa42h @ fd8ch
+ ld a, 0fh
+ cp (ix+5h) ; 01h @ 1005h
+ push af ;0f02h @ fd8ah
+ ld a, 20h
+ cp (iy+5h) ; 60h @ 2005h
+ push af ;2083h @ fd88h
+ scf
+ ld a, 0aah
+ ld b, 060h
+ ld c, 030h
+ ld d, 0aeh
+ ld e, 07h
+ ld h, 055h
+ ld l, 0f6h
+ adc a, b
+ push af ;0b01h @ fd86h
+ ld a, 0aah
+ adc a, c
+ push af ;db80h @ fd84h
+ ld a, 0aah
+ adc a, d
+ push af ;5815h @ fd82h
+ ld a, 0aah
+ adc a, e
+ push af ;b290h @ fd80h
+ ld a, 0aah
+ adc a, h
+ push af ;ff80h @ fd7eh
+ ld a, 0aah
+ adc a, l
+ push af ;a091h @ fd7ch
+ adc a, 055h
+ push af ;f680h @ fd7ah
+ ld hl, 03006h
+ ld a, 0aah
+ adc a, (hl) ; ffh @ 3006h
+ push af ;a991h @ fd78h
+ ld a, 0fh
+ adc a, (ix+6h) ; 01h @ 1006h
+ push af ;1110h @ fd76h
+ ld a, 20h
+ adc a, (iy+6h) ; 78h @ 2006h
+ push af ;9884h @ fd74h
+ scf
+ ld a, 0aah
+ ld b, 060h
+ ld c, 030h
+ ld d, 0aeh
+ ld e, 07h
+ ld h, 055h
+ ld l, 0f6h
+ sbc a, b
+ push af ;4906h @ fd72h
+ ld a, 0aah
+ sbc a, c
+ push af ;7a06h @ fd70h
+ ld a, 0aah
+ sbc a, d
+ push af ;fc93h @ fd6eh
+ ld a, 0aah
+ sbc a, e
+ push af ;a282h @ fd6ch
+ ld a, 0aah
+ sbc a, h
+ push af ;5506h @ fd6ah
+ ld a, 0aah
+ sbc a, l
+ push af ;b483h @ fd68h
+ sbc a, 055h
+ push af ;5e16h @ fd66h
+ ld hl, 03007h
+ ld a, 0aah
+ sbc a, (hl) ; aah @ 3007h
+ push af ;0042h @ fd64h
+ ld a, 0fh
+ sbc a, (ix+7h) ; 01h @ 1007h
+ push af ;0e02h @ fd62h
+ ld a, 20h
+ sbc a, (iy+7h) ; 60h @ 2007h
+ push af ;c083h @ fd60h
+ scf
+ xor a
+ push af ;0044h @ fd5eh
+ ld a, 38h
+ and a
+ push af ;3810h @ fd5ch
+ cp a
+ push af ;3842h @ fd5ah
+ add a, a
+ push af ;7010h @ fd58h
+ adc a, a
+ push af ;e084h @ fd56h
+ or a
+ push af ;e080h @ fd54h
+ scf
+ adc a, a
+ push af ;c181h @ fd52h
+ ccf
+ sbc a, a
+ push af ;0042h @ fd50h
+ scf
+ sbc a, a
+ push af ;ff93h @ fd4eh
+ sub a
+ push af ;0042h @ fd4ch
+ ld sp, 0fd00h
+ xor a
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ ld a, 35h
+ rlc a
+ push af ;6a04h @ fcfeh
+ rlc a
+ push af ;d484h @ fcfch
+ rlc a
+ push af ;a985h @ fcfah
+ rlc a
+ push af ;5305h @ fcf8h
+ rlc a
+ push af ;a684h @ fcf6h
+ rrc a
+ push af ;5304h @ fcf4h
+ rrc a
+ push af ;a985h @ fcf2h
+ rrc a
+ push af ;d485h @ fcf0h
+ rrc a
+ push af ;6a04h @ fceeh
+ rrc a
+ push af ;3504h @ fcech
+ rl a
+ push af ;6a04h @ fceah
+ rl a
+ push af ;d484h @ fce8h
+ rl a
+ push af ;a881h @ fce6h
+ rl a
+ push af ;5101h @ fce4h
+ rl a
+ push af ;a384h @ fce2h
+ rr a
+ push af ;5101h @ fce0h
+ rr a
+ push af ;a881h @ fcdeh
+ rr a
+ push af ;d484h @ fcdch
+ rr a
+ push af ;6a04h @ fcdah
+ rr a
+ push af ;3504h @ fcd8h
+ sla a
+ push af ;6a04h @ fcd6h
+ sla a
+ push af ;d484h @ fcd4h
+ sla a
+ push af ;a881h @ fcd2h
+ sla a
+ push af ;5005h @ fcd0h
+ sla a
+ push af ;a084h @ fcceh
+ ld a, 35h
+ sra a
+ push af ;1a01h @ fccch
+ sra a
+ push af ;0d00h @ fccah
+ sra a
+ push af ;0605h @ fcc8h
+ ld a, 86h
+ sra a
+ push af ;c384h @ fcc6h
+ sra a
+ push af ;e185h @ fcc4h
+ ld a, 35h
+ srl a
+ push af ;1a01h @ fcc2h
+ srl a
+ push af ;0d00h @ fcc0h
+ srl a
+ push af ;0605h @ fcbeh
+ ld a, 86h
+ srl a
+ push af ;4300h @ fcbch
+ srl a
+ push af ;2105h @ fcbah
+ push bc ;0000h @ fcb8h
+ push de ;0000h @ fcb6h
+ push hl ;0000h @ fcb4h
+ xor a
+ ld bc, 05867h
+ ld de, 09acbh
+ ld hl, 021f0h
+ rlc b
+ push bc ;b067h @ fcb2h
+ rlc c
+ push bc ;b0ceh @ fcb0h
+ rlc d
+ push de ;35cbh @ fcaeh
+ rlc e
+ push de ;3597h @ fcach
+ rlc h
+ push hl ;42f0h @ fcaah
+ rlc l
+ push hl ;42e1h @ fca8h
+ push af ;0085h @ fca6h
+ ld bc, 05867h
+ ld de, 09acbh
+ ld hl, 021f0h
+ rrc b
+ push bc ;2c67h @ fca4h
+ rrc c
+ push bc ;2cb3h @ fca2h
+ rrc d
+ push de ;4dcbh @ fca0h
+ rrc e
+ push de ;4de5h @ fc9eh
+ rrc h
+ push hl ;90f0h @ fc9ch
+ rrc l
+ push hl ;9078h @ fc9ah
+ push af ;0004h @ fc98h
+ ld bc, 05867h
+ ld de, 09acbh
+ ld hl, 021f0h
+ rl b
+ push bc ;b067h @ fc96h
+ rl c
+ push bc ;b0ceh @ fc94h
+ rl d
+ push de ;34cbh @ fc92h
+ rl e
+ push de ;3497h @ fc90h
+ rl h
+ push hl ;43f0h @ fc8eh
+ rl l
+ push hl ;43e0h @ fc8ch
+ push af ;0081h @ fc8ah
+ ld bc, 05867h
+ ld de, 09acbh
+ ld hl, 021f0h
+ rr b
+ push bc ;ac67h @ fc88h
+ rr c
+ push bc ;ac33h @ fc86h
+ rr d
+ push de ;cdcbh @ fc84h
+ rr e
+ push de ;cd65h @ fc82h
+ rr h
+ push hl ;90f0h @ fc80h
+ rr l
+ push hl ;90f8h @ fc7eh
+ push af ;0080h @ fc7ch
+ ld bc, 05867h
+ ld de, 09acbh
+ ld hl, 021f0h
+ sla b
+ push bc ;b067h @ fc7ah
+ sla c
+ push bc ;b0ceh @ fc78h
+ sla d
+ push de ;34cbh @ fc76h
+ sla e
+ push de ;3496h @ fc74h
+ sla h
+ push hl ;42f0h @ fc72h
+ sla l
+ push hl ;42e0h @ fc70h
+ push af ;0081h @ fc6eh
+ ld bc, 05867h
+ ld de, 09acbh
+ ld hl, 021f0h
+ sra b
+ push bc ;2c67h @ fc6ch
+ sra c
+ push bc ;2c33h @ fc6ah
+ sra d
+ push de ;cdcbh @ fc68h
+ sra e
+ push de ;cde5h @ fc66h
+ sra h
+ push hl ;10f0h @ fc64h
+ sra l
+ push hl ;10f8h @ fc62h
+ push af ;0080h @ fc60h
+ ld bc, 05867h
+ ld de, 09acbh
+ ld hl, 021f0h
+ srl b
+ push bc ;2c67h @ fc5eh
+ srl c
+ push bc ;2c33h @ fc5ch
+ srl d
+ push de ;4dcbh @ fc5ah
+ srl e
+ push de ;4d65h @ fc58h
+ srl h
+ push hl ;10f0h @ fc56h
+ srl l
+ push hl ;1078h @ fc54h
+ push af ;0004h @ fc52h
+ ld hl, 3008h
+ rlc (hl) ; c5h @ 3008h read
+ ; 8bh @ 3008h write
+ push af ;0085h @ fc50h
+ inc hl
+ rrc (hl) ; c5h @ 3009h read
+ ; e2h @ 3009h write
+ push af ;0085h @ fc4eh
+ inc hl
+ rl (hl) ; c5h @ 300ah read
+ ; 8bh @ 300ah write
+ push af ;0085h @ fc4ch
+ inc hl
+ rr (hl) ; c4h @ 300bh read
+ ; e2h @ 300bh write
+ push af ;0084h @ fc4ah
+ inc hl
+ sla (hl) ; c5h @ 300ch read
+ ; 8ah @ 300ch write
+ push af ;0081h @ fc48h
+ ccf
+ inc hl
+ sra (hl) ; c5h @ 300dh read
+ ; e2h @ 300dh write
+ push af ;0085h @ fc46h
+ inc hl
+ srl (hl) ; c5h @ 300eh read
+ ; 62h @ 300eh write
+ push af ;0001h @ fc44h
+ rlc (ix+8h) ; 67h @ 1008h read
+ ; ceh @ 1008h write
+ push af ;0080h @ fc42h
+ rrc (ix+9h) ; 67h @ 1009h read
+ ; b3h @ 1009 write
+ push af ;0081h @ fc40h
+ rl (ix+0ah) ; 67h @ 100ah read
+ ; cfh @ 100ah write
+ push af ;0084h @ fc3eh
+ rr (ix+0bh) ; 67h @ 100bh read
+ ; 33h @ 100bh write
+ push af ;0005h @ fc3ch
+ sla (ix+0ch) ; 67h @ 100ch read
+ ; ceh @ 100ch write
+ push af ;0080h @ fc3ah
+ sra (ix+0dh) ; 67h @ 100dh read
+ ; 33h @ 100dh write
+ push af ;0005h @ fc38h
+ srl (ix+0eh) ; 67h @ 100eh read
+ ; 33h @ 100eh write
+ push af ;0005h @ fc36h
+ rlc (iy+8h) ; f0h @ 2008h read
+ ; e1h @ 2008h write
+ push af ;0085h @ fc34h
+ rrc (iy+9h) ; f0h @ 2009h read
+ ; 78h @ 2009 write
+ push af ;0004h @ fc32h
+ rl (iy+0ah) ; f0h @ 200ah read
+ ; e0h @ 200ah write
+ push af ;0081h @ fc30h
+ rr (iy+0bh) ; f0h @ 200bh read
+ ; f8h @ 200bh write
+ push af ;0080h @ fc2eh
+ sla (iy+0ch) ; f0h @ 200ch read
+ ; e0h @ 200ch write
+ push af ;0081h @ fc2ch
+ sra (iy+0dh) ; f0h @ 200dh read
+ ; f8h @ 200dh write
+ push af ;0080h @ fc2ah
+ srl (iy+0eh) ; f0h @ 200eh read
+ ; 78h @ 200eh write
+ push af ;0004h @ fc28h
+ xor a
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ ld a, 35h
+ rlca
+ push af ;6a44h @ fc26h
+ rlca
+ push af ;d444h @ fc24h
+ rlca
+ push af ;a945h @ fc22h
+ rlca
+ push af ;5345h @ fc20h
+ rlca
+ push af ;a644h @ fc1eh
+ rrca
+ push af ;5344h @ fc1ch
+ rrca
+ push af ;a945h @ fc1ah
+ rrca
+ push af ;d445h @ fc18h
+ rrca
+ push af ;6a44h @ fc16h
+ rrca
+ push af ;3544h @ fc14h
+ rla
+ push af ;6a44h @ fc12h
+ rla
+ push af ;d444h @ fc10h
+ rla
+ push af ;a845h @ fc0eh
+ rla
+ push af ;5145h @ fc0ch
+ rla
+ push af ;a344h @ fc0ah
+ rra
+ push af ;5145h @ fc08h
+ rra
+ push af ;a845h @ fc06h
+ rra
+ push af ;d444h @ fc04h
+ rra
+ push af ;6a44h @ fc02h
+ rra
+ push af ;3544h @ fc00h
+ ld bc, 05867h
+ ld de, 09acbh
+ ld hl, 021f0h
+ ld sp, 0fd48h
+ cp a
+ ld a, 35h
+ sll a
+ push af ;6b00h @ fd46h
+ sll a
+ push af ;d784h @ fd44h
+ sll a
+ push af ;af85h @ fd42h
+ add a,a ;set H flag
+ ld a,0afh
+ sll a
+ push af ;5f05h @ fd40h
+ sll a
+ push af ;bf80h @ fd3eh
+ push bc ;5867h @ fd3ch
+ push de ;9acbh @ fd3ah
+ push hl ;21f0h @ fd38h
+ sll b
+ push bc ;b167h @ fd36h
+ sll c
+ push bc ;b1cfh @ fd34h
+ sll d
+ push de ;35cbh @ fd32h
+ sll e
+ push de ;3597h @ fd30h
+ sll h
+ push hl ;43f0h @ fd2eh
+ sll l
+ push hl ;43e1h @ fd2ch
+ push af ;bf85h @ fd2ah
+ cp a
+ ld hl, 03011h
+ sll (hl) ; c5h @ 3011h read
+ ; 8bh @ 3011h write
+ push af ;bf85h @ fd28h
+ cp a
+ sll (ix+0fh) ; 66h @ 100fh read
+ ; cdh @ 100fh write
+ push af ;bf80h @ fd26h
+ cp a
+ sll (iy+0fh) ; f0h @ 200fh read
+ ; e1h @ 200fh write
+ push af ;bf85h @ fd24h
+ ld sp, 0fa00h
+ pop af ;9900h @ fa00h
+ ld sp, 0fb00h
+ daa
+ push af ;9984h @ fafeh
+ ld sp, 0fa02h
+ pop af ;8a00h @ fa02h
+ ld sp, 0fafeh
+ daa
+ push af ;9094h @ fafch
+ ld sp, 0fa04h
+ pop af ;7210h @ fa04h
+ ld sp, 0fafch
+ daa
+ push af ;7804h @ fafah
+ ld sp, 0fa06h
+ pop af ;a600h @ fa06h
+ ld sp, 0fafah
+ daa
+ push af ;0605h @ faf8h
+ ld sp, 0fa08h
+ pop af ;9b00h @ fa08h
+ ld sp, 0faf8h
+ daa
+ push af ;0111h @ faf6h
+ ld sp, 0fa0ah
+ pop af ;b110h @ fa0ah
+ ld sp, 0faf6h
+ daa
+ push af ;1705h @ faf4h
+ ld sp, 0fa0ch
+ pop af ;2401h @ fa0ch
+ ld sp, 0faf4h
+ daa
+ push af ;8485h @ faf2h
+ ld sp, 0fa0eh
+ pop af ;1f01h @ fa0eh
+ ld sp, 0faf2h
+ daa
+ push af ;8591h @ faf0h
+ ld sp, 0fa10h
+ pop af ;0111h @ fa10h
+ ld sp, 0faf0h
+ daa
+ push af ;6701h @ faeeh
+ ld sp, 0fa12h
+ pop af ;7702h @ fa12h
+ ld sp, 0faeeh
+ daa
+ push af ;7706h @ faech
+ ld sp, 0fa14h
+ pop af ;8812h @ fa14h
+ ld sp, 0faech
+ daa
+ push af ;8296h @ faeah
+ ld sp, 0fa16h
+ pop af ;7303h @ fa16h
+ ld sp, 0faeah
+ daa
+ push af ;1303h @ fae8h
+ ld sp, 0fa18h
+ pop af ;6613h @ fa18h
+ ld sp, 0fae8h
+ daa
+ push af ;0057h @ fae6h
+
+ xor a
+ ld sp, 0facch
+ ld hl, 0300fh
+ ld a, 67h
+ rld ; 2fh @ 300fh read
+ ; f7h @ 300fh write
+ push af ;6200h @ facah
+ inc hl
+ rrd ; e3h @ 3010h read
+ ; 2eh @ 3010h write
+ push af ;6304h @ fac8h
+;--------
+ ld hl,0aaaah
+ ld bc,0bcbch
+ ld de,0dedeh
+ ld sp,0fc00h
+ ld ix, 06030h
+ ld iy, 0ae07h
+ ld a, 0aah
+ adc a,xh
+ push af ;0a01h @ fbfeh
+ ld a, 0aah
+ adc a,xl
+ push af ;db80h @ fbfch
+ ld a, 0aah
+ adc a,yh
+ push af ;5815h @ fbfah
+ ld a, 0aah
+ adc a,yl
+ push af ;b290h @ fbf8h
+ ld a, 0aah
+ add a,xh
+ push af ;0a01h @ fbf6h
+ ld a, 0aah
+ add a,xl
+ push af ;da80h @ fbf4h
+ ld a, 0aah
+ add a,yh
+ push af ;5815h @ fbf2h
+ ld a, 0aah
+ add a,yl
+ push af ;b190h @ fbf0h
+ ld a,0aah
+ and xh
+ push af ;2010h @ fbeeh
+ ld a,0aah
+ and xl
+ push af ;2010h @ fbech
+ ld a,0aah
+ and yh
+ push af ;aa94h @ fbeah
+ ld a,0aah
+ and yl
+ push af ;0210h @ fbe8h
+ ld a,0aah
+ ld ix,0101h
+ ld iy,0101h
+ scf
+ dec xh
+ push af ;aa43h @ fbe6h
+ ccf
+ dec xh
+ push af ;aa92h @ fbe4h
+ dec xl
+ push af ;aa42h @ fbe2h
+ scf
+ dec xl
+ push af ;aa93h @ fbe0h
+ dec yh
+ push af ;aa43h @ fbdeh
+ dec yh
+ ccf
+ push af ;aa90h @ fbdch
+ dec yl
+ push af ;aa42h @ fbdah
+ dec yl
+ push af ;aa92h @ fbd8h
+ push ix ;ffffh @ fbd6h
+ push iy ;ffffh @ fbd4h
+ inc xh
+ push af ;aa50h @ fbd2h
+ inc xl
+ push af ;aa50h @ fbd0h
+ scf
+ inc yh
+ push af ;aa51h @ fbceh
+ inc yl
+ push af ;aa51h @ fbcch
+ inc xh
+ push af ;aa01h @ fbcah
+ ccf
+ inc xl
+ push af ;aa00h @ fbc8h
+ scf
+ inc yh
+ push af ;aa01h @ fbc6h
+ ccf
+ inc yl
+ push af ;aa00h @ fbc4h
+ push ix ;0101h @ fbc2h
+ push iy ;0101h @ fbc0h
+ ld ix, 06030h
+ ld iy, 0ae07h
+ ld a,0aah
+ or xh
+ push af ;ea80h @ fbbeh
+ ld a, 0aah
+ scf
+ or xl
+ push af ;ba80h @ fbbch
+ scf
+ ld a, 0aah
+ or yh
+ push af ;ae80h @ fbbah
+ ld a, 0aah
+ or yl
+ push af ;af84h @ fbb8h
+ ld a, 0aah
+ xor xh
+ push af ;ca84h @ fbb6h
+ ld a, 0aah
+ xor xl
+ push af ;9a84h @ fbb4h
+ ld a, 0aah
+ xor yh
+ push af ;0400h @ fbb2h
+ ld a, 0aah
+ xor yl
+ push af ;ad80h @ fbb0h
+ ld a, 060h
+ cp xh
+ push af ;6042h @ fbaeh
+ cp xl
+ push af ;6002h @ fbach
+ cp yh
+ push af ;6097h @ fbaah
+ cp yl
+ push af ;6012h @ fba8h
+ ld a, 0aah
+ sbc a,xh
+ push af ;4a06h @ fba6h
+ ld a, 0aah
+ sbc a,xl
+ push af ;7a06h @ fba4h
+ ld a, 0aah
+ sbc a,yh
+ push af ;fc93h @ fba2h
+ ld a, 0aah
+ sbc a,yl
+ push af ;a282h @ fba0h
+ ld a, 0aah
+ sub xh
+ push af ;4a06h @ fb9eh
+ ld a, 0aah
+ sub xl
+ push af ;7a06h @ fb9ch
+ ld a, 0aah
+ sub yh
+ push af ;fc93h @ fb9ah
+ ld a, 0aah
+ sub yl
+ push af ;a382h @ fb98h
+ push bc ;bcbch @ fb96h
+ push de ;dedeh @ fb94h
+ push hl ;aaaah @ fb92h
+ push ix ;6030h @ fb90h
+;--------
+; ld sp,0fb80h
+; ld ix,04000h
+; ld iy,04100h
+; xor a
+; set 0,(ix+0),a ;a0h @ 4000h read
+; ;a1h @ 4000h write
+; push af ;a140h @ fb7eh
+; and a
+; scf
+; set 1,(iy+0),b ;e0h @ 4100h read
+; ;e2h @ 4100h write
+; set 2,(ix+1),c ;b0h @ 4001h read
+; ;b4h @ 4001h write
+; set 3,(iy+1),d ;f0h @ 4101h read
+; ;f8h @ 4101h write
+; set 4,(ix+2),e ;0ch @ 4002h read
+; ;1ch @ 4002h write
+; set 5,(iy+2),h ;03h @ 4102h read
+; ;23h @ 4102h write
+; set 6,(ix+3),l ;0dh @ 4003h read
+; ;4dh @ 4003h write
+; set 7,(iy+3),a ;05h @ 4103h read
+; ;85h @ 4103h write
+; push af ;8501h @ fb7ch
+; push bc ;e2b4h @ fb7ah
+; push de ;f81ch @ fb78h
+; push hl ;234dh @ fb76h
+;--------
+ ld hl, 0100h
+ jp 0c0h
+
+ org 1000h
+ db 0c7h, 0a2h, 080h, 001h, 001h, 001h, 001h, 001h
+ db 067h, 067h, 067h, 067h, 067h, 067h, 067h, 066h
+
+ org 2000h
+ db 082h, 0abh, 078h, 078h, 060h, 060h, 078h, 060h
+ db 0f0h, 0f0h, 0f0h, 0f0h, 0f0h, 0f0h, 0f0h, 0f0h
+
+ org 3000h
+ db 03ch, 055h, 055h, 0ffh, 0aah, 0aah, 0ffh, 0aah
+ db 0c5h, 0c5h, 0c5h, 0c4h, 0c5h, 0c5h, 0c5h, 02fh
+ db 0e3h, 0c5h
+
+; org 4000h
+; db 0a0h, 0b0h, 00ch, 00dh
+
+; org 4100h
+; db 0e0h, 0f0h, 003h, 005h
+
+ org 078cbh
+ db 02eh, 0c0h
+
+ org 0bc9eh
+ db 0f0h, 080h
+
+ org 0ca02h
+ db 01fh, 00h
+
+ org 0fa00h
+ dw 09900h, 08a00h, 07210h, 0a600h
+ dw 09b00h, 0b110h, 02401h, 01f01h
+ dw 00111h, 07702h, 08812h, 07303h
+ dw 06613h
+ end
Index: tags/ez80-instructions/asm/alu_opsd.s
===================================================================
--- tags/ez80-instructions/asm/alu_opsd.s (nonexistent)
+++ tags/ez80-instructions/asm/alu_opsd.s (revision 9)
@@ -0,0 +1,187 @@
+;**********************************************************************************
+;* *
+;* alu_ops compare data *
+;* *
+;**********************************************************************************
+ org 01008h
+ db 0ceh, 0b3h, 0cfh, 033h, 0ceh, 033h, 033h, 0cdh
+
+ org 02008h
+ db 0e1h, 078h, 0e0h, 0f8h, 0e0h, 0f8h, 078h, 0e1h
+
+ org 02da8h
+ dw 0ffffh, 0ffffh, 0ffffh, 03872h ;2da8h
+ dw 00000h, 00000h, 0ffffh, 0ffffh ;2db0h
+
+ org 03008h
+ db 08bh, 0e2h, 08bh, 0e2h, 08ah, 0e2h, 062h, 0f7h, 02eh, 08bh
+
+; org 04000h
+; db 0a1h, 0b4h, 01ch, 04dh
+
+; org 04100h
+; db 0e2h, 0f8h, 023h, 085h
+
+ org 078cbh
+ db 02fh, 0bfh
+
+ org 0bc9eh
+ db 0f1h, 07fh
+
+ org 0ca02h
+ db 020h, 0ffh
+
+ org 0fac8h
+ dw 06304h, 06200h, 03872h, 00ff0h ;fac8h
+ dw 03872h, 03f01h, 000ffh, 0fe01h ;fad0h
+ dw 00000h, 0ff01h, 0fe01h, 00000h ;fad8h
+ dw 0ff01h, 0ffffh, 00000h, 00057h ;fae0h
+ dw 01303h, 08296h, 07706h, 06701h ;fae8h
+ dw 08591h, 08485h, 01705h, 00111h ;faf0h
+ dw 00605h, 07804h, 09094h, 09984h ;faf8h
+
+; org 0fb76h
+; dw 0234dh
+; dw 0f81ch, 0e2b4h, 08501h, 0a140h ;fb78h
+
+ org 0fb90h
+ dw 06030h, 0aaaah, 0dedeh, 0bcbch ;fb90h
+ dw 0a382h, 0fc93h, 07a06h, 04a06h ;fb98h
+ dw 0a282h, 0fc93h, 07a06h, 04a06h ;fba0h
+ dw 06012h, 06097h, 06002h, 06042h ;fba8h
+ dw 0ad80h, 00400h, 09a84h, 0ca84h ;fbb0h
+ dw 0af84h, 0ae80h, 0ba80h, 0ea80h ;fbb8h
+ dw 00101h, 00101h, 0aa00h, 0aa01h ;fbc0h
+ dw 0aa00h, 0aa01h, 0aa51h, 0aa51h ;fbc8h
+ dw 0aa50h, 0aa50h, 0ffffh, 0ffffh ;fbd0h
+ dw 0aa92h, 0aa42h, 0aa90h, 0aa43h ;fbd8h
+ dw 0aa93h, 0aa42h, 0aa92h, 0aa43h ;fbe0h
+ dw 00210h, 0aa94h, 02010h, 02010h ;fbe8h
+ dw 0b190h, 05815h, 0da80h, 00a01h ;fbf0h
+ dw 0b290h, 05815h, 0db80h, 00a01h ;fbf8h
+
+ org 0fc00h
+ dw 03544h, 06a44h, 0d444h, 0a845h ;fc00h
+ dw 05145h, 0a344h, 05145h, 0a845h ;fc08h
+ dw 0d444h, 06a44h, 03544h, 06a44h ;fc10h
+ dw 0d445h, 0a945h, 05344h, 0a644h ;fc18h
+ dw 05345h, 0a945h, 0d444h, 06a44h ;fc20h
+ dw 00004h, 00080h, 00081h, 00080h ;fc28h
+ dw 00081h, 00004h, 00085h, 00005h ;fc30h
+ dw 00005h, 00080h, 00005h, 00084h ;fc38h
+ dw 00081h, 00080h, 00001h, 00085h ;fc40h
+ dw 00081h, 00084h, 00085h, 00085h ;fc48h
+ dw 00085h, 00004h, 01078h, 010f0h ;fc50h
+ dw 04d65h, 04dcbh, 02c33h, 02c67h ;fc58h
+ dw 00080h, 010f8h, 010f0h, 0cde5h ;fc60h
+ dw 0cdcbh, 02c33h, 02c67h, 00081h ;fc68h
+ dw 042e0h, 042f0h, 03496h, 034cbh ;fc70h
+ dw 0b0ceh, 0b067h, 00080h, 090f8h ;fc78h
+ dw 090f0h, 0cd65h, 0cdcbh, 0ac33h ;fc80h
+ dw 0ac67h, 00081h, 043e0h, 043f0h ;fc88h
+ dw 03497h, 034cbh, 0b0ceh, 0b067h ;fc90h
+ dw 00004h, 09078h, 090f0h, 04de5h ;fc98h
+ dw 04dcbh, 02cb3h, 02c67h, 00085h ;fca0h
+ dw 042e1h, 042f0h, 03597h, 035cbh ;fca8h
+ dw 0b0ceh, 0b067h, 00000h, 00000h ;fcb0h
+ dw 00000h, 02105h, 04300h, 00605h ;fcb8h
+ dw 00d00h, 01a01h, 0e185h, 0c384h ;fcc0h
+ dw 00605h, 00d00h, 01a01h, 0a084h ;fcc8h
+ dw 05005h, 0a881h, 0d484h, 06a04h ;fcd0h
+ dw 03504h, 06a04h, 0d484h, 0a881h ;fcd8h
+ dw 05101h, 0a384h, 05101h, 0a881h ;fce0h
+ dw 0d484h, 06a04h, 03504h, 06a04h ;fce8h
+ dw 0d485h, 0a985h, 05304h, 0a684h ;fcf0h
+ dw 05305h, 0a985h, 0d484h, 06a04h ;fcf8h
+
+ org 0fd24h
+ dw 0bf85h, 0bf80h ;fd24h
+ dw 0bf85h, 0bf85h, 043e1h, 043f0h ;fd28h
+ dw 03597h, 035cbh, 0b1cfh, 0b167h ;fd30h
+ dw 021f0h, 09acbh, 05867h, 0bf80h ;fd38h
+ dw 05f05h, 0af85h, 0d784h, 06b00h ;fd40h
+
+ org 0fd48h
+ dw 0ffffh, 0ffffh, 00042h, 0ff93h ;fd48h
+ dw 00042h, 0c181h, 0e080h, 0e084h ;fd50h
+ dw 07010h, 03842h, 03810h, 00044h ;fd58h
+ dw 0c083h, 00e02h, 00042h, 05e16h ;fd60h
+ dw 0b483h, 05506h, 0a282h, 0fc93h ;fd68h
+ dw 07a06h, 04906h, 09884h, 01110h ;fd70h
+ dw 0a991h, 0f680h, 0a091h, 0ff80h ;fd78h
+ dw 0b290h, 05815h, 0db80h, 00b01h ;fd80h
+ dw 02083h, 00f02h, 0aa42h, 0b416h ;fd88h
+ dw 0aa83h, 0aa06h, 0aa82h, 0aa93h ;fd90h
+ dw 0aa06h, 0aa06h, 0c083h, 00e02h ;fd98h
+ dw 00042h, 05f16h, 0b483h, 05506h ;fda0h
+ dw 0a382h, 0fc93h, 07a06h, 04a06h ;fda8h
+ dw 09884h, 01010h, 0a991h, 0f580h ;fdb0h
+ dw 0a091h, 0ff80h, 0b190h, 05815h ;fdb8h
+ dw 0da80h, 00a01h, 07804h, 08f80h ;fdc0h
+ dw 0df80h, 05504h, 00044h, 0ff84h ;fdc8h
+ dw 0af84h, 0ae80h, 0ba80h, 0ea80h ;fdd0h
+ dw 00100h, 05d00h, 0ff84h, 0df80h ;fdd8h
+ dw 02000h, 00044h, 0ad80h, 00400h ;fde0h
+ dw 09a84h, 0ca84h, 08294h, 00054h ;fde8h
+ dw 02814h, 00a14h, 08a90h, 00054h ;fdf0h
+ dw 00210h, 00810h, 02010h, 08090h ;fdf8h
+
+ org 0fe30h
+ dw 0ffffh, 0ffffh, 01234h, 05256h ;fe30h
+ dw 00093h, 00000h, 01234h, 05256h ;fe38h
+ dw 00042h, 083afh, 01234h, 05256h ;fe40h
+ dw 00093h, 081fah, 01234h, 05256h ;fe48h
+ dw 00093h, 0804ch, 01234h, 05256h ;fe50h
+ dw 00082h, 09281h, 01234h, 05256h ;fe58h
+ dw 00082h, 0a4b5h, 01234h, 05256h ;fe60h
+ dw 00082h, 0f70ch, 01234h, 05256h ;fe68h
+ dw 00083h, 04962h, 01234h, 05256h ;fe70h
+ dw 00011h, 04ae7h, 01234h, 05256h ;fe78h
+ dw 00011h, 04c65h, 01234h, 05256h ;fe80h
+ dw 00000h, 02632h, 01234h, 05256h ;fe88h
+ dw 00005h, 09319h, 01234h, 05256h ;fe90h
+ dw 00080h, 080e4h, 01234h, 05256h ;fe98h
+ dw 00094h, 06eb0h, 01234h, 05256h ;fea0h
+ dw 00000h, 01c59h, 01234h, 05256h ;fea8h
+ dw 00001h, 0bca0h, 078bch, 0ca03h ;feb0h
+ dw 01234h, 05256h, 07f16h, 07f92h ;feb8h
+ dw 07f10h, 0bca0h, 078bch, 0ca02h ;fec0h
+ dw 01234h, 05256h, 07f02h, 0ca05h ;fec8h
+ dw 01236h, 05257h, 07f82h, 0cb05h ;fed0h
+ dw 01436h, 05557h, 07f00h, 0cb04h ;fed8h
+ dw 01434h, 05554h, 07f80h, 0bca0h ;fee0h
+ dw 078bch, 0c804h, 01234h, 05454h ;fee8h
+ dw 07f16h, 00f12h, 0fe82h, 0ff92h ;fef0h
+ dw 00050h, 08094h, 01010h, 00100h ;fef8h
+
+ org 0ff10h
+ dw 0ffffh, 0ffffh, 0ffffh, 0bca0h ;ff10h
+ dw 078bch, 0c804h, 01234h, 05454h ;ff18h
+ dw 00055h, 0de50h, 078bch, 0c804h ;ff20h
+ dw 01234h, 05454h, 00055h, 0df22h ;ff28h
+ dw 078bch, 0c804h, 01234h, 05454h ;ff30h
+ dw 00044h, 0cceeh, 078bch, 0c804h ;ff38h
+ dw 01234h, 05454h, 00044h, 0789ah ;ff40h
+ dw 078bch, 0c804h, 01234h, 05454h ;ff48h
+ dw 00055h, 0789ah, 0bc5eh, 0c804h ;ff50h
+ dw 01234h, 05454h, 00055h, 0789ah ;ff58h
+ dw 0bd00h, 0c804h, 01234h, 05454h ;ff60h
+ dw 00044h, 0789ah, 0aacch, 0c804h ;ff68h
+ dw 01234h, 05454h, 00044h, 0789ah ;ff70h
+ dw 05678h, 0c804h, 01234h, 05454h ;ff78h
+ dw 00055h, 0c882h, 01234h, 05454h ;ff80h
+ dw 00044h, 06441h, 01234h, 05454h ;ff88h
+ dw 00044h, 0520dh, 01234h, 05454h ;ff90h
+ dw 00055h, 00000h, 00000h, 00001h ;ff98h
+ dw 00044h ;ffa0h
+
+ org 0ffc8h
+ dw 0ffffh, 0ffffh, 0789ah, 05678h ;ffc8h
+ dw 07899h, 05678h, 07899h, 0ffffh ;ffd0h
+ dw 07899h, 05677h, 00000h, 0ffffh ;ffd8h
+ dw 00000h, 0ffffh, 00001h, 00000h ;ffe0h
+ dw 0ffffh, 08087h, 00213h, 0fe93h ;ffe8h
+ dw 0ff93h, 00042h, 08057h, 07f57h ;fff0h
+ dw 00045h, 00045h, 00054h, 00045h ;fff8h
+
+ end
Index: tags/ez80-instructions/asm/bit_ops.s
===================================================================
--- tags/ez80-instructions/asm/bit_ops.s (nonexistent)
+++ tags/ez80-instructions/asm/bit_ops.s (revision 9)
@@ -0,0 +1,731 @@
+;**********************************************************************************
+;* *
+;* checks all bit manipulation instructions *
+;* *
+;**********************************************************************************
+ aseg
+
+ org 00h
+ jp 100h
+
+ org 0c0h ;pattern finish location
+ nop
+ jr 0c0h
+
+ org 0100h
+ ld sp, 0000h ;point sp at result table
+ ld a, 0ffh ;initialize the main registers
+ xor a ;initialize flags
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ ld ix, 07ffeh
+ ld iy, 07201h
+ push af ;0044h @ fffeh
+ push bc ;0000h @ fffch
+ push de ;0000h @ fffah
+ push hl ;0000h @ fff8h
+ push ix ;7ffeh @ fff6h
+ push iy ;7201h @ fff4h
+ set 0, a
+ set 1, b
+ set 2, c
+ set 3, d
+ set 4, e
+ set 5, h
+ set 6, l
+ push af ;0144h @ fff2h
+ push bc ;0204h @ fff0h
+ push de ;0810h @ ffeeh
+ push hl ;2040h @ ffech
+ xor a
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ set 0, b
+ set 1, c
+ set 2, d
+ set 3, e
+ set 4, h
+ set 5, l
+ set 6, a
+ push af ;4044h @ ffeah
+ push bc ;0102h @ ffe8h
+ push de ;0408h @ ffe6h
+ push hl ;1020h @ ffe4h
+ xor a
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ set 0, c
+ set 1, d
+ set 2, e
+ set 3, h
+ set 4, l
+ set 5, a
+ set 6, b
+ push af ;2044h @ ffe2h
+ push bc ;4001h @ ffe0h
+ push de ;0204h @ ffdeh
+ push hl ;0810h @ ffdch
+ xor a
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ set 0, d
+ set 1, e
+ set 2, h
+ set 3, l
+ set 4, a
+ set 5, b
+ set 6, c
+ push af ;1044h @ ffdah
+ push bc ;2040h @ ffd8h
+ push de ;0102h @ ffd6h
+ push hl ;0408h @ ffd4h
+ xor a
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ set 0, e
+ set 1, h
+ set 2, l
+ set 3, a
+ set 4, b
+ set 5, c
+ set 6, d
+ push af ;0844h @ ffd2h
+ push bc ;1020h @ ffd0h
+ push de ;4001h @ ffceh
+ push hl ;0204h @ ffcch
+ xor a
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ set 0, h
+ set 1, l
+ set 2, a
+ set 3, b
+ set 4, c
+ set 5, d
+ set 6, e
+ push af ;0444h @ ffcah
+ push bc ;0810h @ ffc8h
+ push de ;2040h @ ffc6h
+ push hl ;0102h @ ffc4h
+ xor a
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ set 0, l
+ set 1, a
+ set 2, b
+ set 3, c
+ set 4, d
+ set 5, e
+ set 6, h
+ push af ;0244h @ ffc2h
+ push bc ;0408h @ ffc0h
+ push de ;1020h @ ffbeh
+ push hl ;4001h @ ffbch
+ xor a
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld hl, 7000h
+ set 0, (hl) ; 00h @ 7000h read
+ ; 01h @ 7000h write
+ set 7, a
+ push af ;8044h @ ffbah
+ push bc ;0000h @ ffb8h
+ push de ;0000h @ ffb6h
+ push hl ;7000h @ ffb4h
+ ld a, b
+ inc hl
+ set 1, (hl) ; 00h @ 7001h read
+ ; 02h @ 7001h write
+ set 7, b
+ push af ;0044h @ ffb2h
+ push bc ;8000h @ ffb0h
+ push de ;0000h @ ffaeh
+ push hl ;7001h @ ffach
+ ld b, a
+ inc hl
+ set 2, (hl) ; 00h @ 7002h read
+ ; 04h @ 7002h write
+ set 7, c
+ push af ;0044h @ ffaah
+ push bc ;0080h @ ffa8h
+ push de ;0000h @ ffa6h
+ push hl ;7002h @ ffa4h
+ ld c, a
+ inc hl
+ set 3, (hl) ; 00h @ 7003h read
+ ; 08h @ 7003h write
+ set 7, d
+ push af ;0044h @ ffa2h
+ push bc ;0000h @ ffa0h
+ push de ;8000h @ ff9eh
+ push hl ;7003h @ ff9ch
+ ld d, a
+ inc hl
+ set 4, (hl) ; 00h @ 7004h read
+ ; 10h @ 7004h write
+ set 7, e
+ push af ;0044h @ ff9ah
+ push bc ;0000h @ ff98h
+ push de ;0080h @ ff96h
+ push hl ;7004h @ ff94h
+ ld e, a
+ inc hl
+ set 5, (hl) ; 00h @ 7005h read
+ ; 20h @ 7005h write
+ set 7, h
+ push af ;0044h @ ff92h
+ push bc ;0000h @ ff90h
+ push de ;0000h @ ff8eh
+ push hl ;f005h @ ff8ch
+ ld hl, 7006h
+ set 6, (hl) ; 00h @ 7006h read
+ ; 40h @ 7006h write
+ set 7, l
+ push af ;0044h @ ff8ah
+ push bc ;0000h @ ff88h
+ push de ;0000h @ ff86h
+ push hl ;7086h @ ff84h
+ ld hl, 7007h
+ set 7, (hl) ; 00h @ 7007h read
+ ; 80h @ 7007h write
+ push af ;0044h @ ff82h
+ push bc ;0000h @ ff80h
+ push de ;0000h @ ff7eh
+ push hl ;7007h @ ff7ch
+ set 0, (ix+7h) ; 00h @ 8005h read
+ ; 01h @ 8005h write
+ set 1, (ix+6h) ; 00h @ 8004h read
+ ; 02h @ 8004h write
+ set 2, (ix+5h) ; 00h @ 8003h read
+ ; 04h @ 8003h write
+ set 3, (ix+4h) ; 00h @ 8002h read
+ ; 08h @ 8002h write
+ set 4, (ix+3h) ; 00h @ 8001h read
+ ; 10h @ 8001h write
+ set 5, (ix+2h) ; 00h @ 8000h read
+ ; 20h @ 8000h write
+ set 6, (ix+1h) ; 00h @ 7fffh read
+ ; 40h @ 7fffh write
+ set 7, (ix+0h) ; 00h @ 7ffeh read
+ ; 80h @ 7ffeh write
+ set 0, (iy+0ffh) ; 00h @ 7200h read
+ ; 01h @ 7200h write
+ set 1, (iy+0feh) ; 00h @ 71ffh read
+ ; 02h @ 71ffh write
+ set 2, (iy+0fdh) ; 00h @ 71feh read
+ ; 04h @ 71feh write
+ set 3, (iy+0fch) ; 00h @ 71fdh read
+ ; 08h @ 71fdh write
+ set 4, (iy+0fbh) ; 00h @ 71fch read
+ ; 10h @ 71fch write
+ set 5, (iy+0fah) ; 00h @ 71fbh read
+ ; 20h @ 71fbh write
+ set 6, (iy+0f9h) ; 00h @ 71fah read
+ ; 40h @ 71fah write
+ set 7, (iy+0f8h) ; 00h @ 71f9h read
+ ; 80h @ 71f9h write
+ ld a, 0ffh ;initialize the main registers
+ or a ;initialize flags
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ ld ix, 7401h
+ ld iy, 70feh
+ push af ;ff84h @ ff7ah
+ push bc ;ffffh @ ff78h
+ push de ;ffffh @ ff76h
+ push hl ;ffffh @ ff74h
+ push ix ;7401h @ ff72h
+ push iy ;70feh @ ff70h
+ res 0, a
+ res 1, b
+ res 2, c
+ res 3, d
+ res 4, e
+ res 5, h
+ res 6, l
+ push af ;fe84h @ ff6eh
+ push bc ;fdfbh @ ff6ch
+ push de ;f7efh @ ff6ah
+ push hl ;dfbfh @ ff68h
+ ld a, 0ffh
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ res 0, b
+ res 1, c
+ res 2, d
+ res 3, e
+ res 4, h
+ res 5, l
+ res 6, a
+ push af ;bf84h @ ff66h
+ push bc ;fefdh @ ff64h
+ push de ;fbf7h @ ff62h
+ push hl ;efdfh @ ff60h
+ ld a, 0ffh
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ res 0, c
+ res 1, d
+ res 2, e
+ res 3, h
+ res 4, l
+ res 5, a
+ res 6, b
+ push af ;df84h @ ff5eh
+ push bc ;bffeh @ ff5ch
+ push de ;fdfbh @ ff5ah
+ push hl ;f7efh @ ff58h
+ ld a, 0ffh
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ res 0, d
+ res 1, e
+ res 2, h
+ res 3, l
+ res 4, a
+ res 5, b
+ res 6, c
+ push af ;ef84h @ ff56h
+ push bc ;dfbfh @ ff54h
+ push de ;fefdh @ ff52h
+ push hl ;fbf7h @ ff50h
+ ld a, 0ffh
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ res 0, e
+ res 1, h
+ res 2, l
+ res 3, a
+ res 4, b
+ res 5, c
+ res 6, d
+ push af ;f784h @ ff4eh
+ push bc ;efdfh @ ff4ch
+ push de ;bffeh @ ff4ah
+ push hl ;fdfbh @ ff48h
+ ld a, 0ffh
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ res 0, h
+ res 1, l
+ res 2, a
+ res 3, b
+ res 4, c
+ res 5, d
+ res 6, e
+ push af ;fb84h @ ff46h
+ push bc ;f7efh @ ff44h
+ push de ;dfbfh @ ff42h
+ push hl ;fefdh @ ff40h
+ ld a, 0ffh
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ res 0, l
+ res 1, a
+ res 2, b
+ res 3, c
+ res 4, d
+ res 5, e
+ res 6, h
+ push af ;fd84h @ ff3eh
+ push bc ;fbf7h @ ff3ch
+ push de ;efdfh @ ff3ah
+ push hl ;bffeh @ ff38h
+ ld a, 0ffh
+ ld b, a
+ ld c, a
+ ld d, a
+ ld e, a
+ ld hl, 08480h
+ res 0, (hl) ; ffh @ 8480h read
+ ; feh @ 8480h write
+ res 7, a
+ push af ;7f84h @ ff36h
+ push bc ;ffffh @ ff34h
+ push de ;ffffh @ ff32h
+ push hl ;8480h @ ff30h
+ ld a, b
+ inc hl
+ res 1, (hl) ; ffh @ 8481h read
+ ; fdh @ 8481h write
+ res 7, b
+ push af ;ff84h @ ff2eh
+ push bc ;7fffh @ ff2ch
+ push de ;ffffh @ ff2ah
+ push hl ;8481h @ ff28h
+ ld b, a
+ inc hl
+ res 2, (hl) ; ffh @ 8482h read
+ ; fbh @ 8482h write
+ res 7, c
+ push af ;ff84h @ ff26h
+ push bc ;ff7fh @ ff24h
+ push de ;ffffh @ ff22h
+ push hl ;8482h @ ff20h
+ ld c, a
+ inc hl
+ res 3, (hl) ; ffh @ 8483h read
+ ; f7h @ 8483h write
+ res 7, d
+ push af ;ff84h @ ff1eh
+ push bc ;ffffh @ ff1ch
+ push de ;7fffh @ ff1ah
+ push hl ;8483h @ ff18h
+ ld d, a
+ inc hl
+ res 4, (hl) ; ffh @ 8484h read
+ ; efh @ 8484h write
+ res 7, e
+ push af ;ff84h @ ff16h
+ push bc ;ffffh @ ff14h
+ push de ;ff7fh @ ff12h
+ push hl ;8484h @ ff10h
+ ld e, a
+ inc hl
+ res 5, (hl) ; ffh @ 8485h read
+ ; dfh @ 8485h write
+ res 7, h
+ push af ;ff84h @ ff0eh
+ push bc ;ffffh @ ff0ch
+ push de ;ffffh @ ff0ah
+ push hl ;0485h @ ff08h
+ ld hl, 8486h
+ res 6, (hl) ; ffh @ 8486h read
+ ; bfh @ 8486h write
+ res 7, l
+ push af ;ff84h @ ff06h
+ push bc ;ffffh @ ff04h
+ push de ;ffffh @ ff02h
+ push hl ;8406h @ ff00h
+ ld hl, 8487h
+ res 7, (hl) ; ffh @ 8487h read
+ ; 7fh @ 8487h write
+ push af ;ff84h @ fefeh
+ push bc ;ffffh @ fefch
+ push de ;ffffh @ fefah
+ push hl ;8487h @ fef8h
+ res 0, (ix+00h) ; ffh @ 7401h read
+ ; feh @ 7401h write
+ res 1, (ix+0ffh) ; ffh @ 7400h read
+ ; fdh @ 7400h write
+ res 2, (ix+0feh) ; ffh @ 73ffh read
+ ; fbh @ 73ffh write
+ res 3, (ix+0fdh) ; ffh @ 73feh read
+ ; f7h @ 73feh write
+ res 4, (ix+0fch) ; ffh @ 73fdh read
+ ; efh @ 73fdh write
+ res 5, (ix+0fbh) ; ffh @ 73fch read
+ ; dfh @ 73fch write
+ res 6, (ix+0fah) ; ffh @ 73fbh read
+ ; bfh @ 73fbh write
+ res 7, (ix+0f9h) ; ffh @ 73fah read
+ ; 7fh @ 73fah write
+ res 0, (iy+2h) ; ffh @ 7100h read
+ ; feh @ 7100h write
+ res 1, (iy+3h) ; ffh @ 7101h read
+ ; fdh @ 7101h write
+ res 2, (iy+4h) ; ffh @ 7102h read
+ ; fbh @ 7102h write
+ res 3, (iy+5h) ; ffh @ 7103h read
+ ; f7h @ 7103h write
+ res 4, (iy+6h) ; ffh @ 7104h read
+ ; efh @ 7104h write
+ res 5, (iy+7h) ; ffh @ 7105h read
+ ; dfh @ 7105h write
+ res 6, (iy+8h) ; ffh @ 7106h read
+ ; bfh @ 7106h write
+ res 7, (iy+9h) ; ffh @ 7107h read
+ ; 7fh @ 7107h write
+ xor a ;clear accumulator
+ ld b, a ;clear register file
+ ld c, a
+ ld d, a
+ ld e, a
+ ld h, a
+ ld l, a
+ ld ix, 0a000h
+ ld iy, 09000h
+ ld sp, 0c000h
+ pop af ;7fffh @ c000h
+ ld sp, 0c000h
+ bit 7, a
+ push af ;7ffdh @ bffeh
+ ld sp, 0c002h
+ pop af ;40ffh @ c002h
+ ld sp, 0bffeh
+ bit 6, a
+ push af ;40bdh @ bffch
+ ld sp, 0c004h
+ pop af ;df00h @ c004h
+ ld sp, 0bffch
+ bit 5, a
+ push af ;df50h @ bffah
+ ld sp, 0c006h
+ pop af ;1000h @ c006h
+ ld sp, 0bffah
+ bit 4, a
+ push af ;1010h @ bff8h
+ ld a, 0f7h
+ bit 3, a
+ push af ;f750f @ bff6h
+ ld a, 04h
+ bit 2, a
+ push af ;0410h @ bff4h
+ ld a, 0fdh
+ bit 1, a
+ push af ;fd50h @ bff2h
+ ld a, 01h
+ bit 0, a
+ push af ;0110h @ bff0h
+ xor a
+ ld bc, 0f0cch
+ ld de, 0aa0fh
+ ld hl, 3355h
+ bit 7, b
+ push af ;0014h @ bfeeh
+ bit 6, b
+ push af ;0014h @ bfech
+ bit 5, b
+ push af ;0014h @ bfeah
+ bit 4, b
+ push af ;0014h @ bfe8h
+ bit 3, b
+ push af ;0054h @ bfe6h
+ bit 2, b
+ push af ;0054h @ bfe4h
+ bit 1, b
+ push af ;0054h @ bfe2h
+ bit 0, b
+ push af ;0054h @ bfe0h
+ bit 7, c
+ push af ;0014h @ bfdeh
+ bit 6, c
+ push af ;0014h @ bfdch
+ bit 5, c
+ push af ;0054h @ bfdah
+ bit 4, c
+ push af ;0054h @ bfd8h
+ bit 3, c
+ push af ;0014h @ bfd6h
+ bit 2, c
+ push af ;0014h @ bfd4h
+ bit 1, c
+ push af ;0054h @ bfd2h
+ bit 0, c
+ push af ;0054h @ bfd0h
+ bit 7, d
+ push af ;0014h @ bfceh
+ bit 6, d
+ push af ;0054h @ bfcch
+ bit 5, d
+ push af ;0014h @ bfcah
+ bit 4, d
+ push af ;0054h @ bfc8h
+ bit 3, d
+ push af ;0014h @ bfc6h
+ bit 2, d
+ push af ;0054h @ bfc4h
+ bit 1, d
+ push af ;0014h @ bfc2h
+ bit 0, d
+ push af ;0054h @ bfc0h
+ bit 7, e
+ push af ;0054h @ bfbeh
+ bit 6, e
+ push af ;0054h @ bfbch
+ bit 5, e
+ push af ;0054h @ bfbah
+ bit 4, e
+ push af ;0054h @ bfb8h
+ bit 3, e
+ push af ;0014h @ bfb6h
+ bit 2, e
+ push af ;0014h @ bfb4h
+ bit 1, e
+ push af ;0014h @ bfb2h
+ bit 0, e
+ push af ;0014h @ bfb0h
+ bit 7, h
+ push af ;0054h @ bfaeh
+ bit 6, h
+ push af ;0054h @ bfach
+ bit 5, h
+ push af ;0014h @ bfaah
+ bit 4, h
+ push af ;0014h @ bfa8h
+ bit 3, h
+ push af ;0054h @ bfa6h
+ bit 2, h
+ push af ;0054h @ bfa4h
+ bit 1, h
+ push af ;0014h @ bfa2h
+ bit 0, h
+ push af ;0014h @ bfa0h
+ bit 7, l
+ push af ;0054h @ bf9eh
+ bit 6, l
+ push af ;0014h @ bf9ch
+ bit 5, l
+ push af ;0054h @ bf9ah
+ bit 4, l
+ push af ;0014h @ bf98h
+ bit 3, l
+ push af ;0054h @ bf96h
+ bit 2, l
+ push af ;0014h @ bf94h
+ bit 1, l
+ push af ;0054h @ bf92h
+ bit 0, l
+ push af ;0014h @ bf90h
+ ld hl, 8500h
+ bit 7, (hl) ; 80h @ 8500h
+ push af ;0014h @ bf8eh
+ inc hl
+ bit 6, (hl) ; bfh @ 8501h
+ push af ;0054h @ bf8ch
+ inc hl
+ bit 5, (hl) ; 20h @ 8502h
+ push af ;0014h @ bf8ah
+ inc hl
+ bit 4, (hl) ; 10h @ 8503h
+ push af ;0014h @ bf88h
+ inc hl
+ bit 3, (hl) ; f7h @ 8504h
+ push af ;0054h @ bf86h
+ inc hl
+ bit 2, (hl) ; 40h @ 8505h
+ push af ;0054h @ bf84h
+ inc hl
+ bit 1, (hl) ; fdh @ 8506h
+ push af ;0054h @ bf82h
+ inc hl
+ bit 0, (hl) ; feh @ 8507h
+ push af ;0054h @ bf80h
+ ld ix, 8502h
+ ld iy, 8564h
+ bit 7, (ix+3eh) ; 00h @ 8540h
+ push af ;0054h @ bf7eh
+ bit 6, (ix+3fh) ; 00h @ 8541h
+ push af ;0054h @ bf7ch
+ bit 5, (ix+40h) ; ffh @ 8542h
+ push af ;0014h @ bf7ah
+ bit 4, (ix+41h) ; ffh @ 8543h
+ push af ;0014h @ bf78h
+ bit 3, (ix+42h) ; ffh @ 8544h
+ push af ;0014h @ bf76h
+ bit 2, (ix+43h) ; ffh @ 8545h
+ push af ;0014h @ bf74h
+ bit 1, (ix+44h) ; 00h @ 8546h
+ push af ;0054h @ bf72h
+ bit 0, (ix+45h) ; 00h @ 8547h
+ push af ;0054h @ bf70h
+ bit 7, (iy+1ch) ; 00h @ 8580h
+ push af ;0054h @ bf6eh
+ bit 6, (iy+1dh) ; ffh @ 8581h
+ push af ;0014h @ bf6ch
+ bit 5, (iy+1eh) ; 00h @ 8582h
+ push af ;0054h @ bf6ah
+ bit 4, (iy+1fh) ; ffh @ 8583h
+ push af ;0014h @ bf68h
+ bit 3, (iy+20h) ; ffh @ 8584h
+ push af ;0014h @ bf66h
+ bit 2, (iy+21h) ; 00h @ 8585h
+ push af ;0054h @ bf64h
+ bit 1, (iy+22h) ; ffh @ 8586h
+ push af ;0014h @ bf62h
+ bit 0, (iy+23h) ; 00h @ 8587h
+ push af ;0054h @ bf60h
+
+ ld hl, 0100h ;init hl for next pattern
+ jp 0c0h
+
+ org 07000h ;data for set (hl)
+ db 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
+
+ org 07100h ;data for res (iy+d)
+ db 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh
+
+ org 071f9h ;data for set (iy+d)
+ db 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
+
+ org 073fah ;data for res (ix+d)
+ db 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh
+
+ org 07ffeh ;data for set (ix+d)
+ db 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
+
+ org 08480h ;data for res (hl)
+ db 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh
+
+ org 08500h ;data for bit (hl)
+ db 80h, 0bfh, 20h, 10h, 0f7h, 40h, 0fdh, 0feh
+
+ org 08540h ;data for bit (ix+d)
+ db 00h, 00h, 0ffh, 0ffh, 0ffh, 0ffh, 00h, 00h
+
+ org 08580h ;data for bit (iy+d)
+ db 00h, 0ffh, 00h, 0ffh, 0ffh, 00h, 0ffh, 00h
+
+ org 0c000h ;af data for bit
+ dw 07fffh
+ dw 040ffh
+ dw 0df00h
+ dw 01000h
Index: tags/ez80-instructions/asm/setup_hl.s
===================================================================
--- tags/ez80-instructions/asm/setup_hl.s (nonexistent)
+++ tags/ez80-instructions/asm/setup_hl.s (revision 9)
@@ -0,0 +1,15 @@
+;**********************************************************************************
+;* *
+;* set up hl register for trap patterns *
+;* *
+;**********************************************************************************
+ org 00h
+ jp 100h
+
+ org 0c0h ;pattern finish location
+ nop
+ jr 0c0h
+
+ org 0100h
+ ld hl, 0100h ;init hl for next pattern
+ jp 0c0h
Index: tags/ez80-instructions/asm/bit_opsd.s
===================================================================
--- tags/ez80-instructions/asm/bit_opsd.s (nonexistent)
+++ tags/ez80-instructions/asm/bit_opsd.s (revision 9)
@@ -0,0 +1,82 @@
+;**********************************************************************************
+;* *
+;* bit_ops compare data *
+;* *
+;**********************************************************************************
+ org 07000h
+ db 001h, 002h, 004h, 008h, 010h, 020h, 040h, 080h
+
+ org 07100h
+ db 0feh, 0fdh, 0fbh, 0f7h, 0efh, 0dfh, 0bfh, 07fh
+
+ org 71f8h
+ db 001h, 080h, 040h, 020h, 010h, 008h, 004h, 002h
+ db 001h, 000h, 000h, 000h, 000h, 000h, 000h, 000h
+
+ org 073fah
+ db 07fh, 0bfh, 0dfh, 0efh, 0f7h, 0fbh, 0fdh, 0feh
+
+ org 7ff8h
+ db 000h, 000h, 000h, 000h, 000h, 000h, 080h, 040h
+ db 020h, 010h, 008h, 004h, 002h, 001h, 000h, 000h
+
+ org 08480h
+ db 0feh, 0fdh, 0fbh, 0f7h, 0efh, 0dfh, 0bfh, 07fh
+
+ org 0bf60h
+ dw 00054h, 00014h, 00054h, 00014h ;bf60h
+ dw 00014h, 00054h, 00014h, 00054h ;bf68h
+ dw 00054h, 00054h, 00014h, 00014h ;bf70h
+ dw 00014h, 00014h, 00054h, 00054h ;bf78h
+ dw 00054h, 00054h, 00054h, 00054h ;bf80h
+ dw 00014h, 00014h, 00054h, 00014h ;bf88h
+ dw 00014h, 00054h, 00014h, 00054h ;bf90h
+ dw 00014h, 00054h, 00014h, 00054h ;bf98h
+ dw 00014h, 00014h, 00054h, 00054h ;bfa0h
+ dw 00014h, 00014h, 00054h, 00054h ;bfa8h
+ dw 00014h, 00014h, 00014h, 00014h ;bfb0h
+ dw 00054h, 00054h, 00054h, 00054h ;bfb8h
+ dw 00054h, 00014h, 00054h, 00014h ;bfc0h
+ dw 00054h, 00014h, 00054h, 00014h ;bfc8h
+ dw 00054h, 00054h, 00014h, 00014h ;bfd0h
+ dw 00054h, 00054h, 00014h, 00014h ;bfd8h
+ dw 00054h, 00054h, 00054h, 00054h ;bfe0h
+ dw 00014h, 00014h, 00014h, 00014h ;bfe8h
+ dw 00110h, 0fd50h, 00410h, 0f750h ;bff0h
+ dw 01010h, 0df50h, 040bdh, 07ffdh ;bff8h
+
+ org 0fef8h
+ dw 08487h, 0ffffh, 0ffffh, 0ff84h ;fef8h
+ dw 08406h, 0ffffh, 0ffffh, 0ff84h ;ff00h
+ dw 00485h, 0ffffh, 0ffffh, 0ff84h ;ff08h
+ dw 08484h, 0ff7fh, 0ffffh, 0ff84h ;ff10h
+ dw 08483h, 07fffh, 0ffffh, 0ff84h ;ff18h
+ dw 08482h, 0ffffh, 0ff7fh, 0ff84h ;ff20h
+ dw 08481h, 0ffffh, 07fffh, 0ff84h ;ff28h
+ dw 08480h, 0ffffh, 0ffffh, 07f84h ;ff30h
+ dw 0bffeh, 0efdfh, 0fbf7h, 0fd84h ;ff38h
+ dw 0fefdh, 0dfbfh, 0f7efh, 0fb84h ;ff40h
+ dw 0fdfbh, 0bffeh, 0efdfh, 0f784h ;ff48h
+ dw 0fbf7h, 0fefdh, 0dfbfh, 0ef84h ;ff50h
+ dw 0f7efh, 0fdfbh, 0bffeh, 0df84h ;ff58h
+ dw 0efdfh, 0fbf7h, 0fefdh, 0bf84h ;ff60h
+ dw 0dfbfh, 0f7efh, 0fdfbh, 0fe84h ;ff68h
+ dw 070feh, 07401h, 0ffffh, 0ffffh ;ff70h
+ dw 0ffffh, 0ff84h, 07007h, 00000h ;ff78h
+ dw 00000h, 00044h, 07086h, 00000h ;ff80h
+ dw 00000h, 00044h, 0f005h, 00000h ;ff88h
+ dw 00000h, 00044h, 07004h, 00080h ;ff90h
+ dw 00000h, 00044h, 07003h, 08000h ;ff98h
+ dw 00000h, 00044h, 07002h, 00000h ;ffa0h
+ dw 00080h, 00044h, 07001h, 00000h ;ffa8h
+ dw 08000h, 00044h, 07000h, 00000h ;ffb0h
+ dw 00000h, 08044h, 04001h, 01020h ;ffb8h
+ dw 00408h, 00244h, 00102h, 02040h ;ffc0h
+ dw 00810h, 00444h, 00204h, 04001h ;ffc8h
+ dw 01020h, 00844h, 00408h, 00102h ;ffd0h
+ dw 02040h, 01044h, 00810h, 00204h ;ffd8h
+ dw 04001h, 02044h, 01020h, 00408h ;ffe0h
+ dw 00102h, 04044h, 02040h, 00810h ;ffe8h
+ dw 00204h, 00144h, 07201h, 07ffeh ;fff0h
+ dw 00000h, 00000h, 00000h, 00044h ;fff8h
+
Index: tags/ez80-instructions/asm/jmp_ops.s
===================================================================
--- tags/ez80-instructions/asm/jmp_ops.s (nonexistent)
+++ tags/ez80-instructions/asm/jmp_ops.s (revision 9)
@@ -0,0 +1,528 @@
+;**********************************************************************************
+;* *
+;* checks all jump, call, etc. instructions *
+;* *
+;**********************************************************************************
+ aseg
+
+ org 00h
+ jp (hl)
+
+ org 08h
+ push bc ;0004h @ fff4h
+ inc bc
+ jp (hl)
+
+ org 10h
+ push bc ;0006h @ ffeeh
+ inc bc
+ jp (hl)
+
+ org 18h
+ push bc ;0008h @ ffe8h
+ inc bc
+ jp (hl)
+
+ org 20h
+ push bc ;000ah @ ffe2h
+ inc bc
+ jp (hl)
+
+ org 28h
+ push bc ;000ch @ ffdch
+ inc bc
+ jp (hl)
+
+ org 30h
+ push bc ;000eh @ ffd6h
+ inc bc
+ jp (hl)
+
+ org 38h
+ push bc ;0010h @ ffd0h
+ inc bc
+ jp (hl)
+
+ org 0c0h ;pattern finish location
+ nop
+ jr 0c0h
+
+ org 0100h
+ ld sp, 0000h
+ xor a
+ ld bc, 0000h
+ ld de, 0010h
+ ld hl, 2010h
+ ld ix, 1000h
+ ld iy, 2000h
+ inc bc
+ jp (ix)
+
+ org 300h
+ dw 0001h ;c flag
+ dw 00feh ;not c flag
+ dw 0004h ;p/v flag
+ dw 00fbh ;not p/v flag
+ dw 0040h ;z flag
+ dw 00bfh ;not z flag
+ dw 0080h ;s flag
+ dw 007fh ;not s flag
+ dw 0000h ;pattern exit value
+
+ org 0400h
+ dw 7160h
+ dw 7170h
+ dw 7180h
+ dw 7190h
+ dw 71a0h
+ dw 71b0h
+ dw 71c0h
+ dw 71d0h
+ dw 71e0h
+ dw 71f0h
+
+ org 1000h
+ push bc ;0001h @ fffeh
+ inc bc
+ jp (iy)
+
+ org 2000h
+ push bc ;0002h @ fffch
+ inc bc
+ rst 00h ;2003h @ fffah
+
+ org 2010h
+ push bc ;0003h @ fff8h
+ add hl, de
+ inc bc
+ rst 08h ;2014h @ fff6h
+
+ org 2020h
+ push bc ;0005h @ fff2h
+ add hl, de
+ inc bc
+ rst 10h ;2024h @ fff0h
+
+ org 2030h
+ push bc ;0007h @ ffech
+ add hl, de
+ inc bc
+ rst 18h ;2034h @ ffeah
+
+ org 2040h
+ push bc ;0009h @ ffe6h
+ add hl, de
+ inc bc
+ rst 20h ;2044h @ ffe4h
+
+ org 2050h
+ push bc ;000bh @ ffe0h
+ add hl, de
+ inc bc
+ rst 28h ;2054h @ ffdeh
+
+ org 2060h
+ push bc ;000dh @ ffdah
+ add hl, de
+ inc bc
+ rst 30h ;2064h @ ffd8h
+
+ org 2070h
+ push bc ;000fh @ ffd4h
+ add hl, de
+ inc bc
+ rst 38h ;2074h @ ffd2h
+
+ org 2080h
+ jp 0ccffh
+
+ org 7000h
+ push bc ;0018h @ ffbeh
+ inc bc
+ ld sp, 0300h
+ pop af ;0001h @ 0300h
+ ld sp, 0ffbeh
+ call c, 7010h ;700ch @ ffbch
+ halt
+
+ org 7010h
+ push bc ;0019h @ ffbah
+ inc bc
+ jp c, 7020h
+ halt
+
+ org 7020h
+ push bc ;001ah @ ffb8h
+ inc bc
+ jr c, 7030h
+ halt
+
+ org 7030h
+ push bc ;001bh @ ffb6h
+ inc bc
+ ld sp, 0302h
+ pop af ;00feh @ 0302h
+ ld sp, 0ffb6h
+ call nc, 7040h ;703ch @ ffb4h
+ halt
+
+ org 7040h
+ push bc ;001ch @ ffb2h
+ inc bc
+ jp nc, 7050h
+ halt
+
+ org 7050h
+ push bc ;001dh @ ffb0h
+ inc bc
+ jr nc, 7060h
+ halt
+
+ org 7060h
+ push bc ;001eh @ ffaeh
+ inc bc
+ ld sp, 0304h
+ pop af ;0004h @ 0304h
+ ld sp, 0ffaeh
+ call pe, 7070h ;706ch @ ffach
+ halt
+
+ org 7070h
+ push bc ;001fh @ ffaah
+ inc bc
+ jp pe, 7080h
+ halt
+
+ org 7080h
+ push bc ;0020h @ ffa8h
+ inc bc
+ ld sp, 0306h
+ pop af ;00fbh @ 0306h
+ ld sp, 0ffa8h
+ call po, 7090h ;708ch @ ffa6h
+ halt
+
+ org 7090h
+ push bc ;0021h @ ffa4h
+ inc bc
+ jp po, 70a0h
+ halt
+
+ org 70a0h
+ push bc ;0022h @ ffa2h
+ inc bc
+ ld sp, 0308h
+ pop af ;0040h @ 0308h
+ ld sp, 0ffa2h
+ call z, 70b0h ;70ach @ ffa0h
+ halt
+
+ org 70b0h
+ push bc ;0023h @ ff9eh
+ inc bc
+ jp z, 70c0h
+ halt
+
+ org 70c0h
+ push bc ;0024h @ ff9ch
+ inc bc
+ jr z, 70d0h
+ halt
+
+ org 70d0h
+ push bc ;0025h @ ff9ah
+ inc bc
+ ld sp, 030ah
+ pop af ;00bfh @ 030ah
+ ld sp, 0ff9ah
+ call nz, 70e0h ;70dch @ ff98h
+ halt
+
+ org 70e0h
+ push bc ;0026h @ ff96h
+ inc bc
+ jp nz, 70f0h
+ halt
+
+ org 70f0h
+ push bc ;0027h @ ff94h
+ inc bc
+ jr nz, 7100h
+ halt
+
+ org 7100h
+ push bc ;0028h @ ff92h
+ inc bc
+ ld sp, 030ch
+ pop af ;0080h @ 030ch
+ ld sp, 0ff92h
+ call m, 7110h ;710ch @ ff90h
+ halt
+
+ org 7110h
+ push bc ;0029h @ ff8eh
+ inc bc
+ jp m, 7120h
+ halt
+
+ org 7120h
+ push bc ;002ah @ ff8ch
+ inc bc
+ ld sp, 030eh
+ pop af ;007fh @ 030eh
+ ld sp, 0ff8ch
+ call p, 7130h ;712ch @ ff8ah
+ halt
+
+ org 7130h
+ push bc ;002bh @ ff88h
+ inc bc
+ jp p, 7140h
+ halt
+
+ org 7140h
+ push bc ;002ch @ ff86h
+ inc bc
+ ld sp, 0300h
+ pop af ;0001h @ 0300h
+ ccf
+ ld hl, 0fe00h
+ ld sp, 0400h
+ ret ;7160h @ 0400h
+
+ org 7160h
+ ld (hl), c ; 2dh @ fe00h
+ inc bc
+ inc hl
+ ld sp, 0302h
+ pop af ;00feh @ 0302h
+ ccf
+ ld sp, 0402h
+ ret ;7170h @ 0402h
+
+ org 7170h
+ ld (hl), c ; 2eh @ fe01h
+ inc bc
+ inc hl
+ ld sp, 0300h
+ pop af ;0001h @ 0300h
+ ld sp, 0404h
+ ret c ;7180h @ 0404h
+
+ org 7180h
+ ld (hl), c ; 2fh @ fe02h
+ inc bc
+ inc hl
+ ld sp, 0302h
+ pop af ;00feh @ 0302h
+ ld sp, 0406h
+ ret nc ;7190h @ 0406h
+
+ org 7190h
+ ld (hl), c ; 30h @ fe03h
+ inc bc
+ inc hl
+ ld sp, 0304h
+ pop af ;0004h @ 0304h
+ ld sp, 0408h
+ ret pe ;71a0h @ 0408h
+
+ org 71a0h
+ ld (hl), c ; 31h @ fe04h
+ inc bc
+ inc hl
+ ld sp, 0306h
+ pop af ;00fbh @ 0306h
+ ld sp, 040ah
+ ret po ;71b0h @ 040ah
+
+ org 71b0h
+ ld (hl), c ; 32h @ fe05h
+ inc bc
+ inc hl
+ ld sp, 0308h
+ pop af ;0040h @ 0308h
+ ld sp, 040ch
+ ret z ;71c0h @ 040ch
+
+ org 71c0h
+ ld (hl), c ; 33h @ fe06h
+ inc bc
+ inc hl
+ ld sp, 030ah
+ pop af ;00bfh @ 030ah
+ ld sp, 040eh
+ ret nz ;71d0h @ 040eh
+
+ org 71d0h
+ ld (hl), c ; 34h @ fe07h
+ inc bc
+ inc hl
+ ld sp, 030ch
+ pop af ;0080h @ 030ch
+ ld sp, 0410h
+ ret m ;71e0h @ 0410h
+
+ org 71e0h
+ ld (hl), c ; 35h @ fe08h
+ inc bc
+ inc hl
+ ld sp, 030eh
+ pop af ;007fh @ 030eh
+ ld sp, 0412h
+ ret p ;71f0h @ 0412h
+
+ org 71f0h
+ ld (hl), c ; 36h @ fe09h
+ inc bc
+ ld sp, 0ff86h
+ ld b, 81h
+ djnz dlp1
+
+ org 7200h
+dlp1: push bc ;8037h @ ff84h
+ inc bc
+ ld b, 41h
+ djnz dlp2
+
+ org 7210h
+dlp2: push bc ;4038h @ ff82h
+ inc bc
+ ld b, 21h
+ djnz dlp3
+
+ org 7220h
+dlp3: push bc ;2039h @ ff80h
+ inc bc
+ ld b, 11h
+ djnz dlp4
+
+ org 7230h
+dlp4: push bc ;103ah @ ff7eh
+ inc bc
+ ld b, 09h
+ djnz dlp5
+
+ org 7240h
+dlp5: push bc ;083bh @ ff7ch
+ inc bc
+ ld b, 05h
+ djnz dlp6
+
+ org 7250h
+dlp6: push bc ;043ch @ ff7ah
+ inc bc
+ ld b, 03h
+ djnz dlp7
+
+ org 7260h
+dlp7: push bc ;023dh @ ff78h
+ inc bc
+ ld b, 01h
+ djnz dlp8
+ push bc ;003eh @ ff76h
+ inc bc
+ jr dlp9
+
+ org 7270h
+dlp8: halt
+
+ org 7280h
+dlp9: push bc ;003fh @ ff74h
+ inc bc
+ inc b
+ inc b
+ djnz dlpb
+ halt
+
+ org 728bh
+dlpa: push bc ;0241h @ ff70h
+ ld sp, 0310h
+ pop af ;0000h @ 0310h
+ ld hl, 0100h
+ jp 0c0h
+
+ org 7305h
+dlpb: push bc ;0140h @ ff72h
+ inc bc
+ inc b
+ inc b
+ djnz dlpa
+ halt
+
+ org 0ccffh
+ push bc ;0011h @ ffceh
+ inc bc
+ ld sp, 0300h
+ pop af ;0001h @ 0300h
+ jp nc, fail ;none taken
+ jr nc, fail
+ call nc, fail
+ ret nc
+ pop af ;00feh @ 0302h
+ jp c, fail ;none taken
+ jr c, fail
+ call c, fail
+ ret c
+ pop af ;0004h @ 0304h
+ jp po, fail ;none taken
+ call po, fail
+ ret po
+ pop af ;00fbh @ 0306h
+ jp pe, fail ;none taken
+ call pe, fail
+ ret pe
+ pop af ;0040h @ 0308h
+ jp nz, fail ;none taken
+ jr nz, fail
+ call nz, fail
+ ret nz
+ pop af ;00bfh @ 030ah
+ jp z, fail ;none taken
+ jr z, fail
+ call z, fail
+ ret z
+ pop af ;0080h @ 030ch
+ jp p, fail ;none taken
+ call p, fail
+ ret p
+ pop af ;007fh @ 030eh
+ jp m, fail ;none taken
+ call m, fail
+ ret m
+ jr rel2
+rel1: push bc ;0013h @ ffcah
+ inc bc
+ jr rel3
+fail: halt
+rel2: ld sp, 0300h
+ pop af ;0001h @ 0300h
+ ccf
+ ld sp, 0ffceh
+ push bc ;0012h @ ffcch
+ inc bc
+ jr rel1
+rel3: push bc ;0014h @ ffc8h
+ inc bc
+ jp 0cefbh
+
+ org 0cefbh
+ push bc ;0015h @ ffc6h
+ inc bc
+ jr rel5
+
+ org 0cf02h
+rel4: push bc ;0017h @ ffc2h
+ inc bc
+ call 07000h ;cf07h @ ffc0h
+
+ org 0cf7eh
+rel5: push bc ;0016h @ ffc4h
+ inc bc
+ jr rel4
+
+
+
+
+
+
Index: tags/ez80-instructions/asm/io_ops.s
===================================================================
--- tags/ez80-instructions/asm/io_ops.s (nonexistent)
+++ tags/ez80-instructions/asm/io_ops.s (revision 9)
@@ -0,0 +1,287 @@
+;**********************************************************************************
+;* *
+;* checks all i/o and block instructions *
+;* *
+;**********************************************************************************
+ aseg
+
+ org 00h
+ jp 01000h
+
+ org 0c0h ;pattern finish location
+ nop
+ jr 0c0h
+
+ org 0e0h
+ db 010h
+
+ org 01e1h
+ db 013h
+ db 088h
+
+ org 02e1h
+ db 012h
+ db 017h
+
+ org 03e1h
+ db 011h
+ db 016h
+
+ org 04e2h
+ db 015h
+
+ org 05e2h
+ db 014h
+
+ org 01000h
+ ld sp, 0000h
+ xor a
+ ld b, a
+ ld c, 0ffh
+ ld d, a
+ ld e, 021h
+ ld h, a
+ ld l, 0aah
+ ld a, 0cch
+ in a, (0f0h) ; 5ah @ ccf0h
+ push af ;5a44h @ fffeh
+ out (3ch), a ; 5ah @ 5a3ch
+ ld a, 0ffh
+
+ ld sp, 0ffd2h
+ ld bc, 0e123h
+ in b, (c) ; c6h @ e123h
+ push af ;ff84h @ ffd0h
+ push bc ;c623h @ ffceh
+ in c, (c) ; 10h @ c623h
+ push af ;ff00h @ ffcch
+ push bc ;c610h @ ffcah
+ in d, (c) ; a0h @ c610h
+ push af ;ff84h @ ffc8h
+ push bc ;c610h @ ffc6h
+ push de ;a021h @ ffc4h
+ inc bc
+ in e, (c) ; eah @ c611h
+ push af ;ff80h @ ffc2h
+ push bc ;c611h @ ffc0h
+ push de ;a0eah @ ffbeh
+ inc bc
+ in h, (c) ; 66h @ c612h
+ push af ;ff04h @ ffbch
+ push bc ;c612h @ ffbah
+ push de ;a0eah @ ffb8h
+ push hl ;66aah @ ffb6h
+ inc bc
+ in l, (c) ; 00h @ c613h
+ push af ;ff44h @ ffb4h
+ push bc ;c613h @ ffb2h
+ push de ;a0eah @ ffb0h
+ push hl ;6600h @ ffaeh
+ inc bc
+ in a, (c) ; 43h 2 c614h
+ push af ;4300h @ ffach
+ push bc ;c614h @ ffaah
+ push de ;a0eah @ ffa8h
+ push hl ;6600h @ ffa6h
+
+ inc bc
+ out (c), b ; c6h @ c615h
+ inc bc
+ out (c), c ; 16h @ c616h
+ inc bc
+ out (c), d ; a0h @ c617h
+ inc bc
+ out (c), e ; eah @ c618h
+ inc bc
+ out (c), h ; 66h @ c619h
+ inc bc
+ out (c), l ; 00h @ c61ah
+ inc bc
+ out (c), a ; 43h @ c61bh
+
+ or b
+ ld a, 043h
+
+ ld sp, 0ff8eh
+ ld bc, 08000h
+ ld de, 0a000h
+ ld hl, 05000h
+ ldd ; 55h @ 5000h read
+ ; 55h @ a000h write
+ push af ;4384h @ ff8ch
+ push bc ;7fffh @ ff8ah
+ push de ;9fffh @ ff88h
+ push hl ;4fffh @ ff86h
+ ldi ; aah @ 4fffh read
+ ; aah @ 9fffh write
+ push af ;4384h @ ff84h
+ push bc ;7ffeh @ ff82h
+ push de ;a000h @ ff80h
+ push hl ;5000h @ ff7eh
+ ld bc, 0003h
+ ld de, 0a001h
+ ld hl, 05002h
+ ldir ; 01h @ 5002h read
+ ; 01h @ a001h write
+ ; 02h @ 5003h read
+ ; 02h @ a002h write
+ ; 03h @ 5004h read
+ ; 03h @ a003h write
+ push af ;4380h @ ff7ch
+ push bc ;0000h @ ff7ah
+ push de ;a004h @ ff78h
+ push hl ;5005h @ ff76h
+ ld bc, 0004h
+ ld de, 09ffeh
+ ld hl, 04ffdh
+ lddr ; 04h @ 4ffdh read
+ ; 04h @ 9ffeh write
+ ; 05h @ 4ffch read
+ ; 05h @ 9ffdh write
+ ; 06h @ 4ffbh read
+ ; 06h @ 9ffch write
+ ; 07h @ 4ffah read
+ ; 07h @ 9ffbh write
+ push af ;4380h @ ff74h
+ push bc ;0000h @ ff72h
+ push de ;9ffah @ ff70h
+ push hl ;4ff9h @ ff6eh
+ cpd ; 08h @ 4ff9h read
+ push af ;4316h @ ff6ch
+ push bc ;ffffh @ ff6ah
+ push de ;9ffah @ ff68h
+ push hl ;4ff8h @ ff66h
+ ld bc, 0007h
+ cpdr ; 09h @ 4ff8h read
+ ; 0ah @ 4ff7h read
+ ; 43h @ 4ff6h read
+ push af ;4346h @ ff64h
+ push bc ;0004h @ ff62h
+ push de ;9ffah @ ff60h
+ push hl ;4ff5h @ ff5eh
+ ld bc, 8000h
+ ld hl, 5005h
+ cpi ; 0bh @ 5005h read
+ push af ;4316h @ ff5ch
+ push bc ;7fffh @ ff5ah
+ push de ;9ffah @ ff58h
+ push hl ;5006h @ ff56h
+ ld bc, 0004h
+ cpir ; 0ch @ 5006h read
+ ; 0dh @ 5007h read
+ ; 0eh @ 5008h read
+ ; 0fh @ 5009h read
+ push af ;4312h @ ff54h
+ push bc ;0000h @ ff52h
+ push de ;9ffah @ ff50h
+ push hl ;500ah @ ff4eh
+ ld bc, 00e0h
+ ini ; 10h @ 00e0h read
+ ; 10h @ 500ah write
+ push af ;4310h @ ff4ch
+ push bc ;ffe0h @ ff4ah
+ push de ;9ffah @ ff48h
+ push hl ;500bh @ ff46h
+ ld bc, 03e1h
+ inir ; 11h @ 03e1h read
+ ; 11h @ 500bh write
+ ; 12h @ 02e1h read
+ ; 12h @ 500ch write
+ ; 13h @ 01e1h read
+ ; 13h @ 500dh write
+ push af ;4350h @ ff44h
+ push bc ;00e1h @ ff42h
+ push de ;9ffah @ ff40h
+ push hl ;500eh @ ff3eh
+ ld bc, 05e2h
+ ld hl, 4ff5h
+ ind ; 14h @ 05e2h read
+ ; 14h @ 4ff5h write
+ push af ;4310h @ ff3ch
+ push bc ;04e2h @ ff3ah
+ push de ;9ffah @ ff38h
+ push hl ;4ff4h @ ff36h
+ indr ; 15h @ 04e2h read
+ ; 15h @ 4ff4h write
+ ; 16h @ 03e2h read
+ ; 16h @ 4ff3h write
+ ; 17h @ 02e2h read
+ ; 17h @ 4ff2h write
+ ; 88h @ 01e2h read
+ ; 88h @ 4ff1h write
+ push af ;4352h @ ff34h
+ push bc ;00e2h @ ff32h
+ push de ;9ffah @ ff30h
+ push hl ;4ff0h @ ff2eh
+ ld bc, 04e3h
+ outd ; 19h @ 4ff0h read
+ ; 19h @ 04e3h write
+ push af ;4310h @ ff2ch
+ push bc ;00e3h @ ff2ah
+ push de ;9ffah @ ff28h
+ push hl ;4fefh @ ff26h
+ otdr ; 1ah @ 4fefh read
+ ; 1ah @ 03e3h write
+ ; 1bh @ 4feeh read
+ ; 1bh @ 02e3h write
+ ; 1ch @ 4fedh read
+ ; 1ch @ 01e3h write
+ push af ;4350h @ ff24h
+ push bc ;00e3h @ ff22h
+ push de ;9ffah @ ff20h
+ push hl ;4fech @ ff1eh
+ ld bc, 05e4h
+ ld hl, 500eh
+ outi ; 1dh @ 500eh read
+ ; 1dh @ 05e4h write
+ push af ;4310h @ ff1ch
+ push bc ;04e4h @ ff1ah
+ push de ;9ffah @ ff18h
+ push hl ;500fh @ ff16h
+ otir ; 1eh @ 500fh read
+ ; 1eh @ 04e4h write
+ ; 1fh @ 5010h read
+ ; 1fh @ 03e4h write
+ ; 20h @ 5011h read
+ ; 20h @ 02e4h write
+ ; a1h @ 5012h read
+ ; a1h @ 01e4h write
+ push af ;4352h @ ff14h
+ push bc ;00e4h @ ff12h
+ push de ;9ffah @ ff10h
+ push hl ;5013h @ ff0eh
+
+ ld hl, 0100h
+ jp 0c0h
+
+ org 04fe8h
+ db 0ffh, 0ffh, 0a8h, 027h, 026h, 01ch, 01bh, 01ah
+ db 019h, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 043h, 00ah
+ db 009h, 008h, 007h, 006h, 005h, 004h, 0ffh, 0aah
+ db 055h, 0ffh, 001h, 002h, 003h, 00bh, 00ch, 00dh
+ db 00eh, 00fh, 0ffh, 0ffh, 0ffh, 0ffh, 01dh, 01eh
+ db 01fh, 020h, 0a1h, 022h, 023h, 022h, 025h, 0ffh
+
+ org 06600h
+ db 0bch
+
+ org 0c610h
+ db 0a0h, 0eah, 066h, 000h, 043h
+
+ org 0c61bh
+ db 08fh
+
+ org 0c623h
+ db 10h
+
+ org 0ccf0h
+ db 05ah
+
+ org 0e123h
+ db 0c6h
+
+
+
+
+
+
Index: tags/ez80-instructions/asm/jmp_opsd.s
===================================================================
--- tags/ez80-instructions/asm/jmp_opsd.s (nonexistent)
+++ tags/ez80-instructions/asm/jmp_opsd.s (revision 9)
@@ -0,0 +1,29 @@
+;**********************************************************************************
+;* *
+;* jmp_ops compare data *
+;* *
+;**********************************************************************************
+ org 0fe00h
+ db 02dh, 02eh, 02fh, 030h, 031h, 032h, 033h, 034h
+ db 035h, 036h
+
+ org 0ff70h
+ dw 00241h, 00140h, 0003fh, 0003eh ;ff70h
+ dw 0023dh, 0043ch, 0083bh, 0103ah ;ff78h
+ dw 02039h, 04038h, 08037h, 0002ch ;ff80h
+ dw 0002bh, 0712ch, 0002ah, 00029h ;ff88h
+ dw 0710ch, 00028h, 00027h, 00026h ;ff90h
+ dw 070dch, 00025h, 00024h, 00023h ;ff98h
+ dw 070ach, 00022h, 00021h, 0708ch ;ffa0h
+ dw 00020h, 0001fh, 0706ch, 0001eh ;ffa8h
+ dw 0001dh, 0001ch, 0703ch, 0001bh ;ffb0h
+ dw 0001ah, 00019h, 0700ch, 00018h ;ffb8h
+ dw 0cf07h, 00017h, 00016h, 00015h ;ffc0h
+ dw 00014h, 00013h, 00012h, 00011h ;ffc8h
+ dw 00010h, 02074h, 0000fh, 0000eh ;ffd0h
+ dw 02064h, 0000dh, 0000ch, 02054h ;ffd8h
+ dw 0000bh, 0000ah, 02044h, 00009h ;ffe0h
+ dw 00008h, 02034h, 00007h, 00006h ;ffe8h
+ dw 02024h, 00005h, 00004h, 02014h ;fff0h
+ dw 00003h, 02003h, 00002h, 00001h ;fff8h
+
Index: tags/ez80-instructions/asm/io_opsd.s
===================================================================
--- tags/ez80-instructions/asm/io_opsd.s (nonexistent)
+++ tags/ez80-instructions/asm/io_opsd.s (revision 9)
@@ -0,0 +1,80 @@
+;**********************************************************************************
+;* *
+;* io_ops compare data *
+;* *
+;**********************************************************************************
+ org 000h
+ db 025h
+
+ org 0f8h
+ db 0ffh, 0a8h, 027h, 026h, 025h, 024h, 023h, 022h ;00f8h
+
+ org 01e3h
+ db 01ch, 0a1h
+
+ org 02e3h
+ db 01bh, 020h
+
+ org 03e3h
+ db 01ah, 01fh
+
+ org 04e3h
+ db 019h, 01eh
+
+ org 05e4h
+ db 01dh
+
+ org 04ff0h
+ db 0ffh, 088h, 017h, 016h, 015h, 014h, 0ffh, 0ffh ;4ff0h
+
+ org 05008h
+ db 0ffh, 0ffh, 010h, 011h, 012h, 013h, 0ffh, 0ffh ;5008h
+
+ org 05a3ch
+ db 05ah
+
+ org 09ff8h
+ db 0ffh, 0ffh, 0ffh, 007h, 006h, 005h, 004h, 0aah ;09ff8h
+ db 055h, 001h, 002h, 003h, 0ffh, 0ffh, 0ffh, 0ffh ;0a000h
+
+ org 0c610h
+ db 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0c6h, 016h, 0a0h ;c610h
+ db 0eah, 066h, 000h, 043h, 08fh, 0ffh, 0ffh, 0ffh ;c618h
+
+ org 0fee8h
+ dw 0ffffh, 0ffffh, 0ffffh, 0ffffh ;fee8h
+ dw 0ffffh, 0ffffh, 0ffffh, 0ffffh ;fef0h
+ dw 0ffffh, 0ffffh, 0ffffh, 0ffffh ;fef8h
+ dw 0ffffh, 0ffffh, 0ffffh, 0ffffh ;ff00h
+ dw 0ffffh, 0ffffh, 0ffffh, 05013h ;ff08h
+ dw 09ffah, 000e4h, 04352h, 0500fh ;ff10h
+ dw 09ffah, 004e4h, 04310h, 04fech ;ff18h
+ dw 09ffah, 000e3h, 04350h, 04fefh ;ff20h
+ dw 09ffah, 003e3h, 04310h, 04ff0h ;ff28h
+ dw 09ffah, 000e2h, 04352h, 04ff4h ;ff30h
+ dw 09ffah, 004e2h, 04310h, 0500eh ;ff38h
+ dw 09ffah, 000e1h, 04350h, 0500bh ;ff40h
+ dw 09ffah, 0ffe0h, 04310h, 0500ah ;ff48h
+ dw 09ffah, 00000h, 04312h, 05006h ;ff50h
+ dw 09ffah, 07fffh, 04316h, 04ff5h ;ff58h
+ dw 09ffah, 00004h, 04346h, 04ff8h ;ff60h
+ dw 09ffah, 0ffffh, 04316h, 04ff9h ;ff68h
+ dw 09ffah, 00000h, 04380h, 05005h ;ff70h
+ dw 0a004h, 00000h, 04380h, 05000h ;ff78h
+ dw 0a000h, 07ffeh, 04384h, 04fffh ;ff80h
+ dw 09fffh, 07fffh, 04384h, 0ffffh ;ff88h
+ dw 0ffffh, 0ffffh, 0ffffh, 0ffffh ;ff90h
+ dw 0ffffh, 0ffffh, 0ffffh, 0ffffh ;ff98h
+ dw 0ffffh, 0ffffh, 0ffffh, 06600h ;ffa0h
+ dw 0a0eah, 0c614h, 04300h, 06600h ;ffa8h
+ dw 0a0eah, 0c613h, 0ff44h, 066aah ;ffb0h
+ dw 0a0eah, 0c612h, 0ff04h, 0a0eah ;ffb8h
+ dw 0c611h, 0ff80h, 0a021h, 0c610h ;ffc0h
+ dw 0ff84h, 0c610h, 0ff00h, 0c623h ;ffc8h
+ dw 0ff84h, 0ffffh, 0ffffh, 0ffffh ;ffd0h
+ dw 0ffffh, 0ffffh, 0ffffh, 0ffffh ;ffd8h
+ dw 0ffffh, 0ffffh, 0ffffh, 0ffffh ;ffe0h
+ dw 0ffffh, 0ffffh, 0ffffh, 0ffffh ;ffe8h
+ dw 0ffffh, 0ffffh, 0ffffh, 0ffffh ;fff0h
+ dw 0ffffh, 0ffffh, 0ffffh, 05a44h ;fff8h
+
Index: tags/ez80-instructions/rtl/defines.v
===================================================================
--- tags/ez80-instructions/rtl/defines.v (nonexistent)
+++ tags/ez80-instructions/rtl/defines.v (revision 9)
@@ -0,0 +1,476 @@
+/*******************************************************************************************/
+/** **/
+/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
+/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
+/** **/
+/** define file to make the code more readable Rev 0.0 06/18/2012 **/
+/** **/
+/*******************************************************************************************/
+
+ /*****************************************************************************************/
+ /* */
+ /* page register control - DO NOT MODIFY */
+ /* */
+ /*****************************************************************************************/
+ `define MAIN_PG 4'b0000 //no instruction prefix byte(s)
+ `define INTR_PG 4'b0001 //interrupt acknowledge
+ `define CB_PAGE 4'b0010 //CB instruction prefix
+ `define DMA_PG 4'b0011 //dma acknowledge
+ `define DD_PAGE 4'b0100 //DD instruction prefix
+ `define FD_PAGE 4'b0101 //FD instruction prefix
+ `define DDCB_PG 4'b0110 //DD-CB instruction prefix
+ `define FDCB_PG 4'b0111 //FD-CB instruction prefix
+ `define ED_PAGE 4'b1000 //ED instruction prefix
+ `define DEC_MAIN 4'b0x0x //main page or DD page or FD page
+ `define DEC_ED 4'b1xxx //ED page
+
+ /*****************************************************************************************/
+ /* */
+ /* program counter register control: pc_sel */
+ /* */
+ /*****************************************************************************************/
+ `define PCCTL_IDX 2
+ `define PC_NUL 3'b000 //No operation on PC
+ `define PC_LD 3'b001 //PC loaded unconditionally
+ `define PC_NILD 3'b011 //PC loaded if no interrupt, sample interrupt
+ `define PC_INT 3'b100 //Sample interrupt/dma only
+ `define PC_DMA 3'b110 //Sample dma only
+ `define PC_NILD2 3'b111 //PC loaded if no latched interrupt
+
+ /*****************************************************************************************/
+ /* */
+ /* address bus select: add_sel */
+ /* */
+ /*****************************************************************************************/
+ `define ADCTL_IDX 4
+ `define ADD_RSTVAL 5'b00000 //Pipeline register reset value
+ `define ADD_PC 5'b00001 //Select address register from PC
+ `define ADD_HL 5'b00010 //Select address register from HL
+ `define ADD_SP 5'b00100 //Select address register from SP
+ `define ADD_ALU 5'b01000 //Select address register from ALU
+ `define ADD_ALU8 5'b10000 //Select address register from {8'h0, ALU[7:0]}
+
+ `define AD_PC 0 //Address from PC
+ `define AD_HL 1 //Address from HL
+ `define AD_SP 2 //Address from SP
+ `define AD_ALU 3 //Address from ALU
+ `define AD_ALU8 4 //Address from {8'h0, ALU[7:0]}
+
+ /*****************************************************************************************/
+ /* */
+ /* transaction type select: tran_sel */
+ /* */
+ /*****************************************************************************************/
+ `define TTYPE_IDX 5
+ `define TRAN_RSTVAL 6'b000000 //Transaction type reset value
+ `define TRAN_IAK 6'b000001 //Intack transaction
+ `define TRAN_IDL 6'b000010 //Idle transaction
+ `define TRAN_IF 6'b000100 //Instruction fetch transaction
+ `define TRAN_IO 6'b001000 //I/O transaction
+ `define TRAN_MEM 6'b010000 //Memory (data) transaction
+ `define TRAN_STK 6'b100000 //Memory (stack) transaction
+
+ `define TT_IAK 0 //Interrupt acknowledge transaction
+ `define TT_IDL 1 //Idle transaction
+ `define TT_IF 2 //Instruction fetch transaction
+ `define TT_IO 3 //I/O transaction
+ `define TT_MEM 4 //Memory (data) transaction
+ `define TT_STK 5 //Memory (stack) transaction
+
+ /*****************************************************************************************/
+ /* */
+ /* data output control: do_ctl - DO NOT MODIFY */
+ /* */
+ /*****************************************************************************************/
+ `define DO_IDX 2
+ `define DO_NUL 3'b000 //No load
+ `define DO_IO 3'b010 //Load i/o data from lsb
+ `define DO_LSB 3'b100 //Load mem data from lsb
+ `define DO_MSB 3'b101 //Load mem data from msb
+
+ /*****************************************************************************************/
+ /* */
+ /* data input control: di_ctl - DO NOT MODIFY */
+ /* */
+ /*****************************************************************************************/
+ `define DI_IDX 1
+ `define DI_NUL 2'b00 //No load
+ `define DI_DI0 2'b01 //Load din0
+ `define DI_DI1 2'b10 //Load din1
+ `define DI_DI10 2'b11 //Load both din0 and din1
+
+ /*****************************************************************************************/
+ /* */
+ /* interrupt enable control: ief_ctl - DO NOT MODIFY */
+ /* */
+ /*****************************************************************************************/
+ `define IEF_IDX 2
+ `define IEF_NUL 3'b000 //No load
+ `define IEF_0 3'b010 //Load zero
+ `define IEF_1 3'b011 //Load one
+ `define IEF_NMI 3'b100 //ief2 <= ief1, ief1 <= 0
+ `define IEF_RTN 3'b101 //ief1 <= ief2
+
+ /*****************************************************************************************/
+ /* */
+ /* int mode control: imd_ctl - DO NOT MODIFY */
+ /* */
+ /*****************************************************************************************/
+ `define IMD_IDX 1
+ `define IMD_NUL 2'b00 //No load
+ `define IMD_0 2'b01 //Set interrupt mode 0
+ `define IMD_1 2'b10 //Set interrupt mode 1
+ `define IMD_2 2'b11 //Set interrupt mode 2
+
+ /*****************************************************************************************/
+ /* */
+ /* half-carry flag control: hflg_ctl - DO NOT MODIFY */
+ /* */
+ /*****************************************************************************************/
+ `define HFLG_IDX 1
+ `define HFLG_NUL 2'b00 //No load
+ `define HFLG_H 2'b01 //Load half-carry result
+ `define HFLG_0 2'b10 //Load zero
+ `define HFLG_1 2'b11 //Load one
+
+ /*****************************************************************************************/
+ /* */
+ /* parity/overflow flag control: pflg_ctl */
+ /* */
+ /*****************************************************************************************/
+ `define PFLG_IDX 2
+ `define PFLG_NUL 3'b000 //No load
+ `define PFLG_V 3'b001 //Load overflow result
+ `define PFLG_0 3'b010 //Load zero
+ `define PFLG_1 3'b011 //Load one
+ `define PFLG_P 3'b100 //Load parity result
+ `define PFLG_B 3'b101 //Load block count zero result
+ `define PFLG_F 3'b111 //Load ief
+
+ /*****************************************************************************************/
+ /* */
+ /* negate flag control: nflg_ctl - DO NOT MODIFY */
+ /* */
+ /*****************************************************************************************/
+ `define NFLG_IDX 1
+ `define NFLG_NUL 2'b00 //No load
+ `define NFLG_S 2'b01 //Load sign result
+ `define NFLG_0 2'b10 //Load zero
+ `define NFLG_1 2'b11 //Load one
+
+ /*****************************************************************************************/
+ /* */
+ /* temporary flag control: tflg_ctl */
+ /* */
+ /*****************************************************************************************/
+ `define TFLG_IDX 1
+ `define TFLG_NUL 2'b00 //No load
+ `define TFLG_Z 2'b01 //Load zero result
+ `define TFLG_1 2'b10 //Load one result (blk out)
+ `define TFLG_B 2'b11 //Load blk cp result
+
+ /*****************************************************************************************/
+ /* */
+ /* write register control: wr_sel - unencoded */
+ /* */
+ /*****************************************************************************************/
+ `define WREG_IDX 16
+ `define WREG_BB 17'b11000000000000000 //Select B to write
+ `define WREG_BC 17'b11100000000000000 //Select BC to write
+ `define WREG_CC 17'b10100000000000000 //Select C to write
+ `define WREG_DD 17'b10010000000000000 //Select D to write
+ `define WREG_DE 17'b10011000000000000 //Select DE to write
+ `define WREG_EE 17'b10001000000000000 //Select E to write
+ `define WREG_HH 17'b10000100000000000 //Select H to write
+ `define WREG_HL 17'b10000110000000000 //Select HL to write
+ `define WREG_LL 17'b10000010000000000 //Select L to write
+ `define WREG_DEHL 17'b10011110000000000 //Select DEHL to write (ex case)
+ `define WREG_AA 17'b10000001000000000 //Select A to write
+ `define WREG_AF 17'b10000001100000000 //Select A and F to write
+ `define WREG_FF 17'b10000000100000000 //Select F to write
+ `define WREG_SP 17'b10000000010000000 //Select SP to write
+ `define WREG_TMP 17'b10000000001000000 //Select TMP register to write
+ `define WREG_IXH 17'b10000000000100000 //Select IXH to write
+ `define WREG_IX 17'b10000000000110000 //Select IX to write
+ `define WREG_IXL 17'b10000000000010000 //Select IXL to write
+ `define WREG_IYH 17'b10000000000001000 //Select IYH to write
+ `define WREG_IY 17'b10000000000001100 //Select IY to write
+ `define WREG_IYL 17'b10000000000000100 //Select IYL to write
+ `define WREG_II 17'b10000000000000010 //Select I register to write
+ `define WREG_RR 17'b10000000000000001 //Select R register to write
+ `define WREG_NUL 17'b00000000000000000 //No register write
+
+ `define WR_REG 16 //register write
+ `define WR_BB 15 //BB register index
+ `define WR_CC 14 //CC register index
+ `define WR_DD 13 //DD register index
+ `define WR_EE 12 //EE register index
+ `define WR_HH 11 //HH register index
+ `define WR_LL 10 //LL register index
+ `define WR_AA 9 //AA register index
+ `define WR_FF 8 //FF register index
+ `define WR_SP 7 //SP register index
+ `define WR_TMP 6 //TMP register index
+ `define WR_IXH 5 //IXH register index
+ `define WR_IXL 4 //IXL register index
+ `define WR_IYH 3 //IYH register index
+ `define WR_IYL 2 //IYL register index
+ `define WR_II 1 //II register index
+ `define WR_RR 0 //RR register index
+
+ /*****************************************************************************************/
+ /* */
+ /* ALU input A control: alua_sel */
+ /* */
+ /*****************************************************************************************/
+ `define ALUA_IDX 14
+ `define ALUA_RSTVAL 15'h0000 //Reset value for pipeline controls
+ `define ALUA_ZER 15'h0000 //Select 16'h0000 (default)
+ `define ALUA_ONE 15'h0001 //Select 16'h0001
+ `define ALUA_M1 15'h0002 //Select 16'hFFFF
+ `define ALUA_M2 15'h0004 //Select 16'hFFFE
+ `define ALUA_HL 15'h0008 //Select HL register
+ `define ALUA_IX 15'h0010 //Select IX register
+ `define ALUA_IY 15'h0020 //Select IY register
+ `define ALUA_PC 15'h0040 //Select PC register
+ `define ALUA_AA 15'h0080 //Select A register
+ `define ALUA_BIT 15'h0100 //Select bit select constant
+ `define ALUA_DAA 15'h0200 //Select decimal adjust constant
+ `define ALUA_II 15'h0400 //Select I register
+ `define ALUA_RR 15'h0800 //Select R register
+ `define ALUA_INT 15'h1000 //Select interrupt address
+ `define ALUA_TMP 15'h2000 //Select TMP register
+ `define ALUA_RST 15'h4000 //Select restart address
+
+ `define AA_ONE 0 //alua one
+ `define AA_M1 1 //alua -1
+ `define AA_M2 2 //alua -2
+ `define AA_HL 3 //alua hl
+ `define AA_IX 4 //alua ix
+ `define AA_IY 5 //alua iy
+ `define AA_PC 6 //alua pc
+ `define AA_AA 7 //alua aa
+ `define AA_BIT 8 //alua bit
+ `define AA_DAA 9 //alua daa
+ `define AA_II 10 //alua ii
+ `define AA_RR 11 //alua rr
+ `define AA_INT 12 //alua interrupt
+ `define AA_TMP 13 //alua tmp
+ `define AA_RST 14 //alua restart
+
+ /*****************************************************************************************/
+ /* */
+ /* ALU input B control: alub_sel */
+ /* */
+ /*****************************************************************************************/
+ `define ALUB_IDX 12
+ `define ALUB_RSTVAL 13'h1000 //Reset value for pipeline controls
+ `define ALUB_AF 13'h1002 //Select A and F registers
+ `define ALUB_AA 13'h1003 //Select A register
+ `define ALUB_BC 13'h0004 //Select BC register
+ `define ALUB_BB 13'h0005 //Select B register
+ `define ALUB_CC 13'h0004 //Select C register
+ `define ALUB_DE 13'h0008 //Select DE register
+ `define ALUB_DD 13'h0009 //Select D register
+ `define ALUB_EE 13'h0008 //Select E register
+ `define ALUB_HL 13'h0010 //Select HL register
+ `define ALUB_HH 13'h0011 //Select H register
+ `define ALUB_LL 13'h0010 //Select L register
+ `define ALUB_IX 13'h0020 //Select IX register
+ `define ALUB_IXH 13'h0021 //Select IX register high byte
+ `define ALUB_IXL 13'h0020 //Select IX register low byte
+ `define ALUB_IY 13'h0040 //Select IY register
+ `define ALUB_IYH 13'h0041 //Select IY register high byte
+ `define ALUB_IYL 13'h0040 //Select IY register low byte
+ `define ALUB_SP 13'h0080 //Select SP register
+ `define ALUB_SPH 13'h0081 //Select SP register high byte
+ `define ALUB_DIN 13'h0100 //Select data input register
+ `define ALUB_DINH 13'h0101 //Select data input register high byte
+ `define ALUB_IO 13'h0200 //Select i/o address
+ `define ALUB_TMP 13'h0400 //Select TMP register
+ `define ALUB_TMPH 13'h0401 //Select TMP register high byte
+ `define ALUB_PC 13'h1800 //Select PC register
+ `define ALUB_PCH 13'h1801 //Select PC register high byte
+
+ `define AB_SHR 0 //alub shift right
+ `define AB_AF 1 //alub af
+ `define AB_BC 2 //alub bc
+ `define AB_DE 3 //alub de
+ `define AB_HL 4 //alub hl
+ `define AB_IX 5 //alub ix
+ `define AB_IY 6 //alub iy
+ `define AB_SP 7 //alub sp
+ `define AB_DIN 8 //alub din
+ `define AB_IO 9 //alub io
+ `define AB_TMP 10 //alub tmp
+ `define AB_PC 11 //alub pc
+ `define AB_ADR 12 //alub address pc
+
+ /*****************************************************************************************/
+ /* */
+ /* ALU operation control: aluop_sel - 2 MSBs fixed for unit sel */
+ /* */
+ /*****************************************************************************************/
+ `define ALUOP_IDX 7
+ `define ALUOP_RSTVAL 8'b00000000 //Reset Value for pipeline controls
+ `define ALUOP_ADD 8'b01000000 //ALU math: add
+ `define ALUOP_BADD 8'b01000001 //ALU math: byte add
+ `define ALUOP_BDEC 8'b01000011 //ALU math: byte add (decrement)
+ `define ALUOP_ADS 8'b01000100 //ALU math: add signed byte
+ `define ALUOP_DAA 8'b01000101 //ALU math: byte add (daa)
+ `define ALUOP_ADC 8'b01001000 //ALU math: add with carry
+ `define ALUOP_BADC 8'b01001001 //ALU math: byte add with carry
+ `define ALUOP_SUB 8'b01010000 //ALU math: subtract
+ `define ALUOP_BSUB 8'b01010001 //ALU math: subtract
+ `define ALUOP_SBC 8'b01100000 //ALU math: subtract with carry
+ `define ALUOP_BSBC 8'b01100001 //ALU math: byte subtract with carry
+
+ `define ALUOP_PASS 8'b00000000 //ALU logic: pass b bus
+ `define ALUOP_BAND 8'b00000011 //ALU logic: byte and
+ `define ALUOP_BOR 8'b00000101 //ALU logic: byte or
+ `define ALUOP_BXOR 8'b00001001 //ALU logic: byte or
+ `define ALUOP_CCF 8'b00010000 //ALU logic: complement carry
+ `define ALUOP_SCF 8'b00010010 //ALU logic: set carry
+ `define ALUOP_RLD1 8'b00011000 //ALU logic: rld first step
+ `define ALUOP_RLD2 8'b00011010 //ALU logic: rld second step
+ `define ALUOP_RRD1 8'b00011100 //ALU logic: rrd first step
+ `define ALUOP_RRD2 8'b00011110 //ALU logic: rrd second step
+ `define ALUOP_APAS 8'b00100000 //ALU logic: pass a bus
+
+ `define ALUOP_RL 8'b10000000 //ALU shft: rotate left
+ `define ALUOP_RLA 8'b10000001 //ALU shft: rotate left acc
+ `define ALUOP_RLC 8'b10000010 //ALU shft: rotate left circular
+ `define ALUOP_RLCA 8'b10000011 //ALU shft: rotate left circular acc
+ `define ALUOP_RR 8'b10000100 //ALU shft: rotate right
+ `define ALUOP_RRA 8'b10000101 //ALU shft: rotate right acc
+ `define ALUOP_RRC 8'b10001000 //ALU shft: rotate right circular
+ `define ALUOP_RRCA 8'b10001001 //ALU shft: rotate right circular acc
+ `define ALUOP_SLA 8'b10010000 //ALU shft: shift left arithmetic
+ `define ALUOP_SLL 8'b10011000 //ALU shft: shift left logical (x = (x << 1) | 1)
+ `define ALUOP_SRL 8'b10100000 //ALU shft: shift right logical
+ `define ALUOP_SRA 8'b10101000 //ALU shft: shift right arithmetic
+
+ `define ALUOP_MLT 8'b11000000 //ALU mult: 8 bit multiplication
+ /*****************************************************************************************/
+ /* */
+ /* ALU operation control: 6 encoded */
+ /* */
+ /*****************************************************************************************/
+ `define AOP_IDX 5
+ `define AOP_ADD 6'b000000 //ALU math: add
+ `define AOP_BADD 6'b000001 //ALU math: byte add
+ `define AOP_BDEC 6'b000011 //ALU math: byte add (decrement)
+ `define AOP_ADS 6'b000100 //ALU math: add signed byte
+ `define AOP_DAA 6'b000101 //ALU math: byte add (daa)
+ `define AOP_ADC 6'b001000 //ALU math: add with carry
+ `define AOP_BADC 6'b001001 //ALU math: byte add with carry
+ `define AOP_SUB 6'b010000 //ALU math: subtract
+ `define AOP_BSUB 6'b010001 //ALU math: subtract
+ `define AOP_SBC 6'b100000 //ALU math: subtract with carry
+ `define AOP_BSBC 6'b100001 //ALU math: byte subtract with carry
+
+ `define AOP_PASS 6'b000000 //ALU logic: pass b bus
+ `define AOP_BAND 6'b000011 //ALU logic: byte and
+ `define AOP_BOR 6'b000101 //ALU logic: byte or
+ `define AOP_BXOR 6'b001001 //ALU logic: byte or
+ `define AOP_CCF 6'b010000 //ALU logic: complement carry
+ `define AOP_SCF 6'b010010 //ALU logic: set carry
+ `define AOP_RLD1 6'b011000 //ALU logic: rld first step
+ `define AOP_RLD2 6'b011010 //ALU logic: rld second step
+ `define AOP_RRD1 6'b011100 //ALU logic: rrd first step
+ `define AOP_RRD2 6'b011110 //ALU logic: rrd second step
+ `define AOP_APAS 6'b100000 //ALU logic: pass a bus
+
+ `define AOP_RL 6'b000000 //ALU shft: rotate left
+ `define AOP_RLA 6'b000001 //ALU shft: rotate left acc
+ `define AOP_RLC 6'b000010 //ALU shft: rotate left circular
+ `define AOP_RLCA 6'b000011 //ALU shft: rotate left circular acc
+ `define AOP_RR 6'b000100 //ALU shft: rotate right
+ `define AOP_RRA 6'b000101 //ALU shft: rotate right acc
+ `define AOP_RRC 6'b001000 //ALU shft: rotate right circular
+ `define AOP_RRCA 6'b001001 //ALU shft: rotate right circular acc
+ `define AOP_SLA 6'b010000 //ALU shft: shift left arithmetic
+ `define AOP_SLL 6'b011000 //ALU shft: shift left logical
+ `define AOP_SRL 6'b100000 //ALU shft: shift right logical
+ `define AOP_SRA 6'b101000 //ALU shft: shift right arithmetic
+
+ `define AOP_MLT 6'b000000 //ALU mult: 8 bit multiplication
+ /*****************************************************************************************/
+ /* */
+ /* machine state - pseudo-one-hot */
+ /* */
+ /*****************************************************************************************/
+ `define STATE_IDX 31
+ `define sRST 32'b00000000000000000000000000000000 //reset
+ `define sDEC1 32'b00000000000000000000000000000011 //decode 1st opcode
+ `define sIF2B 32'b00000000000000000000000000000101 //fetch 2nd opcode (2)
+ `define sDEC2 32'b00000000000000000000000000001001 //decode 2nd opcode
+ `define sOF1B 32'b00000000000000000000000000010001 //fetch 1st operand (2)
+ `define sOF2A 32'b00000000000000000000000000100001 //fetch 2nd operand (1)
+ `define sOF2B 32'b00000000000000000000000001000001 //fetch 2nd operand (2)
+ `define sIF3A 32'b00000000000000000000000010000001 //fetch 3rd opcode (1)
+ `define sIF3B 32'b00000000000000000000000100000001 //fetch 3rd opcode (2)
+ `define sADR1 32'b00000000000000000000001000000001 //address calculate (1)
+ `define sADR2 32'b00000000000000000000010000000001 //address calculate (2)
+ `define sRD1A 32'b00000000000000000000100000000001 //read 1st operand (1)
+ `define sRD1B 32'b00000000000000000001000000000001 //read 1st operand (2)
+ `define sRD2A 32'b00000000000000000010000000000001 //read 2nd operand (1)
+ `define sRD2B 32'b00000000000000000100000000000001 //read 2nd operand (2)
+ `define sWR1A 32'b00000000000000001000000000000001 //write 1st operand (1)
+ `define sWR1B 32'b00000000000000010000000000000001 //write 1st operand (2)
+ `define sWR2A 32'b00000000000000100000000000000001 //write 2nd operand (1)
+ `define sWR2B 32'b00000000000001000000000000000001 //write 2nd operand (2)
+ `define sBLK1 32'b00000000000010000000000000000001 //block instruction (1)
+ `define sBLK2 32'b00000000000100000000000000000001 //block instruction (2)
+ `define sPCA 32'b00000000001000000000000000000001 //PC adjust
+ `define sPCO 32'b00000000010000000000000000000001 //PC output
+ `define sIF1A 32'b00000000100000000000000000000001 //fetch 1st opcode (1)
+ `define sIF1B 32'b00000001000000000000000000000001 //fetch 1st opcode (2)
+ `define sINTA 32'b00000010000000000000000000000001 //interrupt acknowledge (1)
+ `define sINTB 32'b00000100000000000000000000000001 //interrupt acknowledge (2)
+ `define sHLTA 32'b00001000000000000000000000000001 //halt & sleep (1)
+ `define sHLTB 32'b00010000000000000000000000000001 //halt & sleep (2)
+ `define sDMA1 32'b00100000000000000000000000000001 //dma transfer (1)
+ `define sDMA2 32'b01000000000000000000000000000001 //dma transfer (2)
+ `define sRSTE 32'b10000000000000000000000000000001 //reset exit
+
+ `define RST 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0 //reset
+ `define DEC1 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11 //decode 1st opcode
+ `define IF2B 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1x1 //fetch 2nd opcode (2)
+ `define DEC2 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxx1xx1 //decode 2nd opcode
+ `define OF1B 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxx1xxx1 //fetch 1st operand (2)
+ `define OF2A 32'bxxxxxxxxxxxxxxxxxxxxxxxxxx1xxxx1 //fetch 2nd operand (1)
+ `define OF2B 32'bxxxxxxxxxxxxxxxxxxxxxxxxx1xxxxx1 //fetch 2nd operand (2)
+ `define IF3A 32'bxxxxxxxxxxxxxxxxxxxxxxxx1xxxxxx1 //fetch 3rd opcode (1)
+ `define IF3B 32'bxxxxxxxxxxxxxxxxxxxxxxx1xxxxxxx1 //fetch 3rd opcode (2)
+ `define ADR1 32'bxxxxxxxxxxxxxxxxxxxxxx1xxxxxxxx1 //address calculate (1)
+ `define ADR2 32'bxxxxxxxxxxxxxxxxxxxxx1xxxxxxxxx1 //address calculate (2)
+ `define RD1A 32'bxxxxxxxxxxxxxxxxxxxx1xxxxxxxxxx1 //read 1st operand (1)
+ `define RD1B 32'bxxxxxxxxxxxxxxxxxxx1xxxxxxxxxxx1 //read 1st operand (2)
+ `define RD2A 32'bxxxxxxxxxxxxxxxxxx1xxxxxxxxxxxx1 //read 2nd operand (1)
+ `define RD2B 32'bxxxxxxxxxxxxxxxxx1xxxxxxxxxxxxx1 //read 2nd operand (2)
+ `define WR1A 32'bxxxxxxxxxxxxxxxx1xxxxxxxxxxxxxx1 //write 1st operand (1)
+ `define WR1B 32'bxxxxxxxxxxxxxxx1xxxxxxxxxxxxxxx1 //write 1st operand (2)
+ `define WR2A 32'bxxxxxxxxxxxxxx1xxxxxxxxxxxxxxxx1 //write 2nd operand (1)
+ `define WR2B 32'bxxxxxxxxxxxxx1xxxxxxxxxxxxxxxxx1 //write 2nd operand (2)
+ `define BLK1 32'bxxxxxxxxxxxx1xxxxxxxxxxxxxxxxxx1 //block instruction (1)
+ `define BLK2 32'bxxxxxxxxxxx1xxxxxxxxxxxxxxxxxxx1 //block instruction (2)
+ `define PCA 32'bxxxxxxxxxx1xxxxxxxxxxxxxxxxxxxx1 //PC adjust
+ `define PCO 32'bxxxxxxxxx1xxxxxxxxxxxxxxxxxxxxx1 //PC output
+ `define IF1A 32'bxxxxxxxx1xxxxxxxxxxxxxxxxxxxxxx1 //fetch 1st opcode (1)
+ `define IF1B 32'bxxxxxxx1xxxxxxxxxxxxxxxxxxxxxxx1 //fetch 1st opcode (2)
+ `define INTA 32'bxxxxxx1xxxxxxxxxxxxxxxxxxxxxxxx1 //interrupt acknowledge (1)
+ `define INTB 32'bxxxxx1xxxxxxxxxxxxxxxxxxxxxxxxx1 //interrupt acknowledge (2)
+ `define HLTA 32'bxxxx1xxxxxxxxxxxxxxxxxxxxxxxxxx1 //halt & sleep (1)
+ `define HLTB 32'bxxx1xxxxxxxxxxxxxxxxxxxxxxxxxxx1 //halt & sleep (2)
+ `define DMA1 32'bxx1xxxxxxxxxxxxxxxxxxxxxxxxxxxx1 //dma transfer (1)
+ `define DMA2 32'bx1xxxxxxxxxxxxxxxxxxxxxxxxxxxxx1 //dma transfer (2)
+ `define RSTE 32'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1 //reset exit
+
+
+
+
+
+
+
+
Index: tags/ez80-instructions/rtl/control.v
===================================================================
--- tags/ez80-instructions/rtl/control.v (nonexistent)
+++ tags/ez80-instructions/rtl/control.v (revision 9)
@@ -0,0 +1,5232 @@
+/*******************************************************************************************/
+/** **/
+/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
+/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
+/** **/
+/** control module Rev 0.0 06/18/2012 **/
+/** **/
+/*******************************************************************************************/
+module control (add_sel, alua_sel, alub_sel, aluop_sel, cflg_en, di_ctl, do_ctl, ex_af_pls,
+ ex_bank_pls, ex_dehl_inst, halt_nxt, hflg_ctl, ief_ctl, if_frst, inta_frst,
+ imd_ctl, ld_dmaa, ld_inst, ld_inta, ld_page, ld_wait, nflg_ctl, output_inh,
+ page_sel, pc_sel, pflg_ctl, rd_frst, rd_nxt, reti_nxt, rreg_en, sflg_en, state_nxt,
+ tflg_ctl, tran_sel, wr_addr, wr_frst, zflg_en, carry_bit, dmar_reg, inst_reg,
+ intr_reg, page_reg, par_bit, sign_bit, state_reg, tflg_reg, vector_int,
+ xhlt_reg, zero_bit, int_req);
+
+ input carry_bit; /* carry flag */
+ input dmar_reg; /* latched dma request */
+ input intr_reg; /* latched interrupt request */
+ input int_req; /* interrupt request (for SLP) */
+ input par_bit; /* parity flag */
+ input sign_bit; /* sign flag */
+ input tflg_reg; /* temporary flag */
+ input vector_int; /* int vector enable */
+ input xhlt_reg; /* halt exit */
+ input zero_bit; /* zero flag */
+ input [3:0] page_reg; /* instruction decode "page" */
+ input [7:0] inst_reg; /* instruction register */
+ input [`STATE_IDX:0] state_reg; /* current processor state */
+ output cflg_en; /* carry flag control */
+ output ex_af_pls; /* exchange af,af' */
+ output ex_bank_pls; /* exchange register bank */
+ output ex_dehl_inst; /* exchange de,hl */
+ output halt_nxt; /* halt cycle next */
+ output if_frst; /* ifetch first cycle */
+ output inta_frst; /* intack first cycle */
+ output ld_dmaa; /* load dma request */
+ output ld_inst; /* load instruction register */
+ output ld_inta; /* load interrupt request */
+ output ld_page; /* load page register */
+ output ld_wait; /* load wait request */
+ output output_inh; /* disable cpu outputs */
+ output rd_frst; /* read first cycle */
+ output rd_nxt; /* read cycle identifier */
+ output reti_nxt; /* reti identifier */
+ output rreg_en; /* update refresh register */
+ output sflg_en; /* sign flag control */
+ output wr_frst; /* write first cycle */
+ output zflg_en; /* zero flag control */
+ output [3:0] page_sel; /* instruction decode "page" control */
+ output [`ADCTL_IDX:0] add_sel; /* address output mux control */
+ output [`ALUA_IDX:0] alua_sel; /* alu input a mux control */
+ output [`ALUB_IDX:0] alub_sel; /* alu input b mux control */
+ output [`ALUOP_IDX:0] aluop_sel; /* alu operation control */
+ output [`DI_IDX:0] di_ctl; /* data input control */
+ output [`DO_IDX:0] do_ctl; /* data output control */
+ output [`HFLG_IDX:0] hflg_ctl; /* half-carry flag control */
+ output [`IEF_IDX:0] ief_ctl; /* interrupt enable control */
+ output [`IMD_IDX:0] imd_ctl; /* interrupt mode control */
+ output [`NFLG_IDX:0] nflg_ctl; /* negate flag control */
+ output [`PCCTL_IDX:0] pc_sel; /* program counter source control */
+ output [`PFLG_IDX:0] pflg_ctl; /* parity/overflow flag control */
+ output [`STATE_IDX:0] state_nxt; /* next processor state */
+ output [`TFLG_IDX:0] tflg_ctl; /* temp flag control */
+ output [`TTYPE_IDX:0] tran_sel; /* transaction type select */
+ output [`WREG_IDX:0] wr_addr; /* register write address bus */
+
+ /*****************************************************************************************/
+ /* */
+ /* signal declarations */
+ /* */
+ /*****************************************************************************************/
+ reg cflg_en; /* carry flag control */
+ reg ex_af_pls; /* exchange af,af' */
+ reg ex_bank_pls; /* exchange register bank */
+ reg ex_dehl_inst; /* exchange de,hl */
+ reg halt_nxt; /* halt transaction */
+ reg if_frst; /* first clock if ifetch */
+ reg inta_frst; /* first clock of intack */
+ reg ld_inst; /* load instruction register */
+ reg ld_inta; /* sample latched int */
+ reg ld_dmaa; /* sample latched dma */
+ reg ld_page; /* load page register */
+ reg ld_wait; /* sample wait input */
+ reg output_inh; /* disable cpu outputs */
+ reg rd_frst; /* first clock of read */
+ reg rd_nxt; /* read trans next */
+ reg reti_nxt; /* reti trans next */
+`ifdef RREG_EMU
+ reg rreg_en; /* update refresh register */
+`endif
+ reg sflg_en; /* sign flag control */
+ reg wr_frst; /* first clock of write */
+ reg zflg_en; /* zero flag control */
+ reg [3:0] page_sel; /* inst decode page control */
+ reg [`ADCTL_IDX:0] add_sel; /* address output mux control */
+ reg [`ALUA_IDX:0] alua_sel; /* alu input a mux control */
+ reg [`ALUB_IDX:0] alub_sel; /* alu input b mux control */
+ reg [`ALUOP_IDX:0] aluop_sel; /* alu operation control */
+ reg [`DI_IDX:0] di_ctl; /* data input control */
+ reg [`DO_IDX:0] do_ctl; /* data output control */
+ reg [`HFLG_IDX:0] hflg_ctl; /* half-carry flag control */
+ reg [`IEF_IDX:0] ief_ctl; /* interrupt enable control */
+ reg [`IMD_IDX:0] imd_ctl; /* interrupt mode control */
+ reg [`NFLG_IDX:0] nflg_ctl; /* negate flag control */
+ reg [`PCCTL_IDX:0] pc_sel; /* pc source control */
+ reg [`PFLG_IDX:0] pflg_ctl; /* parity/overflow flag control */
+ reg [`STATE_IDX:0] state_nxt; /* machine state */
+ reg [`TFLG_IDX:0] tflg_ctl; /* temp flag control */
+ reg [`TTYPE_IDX:0] tran_sel; /* transaction type */
+ reg [`WREG_IDX:0] wr_addr; /* register write address bus */
+
+ /*****************************************************************************************/
+ /* */
+ /* refresh register control */
+ /* */
+ /*****************************************************************************************/
+`ifdef RREG_EMU
+ always @ (inst_reg or page_reg or state_reg or dmar_reg) begin
+ casex (state_reg) //sysnopsys parallel_case
+ `IF1B,
+ `IF2B,
+ `IF3B: rreg_en = 1'b1;
+ `WR1B,
+ `WR2B: begin
+ casex ({page_reg, inst_reg}) //sysnopsys parallel_case
+ 12'b1xxx10111001,
+ 12'b1xxx10110001,
+ 12'b1xxx10111010,
+ 12'b1xxx10110010,
+ 12'b1xxx10111000,
+ 12'b1xxx10110000,
+ 12'b1xxx10111011,
+ 12'b1xxx10110011,
+ 12'b0001xxxxxxxx: rreg_en = 1'b1;
+ default: rreg_en = 1'b0;
+ endcase
+ end
+ default: rreg_en = 1'b0;
+ endcase
+ end
+`endif
+
+ /*****************************************************************************************/
+ /* */
+ /* exchange instruction control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg)
+ `IF1B: begin
+ case ({page_reg, inst_reg})
+ 12'b000000001000: ex_af_pls = 1'b1;
+ default: ex_af_pls = 1'b0;
+ endcase
+ end
+ default: ex_af_pls = 1'b0;
+ endcase
+ end
+
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg)
+ `IF1B: begin
+ case ({page_reg, inst_reg})
+ 12'b000011011001: ex_bank_pls = 1'b1;
+ default: ex_bank_pls = 1'b0;
+ endcase
+ end
+ default: ex_bank_pls = 1'b0;
+ endcase
+ end
+
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg)
+ `DEC1: begin
+ case (inst_reg)
+ 8'b11101011: ex_dehl_inst = 1'b1;
+ default: ex_dehl_inst = 1'b0;
+ endcase
+ end
+ default: ex_dehl_inst = 1'b0;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* interrupt control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg)
+ `IF1B: begin
+ casex ({page_reg, inst_reg})
+ 12'b000011110011: ief_ctl = `IEF_0;
+ 12'b000011111011: ief_ctl = `IEF_1;
+ 12'b0001xxxxxxxx: ief_ctl = `IEF_NMI;
+ 12'b1xxx01000101: ief_ctl = `IEF_RTN;
+ default: ief_ctl = `IEF_NUL;
+ endcase
+ end
+ default: ief_ctl = `IEF_NUL;
+ endcase
+ end
+
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg)
+ `IF1B: begin
+ casex ({page_reg, inst_reg})
+ 12'b1xxx01000110: imd_ctl = `IMD_0;
+ 12'b1xxx01010110: imd_ctl = `IMD_1;
+ 12'b1xxx01011110: imd_ctl = `IMD_2;
+ default: imd_ctl = `IMD_NUL;
+ endcase
+ end
+ default: imd_ctl = `IMD_NUL;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* identifiers to create timing signals */
+ /* */
+ /*****************************************************************************************/
+ always @ (state_reg) begin
+ casex (state_reg) //synopsys parallel_case
+ `DEC1,
+ `DEC2,
+ `OF2A,
+ `IF3A,
+ `IF1A: if_frst = 1'b1;
+ default: if_frst = 1'b0;
+ endcase
+ end
+
+ always @ (state_reg) begin
+ casex (state_reg) //synopsys parallel_case
+ `INTA,
+ `RSTE: inta_frst = 1'b1;
+ default: inta_frst = 1'b0;
+ endcase
+ end
+
+ always @ (inst_reg or page_reg or state_nxt) begin
+ casex (state_nxt) //synopsys parallel_case
+ `RD1A,
+ `RD2A: rd_nxt = 1'b1;
+ default: rd_nxt = 1'b0;
+ endcase
+ end
+
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg) //synopsys parallel_case
+ `RD1A,
+ `RD2A: rd_frst = 1'b1;
+ default: rd_frst = 1'b0;
+ endcase
+ end
+
+ always @ (state_reg) begin
+ casex (state_reg) //synopsys parallel_case
+ `WR1A,
+ `WR2A: wr_frst = 1'b1;
+ default: wr_frst = 1'b0;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* wait sample */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg or carry_bit or par_bit or
+ sign_bit or zero_bit) begin
+ casex (state_reg) //synopsys parallel_case
+ `DEC1: begin
+ casex (inst_reg) //synopsys parallel_case
+ 8'b00000010,
+ 8'b00001010,
+ 8'b00010010,
+ 8'b00011010,
+ 8'b00110100,
+ 8'b00110101,
+ 8'b011100xx,
+ 8'b0111010x,
+ 8'b01110111,
+ 8'b010xx110,
+ 8'b0110x110,
+ 8'b01111110,
+ 8'b10000110,
+ 8'b10001110,
+ 8'b10010110,
+ 8'b10011110,
+ 8'b10100110,
+ 8'b10101110,
+ 8'b10110110,
+ 8'b10111110,
+ 8'b11001001,
+ 8'b11100011,
+ 8'b11xx0001,
+ 8'b11xx0101,
+ 8'b11xxx111,
+ 8'b01110110,
+ 8'b11101001: ld_wait = 1'b0;
+ 8'b11000000: ld_wait = zero_bit;
+ 8'b11001000: ld_wait = !zero_bit;
+ 8'b11010000: ld_wait = carry_bit;
+ 8'b11011000: ld_wait = !carry_bit;
+ 8'b11100000: ld_wait = par_bit;
+ 8'b11101000: ld_wait = !par_bit;
+ 8'b11110000: ld_wait = sign_bit;
+ 8'b11111000: ld_wait = !sign_bit;
+ default: ld_wait = 1'b1;
+ endcase
+ end
+ `DEC2: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b0010xxxxx110,
+ 12'b010x11100001,
+ 12'b010x11100011,
+ 12'b010x11100101,
+ 12'b1xxx00xxx11x, //ld (hl),rr; ld (hl),ii; ld rr,(hl); ld ii,(hl)
+ 12'b1xxx0100x101,
+ 12'b1xxx0110x111,
+ 12'b1xxx01xxx00x,
+ 12'b1xxx01110110, //slp
+ 12'b1xxx100xx01x, //indm,indmr,inim,inimr, otdm,otdmr,otim,otimr
+ 12'b1xxx101xx0xx,
+ 12'b1xxx10xxx100, //ind2,ind2r,ini2,ini2r, outd2,otd2r,outi2,oti2r
+ 12'b1xxx1100x01x, //indrx,inirx, otdrx,otirx
+ 12'b010x11101001: ld_wait = 1'b0;
+ default: ld_wait = 1'b1;
+ endcase
+ end
+ `OF2A,
+ `IF3A,
+ `RD1A,
+ `RD2A,
+ `WR1A,
+ `WR2A,
+ `IF1A,
+ `INTA: ld_wait = 1'b1;
+ default: ld_wait = 1'b0;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* instruction register and page register control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg) //synopsys parallel_case
+ `IF2B,
+ `IF3B,
+ `IF1B: ld_inst = 1'b1;
+ default: ld_inst = 1'b0;
+ endcase
+ end
+
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg)
+ `DEC1: begin
+ case (inst_reg)
+ 8'b11001011: page_sel = `CB_PAGE;
+ 8'b11011101: page_sel = `DD_PAGE;
+ 8'b11101101: page_sel = `ED_PAGE;
+ 8'b11111101: page_sel = `FD_PAGE;
+ default: page_sel = `MAIN_PG;
+ endcase
+ end
+ `DEC2: begin
+ casex ({page_reg, inst_reg})
+ 12'bx10011001011: page_sel = `DDCB_PG;
+ 12'bx10111001011: page_sel = `FDCB_PG;
+ default: page_sel = `MAIN_PG;
+ endcase
+ end
+ `INTA: page_sel = `INTR_PG;
+ `DMA1: page_sel = `DMA_PG;
+ default: page_sel = `MAIN_PG;
+ endcase
+ end
+
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg) //synopsys parallel_case
+ `DEC1: ld_page = 1'b1;
+ `DEC2: begin
+ casex ({page_reg, inst_reg})
+ 12'bx10x11001011: ld_page = 1'b1;
+ default: ld_page = 1'b0;
+ endcase
+ end
+ `INTA,
+ `DMA1: ld_page = 1'b1;
+ default: ld_page = 1'b0;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* next state control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg or carry_bit or dmar_reg or intr_reg or
+ par_bit or sign_bit or tflg_reg or vector_int or xhlt_reg or zero_bit) begin
+ casex (state_reg) //synopsys parallel_case
+ `DEC1: begin
+ casex (inst_reg) //synopsys parallel_case
+ 8'b00000010,
+ 8'b00001010,
+ 8'b00010010,
+ 8'b00011010,
+ 8'b00110100,
+ 8'b00110101,
+ 8'b011100xx,
+ 8'b0111010x,
+ 8'b01110111,
+ 8'b010xx110,
+ 8'b0110x110,
+ 8'b01111110,
+ 8'b10000110,
+ 8'b10001110,
+ 8'b10010110,
+ 8'b10011110,
+ 8'b10100110,
+ 8'b10101110,
+ 8'b10110110,
+ 8'b10111110,
+ 8'b11001001,
+ 8'b11100011,
+ 8'b11xx0001,
+ 8'b11xx0101,
+ 8'b11xxx111: state_nxt = `sADR2;
+ 8'b11000000: state_nxt = ( !zero_bit) ? `sADR2 : `sIF1B;
+ 8'b11001000: state_nxt = ( zero_bit) ? `sADR2 : `sIF1B;
+ 8'b11010000: state_nxt = (!carry_bit) ? `sADR2 : `sIF1B;
+ 8'b11011000: state_nxt = ( carry_bit) ? `sADR2 : `sIF1B;
+ 8'b11100000: state_nxt = ( !par_bit) ? `sADR2 : `sIF1B;
+ 8'b11101000: state_nxt = ( par_bit) ? `sADR2 : `sIF1B;
+ 8'b11110000: state_nxt = ( !sign_bit) ? `sADR2 : `sIF1B;
+ 8'b11111000: state_nxt = ( sign_bit) ? `sADR2 : `sIF1B;
+ 8'b11001011,
+ 8'b11011101,
+ 8'b11101101,
+ 8'b11111101: state_nxt = `sIF2B;
+ 8'b00010000,
+ 8'b00011000,
+ 8'b00100010,
+ 8'b00101010,
+ 8'b00110010,
+ 8'b00111010,
+ 8'b001xx000,
+ 8'b00xx0001,
+ 8'b00xxx110,
+ 8'b11000011,
+ 8'b11000110,
+ 8'b11001101,
+ 8'b11001110,
+ 8'b11010011,
+ 8'b11010110,
+ 8'b11011011,
+ 8'b11011110,
+ 8'b11100110,
+ 8'b11101110,
+ 8'b11110110,
+ 8'b11111110,
+ 8'b11xxx010,
+ 8'b11xxx100: state_nxt = `sOF1B;
+ 8'b01110110,
+ 8'b11101001: state_nxt = `sPCO;
+ default: state_nxt = `sIF1B;
+ endcase
+ end
+ `IF2B: state_nxt = `sDEC2;
+ `DEC2: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b001000000110,
+ 12'b001000001110,
+ 12'b001000010110,
+ 12'b001000011110,
+ 12'b001000100110,
+ 12'b001000101110,
+ 12'b001000110110,
+ 12'b001000111110,
+ 12'b001001xxx110,
+ 12'b001010xxx110,
+ 12'b001011xxx110,
+ 12'b010011100001,
+ 12'b010011100011,
+ 12'b010011100101,
+ 12'b010111100001,
+ 12'b010111100011,
+ 12'b010111100101,
+ 12'b1xxx00110100,
+ 12'b1xxx00110110,
+ 12'b1xxx00110111,
+ 12'b1xxx00111110,
+ 12'b1xxx00111111,
+ 12'b1xxx00xx0111,
+ 12'b1xxx00xx1111,
+ 12'b1xxx01000101,
+ 12'b1xxx01001101,
+ 12'b1xxx01100111,
+ 12'b1xxx01101111,
+ 12'b1xxx01xxx000,
+ 12'b1xxx01xxx001,
+ 12'b1xxx10000010,
+ 12'b1xxx10000011,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001011,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10010011,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011011,
+ 12'b1xxx10011100,
+ 12'b1xxx10100000,
+ 12'b1xxx10100001,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10100100,
+ 12'b1xxx10101000,
+ 12'b1xxx10101001,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10101100,
+ 12'b1xxx10110000,
+ 12'b1xxx10110001,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111001,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: state_nxt = `sADR2;
+ 12'b001000000xxx,
+ 12'b001000001xxx,
+ 12'b001000010xxx,
+ 12'b001000011xxx,
+ 12'b001000100xxx,
+ 12'b001000101xxx,
+ 12'b001000110xxx,
+ 12'b001000111xxx,
+ 12'b001001xxxxxx,
+ 12'b001010xxxxxx,
+ 12'b001011xxxxxx,
+ 12'b010000100011,
+ 12'b010000100100,
+ 12'b010000100101,
+ 12'b010000101011,
+ 12'b010000101100,
+ 12'b010000101101,
+ 12'b010000xx1001,
+ 12'b01000110x0xx,12'b01000110x10x,12'b01000110x111,
+ 12'b0100010xx10x,12'b01000110x10x,12'b01000111110x,
+ 12'b010010000100,
+ 12'b010010000101,
+ 12'b010010001100,
+ 12'b010010001101,
+ 12'b010010010100,
+ 12'b010010010101,
+ 12'b010010011100,
+ 12'b010010011101,
+ 12'b010010100100,
+ 12'b010010100101,
+ 12'b010010101100,
+ 12'b010010101101,
+ 12'b010010110100,
+ 12'b010010110101,
+ 12'b010010111100,
+ 12'b010010111101,
+ 12'b010011111001,
+ 12'b010100100011,
+ 12'b010100100100,
+ 12'b010100100101,
+ 12'b010100101011,
+ 12'b010100101100,
+ 12'b010100101101,
+ 12'b010100xx1001,
+ 12'b01010110x0xx,12'b01010110x10x,12'b01010110x111,
+ 12'b0101010xx10x,12'b01010110x10x,12'b01010111110x,
+ 12'b010110000100,
+ 12'b010110000101,
+ 12'b010110001100,
+ 12'b010110001101,
+ 12'b010110010100,
+ 12'b010110010101,
+ 12'b010110011100,
+ 12'b010110011101,
+ 12'b010110100100,
+ 12'b010110100101,
+ 12'b010110101100,
+ 12'b010110101101,
+ 12'b010110110100,
+ 12'b010110110101,
+ 12'b010110111100,
+ 12'b010110111101,
+ 12'b010111111001,
+ 12'b1xxx00xxx100,
+ 12'b1xxx01000100,
+ 12'b1xxx01000110,
+ 12'b1xxx01000111,
+ 12'b1xxx01001111,
+ 12'b1xxx01010110,
+ 12'b1xxx01010111,
+ 12'b1xxx01011110,
+ 12'b1xxx01011111,
+ 12'b1xxx01xx1100,
+ 12'b1xxx01xx0010,
+ 12'b1xxx01xx1010: state_nxt = `sIF1B;
+ 12'b010011101001,
+ 12'b010111101001,
+ 12'b1xxx01110110: state_nxt = `sPCO;
+ default: state_nxt = `sOF1B;
+ endcase
+ end
+ `OF1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b0000000xx110,12'b00000010x110,12'b000000111110,
+ 12'b000011000110,
+ 12'b000011001110,
+ 12'b000011010110,
+ 12'b000011011110,
+ 12'b000011100110,
+ 12'b000011101110,
+ 12'b000011110110,
+ 12'b000011111110,
+ 12'b010000100110,
+ 12'b010000101110,
+ 12'b010100100110,
+ 12'b010100101110,
+ 12'b1xxx00110010,
+ 12'b1xxx00110011,
+ 12'b1xxx00xx0010,
+ 12'b1xxx00xx0011,
+ 12'b1xxx01010100,
+ 12'b1xxx01010101,
+ 12'b1xxx01100100: state_nxt = `sIF1A;
+ 12'b000000100000: state_nxt = ( !zero_bit) ? `sPCA : `sIF1A;
+ 12'b000000101000: state_nxt = ( zero_bit) ? `sPCA : `sIF1A;
+ 12'b000000110000: state_nxt = (!carry_bit) ? `sPCA : `sIF1A;
+ 12'b000000111000: state_nxt = ( carry_bit) ? `sPCA : `sIF1A;
+ 12'b011xxxxxxxxx: state_nxt = `sIF3A; //DD/FD + CB
+ 12'b000000100010,
+ 12'b000000101010,
+ 12'b000000110010,
+ 12'b000000111010,
+ 12'b000000xx0001,
+ 12'b000011000011,
+ 12'b000011001101,
+ 12'b000011xxx010,
+ 12'b000011xxx100,
+ 12'b010000100001,
+ 12'b010000100010,
+ 12'b010000101010,
+ 12'b010000110110,
+ 12'b010100100001,
+ 12'b010100100010,
+ 12'b010100101010,
+ 12'b010100110110,
+ 12'b1xxx01xx0011,
+ 12'b1xxx01xx1011: state_nxt = `sOF2A;
+ 12'b000000010000,
+ 12'b000000011000: state_nxt = `sPCA;
+ 12'b000000110110: state_nxt = `sWR2A;
+ default: state_nxt = `sADR1;
+ endcase
+ end
+ `OF2A: state_nxt = `sOF2B;
+ `OF2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000xx0001,
+ 12'b010000100001,
+ 12'b010100100001: state_nxt = `sIF1A;
+ 12'b000011000010: state_nxt = ( !zero_bit) ? `sPCA : `sIF1A;
+ 12'b000011001010: state_nxt = ( zero_bit) ? `sPCA : `sIF1A;
+ 12'b000011010010: state_nxt = (!carry_bit) ? `sPCA : `sIF1A;
+ 12'b000011011010: state_nxt = ( carry_bit) ? `sPCA : `sIF1A;
+ 12'b000011100010: state_nxt = ( !par_bit) ? `sPCA : `sIF1A;
+ 12'b000011101010: state_nxt = ( par_bit) ? `sPCA : `sIF1A;
+ 12'b000011110010: state_nxt = ( !sign_bit) ? `sPCA : `sIF1A;
+ 12'b000011111010: state_nxt = ( sign_bit) ? `sPCA : `sIF1A;
+ 12'b000011000100: state_nxt = ( !zero_bit) ? `sWR1A : `sIF1A;
+ 12'b000011001100: state_nxt = ( zero_bit) ? `sWR1A : `sIF1A;
+ 12'b000011010100: state_nxt = (!carry_bit) ? `sWR1A : `sIF1A;
+ 12'b000011011100: state_nxt = ( carry_bit) ? `sWR1A : `sIF1A;
+ 12'b000011100100: state_nxt = ( !par_bit) ? `sWR1A : `sIF1A;
+ 12'b000011101100: state_nxt = ( par_bit) ? `sWR1A : `sIF1A;
+ 12'b000011110100: state_nxt = ( !sign_bit) ? `sWR1A : `sIF1A;
+ 12'b000011111100: state_nxt = ( sign_bit) ? `sWR1A : `sIF1A;
+ 12'b000011000011: state_nxt = `sPCA;
+ 12'b000011001101: state_nxt = `sWR1A;
+ 12'b010000110110,
+ 12'b010100110110: state_nxt = `sWR2A;
+ default: state_nxt = `sADR1;
+ endcase
+ end
+ `IF3A: state_nxt = `sIF3B;
+ `IF3B: state_nxt = `sRD2A;
+ `ADR1: state_nxt = `sADR2;
+ `ADR2: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000101010,
+ 12'b000011001001,
+ 12'b000011100011,
+ 12'b000011xxx000,
+ 12'b000011xx0001,
+ 12'b0001xxxxxxxx,
+ 12'b010000101010,
+ 12'b010000110001,
+ 12'b010000110111,
+ 12'b010000xx0111,
+ 12'b010011100001,
+ 12'b010011100011,
+ 12'b010100101010,
+ 12'b010100110001,
+ 12'b010100110111,
+ 12'b010100xx0111,
+ 12'b010111100001,
+ 12'b010111100011,
+ 12'b1xxx00110110,
+ 12'b1xxx00110111,
+ 12'b1xxx00xx0111,
+ 12'b1xxx01000101,
+ 12'b1xxx01001101,
+ 12'b1xxx01xx1011,
+ 12'b1xxx10000010,
+ 12'b1xxx10000011,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001011,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10010011,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011011,
+ 12'b1xxx10011100,
+ 12'b1xxx10100000,
+ 12'b1xxx10100001,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10100100,
+ 12'b1xxx10101000,
+ 12'b1xxx10101001,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10101100,
+ 12'b1xxx10110000,
+ 12'b1xxx10110001,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111001,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: state_nxt = `sRD1A;
+ 12'b000000100010,
+ 12'b000011xxx111,
+ 12'b000011xx0101,
+ 12'b010000100010,
+ 12'b010000111110,
+ 12'b010000111111,
+ 12'b010000xx1111,
+ 12'b010011100101,
+ 12'b010100100010,
+ 12'b010100111110,
+ 12'b010100111111,
+ 12'b010100xx1111,
+ 12'b010111100101,
+ 12'b1xxx00111110,
+ 12'b1xxx00111111,
+ 12'b1xxx00xx1111,
+ 12'b1xxx01100101,
+ 12'b1xxx01100110,
+ 12'b1xxx01xx0011: state_nxt = `sWR1A;
+ 12'b000000000010,
+ 12'b000000010010,
+ 12'b000000110010,
+ 12'b000001110xxx,
+ 12'b000011010011,
+ 12'b010001110xxx,
+ 12'b010101110xxx,
+ 12'b1xxx00xxx001,
+ 12'b1xxx01xxx001: state_nxt = `sWR2A;
+ default: state_nxt = `sRD2A;
+ endcase
+ end
+ `RD1A: state_nxt = `sRD1B;
+ `RD1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100001,
+ 12'b1xxx10101001,
+ 12'b1xxx10110001,
+ 12'b1xxx10111001: state_nxt = `sBLK1;
+ 12'b1xxx10000010,
+ 12'b1xxx10000011,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001011,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10010011,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011011,
+ 12'b1xxx10011100,
+ 12'b1xxx10100000,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10100100,
+ 12'b1xxx10101000,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10101100,
+ 12'b1xxx10110000,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: state_nxt = `sWR1A;
+ default: state_nxt = `sRD2A;
+ endcase
+ end
+ `RD2A: state_nxt = `sRD2B;
+ `RD2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100001,
+ 12'b1xxx10101001,
+ 12'b1xxx10110001,
+ 12'b1xxx10111001: state_nxt = `sBLK1;
+ 12'b000000001010,
+ 12'b000000011010,
+ 12'b000000101010,
+ 12'b000000111010,
+ 12'b000001xxxxxx,
+ 12'b000001xxx110,
+ 12'b000010000110,
+ 12'b000010000xxx,
+ 12'b000010001110,
+ 12'b000010001xxx,
+ 12'b000010010110,
+ 12'b000010011110,
+ 12'b000010100110,
+ 12'b000010100xxx,
+ 12'b000010101110,
+ 12'b000010110110,
+ 12'b000010110xxx,
+ 12'b000010111110,
+ 12'b000010111xxx,
+ 12'b000011011011,
+ 12'b000011xx0001,
+ 12'b001001xxx110,
+ 12'b001001xxxxxx,
+ 12'b010000101010,
+ 12'b010000110001,
+ 12'b010000110111,
+ 12'b010000xx0111,
+ 12'b010001xxx110,
+ 12'b010010000110,
+ 12'b010010001110,
+ 12'b010010010110,
+ 12'b010010011110,
+ 12'b010010100110,
+ 12'b010010101110,
+ 12'b010010110110,
+ 12'b010010111110,
+ 12'b010011100001,
+ 12'b010100101010,
+ 12'b010100110001,
+ 12'b010100110111,
+ 12'b010100xx0111,
+ 12'b010101xxx110,
+ 12'b010110000110,
+ 12'b010110001110,
+ 12'b010110010110,
+ 12'b010110011110,
+ 12'b010110100110,
+ 12'b010110101110,
+ 12'b010110110110,
+ 12'b010110111110,
+ 12'b010111100001,
+ 12'b011001xxx110,
+ 12'b011101xxx110,
+ 12'b1xxx00110100,
+ 12'b1xxx00110110,
+ 12'b1xxx00110111,
+ 12'b1xxx00xx0111,
+ 12'b1xxx00xxx000,
+ 12'b1xxx00xxx100,
+ 12'b1xxx01110100,
+ 12'b1xxx01xxx000,
+ 12'b1xxx01xx1011: state_nxt = `sIF1A;
+ 12'b000011001001,
+ 12'b000011xxx000,
+ 12'b1xxx01000101,
+ 12'b1xxx01001101: state_nxt = `sPCA;
+ 12'b000011100011,
+ 12'b0001xxxxxxxx,
+ 12'b010011100011,
+ 12'b010111100011: state_nxt = `sWR1A;
+ default: state_nxt = `sWR2A;
+ endcase
+ end
+ `WR1A: state_nxt = `sWR1B;
+ `WR1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10000010,
+ 12'b1xxx10000011,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001011,
+ 12'b1xxx10001100,
+ 12'b1xxx10100000,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10100100,
+ 12'b1xxx10101000,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10101100: state_nxt = `sIF1A;
+ 12'b1xxx10010010,
+ 12'b1xxx10010011,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011011,
+ 12'b1xxx10011100,
+ 12'b1xxx10110000,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: state_nxt = (tflg_reg || intr_reg || dmar_reg) ? `sPCA : `sRD2A;
+ default: state_nxt = `sWR2A;
+ endcase
+ end
+ `WR2A: state_nxt = `sWR2B;
+ `WR2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10010010,
+ 12'b1xxx10010011,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011011,
+ 12'b1xxx10011100,
+ 12'b1xxx10100000,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10101000,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10110000,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: state_nxt = (tflg_reg || intr_reg || dmar_reg) ? `sPCA : `sRD2A;
+ default: state_nxt = `sIF1A;
+ endcase
+ end
+ `BLK1: state_nxt = `sBLK2;
+ `BLK2: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10110001,
+ 12'b1xxx10111001: state_nxt = (tflg_reg || intr_reg || dmar_reg) ? `sPCA : `sRD2A;
+ default: state_nxt = `sIF1A;
+ endcase
+ end
+ `PCA: state_nxt = `sPCO;
+ `PCO: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000001110110,
+ 12'b1xxx01110110: state_nxt = `sHLTA;
+ default: state_nxt = `sIF1A;
+ endcase
+ end
+ `HLTA: state_nxt = `sHLTB;
+ `HLTB: state_nxt = (xhlt_reg || (int_req && page_reg[3])) ? `sIF1A : `sHLTA;
+ `IF1A: state_nxt = `sIF1B;
+ `IF1B: state_nxt = `sDEC1;
+ `INTA: state_nxt = `sINTB;
+ `INTB: state_nxt = (vector_int) ? `sADR1 : `sWR1A;
+ `DMA1: state_nxt = `sDMA2;
+ `DMA2: state_nxt = (dmar_reg) ? `sDMA1 : `sIF1A;
+ `RSTE: state_nxt = `sIF1A;
+ default: state_nxt = `sRSTE;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* transaction type control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg or carry_bit or dmar_reg or intr_reg or
+ par_bit or sign_bit or tflg_reg or vector_int or xhlt_reg or zero_bit) begin
+ casex (state_reg) //synopsys parallel_case
+ `IF2B: tran_sel = `TRAN_IF;
+ `OF1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000010000,
+ 12'b000000011000,
+ 12'b000011010011,
+ 12'b000011011011,
+ 12'b010000110001,
+ 12'b010000110100,
+ 12'b010000110101,
+ 12'b010000110111,
+ 12'b010000111110,
+ 12'b010000111111,
+ 12'b010000xx0111,
+ 12'b010000xx1111,
+ 12'b010001110xxx,
+ 12'b010001xxx110,
+ 12'b010010000110,
+ 12'b010010001110,
+ 12'b010010010110,
+ 12'b010010011110,
+ 12'b010010100110,
+ 12'b010010101110,
+ 12'b010010110110,
+ 12'b010010111110,
+ 12'b010100110001,
+ 12'b010100110100,
+ 12'b010100110101,
+ 12'b010100110111,
+ 12'b010100111110,
+ 12'b010100111111,
+ 12'b010100xx0111,
+ 12'b010100xx1111,
+ 12'b010101110xxx,
+ 12'b010101xxx110,
+ 12'b010110000110,
+ 12'b010110001110,
+ 12'b010110010110,
+ 12'b010110011110,
+ 12'b010110100110,
+ 12'b010110101110,
+ 12'b010110110110,
+ 12'b010110111110,
+ 12'b1xxx00110010,
+ 12'b1xxx00110011,
+ 12'b1xxx00xx0010,
+ 12'b1xxx00xx0011,
+ 12'b1xxx01010100,
+ 12'b1xxx01010101,
+ 12'b1xxx01100101,
+ 12'b1xxx01100110: tran_sel = `TRAN_IDL;
+ 12'b000000100000: tran_sel = ( zero_bit) ? `TRAN_IF : `TRAN_IDL;
+ 12'b000000101000: tran_sel = ( !zero_bit) ? `TRAN_IF : `TRAN_IDL;
+ 12'b000000110000: tran_sel = ( carry_bit) ? `TRAN_IF : `TRAN_IDL;
+ 12'b000000111000: tran_sel = (!carry_bit) ? `TRAN_IF : `TRAN_IDL;
+ 12'b000000110110: tran_sel = `TRAN_MEM;
+ default: tran_sel = `TRAN_IF;
+ endcase
+ end
+ `OF2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000xx0001,
+ 12'b010000100001,
+ 12'b010100100001: tran_sel = `TRAN_IF;
+ 12'b010000110110,
+ 12'b010100110110: tran_sel = `TRAN_MEM;
+ 12'b000011001101: tran_sel = `TRAN_STK;
+ 12'b000011000010: tran_sel = ( !zero_bit) ? `TRAN_IDL : `TRAN_IF;
+ 12'b000011001010: tran_sel = ( zero_bit) ? `TRAN_IDL : `TRAN_IF;
+ 12'b000011010010: tran_sel = (!carry_bit) ? `TRAN_IDL : `TRAN_IF;
+ 12'b000011011010: tran_sel = ( carry_bit) ? `TRAN_IDL : `TRAN_IF;
+ 12'b000011100010: tran_sel = ( !par_bit) ? `TRAN_IDL : `TRAN_IF;
+ 12'b000011101010: tran_sel = ( par_bit) ? `TRAN_IDL : `TRAN_IF;
+ 12'b000011110010: tran_sel = ( !sign_bit) ? `TRAN_IDL : `TRAN_IF;
+ 12'b000011111010: tran_sel = ( sign_bit) ? `TRAN_IDL : `TRAN_IF;
+ 12'b000011000100: tran_sel = ( !zero_bit) ? `TRAN_STK : `TRAN_IF;
+ 12'b000011001100: tran_sel = ( zero_bit) ? `TRAN_STK : `TRAN_IF;
+ 12'b000011010100: tran_sel = (!carry_bit) ? `TRAN_STK : `TRAN_IF;
+ 12'b000011011100: tran_sel = ( carry_bit) ? `TRAN_STK : `TRAN_IF;
+ 12'b000011100100: tran_sel = ( !par_bit) ? `TRAN_STK : `TRAN_IF;
+ 12'b000011101100: tran_sel = ( par_bit) ? `TRAN_STK : `TRAN_IF;
+ 12'b000011110100: tran_sel = ( !sign_bit) ? `TRAN_STK : `TRAN_IF;
+ 12'b000011111100: tran_sel = ( sign_bit) ? `TRAN_STK : `TRAN_IF;
+ default: tran_sel = `TRAN_IDL;
+ endcase
+ end
+ `IF3B: tran_sel = `TRAN_MEM;
+ `ADR2: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000011010011,
+ 12'b000011011011,
+ 12'b1xxx00xxx000,
+ 12'b1xxx00xxx001,
+ 12'b1xxx01110100,
+ 12'b1xxx01xxx000,
+ 12'b1xxx01xxx001,
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011100,
+ 12'b1xxx10100010,
+ 12'b1xxx10101010,
+ 12'b1xxx10110010,
+ 12'b1xxx10111010,
+ 12'b1xxx11000010,
+ 12'b1xxx11001010: tran_sel = `TRAN_IO;
+ 12'b000011001001,
+ 12'b000011xxx000,
+ 12'b000011xxx111,
+ 12'b000011xx0001,
+ 12'b000011xx0101,
+ 12'b010011100001,
+ 12'b010011100101,
+ 12'b010111100001,
+ 12'b010111100101,
+ 12'b1xxx01000101,
+ 12'b1xxx01001101,
+ 12'b1xxx01100101,
+ 12'b1xxx01100110: tran_sel = `TRAN_STK;
+ default: tran_sel = `TRAN_MEM;
+ endcase
+ end
+ `RD1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100001,
+ 12'b1xxx10101001,
+ 12'b1xxx10110001,
+ 12'b1xxx10111001: tran_sel = `TRAN_IDL;
+ 12'b1xxx10000011,
+ 12'b1xxx10001011,
+ 12'b1xxx10010011,
+ 12'b1xxx10011011,
+ 12'b1xxx10100011,
+ 12'b1xxx10100100,
+ 12'b1xxx10101011,
+ 12'b1xxx10101100,
+ 12'b1xxx10110011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11000011,
+ 12'b1xxx11001011: tran_sel = `TRAN_IO;
+ 12'b000011001001,
+ 12'b000011xxx000,
+ 12'b000011xx0001,
+ 12'b010011100001,
+ 12'b010111100001,
+ 12'b1xxx01000101,
+ 12'b1xxx01001101: tran_sel = `TRAN_STK;
+ default: tran_sel = `TRAN_MEM;
+ endcase
+ end
+ `RD2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000011001001,
+ 12'b000011xxx000,
+ 12'b1xxx01000101,
+ 12'b1xxx01001101,
+ 12'b1xxx10100001,
+ 12'b1xxx10101001,
+ 12'b1xxx10110001,
+ 12'b1xxx10111001: tran_sel = `TRAN_IDL;
+ 12'b000000001010,
+ 12'b000000011010,
+ 12'b000000101010,
+ 12'b000000111010,
+ 12'b000001xxx110,
+ 12'b000010000110,
+ 12'b000010001110,
+ 12'b000010010110,
+ 12'b000010011110,
+ 12'b000010100110,
+ 12'b000010101110,
+ 12'b000010110110,
+ 12'b000010111110,
+ 12'b000011011011,
+ 12'b000011xx0001,
+ 12'b001001xxx110,
+ 12'b010000101010,
+ 12'b010000110001,
+ 12'b010000110111,
+ 12'b010000xx0111,
+ 12'b010001xxx110,
+ 12'b010010000110,
+ 12'b010010001110,
+ 12'b010010010110,
+ 12'b010010011110,
+ 12'b010010100110,
+ 12'b010010101110,
+ 12'b010010110110,
+ 12'b010010111110,
+ 12'b010011100001,
+ 12'b010100101010,
+ 12'b010100110001,
+ 12'b010100110111,
+ 12'b010100xx0111,
+ 12'b010101xxx110,
+ 12'b010110000110,
+ 12'b010110001110,
+ 12'b010110010110,
+ 12'b010110011110,
+ 12'b010110100110,
+ 12'b010110101110,
+ 12'b010110110110,
+ 12'b010110111110,
+ 12'b010111100001,
+ 12'b011001xxx110,
+ 12'b011101xxx110,
+ 12'b1xxx00110100,
+ 12'b1xxx00110110,
+ 12'b1xxx00110111,
+ 12'b1xxx00xx0111,
+ 12'b1xxx00xxx000,
+ 12'b1xxx01xxx000,
+ 12'b1xxx01xx1011: tran_sel = `TRAN_IF;
+ 12'b1xxx10000011,
+ 12'b1xxx10001011,
+ 12'b1xxx10010011,
+ 12'b1xxx10011011,
+ 12'b1xxx10100011,
+ 12'b1xxx10100100,
+ 12'b1xxx10101011,
+ 12'b1xxx10101100,
+ 12'b1xxx10110011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11000011,
+ 12'b1xxx11001011: tran_sel = `TRAN_IO;
+ 12'b000011100011,
+ 12'b0001xxxxxxxx,
+ 12'b010011100011,
+ 12'b010111100011: tran_sel = `TRAN_STK;
+ default: tran_sel = `TRAN_MEM;
+ endcase
+ end
+ `WR1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10010010,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011100,
+ 12'b1xxx10110010,
+ 12'b1xxx10111010,
+ 12'b1xxx11000010,
+ 12'b1xxx11001010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
+ 12'b1xxx10010011,
+ 12'b1xxx10011011,
+ 12'b1xxx10110000,
+ 12'b1xxx10110011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11000011,
+ 12'b1xxx11001011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
+ 12'b000000100010,
+ 12'b010000100010,
+ 12'b010000111110,
+ 12'b010000111111,
+ 12'b010000xx1111,
+ 12'b010100100010,
+ 12'b010100111110,
+ 12'b010100111111,
+ 12'b010100xx1111,
+ 12'b1xxx00111110,
+ 12'b1xxx00111111,
+ 12'b1xxx00xx1111,
+ 12'b1xxx01xx0011: tran_sel = `TRAN_MEM;
+ 12'b000011001101,
+ 12'b000011100011,
+ 12'b000011xxx100,
+ 12'b000011xxx111,
+ 12'b000011xx0101,
+ 12'b0001xxxxxxxx,
+ 12'b010011100011,
+ 12'b010011100101,
+ 12'b010111100011,
+ 12'b010111100101,
+ 12'b1xxx01100101,
+ 12'b1xxx01100110: tran_sel = `TRAN_STK;
+ default: tran_sel = `TRAN_IF;
+ endcase
+ end
+ `WR2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10010010,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011100,
+ 12'b1xxx10110010,
+ 12'b1xxx11000010,
+ 12'b1xxx11001010,
+ 12'b1xxx10111010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
+ 12'b1xxx10010011,
+ 12'b1xxx10011011,
+ 12'b1xxx10110000,
+ 12'b1xxx10110011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11000011,
+ 12'b1xxx11001011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
+ default: tran_sel = `TRAN_IF;
+ endcase
+ end
+ `BLK2: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10110001,
+ 12'b1xxx10111001: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
+ default: tran_sel = `TRAN_IF;
+ endcase
+ end
+ `PCO: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000001110110,
+ 12'b1xxx01110110: tran_sel = `TRAN_IDL;
+ default: tran_sel = `TRAN_IF;
+ endcase
+ end
+ `IF1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx01000101,
+ 12'b1xxx01001101,
+ 12'b000011110011,
+ 12'b0001xxxxxxxx: tran_sel = `TRAN_IF;
+ default: tran_sel = (dmar_reg) ? `TRAN_IDL :
+ (intr_reg) ? `TRAN_IAK : `TRAN_IF;
+ endcase
+ end
+ `HLTB: tran_sel = (xhlt_reg || (page_reg[3] && int_req)) ? `TRAN_IF : `TRAN_IDL;
+ `INTB: tran_sel = (vector_int) ? `TRAN_IDL : `TRAN_MEM;
+ `DMA2: tran_sel = (dmar_reg) ? `TRAN_IDL : `TRAN_IF;
+ `RSTE: tran_sel = `TRAN_IF;
+ default: tran_sel = `TRAN_RSTVAL;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* special transaction identifiers */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg or xhlt_reg) begin
+ casex (state_reg)
+ `PCO,
+ `HLTB: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000001110110: halt_nxt = !xhlt_reg;
+ 12'b1xxx01110110: halt_nxt = !int_req;
+ default: halt_nxt = 1'b0;
+ endcase
+ end
+ default: halt_nxt = 1'b0;
+ endcase
+ end
+
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg)
+ `RD2B: begin
+ casex ({page_reg, inst_reg})
+ 12'b1xxx01001101: reti_nxt = 1'b1;
+ default: reti_nxt = 1'b0;
+ endcase
+ end
+ default: reti_nxt = 1'b0;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* output inhibit */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg or dmar_reg or xhlt_reg) begin
+ casex (state_reg)
+ `IF1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx01000101,
+ 12'b1xxx01001101,
+ 12'b000011110011,
+ 12'b0001xxxxxxxx: output_inh = 1'b0;
+ default: output_inh = dmar_reg;
+ endcase
+ end
+ `DMA2: output_inh = dmar_reg;
+ `PCO,
+ `HLTB: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000001110110: output_inh = !xhlt_reg;
+ 12'b1xxx01110110: output_inh = !int_req;
+ default: output_inh = 1'b0;
+ endcase
+ end
+ default: output_inh = 1'b0;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* address output control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg or carry_bit or par_bit or sign_bit or
+ vector_int or zero_bit) begin
+ casex (state_reg) //synopsys parallel_case
+ `DEC1: begin
+ casex (inst_reg) //synopsys parallel_case
+ 8'b00000010,
+ 8'b00001010,
+ 8'b00010010,
+ 8'b00011010,
+ 8'b11101001,
+ 8'b11xx0101,
+ 8'b11xxx111: add_sel = `ADD_ALU;
+ 8'b00110100,
+ 8'b00110101,
+ 8'b00110110,
+ 8'b011100xx,
+ 8'b0111010x,
+ 8'b01110111,
+ 8'b010xx110,
+ 8'b0110x110,
+ 8'b01111110,
+ 8'b10000110,
+ 8'b10001110,
+ 8'b10010110,
+ 8'b10011110,
+ 8'b10100110,
+ 8'b10101110,
+ 8'b10110110,
+ 8'b10111110: add_sel = `ADD_HL;
+ 8'b11000000: add_sel = ( !zero_bit) ? `ADD_SP : `ADD_PC;
+ 8'b11001000: add_sel = ( zero_bit) ? `ADD_SP : `ADD_PC;
+ 8'b11010000: add_sel = (!carry_bit) ? `ADD_SP : `ADD_PC;
+ 8'b11011000: add_sel = ( carry_bit) ? `ADD_SP : `ADD_PC;
+ 8'b11100000: add_sel = ( !par_bit) ? `ADD_SP : `ADD_PC;
+ 8'b11101000: add_sel = ( par_bit) ? `ADD_SP : `ADD_PC;
+ 8'b11110000: add_sel = ( !sign_bit) ? `ADD_SP : `ADD_PC;
+ 8'b11111000: add_sel = ( sign_bit) ? `ADD_SP : `ADD_PC;
+ 8'b11xx0001,
+ 8'b11100011,
+ 8'b11001001: add_sel = `ADD_SP;
+ default: add_sel = `ADD_PC;
+ endcase
+ end
+ `DEC2: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b010011100101,
+ 12'b010011101001,
+ 12'b010111100101,
+ 12'b010111101001,
+ 12'b1xxx01xxx000,
+ 12'b1xxx01xxx001,
+ 12'b1xxx10000011,
+ 12'b1xxx10000100,
+ 12'b1xxx10001011,
+ 12'b1xxx10001100,
+ 12'b1xxx10010011,
+ 12'b1xxx10010100,
+ 12'b1xxx10011011,
+ 12'b1xxx10011100,
+ 12'b1xxx10100000,
+ 12'b1xxx10100001,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10101000,
+ 12'b1xxx10101001,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10110000,
+ 12'b1xxx10110001,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111001,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: add_sel = `ADD_ALU;
+ 12'b1xxx10000010,
+ 12'b1xxx10001010,
+ 12'b1xxx10010010,
+ 12'b1xxx10011010: add_sel = `ADD_ALU8;
+ 12'b001000000110,
+ 12'b001000001110,
+ 12'b001000010110,
+ 12'b001000011110,
+ 12'b001000100110,
+ 12'b001000101110,
+ 12'b001000110110,
+ 12'b001000111110,
+ 12'b001001xxx110,
+ 12'b001010xxx110,
+ 12'b001011xxx110,
+ 12'b1xxx10100100,
+ 12'b1xxx10101100,
+ 12'b1xxx00110100,
+ 12'b1xxx00110110,
+ 12'b1xxx00110111,
+ 12'b1xxx00111110,
+ 12'b1xxx00111111,
+ 12'b1xxx00xx0111,
+ 12'b1xxx00xx1111,
+ 12'b1xxx01100111,
+ 12'b1xxx01101111: add_sel = `ADD_HL;
+ 12'b010011100001,
+ 12'b010011100011,
+ 12'b010111100001,
+ 12'b010111100011,
+ 12'b1xxx01000101,
+ 12'b1xxx01001101: add_sel = `ADD_SP;
+ default: add_sel = `ADD_PC;
+ endcase
+ end
+ `OF2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000011001101,
+ 12'b010000110110,
+ 12'b010100110110: add_sel = `ADD_ALU;
+ 12'b000011000100: add_sel = ( !zero_bit) ? `ADD_ALU : `ADD_PC;
+ 12'b000011001100: add_sel = ( zero_bit) ? `ADD_ALU : `ADD_PC;
+ 12'b000011010100: add_sel = (!carry_bit) ? `ADD_ALU : `ADD_PC;
+ 12'b000011011100: add_sel = ( carry_bit) ? `ADD_ALU : `ADD_PC;
+ 12'b000011100100: add_sel = ( !par_bit) ? `ADD_ALU : `ADD_PC;
+ 12'b000011101100: add_sel = ( par_bit) ? `ADD_ALU : `ADD_PC;
+ 12'b000011110100: add_sel = ( !sign_bit) ? `ADD_ALU : `ADD_PC;
+ 12'b000011111100: add_sel = ( sign_bit) ? `ADD_ALU : `ADD_PC;
+ default: add_sel = `ADD_PC;
+ endcase
+ end
+ `IF3A: add_sel = `ADD_ALU;
+ `ADR1: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx01110100,
+ 12'b1xxx00xxx000,
+ 12'b1xxx00xxx001: add_sel = `ADD_ALU8;
+ default: add_sel = `ADD_ALU;
+ endcase
+ end
+ `RD1A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx100xx011: add_sel = `ADD_ALU8;
+ default: add_sel = `ADD_ALU;
+ endcase
+ end
+ `RD2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000011100011,
+ 12'b0001xxxxxxxx,
+ 12'b010000110100,
+ 12'b010000110101,
+ 12'b010011100011,
+ 12'b010100110100,
+ 12'b010100110101,
+ 12'b010111100011,
+ 12'b011000000110,
+ 12'b011000001110,
+ 12'b011000010110,
+ 12'b011000011110,
+ 12'b011000100110,
+ 12'b011000101110,
+ 12'b011000110110,
+ 12'b011000111110,
+ 12'b011010xxx110,
+ 12'b011011xxx110,
+ 12'b011100000110,
+ 12'b011100001110,
+ 12'b011100010110,
+ 12'b011100011110,
+ 12'b011100100110,
+ 12'b011100101110,
+ 12'b011100110110,
+ 12'b011100111110,
+ 12'b011110xxx110,
+ 12'b011111xxx110,
+ 12'b1xxx10000010,
+ 12'b1xxx10001010,
+ 12'b1xxx10010010,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011100,
+ 12'b1xxx10100000,
+ 12'b1xxx10100001,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10101000,
+ 12'b1xxx10101001,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10110000,
+ 12'b1xxx10110001,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111001,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: add_sel = `ADD_ALU;
+ 12'b1xxx100xx011: add_sel = `ADD_ALU8;
+ 12'b000000110100,
+ 12'b000000110101,
+ 12'b000000xxx100,
+ 12'b000000xxx101,
+ 12'b001000000110,
+ 12'b001000000xxx,
+ 12'b001000001110,
+ 12'b001000001xxx,
+ 12'b001000010110,
+ 12'b001000010xxx,
+ 12'b001000011110,
+ 12'b001000011xxx,
+ 12'b001000100110,
+ 12'b001000100xxx,
+ 12'b001000101110,
+ 12'b001000101xxx,
+ 12'b001000110110,
+ 12'b001000110xxx,
+ 12'b001000111110,
+ 12'b001000111xxx,
+ 12'b001010xxx110,
+ 12'b001010xxxxxx,
+ 12'b001011xxx110,
+ 12'b001011xxxxxx,
+ 12'b1xxx01100111,
+ 12'b1xxx01101111: add_sel = `ADD_HL;
+ default: add_sel = `ADD_PC;
+ endcase
+ end
+ `WR1A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10010010,
+ 12'b1xxx10011010: add_sel = `ADD_ALU8;
+ 12'b1xxx10000010,
+ 12'b1xxx10000011,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001011,
+ 12'b1xxx10001100,
+ 12'b1xxx10100000,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10100100,
+ 12'b1xxx10101000,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10101100: add_sel = `ADD_PC;
+ default: add_sel = `ADD_ALU;
+ endcase
+ end
+ `WR2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000011001101,
+ 12'b000011xxx100,
+ 12'b000011xxx111,
+ 12'b0001xxxxxxxx,
+ 12'b1xxx10000011,
+ 12'b1xxx10001011,
+ 12'b1xxx10010011,
+ 12'b1xxx10010100,
+ 12'b1xxx10011011,
+ 12'b1xxx10011100,
+ 12'b1xxx10100000,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10101000,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10110000,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: add_sel = `ADD_ALU;
+ 12'b1xxx10000010,
+ 12'b1xxx10001010,
+ 12'b1xxx10010010,
+ 12'b1xxx10011010: add_sel = `ADD_ALU8;
+ default: add_sel = `ADD_PC;
+ endcase
+ end
+ `BLK1: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10110001,
+ 12'b1xxx10111001: add_sel = `ADD_ALU;
+ default: add_sel = `ADD_PC;
+ endcase
+ end
+ `PCA: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000010000,
+ 12'b000000011000,
+ 12'b0000001xx000,
+ 12'b000011000011,
+ 12'b000011001001,
+ 12'b000011xxx000,
+ 12'b000011xxx010,
+ 12'b1xxx01000101,
+ 12'b1xxx01001101: add_sel = `ADD_PC;
+ default: add_sel = `ADD_ALU;
+ endcase
+ end
+ `IF1A: add_sel = `ADD_PC;
+ `INTA: add_sel = (vector_int) ? `ADD_PC : `ADD_ALU;
+ `HLTA: add_sel = `ADD_PC;
+ `DMA1: add_sel = `ADD_PC;
+ default: add_sel = `ADD_RSTVAL;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* program counter control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg or carry_bit or par_bit or sign_bit or
+ tflg_reg or zero_bit) begin
+ casex (state_reg) //synopsys parallel_case
+ `DEC1: begin
+ casex (inst_reg) //synopsys parallel_case
+ 8'b00000000,
+ 8'b00000111,
+ 8'b00001000,
+ 8'b00001111,
+ 8'b00010111,
+ 8'b00011111,
+ 8'b00100111,
+ 8'b00101111,
+ 8'b00110111,
+ 8'b00111111,
+ 8'b000xx10x,
+ 8'b0010x10x,
+ 8'b0011110x,
+ 8'b00xx0011,
+ 8'b00xx1001,
+ 8'b00xx1011,
+ 8'b010xx0xx,
+ 8'b0110x0xx,
+ 8'b011110xx,
+ 8'b010xx10x,
+ 8'b0110x10x,
+ 8'b0111110x,
+ 8'b010xx111,
+ 8'b0110x111,
+ 8'b01111111,
+ 8'b10xxx0xx,
+ 8'b10xxx10x,
+ 8'b10xxx111,
+ 8'b11011001,
+ 8'b11101011,
+ 8'b11111001,
+ 8'b11111011: pc_sel = `PC_NILD;
+ 8'b01110110,
+ 8'b11xxx111,
+ 8'b00000010,
+ 8'b00001010,
+ 8'b00010010,
+ 8'b00011010,
+ 8'b00110100,
+ 8'b00110101,
+ 8'b011100xx,
+ 8'b0111010x,
+ 8'b01110111,
+ 8'b010xx110,
+ 8'b0110x110,
+ 8'b01111110,
+ 8'b10000110,
+ 8'b10001110,
+ 8'b10010110,
+ 8'b10011110,
+ 8'b10100110,
+ 8'b10101110,
+ 8'b10110110,
+ 8'b10111110,
+ 8'b11xx0001,
+ 8'b11xx0101,
+ 8'b11100011: pc_sel = `PC_NUL;
+ default: pc_sel = `PC_LD;
+ endcase
+ end
+ `DEC2: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b001000000110,
+ 12'b001000001110,
+ 12'b001000010110,
+ 12'b001000011110,
+ 12'b001000100110,
+ 12'b001000101110,
+ 12'b001000110110,
+ 12'b001000111110,
+ 12'b001001xxx110,
+ 12'b001010xxx110,
+ 12'b001011xxx110,
+ 12'b010011100001,
+ 12'b010011100011,
+ 12'b010011100101,
+ 12'b010111100001,
+ 12'b010111100011,
+ 12'b010111100101,
+ 12'b1xxx00110100,
+ 12'b1xxx00110110,
+ 12'b1xxx00110111,
+ 12'b1xxx00111110,
+ 12'b1xxx00111111,
+ 12'b1xxx00xx0111,
+ 12'b1xxx00xx1111,
+ 12'b1xxx01100111,
+ 12'b1xxx01101111,
+ 12'b1xxx01110110,
+ 12'b1xxx01xxx000,
+ 12'b1xxx01xxx001,
+ 12'b1xxx10000010,
+ 12'b1xxx10000011,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001011,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10010011,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011011,
+ 12'b1xxx10011100,
+ 12'b1xxx10100000,
+ 12'b1xxx10100001,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10100100,
+ 12'b1xxx10101000,
+ 12'b1xxx10101001,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10101100,
+ 12'b1xxx10110000,
+ 12'b1xxx10110001,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111001,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: pc_sel = `PC_NUL;
+ 12'b010000100001,
+ 12'b010000100010,
+ 12'b010000100110,
+ 12'b010000101010,
+ 12'b010000101110,
+ 12'b010000110001,
+ 12'b010000110100,
+ 12'b010000110101,
+ 12'b010000110110,
+ 12'b010000110111,
+ 12'b010000111110,
+ 12'b010000111111,
+ 12'b010000xx0111,
+ 12'b010000xx1111,
+ 12'b010001110xxx,
+ 12'b010001xxx110,
+ 12'b010010000110,
+ 12'b010010001110,
+ 12'b010010010110,
+ 12'b010010011110,
+ 12'b010010100110,
+ 12'b010010101110,
+ 12'b010010110110,
+ 12'b010010111110,
+ 12'b010011101001,
+ 12'b010100100001,
+ 12'b010100100010,
+ 12'b010100100110,
+ 12'b010100101010,
+ 12'b010100101110,
+ 12'b010100110001,
+ 12'b010100110100,
+ 12'b010100110101,
+ 12'b010100110110,
+ 12'b010100110111,
+ 12'b010100111110,
+ 12'b010100111111,
+ 12'b010100xx0111,
+ 12'b010100xx1111,
+ 12'b010101110xxx,
+ 12'b010101xxx110,
+ 12'b010110000110,
+ 12'b010110001110,
+ 12'b010110010110,
+ 12'b010110011110,
+ 12'b010110100110,
+ 12'b010110101110,
+ 12'b010110110110,
+ 12'b010110111110,
+ 12'b010111101001,
+ 12'b010011001011, //DD+CB prefix
+ 12'b010111001011, //FD+CB prefix
+ 12'b1xxx00110010,
+ 12'b1xxx00110011,
+ 12'b1xxx00xx0010,
+ 12'b1xxx00xx0011,
+ 12'b1xxx00xxx000,
+ 12'b1xxx00xxx001,
+ 12'b1xxx01000101,
+ 12'b1xxx01001101,
+ 12'b1xxx01010100,
+ 12'b1xxx01010101,
+ 12'b1xxx01100100,
+ 12'b1xxx01100101,
+ 12'b1xxx01100110,
+ 12'b1xxx01110100,
+ 12'b1xxx01xx1011,
+ 12'b1xxx01xx0011: pc_sel = `PC_LD;
+ default: pc_sel = `PC_NILD;
+ endcase
+ end
+ `OF2A,
+ `IF3A: pc_sel = `PC_LD;
+ `RD1B,
+ `RD2B: pc_sel = `PC_INT;
+ `WR2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000011001101,
+ 12'b000011xxx100,
+ 12'b000011xxx111,
+ 12'b0001xxxxxxxx: pc_sel = `PC_LD;
+ default: pc_sel = `PC_NUL;
+ endcase
+ end
+ `PCA: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000010000: pc_sel = (tflg_reg) ? `PC_NUL : `PC_LD;
+ 12'b000000011000,
+ 12'b0000001xx000,
+ 12'b000011000011,
+ 12'b000011001001,
+ 12'b000011xxx000,
+ 12'b000011xxx010,
+ 12'b1xxx01000101,
+ 12'b1xxx01001101: pc_sel = `PC_LD;
+ default: pc_sel = `PC_NUL;
+ endcase
+ end
+ `PCO: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000011101001,
+ 12'b010011101001,
+ 12'b010111101001,
+ 12'b1xxx10010010,
+ 12'b1xxx10010011,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011011,
+ 12'b1xxx10011100,
+ 12'b1xxx10110000,
+ 12'b1xxx10110001,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111001,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: pc_sel = `PC_LD;
+ default: pc_sel = `PC_NUL;
+ endcase
+ end
+ `IF1A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b0001xxxxxxxx,
+ 12'b1xxx01000101,
+ 12'b1xxx01001101: pc_sel = `PC_LD;
+ 12'b1xxx10010010,
+ 12'b1xxx10010011,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011011,
+ 12'b1xxx10011100,
+ 12'b1xxx10110000,
+ 12'b1xxx10110001,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111001,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: pc_sel = `PC_NILD2;
+ default: pc_sel = `PC_NILD;
+ endcase
+ end
+ `HLTA: pc_sel = `PC_INT;
+ `DMA1: pc_sel = `PC_DMA;
+ default: pc_sel = `PC_NUL;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* interrupt ack and dma ack */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg) //synopsys parallel_case
+ `IF1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx01000101,
+ 12'b1xxx01001101,
+ 12'b000011110011,
+ 12'b0001xxxxxxxx: ld_inta = 1'b0;
+ default: ld_inta = 1'b1;
+ endcase
+ end
+ default: ld_inta = 1'b0;
+ endcase
+ end
+
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg) //synopsys parallel_case
+ `IF1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx01000101,
+ 12'b1xxx01001101,
+ 12'b000011110011,
+ 12'b0001xxxxxxxx: ld_dmaa = 1'b0;
+ default: ld_dmaa = 1'b1;
+ endcase
+ end
+ `HLTB,
+ `DMA2: ld_dmaa = 1'b1;
+ default: ld_dmaa = 1'b0;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* data input register control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg) //synopsys parallel_case
+ `OF1B: di_ctl = `DI_DI10;
+ `OF2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b010000110110,
+ 12'b010100110110: di_ctl = `DI_DI0;
+ default: di_ctl = `DI_DI1;
+ endcase
+ end
+ `RD1B: di_ctl = `DI_DI0;
+ `RD2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000101010,
+ 12'b000011001001,
+ 12'b000011100011,
+ 12'b000011xxx000,
+ 12'b000011xx0001,
+ 12'b0001xxxxxxxx,
+ 12'b010000101010,
+ 12'b010000110001,
+ 12'b010000110111,
+ 12'b010000xx0111,
+ 12'b010011100001,
+ 12'b010011100011,
+ 12'b010100101010,
+ 12'b010100110001,
+ 12'b010100110111,
+ 12'b010100xx0111,
+ 12'b010111100001,
+ 12'b010111100011,
+ 12'b1xxx00110110,
+ 12'b1xxx00110111,
+ 12'b1xxx00xx0111,
+ 12'b1xxx01000101,
+ 12'b1xxx01001101,
+ 12'b1xxx01xx1011: di_ctl = `DI_DI1;
+ default: di_ctl = `DI_DI0;
+ endcase
+ end
+ `INTB: di_ctl = `DI_DI0;
+ default: di_ctl = `DI_NUL;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* data output register control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg) //synopsys parallel_case
+ `WR1A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000011001101,
+ 12'b000011xxx100,
+ 12'b000011xx0101,
+ 12'b000011xxx111,
+ 12'b0001xxxxxxxx,
+ 12'b010011100101,
+ 12'b010111100101,
+ 12'b1xxx01100101,
+ 12'b1xxx01100110: do_ctl = `DO_MSB;
+ 12'b1xxx10000011,
+ 12'b1xxx10001011,
+ 12'b1xxx10010011,
+ 12'b1xxx10011011,
+ 12'b1xxx10100011,
+ 12'b1xxx10100100,
+ 12'b1xxx10101011,
+ 12'b1xxx10101100,
+ 12'b1xxx10110011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11000011,
+ 12'b1xxx11001011: do_ctl = `DO_IO;
+ default: do_ctl = `DO_LSB;
+ endcase
+ end
+ `WR2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000100010,
+ 12'b000011100011,
+ 12'b010000100010,
+ 12'b010000111110,
+ 12'b010000111111,
+ 12'b010000xx1111,
+ 12'b010011100011,
+ 12'b010100100010,
+ 12'b010100111110,
+ 12'b010100111111,
+ 12'b010100xx1111,
+ 12'b010111100011,
+ 12'b1xxx00111110,
+ 12'b1xxx00111111,
+ 12'b1xxx00xx1111,
+ 12'b1xxx01xx0011: do_ctl = `DO_MSB;
+ 12'b000011010011,
+ 12'b1xxx00xxx001,
+ 12'b1xxx01xxx001,
+ 12'b1xxx10000011,
+ 12'b1xxx10001011,
+ 12'b1xxx10010011,
+ 12'b1xxx10011011,
+ 12'b1xxx10100011,
+ 12'b1xxx10101011,
+ 12'b1xxx10110011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111100,
+ 12'b1xxx11000011,
+ 12'b1xxx11001011,
+ 12'b1xxx10111011: do_ctl = `DO_IO;
+ default: do_ctl = `DO_LSB;
+ endcase
+ end
+ default: do_ctl = `DO_NUL;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* alu operation control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg or carry_bit or par_bit or sign_bit or
+ zero_bit) begin
+ casex (state_reg) //synopsys parallel_case
+ `DEC1: begin
+ casex (inst_reg) //synopsys parallel_case
+ 8'b00xx0011,
+ 8'b00xx1001,
+ 8'b00xx1011,
+ 8'b11100011,
+ 8'b11xx0101,
+ 8'b11xxx111: aluop_sel = `ALUOP_ADD;
+ 8'b10001xxx: aluop_sel = `ALUOP_BADC;
+ 8'b00010000,
+ 8'b00xxx100,
+ 8'b10000xxx: aluop_sel = `ALUOP_BADD;
+ 8'b10100xxx: aluop_sel = `ALUOP_BAND;
+ 8'b00xxx101: aluop_sel = `ALUOP_BDEC;
+ 8'b10110xxx: aluop_sel = `ALUOP_BOR;
+ 8'b10011xxx: aluop_sel = `ALUOP_BSBC;
+ 8'b10010xxx,
+ 8'b10111xxx: aluop_sel = `ALUOP_BSUB;
+ 8'b00101111,
+ 8'b10101xxx: aluop_sel = `ALUOP_BXOR;
+ 8'b00111111: aluop_sel = `ALUOP_CCF;
+ 8'b00100111: aluop_sel = `ALUOP_DAA;
+ 8'b00010111: aluop_sel = `ALUOP_RLA;
+ 8'b00000111: aluop_sel = `ALUOP_RLCA;
+ 8'b00011111: aluop_sel = `ALUOP_RRA;
+ 8'b00001111: aluop_sel = `ALUOP_RRCA;
+ 8'b00110111: aluop_sel = `ALUOP_SCF;
+ default: aluop_sel = `ALUOP_PASS;
+ endcase
+ end
+ `IF2B: aluop_sel = `ALUOP_ADD;
+ `DEC2: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx01xx1010: aluop_sel = `ALUOP_ADC;
+ 12'b1xxx10100100,
+ 12'b1xxx10101100,
+ 12'b010000100011,
+ 12'b010000101011,
+ 12'b010000xx1001,
+ 12'b010011100101,
+ 12'b010100100011,
+ 12'b010100101011,
+ 12'b010100xx1001,
+ 12'b010111100101: aluop_sel = `ALUOP_ADD;
+ 12'b1xxx01010111,
+ 12'b1xxx01011111: aluop_sel = `ALUOP_APAS;
+ 12'b010010001100,
+ 12'b010010001101,
+ 12'b010110001100,
+ 12'b010110001101: aluop_sel = `ALUOP_BADC;
+ 12'b010010000100,
+ 12'b010010000101,
+ 12'b010110000100,
+ 12'b010110000101,
+ 12'b010000100100,
+ 12'b010000101100,
+ 12'b010100100100,
+ 12'b010100101100: aluop_sel = `ALUOP_BADD;
+ 12'b010010100100,
+ 12'b010010100101,
+ 12'b010110100100,
+ 12'b010110100101,
+ 12'b001001xxxxxx,
+ 12'b001010xxxxxx,
+ 12'b1xxx00xxx100: aluop_sel = `ALUOP_BAND;
+ 12'b010000100101,
+ 12'b010000101101,
+ 12'b010100100101,
+ 12'b010100101101: aluop_sel = `ALUOP_BDEC;
+ 12'b010010110100,
+ 12'b010010110101,
+ 12'b010110110100,
+ 12'b010110110101,
+ 12'b001011xxxxxx: aluop_sel = `ALUOP_BOR;
+ 12'b010010011100,
+ 12'b010010011101,
+ 12'b010110011100,
+ 12'b010110011101: aluop_sel = `ALUOP_BSBC;
+ 12'b010010111100,
+ 12'b010010111101,
+ 12'b010110111100,
+ 12'b010110111101,
+ 12'b010010010100,
+ 12'b010010010101,
+ 12'b010110010100,
+ 12'b010110010101,
+ 12'b1xxx01000100: aluop_sel = `ALUOP_BSUB;
+ 12'b010010101100,
+ 12'b010010101101,
+ 12'b010110101100,
+ 12'b010110101101: aluop_sel = `ALUOP_BXOR;
+ 12'b1xxx01xx1100: aluop_sel = `ALUOP_MLT;
+ 12'b001000010xxx: aluop_sel = `ALUOP_RL;
+ 12'b001000000xxx: aluop_sel = `ALUOP_RLC;
+ 12'b001000011xxx: aluop_sel = `ALUOP_RR;
+ 12'b001000001xxx: aluop_sel = `ALUOP_RRC;
+ 12'b1xxx01xx0010: aluop_sel = `ALUOP_SBC;
+ 12'b001000100xxx: aluop_sel = `ALUOP_SLA;
+ 12'b001000110xxx: aluop_sel = `ALUOP_SLL;
+ 12'b001000101xxx: aluop_sel = `ALUOP_SRA;
+ 12'b001000111xxx: aluop_sel = `ALUOP_SRL;
+ default: aluop_sel = `ALUOP_PASS;
+ endcase
+ end
+ `OF1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000100000: aluop_sel = ( !zero_bit) ? `ALUOP_ADS : `ALUOP_ADD;
+ 12'b000000101000: aluop_sel = ( zero_bit) ? `ALUOP_ADS : `ALUOP_ADD;
+ 12'b000000110000: aluop_sel = (!carry_bit) ? `ALUOP_ADS : `ALUOP_ADD;
+ 12'b000000111000: aluop_sel = ( carry_bit) ? `ALUOP_ADS : `ALUOP_ADD;
+ 12'b000000010000,
+ 12'b000000011000: aluop_sel = `ALUOP_ADS;
+ 12'b1xxx01110100,
+ 12'b000000110110: aluop_sel = `ALUOP_PASS;
+ default: aluop_sel = `ALUOP_ADD;
+ endcase
+ end
+ `OF2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b010000110110,
+ 12'b010100110110: aluop_sel = `ALUOP_ADS;
+ default: aluop_sel = `ALUOP_ADD;
+ endcase
+ end
+ `OF2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000xx0001,
+ 12'b010000100001,
+ 12'b010100100001: aluop_sel = `ALUOP_ADD;
+ 12'b000011000010,
+ 12'b000011000100: aluop_sel = ( !zero_bit) ? `ALUOP_PASS : `ALUOP_ADD;
+ 12'b000011001010,
+ 12'b000011001100: aluop_sel = ( zero_bit) ? `ALUOP_PASS : `ALUOP_ADD;
+ 12'b000011010010,
+ 12'b000011010100: aluop_sel = (!carry_bit) ? `ALUOP_PASS : `ALUOP_ADD;
+ 12'b000011011010,
+ 12'b000011011100: aluop_sel = ( carry_bit) ? `ALUOP_PASS : `ALUOP_ADD;
+ 12'b000011100010,
+ 12'b000011100100: aluop_sel = ( !par_bit) ? `ALUOP_PASS : `ALUOP_ADD;
+ 12'b000011101010,
+ 12'b000011101100: aluop_sel = ( par_bit) ? `ALUOP_PASS : `ALUOP_ADD;
+ 12'b000011110010,
+ 12'b000011110100: aluop_sel = ( !sign_bit) ? `ALUOP_PASS : `ALUOP_ADD;
+ 12'b000011111010,
+ 12'b000011111100: aluop_sel = ( sign_bit) ? `ALUOP_PASS : `ALUOP_ADD;
+ default: aluop_sel = `ALUOP_PASS;
+ endcase
+ end
+ `IF3A: aluop_sel = `ALUOP_ADS;
+ `ADR1: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx01100101,
+ 12'b1xxx01100110: aluop_sel = `ALUOP_ADD;
+ 12'b000000100010,
+ 12'b000000101010,
+ 12'b000000110010,
+ 12'b000000111010,
+ 12'b000011010011,
+ 12'b000011011011,
+ 12'b0001xxxxxxxx,
+ 12'b010000100010,
+ 12'b010000101010,
+ 12'b010100100010,
+ 12'b010100101010,
+ 12'b1xxx00xxx000,
+ 12'b1xxx00xxx001,
+ 12'b1xxx01110100,
+ 12'b1xxx01xx1011,
+ 12'b1xxx01xx0011: aluop_sel = `ALUOP_PASS;
+ default: aluop_sel = `ALUOP_ADS;
+ endcase
+ end
+ `ADR2: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10010100,
+ 12'b1xxx10011100,
+ 12'b1xxx10100000,
+ 12'b1xxx10100001,
+ 12'b1xxx10101000,
+ 12'b1xxx10101001,
+ 12'b1xxx10110000,
+ 12'b1xxx10110001,
+ 12'b1xxx10110100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111001,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: aluop_sel = `ALUOP_ADD;
+ 12'b1xxx01100101,
+ 12'b1xxx01100110: aluop_sel = `ALUOP_ADS;
+ 12'b1xxx10000010,
+ 12'b1xxx10000011,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001011,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10010011,
+ 12'b1xxx10011010,
+ 12'b1xxx10011011,
+ 12'b1xxx10100010,
+ 12'b1xxx10101010,
+ 12'b1xxx10110010,
+ 12'b1xxx10111010: aluop_sel = `ALUOP_BADD;
+ 12'b1xxx10100100,
+ 12'b1xxx10101100,
+ 12'b1xxx10100011,
+ 12'b1xxx10101011,
+ 12'b1xxx10110011,
+ 12'b1xxx10111011: aluop_sel = `ALUOP_BAND;
+ default: aluop_sel = `ALUOP_PASS;
+ endcase
+ end
+ `RD1A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000101010,
+ 12'b000011001001,
+ 12'b000011100011,
+ 12'b000011xxx000,
+ 12'b000011xx0001,
+ 12'b0001xxxxxxxx,
+ 12'b010000101010,
+ 12'b010000110001,
+ 12'b010000110111,
+ 12'b010000xx0111,
+ 12'b010011100001,
+ 12'b010011100011,
+ 12'b010100101010,
+ 12'b010100110001,
+ 12'b010100110111,
+ 12'b010100xx0111,
+ 12'b010111100001,
+ 12'b010111100011,
+ 12'b1xxx00110110,
+ 12'b1xxx00110111,
+ 12'b1xxx00xx0111,
+ 12'b1xxx01000101,
+ 12'b1xxx01001101,
+ 12'b1xxx01xx1011: aluop_sel = `ALUOP_ADD;
+ default: aluop_sel = `ALUOP_PASS;
+ endcase
+ end
+ `RD1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011: aluop_sel = `ALUOP_BAND;
+ 12'b1xxx10100001,
+ 12'b1xxx10101001,
+ 12'b1xxx10110001,
+ 12'b1xxx10111001: aluop_sel = `ALUOP_BSUB;
+ default: aluop_sel = `ALUOP_PASS;
+ endcase
+ end
+ `RD2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000011001001,
+ 12'b000011xxx000,
+ 12'b000011xx0001,
+ 12'b0001xxxxxxxx,
+ 12'b010011100001,
+ 12'b010111100001,
+ 12'b1xxx01000101,
+ 12'b1xxx01001101,
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011100,
+ 12'b1xxx10100000,
+ 12'b1xxx10100010,
+ 12'b1xxx10100100,
+ 12'b1xxx10101000,
+ 12'b1xxx10101010,
+ 12'b1xxx10101100,
+ 12'b1xxx10110000,
+ 12'b1xxx10110010,
+ 12'b1xxx10110100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111010,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11001010: aluop_sel = `ALUOP_ADD;
+ 12'b1xxx10000011,
+ 12'b1xxx10001011,
+ 12'b1xxx10010011,
+ 12'b1xxx10011011: aluop_sel = `ALUOP_BADD;
+ default: aluop_sel = `ALUOP_PASS;
+ endcase
+ end
+ `RD2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000110100,
+ 12'b000000xxx100,
+ 12'b010000110100,
+ 12'b010100110100: aluop_sel = `ALUOP_BADD;
+ 12'b001010xxx110,
+ 12'b001010xxxxxx,
+ 12'b011010xxx110,
+ 12'b011110xxx110,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011: aluop_sel = `ALUOP_BAND;
+ 12'b000000110101,
+ 12'b000000xxx101,
+ 12'b010000110101,
+ 12'b010100110101: aluop_sel = `ALUOP_BDEC;
+ 12'b001011xxx110,
+ 12'b001011xxxxxx,
+ 12'b011011xxx110,
+ 12'b011111xxx110: aluop_sel = `ALUOP_BOR;
+ 12'b1xxx10100001,
+ 12'b1xxx10101001,
+ 12'b1xxx10110001,
+ 12'b1xxx10111001: aluop_sel = `ALUOP_BSUB;
+ 12'b000011001001,
+ 12'b000011100011,
+ 12'b000011xxx000,
+ 12'b0001xxxxxxxx,
+ 12'b010011100011,
+ 12'b010111100011,
+ 12'b1xxx01000101,
+ 12'b1xxx01001101,
+ 12'b1xxx10000010,
+ 12'b1xxx10000011,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001011,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10010011,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011011,
+ 12'b1xxx10011100,
+ 12'b1xxx10100000,
+ 12'b1xxx10100100,
+ 12'b1xxx10101000,
+ 12'b1xxx10101100,
+ 12'b1xxx10110000,
+ 12'b1xxx10110100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: aluop_sel = `ALUOP_PASS;
+ 12'b0x1x00000xxx: aluop_sel = `ALUOP_RLC;
+ 12'b0x1x00001xxx: aluop_sel = `ALUOP_RRC;
+ 12'b0x1x00010xxx: aluop_sel = `ALUOP_RL;
+ 12'b0x1x00011xxx: aluop_sel = `ALUOP_RR;
+ 12'b0x1x00100xxx: aluop_sel = `ALUOP_SLA;
+ 12'b0x1x00101xxx: aluop_sel = `ALUOP_SRA;
+ 12'b0x1x00110xxx: aluop_sel = `ALUOP_SLL;
+ 12'b0x1x00111xxx: aluop_sel = `ALUOP_SRL;
+ 12'b1xxx01101111: aluop_sel = `ALUOP_RLD1;
+ 12'b1xxx01100111: aluop_sel = `ALUOP_RRD1;
+ default: aluop_sel = `ALUOP_ADD;
+ endcase
+ end
+ `WR1A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100010,
+ 12'b1xxx10101010,
+ 12'b1xxx10110010,
+ 12'b1xxx10111010,
+ 12'b1xxx11000010,
+ 12'b1xxx11001010: aluop_sel = `ALUOP_PASS;
+ 12'b1xxx10100100,
+ 12'b1xxx10101100: aluop_sel = `ALUOP_BADD;
+ default: aluop_sel = `ALUOP_ADD;
+ endcase
+ end
+ `WR1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10011011,
+ 12'b1xxx10010011,
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010100,
+ 12'b1xxx10011100,
+ 12'b1xxx10100100,
+ 12'b1xxx10101100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011,
+ 12'b1xxx10100000,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10101000,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10110000,
+ 12'b1xxx10110100,
+ 12'b1xxx10111100,
+ 12'b1xxx10111000: aluop_sel = `ALUOP_ADD;
+ 12'b1xxx10001011,
+ 12'b1xxx10000011,
+ 12'b1xxx10010010,
+ 12'b1xxx10011010,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011: aluop_sel = `ALUOP_BADD;
+ default: aluop_sel = `ALUOP_PASS;
+ endcase
+ end
+ `WR2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx100xx011,
+ 12'b1xxx10010100,
+ 12'b1xxx10011100,
+ 12'b1xxx10110100,
+ 12'b1xxx10111100,
+ 12'b1xxx11000011,
+ 12'b1xxx11001011,
+ 12'b1xxx10100000,
+ 12'b1xxx10100011,
+ 12'b1xxx10101000,
+ 12'b1xxx10101011,
+ 12'b1xxx10110000,
+ 12'b1xxx10110011,
+ 12'b1xxx10111000,
+ 12'b1xxx10111011: aluop_sel = `ALUOP_ADD;
+ 12'b000011xxx111,
+ 12'b0001xxxxxxxx: aluop_sel = `ALUOP_APAS;
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10011010,
+ 12'b1xxx10100100,
+ 12'b1xxx10101100: aluop_sel = `ALUOP_BADD;
+ default: aluop_sel = `ALUOP_PASS;
+ endcase
+ end
+ `WR2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx100xx011,
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10011010,
+ 12'b1xxx10100100,
+ 12'b1xxx10101100,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011: aluop_sel = `ALUOP_BADD;
+ default: aluop_sel = `ALUOP_ADD;
+ endcase
+ end
+ `PCA,
+ `PCO: aluop_sel = `ALUOP_ADD;
+ `IF1A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011100,
+ 12'b1xxx10100000,
+ 12'b1xxx10100010,
+ 12'b1xxx10101000,
+ 12'b1xxx10101010,
+ 12'b1xxx10110000,
+ 12'b1xxx10110010,
+ 12'b1xxx10110100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111010,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: aluop_sel = `ALUOP_ADD;
+ 12'b1xxx00011010,
+ 12'b1xxx01010100,
+ 12'b1xxx01010101,
+ 12'b1xxx00110010,
+ 12'b1xxx00110011,
+ 12'b1xxx00xx0010,
+ 12'b1xxx00xx0011: aluop_sel = `ALUOP_ADS;
+ 12'b000010001xxx,
+ 12'b000011001110,
+ 12'b010x10001110: aluop_sel = `ALUOP_BADC;
+ 12'b000010000xxx,
+ 12'b000011000110,
+ 12'b010x10000110,
+ 12'b1xxx100xx011,
+ 12'b1xxx10100100,
+ 12'b1xxx10101100,
+ 12'b1xxx10100011,
+ 12'b1xxx10101011,
+ 12'b1xxx10110011,
+ 12'b1xxx10111011: aluop_sel = `ALUOP_BADD;
+ 12'b000010100xxx,
+ 12'b0x1x01xxxxxx,
+ 12'b010x10100110,
+ 12'b000011100110,
+ 12'b1xxx00110100,
+ 12'b1xxx00xxx000,
+ 12'b1xxx011x0100,
+ 12'b1xxx01xxx000: aluop_sel = `ALUOP_BAND;
+ 12'b000010110xxx,
+ 12'b010x10110110,
+ 12'b000011110110: aluop_sel = `ALUOP_BOR;
+ 12'b000010011xxx,
+ 12'b010x10011110,
+ 12'b000011011110: aluop_sel = `ALUOP_BSBC;
+ 12'b000010010xxx,
+ 12'b000010111xxx,
+ 12'b000011010110,
+ 12'b010x10010110,
+ 12'b010x10111110,
+ 12'b000011111110: aluop_sel = `ALUOP_BSUB;
+ 12'b000010101xxx,
+ 12'b010x10101110,
+ 12'b000011101110: aluop_sel = `ALUOP_BXOR;
+ 12'b1xxx01101111: aluop_sel = `ALUOP_RLD2;
+ 12'b1xxx01100111: aluop_sel = `ALUOP_RRD2;
+ default: aluop_sel = `ALUOP_PASS;
+ endcase
+ end
+ `INTB: aluop_sel = `ALUOP_PASS;
+ default: aluop_sel = `ALUOP_ADD;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* alu a input control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg or carry_bit or par_bit or sign_bit or
+ tflg_reg or zero_bit) begin
+ casex (state_reg) //synopsys parallel_case
+ `DEC1: begin
+ casex (inst_reg) //synopsys parallel_case
+ 8'b10000xxx,
+ 8'b10001xxx,
+ 8'b10010xxx,
+ 8'b10011xxx,
+ 8'b10100xxx,
+ 8'b10101xxx,
+ 8'b10110xxx,
+ 8'b10111xxx: alua_sel = `ALUA_AA;
+ 8'b00100111: alua_sel = `ALUA_DAA;
+ 8'b00xx1001: alua_sel = `ALUA_HL;
+ 8'b00010000,
+ 8'b00101111,
+ 8'b00xxx101,
+ 8'b00xx1011,
+ 8'b11xx0101,
+ 8'b11xxx111: alua_sel = `ALUA_M1;
+ default: alua_sel = `ALUA_ONE;
+ endcase
+ end
+ `DEC2: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b001001xxxxxx,
+ 12'b001010xxxxxx,
+ 12'b001011xxxxxx: alua_sel = `ALUA_BIT;
+ 12'b1xxx01xx0010,
+ 12'b1xxx01xx1010: alua_sel = `ALUA_HL;
+ 12'b1xxx01010111: alua_sel = `ALUA_II;
+ 12'b010000xx1001: alua_sel = `ALUA_IX;
+ 12'b010100xx1001: alua_sel = `ALUA_IY;
+ 12'b010000100101,
+ 12'b010000101011,
+ 12'b010000101101,
+ 12'b010011100101,
+ 12'b010100100101,
+ 12'b010100101011,
+ 12'b010100101101,
+ 12'b1xxx10101100,
+ 12'b010111100101: alua_sel = `ALUA_M1;
+ 12'b1xxx10100100,
+ 12'b010000100100,
+ 12'b010000101100,
+ 12'b010000100011,
+ 12'b010100100100,
+ 12'b010100101100,
+ 12'b010100100011: alua_sel = `ALUA_ONE;
+ 12'b1xxx01011111: alua_sel = `ALUA_RR;
+ 12'b1xxx01000100: alua_sel = `ALUA_ZER;
+ default: alua_sel = `ALUA_AA;
+ endcase
+ end
+ `OF1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000100000: alua_sel = ( !zero_bit) ? `ALUA_PC : `ALUA_ONE;
+ 12'b000000101000: alua_sel = ( zero_bit) ? `ALUA_PC : `ALUA_ONE;
+ 12'b000000110000: alua_sel = (!carry_bit) ? `ALUA_PC : `ALUA_ONE;
+ 12'b000000111000: alua_sel = ( carry_bit) ? `ALUA_PC : `ALUA_ONE;
+ 12'b000000010000,
+ 12'b000000011000: alua_sel = `ALUA_PC;
+ default: alua_sel = `ALUA_ONE;
+ endcase
+ end
+ `OF2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b010000110110: alua_sel = `ALUA_IX;
+ 12'b010100110110: alua_sel = `ALUA_IY;
+ default: alua_sel = `ALUA_M1;
+ endcase
+ end
+ `IF3A: alua_sel = (page_reg[0]) ? `ALUA_IY : `ALUA_IX;
+ `ADR1: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000011010011: alua_sel = `ALUA_M1;
+ 12'b1xxx01100101,
+ 12'b1xxx01100110: alua_sel = `ALUA_M1;
+ default: alua_sel = (page_reg[0]) ? `ALUA_IY : `ALUA_IX;
+ endcase
+ end
+ `ADR2: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx01100101: alua_sel = `ALUA_IX;
+ 12'b1xxx01100110: alua_sel = `ALUA_IY;
+ default: alua_sel = `ALUA_M1;
+ endcase
+ end
+ `RD1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100001,
+ 12'b1xxx10101001,
+ 12'b1xxx10110001,
+ 12'b1xxx10111001: alua_sel = `ALUA_AA;
+ default: alua_sel = `ALUA_M1;
+ endcase
+ end
+ `RD2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b0001xxxxxxxx,
+ 12'b1xxx10001010,
+ 12'b1xxx10001011,
+ 12'b1xxx10001100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011011,
+ 12'b1xxx10011100,
+ 12'b1xxx10101000,
+ 12'b1xxx10101010,
+ 12'b1xxx10101100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111010,
+ 12'b1xxx10111100,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: alua_sel = `ALUA_M1;
+ default: alua_sel = `ALUA_ONE;
+ endcase
+ end
+ `RD2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx01100111,
+ 12'b1xxx01101111,
+ 12'b1xxx10100001,
+ 12'b1xxx10101001,
+ 12'b1xxx10110001,
+ 12'b1xxx10111001: alua_sel = `ALUA_AA;
+ 12'b0x1x1xxxxxxx: alua_sel = `ALUA_BIT;
+ 12'b000000xxx101,
+ 12'b010000110101,
+ 12'b010100110101,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011: alua_sel = `ALUA_M1;
+ default: alua_sel = `ALUA_ONE;
+ endcase
+ end
+ `WR1A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000011001101,
+ 12'b000011xxx100,
+ 12'b000011xx0101,
+ 12'b000011xxx111,
+ 12'b0001xxxxxxxx,
+ 12'b010011100101,
+ 12'b010111100101,
+ 12'b1xxx01100101,
+ 12'b1xxx01100110,
+ 12'b1xxx10001010,
+ 12'b1xxx10001011,
+ 12'b1xxx10001100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011011,
+ 12'b1xxx10011100,
+ 12'b1xxx10101000,
+ 12'b1xxx10101011,
+ 12'b1xxx10100100,
+ 12'b1xxx10101100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: alua_sel = `ALUA_M1;
+ default: alua_sel = `ALUA_ONE;
+ endcase
+ end
+ `WR1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10000010,
+ 12'b1xxx10000011,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001011,
+ 12'b1xxx10001100,
+ 12'b1xxx10100000,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10100100,
+ 12'b1xxx10101000,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10101100: alua_sel = `ALUA_ONE;
+ default: alua_sel = `ALUA_M1;
+ endcase
+ end
+ `WR2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b0001xxxxxxxx: alua_sel = `ALUA_INT;
+ 12'b1xxx10001010,
+ 12'b1xxx10001011,
+ 12'b1xxx10001100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011011,
+ 12'b1xxx10011100,
+ 12'b1xxx10101000,
+ 12'b1xxx10101011,
+ 12'b1xxx10101100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: alua_sel = `ALUA_M1;
+ 12'b000011xxx111: alua_sel = `ALUA_RST;
+ default: alua_sel = `ALUA_ONE;
+ endcase
+ end
+ `WR2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10000010,
+ 12'b1xxx10000011,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001011,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10010011,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011011,
+ 12'b1xxx10011100,
+ 12'b1xxx10100000,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10100100,
+ 12'b1xxx10101000,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10101100,
+ 12'b1xxx10110000,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: alua_sel = `ALUA_M1;
+ default: alua_sel = `ALUA_ONE;
+ endcase
+ end
+ `BLK1: begin
+ alua_sel = (inst_reg[3]) ? `ALUA_M1 : `ALUA_ONE;
+ end
+ `BLK2: begin
+ alua_sel = (inst_reg[4]) ? `ALUA_M1 : `ALUA_ONE;
+ end
+ `PCA: alua_sel = (tflg_reg) ? `ALUA_ZER : `ALUA_M2;
+ `IF1A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b0x1x01xxxxxx: alua_sel = `ALUA_BIT;
+ 12'b1xxx00110010,
+ 12'b1xxx00xx0010,
+ 12'b1xxx01010101: alua_sel = `ALUA_IX;
+ 12'b1xxx00110011,
+ 12'b1xxx00xx0011,
+ 12'b1xxx01010100: alua_sel = `ALUA_IY;
+ 12'b1xxx00xxx000,
+ 12'b1xxx01xxx000,
+ 12'b1xxx10001010,
+ 12'b1xxx10001011,
+ 12'b1xxx10001100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011011,
+ 12'b1xxx10011100,
+ 12'b1xxx10100011,
+ 12'b1xxx10101000,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10101100,
+ 12'b1xxx10110011,
+ 12'b1xxx10111000,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011,
+ 12'b1xxx10111100,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011: alua_sel = `ALUA_M1;
+ 12'b1xxx10000010,
+ 12'b1xxx10000011,
+ 12'b1xxx10000100,
+ 12'b1xxx10010010,
+ 12'b1xxx10010011,
+ 12'b1xxx10010100,
+ 12'b1xxx10100000,
+ 12'b1xxx10100010,
+ 12'b1xxx10100100,
+ 12'b1xxx10110000,
+ 12'b1xxx10110010,
+ 12'b1xxx10110100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011: alua_sel = `ALUA_ONE;
+ 12'b1xxx01110100: alua_sel = `ALUA_TMP;
+ default: alua_sel = `ALUA_AA;
+ endcase
+ end
+ `INTA: alua_sel = `ALUA_M1;
+ default: alua_sel = `ALUA_ONE;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* alu b input control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg or carry_bit or par_bit or sign_bit or
+ zero_bit) begin
+ casex (state_reg) //synopsys parallel_case
+ `DEC1: begin
+ casex (inst_reg) //synopsys parallel_case
+ 8'b00000111,
+ 8'b00001111,
+ 8'b00010111,
+ 8'b00011111,
+ 8'b00100111,
+ 8'b00101111: alub_sel = `ALUB_AA;
+ 8'b00010000: alub_sel = `ALUB_BB;
+ 8'b00000010,
+ 8'b00001010: alub_sel = `ALUB_BC;
+ 8'b00010010,
+ 8'b00011010,
+ 8'b11101011: alub_sel = `ALUB_DE;
+ 8'b11101001,
+ 8'b11111001: alub_sel = `ALUB_HL;
+ 8'b01xxx000,
+ 8'b10xxx000: alub_sel = `ALUB_BB;
+ 8'b01xxx001,
+ 8'b10xxx001: alub_sel = `ALUB_CC;
+ 8'b01xxx010,
+ 8'b10xxx010: alub_sel = `ALUB_DD;
+ 8'b01xxx011,
+ 8'b10xxx011: alub_sel = `ALUB_EE;
+ 8'b01xxx100,
+ 8'b10xxx100: alub_sel = `ALUB_HH;
+ 8'b01xxx101,
+ 8'b10xxx101: alub_sel = `ALUB_LL;
+ 8'b01xxx111,
+ 8'b10xxx111: alub_sel = `ALUB_AA;
+ 8'b0000010x: alub_sel = `ALUB_BB;
+ 8'b0000110x: alub_sel = `ALUB_CC;
+ 8'b0001010x: alub_sel = `ALUB_DD;
+ 8'b0001110x: alub_sel = `ALUB_EE;
+ 8'b0010010x: alub_sel = `ALUB_HH;
+ 8'b0010110x: alub_sel = `ALUB_LL;
+ 8'b0011110x: alub_sel = `ALUB_AA;
+ 8'b00000011,
+ 8'b00001001,
+ 8'b00001011: alub_sel = `ALUB_BC;
+ 8'b00010011,
+ 8'b00011001,
+ 8'b00011011: alub_sel = `ALUB_DE;
+ 8'b00100011,
+ 8'b00101001,
+ 8'b00101011: alub_sel = `ALUB_HL;
+ 8'b00110011,
+ 8'b00111001,
+ 8'b00111011: alub_sel = `ALUB_SP;
+ 8'b11xx0101,
+ 8'b11xxx111: alub_sel = `ALUB_SP;
+ default: alub_sel = `ALUB_PC;
+ endcase
+ end
+ `IF2B: alub_sel = `ALUB_PC;
+ `DEC2: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx01000100,
+ 12'b1xxx01000111,
+ 12'b1xxx01001111: alub_sel = `ALUB_AA;
+ 12'b1xxx01xxx000,
+ 12'b1xxx01xxx001,
+ 12'b1xxx10000100,
+ 12'b1xxx10001100,
+ 12'b1xxx10100010,
+ 12'b1xxx10101010,
+ 12'b1xxx10110010,
+ 12'b1xxx10111010: alub_sel = `ALUB_BC;
+ 12'b010000100011,
+ 12'b010000101011,
+ 12'b010011101001,
+ 12'b010011111001: alub_sel = `ALUB_IX;
+ 12'b010000100100,
+ 12'b010000100101,
+ 12'b0100010xx100,12'b01000110x100,12'b010001111100,
+ 12'b010010000100,
+ 12'b010010001100,
+ 12'b010010010100,
+ 12'b010010011100,
+ 12'b010010100100,
+ 12'b010010101100,
+ 12'b010010110100,
+ 12'b010010111100: alub_sel = `ALUB_IXH;
+ 12'b010100100100,
+ 12'b010100100101,
+ 12'b0101010xx100,12'b01010110x100,12'b010101111100,
+ 12'b010110000100,
+ 12'b010110001100,
+ 12'b010110010100,
+ 12'b010110011100,
+ 12'b010110100100,
+ 12'b010110101100,
+ 12'b010110110100,
+ 12'b010110111100: alub_sel = `ALUB_IYH;
+ 12'b010000101100,
+ 12'b010000101101,
+ 12'b0100010xx101,12'b01000110x101,12'b010001111101,
+ 12'b010010000101,
+ 12'b010010001101,
+ 12'b010010010101,
+ 12'b010010011101,
+ 12'b010010100101,
+ 12'b010010101101,
+ 12'b010010110101,
+ 12'b010010111101: alub_sel = `ALUB_IXL;
+ 12'b010100101100,
+ 12'b010100101101,
+ 12'b0101010xx101,12'b01010110x101,12'b010101111101,
+ 12'b010110000101,
+ 12'b010110001101,
+ 12'b010110010101,
+ 12'b010110011101,
+ 12'b010110100101,
+ 12'b010110101101,
+ 12'b010110110101,
+ 12'b010110111101: alub_sel = `ALUB_IYL;
+ 12'b010100100011,
+ 12'b010100101011,
+ 12'b010111101001,
+ 12'b010111111001: alub_sel = `ALUB_IY;
+ 12'b1xxx01000101,
+ 12'b1xxx01001101: alub_sel = `ALUB_PC;
+ 12'b010x0110x000,
+ 12'b1xxx00000100,
+ 12'b0010xxxxx000: alub_sel = `ALUB_BB;
+ 12'b010x0110x001,
+ 12'b1xxx00001100,
+ 12'b1xxx10000010,
+ 12'b1xxx10001010,
+ 12'b1xxx10010010,
+ 12'b1xxx10011010,
+ 12'b0010xxxxx001: alub_sel = `ALUB_CC;
+ 12'b010x0110x010,
+ 12'b1xxx00010100,
+ 12'b0010xxxxx010: alub_sel = `ALUB_DD;
+ 12'b010x0110x011,
+ 12'b1xxx00011100,
+ 12'b0010xxxxx011: alub_sel = `ALUB_EE;
+ 12'b1xxx00100100,
+ 12'b0010xxxxx100: alub_sel = `ALUB_HH;
+ 12'b1xxx00101100,
+ 12'b0010xxxxx101: alub_sel = `ALUB_LL;
+ 12'b010x0110x111,
+ 12'b1xxx00111100,
+ 12'b0010xxxxx111: alub_sel = `ALUB_AA;
+ 12'b1xxx01001100,
+ 12'b1xxx0100x010: alub_sel = `ALUB_BC;
+ 12'b1xxx01011100,
+ 12'b1xxx0101x010: alub_sel = `ALUB_DE;
+ 12'b1xxx01111100,
+ 12'b1xxx0111x010: alub_sel = `ALUB_SP;
+ 12'b010011100101,
+ 12'b010111100101: alub_sel = `ALUB_SP;
+ 12'b010x00001001: alub_sel = `ALUB_BC;
+ 12'b1xxx10010100,
+ 12'b1xxx10011100,
+ 12'b1xxx11000010,
+ 12'b1xxx11001010,
+ 12'b010x00011001: alub_sel = `ALUB_DE;
+ 12'b010000101001: alub_sel = `ALUB_IX;
+ 12'b010100101001: alub_sel = `ALUB_IY;
+ 12'b010x00111001: alub_sel = `ALUB_SP;
+ default: alub_sel = `ALUB_HL;
+ endcase
+ end
+ `OF1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx01110100,
+ 12'b000000010000,
+ 12'b000000011000,
+ 12'b000000110110: alub_sel = `ALUB_DIN;
+ 12'b000000100000: alub_sel = ( !zero_bit) ? `ALUB_DIN : `ALUB_PC;
+ 12'b000000101000: alub_sel = ( zero_bit) ? `ALUB_DIN : `ALUB_PC;
+ 12'b000000110000: alub_sel = (!carry_bit) ? `ALUB_DIN : `ALUB_PC;
+ 12'b000000111000: alub_sel = ( carry_bit) ? `ALUB_DIN : `ALUB_PC;
+ default: alub_sel = `ALUB_PC;
+ endcase
+ end
+ `OF2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b010000110110,
+ 12'b010100110110: alub_sel = `ALUB_DIN;
+ default: alub_sel = `ALUB_SP;
+ endcase
+ end
+ `OF2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000011000011,
+ 12'b010000110110,
+ 12'b010100110110: alub_sel = `ALUB_DIN;
+ 12'b000011000010: alub_sel = ( !zero_bit) ? `ALUB_DIN : `ALUB_PC;
+ 12'b000011001010: alub_sel = ( zero_bit) ? `ALUB_DIN : `ALUB_PC;
+ 12'b000011010010: alub_sel = (!carry_bit) ? `ALUB_DIN : `ALUB_PC;
+ 12'b000011011010: alub_sel = ( carry_bit) ? `ALUB_DIN : `ALUB_PC;
+ 12'b000011100010: alub_sel = ( !par_bit) ? `ALUB_DIN : `ALUB_PC;
+ 12'b000011101010: alub_sel = ( par_bit) ? `ALUB_DIN : `ALUB_PC;
+ 12'b000011110010: alub_sel = ( !sign_bit) ? `ALUB_DIN : `ALUB_PC;
+ 12'b000011111010: alub_sel = ( sign_bit) ? `ALUB_DIN : `ALUB_PC;
+ 12'b000011001101: alub_sel = `ALUB_PCH;
+ 12'b000011000100: alub_sel = ( !zero_bit) ? `ALUB_PCH : `ALUB_PC;
+ 12'b000011001100: alub_sel = ( zero_bit) ? `ALUB_PCH : `ALUB_PC;
+ 12'b000011010100: alub_sel = (!carry_bit) ? `ALUB_PCH : `ALUB_PC;
+ 12'b000011011100: alub_sel = ( carry_bit) ? `ALUB_PCH : `ALUB_PC;
+ 12'b000011100100: alub_sel = ( !par_bit) ? `ALUB_PCH : `ALUB_PC;
+ 12'b000011101100: alub_sel = ( par_bit) ? `ALUB_PCH : `ALUB_PC;
+ 12'b000011110100: alub_sel = ( !sign_bit) ? `ALUB_PCH : `ALUB_PC;
+ 12'b000011111100: alub_sel = ( sign_bit) ? `ALUB_PCH : `ALUB_PC;
+ default: alub_sel = `ALUB_PC;
+ endcase
+ end
+ `IF3A: alub_sel = `ALUB_DIN;
+ `ADR1: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx01110100: alub_sel = `ALUB_CC;
+ 12'b000011010011,
+ 12'b000011011011: alub_sel = `ALUB_IO;
+ 12'b1xxx01100101,
+ 12'b1xxx01100110: alub_sel = `ALUB_SP;
+ 12'b0001xxxxxxxx: alub_sel = `ALUB_TMP;
+ default: alub_sel = `ALUB_DIN;
+ endcase
+ end
+ `ADR2: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000000010,
+ 12'b000000010010,
+ 12'b000000110010,
+ 12'b000011010011: alub_sel = `ALUB_AA;
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10011010,
+ 12'b1xxx10100100,
+ 12'b1xxx10101100,
+ 12'b1xxx100xx011,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011: alub_sel = `ALUB_BB;
+ 12'b1xxx10010100,
+ 12'b1xxx10011100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011,
+ 12'b1xxx10100000,
+ 12'b1xxx10100001,
+ 12'b1xxx10101000,
+ 12'b1xxx10101001,
+ 12'b1xxx10110000,
+ 12'b1xxx10110001,
+ 12'b1xxx10110100,
+ 12'b1xxx10111100,
+ 12'b1xxx10111000,
+ 12'b1xxx10111001: alub_sel = `ALUB_BC;
+ 12'b1xxx01100101,
+ 12'b1xxx01100110: alub_sel = `ALUB_DIN;
+ 12'b010000100010: alub_sel = `ALUB_IX;
+ 12'b010011100101: alub_sel = `ALUB_IXH;
+ 12'b010000111111,
+ 12'b010100111110,
+ 12'b1xxx00111111: alub_sel = `ALUB_IXL;
+ 12'b010100100010: alub_sel = `ALUB_IY;
+ 12'b010111100101: alub_sel = `ALUB_IYH;
+ 12'b010000111110,
+ 12'b010100111111,
+ 12'b1xxx00111110: alub_sel = `ALUB_IYL;
+ 12'b000011xxx111: alub_sel = `ALUB_PCH;
+ 12'b000001xxx000,
+ 12'b010x01110000,
+ 12'b1xxx00000001,
+ 12'b1xxx01000001: alub_sel = `ALUB_BB;
+ 12'b010000001111,
+ 12'b010100001111,
+ 12'b1xxx00001111,
+ 12'b000001xxx001,
+ 12'b010x01110001,
+ 12'b1xxx01110100,
+ 12'b1xxx00001001,
+ 12'b1xxx01001001: alub_sel = `ALUB_CC;
+ 12'b000001xxx010,
+ 12'b010x01110010,
+ 12'b1xxx00010001,
+ 12'b1xxx01010001: alub_sel = `ALUB_DD;
+ 12'b010000011111,
+ 12'b010100011111,
+ 12'b1xxx00011111,
+ 12'b000001xxx011,
+ 12'b010x01110011,
+ 12'b1xxx00011001,
+ 12'b1xxx01011001: alub_sel = `ALUB_EE;
+ 12'b000001xxx100,
+ 12'b010x01110100,
+ 12'b1xxx00100001,
+ 12'b1xxx01100001: alub_sel = `ALUB_HH;
+ 12'b010000101111,
+ 12'b010100101111,
+ 12'b1xxx00101111,
+ 12'b000001xxx101,
+ 12'b010x01110101,
+ 12'b1xxx00101001,
+ 12'b1xxx01101001: alub_sel = `ALUB_LL;
+ 12'b000001xxx111,
+ 12'b010x01110111,
+ 12'b1xxx00111001,
+ 12'b1xxx01111001: alub_sel = `ALUB_AA;
+ 12'b1xxx01000011: alub_sel = `ALUB_BC;
+ 12'b1xxx01010011: alub_sel = `ALUB_DE;
+ 12'b1xxx01110011: alub_sel = `ALUB_SP;
+ 12'b000011000101: alub_sel = `ALUB_BB;
+ 12'b000011010101: alub_sel = `ALUB_DD;
+ 12'b000011100101: alub_sel = `ALUB_HH;
+ 12'b000011110101: alub_sel = `ALUB_AA;
+ 12'b1xxx01100101,
+ 12'b1xxx01100110: alub_sel = `ALUB_TMP;
+ default: alub_sel = `ALUB_HL;
+ endcase
+ end
+ `RD1A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100100,
+ 12'b1xxx10101100,
+ 12'b1xxx10100011,
+ 12'b1xxx10101011,
+ 12'b1xxx10110011,
+ 12'b1xxx10111011: alub_sel = `ALUB_BC;
+ 12'b1xxx100xx011: alub_sel = `ALUB_CC;
+ 12'b1xxx11000011,
+ 12'b1xxx11001011,
+ 12'b1xxx10100000,
+ 12'b1xxx10101000,
+ 12'b1xxx10110000,
+ 12'b1xxx10110100,
+ 12'b1xxx10111100,
+ 12'b1xxx10111000: alub_sel = `ALUB_DE;
+ 12'b1xxx00110110,
+ 12'b1xxx00110111,
+ 12'b1xxx00xx0111,
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011100,
+ 12'b1xxx11000010,
+ 12'b1xxx11001010,
+ 12'b1xxx10100001,
+ 12'b1xxx10100010,
+ 12'b1xxx10101001,
+ 12'b1xxx10101010,
+ 12'b1xxx10110001,
+ 12'b1xxx10110010,
+ 12'b1xxx10111001,
+ 12'b1xxx10111010: alub_sel = `ALUB_HL;
+ 12'b010000110001,
+ 12'b010000110111,
+ 12'b010000xx0111,
+ 12'b010100110001,
+ 12'b010100110111,
+ 12'b010100xx0111,
+ 12'b000000101010,
+ 12'b0001xxxxxxxx,
+ 12'b010000101010,
+ 12'b010100101010,
+ 12'b1xxx01xx1011: alub_sel = `ALUB_TMP;
+ default: alub_sel = `ALUB_SP;
+ endcase
+ end
+ `RD1B: alub_sel = `ALUB_DIN;
+ `RD2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100100,
+ 12'b1xxx10101100,
+ 12'b1xxx10100011,
+ 12'b1xxx10101011,
+ 12'b1xxx10110011,
+ 12'b1xxx10111011: alub_sel = `ALUB_BC;
+ 12'b1xxx01110100,
+ 12'b1xxx100xx011: alub_sel = `ALUB_CC;
+ 12'b1xxx11000011,
+ 12'b1xxx11001011,
+ 12'b1xxx10100000,
+ 12'b1xxx10101000,
+ 12'b1xxx10110000,
+ 12'b1xxx10110100,
+ 12'b1xxx10111100,
+ 12'b1xxx10111000: alub_sel = `ALUB_DE;
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011100,
+ 12'b1xxx11000010,
+ 12'b1xxx11001010,
+ 12'b001010xxxxxx,
+ 12'b1xxx10100001,
+ 12'b1xxx10100010,
+ 12'b1xxx10101001,
+ 12'b1xxx10101010,
+ 12'b1xxx10110001,
+ 12'b1xxx10110010,
+ 12'b1xxx10111001,
+ 12'b1xxx10111010: alub_sel = `ALUB_HL;
+ 12'b000011001001,
+ 12'b000011100011,
+ 12'b000011xxx000,
+ 12'b000011xx0001,
+ 12'b0001xxxxxxxx,
+ 12'b010011100001,
+ 12'b010011100011,
+ 12'b010111100001,
+ 12'b010111100011,
+ 12'b1xxx01000101,
+ 12'b1xxx01001101: alub_sel = `ALUB_SP;
+ default: alub_sel = `ALUB_TMP;
+ endcase
+ end
+ `RD2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000011100011: alub_sel = `ALUB_HL;
+ 12'b010011100011: alub_sel = `ALUB_IX;
+ 12'b010111100011: alub_sel = `ALUB_IY;
+ 12'b010000110001,
+ 12'b010000110111,
+ 12'b010000xx0111,
+ 12'b010100110001,
+ 12'b010100110111,
+ 12'b010100xx0111,
+ 12'b1xxx00110110,
+ 12'b1xxx00110111,
+ 12'b1xxx00xx0111,
+ 12'b000000001010,
+ 12'b000000011010,
+ 12'b000000101010,
+ 12'b000000111010,
+ 12'b000001xxxxxx,
+ 12'b000010000xxx,
+ 12'b000010001xxx,
+ 12'b000010010xxx,
+ 12'b000010011xxx,
+ 12'b000010100xxx,
+ 12'b000010101xxx,
+ 12'b000010110xxx,
+ 12'b000010111xxx,
+ 12'b000011011011,
+ 12'b000011xx0001,
+ 12'b001001xxx110,
+ 12'b001001xxxxxx,
+ 12'b010000101010,
+ 12'b010001xxx110,
+ 12'b010010000110,
+ 12'b010010001110,
+ 12'b010010010110,
+ 12'b010010011110,
+ 12'b010010100110,
+ 12'b010010101110,
+ 12'b010010110110,
+ 12'b010010111110,
+ 12'b010011100001,
+ 12'b010100101010,
+ 12'b010101xxx110,
+ 12'b010110000110,
+ 12'b010110001110,
+ 12'b010110010110,
+ 12'b010110011110,
+ 12'b010110100110,
+ 12'b010110101110,
+ 12'b010110110110,
+ 12'b010110111110,
+ 12'b010111100001,
+ 12'b011001xxx110,
+ 12'b011101xxx110,
+ 12'b1xxx00xxx000,
+ 12'b1xxx00xxx100,
+ 12'b1xxx01xxx000,
+ 12'b1xxx01xxx100,
+ 12'b1xxx01xx1011: alub_sel = `ALUB_PC;
+ 12'b0001xxxxxxxx: alub_sel = `ALUB_PCH;
+ default: alub_sel = `ALUB_DIN;
+ endcase
+ end
+ `WR1A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100100,
+ 12'b1xxx10101100: alub_sel = `ALUB_BB;
+ 12'b1xxx10000100,
+ 12'b1xxx10001100,
+ 12'b1xxx10100010,
+ 12'b1xxx10101010,
+ 12'b1xxx10110010,
+ 12'b1xxx10111010: alub_sel = `ALUB_BC;
+ 12'b1xxx10000010,
+ 12'b1xxx10001010,
+ 12'b1xxx10010010,
+ 12'b1xxx10011010: alub_sel = `ALUB_CC;
+ 12'b1xxx10010100,
+ 12'b1xxx10011100,
+ 12'b1xxx11000010,
+ 12'b1xxx11001010: alub_sel = `ALUB_DE;
+ 12'b1xxx00111110,
+ 12'b1xxx00111111,
+ 12'b1xxx00xx1111,
+ 12'b1xxx10100100,
+ 12'b1xxx10101100,
+ 12'b1xxx10110100,
+ 12'b1xxx10111100,
+ 12'b1xxx11000011,
+ 12'b1xxx11001011,
+ 12'b1xxx100xx011,
+ 12'b1xxx10100000,
+ 12'b1xxx10100011,
+ 12'b1xxx10101000,
+ 12'b1xxx10101011,
+ 12'b1xxx10110000,
+ 12'b1xxx10110011,
+ 12'b1xxx10111000,
+ 12'b1xxx10111011: alub_sel = `ALUB_HL;
+ 12'b010000111110,
+ 12'b010000111111,
+ 12'b010000xx1111,
+ 12'b010100111110,
+ 12'b010100111111,
+ 12'b010100xx1111,
+ 12'b000000100010,
+ 12'b010000100010,
+ 12'b010100100010,
+ 12'b1xxx01xx0011: alub_sel = `ALUB_TMP;
+ default: alub_sel = `ALUB_SP;
+ endcase
+ end
+ `WR1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10010010,
+ 12'b1xxx10011010,
+ 12'b010000001111,
+ 12'b010100001111,
+ 12'b1xxx00001111,
+ 12'b1xxx1001x011,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011: alub_sel = `ALUB_BB;
+ 12'b1xxx10010100,
+ 12'b1xxx10011100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111100,
+ 12'b1xxx10110000,
+ 12'b1xxx10111000: alub_sel = `ALUB_BC;
+ 12'b010000011111,
+ 12'b010100011111,
+ 12'b1xxx00011111: alub_sel = `ALUB_DD;
+ 12'b010000101111,
+ 12'b010100101111,
+ 12'b1xxx00101111,
+ 12'b000000100010,
+ 12'b000011100011: alub_sel = `ALUB_HH;
+ 12'b010011100101: alub_sel = `ALUB_IX;
+ 12'b010000111111,
+ 12'b010100111110,
+ 12'b1xxx00111111,
+ 12'b010000100010,
+ 12'b010011100011: alub_sel = `ALUB_IXH;
+ 12'b010111100101: alub_sel = `ALUB_IY;
+ 12'b010000111110,
+ 12'b010100111111,
+ 12'b1xxx00111110,
+ 12'b010100100010,
+ 12'b010111100011: alub_sel = `ALUB_IYH;
+ 12'b1xxx01000011: alub_sel = `ALUB_BC;
+ 12'b1xxx01010011: alub_sel = `ALUB_DE;
+ 12'b1xxx01100011: alub_sel = `ALUB_HL;
+ 12'b1xxx01110011: alub_sel = `ALUB_SP;
+ 12'b000011000101: alub_sel = `ALUB_BC;
+ 12'b000011010101: alub_sel = `ALUB_DE;
+ 12'b000011100101: alub_sel = `ALUB_HL;
+ 12'b000011110101: alub_sel = `ALUB_AF;
+ 12'b1xxx01100101,
+ 12'b1xxx01100110: alub_sel = `ALUB_TMP;
+ default: alub_sel = `ALUB_PC;
+ endcase
+ end
+ `WR2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10000010,
+ 12'b1xxx10001010,
+ 12'b1xxx10010010,
+ 12'b1xxx10011010: alub_sel = `ALUB_CC;
+ 12'b1xxx10100010,
+ 12'b1xxx10101010,
+ 12'b1xxx10110010,
+ 12'b1xxx10111010: alub_sel = `ALUB_BC;
+ 12'b1xxx10010100,
+ 12'b1xxx10011100,
+ 12'b1xxx11000010,
+ 12'b1xxx11001010: alub_sel = `ALUB_DE;
+ 12'b000011001101,
+ 12'b000011xxx100: alub_sel = `ALUB_DIN;
+ default: alub_sel = `ALUB_HL;
+ endcase
+ end
+ `WR2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10011010,
+ 12'b1xxx10100100,
+ 12'b1xxx10101100,
+ 12'b1xxx100xx011,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011: alub_sel = `ALUB_BB;
+ 12'b1xxx10010100,
+ 12'b1xxx10011100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011,
+ 12'b1xxx10110100,
+ 12'b1xxx10111100,
+ 12'b1xxx10100000,
+ 12'b1xxx10101000,
+ 12'b1xxx10110000,
+ 12'b1xxx10111000: alub_sel = `ALUB_BC;
+ default: alub_sel = `ALUB_PC;
+ endcase
+ end
+ `BLK1: alub_sel = `ALUB_HL;
+ `BLK2: alub_sel = (inst_reg[4]) ? `ALUB_BC : `ALUB_PC;
+ `PCA,
+ `PCO: alub_sel = `ALUB_PC;
+ `IF1A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100011,
+ 12'b1xxx10101011,
+ 12'b1xxx10110011,
+ 12'b1xxx10111011: alub_sel = `ALUB_BB;
+ 12'b1xxx10100100,
+ 12'b1xxx10101100,
+ 12'b1xxx100xx011: alub_sel = `ALUB_CC;
+ 12'b1xxx11000011,
+ 12'b1xxx11001011,
+ 12'b1xxx10100000,
+ 12'b1xxx10101000,
+ 12'b1xxx10110100,
+ 12'b1xxx10111100,
+ 12'b1xxx10110000,
+ 12'b1xxx10111000: alub_sel = `ALUB_DE;
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011100,
+ 12'b1xxx10101010,
+ 12'b1xxx10111010,
+ 12'b1xxx10100010,
+ 12'b1xxx10110010,
+ 12'b1xxx11000010,
+ 12'b1xxx11001010: alub_sel = `ALUB_HL;
+ default: alub_sel = `ALUB_DIN;
+ endcase
+ end
+ `INTA: alub_sel = `ALUB_SP;
+ `INTB: alub_sel = `ALUB_PCH;
+ default: alub_sel = `ALUB_PC;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* register write control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg or carry_bit or par_bit or sign_bit or
+ vector_int or zero_bit) begin
+ casex (state_reg) //synopsys parallel_case
+ `OF1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000010000: wr_addr = `WREG_BB;
+ default: wr_addr = `WREG_NUL;
+ endcase
+ end
+ `OF2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000011001101: wr_addr = `WREG_SP;
+ 12'b000011000100: wr_addr = ( !zero_bit) ? `WREG_SP : `WREG_NUL;
+ 12'b000011001100: wr_addr = ( zero_bit) ? `WREG_SP : `WREG_NUL;
+ 12'b000011010100: wr_addr = (!carry_bit) ? `WREG_SP : `WREG_NUL;
+ 12'b000011011100: wr_addr = ( carry_bit) ? `WREG_SP : `WREG_NUL;
+ 12'b000011100100: wr_addr = ( !par_bit) ? `WREG_SP : `WREG_NUL;
+ 12'b000011101100: wr_addr = ( par_bit) ? `WREG_SP : `WREG_NUL;
+ 12'b000011110100: wr_addr = ( !sign_bit) ? `WREG_SP : `WREG_NUL;
+ 12'b000011111100: wr_addr = ( sign_bit) ? `WREG_SP : `WREG_NUL;
+ default: wr_addr = `WREG_NUL;
+ endcase
+ end
+ `IF3B: wr_addr = `WREG_TMP;
+ `ADR1: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx01110100: wr_addr = `WREG_TMP;
+ default: wr_addr = `WREG_NUL;
+ endcase
+ end
+ `ADR2: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100100,
+ 12'b1xxx10101100: wr_addr = `WREG_HL;
+ 12'b1xxx01100101,
+ 12'b1xxx01100110,
+ 12'b000011xxx111,
+ 12'b000011xx0101,
+ 12'b010011100101,
+ 12'b010111100101: wr_addr = `WREG_SP;
+ 12'b010000110001,
+ 12'b010000110111,
+ 12'b010000111110,
+ 12'b010000111111,
+ 12'b010000xx0111,
+ 12'b010000xx1111,
+ 12'b010100110001,
+ 12'b010100110111,
+ 12'b010100111110,
+ 12'b010100111111,
+ 12'b010100xx0111,
+ 12'b010100xx1111,
+ 12'b000000100010,
+ 12'b000000101010,
+ 12'b010000100010,
+ 12'b010000101010,
+ 12'b010000110100,
+ 12'b010000110101,
+ 12'b010100100010,
+ 12'b010100101010,
+ 12'b010100110100,
+ 12'b010100110101,
+ 12'b1xxx01xx0011,
+ 12'b1xxx01xx1011: wr_addr = `WREG_TMP;
+ default: wr_addr = `WREG_NUL;
+ endcase
+ end
+ `RD1A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10011010,
+ 12'b1xxx100xx011,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011: wr_addr = `WREG_BB;
+ 12'b1xxx10010100,
+ 12'b1xxx10011100,
+ 12'b1xxx10110100,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011,
+ 12'b1xxx10100000,
+ 12'b1xxx10100001,
+ 12'b1xxx10101000,
+ 12'b1xxx10101001,
+ 12'b1xxx10110000,
+ 12'b1xxx10110001,
+ 12'b1xxx10111000,
+ 12'b1xxx10111001: wr_addr = `WREG_BC;
+ default: wr_addr = `WREG_NUL;
+ endcase
+ end
+ `RD1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000011001001,
+ 12'b000011xxx000,
+ 12'b000011xx0001,
+ 12'b010011100001,
+ 12'b010111100001,
+ 12'b1xxx01000101,
+ 12'b1xxx01001101: wr_addr = `WREG_SP;
+ default: wr_addr = `WREG_NUL;
+ endcase
+ end
+ `RD2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10011010,
+ 12'b1xxx10100100,
+ 12'b1xxx10101100,
+ 12'b1xxx100xx011,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011: wr_addr = `WREG_BB;
+ 12'b1xxx10010100,
+ 12'b1xxx10011100,
+ 12'b1xxx10110100,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011,
+ 12'b1xxx10100000,
+ 12'b1xxx10100001,
+ 12'b1xxx10101000,
+ 12'b1xxx10101001,
+ 12'b1xxx10110000,
+ 12'b1xxx10110001,
+ 12'b1xxx10111000,
+ 12'b1xxx10111001: wr_addr = `WREG_BC;
+ default: wr_addr = `WREG_NUL;
+ endcase
+ end
+ `RD2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx100xx011: wr_addr = `WREG_CC;
+ 12'b1xxx10110100,
+ 12'b1xxx10111100,
+ 12'b1xxx10100000,
+ 12'b1xxx10101000,
+ 12'b1xxx10110000,
+ 12'b1xxx10111000: wr_addr = `WREG_DE;
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011100,
+ 12'b1xxx10100010,
+ 12'b1xxx10101010,
+ 12'b1xxx10110010,
+ 12'b1xxx10111010,
+ 12'b1xxx11000010,
+ 12'b1xxx11001010: wr_addr = `WREG_HL;
+ 12'b000011001001,
+ 12'b000011xxx000,
+ 12'b000011xx0001,
+ 12'b0001xxxxxxxx,
+ 12'b010011100001,
+ 12'b010111100001,
+ 12'b1xxx01000101,
+ 12'b1xxx01001101: wr_addr = `WREG_SP;
+ default: wr_addr = `WREG_NUL;
+ endcase
+ end
+ `WR1A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx01100101,
+ 12'b1xxx01100110: wr_addr = `WREG_TMP;
+ default: wr_addr = `WREG_NUL;
+ endcase
+ end
+ `WR1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100100,
+ 12'b1xxx10101100: wr_addr = `WREG_BB;
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10011010: wr_addr = `WREG_CC;
+ 12'b1xxx10010100,
+ 12'b1xxx10011100: wr_addr = `WREG_DE;
+ 12'b1xxx10110100,
+ 12'b1xxx10111100,
+ 12'b1xxx11000011,
+ 12'b1xxx11001011,
+ 12'b1xxx100xx011,
+ 12'b1xxx10100000,
+ 12'b1xxx10100011,
+ 12'b1xxx10101000,
+ 12'b1xxx10101011,
+ 12'b1xxx10110000,
+ 12'b1xxx10110011,
+ 12'b1xxx10111000,
+ 12'b1xxx10111011: wr_addr = `WREG_HL;
+ 12'b1xxx01100101,
+ 12'b1xxx01100110,
+ 12'b000011001101,
+ 12'b000011xxx100,
+ 12'b000011xxx111,
+ 12'b000011xx0101,
+ 12'b0001xxxxxxxx,
+ 12'b010011100101,
+ 12'b010111100101: wr_addr = `WREG_SP;
+ default: wr_addr = `WREG_NUL;
+ endcase
+ end
+ `WR2B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10011010: wr_addr = `WREG_CC;
+ 12'b1xxx10010100,
+ 12'b1xxx10011100: wr_addr = `WREG_DE;
+ 12'b1xxx10100100,
+ 12'b1xxx10101100,
+ 12'b1xxx10110100,
+ 12'b1xxx10111100,
+ 12'b1xxx11000011,
+ 12'b1xxx11001011,
+ 12'b1xxx100xx011,
+ 12'b1xxx10100000,
+ 12'b1xxx10100011,
+ 12'b1xxx10101000,
+ 12'b1xxx10101011,
+ 12'b1xxx10110000,
+ 12'b1xxx10110011,
+ 12'b1xxx10111000,
+ 12'b1xxx10111011: wr_addr = `WREG_HL;
+ default: wr_addr = `WREG_NUL;
+ endcase
+ end
+ `BLK2: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100001,
+ 12'b1xxx10101001,
+ 12'b1xxx10110001,
+ 12'b1xxx10111001: wr_addr = `WREG_HL;
+ default: wr_addr = `WREG_NUL;
+ endcase
+ end
+ `IF1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000000111,
+ 12'b000000001010,
+ 12'b000000001111,
+ 12'b000000010111,
+ 12'b000000011010,
+ 12'b000000011111,
+ 12'b000000100111,
+ 12'b000000101111,
+ 12'b000000111010,
+ 12'b00000011110x,
+ 12'b000000111110,
+ 12'b000001111xxx,
+ 12'b000010000xxx,
+ 12'b000010001xxx,
+ 12'b000010010xxx,
+ 12'b000010011xxx,
+ 12'b000010100xxx,
+ 12'b000010101xxx,
+ 12'b000010110xxx,
+ 12'b000011000110,
+ 12'b000011001110,
+ 12'b000011010110,
+ 12'b000011011011,
+ 12'b000011011110,
+ 12'b000011100110,
+ 12'b000011101110,
+ 12'b000011110110,
+ 12'b001000xxx111,
+ 12'b00101xxxx111,
+ 12'b010010000100,
+ 12'b010010000101,
+ 12'b010010000110,
+ 12'b010010001100,
+ 12'b010010001101,
+ 12'b010010001110,
+ 12'b010010010100,
+ 12'b010010010101,
+ 12'b010010010110,
+ 12'b010010011100,
+ 12'b010010011101,
+ 12'b010010011110,
+ 12'b010010100100,
+ 12'b010010100101,
+ 12'b010010100110,
+ 12'b010010101100,
+ 12'b010010101101,
+ 12'b010010101110,
+ 12'b010010110100,
+ 12'b010010110101,
+ 12'b010010110110,
+ 12'b010110000100,
+ 12'b010110000101,
+ 12'b010110000110,
+ 12'b010110001100,
+ 12'b010110001101,
+ 12'b010110001110,
+ 12'b010110010100,
+ 12'b010110010101,
+ 12'b010110010110,
+ 12'b010110011100,
+ 12'b010110011101,
+ 12'b010110011110,
+ 12'b010110100100,
+ 12'b010110100101,
+ 12'b010110100110,
+ 12'b010110101100,
+ 12'b010110101101,
+ 12'b010110101110,
+ 12'b010110110100,
+ 12'b010110110101,
+ 12'b010110110110,
+ 12'b010x0111110x,
+ 12'b010x01111110,
+ 12'b1xxx01000100,
+ 12'b1xxx01010111,
+ 12'b1xxx01011111,
+ 12'b1xxx01100111,
+ 12'b1xxx01101111,
+ 12'b1xxx0x111000: wr_addr = `WREG_AA;
+ 12'b000011110001: wr_addr = `WREG_AF;
+ 12'b00000000010x,
+ 12'b000000000110,
+ 12'b000001000xxx,
+ 12'b001000xxx000,
+ 12'b00101xxxx000,
+ 12'b010x0100010x,
+ 12'b010x01000110,
+ 12'b1xxx0x000000,
+ 12'b1xxx10100011,
+ 12'b1xxx10101011,
+ 12'b1xxx10110011,
+ 12'b1xxx10111011: wr_addr = `WREG_BB;
+ 12'b010000000111,
+ 12'b010100000111,
+ 12'b1xxx00000111,
+ 12'b1xxx00000010,
+ 12'b1xxx00000011,
+ 12'b000000000001,
+ 12'b00000000x011,
+ 12'b000011000001,
+ 12'b1xxx01001100,
+ 12'b1xxx01001011: wr_addr = `WREG_BC;
+ 12'b1xxx10100100,
+ 12'b1xxx10101100,
+ 12'b00000000110x,
+ 12'b000000001110,
+ 12'b000001001xxx,
+ 12'b001000xxx001,
+ 12'b00101xxxx001,
+ 12'b010x0100110x,
+ 12'b010x01001110,
+ 12'b1xxx100xx011,
+ 12'b1xxx0x001000: wr_addr = `WREG_CC;
+ 12'b00000001010x,
+ 12'b000000010110,
+ 12'b000001010xxx,
+ 12'b001000xxx010,
+ 12'b00101xxxx010,
+ 12'b010x0101010x,
+ 12'b010x01010110,
+ 12'b1xxx0x010000: wr_addr = `WREG_DD;
+ 12'b010000010111,
+ 12'b010100010111,
+ 12'b1xxx00010111,
+ 12'b1xxx10110100,
+ 12'b1xxx10111100,
+ 12'b1xxx00010010,
+ 12'b1xxx00010011,
+ 12'b000011010001,
+ 12'b00000001x011,
+ 12'b000000010001,
+ 12'b1xxx01011100,
+ 12'b1xxx01011011,
+ 12'b1xxx10100000,
+ 12'b1xxx10101000,
+ 12'b1xxx10110000,
+ 12'b1xxx10111000: wr_addr = `WREG_DE;
+ 12'b000011101011: wr_addr = `WREG_DEHL;
+ 12'b00000001110x,
+ 12'b000000011110,
+ 12'b000001011xxx,
+ 12'b001000xxx011,
+ 12'b00101xxxx011,
+ 12'b010x0101110x,
+ 12'b010x01011110,
+ 12'b1xxx0x011000: wr_addr = `WREG_EE;
+ 12'b00000010010x,
+ 12'b000000100110,
+ 12'b000001100xxx,
+ 12'b001000xxx100,
+ 12'b00101xxxx100,
+ 12'b010x01100110,
+ 12'b1xxx0x100000: wr_addr = `WREG_HH;
+ 12'b010000100111,
+ 12'b010100100111,
+ 12'b1xxx00100010,
+ 12'b1xxx00100011,
+ 12'b1xxx00100111,
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011100,
+ 12'b000000100001,
+ 12'b000000101010,
+ 12'b00000010x011,
+ 12'b000000xx1001,
+ 12'b000011100001,
+ 12'b000011100011,
+ 12'b1xxx01101100,
+ 12'b1xxx01101011,
+ 12'b1xxx01xx0010,
+ 12'b1xxx01xx1010,
+ 12'b1xxx10100010,
+ 12'b1xxx10101010,
+ 12'b1xxx10110010,
+ 12'b1xxx10111010,
+ 12'b1xxx11000010,
+ 12'b1xxx11001010: wr_addr = `WREG_HL;
+ 12'b1xxx01000111: wr_addr = `WREG_II;
+ 12'b010000110111,
+ 12'b010100110001,
+ 12'b1xxx00110111,
+ 12'b1xxx00110010,
+ 12'b1xxx01010100,
+ 12'b010000100001,
+ 12'b010000100011,
+ 12'b010000101010,
+ 12'b010000101011,
+ 12'b010000xx1001,
+ 12'b010011100001,
+ 12'b010011100011: wr_addr = `WREG_IX;
+ 12'b010000100100,
+ 12'b010000100101,
+ 12'b010000100110,
+ 12'b0100011000xx,
+ 12'b01000110010x,
+ 12'b010001100111: wr_addr = `WREG_IXH;
+ 12'b010000101100,
+ 12'b010000101101,
+ 12'b010000101110,
+ 12'b0100011010xx,
+ 12'b01000110110x,
+ 12'b010001101111: wr_addr = `WREG_IXL;
+ 12'b010000110001,
+ 12'b010100110111,
+ 12'b1xxx00110110,
+ 12'b1xxx00110011,
+ 12'b1xxx01010101,
+ 12'b010100100001,
+ 12'b010100100011,
+ 12'b010100101010,
+ 12'b010100101011,
+ 12'b010100xx1001,
+ 12'b010111100001,
+ 12'b010111100011: wr_addr = `WREG_IY;
+ 12'b010100100100,
+ 12'b010100100101,
+ 12'b010100100110,
+ 12'b0101011000xx,
+ 12'b01010110010x,
+ 12'b010101100111: wr_addr = `WREG_IYH;
+ 12'b010100101100,
+ 12'b010100101101,
+ 12'b010100101110,
+ 12'b0101011010xx,
+ 12'b01010110110x,
+ 12'b010101101111: wr_addr = `WREG_IYL;
+ 12'b00000010110x,
+ 12'b000000101110,
+ 12'b000001101xxx,
+ 12'b001000xxx101,
+ 12'b00101xxxx101,
+ 12'b010x01101110,
+ 12'b1xxx0x101000: wr_addr = `WREG_LL;
+ 12'b1xxx01001111: wr_addr = `WREG_RR;
+ 12'b000000110001,
+ 12'b00000011x011,
+ 12'b000011111001,
+ 12'b010x11111001,
+ 12'b1xxx01111100,
+ 12'b1xxx01111011: wr_addr = `WREG_SP;
+ default: wr_addr = `WREG_NUL;
+ endcase
+ end
+ `INTB: wr_addr = (vector_int) ? `WREG_TMP : `WREG_SP;
+ default: wr_addr = `WREG_NUL;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* s flag control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg) //synopsys parallel_case
+ `WR2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000110100,
+ 12'b000000110101,
+ 12'b001000xxxxxx,
+ 12'b010000110100,
+ 12'b010000110101,
+ 12'b010100110100,
+ 12'b010100110101,
+ 12'b011x00xxxxxx: sflg_en = 1'b1;
+ default: sflg_en = 1'b0;
+ endcase
+ end
+ `BLK1: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100001,
+ 12'b1xxx10101001,
+ 12'b1xxx10110001,
+ 12'b1xxx10111001: sflg_en = 1'b1;
+ default: sflg_en = 1'b0;
+ endcase
+ end
+ `IF1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000100111,
+ 12'b0000000xx100,12'b00000010x100,12'b000000111100,
+ 12'b0000000xx101,12'b00000010x101,12'b000000111101,
+ 12'b000010000110,
+ 12'b000010000xxx,
+ 12'b000010001110,
+ 12'b000010001xxx,
+ 12'b000010010110,
+ 12'b000010010xxx,
+ 12'b000010011110,
+ 12'b000010011xxx,
+ 12'b000010100110,
+ 12'b000010100xxx,
+ 12'b000010101110,
+ 12'b000010101xxx,
+ 12'b000010110110,
+ 12'b000010110xxx,
+ 12'b000010111110,
+ 12'b000010111xxx,
+ 12'b000011000110,
+ 12'b000011001110,
+ 12'b000011010110,
+ 12'b000011011110,
+ 12'b000011100110,
+ 12'b000011101110,
+ 12'b000011110110,
+ 12'b000011111110,
+ 12'b001000xxx0xx,
+ 12'b001000xxx10x,
+ 12'b001000xxx111,
+ 12'b010000100100,
+ 12'b010000100101,
+ 12'b010000101100,
+ 12'b010000101101,
+ 12'b010010000100,
+ 12'b010010000101,
+ 12'b010010000110,
+ 12'b010010001100,
+ 12'b010010001101,
+ 12'b010010001110,
+ 12'b010010010100,
+ 12'b010010010101,
+ 12'b010010010110,
+ 12'b010010011100,
+ 12'b010010011101,
+ 12'b010010011110,
+ 12'b010010100100,
+ 12'b010010100101,
+ 12'b010010100110,
+ 12'b010010101100,
+ 12'b010010101101,
+ 12'b010010101110,
+ 12'b010010110100,
+ 12'b010010110101,
+ 12'b010010110110,
+ 12'b010010111100,
+ 12'b010010111101,
+ 12'b010010111110,
+ 12'b010100100100,
+ 12'b010100100101,
+ 12'b010100101100,
+ 12'b010100101101,
+ 12'b010110000100,
+ 12'b010110000101,
+ 12'b010110000110,
+ 12'b010110001100,
+ 12'b010110001101,
+ 12'b010110001110,
+ 12'b010110010100,
+ 12'b010110010101,
+ 12'b010110010110,
+ 12'b010110011100,
+ 12'b010110011101,
+ 12'b010110011110,
+ 12'b010110100100,
+ 12'b010110100101,
+ 12'b010110100110,
+ 12'b010110101100,
+ 12'b010110101101,
+ 12'b010110101110,
+ 12'b010110110100,
+ 12'b010110110101,
+ 12'b010110110110,
+ 12'b010110111100,
+ 12'b010110111101,
+ 12'b010110111110,
+ 12'b1xxx00110100,
+ 12'b1xxx00xxxx00,
+ 12'b1xxx011x0100,
+ 12'b1xxx01000100,
+ 12'b1xxx01010111,
+ 12'b1xxx01011111,
+ 12'b1xxx01100111,
+ 12'b1xxx01101111,
+ 12'b1xxx01xxx000,
+ 12'b1xxx01xx0010,
+ 12'b1xxx01xx1010: sflg_en = 1'b1;
+ default: sflg_en = 1'b0;
+ endcase
+ end
+ default: sflg_en = 1'b0;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* z flag control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg) //synopsys parallel_case
+ `RD1A,
+ `RD2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011100,
+ 12'b1xxx10110100,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011,
+ 12'b1xxx100xx011,
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011: zflg_en = 1'b1;
+ default: zflg_en = 1'b0;
+ endcase
+ end
+ `WR1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100100,
+ 12'b1xxx10101100: zflg_en = 1'b1;
+ default: zflg_en = 1'b0;
+ endcase
+ end
+ `WR2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000110100,
+ 12'b000000110101,
+ 12'b001000xxxxxx,
+ 12'b010000110100,
+ 12'b010000110101,
+ 12'b010100110100,
+ 12'b010100110101,
+ 12'b011x00xxxxxx: zflg_en = 1'b1;
+ default: zflg_en = 1'b0;
+ endcase
+ end
+ `BLK1: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100001,
+ 12'b1xxx10101001,
+ 12'b1xxx10110001,
+ 12'b1xxx10111001: zflg_en = 1'b1;
+ default: zflg_en = 1'b0;
+ endcase
+ end
+ `IF1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000100111,
+ 12'b0000000xx100,12'b00000010x100,12'b000000111100,
+ 12'b0000000xx101,12'b00000010x101,12'b000000111101,
+ 12'b000010000110,
+ 12'b000010000xxx,
+ 12'b000010001110,
+ 12'b000010001xxx,
+ 12'b000010010110,
+ 12'b000010010xxx,
+ 12'b000010011110,
+ 12'b000010011xxx,
+ 12'b000010100110,
+ 12'b000010100xxx,
+ 12'b000010101110,
+ 12'b000010101xxx,
+ 12'b000010110110,
+ 12'b000010110xxx,
+ 12'b000010111110,
+ 12'b000010111xxx,
+ 12'b000011000110,
+ 12'b000011001110,
+ 12'b000011010110,
+ 12'b000011011110,
+ 12'b000011100110,
+ 12'b000011101110,
+ 12'b000011110110,
+ 12'b000011111110,
+ 12'b001000xxx0xx,12'b001000xxx10x,12'b001000xxx111,
+ 12'b001001xxx110,
+ 12'b001001xxxxxx,
+ 12'b010000100100,
+ 12'b010000100101,
+ 12'b010000101100,
+ 12'b010000101101,
+ 12'b010010000100,
+ 12'b010010000101,
+ 12'b010010000110,
+ 12'b010010001100,
+ 12'b010010001101,
+ 12'b010010001110,
+ 12'b010010010100,
+ 12'b010010010101,
+ 12'b010010010110,
+ 12'b010010011100,
+ 12'b010010011101,
+ 12'b010010011110,
+ 12'b010010100100,
+ 12'b010010100101,
+ 12'b010010100110,
+ 12'b010010101100,
+ 12'b010010101101,
+ 12'b010010101110,
+ 12'b010010110100,
+ 12'b010010110101,
+ 12'b010010110110,
+ 12'b010010111100,
+ 12'b010010111101,
+ 12'b010010111110,
+ 12'b010100100100,
+ 12'b010100100101,
+ 12'b010100101100,
+ 12'b010100101101,
+ 12'b010110000100,
+ 12'b010110000101,
+ 12'b010110000110,
+ 12'b010110001100,
+ 12'b010110001101,
+ 12'b010110001110,
+ 12'b010110010100,
+ 12'b010110010101,
+ 12'b010110010110,
+ 12'b010110011100,
+ 12'b010110011101,
+ 12'b010110011110,
+ 12'b010110100100,
+ 12'b010110100101,
+ 12'b010110100110,
+ 12'b010110101100,
+ 12'b010110101101,
+ 12'b010110101110,
+ 12'b010110110100,
+ 12'b010110110101,
+ 12'b010110110110,
+ 12'b010110111100,
+ 12'b010110111101,
+ 12'b010110111110,
+ 12'b011001xxx110,
+ 12'b011101xxx110,
+ 12'b1xxx00xxxx00,
+ 12'b1xxx01000100,
+ 12'b1xxx01010111,
+ 12'b1xxx01011111,
+ 12'b1xxx01100111,
+ 12'b1xxx01101111,
+ 12'b1xxx011x0100,
+ 12'b1xxx01xxx000,
+ 12'b1xxx01xx0010,
+ 12'b1xxx01xx1010,
+ 12'b1xxx10100011,
+ 12'b1xxx10101011,
+ 12'b1xxx10110011,
+ 12'b1xxx10111011: zflg_en = 1'b1;
+ default: zflg_en = 1'b0;
+ endcase
+ end
+ default: zflg_en = 1'b0;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* h flag control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg) //synopsys parallel_case
+ `WR2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b001000xxxxxx,
+ 12'b011x00xxxxxx,
+ 12'b1xxx01100111,
+ 12'b1xxx01101111: hflg_ctl = `HFLG_0;
+ 12'b000000110100,
+ 12'b000000110101,
+ 12'b010x00110100,
+ 12'b010x00110101: hflg_ctl = `HFLG_H;
+ default: hflg_ctl = `HFLG_NUL;
+ endcase
+ end
+ `BLK1: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100001,
+ 12'b1xxx10101001,
+ 12'b1xxx10110001,
+ 12'b1xxx10111001: hflg_ctl = `HFLG_H;
+ default: hflg_ctl = `HFLG_NUL;
+ endcase
+ end
+ `IF1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000000111,
+ 12'b000000001111,
+ 12'b000000010111,
+ 12'b000000011111,
+ 12'b000000110111,
+ 12'b000010101110,
+ 12'b000010101xxx,
+ 12'b000010110110,
+ 12'b000010110xxx,
+ 12'b000011101110,
+ 12'b000011110110,
+ 12'b001000000xxx,
+ 12'b001000001xxx,
+ 12'b001000010xxx,
+ 12'b001000011xxx,
+ 12'b001000100xxx,
+ 12'b001000101xxx,
+ 12'b001000110xxx,
+ 12'b001000111xxx,
+ 12'b010010101100,
+ 12'b010010101101,
+ 12'b010010101110,
+ 12'b010010110100,
+ 12'b010010110101,
+ 12'b010010110110,
+ 12'b010110101100,
+ 12'b010110101101,
+ 12'b010110101110,
+ 12'b010110110100,
+ 12'b010110110101,
+ 12'b010110110110,
+ 12'b1xxx00xxx000,
+ 12'b1xxx01010111,
+ 12'b1xxx01011111,
+ 12'b1xxx01xxx000,
+ 12'b1xxx10100000,
+ 12'b1xxx10101000,
+ 12'b1xxx10110000,
+ 12'b1xxx10111000: hflg_ctl = `HFLG_0;
+ 12'b000000101111,
+ 12'b000010100110,
+ 12'b000010100xxx,
+ 12'b000011100110,
+ 12'b001001xxx110,
+ 12'b001001xxxxxx,
+ 12'b010010100100,
+ 12'b010010100101,
+ 12'b010010100110,
+ 12'b010110100100,
+ 12'b010110100101,
+ 12'b010110100110,
+ 12'b011001xxx110,
+ 12'b011101xxx110,
+ 12'b1xxx00xxx100,
+ 12'b1xxx011x0100: hflg_ctl = `HFLG_1;
+ 12'b000000111111,
+ 12'b000000100111,
+ 12'b0000000xx100,12'b00000010x100,12'b000000111100,
+ 12'b0000000xx101,12'b00000010x101,12'b000000111101,
+ 12'b000000xx1001,
+ 12'b000010000110,
+ 12'b000010000xxx,
+ 12'b000010001110,
+ 12'b000010001xxx,
+ 12'b000010010110,
+ 12'b000010010xxx,
+ 12'b000010011110,
+ 12'b000010011xxx,
+ 12'b000010111110,
+ 12'b000010111xxx,
+ 12'b000011000110,
+ 12'b000011001110,
+ 12'b000011010110,
+ 12'b000011011110,
+ 12'b000011111110,
+ 12'b010000100100,
+ 12'b010000100101,
+ 12'b010000101100,
+ 12'b010000101101,
+ 12'b010000xx1001,
+ 12'b010010000100,
+ 12'b010010000101,
+ 12'b010010000110,
+ 12'b010010001100,
+ 12'b010010001101,
+ 12'b010010001110,
+ 12'b010010010100,
+ 12'b010010010101,
+ 12'b010010010110,
+ 12'b010010011100,
+ 12'b010010011101,
+ 12'b010010011110,
+ 12'b010010111100,
+ 12'b010010111101,
+ 12'b010010111110,
+ 12'b010100100100,
+ 12'b010100100101,
+ 12'b010100101100,
+ 12'b010100101101,
+ 12'b010100xx1001,
+ 12'b010110000100,
+ 12'b010110000101,
+ 12'b010110000110,
+ 12'b010110001100,
+ 12'b010110001101,
+ 12'b010110001110,
+ 12'b010110010100,
+ 12'b010110010101,
+ 12'b010110010110,
+ 12'b010110011100,
+ 12'b010110011101,
+ 12'b010110011110,
+ 12'b010110111100,
+ 12'b010110111101,
+ 12'b010110111110,
+ 12'b1xxx01000100,
+ 12'b1xxx01xx0010,
+ 12'b1xxx01xx1010: hflg_ctl = `HFLG_H;
+ default: hflg_ctl = `HFLG_NUL;
+ endcase
+ end
+ default: hflg_ctl = `HFLG_NUL;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* pv flag control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg) //synopsys parallel_case
+ `RD1A,
+ `RD2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100000,
+ 12'b1xxx10100001,
+ 12'b1xxx10101000,
+ 12'b1xxx10101001,
+ 12'b1xxx10110000,
+ 12'b1xxx10110001,
+ 12'b1xxx10111000,
+ 12'b1xxx10111001: pflg_ctl = `PFLG_B;
+ default: pflg_ctl = `PFLG_NUL;
+ endcase
+ end
+ `WR2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b001000xxxxxx,
+ 12'b011x00xxxxxx: pflg_ctl = `PFLG_P;
+ 12'b000000110100,
+ 12'b000000110101,
+ 12'b010000110100,
+ 12'b010000110101,
+ 12'b010100110100,
+ 12'b010100110101: pflg_ctl = `PFLG_V;
+ default: pflg_ctl = `PFLG_NUL;
+ endcase
+ end
+ `IF1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx01010111,
+ 12'b1xxx01011111: pflg_ctl = `PFLG_F;
+ 12'b000000100111,
+ 12'b000010100110,
+ 12'b000010100xxx,
+ 12'b000010101110,
+ 12'b000010101xxx,
+ 12'b000010110110,
+ 12'b000010110xxx,
+ 12'b000011100110,
+ 12'b000011101110,
+ 12'b000011110110,
+ 12'b001000xxx0xx,12'b001000xxx10x,12'b001000xxx111,
+ 12'b010010100100,
+ 12'b010010100101,
+ 12'b010010100110,
+ 12'b010010101100,
+ 12'b010010101101,
+ 12'b010010101110,
+ 12'b010010110100,
+ 12'b010010110101,
+ 12'b010010110110,
+ 12'b010110100100,
+ 12'b010110100101,
+ 12'b010110100110,
+ 12'b010110101100,
+ 12'b010110101101,
+ 12'b010110101110,
+ 12'b010110110100,
+ 12'b010110110101,
+ 12'b010110110110,
+ 12'b1xxx00xxxx00,
+ 12'b1xxx00110100,
+ 12'b1xxx011x0100,
+ 12'b1xxx01100111,
+ 12'b1xxx01101111,
+ 12'b1xxx01xxx000: pflg_ctl = `PFLG_P;
+ 12'b0000000xx100,12'b00000010x100,12'b000000111100,
+ 12'b0000000xx101,12'b00000010x101,12'b000000111101,
+ 12'b000010000110,
+ 12'b000010000xxx,
+ 12'b000010001110,
+ 12'b000010001xxx,
+ 12'b000010010110,
+ 12'b000010010xxx,
+ 12'b000010011110,
+ 12'b000010011xxx,
+ 12'b000010111110,
+ 12'b000010111xxx,
+ 12'b000011000110,
+ 12'b000011001110,
+ 12'b000011010110,
+ 12'b000011011110,
+ 12'b000011111110,
+ 12'b010000100100,
+ 12'b010000100101,
+ 12'b010000101100,
+ 12'b010000101101,
+ 12'b010010000100,
+ 12'b010010000101,
+ 12'b010010000110,
+ 12'b010010001100,
+ 12'b010010001101,
+ 12'b010010001110,
+ 12'b010010010100,
+ 12'b010010010101,
+ 12'b010010010110,
+ 12'b010010011100,
+ 12'b010010011101,
+ 12'b010010011110,
+ 12'b010010111100,
+ 12'b010010111101,
+ 12'b010010111110,
+ 12'b010100100100,
+ 12'b010100100101,
+ 12'b010100101100,
+ 12'b010100101101,
+ 12'b010110000100,
+ 12'b010110000101,
+ 12'b010110000110,
+ 12'b010110001100,
+ 12'b010110001101,
+ 12'b010110001110,
+ 12'b010110010100,
+ 12'b010110010101,
+ 12'b010110010110,
+ 12'b010110011100,
+ 12'b010110011101,
+ 12'b010110011110,
+ 12'b010110111100,
+ 12'b010110111101,
+ 12'b010110111110,
+ 12'b1xxx01000100,
+ 12'b1xxx01xx0010,
+ 12'b1xxx01xx1010: pflg_ctl = `PFLG_V;
+ default: pflg_ctl = `PFLG_NUL;
+ endcase
+ end
+ default: pflg_ctl = `PFLG_NUL;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* n flag control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg) //synopsys parallel_case
+ `WR1A,
+ `WR2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b1xxx10100010,
+ 12'b1xxx10100011,
+ 12'b1xxx10101010,
+ 12'b1xxx10101011,
+ 12'b1xxx10110010,
+ 12'b1xxx10110011,
+ 12'b1xxx10111010,
+ 12'b1xxx10111011: nflg_ctl = `NFLG_S;
+ default: nflg_ctl = `NFLG_NUL;
+ endcase
+ end
+ `IF1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000000000111,
+ 12'b000000001111,
+ 12'b000000010111,
+ 12'b000000011111,
+ 12'b000000110100,
+ 12'b000000110111,
+ 12'b000000111111,
+ 12'b000000xxx100,
+ 12'b000000xx1001,
+ 12'b000010000110,
+ 12'b000010000xxx,
+ 12'b000010001110,
+ 12'b000010001xxx,
+ 12'b000010100110,
+ 12'b000010100xxx,
+ 12'b000010101110,
+ 12'b000010101xxx,
+ 12'b000010110110,
+ 12'b000010110xxx,
+ 12'b000011000110,
+ 12'b000011001110,
+ 12'b000011100110,
+ 12'b000011101110,
+ 12'b000011110110,
+ 12'b010000100100,
+ 12'b010000101100,
+ 12'b010000110100,
+ 12'b010000xx1001,
+ 12'b010010000100,
+ 12'b010010000101,
+ 12'b010010000110,
+ 12'b010010001100,
+ 12'b010010001101,
+ 12'b010010001110,
+ 12'b010010100100,
+ 12'b010010100101,
+ 12'b010010100110,
+ 12'b010010101100,
+ 12'b010010101101,
+ 12'b010010101110,
+ 12'b010010110100,
+ 12'b010010110101,
+ 12'b010010110110,
+ 12'b010100100100,
+ 12'b010100101100,
+ 12'b010100110100,
+ 12'b010100xx1001,
+ 12'b010110000100,
+ 12'b010110000101,
+ 12'b010110000110,
+ 12'b010110001100,
+ 12'b010110001101,
+ 12'b010110001110,
+ 12'b010110100100,
+ 12'b010110100101,
+ 12'b010110100110,
+ 12'b010110101100,
+ 12'b010110101101,
+ 12'b010110101110,
+ 12'b010110110100,
+ 12'b010110110101,
+ 12'b010110110110,
+ 12'b00100xxxxxxx,
+ 12'b011x0xxxxxxx,
+ 12'b1xxx00xxxx00,
+ 12'b1xxx00110100,
+ 12'b1xxx011x0100,
+ 12'b1xxx01010111,
+ 12'b1xxx01011111,
+ 12'b1xxx01100111,
+ 12'b1xxx01101111,
+ 12'b1xxx01xxx000,
+ 12'b1xxx01xx1010,
+ 12'b1xxx10100000,
+ 12'b1xxx10101000,
+ 12'b1xxx10110000,
+ 12'b1xxx10111000: nflg_ctl = `NFLG_0;
+ 12'b1xxx10000010,
+ 12'b1xxx10000100,
+ 12'b1xxx10001010,
+ 12'b1xxx10001100,
+ 12'b1xxx10010010,
+ 12'b1xxx10010100,
+ 12'b1xxx10011010,
+ 12'b1xxx10011100,
+ 12'b1xxx10100100,
+ 12'b1xxx10101100,
+ 12'b1xxx10110100,
+ 12'b1xxx10111100,
+ 12'b1xxx11000010,
+ 12'b1xxx11000011,
+ 12'b1xxx11001010,
+ 12'b1xxx11001011,
+ 12'b000000101111,
+ 12'b000000110101,
+ 12'b000000xxx101,
+ 12'b000010010110,
+ 12'b000010010xxx,
+ 12'b000010011110,
+ 12'b000010011xxx,
+ 12'b000010111110,
+ 12'b000010111xxx,
+ 12'b000011010110,
+ 12'b000011011110,
+ 12'b000011111110,
+ 12'b010000100101,
+ 12'b010000101101,
+ 12'b010000110101,
+ 12'b010010010100,
+ 12'b010010010101,
+ 12'b010010010110,
+ 12'b010010011100,
+ 12'b010010011101,
+ 12'b010010011110,
+ 12'b010010111100,
+ 12'b010010111101,
+ 12'b010010111110,
+ 12'b010100100101,
+ 12'b010100101101,
+ 12'b010100110101,
+ 12'b010110010100,
+ 12'b010110010101,
+ 12'b010110010110,
+ 12'b010110011100,
+ 12'b010110011101,
+ 12'b010110011110,
+ 12'b010110111100,
+ 12'b010110111101,
+ 12'b010110111110,
+ 12'b1xxx01000100,
+ 12'b1xxx01xx0010,
+ 12'b1xxx100xx011,
+ 12'b1xxx10100001,
+ 12'b1xxx10101001,
+ 12'b1xxx10110001,
+ 12'b1xxx10111001: nflg_ctl = `NFLG_1;
+ default: nflg_ctl = `NFLG_NUL;
+ endcase
+ end
+ default: nflg_ctl = `NFLG_NUL;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* c flag control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg) //synopsys parallel_case
+ `WR2A: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b001000xxxxxx,
+ 12'b011x00xxxxxx: cflg_en = 1'b1;
+ default: cflg_en = 1'b0;
+ endcase
+ end
+ `IF1B: begin
+ casex ({page_reg, inst_reg}) //synopsys parallel_case
+ 12'b000010100110,
+ 12'b000010100xxx,
+ 12'b000010101110,
+ 12'b000010101xxx,
+ 12'b000010110110,
+ 12'b000010110xxx,
+ 12'b000011100110,
+ 12'b000011101110,
+ 12'b000011110110,
+ 12'b010010100100,
+ 12'b010010100101,
+ 12'b010010100110,
+ 12'b010010101100,
+ 12'b010010101101,
+ 12'b010010101110,
+ 12'b010010110100,
+ 12'b010010110101,
+ 12'b010010110110,
+ 12'b010110100100,
+ 12'b010110100101,
+ 12'b010110100110,
+ 12'b010110101100,
+ 12'b010110101101,
+ 12'b010110101110,
+ 12'b010110110100,
+ 12'b010110110101,
+ 12'b010110110110,
+ 12'b000000110111,
+ 12'b000000000111,
+ 12'b000000001111,
+ 12'b000000010111,
+ 12'b000000011111,
+ 12'b000000100111,
+ 12'b000000111111,
+ 12'b000000xx1001,
+ 12'b000010000110,
+ 12'b000010000xxx,
+ 12'b000010001110,
+ 12'b000010001xxx,
+ 12'b000010010110,
+ 12'b000010010xxx,
+ 12'b000010011110,
+ 12'b000010011xxx,
+ 12'b000010111110,
+ 12'b000010111xxx,
+ 12'b000011000110,
+ 12'b000011001110,
+ 12'b000011010110,
+ 12'b000011011110,
+ 12'b000011111110,
+ 12'b001000xxx0xx,12'b001000xxx10x,12'b001000xxx111,
+ 12'b010000xx1001,
+ 12'b010010000100,
+ 12'b010010000101,
+ 12'b010010000110,
+ 12'b010010001100,
+ 12'b010010001101,
+ 12'b010010001110,
+ 12'b010010010100,
+ 12'b010010010101,
+ 12'b010010010110,
+ 12'b010010011100,
+ 12'b010010011101,
+ 12'b010010011110,
+ 12'b010010111100,
+ 12'b010010111101,
+ 12'b010010111110,
+ 12'b010100xx1001,
+ 12'b010110000100,
+ 12'b010110000101,
+ 12'b010110000110,
+ 12'b010110001100,
+ 12'b010110001101,
+ 12'b010110001110,
+ 12'b010110010100,
+ 12'b010110010101,
+ 12'b010110010110,
+ 12'b010110011100,
+ 12'b010110011101,
+ 12'b010110011110,
+ 12'b010110111100,
+ 12'b010110111101,
+ 12'b010110111110,
+ 12'b1xxx00xxxx00,
+ 12'b1xxx00110100,
+ 12'b1xxx011x0100,
+ 12'b1xxx01000100,
+ 12'b1xxx01xx0010,
+ 12'b1xxx01xx1010: cflg_en = 1'b1;
+ default: cflg_en = 1'b0;
+ endcase
+ end
+ default: cflg_en = 1'b0;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* temporary flag control */
+ /* */
+ /*****************************************************************************************/
+ always @ (inst_reg or page_reg or state_reg) begin
+ casex (state_reg) //synopsys parallel_case
+ `OF1B: tflg_ctl = `TFLG_Z;
+ `RD1A,
+ `RD2A: begin
+ casex ({page_reg, inst_reg})
+ 12'b1xxx10100011,
+ 12'b1xxx10101011,
+ 12'b1xxx10110011,
+ 12'b1xxx10111011: tflg_ctl = `TFLG_1;
+ default: tflg_ctl = `TFLG_Z;
+ endcase
+ end
+ `BLK1: tflg_ctl = `TFLG_B;
+ default: tflg_ctl = `TFLG_NUL;
+ endcase
+ end
+
+ endmodule
+
+
+
+
+
Index: tags/ez80-instructions/rtl/top_levl.v
===================================================================
--- tags/ez80-instructions/rtl/top_levl.v (nonexistent)
+++ tags/ez80-instructions/rtl/top_levl.v (revision 9)
@@ -0,0 +1,590 @@
+/*******************************************************************************************/
+/** **/
+/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
+/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
+/** **/
+/** Y80e processor test bench Rev 0.0 06/18/2012 **/
+/** **/
+/*******************************************************************************************/
+`timescale 1ns / 10ps /* set time scale */
+`include "version.v" /* select version */
+`include "hierarchy.v" /* include sources */
+
+module top_levl;
+
+ wire DMA_ACK; /* dma acknowledge */
+ wire HALT_TRAN; /* halt transaction */
+ wire IACK_TRAN; /* int ack transaction */
+ wire IO_READ; /* i/o read/write status */
+ wire IO_STROBE; /* i/o strobe */
+ wire IO_TRAN; /* i/o transaction */
+ wire IVEC_RD; /* int vector read strobe */
+ wire MEM_RD; /* mem read strobe */
+ wire MEM_TRAN; /* mem transaction */
+ wire MEM_WR; /* mem write strobe */
+ wire RETI_TRAN; /* reti transaction */
+ wire T1; /* first clock of transaction */
+ wire [7:0] IO_DATA_OUT; /* i/o data output bus */
+ wire [7:0] MEM_DATA_OUT; /* mem data output bus */
+ wire [15:0] IO_ADDR; /* i/o address bus */
+ wire [15:0] MEM_ADDR; /* mem address bus */
+
+ reg CLEARB; /* master (test) reset */
+ reg CLKC; /* clock */
+ reg DMA_REQ; /* dma request */
+ reg INT_REQ; /* interrupt request */
+ reg NMI_REQ; /* non-maskable interrupt req */
+ reg RESETB; /* internal (user) reset */
+ reg WAIT_REQ; /* wait request */
+ reg [7:0] IO_DATA_IN; /* i/o data input bus */
+ reg [7:0] IVEC_DATA_IN; /* vector input bus */
+ reg [7:0] MEM_DATA_IN; /* mem data input bus */
+
+ /*****************************************************************************************/
+ /* */
+ /* testbench internal variables */
+ /* */
+ /*****************************************************************************************/
+ reg CLR_INT; /* deassert interrupt */
+ reg CLR_NMI; /* deassert nmi */
+ reg DISABLE_BREQ; /* bus req generator control */
+ reg DISABLE_INT; /* interrupt generator control */
+ reg DISABLE_WAIT; /* wait generator control */
+ reg INT_TYPE; /* int type during bus req */
+ reg PAT_DONE; /* pattern done flag */
+ reg TRIG_INT; /* assert interrupt */
+ reg TRIG_NMI; /* assert nmi */
+ reg [3:0] PAT_CNT; /* counter to track patterns */
+ reg [15:0] CMP_ERR_L; /* error counter */
+
+ reg wait_dly; /* wait request state machine */
+ reg [5:0] breq_mach; /* bus request state machine */
+
+ reg TREF0, TREF1, TREF2, TREF3, TREF4; /* timing generator */
+ reg TREF5, TREF6, TREF7, TREF8, TREF9;
+
+ /*****************************************************************************************/
+ /* */
+ /* read memory and write data compare memory */
+ /* */
+ /*****************************************************************************************/
+ reg [7:0] rdmem [0:65535];
+ reg [7:0] wrmem [0:65535];
+
+ wire [7:0] wr_data = (MEM_TRAN) ? wrmem[MEM_ADDR] :
+ (IO_TRAN) ? wrmem[IO_ADDR] : 8'hxx;
+
+ wire [7:0] rd_data = rdmem[MEM_ADDR];
+ wire [7:0] iord_data = rdmem[IO_ADDR];
+
+ always @ (posedge TREF6) begin
+ IO_DATA_IN = (IO_TRAN && IO_READ && IO_STROBE && !WAIT_REQ) ? iord_data : 8'hxx;
+ MEM_DATA_IN = (MEM_TRAN && MEM_RD && !WAIT_REQ) ? rd_data : 8'hxx;
+ end
+
+ always @ (posedge TREF6) begin
+ IVEC_DATA_IN = (IACK_TRAN && IVEC_RD && !WAIT_REQ) ? rd_data : 8'hxx;
+ end
+
+ always @ (posedge TREF0) begin
+ IO_DATA_IN = 8'hxx;
+ MEM_DATA_IN = 8'hxx;
+ IVEC_DATA_IN = 8'hxx;
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* instantiate the design */
+ /* */
+ /*****************************************************************************************/
+ y80_top Y80 ( .dma_ack(DMA_ACK), .halt_tran(HALT_TRAN), .iack_tran(IACK_TRAN),
+ .io_addr_out(IO_ADDR), .io_data_out(IO_DATA_OUT), .io_read(IO_READ),
+ .io_strobe(IO_STROBE), .io_tran(IO_TRAN), .ivec_rd(IVEC_RD),
+ .mem_addr_out(MEM_ADDR), .mem_data_out(MEM_DATA_OUT), .mem_rd(MEM_RD),
+ .mem_tran(MEM_TRAN), .mem_wr(MEM_WR), .reti_tran(RETI_TRAN), .t1(T1),
+ .clearb(CLEARB), .clkc(CLKC), .dma_req(DMA_REQ), .int_req(INT_REQ),
+ .io_data_in(IO_DATA_IN), .ivec_data_in(IVEC_DATA_IN),
+ .mem_data_in(MEM_DATA_IN), .nmi_req(NMI_REQ), .resetb(RESETB),
+ .wait_req(WAIT_REQ) );
+
+ /*****************************************************************************************/
+ /* */
+ /* timing generator */
+ /* */
+ /*****************************************************************************************/
+ initial begin
+ TREF0 = 1;
+ CLKC = 1;
+ end
+
+ always begin
+ #10 TREF0 <= 1'b0;
+ TREF1 <= 1'b1;
+ #10 TREF1 <= 1'b0;
+ TREF2 <= 1'b1;
+ #10 TREF2 <= 1'b0;
+ TREF3 <= 1'b1;
+ #10 TREF3 <= 1'b0;
+ TREF4 <= 1'b1;
+ #10 TREF4 <= 1'b0;
+ TREF5 <= 1'b1;
+ #10 TREF5 <= 1'b0;
+ TREF6 <= 1'b1;
+ #10 TREF6 <= 1'b0;
+ TREF7 <= 1'b1;
+ #10 TREF7 <= 1'b0;
+ TREF8 <= 1'b1;
+ #10 TREF8 <= 1'b0;
+ TREF9 <= 1'b1;
+ #10 TREF9 <= 1'b0;
+ TREF0 <= 1'b1;
+ end
+
+ always @ (posedge TREF3) CLKC = 0;
+ always @ (posedge TREF8) CLKC = 1;
+
+ /*****************************************************************************************/
+ /* */
+ /* initialize input signals */
+ /* */
+ /*****************************************************************************************/
+ initial begin
+ CLEARB = 1;
+ DMA_REQ = 0;
+ INT_REQ = 0;
+ NMI_REQ = 0;
+ RESETB = 1;
+ WAIT_REQ = 0;
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* initialize testbench variables */
+ /* */
+ /*****************************************************************************************/
+ initial begin
+ breq_mach = 6'b000000;
+ CMP_ERR_L = 16'h0000;
+ CLR_INT = 0;
+ CLR_NMI = 0;
+ DISABLE_BREQ = 1;
+ DISABLE_INT = 1;
+ DISABLE_WAIT = 1;
+ INT_TYPE = 0;
+ PAT_DONE = 0;
+ TRIG_INT = 0;
+ TRIG_NMI = 0;
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* reset and clear task */
+ /* */
+ /*****************************************************************************************/
+ task resettask;
+ begin
+ wait(TREF6);
+ RESETB = 0;
+ wait(TREF0);
+ wait(TREF6);
+ wait(TREF0);
+ wait(TREF6);
+ RESETB = 1;
+ CLR_INT = 1;
+ CLR_NMI = 1;
+ wait(TREF0);
+ PAT_DONE = 0;
+ end
+ endtask
+
+ task cleartask;
+ begin
+ wait(TREF6);
+ CLEARB = 0;
+ RESETB = 0;
+ wait(TREF0);
+ wait(TREF6);
+ wait(TREF0);
+ wait(TREF6);
+ CLEARB = 1;
+ RESETB = 1;
+ CLR_INT = 1;
+ CLR_NMI = 1;
+ wait(TREF0);
+ PAT_DONE = 0;
+ end
+ endtask
+
+ /*****************************************************************************************/
+ /* */
+ /* error log */
+ /* */
+ /*****************************************************************************************/
+ always @ (posedge TREF4) begin
+ if (MEM_WR) CMP_ERR_L = CMP_ERR_L + (MEM_DATA_OUT != wr_data);
+ if (!IO_READ && IO_STROBE) CMP_ERR_L = CMP_ERR_L + (IO_DATA_OUT != wr_data);
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* end-of-pattern detect */
+ /* */
+ /*****************************************************************************************/
+ always @ (posedge TREF4) begin
+ PAT_DONE = (MEM_ADDR[15:0] == 16'h00c3);
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* interrupt/nmi request generator */
+ /* */
+ /*****************************************************************************************/
+ always @ (posedge TREF4) begin
+ TRIG_INT = !((MEM_ADDR[15:13] == 3'b110) && (MEM_ADDR[8:0] == 9'h0ff)) ||
+ DISABLE_INT || |breq_mach;
+ TRIG_NMI = !((MEM_ADDR[15:13] == 3'b110) && (MEM_ADDR[8:0] == 9'h1ff)) ||
+ DISABLE_INT || |breq_mach;
+ CLR_INT = (MEM_ADDR[15:13] == 3'b111);
+ CLR_NMI = (MEM_ADDR[15:13] == 3'b111);
+ if (T1) INT_TYPE = MEM_ADDR[8];
+ end
+
+ always @ (negedge TRIG_NMI) begin
+ NMI_REQ = 1;
+ end
+
+ always @ (posedge CLR_NMI) begin
+ NMI_REQ = 0;
+ end
+
+ always @ (negedge TRIG_INT) begin
+ INT_REQ = 1;
+ end
+
+ always @ (posedge CLR_INT) begin
+ wait(TREF0);
+ wait(TREF4);
+ wait(TREF0);
+ wait(TREF4);
+ INT_REQ = 0;
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* interrupt request generator (during Halt) */
+ /* */
+ /*****************************************************************************************/
+ integer j;
+
+ always @ (posedge HALT_TRAN) begin
+ for (j=0; j < 10; j=j+1) begin
+ wait (TREF6);
+ wait (TREF0);
+ end
+ wait (TREF6);
+ INT_REQ = HALT_TRAN && !INT_TYPE;
+ NMI_REQ = HALT_TRAN && INT_TYPE;
+ wait (TREF0);
+ for (j=0; j < 12; j=j+1) begin
+ wait (TREF6);
+ wait (TREF0);
+ end
+ INT_REQ = 0;
+ NMI_REQ = 0;
+ wait (TREF6);
+ wait (TREF0);
+ wait (TREF6);
+ NMI_REQ = HALT_TRAN && INT_TYPE;
+ wait (TREF0);
+ wait (TREF6);
+ wait (TREF0);
+ NMI_REQ = 0;
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* wait request generator */
+ /* */
+ /*****************************************************************************************/
+ always @ (posedge CLKC) begin
+ wait_dly <= T1;
+ end
+
+ always @ (posedge TREF6) WAIT_REQ = !DISABLE_WAIT && (T1 || wait_dly);
+ always @ (posedge TREF9) WAIT_REQ = 1'b0;
+
+ /*****************************************************************************************/
+ /* */
+ /* bus request generator */
+ /* */
+ /*****************************************************************************************/
+ always @ (posedge CLKC) begin
+ breq_mach <= (DISABLE_BREQ) ? 6'b000000 :
+ (T1) ? 6'b000001 : {breq_mach[4:0], wait_dly};
+ end
+
+ always @ (posedge TREF6) DMA_REQ = !DISABLE_BREQ &&
+ (T1 || |breq_mach[2:0] || (HALT_TRAN && |breq_mach));
+
+ /*****************************************************************************************/
+ /* */
+ /* run the test patterns */
+ /* */
+ /*****************************************************************************************/
+ initial begin
+ $readmemh("setup_hl.vm", rdmem);
+ cleartask;
+ wait (PAT_DONE);
+
+ DISABLE_INT = 0; /* interrupt generator on */
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h1;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("int_ops.vm", rdmem);
+ $readmemh("int_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ DISABLE_INT = 1; /* interrupt generator off */
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h2;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("alu_ops.vm", rdmem);
+ $readmemh("alu_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h3;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("dat_mov.vm", rdmem);
+ $readmemh("dat_movd.vm", wrmem);
+ wait (PAT_DONE);
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h4;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("bit_ops.vm", rdmem);
+ $readmemh("bit_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h5;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("jmp_ops.vm", rdmem);
+ $readmemh("jmp_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h6;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("io_ops.vm", rdmem);
+ $readmemh("io_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h7;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("180_ops.vm", rdmem);
+ $readmemh("180_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h8;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("ez8_ops.vm", rdmem);
+ $readmemh("ez8_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ DISABLE_INT = 0; /* interrupt generator on */
+ DISABLE_WAIT = 0; /* wait generator on */
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h1;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("int_ops.vm", rdmem);
+ $readmemh("int_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ DISABLE_INT = 1; /* interrupt generator off */
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h2;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("alu_ops.vm", rdmem);
+ $readmemh("alu_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h3;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("dat_mov.vm", rdmem);
+ $readmemh("dat_movd.vm", wrmem);
+ wait (PAT_DONE);
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h4;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("bit_ops.vm", rdmem);
+ $readmemh("bit_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h5;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("jmp_ops.vm", rdmem);
+ $readmemh("jmp_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h6;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("io_ops.vm", rdmem);
+ $readmemh("io_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h7;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("180_ops.vm", rdmem);
+ $readmemh("180_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h8;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("ez8_ops.vm", rdmem);
+ $readmemh("ez8_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ DISABLE_INT = 0; /* interrupt generator on */
+ DISABLE_BREQ = 0; /* bus req generator on */
+ DISABLE_WAIT = 1; /* wait generator off */
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h1;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("int_ops.vm", rdmem);
+ $readmemh("int_opss.vm", wrmem);
+ wait (PAT_DONE);
+
+ DISABLE_INT = 1; /* interrupt generator off */
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h2;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("alu_ops.vm", rdmem);
+ $readmemh("alu_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h3;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("dat_mov.vm", rdmem);
+ $readmemh("dat_movd.vm", wrmem);
+ wait (PAT_DONE);
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h4;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("bit_ops.vm", rdmem);
+ $readmemh("bit_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h5;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("jmp_ops.vm", rdmem);
+ $readmemh("jmp_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h6;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("io_ops.vm", rdmem);
+ $readmemh("io_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h7;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("180_ops.vm", rdmem);
+ $readmemh("180_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ resettask;
+ CMP_ERR_L = 16'h0000;
+ PAT_CNT = 5'h8;
+ $readmemh("blank_xx.vm", rdmem);
+ $readmemh("blank_xx.vm", wrmem);
+ $readmemh("ez8_ops.vm", rdmem);
+ $readmemh("ez8_opsd.vm", wrmem);
+ wait (PAT_DONE);
+
+ $stop;
+ end
+
+ endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: tags/ez80-instructions/rtl/aluamux.v
===================================================================
--- tags/ez80-instructions/rtl/aluamux.v (nonexistent)
+++ tags/ez80-instructions/rtl/aluamux.v (revision 9)
@@ -0,0 +1,112 @@
+/*******************************************************************************************/
+/** **/
+/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
+/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
+/** **/
+/** alu a input multiplexer module Rev 0.0 06/13/2012 **/
+/** **/
+/*******************************************************************************************/
+module aluamux (adda_in, alua_in, alua_reg, aa_reg_out, bit_mask, daa_out, hl_reg_out,
+ ii_reg, int_addr, ix_reg, iy_reg, pc_reg, rr_reg, rst_addr, tmp_reg);
+
+ input [7:0] aa_reg_out; /* a register output */
+ input [7:0] bit_mask; /* bit mask for bit operations */
+ input [7:0] daa_out; /* daa constant */
+ input [7:0] ii_reg; /* i register output */
+ input [7:0] rr_reg; /* r register output */
+ input [7:0] rst_addr; /* restart address */
+ input [15:0] hl_reg_out; /* hl register output */
+ input [15:0] int_addr; /* interrupt address */
+ input [15:0] ix_reg; /* ix register output */
+ input [15:0] iy_reg; /* iy register output */
+ input [15:0] pc_reg; /* pc register output */
+ input [15:0] tmp_reg; /* tmp register output */
+ input [`ALUA_IDX:0] alua_reg; /* pipelined alu input a mux control */
+ output [15:0] adda_in; /* address alu a input bus */
+ output [15:0] alua_in; /* alu a input bus */
+
+ /*****************************************************************************************/
+ /* */
+ /* signal declarations */
+ /* */
+ /*****************************************************************************************/
+ reg [15:0] alua_in;
+ reg [15:0] alua_in_0, alua_in_1, alua_in_2, alua_in_3, alua_in_4, alua_in_5;
+ reg [15:0] alua_in_6, alua_in_7, alua_in_8, alua_in_9, alua_in_10, alua_in_11;
+ reg [15:0] alua_in_12, alua_in_13, alua_in_14;
+
+ wire [15:0] adda_in;
+ wire [15:0] adda_in_0, adda_in_1, adda_in_2, adda_in_4, adda_in_5, adda_in_12;
+ wire [15:0] adda_in_14;
+
+ /*****************************************************************************************/
+ /* */
+ /* alu input a select */
+ /* */
+ /*****************************************************************************************/
+ always @ (alua_reg or aa_reg_out or bit_mask or daa_out or ii_reg or int_addr or
+ hl_reg_out or ix_reg or iy_reg or pc_reg or rr_reg or rst_addr) begin
+ alua_in_0 = 16'h0;
+ alua_in_1 = 16'h0;
+ alua_in_2 = 16'h0;
+ alua_in_3 = 16'h0;
+ alua_in_4 = 16'h0;
+ alua_in_5 = 16'h0;
+ alua_in_6 = 16'h0;
+ alua_in_7 = 16'h0;
+ alua_in_8 = 16'h0;
+ alua_in_9 = 16'h0;
+ alua_in_10 = 16'h0;
+ alua_in_11 = 16'h0;
+ alua_in_12 = 16'h0;
+ alua_in_13 = 16'h0;
+ alua_in_14 = 16'h0;
+ if (alua_reg[`AA_ONE]) alua_in_0 = 16'h0001;
+ if (alua_reg[`AA_M1]) alua_in_1 = 16'hffff;
+ if (alua_reg[`AA_M2]) alua_in_2 = 16'hfffe;
+ if (alua_reg[`AA_HL]) alua_in_3 = hl_reg_out;
+ if (alua_reg[`AA_IX]) alua_in_4 = ix_reg;
+ if (alua_reg[`AA_IY]) alua_in_5 = iy_reg;
+ if (alua_reg[`AA_PC]) alua_in_6 = pc_reg;
+ if (alua_reg[`AA_AA]) alua_in_7 = {8'h00, aa_reg_out};
+ if (alua_reg[`AA_BIT]) alua_in_8 = {8'h00, bit_mask};
+ if (alua_reg[`AA_DAA]) alua_in_9 = {8'h00, daa_out};
+ if (alua_reg[`AA_II]) alua_in_10 = {8'h00, ii_reg};
+ if (alua_reg[`AA_RR]) alua_in_11 = {8'h00, rr_reg};
+ if (alua_reg[`AA_INT]) alua_in_12 = int_addr;
+ if (alua_reg[`AA_TMP]) alua_in_13 = tmp_reg;
+ if (alua_reg[`AA_RST]) alua_in_14 = {8'h00, rst_addr};
+ end
+
+ always @ (alua_in_0 or alua_in_1 or alua_in_2 or alua_in_3 or alua_in_4 or
+ alua_in_5 or alua_in_6 or alua_in_7 or alua_in_8 or alua_in_9 or
+ alua_in_10 or alua_in_11 or alua_in_12 or alua_in_13 or alua_in_14) begin
+ alua_in = alua_in_0 | alua_in_1 | alua_in_2 | alua_in_3 | alua_in_4 |
+ alua_in_5 | alua_in_6 | alua_in_7 | alua_in_8 | alua_in_9 |
+ alua_in_10 | alua_in_11 | alua_in_12 | alua_in_13 | alua_in_14;
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* address alu input a select */
+ /* */
+ /*****************************************************************************************/
+ assign adda_in_0 = (alua_reg[`AA_ONE]) ? 16'h0001 : 16'h0000;
+ assign adda_in_1 = (alua_reg[`AA_M1]) ? 16'hffff : 16'h0000;
+ assign adda_in_2 = (alua_reg[`AA_M2]) ? 16'hfffe : 16'h0000;
+ assign adda_in_4 = (alua_reg[`AA_IX]) ? ix_reg : 16'h0000;
+ assign adda_in_5 = (alua_reg[`AA_IY]) ? iy_reg : 16'h0000;
+ assign adda_in_12 = (alua_reg[`AA_INT]) ? int_addr : 16'h0000;
+ assign adda_in_14 = (alua_reg[`AA_RST]) ? {8'h00, rst_addr} : 16'h0000;
+
+ assign adda_in = adda_in_0 | adda_in_1 | adda_in_2 | adda_in_4 | adda_in_5 |
+ adda_in_12 | adda_in_14;
+
+ endmodule
+
+
+
+
+
+
+
Index: tags/ez80-instructions/rtl/y80_top.v
===================================================================
--- tags/ez80-instructions/rtl/y80_top.v (nonexistent)
+++ tags/ez80-instructions/rtl/y80_top.v (revision 9)
@@ -0,0 +1,202 @@
+/*******************************************************************************************/
+/** **/
+/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
+/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
+/** **/
+/** processor top level Rev 0.0 06/13/2012 **/
+/** **/
+/*******************************************************************************************/
+module y80_top (dma_ack, halt_tran, iack_tran, io_addr_out, io_data_out, io_read, io_strobe,
+ io_tran, ivec_rd, mem_addr_out, mem_data_out, mem_rd, mem_tran, mem_wr,
+ reti_tran, t1, clearb, clkc, dma_req, int_req, io_data_in, ivec_data_in,
+ mem_data_in, nmi_req, resetb, wait_req);
+
+ input clearb; /* master (test) reset */
+ input clkc; /* main cpu clock */
+ input dma_req; /* dma request */
+ input int_req; /* interrupt request */
+ input nmi_req; /* nmi request */
+ input resetb; /* internal (user) reset */
+ input wait_req; /* wait request */
+ input [7:0] io_data_in; /* i/o input data bus */
+ input [7:0] ivec_data_in; /* interrupt vector bus */
+ input [7:0] mem_data_in; /* memory input bus */
+ output dma_ack; /* dma acknowledge */
+ output halt_tran; /* halt transaction */
+ output iack_tran; /* interrupt acknowledge transaction */
+ output io_read; /* i/o read enable */
+ output io_tran; /* i/o transaction */
+ output io_strobe; /* i/o data strobe */
+ output ivec_rd; /* interrupt vector enable */
+ output mem_rd; /* memory read enable */
+ output mem_tran; /* memory transaction */
+ output mem_wr; /* memory write enable */
+ output reti_tran; /* return from interrupt transaction */
+ output t1; /* first clock of transaction */
+ output [7:0] io_data_out; /* i/o output data bus */
+ output [7:0] mem_data_out; /* memory output data bus */
+ output [15:0] io_addr_out; /* i/o address bus */
+ output [15:0] mem_addr_out; /* memory address bus */
+
+ /*****************************************************************************************/
+ /* */
+ /* signal declarations */
+ /* */
+ /*****************************************************************************************/
+ wire burst_done; /* burst/mlt done */
+ wire cflg_en; /* carry flag control */
+ wire carry_bit; /* carry flag */
+ wire dma_ack; /* dma acknowledge */
+ wire dmar_reg; /* latched dma request */
+ wire ex_af_pls; /* exchange af,af' */
+ wire ex_bank_pls; /* exchange register bank */
+ wire ex_dehl_inst; /* exchange de,hl */
+ wire ftch_tran; /* inst fetch transaction */
+ wire halt_nxt, halt_tran; /* halt transaction */
+ wire iack_tran; /* int ack transaction */
+ wire if_frst; /* first clock if ifetch */
+ wire inta_frst; /* first clock of intack */
+ wire intr_reg; /* latched interrupt request */
+ wire io_read; /* i/o read enable */
+ wire io_tran; /* i/o transaction */
+ wire io_strobe; /* i/o data strobe */
+ wire ivec_rd; /* interrupt vector enable */
+ wire ld_ctrl; /* load control register */
+ wire ld_dmaa; /* load dma request */
+ wire ld_inst; /* load instruction register */
+ wire ld_inta; /* sample latched int */
+ wire ld_page; /* load page register */
+ wire ld_wait; /* sample wait input */
+ wire mem_rd; /* memory read enable */
+ wire mem_tran; /* memory transaction */
+ wire mem_wr; /* memory write enable */
+ wire output_inh; /* disable cpu outputs */
+ wire par_bit; /* parity flag */
+ wire rd_brst; /* burst read */
+ wire rd_frst; /* first clock of read */
+ wire rd_nxt; /* read trans next */
+ wire reti_nxt, reti_tran; /* reti transaction */
+ wire rreg_en; /* update refresh register */
+ wire sflg_en; /* sign flag control */
+ wire sign_bit; /* sign flag */
+ wire tflg_reg; /* temporary flag */
+ wire t1; /* first clock of transaction */
+ wire vector_int; /* int vector enable */
+ wire wait_st; /* wait state identifier */
+ wire wr_brst; /* burst write */
+ wire wr_frst; /* first clock of write */
+ wire xhlt_reg; /* halt exit */
+ wire zero_bit; /* zero flag */
+ wire zflg_en; /* zero flag control */
+ wire [3:0] page_sel; /* inst decode page control */
+ wire [3:0] page_reg; /* instruction decode "page" */
+ wire [7:0] inst_reg; /* instruction register */
+ wire [7:0] data_in; /* read data bus */
+ wire [7:0] dout_io_reg, dout_mem_reg; /* write data bus */
+ wire [15:0] addr_reg_in; /* processor logical address */
+ wire [7:0] io_data_out; /* i/o output data bus */
+ wire [7:0] mem_data_out; /* memory output data bus */
+ wire [15:0] io_addr_out; /* i/o address bus */
+ wire [15:0] mem_addr_out; /* memory address bus */
+ wire [`ADCTL_IDX:0] add_sel; /* address output mux control */
+ wire [`ALUA_IDX:0] alua_sel; /* alu input a mux control */
+ wire [`ALUB_IDX:0] alub_sel; /* alu input b mux control */
+ wire [`ALUOP_IDX:0] aluop_sel; /* alu operation control */
+ wire [`DI_IDX:0] di_ctl; /* data input control */
+ wire [`DO_IDX:0] do_ctl; /* data output control */
+ wire [`HFLG_IDX:0] hflg_ctl; /* half-carry flag control */
+ wire [`IEF_IDX:0] ief_ctl; /* interrupt enable control */
+ wire [`IMD_IDX:0] imd_ctl; /* interrupt mode control */
+ wire [`NFLG_IDX:0] nflg_ctl; /* negate flag control */
+ wire [`PCCTL_IDX:0] pc_sel; /* pc source control */
+ wire [`PFLG_IDX:0] pflg_ctl; /* parity/overflow flag control */
+ wire [`STATE_IDX:0] state_nxt, state_reg; /* machine state */
+ wire [`TFLG_IDX:0] tflg_ctl; /* temp flag control */
+ wire [`TTYPE_IDX:0] tran_sel; /* transaction type */
+ wire [`WREG_IDX:0] wr_addr; /* register write address bus */
+
+ /*****************************************************************************************/
+ /* */
+ /* interface module */
+ /* */
+ /*****************************************************************************************/
+ extint EXTINT ( .data_in(data_in), .dma_ack(dma_ack), .ftch_tran(ftch_tran),
+ .halt_tran(halt_tran), .iack_tran(iack_tran),
+ .io_addr_out(io_addr_out), .io_data_out(io_data_out),
+ .io_read(io_read), .io_strobe(io_strobe), .io_tran(io_tran),
+ .ivec_rd(ivec_rd), .mem_addr_out(mem_addr_out),
+ .mem_data_out(mem_data_out), .mem_rd(mem_rd), .mem_tran(mem_tran),
+ .mem_wr(mem_wr), .reti_tran(reti_tran), .t1(t1),
+ .addr_reg_in(addr_reg_in), .clkc(clkc), .dmar_reg(dmar_reg),
+ .dout_io_reg(dout_io_reg), .dout_mem_reg(dout_mem_reg),
+ .halt_nxt(halt_nxt), .if_frst(if_frst), .inta_frst(inta_frst),
+ .io_data_in(io_data_in), .ivec_data_in(ivec_data_in),
+ .ld_dmaa(ld_dmaa), .ld_wait(ld_wait), .mem_data_in(mem_data_in),
+ .output_inh(output_inh), .rd_frst(rd_frst), .rd_nxt(rd_nxt),
+ .resetb(resetb), .reti_nxt(reti_nxt), .tran_sel(tran_sel),
+ .wr_frst(wr_frst) );
+
+ /*****************************************************************************************/
+ /* */
+ /* state machine module */
+ /* */
+ /*****************************************************************************************/
+ machine MACHINE ( .ld_ctrl(ld_ctrl), .state_reg(state_reg), .wait_st(wait_st),
+ .clkc(clkc), .dmar_reg(dmar_reg), .intr_reg(intr_reg),
+ .ld_inta(ld_inta), .ld_wait(ld_wait), .resetb(resetb),
+ .state_nxt(state_nxt), .wait_req(wait_req) );
+
+ /*****************************************************************************************/
+ /* */
+ /* control module */
+ /* */
+ /*****************************************************************************************/
+ control CONTROL ( .add_sel(add_sel), .alua_sel(alua_sel), .alub_sel(alub_sel),
+ .aluop_sel(aluop_sel), .cflg_en(cflg_en), .di_ctl(di_ctl),
+ .do_ctl(do_ctl), .ex_af_pls(ex_af_pls), .ex_bank_pls(ex_bank_pls),
+ .ex_dehl_inst(ex_dehl_inst), .halt_nxt(halt_nxt), .hflg_ctl(hflg_ctl),
+ .ief_ctl(ief_ctl), .if_frst(if_frst), .inta_frst(inta_frst),
+ .imd_ctl(imd_ctl), .ld_dmaa(ld_dmaa), .ld_inst(ld_inst),
+ .ld_inta(ld_inta), .ld_page(ld_page), .ld_wait(ld_wait),
+ .nflg_ctl(nflg_ctl), .output_inh(output_inh), .page_sel(page_sel),
+ .pc_sel(pc_sel), .pflg_ctl(pflg_ctl), .rd_frst(rd_frst),
+ .rd_nxt(rd_nxt), .reti_nxt(reti_nxt), .rreg_en(rreg_en), .sflg_en(sflg_en),
+ .state_nxt(state_nxt), .tflg_ctl(tflg_ctl), .tran_sel(tran_sel),
+ .wr_addr(wr_addr), .wr_frst(wr_frst), .zflg_en(zflg_en),
+ .carry_bit(carry_bit), .dmar_reg(dmar_reg), .inst_reg(inst_reg),
+ .intr_reg(intr_reg), .page_reg(page_reg), .par_bit(par_bit),
+ .sign_bit(sign_bit), .state_reg(state_reg), .tflg_reg(tflg_reg),
+ .vector_int(vector_int), .xhlt_reg(xhlt_reg), .zero_bit(zero_bit),
+ .int_req(int_req) );
+
+ /*****************************************************************************************/
+ /* */
+ /* data path module */
+ /* */
+ /*****************************************************************************************/
+ datapath DATAPATH ( .addr_reg_in(addr_reg_in), .carry_bit(carry_bit), .dmar_reg(dmar_reg),
+ .dout_io_reg(dout_io_reg), .dout_mem_reg(dout_mem_reg),
+ .inst_reg(inst_reg), .intr_reg(intr_reg), .page_reg(page_reg),
+ .par_bit(par_bit), .sign_bit(sign_bit), .tflg_reg(tflg_reg),
+ .vector_int(vector_int), .xhlt_reg(xhlt_reg), .zero_bit(zero_bit),
+ .add_sel(add_sel), .alua_sel(alua_sel), .alub_sel(alub_sel),
+ .aluop_sel(aluop_sel), .clearb(clearb), .clkc(clkc), .cflg_en(cflg_en),
+ .data_in(data_in), .di_ctl(di_ctl), .dma_req(dma_req), .do_ctl(do_ctl),
+ .ex_af_pls(ex_af_pls), .ex_bank_pls(ex_bank_pls),
+ .ex_dehl_inst(ex_dehl_inst), .hflg_ctl(hflg_ctl), .ief_ctl(ief_ctl),
+ .imd_ctl(imd_ctl), .int_req(int_req), .ivec_rd(ivec_rd),
+ .ld_ctrl(ld_ctrl), .ld_inst(ld_inst), .ld_page(ld_page),
+ .nflg_ctl(nflg_ctl), .nmi_req(nmi_req), .page_sel(page_sel),
+ .pc_sel(pc_sel), .pflg_ctl(pflg_ctl), .resetb(resetb), .rreg_en(rreg_en),
+ .sflg_en(sflg_en), .tflg_ctl(tflg_ctl), .wait_st(wait_st),
+ .wr_addr(wr_addr), .zflg_en(zflg_en) );
+
+ endmodule
+
+
+
+
+
+
+
+
Index: tags/ez80-instructions/rtl/alu_shft.v
===================================================================
--- tags/ez80-instructions/rtl/alu_shft.v (nonexistent)
+++ tags/ez80-instructions/rtl/alu_shft.v (revision 9)
@@ -0,0 +1,71 @@
+/*******************************************************************************************/
+/** **/
+/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
+/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
+/** **/
+/** alu shifter module Rev 0.0 06/13/2012 **/
+/** **/
+/*******************************************************************************************/
+module alu_shft (shft_c, shft_out, alub_in, aluop_reg, carry_bit);
+
+ input carry_bit; /* carry flag input */
+ input [7:0] alub_in; /* alu b input */
+ input [`AOP_IDX:0] aluop_reg; /* alu operation control subset */
+ output shft_c; /* alu shifter carry output */
+ output [7:0] shft_out; /* alu shifter output */
+
+ /*****************************************************************************************/
+ /* */
+ /* signal declarations */
+ /* */
+ /*****************************************************************************************/
+ reg shft_c; /* shifter carry output */
+ reg [7:0] shft_out; /* shifter output */
+
+ /*****************************************************************************************/
+ /* */
+ /* alu shifter function */
+ /* */
+ /*****************************************************************************************/
+ always @ (aluop_reg or alub_in) begin
+ casex (aluop_reg) //synopsys parallel_case
+ `AOP_RL,
+ `AOP_RLA: shft_c = alub_in[7];
+ `AOP_RLC,
+ `AOP_RLCA: shft_c = alub_in[7];
+ `AOP_RR,
+ `AOP_RRA: shft_c = alub_in[0];
+ `AOP_RRC,
+ `AOP_RRCA: shft_c = alub_in[0];
+ `AOP_SLL,
+ `AOP_SLA: shft_c = alub_in[7];
+ `AOP_SRA: shft_c = alub_in[0];
+ `AOP_SRL: shft_c = alub_in[0];
+ default: shft_c = 1'b0;
+ endcase
+ end
+
+ always @ (aluop_reg or alub_in or carry_bit) begin
+ casex (aluop_reg) //synopsys parallel_case
+ `AOP_RL,
+ `AOP_RLA: shft_out = {alub_in[6:0], carry_bit};
+ `AOP_RLC,
+ `AOP_RLCA: shft_out = {alub_in[6:0], alub_in[7]};
+ `AOP_RR,
+ `AOP_RRA: shft_out = {carry_bit, alub_in[7:1]};
+ `AOP_RRC,
+ `AOP_RRCA: shft_out = {alub_in[0], alub_in[7:1]};
+ `AOP_SLA: shft_out = {alub_in[6:0], 1'b0};
+ `AOP_SLL: shft_out = {alub_in[6:0], 1'b1};
+ `AOP_SRA: shft_out = {alub_in[7], alub_in[7:1]};
+ `AOP_SRL: shft_out = {1'b0, alub_in[7:1]};
+ default: shft_out = 8'h00;
+ endcase
+ end
+
+ endmodule
+
+
+
+
+
Index: tags/ez80-instructions/rtl/version.v
===================================================================
--- tags/ez80-instructions/rtl/version.v (nonexistent)
+++ tags/ez80-instructions/rtl/version.v (revision 9)
@@ -0,0 +1,71 @@
+/*******************************************************************************************/
+/** **/
+/** ORIGINAL COPYRIGHT (C) 2010, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
+/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
+/** **/
+/** version definition file Rev 0.0 06/13/2012 **/
+/** **/
+/*******************************************************************************************/
+
+/*******************************************************************************************/
+/* */
+/* SELECT ONLY ONE OPTION PER GROUP! default is first option */
+/* */
+/*******************************************************************************************/
+
+/*******************************************************************************************/
+/* */
+/* enable/disable refresh register emulation (if enabled then breaks testbench) */
+/* */
+/*******************************************************************************************/
+// `define RREG_EMU /* enable emulation */
+
+/*******************************************************************************************/
+/* */
+/* select CPU or MPU */
+/* */
+/*******************************************************************************************/
+// `define Y90_CPU /* stand-alone cpu only */
+// `define Y90_MPU /* integrated version */
+`define Y90_180 /* clone version */
+
+/*******************************************************************************************/
+/* */
+/* select the operation of the H flag for the CCF instruction */
+/* */
+/*******************************************************************************************/
+`define Z80_CCF /* z80 CCF operation */
+// `define Z180_CCF /* z180 CCF operation */
+
+/*******************************************************************************************/
+/* */
+/* select the implementation of the MLT instruction */
+/* */
+/*******************************************************************************************/
+`define MUL_NORM /* parallel multiplier */
+// `define MUL_FAST /* serial multiplier */
+
+/*******************************************************************************************/
+/* */
+/* select the value reported in the System Status Block for dreq_bus (Y90 MPU Only) */
+/* */
+/*******************************************************************************************/
+`define DREQ_LOG /* log dreq timeouts */
+// `define DREQ_ACC /* count dreq timeouts */
+
+/*******************************************************************************************/
+/* */
+/* select the value reported in the System Status Block for wait_req (Y90 MPU Only) */
+/* */
+/*******************************************************************************************/
+`define WAIT_LOG /* log wait timeouts */
+// `define WAIT_ACC /* count wait timeouts */
+
+
+
+
+
+
+
+
+
Index: tags/ez80-instructions/rtl/datapath.v
===================================================================
--- tags/ez80-instructions/rtl/datapath.v (nonexistent)
+++ tags/ez80-instructions/rtl/datapath.v (revision 9)
@@ -0,0 +1,702 @@
+/*******************************************************************************************/
+/** **/
+/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
+/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
+/** **/
+/** data path module Rev 0.0 05/13/2012 **/
+/** **/
+/*******************************************************************************************/
+module datapath (addr_reg_in, carry_bit, dmar_reg, dout_io_reg, dout_mem_reg, inst_reg,
+ intr_reg, page_reg, par_bit, sign_bit, tflg_reg, vector_int, xhlt_reg,
+ zero_bit, add_sel, alua_sel, alub_sel, aluop_sel, clearb, clkc, cflg_en,
+ data_in, di_ctl, dma_req, do_ctl, ex_af_pls, ex_bank_pls, ex_dehl_inst,
+ hflg_ctl, ief_ctl, imd_ctl, int_req, ivec_rd, ld_ctrl, ld_inst, ld_page,
+ nflg_ctl, nmi_req, page_sel, pc_sel, pflg_ctl, resetb, sflg_en, tflg_ctl,
+ wait_st, wr_addr, zflg_en, rreg_en);
+
+ input cflg_en; /* carry flag control */
+ input clearb; /* master (testing) reset */
+ input clkc; /* main cpu clock */
+ input dma_req; /* dma request */
+ input ex_af_pls; /* exchange af,af' */
+ input ex_bank_pls; /* exchange register bank */
+ input ex_dehl_inst; /* exchange de,hl */
+ input int_req; /* interrupt request */
+ input ivec_rd; /* interrupt vector enable */
+ input ld_ctrl; /* load control register */
+ input ld_inst; /* load instruction register */
+ input ld_page; /* load page register */
+ input nmi_req; /* nmi request */
+ input resetb; /* internal (user) reset */
+ input rreg_en; /* update R register */
+ input sflg_en; /* sign flag control */
+ input wait_st; /* wait state identifier */
+ input zflg_en; /* zero flag control */
+ input [3:0] page_sel; /* instruction decode "page" control */
+ input [7:0] data_in; /* read data bus */
+ input [`ADCTL_IDX:0] add_sel; /* address output mux control */
+ input [`ALUA_IDX:0] alua_sel; /* alu input a mux control */
+ input [`ALUB_IDX:0] alub_sel; /* alu input b mux control */
+ input [`ALUOP_IDX:0] aluop_sel; /* alu operation control */
+ input [`DI_IDX:0] di_ctl; /* data input control */
+ input [`DO_IDX:0] do_ctl; /* data output control */
+ input [`HFLG_IDX:0] hflg_ctl; /* half-carry flag control */
+ input [`IEF_IDX:0] ief_ctl; /* interrupt enable control */
+ input [`IMD_IDX:0] imd_ctl; /* interrupt mode control */
+ input [`NFLG_IDX:0] nflg_ctl; /* negate flag control */
+ input [`PCCTL_IDX:0] pc_sel; /* program counter source control */
+ input [`PFLG_IDX:0] pflg_ctl; /* parity/overflow flag control */
+ input [`TFLG_IDX:0] tflg_ctl; /* temp flag control */
+ input [`WREG_IDX:0] wr_addr; /* register write address bus */
+ output carry_bit; /* carry flag */
+ output dmar_reg; /* latched dma request */
+ output intr_reg; /* latched interrupt request */
+ output par_bit; /* parity flag */
+ output sign_bit; /* sign flag */
+ output tflg_reg; /* temporary flag */
+ output vector_int; /* int vector enable */
+ output xhlt_reg; /* halt exit */
+ output zero_bit; /* zero flag */
+ output [3:0] page_reg; /* instruction decode "page" */
+ output [7:0] inst_reg; /* instruction register */
+ output [7:0] dout_io_reg; /* i/o write data bus */
+ output [7:0] dout_mem_reg; /* memory write data bus */
+ output [15:0] addr_reg_in; /* processor address bus */
+
+ /*****************************************************************************************/
+ /* */
+ /* signal declarations */
+ /* */
+ /*****************************************************************************************/
+ wire adder_c; /* math carry */
+ wire adder_hc; /* math half-carry */
+ wire adder_ov; /* math overflow result */
+ wire alu_carry; /* final carry */
+ wire alu_hcar; /* final half-carry */
+ wire alu_neg; /* final negate */
+ wire alu_one; /* final one */
+ wire alu_sign; /* final sign */
+ wire alu_zero; /* final zero */
+ wire bit7, bit6, bit5, bit4; /* bit decode */
+ wire bit3, bit2, bit1, bit0;
+ wire carry_bit; /* carry flag */
+ wire carry_daa; /* daa carry */
+ wire cry_nxt; /* combined carry */
+ wire daa_l1, daa_l2, daa_l3, daa_l4; /* decimal adjust */
+ wire daa_l5, daa_h1, daa_h2, daa_h3;
+ wire daa_h4, daa_h5, daa_h6, daa_h7;
+ wire daa1, daa2, daa3, daa4, daa5;
+ wire daa6, daa7;
+ wire hcar_nxt; /* combined half-carry */
+ wire hi_byte; /* replicate data byte */
+ wire ld_m_aa, ld_m_ff, ld_m_bb, ld_m_cc; /* register loads */
+ wire ld_m_dd, ld_m_ee, ld_m_hh, ld_m_ll;
+ wire ld_a_aa, ld_a_ff, ld_a_bb, ld_a_cc;
+ wire ld_a_dd, ld_a_ee, ld_a_hh, ld_a_ll;
+ wire ld_sp;
+ wire ld_ixh, ld_ixl, ld_iyh, ld_iyl;
+ wire ld_ii, ld_rr, ld_tmp;
+ wire ld_dout_io, ld_dout_mem; /* load data out */
+ wire ld_flag; /* load flags */
+ wire ld_regf; /* load register file */
+ wire ld_tflg; /* load temp flag */
+ wire logic_c; /* logic carry */
+ wire logic_hc; /* logic half-carry */
+ wire one_nxt; /* combined one */
+ wire par_bit; /* parity flag */
+ wire par_nxt; /* combined parity */
+ wire shft_c; /* shift carry */
+ wire sign_bit; /* sign flag */
+ wire sign_nxt; /* combined sign */
+ wire vector_int; /* int vector enable */
+ wire zero_bit; /* zero flag */
+ wire zero_nxt; /* combined zero */
+ wire [7:0] bit_mask; /* mask for bit inst */
+ wire [7:0] daa_out; /* daa result */
+ wire [7:0] ff_reg_in; /* register input */
+ wire [7:0] aa_reg_out, ff_reg_out; /* register outputs */
+ wire [7:0] new_flags; /* new flag byte */
+ wire [7:0] rst_addr; /* restart address */
+ wire [7:0] shft_out; /* shift result */
+ wire [15:8] bsign_ext; /* address alu b sign extend */
+ wire [15:0] adda_in, addb_in; /* address alu inputs */
+ wire [15:0] adder_out; /* math result */
+ wire [15:0] addr_alu8, addr_alu, addr_hl, addr_pc, addr_sp; /* address mux terms */
+ wire [15:0] addr_reg_in; /* address register input */
+ wire [15:0] alua_in, alub_in; /* alu inputs */
+ wire [15:0] data_bus; /* alu output */
+ wire [15:0] de_reg_in; /* register inputs */
+ wire [15:0] af_reg_out, bc_reg_out; /* register outputs */
+ wire [15:0] de_reg_out, hl_reg_out;
+ wire [15:0] logic_out; /* logic result */
+
+ reg alt_af_reg, alt_bnk_reg; /* main/alt select */
+ reg alu_ovflo; /* final ov */
+ reg daa_sel, daa_op; /* daa operation */
+ reg decr_sel, decr_op; /* decrement operation */
+ reg dmar_reg; /* latched dma request */
+ reg ex_dehl_reg; /* special exchange */
+ reg ief1_reg; /* int enable flag 1 */
+ reg ief2_reg; /* int enable flag 2 */
+ reg imd1_reg; /* int mode 1 */
+ reg imd2_reg; /* int mode 2 */
+ reg intr_reg; /* latched int req */
+ reg ld_dmar, ld_intr; /* sample int/dma */
+ reg ld_pc; /* load pc */
+ reg nmi_hld; /* nmi edge tracker */
+ reg nmi_reg; /* latched nmi req */
+ reg tflg_nxt, tflg_reg; /* temp flag */
+ reg valid_dma; /* valid dma request */
+ reg valid_int, valid_nmi, valid_xhlt; /* valid int request */
+ reg word_sel, word_op; /* 16-bit operation */
+ reg xhlt_reg; /* halt exit */
+ reg [3:0] page_reg /* synthesis syn_preserve=1 */;
+ reg [7:0] inst_reg; /* instruction register */
+ reg [7:0] m_aa_reg, m_ff_reg, m_bb_reg, m_cc_reg; /* individual registers */
+ reg [7:0] m_dd_reg, m_ee_reg, m_hh_reg, m_ll_reg;
+ reg [7:0] a_aa_reg, a_ff_reg, a_bb_reg, a_cc_reg;
+ reg [7:0] a_dd_reg, a_ee_reg, a_hh_reg, a_ll_reg;
+ reg [7:0] ii_reg, rr_reg;
+ reg [7:0] din0_reg, din1_reg; /* data input registers */
+ reg [7:0] dout_io_reg, dout_mem_reg; /* data output registers */
+ reg [15:0] adda_out; /* address alu out */
+ reg [15:0] int_addr; /* interrupt address */
+ reg [15:0] ix_reg, iy_reg; /* index registers */
+ reg [15:0] pc_reg; /* program counter */
+ reg [15:0] sp_reg; /* stack pointer */
+ reg [15:0] tmp_reg; /* temporary register */
+ reg [`ADCTL_IDX:0] addsel_reg /* synthesis syn_preserve=1 */;
+ reg [`ALUA_IDX:0] alua_reg /* synthesis syn_preserve=1 */;
+ reg [`ALUB_IDX:0] alub_reg /* synthesis syn_preserve=1 */;
+ reg [`ALUOP_IDX:0] aluop_reg /* synthesis syn_preserve=1 */;
+
+ /*****************************************************************************************/
+ /* */
+ /* input synchronization */
+ /* */
+ /*****************************************************************************************/
+ always @ (posedge clkc or negedge resetb) begin
+ if (!resetb) begin
+ nmi_hld <= 1'b0;
+ valid_dma <= 1'b0;
+ valid_int <= 1'b0;
+ valid_nmi <= 1'b0;
+ valid_xhlt <= 1'b0;
+ end
+ else begin
+ nmi_hld <= (nmi_req && !valid_nmi) || (!(ivec_rd && nmi_reg) && nmi_hld);
+ valid_dma <= dma_req;
+ valid_int <= nmi_req || nmi_hld || ((&ief_ctl[1:0] || ief1_reg) && int_req);
+ valid_nmi <= nmi_req || nmi_hld;
+ valid_xhlt <= !dma_req && (nmi_req || nmi_hld || (ief1_reg && int_req));
+ end
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* interrupt mode and enables */
+ /* */
+ /*****************************************************************************************/
+ always @ (posedge clkc or negedge resetb) begin
+ if (!resetb) begin
+ ief1_reg <= 1'b0;
+ ief2_reg <= 1'b0;
+ imd1_reg <= 1'b0;
+ imd2_reg <= 1'b0;
+ end
+ else begin
+ if (|ief_ctl[2:1]) ief1_reg <= (ief_ctl[1]) ? ief_ctl[0] : (ief_ctl[0] && ief2_reg);
+ if (|ief_ctl[2:1]) ief2_reg <= (ief_ctl[1]) ? ief_ctl[0] :
+ (ief_ctl[0]) ? ief2_reg : (nmi_reg && ief1_reg);
+ if (|imd_ctl) imd1_reg <= imd_ctl[1] && !imd_ctl[0];
+ if (|imd_ctl) imd2_reg <= &imd_ctl;
+ end
+ end
+
+ assign vector_int = imd2_reg && !nmi_reg;
+
+ /*****************************************************************************************/
+ /* */
+ /* interrupt pending */
+ /* */
+ /*****************************************************************************************/
+ always @ (pc_sel or wait_st) begin
+ case (pc_sel)
+ `PC_DMA, /* dma xfer dma sample */
+ `PC_INT: ld_dmar = 1'b1; /* block inst dma sample */
+ `PC_NILD: ld_dmar = !wait_st; /* inst end dma sample */
+ default: ld_dmar = 1'b0;
+ endcase
+ end
+
+ always @ (pc_sel or wait_st) begin
+ case (pc_sel)
+ `PC_INT: ld_intr = 1'b1; /* block inst int sample */
+ `PC_NILD: ld_intr = !wait_st; /* inst end int sample */
+ default: ld_intr = 1'b0;
+ endcase
+ end
+
+ always @ (posedge clkc or negedge resetb) begin
+ if (!resetb) begin
+ dmar_reg <= 1'b0;
+ intr_reg <= 1'b0;
+ nmi_reg <= 1'b0;
+ xhlt_reg <= 1'b0;
+ end
+ else begin
+ if (ld_dmar) dmar_reg <= valid_dma;
+ if (ld_intr) intr_reg <= !valid_dma && (valid_nmi || (ief1_reg && valid_int));
+ if (ld_intr) nmi_reg <= !valid_dma && valid_nmi;
+ if (ld_intr) xhlt_reg <= !valid_dma && valid_xhlt;
+ end
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* register control */
+ /* */
+ /*****************************************************************************************/
+ always @ (pc_sel or dmar_reg or intr_reg or valid_dma or valid_int or wait_st) begin
+ case (pc_sel)
+ `PC_LD: ld_pc = !wait_st; /* load PC unconditionally */
+ `PC_NILD: ld_pc = !((ief1_reg && valid_int) || valid_nmi || valid_dma) && !wait_st;
+ `PC_NILD2: ld_pc = !(intr_reg || dmar_reg) && !wait_st; /* if no latched int */
+ default: ld_pc = 1'b0;
+ endcase
+ end
+
+ always @ (posedge clkc or negedge resetb) begin
+ if (!resetb) begin
+ alt_af_reg <= 1'b0;
+ alt_bnk_reg <= 1'b0;
+ ex_dehl_reg <= 1'b0;
+ end
+ else begin
+ alt_af_reg <= ex_af_pls ^ alt_af_reg;
+ alt_bnk_reg <= ex_bank_pls ^ alt_bnk_reg;
+ ex_dehl_reg <= ex_dehl_inst && ld_ctrl;
+ end
+ end
+
+ assign ld_flag = (sflg_en || zflg_en || |hflg_ctl || |pflg_ctl || |nflg_ctl ||
+ cflg_en) && !wait_st;
+ assign ld_regf = wr_addr[`WR_REG] && !wait_st;
+
+ /*****************************************************************************************/
+ /* */
+ /* cpu register interface */
+ /* */
+ /*****************************************************************************************/
+ assign ff_reg_in = (ld_flag) ? new_flags : data_bus[7:0];
+ assign de_reg_in = (ex_dehl_reg) ? hl_reg_out : data_bus;
+
+ assign ld_m_aa = ld_regf && wr_addr[`WR_AA] && !alt_af_reg;
+ assign ld_m_ff = ((ld_regf && wr_addr[`WR_FF]) || ld_flag) && !alt_af_reg;
+ assign ld_m_bb = ld_regf && wr_addr[`WR_BB] && !alt_bnk_reg;
+ assign ld_m_cc = ld_regf && wr_addr[`WR_CC] && !alt_bnk_reg;
+ assign ld_m_dd = ld_regf && wr_addr[`WR_DD] && !alt_bnk_reg;
+ assign ld_m_ee = ld_regf && wr_addr[`WR_EE] && !alt_bnk_reg;
+ assign ld_m_hh = ld_regf && wr_addr[`WR_HH] && !alt_bnk_reg;
+ assign ld_m_ll = ld_regf && wr_addr[`WR_LL] && !alt_bnk_reg;
+ assign ld_a_aa = ld_regf && wr_addr[`WR_AA] && alt_af_reg;
+ assign ld_a_ff = ((ld_regf && wr_addr[`WR_FF]) || ld_flag) && alt_af_reg;
+ assign ld_a_bb = ld_regf && wr_addr[`WR_BB] && alt_bnk_reg;
+ assign ld_a_cc = ld_regf && wr_addr[`WR_CC] && alt_bnk_reg;
+ assign ld_a_dd = ld_regf && wr_addr[`WR_DD] && alt_bnk_reg;
+ assign ld_a_ee = ld_regf && wr_addr[`WR_EE] && alt_bnk_reg;
+ assign ld_a_hh = ld_regf && wr_addr[`WR_HH] && alt_bnk_reg;
+ assign ld_a_ll = ld_regf && wr_addr[`WR_LL] && alt_bnk_reg;
+ assign ld_sp = ld_regf && wr_addr[`WR_SP];
+ assign ld_ixh = ld_regf && wr_addr[`WR_IXH];
+ assign ld_ixl = ld_regf && wr_addr[`WR_IXL];
+ assign ld_iyh = ld_regf && wr_addr[`WR_IYH];
+ assign ld_iyl = ld_regf && wr_addr[`WR_IYL];
+ assign ld_ii = ld_regf && wr_addr[`WR_II];
+ assign ld_rr = ld_regf && wr_addr[`WR_RR];
+ assign ld_tmp = ld_regf && wr_addr[`WR_TMP];
+
+ assign af_reg_out = (alt_af_reg) ? {a_aa_reg, a_ff_reg} : {m_aa_reg, m_ff_reg};
+ assign bc_reg_out = (alt_bnk_reg) ? {a_bb_reg, a_cc_reg} : {m_bb_reg, m_cc_reg};
+ assign de_reg_out = (alt_bnk_reg) ? {a_dd_reg, a_ee_reg} : {m_dd_reg, m_ee_reg};
+ assign hl_reg_out = (alt_bnk_reg) ? {a_hh_reg, a_ll_reg} : {m_hh_reg, m_ll_reg};
+ assign aa_reg_out = af_reg_out[15:8];
+ assign ff_reg_out = af_reg_out[7:0];
+ assign carry_bit = af_reg_out[0];
+ assign par_bit = af_reg_out[2];
+ assign sign_bit = af_reg_out[7];
+ assign zero_bit = af_reg_out[6];
+ assign hi_byte = (wr_addr[`WR_AA] && !wr_addr[`WR_FF]) ||
+ (wr_addr[`WR_BB] && !wr_addr[`WR_CC]) ||
+ (wr_addr[`WR_DD] && !wr_addr[`WR_EE]) ||
+ (wr_addr[`WR_HH] && !wr_addr[`WR_LL]) ||
+ (wr_addr[`WR_IXH]&& !wr_addr[`WR_IXL]) ||
+ (wr_addr[`WR_IYH]&& !wr_addr[`WR_IYL]) ||
+ wr_addr[`WR_II] || wr_addr[`WR_RR];
+
+ /*****************************************************************************************/
+ /* */
+ /* cpu registers */
+ /* */
+ /*****************************************************************************************/
+ always @ (posedge clkc or negedge clearb) begin
+ if (!clearb) begin
+ m_aa_reg <= 8'h00;
+ m_ff_reg <= 8'h00;
+ m_bb_reg <= 8'h00;
+ m_cc_reg <= 8'h00;
+ m_dd_reg <= 8'h00;
+ m_ee_reg <= 8'h00;
+ m_hh_reg <= 8'h00;
+ m_ll_reg <= 8'h00;
+ a_aa_reg <= 8'h00;
+ a_ff_reg <= 8'h00;
+ a_bb_reg <= 8'h00;
+ a_cc_reg <= 8'h00;
+ a_dd_reg <= 8'h00;
+ a_ee_reg <= 8'h00;
+ a_hh_reg <= 8'h00;
+ a_ll_reg <= 8'h00;
+ ix_reg <= 16'h0000;
+ iy_reg <= 16'h0000;
+ end
+ else begin
+ if (ld_m_aa) m_aa_reg <= data_bus[15:8];
+ if (ld_m_ff) m_ff_reg <= ff_reg_in;
+ if (ld_m_bb) m_bb_reg <= data_bus[15:8];
+ if (ld_m_cc) m_cc_reg <= data_bus[7:0];
+ if (ld_m_dd) m_dd_reg <= de_reg_in[15:8];
+ if (ld_m_ee) m_ee_reg <= de_reg_in[7:0];
+ if (ld_m_hh) m_hh_reg <= data_bus[15:8];
+ if (ld_m_ll) m_ll_reg <= data_bus[7:0];
+ if (ld_a_aa) a_aa_reg <= data_bus[15:8];
+ if (ld_a_ff) a_ff_reg <= ff_reg_in;
+ if (ld_a_bb) a_bb_reg <= data_bus[15:8];
+ if (ld_a_cc) a_cc_reg <= data_bus[7:0];
+ if (ld_a_dd) a_dd_reg <= de_reg_in[15:8];
+ if (ld_a_ee) a_ee_reg <= de_reg_in[7:0];
+ if (ld_a_hh) a_hh_reg <= data_bus[15:8];
+ if (ld_a_ll) a_ll_reg <= data_bus[7:0];
+ if (ld_ixh) ix_reg[15:8] <= data_bus[15:8];
+ if (ld_ixl) ix_reg[7:0] <= data_bus[7:0];
+ if (ld_iyh) iy_reg[15:8] <= data_bus[15:8];
+ if (ld_iyl) iy_reg[7:0] <= data_bus[7:0];
+ end
+ end
+
+ always @ (posedge clkc or negedge resetb) begin
+ if (!resetb) begin
+ ii_reg <= 8'h00;
+ pc_reg <= 16'h0000;
+ rr_reg <= 8'h00;
+ sp_reg <= 16'h0000;
+ tmp_reg <= 16'h0000;
+ end
+ else begin
+ if (ld_ii) ii_reg <= data_bus[15:8];
+ if (ld_pc) pc_reg <= data_bus;
+ if (ld_rr)
+ rr_reg <= data_bus[15:8];
+`ifdef RREG_EMU
+ else
+ rr_reg[6:0] <= rr_reg[6:0] + {6'h0, rreg_en && !dmar_reg && !wait_st};
+`endif
+ if (ld_sp) sp_reg <= data_bus;
+ if (ld_tmp) tmp_reg <= (ivec_rd) ? {ii_reg, data_in} : data_bus;
+ end
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* temporary flag */
+ /* */
+ /*****************************************************************************************/
+ assign ld_tflg = |tflg_ctl && !wait_st;
+
+ always @ (tflg_ctl or alu_one or alu_zero or ff_reg_out) begin
+ casex (tflg_ctl)
+ `TFLG_1: tflg_nxt = alu_one; /* blk set if done (next xfr) */
+ `TFLG_Z: tflg_nxt = alu_zero; /* blk set if done (this xfr) */
+ `TFLG_B: tflg_nxt = alu_zero || !ff_reg_out[2]; /* blk cp set if done or match */
+ default: tflg_nxt = 1'b0;
+ endcase
+ end
+
+ always @ (posedge clkc or negedge resetb) begin
+ if (!resetb) tflg_reg <= 1'b0;
+ else if (ld_tflg) tflg_reg <= tflg_nxt;
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* data input and data output registers */
+ /* */
+ /*****************************************************************************************/
+ assign ld_dout_io = do_ctl[1] && !wait_st;
+ assign ld_dout_mem = do_ctl[2] && !wait_st;
+
+ always @ (posedge clkc or negedge resetb) begin
+ if (!resetb) begin
+ din0_reg <= 8'h00;
+ din1_reg <= 8'h00;
+ dout_io_reg <= 8'h00;
+ dout_mem_reg <= 8'h00;
+ end
+ else begin
+ if (di_ctl[0]) din0_reg <= data_in;
+ if (di_ctl[1]) din1_reg <= data_in;
+ if (ld_dout_io) dout_io_reg <= data_bus[7:0];
+ if (ld_dout_mem) dout_mem_reg <= (do_ctl[0]) ? data_bus[15:8] : data_bus[7:0];
+ end
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* instruction and page registers */
+ /* */
+ /*****************************************************************************************/
+ always @ (posedge clkc or negedge resetb) begin
+ if (!resetb) inst_reg <= 8'h00;
+ else if (ld_inst) inst_reg <= data_in;
+ end
+
+ always @ (posedge clkc or negedge resetb) begin
+ if (!resetb) page_reg <= 4'b0000;
+ else if (ld_page && ld_ctrl) page_reg <= page_sel;
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* alu control pipeline registers */
+ /* */
+ /*****************************************************************************************/
+ always @ (aluop_sel) begin
+ case (aluop_sel) //synopsys parallel_case
+ `ALUOP_DAA: daa_sel = 1'b1;
+ default: daa_sel = 1'b0;
+ endcase
+ end
+
+ always @ (aluop_sel) begin
+ case (aluop_sel) //synopsys parallel_case
+ `ALUOP_BDEC: decr_sel = 1'b1;
+ default: decr_sel = 1'b0;
+ endcase
+ end
+
+ always @ (aluop_sel) begin
+ case (aluop_sel) //synopsys parallel_case
+ `ALUOP_ADC,
+ `ALUOP_ADD,
+ `ALUOP_PASS,
+ `ALUOP_SBC,
+ `ALUOP_SUB: word_sel = 1'b1;
+ default: word_sel = 1'b0;
+ endcase
+ end
+
+ always @ (posedge clkc or negedge resetb) begin
+ if (!resetb) begin
+ addsel_reg <= `ADD_RSTVAL;
+ alua_reg <= `ALUA_RSTVAL;
+ alub_reg <= `ALUB_RSTVAL;
+ aluop_reg <= `ALUOP_RSTVAL;
+ daa_op <= 1'b0;
+ decr_op <= 1'b0;
+ word_op <= 1'b0;
+ end
+ else if (ld_ctrl) begin
+ addsel_reg <= add_sel;
+ alua_reg <= alua_sel;
+ alub_reg <= alub_sel;
+ aluop_reg <= aluop_sel;
+ daa_op <= daa_sel;
+ decr_op <= decr_sel;
+ word_op <= word_sel;
+ end
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* bit manipulation constant generator */
+ /* */
+ /*****************************************************************************************/
+ assign bit7 = (inst_reg[7] && !inst_reg[6]) ^ (inst_reg[5:3] == 3'b111);
+ assign bit6 = (inst_reg[7] && !inst_reg[6]) ^ (inst_reg[5:3] == 3'b110);
+ assign bit5 = (inst_reg[7] && !inst_reg[6]) ^ (inst_reg[5:3] == 3'b101);
+ assign bit4 = (inst_reg[7] && !inst_reg[6]) ^ (inst_reg[5:3] == 3'b100);
+ assign bit3 = (inst_reg[7] && !inst_reg[6]) ^ (inst_reg[5:3] == 3'b011);
+ assign bit2 = (inst_reg[7] && !inst_reg[6]) ^ (inst_reg[5:3] == 3'b010);
+ assign bit1 = (inst_reg[7] && !inst_reg[6]) ^ (inst_reg[5:3] == 3'b001);
+ assign bit0 = (inst_reg[7] && !inst_reg[6]) ^ (inst_reg[5:3] == 3'b000);
+ assign bit_mask = {bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0};
+
+ /*****************************************************************************************/
+ /* */
+ /* decimal adjust accumulator constant generator */
+ /* */
+ /*****************************************************************************************/
+ assign daa_l1 = !ff_reg_out[1] && !ff_reg_out[4] &&
+ (!aa_reg_out[3] || (aa_reg_out[3] && !aa_reg_out[2] && !aa_reg_out[1]));
+ assign daa_l2 = !ff_reg_out[1] && !ff_reg_out[4] &&
+ (aa_reg_out[3] && (aa_reg_out[2] || aa_reg_out[1]));
+ assign daa_l3 = !ff_reg_out[1] && ff_reg_out[4] && (!aa_reg_out[3] && !aa_reg_out[2]);
+ assign daa_l4 = ff_reg_out[1] && !ff_reg_out[4] &&
+ (!aa_reg_out[3] || (aa_reg_out[3] && !aa_reg_out[2] && !aa_reg_out[1]));
+ assign daa_l5 = ff_reg_out[1] && ff_reg_out[4] &&
+ ((!aa_reg_out[3] && aa_reg_out[2] && aa_reg_out[1]) || aa_reg_out[3]);
+ assign daa_h1 = !ff_reg_out[0] && (aa_reg_out[7] && (aa_reg_out[6] || aa_reg_out[5]));
+ assign daa_h2 = ff_reg_out[0] &&
+ (!aa_reg_out[7] && !aa_reg_out[6] && (!aa_reg_out[5] || !aa_reg_out[4]));
+ assign daa_h3 = !ff_reg_out[0] &&
+ (aa_reg_out[7] && (aa_reg_out[6] || aa_reg_out[5] || aa_reg_out[4]));
+ assign daa_h4 = ff_reg_out[0] && (!aa_reg_out[7] && !aa_reg_out[6]);
+ assign daa_h5 = ff_reg_out[0] &&
+ ((aa_reg_out[6] && aa_reg_out[5] && aa_reg_out[4]) || aa_reg_out[7]);
+ assign daa_h6 = !ff_reg_out[0] &&
+ ((!aa_reg_out[6] && !aa_reg_out[5] && !aa_reg_out[4]) || !aa_reg_out[7]);
+ assign daa_h7 = ff_reg_out[0] && ((aa_reg_out[6] && aa_reg_out[5]) || aa_reg_out[7]);
+
+ assign daa1 = daa_l2 || daa_l3 || daa_l5;
+ assign daa2 = daa_l2 || daa_l3;
+ assign daa3 = daa_l5;
+ assign daa4 = daa_l5 && (daa_h6 || daa_h7);
+ assign daa5 = (daa_l1 && (daa_h1 || daa_h2)) || (daa_l2 && (daa_h2 || daa_h3)) ||
+ (daa_l3 && (daa_h1 || daa_h4)) || (daa_l4 && daa_h5) ||
+ (daa_l5 && daa_h6);
+ assign daa6 = (daa_l1 && (daa_h1 || daa_h2)) || (daa_l2 && (daa_h2 || daa_h3)) ||
+ (daa_l3 && (daa_h1 || daa_h4)) || (daa_l5 && daa_h6);
+ assign daa7 = (daa_l4 && daa_h5) || (daa_l5 && (daa_h6 || daa_h7));
+
+ assign daa_out = {daa7, daa6, daa5, daa4, daa3, daa2, daa1, 1'b0};
+ assign carry_daa = (daa_l1 && (daa_h1 || daa_h2)) || (daa_l2 && (daa_h2 || daa_h3)) ||
+ (daa_l3 && (daa_h1 || daa_h4)) || (daa_l4 && daa_h5) ||
+ (daa_l5 && daa_h7);
+
+ /*****************************************************************************************/
+ /* */
+ /* interrupt/restart address generator */
+ /* */
+ /*****************************************************************************************/
+ assign rst_addr = {2'b00, inst_reg[5:3], 3'b000};
+
+ always @ (nmi_reg or imd2_reg or imd1_reg or din0_reg or din1_reg) begin
+ casex ({nmi_reg, imd2_reg, imd1_reg})
+ 3'b001: int_addr = 16'h0038;
+ 3'b010: int_addr = {din1_reg, din0_reg};
+ 3'b1xx: int_addr = 16'h0066;
+ default: int_addr = 16'h0000;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* alu input selects */
+ /* */
+ /*****************************************************************************************/
+ aluamux AMUX ( .adda_in(adda_in), .alua_in(alua_in), .alua_reg(alua_reg),
+ .aa_reg_out(aa_reg_out), .bit_mask(bit_mask), .daa_out(daa_out),
+ .hl_reg_out(hl_reg_out), .ii_reg(ii_reg), .int_addr(int_addr),
+ .ix_reg(ix_reg), .iy_reg(iy_reg), .pc_reg(pc_reg), .rr_reg(rr_reg),
+ .rst_addr(rst_addr), .tmp_reg(tmp_reg) );
+
+ alubmux BMUX ( .addb_in(addb_in), .alub_in(alub_in), .alub_reg(alub_reg),
+ .af_reg_out(af_reg_out), .bc_reg_out(bc_reg_out), .de_reg_out(de_reg_out),
+ .din0_reg(din0_reg), .din1_reg(din1_reg), .hl_reg_out(hl_reg_out),
+ .ix_reg(ix_reg), .iy_reg(iy_reg), .pc_reg(pc_reg), .sp_reg(sp_reg),
+ .tmp_reg(tmp_reg) );
+
+ /*****************************************************************************************/
+ /* */
+ /* function units */
+ /* */
+ /*****************************************************************************************/
+ alu_log ALULOG ( .logic_c(logic_c), .logic_hc(logic_hc), .logic_out(logic_out),
+ .alua_in(alua_in), .alub_in(alub_in), .aluop_reg(aluop_reg[`AOP_IDX:0]),
+ .carry_bit(carry_bit) );
+
+ alu_math ALUMATH ( .adder_c(adder_c), .adder_hc(adder_hc), .adder_out(adder_out),
+ .adder_ov(adder_ov), .alua_in(alua_in), .alub_in(alub_in),
+ .aluop_reg(aluop_reg[`AOP_IDX:0]), .carry_bit(carry_bit),
+ .carry_daa(carry_daa), .daa_op(daa_op), .word_op(word_op) );
+
+ alu_shft ALUSHFT ( .shft_c(shft_c), .shft_out(shft_out), .alub_in(alub_in[7:0]),
+ .aluop_reg(aluop_reg[`AOP_IDX:0]), .carry_bit(carry_bit) );
+ wire [15:0] mult_out = alub_in[15:8] * alub_in[7:0];
+ aluout ALUOUT ( .cry_nxt(cry_nxt), .data_bus(data_bus), .hcar_nxt(hcar_nxt),
+ .one_nxt(one_nxt), .par_nxt(par_nxt), .sign_nxt(sign_nxt),
+ .zero_nxt(zero_nxt), .adder_c(adder_c), .adder_hc(adder_hc),
+ .adder_out(adder_out), .hi_byte(hi_byte), .logic_c(logic_c),
+ .logic_hc(logic_hc), .logic_out(logic_out), .shft_c(shft_c),
+ .shft_out(shft_out), .mult_out(mult_out), .unit_sel(aluop_reg[7:6]), .word_op(word_op) );
+
+ /*****************************************************************************************/
+ /* */
+ /* flag generation */
+ /* */
+ /*****************************************************************************************/
+ assign alu_carry = decr_op ^ cry_nxt;
+ assign alu_hcar = (hflg_ctl[1]) ? hflg_ctl[0] : (decr_op ^ hcar_nxt);
+ assign alu_neg = (nflg_ctl[1]) ? nflg_ctl[0] : sign_nxt;
+ assign alu_one = one_nxt;
+ assign alu_sign = sign_nxt;
+ assign alu_zero = zero_nxt;
+
+ always @ (pflg_ctl or adder_ov or ief2_reg or par_nxt or zero_nxt) begin
+ case (pflg_ctl)
+ `PFLG_V: alu_ovflo = adder_ov;
+ `PFLG_1: alu_ovflo = 1'b1;
+ `PFLG_P: alu_ovflo = par_nxt;
+ `PFLG_B: alu_ovflo = !zero_nxt;
+ `PFLG_F: alu_ovflo = ief2_reg;
+ default: alu_ovflo = 1'b0;
+ endcase
+ end
+
+ assign new_flags[7] = (sflg_en) ? alu_sign : ff_reg_out[7];
+ assign new_flags[6] = (zflg_en) ? alu_zero : ff_reg_out[6];
+ assign new_flags[5] = ff_reg_out[5];
+ assign new_flags[4] = (|hflg_ctl) ? alu_hcar : ff_reg_out[4];
+ assign new_flags[3] = ff_reg_out[3];
+ assign new_flags[2] = (|pflg_ctl) ? alu_ovflo : ff_reg_out[2];
+ assign new_flags[1] = (|nflg_ctl) ? alu_neg : ff_reg_out[1];
+ assign new_flags[0] = (cflg_en) ? alu_carry : ff_reg_out[0];
+
+ /*****************************************************************************************/
+ /* */
+ /* address alu */
+ /* */
+ /*****************************************************************************************/
+ assign bsign_ext = {addb_in[7], addb_in[7], addb_in[7], addb_in[7],
+ addb_in[7], addb_in[7], addb_in[7], addb_in[7]};
+
+ always @ (aluop_reg or adda_in or addb_in or bsign_ext) begin
+ case (aluop_reg)
+ `ALUOP_ADS: adda_out = adda_in + {bsign_ext[15:8], addb_in[7:0]};
+ `ALUOP_BADD,
+ `ALUOP_ADD: adda_out = adda_in + addb_in;
+ `ALUOP_APAS: adda_out = adda_in;
+ default: adda_out = addb_in;
+ endcase
+ end
+
+ assign addr_alu8 = (addsel_reg[`AD_ALU8]) ? {8'h00, adda_out[7:0]} : 16'h0000;
+ assign addr_alu = (addsel_reg[`AD_ALU]) ? adda_out : 16'h0000;
+ assign addr_hl = (addsel_reg[`AD_HL]) ? hl_reg_out : 16'h0000;
+ assign addr_pc = (addsel_reg[`AD_PC]) ? pc_reg : 16'h0000;
+ assign addr_sp = (addsel_reg[`AD_SP]) ? sp_reg : 16'h0000;
+
+ assign addr_reg_in = addr_alu8 | addr_alu | addr_hl | addr_pc | addr_sp;
+
+ endmodule
+
+
+
+
+
+
+
+
+
+
+
Index: tags/ez80-instructions/rtl/aluout.v
===================================================================
--- tags/ez80-instructions/rtl/aluout.v (nonexistent)
+++ tags/ez80-instructions/rtl/aluout.v (revision 9)
@@ -0,0 +1,98 @@
+/*******************************************************************************************/
+/** **/
+/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
+/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
+/** **/
+/** alu function unit combiner module Rev 0.0 06/13/2012 **/
+/** **/
+/*******************************************************************************************/
+module aluout (cry_nxt, data_bus, hcar_nxt, one_nxt, par_nxt, sign_nxt, zero_nxt, adder_c,
+ adder_hc, adder_out, hi_byte, logic_c, logic_hc, logic_out, shft_c, shft_out,
+ mult_out,
+ unit_sel, word_op);
+
+ input adder_c; /* math carry result */
+ input adder_hc; /* math half-carry result */
+ input hi_byte; /* shift left byte control */
+ input logic_c; /* logic carry result */
+ input logic_hc; /* logic half-carry result */
+ input shft_c; /* shift carry result */
+ input word_op; /* word operation */
+ input [1:0] unit_sel; /* alu function unit select */
+ input [7:0] shft_out; /* shift unit result */
+ input [15:0] adder_out; /* math unit result */
+ input [15:0] logic_out; /* logic unit result */
+ input [15:0] mult_out; /* multiplier unit result */
+ output cry_nxt; /* carry flag next */
+ output hcar_nxt; /* half-carry flag next */
+ output one_nxt; /* one flag next */
+ output par_nxt; /* parity flag next */
+ output sign_nxt; /* sign flag next */
+ output zero_nxt; /* zero flag next */
+ output [15:0] data_bus; /* datapath data bus */
+
+ /*****************************************************************************************/
+ /* */
+ /* signal declarations */
+ /* */
+ /*****************************************************************************************/
+ wire one_nxt, par_nxt, sign_nxt, zero_nxt;
+ wire [15:0] data_bus;
+
+ reg cry_nxt, hcar_nxt;
+ reg [15:0] alu_result;
+
+ /*****************************************************************************************/
+ /* */
+ /* alu function unit combination */
+ /* */
+ /*****************************************************************************************/
+ always @ (unit_sel or adder_out or logic_out or shft_out or mult_out) begin
+ casex (unit_sel)
+ 2'b01: alu_result = adder_out;
+ 2'b10: alu_result = {8'h00, shft_out};
+ 2'b11: alu_result = mult_out;
+ default: alu_result = logic_out;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* alu flag outputs */
+ /* */
+ /*****************************************************************************************/
+ always @ (unit_sel or adder_c or logic_c or shft_c) begin
+ casex (unit_sel)
+ 2'b01: cry_nxt = adder_c;
+ 2'b1x: cry_nxt = shft_c;
+ default: cry_nxt = logic_c;
+ endcase
+ end
+
+ always @ (unit_sel or adder_hc or logic_hc) begin
+ casex (unit_sel)
+ 2'b01: hcar_nxt = adder_hc;
+ 2'b1x: hcar_nxt = 1'b0;
+ default: hcar_nxt = logic_hc;
+ endcase
+ end
+
+ assign one_nxt = ~|alu_result[7:1] && alu_result[0];
+ assign par_nxt = ~^alu_result[7:0];
+ assign sign_nxt = (word_op) ? alu_result[15] : alu_result[7];
+ assign zero_nxt = (word_op) ? ~|alu_result[15:0] : ~|alu_result[7:0];
+
+ /*****************************************************************************************/
+ /* */
+ /* alu output left shift */
+ /* */
+ /*****************************************************************************************/
+ assign data_bus = (hi_byte) ? {alu_result[7:0], alu_result[7:0]} : alu_result[15:0];
+
+ endmodule
+
+
+
+
+
+
Index: tags/ez80-instructions/rtl/extint.v
===================================================================
--- tags/ez80-instructions/rtl/extint.v (nonexistent)
+++ tags/ez80-instructions/rtl/extint.v (revision 9)
@@ -0,0 +1,163 @@
+/*******************************************************************************************/
+/** **/
+/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
+/** **/
+/** external interface module Rev 0.0 07/21/2011 **/
+/** **/
+/*******************************************************************************************/
+module extint (data_in, dma_ack, ftch_tran, halt_tran, iack_tran, io_addr_out, io_data_out,
+ io_read, io_strobe, io_tran, ivec_rd, mem_addr_out, mem_data_out, mem_rd,
+ mem_tran, mem_wr, reti_tran, t1, addr_reg_in, clkc, dmar_reg,
+ dout_io_reg, dout_mem_reg, halt_nxt, if_frst, inta_frst, io_data_in,
+ ivec_data_in, ld_dmaa, ld_wait, mem_data_in, output_inh, rd_frst, rd_nxt,
+ resetb, reti_nxt, tran_sel, wr_frst);
+
+ input clkc; /* main cpu clock */
+ input dmar_reg; /* latched dma request */
+ input halt_nxt; /* halt cycle identifier */
+ input if_frst; /* first part of fetch cycle identifier */
+ input inta_frst; /* first part of intack cycle identifier */
+ input ld_dmaa; /* load dma request */
+ input ld_wait; /* load wait request */
+ input output_inh; /* disable cpu outputs */
+ input rd_frst; /* first part of read cycle identifier */
+ input rd_nxt; /* read cycle identifier */
+ input resetb; /* internal reset */
+ input reti_nxt; /* reti cycle identifier */
+ input wr_frst; /* first part of write cycle identifier */
+ input [7:0] dout_io_reg; /* io data output */
+ input [7:0] dout_mem_reg; /* mem data output */
+ input [7:0] io_data_in; /* i/o input data bus */
+ input [7:0] ivec_data_in; /* interrupt vector bus */
+ input [7:0] mem_data_in; /* memory input bus */
+ input [15:0] addr_reg_in; /* processor logical address bus */
+ input [`TTYPE_IDX:0] tran_sel; /* transaction type select */
+ output dma_ack; /* dma acknowledge */
+ output ftch_tran; /* instruction fetch transaction */
+ output halt_tran; /* halt transaction */
+ output iack_tran; /* interrupt acknowledge transaction */
+ output io_read; /* i/o read enable */
+ output io_strobe; /* i/o data strobe */
+ output io_tran; /* i/o transaction */
+ output ivec_rd; /* interrupt vector enable */
+ output mem_rd; /* memory read enable */
+ output mem_tran; /* memory transaction */
+ output mem_wr; /* memory write enable */
+ output reti_tran; /* return from interrupt transaction */
+ output t1; /* first clock of transaction */
+ output [7:0] data_in; /* data input bus */
+ output [7:0] io_data_out; /* i/o output data bus */
+ output [7:0] mem_data_out; /* memory output data bus */
+ output [15:0] io_addr_out; /* i/o address bus */
+ output [15:0] mem_addr_out; /* memory address bus */
+
+ /*****************************************************************************************/
+ /* */
+ /* signal declarations */
+ /* */
+ /*****************************************************************************************/
+ wire ld_io_addr; /* update io address */
+ wire ld_mem_addr; /* update memory address */
+ wire [7:0] io_data_out; /* i/o output data bus */
+ wire [7:0] mem_data_out; /* memory output data bus */
+
+ reg dma_ack; /* dma acknowledge */
+ reg ftch_tran; /* inst fetch transaction */
+ reg halt_tran; /* halt transaction */
+ reg iack_tran; /* int ack transaction */
+ reg io_read; /* i/o read enable */
+ reg io_tran; /* i/o transaction */
+ reg io_strobe; /* i/o data strobe */
+ reg ivec_rd; /* interrupt vector enable */
+ reg mem_rd; /* memory read enable */
+ reg mem_tran; /* memory transaction */
+ reg mem_wr; /* memory write enable */
+ reg out_inh_reg; /* latched output inhibit */
+ reg reti_tran; /* reti transaction */
+ reg t1; /* first clock of transaction */
+ reg [7:0] data_in; /* data input bus */
+ reg [15:0] io_addr_out; /* i/o address bus */
+ reg [15:0] mem_addr_out; /* memory address bus */
+
+ /*****************************************************************************************/
+ /* */
+ /* misc signals & buses */
+ /* */
+ /*****************************************************************************************/
+ assign io_data_out = (out_inh_reg) ? 8'h00 : dout_io_reg;
+ assign mem_data_out = (out_inh_reg) ? 8'h00 : dout_mem_reg;
+ assign ld_io_addr = tran_sel[`TT_IO] || output_inh;
+ assign ld_mem_addr = tran_sel[`TT_IAK] || tran_sel[`TT_IDL] || tran_sel[`TT_IF] ||
+ tran_sel[`TT_MEM] || tran_sel[`TT_STK];
+
+ always @ (iack_tran or io_tran or io_data_in or ivec_data_in or mem_data_in) begin
+ case ({iack_tran, io_tran})
+ 2'b01: data_in = io_data_in;
+ 2'b10: data_in = ivec_data_in;
+ default: data_in = mem_data_in;
+ endcase
+ end
+
+ /*****************************************************************************************/
+ /* */
+ /* timing generation */
+ /* */
+ /*****************************************************************************************/
+ always @ (posedge clkc or negedge resetb) begin
+ if (!resetb) begin
+ dma_ack <= 1'b0;
+ ftch_tran <= 1'b0;
+ halt_tran <= 1'b0;
+ iack_tran <= 1'b0;
+ io_addr_out <= 16'h0000;
+ io_read <= 1'b0;
+ io_tran <= 1'b0;
+ mem_addr_out <= 16'h0000;
+ mem_tran <= 1'b0;
+ out_inh_reg <= 1'b0;
+ reti_tran <= 1'b0;
+ end
+ else if (|tran_sel) begin
+ dma_ack <= ld_dmaa && dmar_reg;
+ ftch_tran <= tran_sel[`TT_IF];
+ halt_tran <= halt_nxt;
+ iack_tran <= tran_sel[`TT_IAK];
+ if (ld_io_addr) io_addr_out <= (output_inh) ? 16'h0000 : addr_reg_in;
+ io_read <= tran_sel[`TT_IO] && rd_nxt;
+ io_tran <= tran_sel[`TT_IO];
+ if (ld_mem_addr) mem_addr_out <= (output_inh) ? 16'h0000 : addr_reg_in;
+ mem_tran <= (tran_sel[`TT_IDL] || tran_sel[`TT_IF] || tran_sel[`TT_MEM] ||
+ tran_sel[`TT_STK]) && !output_inh;
+ out_inh_reg <= output_inh;
+ reti_tran <= reti_nxt;
+ end
+ end
+
+ always @ (posedge clkc or negedge resetb) begin
+ if (!resetb) begin
+ io_strobe <= 1'b0;
+ ivec_rd <= 1'b0;
+ mem_rd <= 1'b0;
+ mem_wr <= 1'b0;
+ t1 <= 1'b0;
+ end
+ else begin
+ io_strobe <= io_tran && (rd_frst || wr_frst);
+ ivec_rd <= iack_tran && inta_frst;
+ mem_rd <= (if_frst || (mem_tran && rd_frst)) && ld_wait;
+ mem_wr <= mem_tran && wr_frst;
+ t1 <= |tran_sel && !(halt_nxt || dmar_reg);
+ end
+ end
+
+ endmodule
+
+
+
+
+
+
+
+
+
+
Index: tags/ez80-instructions/rtl/alubmux.v
===================================================================
--- tags/ez80-instructions/rtl/alubmux.v (nonexistent)
+++ tags/ez80-instructions/rtl/alubmux.v (revision 9)
@@ -0,0 +1,104 @@
+/*******************************************************************************************/
+/** **/
+/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
+/** **/
+/** alu b input multiplexer module Rev 0.0 07/24/2011 **/
+/** **/
+/*******************************************************************************************/
+module alubmux (addb_in, alub_in, alub_reg, af_reg_out, bc_reg_out, de_reg_out, din0_reg,
+ din1_reg, hl_reg_out, ix_reg, iy_reg, pc_reg, sp_reg, tmp_reg);
+
+ input [7:0] din0_reg; /* data input 0 register */
+ input [7:0] din1_reg; /* data input 1 register */
+ input [15:0] af_reg_out; /* af register output */
+ input [15:0] bc_reg_out; /* bc register output */
+ input [15:0] de_reg_out; /* de register output */
+ input [15:0] hl_reg_out; /* hl register output */
+ input [15:0] ix_reg; /* ix register output */
+ input [15:0] iy_reg; /* iy register output */
+ input [15:0] pc_reg; /* pc register output */
+ input [15:0] sp_reg; /* sp register output */
+ input [15:0] tmp_reg; /* temporary register output */
+ input [`ALUB_IDX:0] alub_reg; /* pipelined alu input b mux control */
+ output [15:0] addb_in; /* address alu b input bus */
+ output [15:0] alub_in; /* alu b input bus */
+
+ /*****************************************************************************************/
+ /* */
+ /* signal declarations */
+ /* */
+ /*****************************************************************************************/
+ wire [15:0] alub_in;
+ reg [15:0] alub_mux;
+ reg [15:0] alub_mux_1, alub_mux_2, alub_mux_3, alub_mux_4, alub_mux_5;
+ reg [15:0] alub_mux_6, alub_mux_7, alub_mux_8, alub_mux_9, alub_mux_10, alub_mux_11;
+
+ wire [15:0] addb_in;
+ wire [15:0] addb_mux_2, addb_mux_3, addb_mux_4, addb_mux_5, addb_mux_6, addb_mux_7;
+ wire [15:0] addb_mux_8, addb_mux_9, addb_mux_10, addb_mux_12;
+
+ /*****************************************************************************************/
+ /* */
+ /* alu input b select */
+ /* */
+ /*****************************************************************************************/
+ always @ (alub_reg or af_reg_out or bc_reg_out or de_reg_out or hl_reg_out or ix_reg or
+ iy_reg or sp_reg or din1_reg or din0_reg or tmp_reg or pc_reg) begin
+ alub_mux_1 = 32'h0;
+ alub_mux_2 = 32'h0;
+ alub_mux_3 = 32'h0;
+ alub_mux_4 = 32'h0;
+ alub_mux_5 = 32'h0;
+ alub_mux_6 = 32'h0;
+ alub_mux_7 = 32'h0;
+ alub_mux_8 = 32'h0;
+ alub_mux_9 = 32'h0;
+ alub_mux_10 = 32'h0;
+ alub_mux_11 = 32'h0;
+ if (alub_reg[`AB_AF]) alub_mux_1 = af_reg_out;
+ if (alub_reg[`AB_BC]) alub_mux_2 = bc_reg_out;
+ if (alub_reg[`AB_DE]) alub_mux_3 = de_reg_out;
+ if (alub_reg[`AB_HL]) alub_mux_4 = hl_reg_out;
+ if (alub_reg[`AB_IX]) alub_mux_5 = ix_reg;
+ if (alub_reg[`AB_IY]) alub_mux_6 = iy_reg;
+ if (alub_reg[`AB_SP]) alub_mux_7 = sp_reg;
+ if (alub_reg[`AB_DIN]) alub_mux_8 = {din1_reg, din0_reg};
+ if (alub_reg[`AB_IO]) alub_mux_9 = {af_reg_out[15:8], din0_reg};
+ if (alub_reg[`AB_TMP]) alub_mux_10 = tmp_reg;
+ if (alub_reg[`AB_PC]) alub_mux_11 = pc_reg;
+ end
+
+ always @ (alub_mux_1 or alub_mux_2 or alub_mux_3 or alub_mux_4 or alub_mux_5 or
+ alub_mux_6 or alub_mux_7 or alub_mux_8 or alub_mux_9 or alub_mux_10 or
+ alub_mux_11) begin
+ alub_mux = alub_mux_1 | alub_mux_2 | alub_mux_3 | alub_mux_4 | alub_mux_5 |
+ alub_mux_6 | alub_mux_7 | alub_mux_8 | alub_mux_9 | alub_mux_10 | alub_mux_11;
+ end
+
+ assign alub_in = (alub_reg[`AB_SHR]) ? {alub_mux[15:8], alub_mux[15:8]} : alub_mux;
+
+ /*****************************************************************************************/
+ /* */
+ /* address alu input b select */
+ /* */
+ /*****************************************************************************************/
+ assign addb_mux_2 = (alub_reg[`AB_BC]) ? bc_reg_out : 16'h0;
+ assign addb_mux_3 = (alub_reg[`AB_DE]) ? de_reg_out : 16'h0;
+ assign addb_mux_4 = (alub_reg[`AB_HL]) ? hl_reg_out : 16'h0;
+ assign addb_mux_5 = (alub_reg[`AB_IX]) ? ix_reg : 16'h0;
+ assign addb_mux_6 = (alub_reg[`AB_IY]) ? iy_reg : 16'h0;
+ assign addb_mux_7 = (alub_reg[`AB_SP]) ? sp_reg : 16'h0;
+ assign addb_mux_8 = (alub_reg[`AB_DIN]) ? {din1_reg, din0_reg} : 16'h0;
+ assign addb_mux_9 = (alub_reg[`AB_IO]) ? {af_reg_out[15:8], din0_reg} : 16'h0;
+ assign addb_mux_10 = (alub_reg[`AB_TMP]) ? tmp_reg : 16'h0;
+ assign addb_mux_12 = (alub_reg[`AB_ADR]) ? pc_reg : 16'h0;
+
+ assign addb_in = addb_mux_2 | addb_mux_3 | addb_mux_4 | addb_mux_5 | addb_mux_6 |
+ addb_mux_7 | addb_mux_8 |addb_mux_9 | addb_mux_10 | addb_mux_12;
+
+ endmodule
+
+
+
+
+
Index: tags/ez80-instructions/rtl/hierarchy.v
===================================================================
--- tags/ez80-instructions/rtl/hierarchy.v (nonexistent)
+++ tags/ez80-instructions/rtl/hierarchy.v (revision 9)
@@ -0,0 +1,25 @@
+/*******************************************************************************************/
+/** **/
+/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
+/** **/
+/** chip design file include list Rev 0.0 07/17/2011 **/
+/** **/
+/*******************************************************************************************/
+ `include "defines.v" /* control signal mnemonics */
+ `include "control.v" /* processor control */
+ `include "datapath.v" /* processor data path */
+ `include "alu_log.v" /* alu logic unit */
+ `include "alu_math.v" /* alu math unit */
+ `include "alu_shft.v" /* alu shifter unit */
+ `include "aluamux.v" /* alu a input multiplexer */
+ `include "alubmux.v" /* alu b input multiplexer */
+ `include "aluout.v" /* alu output multiplexer */
+ `include "extint.v" /* processor external interface */
+ `include "machine.v" /* processor state machine */
+ `include "y80_top.v" /* cpu top level */
+
+
+
+
+
+
Index: tags/ez80-instructions/rtl/alu_log.v
===================================================================
--- tags/ez80-instructions/rtl/alu_log.v (nonexistent)
+++ tags/ez80-instructions/rtl/alu_log.v (revision 9)
@@ -0,0 +1,68 @@
+/*******************************************************************************************/
+/** **/
+/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
+/** **/
+/** alu logic module Rev 0.0 07/17/2011 **/
+/** **/
+/*******************************************************************************************/
+module alu_log (logic_c, logic_hc, logic_out, alua_in, alub_in, aluop_reg, carry_bit);
+
+ input carry_bit; /* cpu carry flag */
+ input [15:0] alua_in; /* alu a input */
+ input [15:0] alub_in; /* alu b input */
+ input [`AOP_IDX:0] aluop_reg; /* alu operation control */
+ output logic_c; /* alu logic carry result */
+ output logic_hc; /* alu logic half-carry result */
+ output [15:0] logic_out; /* alu logic result */
+
+ /*****************************************************************************************/
+ /* */
+ /* signal declarations */
+ /* */
+ /*****************************************************************************************/
+ reg logic_c; /* logic carry output */
+ reg logic_hc; /* logic half-carry output */
+ reg [15:0] logic_out; /* logic output */
+
+ /*****************************************************************************************/
+ /* */
+ /* alu logic function */
+ /* */
+ /*****************************************************************************************/
+ always @ (aluop_reg or carry_bit) begin
+ casex (aluop_reg)
+ `AOP_CCF: logic_c = !carry_bit;
+ `AOP_SCF: logic_c = 1'b1;
+ default: logic_c = 1'b0;
+ endcase
+ end
+
+ always @ (aluop_reg or carry_bit) begin
+ casex (aluop_reg)
+ `AOP_BAND: logic_hc = 1'b1;
+ `AOP_CCF: logic_hc = carry_bit;
+ default: logic_hc = 1'b0;
+ endcase
+ end
+
+ always @ (aluop_reg or alua_in or alub_in) begin
+ casex (aluop_reg)
+ `AOP_BAND: logic_out = {8'h00, alua_in[7:0] & alub_in[7:0]};
+ `AOP_BOR: logic_out = {8'h00, alua_in[7:0] | alub_in[7:0]};
+ `AOP_BXOR: logic_out = {8'h00, alua_in[7:0] ^ alub_in[7:0]};
+ `AOP_RLD1: logic_out = {8'h00, alub_in[3:0], alua_in[3:0]};
+ `AOP_RLD2: logic_out = {8'h00, alua_in[7:4], alub_in[7:4]};
+ `AOP_RRD1: logic_out = {8'h00, alua_in[3:0], alub_in[7:4]};
+ `AOP_RRD2: logic_out = {8'h00, alua_in[7:4], alub_in[3:0]};
+ `AOP_APAS: logic_out = alua_in;
+ `AOP_PASS: logic_out = alub_in;
+ default: logic_out = 16'h0000;
+ endcase
+ end
+
+ endmodule
+
+
+
+
+
Index: tags/ez80-instructions/rtl/machine.v
===================================================================
--- tags/ez80-instructions/rtl/machine.v (nonexistent)
+++ tags/ez80-instructions/rtl/machine.v (revision 9)
@@ -0,0 +1,56 @@
+/*******************************************************************************************/
+/** **/
+/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
+/** **/
+/** state machine module Rev 0.0 07/01/2011 **/
+/** **/
+/*******************************************************************************************/
+module machine (ld_ctrl, state_reg, wait_st, clkc, dmar_reg, intr_reg, ld_inta, ld_wait,
+ resetb, state_nxt, wait_req);
+
+ input clkc; /* main cpu clock */
+ input dmar_reg; /* latched dma request */
+ input intr_reg; /* latched interrupt request */
+ input ld_inta; /* load interrupt request */
+ input ld_wait; /* load wait request */
+ input resetb; /* internal reset */
+ input wait_req; /* wait request */
+ input [`STATE_IDX:0] state_nxt; /* next processor state */
+ output ld_ctrl; /* load control register */
+ output wait_st; /* wait state identifier */
+ output [`STATE_IDX:0] state_reg; /* current processor state */
+
+ /*****************************************************************************************/
+ /* */
+ /* signal declarations */
+ /* */
+ /*****************************************************************************************/
+ wire ld_ctrl; /* advance state */
+
+ reg wait_st; /* wait state - inhibit op */
+ reg [`STATE_IDX:0] state_reg; /* current processor state */
+
+ /*****************************************************************************************/
+ /* */
+ /* processor state machine */
+ /* */
+ /*****************************************************************************************/
+ assign ld_ctrl = !ld_wait || !wait_req;
+
+ always @ (posedge clkc or negedge resetb) begin
+ if (!resetb) wait_st <= 1'b0;
+ else wait_st <= !ld_ctrl;
+ end
+
+ always @ (posedge clkc or negedge resetb) begin
+ if (!resetb) state_reg <= `sRST;
+ else if (ld_ctrl) state_reg <= (ld_inta && dmar_reg) ? `sDMA1 :
+ (ld_inta && intr_reg) ? `sINTA : state_nxt;
+ end
+
+ endmodule
+
+
+
+
+
Index: tags/ez80-instructions/rtl/alu_math.v
===================================================================
--- tags/ez80-instructions/rtl/alu_math.v (nonexistent)
+++ tags/ez80-instructions/rtl/alu_math.v (revision 9)
@@ -0,0 +1,141 @@
+/*******************************************************************************************/
+/** **/
+/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
+/** **/
+/** alu math module Rev 0.0 07/29/2011 **/
+/** **/
+/*******************************************************************************************/
+module alu_math (adder_c, adder_hc, adder_out, adder_ov, alua_in, alub_in, aluop_reg,
+ carry_bit, carry_daa, daa_op, word_op);
+
+ input carry_bit; /* carry flag */
+ input carry_daa; /* carry for daa */
+ input daa_op; /* daa operation */
+ input word_op; /* word operation */
+ input [15:0] alua_in; /* alu a input */
+ input [15:0] alub_in; /* alu b input */
+ input [`AOP_IDX:0] aluop_reg; /* alu operation control subset */
+ output adder_c; /* alu math carry result */
+ output adder_hc; /* alu math half-carry result */
+ output adder_ov; /* alu math overflow result */
+ output [15:0] adder_out; /* alu math result */
+
+ /*****************************************************************************************/
+ /* */
+ /* signal declarations */
+ /* */
+ /*****************************************************************************************/
+ wire adder_c; /* alu math carry out */
+ wire adder_hc; /* alu math half-carry out */
+ wire [15:8] bsign_ext; /* alu b sign extend */
+ wire [15:0] adder_out; /* alu math out */
+
+ reg alu_cin; /* alu math carry in */
+ reg adder_ov; /* alu math overflow out */
+ reg [4:0] alu0_out; /* alu math nibble 0 */
+ reg [4:0] alu1_out; /* alu math nibble 1 */
+ reg [4:0] alu2_out; /* alu math nibble 2 */
+ reg [4:0] alu3_out; /* alu math nibble 3 */
+
+ /*****************************************************************************************/
+ /* */
+ /* alu math carry input, sign extend */
+ /* */
+ /*****************************************************************************************/
+ always @ (aluop_reg or carry_bit) begin
+ casex (aluop_reg) //synopsys parallel_case
+ `AOP_ADC,
+ `AOP_BADC,
+ `AOP_SBC,
+ `AOP_BSBC: alu_cin = carry_bit;
+ default: alu_cin = 1'b0;
+ endcase
+ end
+
+ assign bsign_ext = {alub_in[7], alub_in[7], alub_in[7], alub_in[7],
+ alub_in[7], alub_in[7], alub_in[7], alub_in[7]};
+
+ /*****************************************************************************************/
+ /* */
+ /* alu math function unit */
+ /* */
+ /*****************************************************************************************/
+ always @ (aluop_reg or alua_in or alub_in or alu_cin) begin
+ casex (aluop_reg) //synopsys parallel_case
+ `AOP_SUB,
+ `AOP_BSUB,
+ `AOP_SBC,
+ `AOP_BSBC: alu0_out = alua_in[3:0] - alub_in[3:0] - alu_cin;
+ default: alu0_out = alua_in[3:0] + alub_in[3:0] + alu_cin;
+ endcase
+ end
+
+ always @ (aluop_reg or alua_in or alub_in or alu0_out) begin
+ casex (aluop_reg) //synopsys parallel_case
+ `AOP_SUB,
+ `AOP_BSUB,
+ `AOP_SBC,
+ `AOP_BSBC: alu1_out = alua_in[7:4] - alub_in[7:4] - alu0_out[4];
+ default: alu1_out = alua_in[7:4] + alub_in[7:4] + alu0_out[4];
+ endcase
+ end
+
+ always @ (aluop_reg or alua_in or alub_in or alu1_out or bsign_ext) begin
+ casex (aluop_reg) //synopsys parallel_case
+ `AOP_ADS: alu2_out = alua_in[11:8] + bsign_ext[11:8] + alu1_out[4];
+ `AOP_SUB,
+ `AOP_BSUB,
+ `AOP_SBC,
+ `AOP_BSBC: alu2_out = alua_in[11:8] - alub_in[11:8] - alu1_out[4];
+ default: alu2_out = alua_in[11:8] + alub_in[11:8] + alu1_out[4];
+ endcase
+ end
+
+ always @ (aluop_reg or alua_in or alub_in or alu2_out or bsign_ext) begin
+ casex (aluop_reg) //synopsys parallel_case
+ `AOP_ADS: alu3_out = alua_in[15:12] + bsign_ext[15:12] + alu2_out[4];
+ `AOP_SUB,
+ `AOP_BSUB,
+ `AOP_SBC,
+ `AOP_BSBC: alu3_out = alua_in[15:12] - alub_in[15:12] - alu2_out[4];
+ default: alu3_out = alua_in[15:12] + alub_in[15:12] + alu2_out[4];
+ endcase
+ end
+
+ assign adder_out = {alu3_out[3:0], alu2_out[3:0], alu1_out[3:0], alu0_out[3:0]};
+
+ /*****************************************************************************************/
+ /* */
+ /* alu math flag generation */
+ /* */
+ /*****************************************************************************************/
+ assign adder_c = (word_op) ? alu3_out[4] :
+ (daa_op) ? carry_daa : alu1_out[4];
+ assign adder_hc = (word_op) ? alu2_out[4] : alu0_out[4];
+
+ always @ (aluop_reg or alua_in or alub_in or alu3_out or alu1_out or bsign_ext) begin
+ casex (aluop_reg) //synopsys parallel_case
+ `AOP_ADC,
+ `AOP_ADD: adder_ov = (!alu3_out[3] && alua_in[15] && alub_in[15]) ||
+ ( alu3_out[3] && !alua_in[15] && !alub_in[15]);
+ `AOP_BADC,
+ `AOP_BADD,
+ `AOP_BDEC: adder_ov = (!alu1_out[3] && alua_in[7] && alub_in[7]) ||
+ ( alu1_out[3] && !alua_in[7] && !alub_in[7]);
+ `AOP_SBC,
+ `AOP_SUB: adder_ov = (!alu3_out[3] && alua_in[15] && !alub_in[15]) ||
+ ( alu3_out[3] && !alua_in[15] && alub_in[15]);
+ `AOP_BSBC,
+ `AOP_BSUB: adder_ov = (!alu1_out[3] && alua_in[7] && !alub_in[7]) ||
+ ( alu1_out[3] && !alua_in[7] && alub_in[7]);
+ default: adder_ov = 1'b0;
+ endcase
+ end
+
+ endmodule
+
+
+
+
+
+
Index: tags/ez80-instructions/doc/execute.ods
===================================================================
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Index: tags/ez80-instructions/doc/execute.ods
===================================================================
--- tags/ez80-instructions/doc/execute.ods (nonexistent)
+++ tags/ez80-instructions/doc/execute.ods (revision 9)
tags/ez80-instructions/doc/execute.ods
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+application/vnd.oasis.opendocument.spreadsheet
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Index: tags/ez80-instructions/mem/alu_ops.vm
===================================================================
--- tags/ez80-instructions/mem/alu_ops.vm (nonexistent)
+++ tags/ez80-instructions/mem/alu_ops.vm (revision 9)
@@ -0,0 +1,69 @@
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+@02C0 AA 06 C0 0E 30 16 0C 1E 03 26 55 2E 8A A0 F5 3E AA A1 F5 3E AA A2 F5 3E AA A3 F5 3E AA A4 F5 3E
+@02E0 AA A5 F5 E6 5F F5 21 00 30 3E AA A6 F5 DD A6 00 F5 3E AA FD A6 00 F5 37 3E AA 06 60 0E 30 16 AE
+@0300 1E 07 26 AA 2E 8A A8 F5 3E AA A9 F5 3E AA AA F5 3E AA AB F5 3E AA AC F5 3E AA AD F5 EE FF F5 21
+@0320 01 30 3E AA AE F5 DD AE 01 F5 3E AA FD AE 01 F5 37 3E AA 06 60 0E 30 16 AE 1E 07 26 55 2E 00 B0
+@0340 F5 3E AA B1 F5 3E AA B2 F5 3E AA B3 F5 3E AA B4 F5 3E 00 B5 F5 F6 55 F5 21 02 30 3E 8E B6 F5 3E
+@0360 0F DD B6 02 F5 3E 20 FD B6 02 F5 37 3E AA 06 60 0E 30 16 AE 1E 07 26 55 2E F6 80 F5 3E AA 81 F5
+@0380 3E AA 82 F5 3E AA 83 F5 3E AA 84 F5 3E AA 85 F5 C6 55 F5 21 03 30 3E AA 86 F5 3E 0F DD 86 03 F5
+@03A0 3E 20 FD 86 03 F5 37 3E AA 06 60 0E 30 16 AE 1E 07 26 55 2E F6 90 F5 3E AA 91 F5 3E AA 92 F5 3E
+@03C0 AA 93 F5 3E AA 94 F5 3E AA 95 F5 D6 55 F5 21 04 30 3E AA 96 F5 3E 0F DD 96 04 F5 3E 20 FD 96 04
+@03E0 F5 37 3E AA 06 60 0E 30 16 AE 1E 07 26 55 2E F6 B8 F5 B9 F5 BA F5 BB F5 BC F5 BD F5 3E B4 FE 55
+@0400 F5 21 05 30 3E AA BE F5 3E 0F DD BE 05 F5 3E 20 FD BE 05 F5 37 3E AA 06 60 0E 30 16 AE 1E 07 26
+@0420 55 2E F6 88 F5 3E AA 89 F5 3E AA 8A F5 3E AA 8B F5 3E AA 8C F5 3E AA 8D F5 CE 55 F5 21 06 30 3E
+@0440 AA 8E F5 3E 0F DD 8E 06 F5 3E 20 FD 8E 06 F5 37 3E AA 06 60 0E 30 16 AE 1E 07 26 55 2E F6 98 F5
+@0460 3E AA 99 F5 3E AA 9A F5 3E AA 9B F5 3E AA 9C F5 3E AA 9D F5 DE 55 F5 21 07 30 3E AA 9E F5 3E 0F
+@0480 DD 9E 07 F5 3E 20 FD 9E 07 F5 37 AF F5 3E 38 A7 F5 BF F5 87 F5 8F F5 B7 F5 37 8F F5 3F 9F F5 37
+@04A0 9F F5 97 F5 31 00 FD AF 47 4F 57 5F 67 6F 3E 35 CB 07 F5 CB 07 F5 CB 07 F5 CB 07 F5 CB 07 F5 CB
+@04C0 0F F5 CB 0F F5 CB 0F F5 CB 0F F5 CB 0F F5 CB 17 F5 CB 17 F5 CB 17 F5 CB 17 F5 CB 17 F5 CB 1F F5
+@04E0 CB 1F F5 CB 1F F5 CB 1F F5 CB 1F F5 CB 27 F5 CB 27 F5 CB 27 F5 CB 27 F5 CB 27 F5 3E 35 CB 2F F5
+@0500 CB 2F F5 CB 2F F5 3E 86 CB 2F F5 CB 2F F5 3E 35 CB 3F F5 CB 3F F5 CB 3F F5 3E 86 CB 3F F5 CB 3F
+@0520 F5 C5 D5 E5 AF 01 67 58 11 CB 9A 21 F0 21 CB 00 C5 CB 01 C5 CB 02 D5 CB 03 D5 CB 04 E5 CB 05 E5
+@0540 F5 01 67 58 11 CB 9A 21 F0 21 CB 08 C5 CB 09 C5 CB 0A D5 CB 0B D5 CB 0C E5 CB 0D E5 F5 01 67 58
+@0560 11 CB 9A 21 F0 21 CB 10 C5 CB 11 C5 CB 12 D5 CB 13 D5 CB 14 E5 CB 15 E5 F5 01 67 58 11 CB 9A 21
+@0580 F0 21 CB 18 C5 CB 19 C5 CB 1A D5 CB 1B D5 CB 1C E5 CB 1D E5 F5 01 67 58 11 CB 9A 21 F0 21 CB 20
+@05A0 C5 CB 21 C5 CB 22 D5 CB 23 D5 CB 24 E5 CB 25 E5 F5 01 67 58 11 CB 9A 21 F0 21 CB 28 C5 CB 29 C5
+@05C0 CB 2A D5 CB 2B D5 CB 2C E5 CB 2D E5 F5 01 67 58 11 CB 9A 21 F0 21 CB 38 C5 CB 39 C5 CB 3A D5 CB
+@05E0 3B D5 CB 3C E5 CB 3D E5 F5 21 08 30 CB 06 F5 23 CB 0E F5 23 CB 16 F5 23 CB 1E F5 23 CB 26 F5 3F
+@0600 23 CB 2E F5 23 CB 3E F5 DD CB 08 06 F5 DD CB 09 0E F5 DD CB 0A 16 F5 DD CB 0B 1E F5 DD CB 0C 26
+@0620 F5 DD CB 0D 2E F5 DD CB 0E 3E F5 FD CB 08 06 F5 FD CB 09 0E F5 FD CB 0A 16 F5 FD CB 0B 1E F5 FD
+@0640 CB 0C 26 F5 FD CB 0D 2E F5 FD CB 0E 3E F5 AF 47 4F 57 5F 67 6F 3E 35 07 F5 07 F5 07 F5 07 F5 07
+@0660 F5 0F F5 0F F5 0F F5 0F F5 0F F5 17 F5 17 F5 17 F5 17 F5 17 F5 1F F5 1F F5 1F F5 1F F5 1F F5 01
+@0680 67 58 11 CB 9A 21 F0 21 31 48 FD BF 3E 35 CB 37 F5 CB 37 F5 CB 37 F5 CB 37 F5 CB 37 F5 C5 D5 E5
+@06A0 CB 30 C5 CB 31 C5 CB 32 D5 CB 33 D5 CB 34 E5 CB 35 E5 F5 BF 21 11 30 CB 36 F5 BF DD CB 0F 36 F5
+@06C0 BF FD CB 0F 36 F5 31 00 FA F1 31 00 FB 27 F5 31 02 FA F1 31 FE FA 27 F5 31 04 FA F1 31 FC FA 27
+@06E0 F5 31 06 FA F1 31 FA FA 27 F5 31 08 FA F1 31 F8 FA 27 F5 31 0A FA F1 31 F6 FA 27 F5 31 0C FA F1
+@0700 31 F4 FA 27 F5 31 0E FA F1 31 F2 FA 27 F5 31 10 FA F1 31 F0 FA 27 F5 31 12 FA F1 31 EE FA 27 F5
+@0720 31 14 FA F1 31 EC FA 27 F5 31 16 FA F1 31 EA FA 27 F5 31 18 FA F1 31 E8 FA 27 F5 AF 31 CC FA 21
+@0740 0F 30 3E 67 ED 6F F5 23 ED 67 F5 21 AA AA 01 BC BC 11 DE DE 31 00 FC DD 21 30 60 FD 21 07 AE 3E
+@0760 AA DD 8C F5 3E AA DD 8D F5 3E AA FD 8C F5 3E AA FD 8D F5 3E AA DD 84 F5 3E AA DD 85 F5 3E AA FD
+@0780 84 F5 3E AA FD 85 F5 3E AA DD A4 F5 3E AA DD A5 F5 3E AA FD A4 F5 3E AA FD A5 F5 3E AA DD 21 01
+@07A0 01 FD 21 01 01 37 DD 25 F5 3F DD 25 F5 DD 2D F5 37 DD 2D F5 FD 25 F5 FD 25 3F F5 FD 2D F5 FD 2D
+@07C0 F5 DD E5 FD E5 DD 24 F5 DD 2C F5 37 FD 24 F5 FD 2C F5 DD 24 F5 3F DD 2C F5 37 FD 24 F5 3F FD 2C
+@07E0 F5 DD E5 FD E5 DD 21 30 60 FD 21 07 AE 3E AA DD B4 F5 3E AA 37 DD B5 F5 37 3E AA FD B4 F5 3E AA
+@0800 FD B5 F5 3E AA DD AC F5 3E AA DD AD F5 3E AA FD AC F5 3E AA FD AD F5 3E 60 DD BC F5 DD BD F5 FD
+@0820 BC F5 FD BD F5 3E AA DD 9C F5 3E AA DD 9D F5 3E AA FD 9C F5 3E AA FD 9D F5 3E AA DD 94 F5 3E AA
+@0840 DD 95 F5 3E AA FD 94 F5 3E AA FD 95 F5 C5 D5 E5 DD E5 21 00 01 C3 C0 00
+@1000 C7 A2 80 01 01 01 01 01 67 67 67 67 67 67 67 66
+@2000 82 AB 78 78 60 60 78 60 F0 F0 F0 F0 F0 F0 F0 F0
+@3000 3C 55 55 FF AA AA FF AA C5 C5 C5 C4 C5 C5 C5 2F E3 C5
+@78CB 2E C0
+@BC9E F0 80
+@CA02 1F 00
+@FA00 00 99 00 8A 10 72 00 A6 00 9B 10 B1 01 24 01 1F 11 01 02 77 12 88 03 73 13 66
+
Index: tags/ez80-instructions/mem/alu_opsd.vm
===================================================================
--- tags/ez80-instructions/mem/alu_opsd.vm (nonexistent)
+++ tags/ez80-instructions/mem/alu_opsd.vm (revision 9)
@@ -0,0 +1,43 @@
+@1008 CE B3 CF 33 CE 33 33 CD
+@2008 E1 78 E0 F8 E0 F8 78 E1
+@2DA8 FF FF FF FF FF FF 72 38 00 00 00 00 FF FF FF FF
+@3008 8B E2 8B E2 8A E2 62 F7 2E 8B
+@78CB 2F BF
+@BC9E F1 7F
+@CA02 20 FF
+@FAC8 04 63 00 62 72 38 F0 0F 72 38 01 3F FF 00 01 FE 00 00 01 FF 01 FE 00 00 01 FF FF FF 00 00 57 00
+@FAE8 03 13 96 82 06 77 01 67 91 85 85 84 05 17 11 01 05 06 04 78 94 90 84 99
+@FB90 30 60 AA AA DE DE BC BC 82 A3 93 FC 06 7A 06 4A 82 A2 93 FC 06 7A 06 4A 12 60 97 60 02 60 42 60
+@FBB0 80 AD 00 04 84 9A 84 CA 84 AF 80 AE 80 BA 80 EA 01 01 01 01 00 AA 01 AA 00 AA 01 AA 51 AA 51 AA
+@FBD0 50 AA 50 AA FF FF FF FF 92 AA 42 AA 90 AA 43 AA 93 AA 42 AA 92 AA 43 AA 10 02 94 AA 10 20 10 20
+@FBF0 90 B1 15 58 80 DA 01 0A 90 B2 15 58 80 DB 01 0A 44 35 44 6A 44 D4 45 A8 45 51 44 A3 45 51 45 A8
+@FC10 44 D4 44 6A 44 35 44 6A 45 D4 45 A9 44 53 44 A6 45 53 45 A9 44 D4 44 6A 04 00 80 00 81 00 80 00
+@FC30 81 00 04 00 85 00 05 00 05 00 80 00 05 00 84 00 81 00 80 00 01 00 85 00 81 00 84 00 85 00 85 00
+@FC50 85 00 04 00 78 10 F0 10 65 4D CB 4D 33 2C 67 2C 80 00 F8 10 F0 10 E5 CD CB CD 33 2C 67 2C 81 00
+@FC70 E0 42 F0 42 96 34 CB 34 CE B0 67 B0 80 00 F8 90 F0 90 65 CD CB CD 33 AC 67 AC 81 00 E0 43 F0 43
+@FC90 97 34 CB 34 CE B0 67 B0 04 00 78 90 F0 90 E5 4D CB 4D B3 2C 67 2C 85 00 E1 42 F0 42 97 35 CB 35
+@FCB0 CE B0 67 B0 00 00 00 00 00 00 05 21 00 43 05 06 00 0D 01 1A 85 E1 84 C3 05 06 00 0D 01 1A 84 A0
+@FCD0 05 50 81 A8 84 D4 04 6A 04 35 04 6A 84 D4 81 A8 01 51 84 A3 01 51 81 A8 84 D4 04 6A 04 35 04 6A
+@FCF0 85 D4 85 A9 04 53 84 A6 05 53 85 A9 84 D4 04 6A
+@FD24 85 BF 80 BF 85 BF 85 BF E1 43 F0 43 97 35 CB 35 CF B1 67 B1 F0 21 CB 9A 67 58 80 BF 05 5F 85 AF
+@FD44 84 D7 00 6B FF FF FF FF 42 00 93 FF 42 00 81 C1 80 E0 84 E0 10 70 42 38 10 38 44 00 83 C0 02 0E
+@FD64 42 00 16 5E 83 B4 06 55 82 A2 93 FC 06 7A 06 49 84 98 10 11 91 A9 80 F6 91 A0 80 FF 90 B2 15 58
+@FD84 80 DB 01 0B 83 20 02 0F 42 AA 16 B4 83 AA 06 AA 82 AA 93 AA 06 AA 06 AA 83 C0 02 0E 42 00 16 5F
+@FDA4 83 B4 06 55 82 A3 93 FC 06 7A 06 4A 84 98 10 10 91 A9 80 F5 91 A0 80 FF 90 B1 15 58 80 DA 01 0A
+@FDC4 04 78 80 8F 80 DF 04 55 44 00 84 FF 84 AF 80 AE 80 BA 80 EA 00 01 00 5D 84 FF 80 DF 00 20 44 00
+@FDE4 80 AD 00 04 84 9A 84 CA 94 82 54 00 14 28 14 0A 90 8A 54 00 10 02 10 08 10 20 90 80
+@FE30 FF FF FF FF 34 12 56 52 93 00 00 00 34 12 56 52 42 00 AF 83 34 12 56 52 93 00 FA 81 34 12 56 52
+@FE50 93 00 4C 80 34 12 56 52 82 00 81 92 34 12 56 52 82 00 B5 A4 34 12 56 52 82 00 0C F7 34 12 56 52
+@FE70 83 00 62 49 34 12 56 52 11 00 E7 4A 34 12 56 52 11 00 65 4C 34 12 56 52 00 00 32 26 34 12 56 52
+@FE90 05 00 19 93 34 12 56 52 80 00 E4 80 34 12 56 52 94 00 B0 6E 34 12 56 52 00 00 59 1C 34 12 56 52
+@FEB0 01 00 A0 BC BC 78 03 CA 34 12 56 52 16 7F 92 7F 10 7F A0 BC BC 78 02 CA 34 12 56 52 02 7F 05 CA
+@FED0 36 12 57 52 82 7F 05 CB 36 14 57 55 00 7F 04 CB 34 14 54 55 80 7F A0 BC BC 78 04 C8 34 12 54 54
+@FEF0 16 7F 12 0F 82 FE 92 FF 50 00 94 80 10 10 00 01
+@FF10 FF FF FF FF FF FF A0 BC BC 78 04 C8 34 12 54 54 55 00 50 DE BC 78 04 C8 34 12 54 54 55 00 22 DF
+@FF30 BC 78 04 C8 34 12 54 54 44 00 EE CC BC 78 04 C8 34 12 54 54 44 00 9A 78 BC 78 04 C8 34 12 54 54
+@FF50 55 00 9A 78 5E BC 04 C8 34 12 54 54 55 00 9A 78 00 BD 04 C8 34 12 54 54 44 00 9A 78 CC AA 04 C8
+@FF70 34 12 54 54 44 00 9A 78 78 56 04 C8 34 12 54 54 55 00 82 C8 34 12 54 54 44 00 41 64 34 12 54 54
+@FF90 44 00 0D 52 34 12 54 54 55 00 00 00 00 00 01 00 44 00
+@FFC8 FF FF FF FF 9A 78 78 56 99 78 78 56 99 78 FF FF 99 78 77 56 00 00 FF FF 00 00 FF FF 01 00 00 00
+@FFE8 FF FF 87 80 13 02 93 FE 93 FF 42 00 57 80 57 7F 45 00 45 00 54 00 45 00
+
Index: tags/ez80-instructions/mem/dat_mov.vm
===================================================================
--- tags/ez80-instructions/mem/dat_mov.vm (nonexistent)
+++ tags/ez80-instructions/mem/dat_mov.vm (revision 9)
@@ -0,0 +1,34 @@
+@0000 C3 00 01
+@00C0 00 18 FD
+@0100 31 00 00 3E FF AF 06 01 0E 02 16 04 1E 08 26 10 2E 20 DD 21 AA AA FD 21 55 55 F5 C5 D5 E5 DD E5
+@0120 FD E5 3E F0 02 3E 0F 12 77 23 70 23 71 23 72 23 73 23 74 23 75 23 36 3C 21 20 10 F5 C5 D5 E5 3E
+@0140 00 08 3E FF B7 D9 01 FD FE 11 F7 FB 21 DF EF F5 C5 D5 E5 D9 F5 C5 D5 E5 EB F5 C5 D5 E5 D9 F5 C5
+@0160 D5 E5 EB F5 C5 D5 E5 D9 F5 C5 D5 E5 EB F5 C5 D5 E5 D9 F5 C5 D5 E5 EB F5 C5 D5 E5 D9 40 49 52 64
+@0180 6D 7F F5 C5 D5 E5 78 41 4A 53 5C 65 6F F5 C5 D5 E5 AF 06 01 0E 02 16 04 1E 08 26 10 2E 20 79 42
+@01A0 4B 54 5D 67 68 F5 C5 D5 E5 AF 06 01 0E 02 16 04 1E 08 26 10 2E 20 7A 43 4C 55 5F 60 69 F5 C5 D5
+@01C0 E5 AF 06 01 0E 02 16 04 1E 08 26 10 2E 20 7B 44 4D 57 58 61 6A F5 C5 D5 E5 AF 06 01 0E 02 16 04
+@01E0 1E 08 26 10 2E 20 7C 45 4F 50 59 62 6B F5 C5 D5 E5 AF 06 01 0E 02 16 04 1E 08 26 10 2E 20 7D 47
+@0200 48 51 5A 63 6C F5 C5 D5 E5 46 23 4E 23 56 23 5E 23 F5 C5 D5 E5 66 E5 26 20 23 6E E5 0A F5 1A F5
+@0220 3A 88 78 F5 ED 4B 89 78 ED 5B 8B 78 2A 8D 78 DD 2A 8F 78 FD 2A 91 78 ED 7B 93 78 32 95 78 ED 43
+@0240 96 78 ED 53 98 78 22 9A 78 DD 22 9C 78 FD 22 9E 78 ED 73 A0 78 31 00 F0 F1 C1 D1 E1 DD E1 FD E1
+@0260 31 00 FE F5 C5 D5 E5 DD E5 FD E5 23 F9 F5 E5 DD F9 F5 DD E5 FD 23 FD F9 F5 FD E5 31 00 FD E3 33
+@0280 33 DD E3 33 33 FD E3 DD 7E 00 DD 46 01 DD 4E 02 DD 56 03 DD 5E 04 DD 66 05 DD 6E 06 31 00 FD F5
+@02A0 C5 D5 E5 FD 7E 00 FD 46 01 FD 4E 02 FD 56 03 FD 5E 04 FD 66 05 FD 6E 06 F5 C5 D5 E5 DD 77 FF DD
+@02C0 70 FE DD 71 FD DD 72 FC DD 73 FB DD 74 FA DD 75 F9 DD 36 F8 0F FD 77 FF FD 70 FE FD 71 FD FD 72
+@02E0 FC FD 73 FB FD 74 FA FD 75 F9 FD 36 F8 0F AF 47 4F 57 5F 67 6F D9 47 4F 57 5F 67 6F D9 08 AF 3E
+@0300 FF ED 4F F5 C5 D5 E5 AF F5 ED 5F F5 C5 D5 E5 AF ED 4F 3E 55 ED 47 F5 C5 D5 E5 AF F5 ED 57 F5 FB
+@0320 ED 57 F5 F3 ED 57 F5 AF 31 00 FC DD 21 00 00 FD 21 FF FF 01 AA AA 11 55 55 21 22 22 DD 26 A5 DD
+@0340 E5 DD 2E 57 DD E5 FD 26 BE FD E5 FD 2E 3D FD E5 F5 C5 D5 E5 DD 7C F5 DD 7D F5 FD 7C F5 FD 7D F5
+@0360 3E 05 DD 6F 3E FE FD 67 3E AD DD 67 3E 7E FD 6F DD E5 FD E5 F5 DD 44 DD 4D DD 68 DD 61 C5 DD E5
+@0380 FD 44 FD 4D FD 68 FD 61 C5 FD E5 DD 45 DD 4C DD 60 DD 69 C5 DD E5 FD 45 FD 4C FD 60 FD 69 C5 FD
+@03A0 E5 F5 DD 5C DD 55 DD 6B DD 62 D5 DD E5 FD 54 FD 5D FD 6A FD 63 D5 FD E5 DD 5D DD 54 DD 63 DD 6A
+@03C0 D5 DD E5 FD 55 FD 5C FD 62 FD 6B D5 FD E5 DD 7D DD 6C DD 67 DD E5 FD 7D FD 6C FD 67 FD E5 C5 E5
+@03E0 21 00 01 C3 C0 00
+@2020 5A 69 78 87 96 A5
+@5A69 B4
+@6789 FF FD FB F9 F7 F5 F3
+@7887 C3 D2 F0 E1 1E 0F 3C 2D 5A 4B 78 69 00 FE
+@ABCD 01 03 05 07 09 0B 0D
+@F000 00 0F 11 EE 22 DD 33 CC 44 BB 55 AA
+@FD00 45 23 89 67 CD AB
+
Index: tags/ez80-instructions/mem/dat_movd.vm
===================================================================
--- tags/ez80-instructions/mem/dat_movd.vm (nonexistent)
+++ tags/ez80-instructions/mem/dat_movd.vm (revision 9)
@@ -0,0 +1,22 @@
+@0102 F0
+@0408 0F
+@1020 0F 01 02 04 08 10 26 3C
+@6780 FF 0F 0D 0B 09 07 05 03 01
+@7895 D2 F0 E1 1E 0F 3C 2D 5A 4B 78 69 00 FE
+@AA50 FF FF 56 AA 00 0F FF FF
+@ABC0 FF FF FF FF FF 0F 0D 0B 09 07 05 03 01
+@BB40 44 BB 00 0F FF FF FF FF
+@CC30 34 CC 00 0F FF FF FF FF
+@FBB8 22 22 7E FE FE 7E AD 05 7E FE 7E FE 05 AD AD 05 FE 7E 7E FE AD 05 AD 05 44 7E 7E FE 7E FE 05 AD
+@FBD8 05 AD FE 7E 7E FE AD 05 05 AD 44 7E 7E FE 05 AD 44 3D 44 BE 44 57 44 A5 22 22 55 55 AA AA 44 00
+@FBF8 3D BE FF BE 57 A5 00 A5
+@FCC8 FF FF FF FF FF FF 00 55 04 55 00 55 44 00 00 00 00 00 00 00 44 55 00 00 00 00 00 00 80 FF 44 00
+@FCE8 00 00 00 00 00 00 44 FF 0D 0B 09 07 05 03 00 01 F3 F5 F7 F9 FB FD 00 FF 34 CC 44 BB 56 AA FF FF
+@FDF0 FF FF FF FF 55 AA 44 BB 33 CC 22 DD 11 EE 00 0F
+@FF58 FF FF 44 D2 44 C3 44 B4 A5 20 24 96 24 20 87 78 69 5A 44 20 20 20 20 20 20 20 44 20 10 20 10 20
+@FF78 10 20 44 10 08 20 10 08 20 10 44 08 10 08 04 20 10 08 44 04 04 02 20 10 08 04 44 02 01 20 10 08
+@FF98 04 02 84 01 20 10 08 04 02 01 84 FF DF EF F7 FB FD FE 84 FF F7 FB DF EF FD FE 84 FF 20 10 08 04
+@FFB8 02 01 84 FF 08 04 20 10 02 01 84 FF F7 FB DF EF FD FE 84 FF DF EF F7 FB FD FE 84 FF 08 04 20 10
+@FFD8 02 01 84 FF 20 10 08 04 02 01 84 FF DF EF F7 FB FD FE 84 FF 20 10 08 04 02 01 44 0F 55 55 AA AA
+@FFF8 20 10 08 04 02 01 44 00
+
Index: tags/ez80-instructions/mem/int_opss.vm
===================================================================
--- tags/ez80-instructions/mem/int_opss.vm (nonexistent)
+++ tags/ez80-instructions/mem/int_opss.vm (revision 9)
@@ -0,0 +1,19 @@
+@3CC4 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3
+@3CD4 D4
+@5A3C 5A
+@966A 03 05 07 09 0B 0D 0F 11 13 15 17 19 1B 1D 1F 21
+@967A 23 25 27 29
+@FF32 CE 3C 21 84 B7 ED 92 FF 10 D6 78 96 00 2E 00 01
+@FF42 1F 00 44 5A 44 5A 00 69 00 2E 00 01 1F 00 00 DE
+@FF52 00 69 00 2D 00 01 1E 00 00 DD 00 69 00 2C 00 01
+@FF62 1D 00 01 DC 00 69 00 2B 00 01 1C 00 01 DB 16 69
+@FF72 00 2A 00 01 1B 00 00 DA 94 93 00 29 00 01 1A 00
+@FF82 00 D9 04 6A 00 28 00 01 19 00 00 D8 04 42 00 27
+@FF92 00 01 18 00 00 D7 00 55 00 26 00 01 17 00 12 D5
+@FFA2 16 00 12 D4 15 00 11 D3 00 55 00 55 14 00 00 D3
+@FFB2 44 00 44 00 13 00 00 D2 12 00 03 D1 11 00 01 D0
+@FFC2 10 00 00 CF 0F 00 01 CE 0E 00 FF CC 0D 00 00 CC
+@FFD2 0C 00 00 CB 0B 00 FF C9 0A 00 FF C8 09 00 FE C7
+@FFE2 08 00 FE C6 07 00 01 C6 06 00 01 C5 05 00 00 50
+@FFF2 04 00 00 50 03 00 02 C2 02 00 01 C1 01 00
+
Index: tags/ez80-instructions/mem/bit_ops.vm
===================================================================
--- tags/ez80-instructions/mem/bit_ops.vm (nonexistent)
+++ tags/ez80-instructions/mem/bit_ops.vm (revision 9)
@@ -0,0 +1,79 @@
+@0000 C3 00 01
+@00C0 00 18 FD
+@0100 31 00 00 3E FF AF 47 4F 57 5F 67 6F DD 21 FE 7F
+@0110 FD 21 01 72 F5 C5 D5 E5 DD E5 FD E5 CB C7 CB C8
+@0120 CB D1 CB DA CB E3 CB EC CB F5 F5 C5 D5 E5 AF 47
+@0130 4F 57 5F 67 6F CB C0 CB C9 CB D2 CB DB CB E4 CB
+@0140 ED CB F7 F5 C5 D5 E5 AF 47 4F 57 5F 67 6F CB C1
+@0150 CB CA CB D3 CB DC CB E5 CB EF CB F0 F5 C5 D5 E5
+@0160 AF 47 4F 57 5F 67 6F CB C2 CB CB CB D4 CB DD CB
+@0170 E7 CB E8 CB F1 F5 C5 D5 E5 AF 47 4F 57 5F 67 6F
+@0180 CB C3 CB CC CB D5 CB DF CB E0 CB E9 CB F2 F5 C5
+@0190 D5 E5 AF 47 4F 57 5F 67 6F CB C4 CB CD CB D7 CB
+@01A0 D8 CB E1 CB EA CB F3 F5 C5 D5 E5 AF 47 4F 57 5F
+@01B0 67 6F CB C5 CB CF CB D0 CB D9 CB E2 CB EB CB F4
+@01C0 F5 C5 D5 E5 AF 47 4F 57 5F 21 00 70 CB C6 CB FF
+@01D0 F5 C5 D5 E5 78 23 CB CE CB F8 F5 C5 D5 E5 47 23
+@01E0 CB D6 CB F9 F5 C5 D5 E5 4F 23 CB DE CB FA F5 C5
+@01F0 D5 E5 57 23 CB E6 CB FB F5 C5 D5 E5 5F 23 CB EE
+@0200 CB FC F5 C5 D5 E5 21 06 70 CB F6 CB FD F5 C5 D5
+@0210 E5 21 07 70 CB FE F5 C5 D5 E5 DD CB 07 C6 DD CB
+@0220 06 CE DD CB 05 D6 DD CB 04 DE DD CB 03 E6 DD CB
+@0230 02 EE DD CB 01 F6 DD CB 00 FE FD CB FF C6 FD CB
+@0240 FE CE FD CB FD D6 FD CB FC DE FD CB FB E6 FD CB
+@0250 FA EE FD CB F9 F6 FD CB F8 FE 3E FF B7 47 4F 57
+@0260 5F 67 6F DD 21 01 74 FD 21 FE 70 F5 C5 D5 E5 DD
+@0270 E5 FD E5 CB 87 CB 88 CB 91 CB 9A CB A3 CB AC CB
+@0280 B5 F5 C5 D5 E5 3E FF 47 4F 57 5F 67 6F CB 80 CB
+@0290 89 CB 92 CB 9B CB A4 CB AD CB B7 F5 C5 D5 E5 3E
+@02A0 FF 47 4F 57 5F 67 6F CB 81 CB 8A CB 93 CB 9C CB
+@02B0 A5 CB AF CB B0 F5 C5 D5 E5 3E FF 47 4F 57 5F 67
+@02C0 6F CB 82 CB 8B CB 94 CB 9D CB A7 CB A8 CB B1 F5
+@02D0 C5 D5 E5 3E FF 47 4F 57 5F 67 6F CB 83 CB 8C CB
+@02E0 95 CB 9F CB A0 CB A9 CB B2 F5 C5 D5 E5 3E FF 47
+@02F0 4F 57 5F 67 6F CB 84 CB 8D CB 97 CB 98 CB A1 CB
+@0300 AA CB B3 F5 C5 D5 E5 3E FF 47 4F 57 5F 67 6F CB
+@0310 85 CB 8F CB 90 CB 99 CB A2 CB AB CB B4 F5 C5 D5
+@0320 E5 3E FF 47 4F 57 5F 21 80 84 CB 86 CB BF F5 C5
+@0330 D5 E5 78 23 CB 8E CB B8 F5 C5 D5 E5 47 23 CB 96
+@0340 CB B9 F5 C5 D5 E5 4F 23 CB 9E CB BA F5 C5 D5 E5
+@0350 57 23 CB A6 CB BB F5 C5 D5 E5 5F 23 CB AE CB BC
+@0360 F5 C5 D5 E5 21 86 84 CB B6 CB BD F5 C5 D5 E5 21
+@0370 87 84 CB BE F5 C5 D5 E5 DD CB 00 86 DD CB FF 8E
+@0380 DD CB FE 96 DD CB FD 9E DD CB FC A6 DD CB FB AE
+@0390 DD CB FA B6 DD CB F9 BE FD CB 02 86 FD CB 03 8E
+@03A0 FD CB 04 96 FD CB 05 9E FD CB 06 A6 FD CB 07 AE
+@03B0 FD CB 08 B6 FD CB 09 BE AF 47 4F 57 5F 67 6F DD
+@03C0 21 00 A0 FD 21 00 90 31 00 C0 F1 31 00 C0 CB 7F
+@03D0 F5 31 02 C0 F1 31 FE BF CB 77 F5 31 04 C0 F1 31
+@03E0 FC BF CB 6F F5 31 06 C0 F1 31 FA BF CB 67 F5 3E
+@03F0 F7 CB 5F F5 3E 04 CB 57 F5 3E FD CB 4F F5 3E 01
+@0400 CB 47 F5 AF 01 CC F0 11 0F AA 21 55 33 CB 78 F5
+@0410 CB 70 F5 CB 68 F5 CB 60 F5 CB 58 F5 CB 50 F5 CB
+@0420 48 F5 CB 40 F5 CB 79 F5 CB 71 F5 CB 69 F5 CB 61
+@0430 F5 CB 59 F5 CB 51 F5 CB 49 F5 CB 41 F5 CB 7A F5
+@0440 CB 72 F5 CB 6A F5 CB 62 F5 CB 5A F5 CB 52 F5 CB
+@0450 4A F5 CB 42 F5 CB 7B F5 CB 73 F5 CB 6B F5 CB 63
+@0460 F5 CB 5B F5 CB 53 F5 CB 4B F5 CB 43 F5 CB 7C F5
+@0470 CB 74 F5 CB 6C F5 CB 64 F5 CB 5C F5 CB 54 F5 CB
+@0480 4C F5 CB 44 F5 CB 7D F5 CB 75 F5 CB 6D F5 CB 65
+@0490 F5 CB 5D F5 CB 55 F5 CB 4D F5 CB 45 F5 21 00 85
+@04A0 CB 7E F5 23 CB 76 F5 23 CB 6E F5 23 CB 66 F5 23
+@04B0 CB 5E F5 23 CB 56 F5 23 CB 4E F5 23 CB 46 F5 DD
+@04C0 21 02 85 FD 21 64 85 DD CB 3E 7E F5 DD CB 3F 76
+@04D0 F5 DD CB 40 6E F5 DD CB 41 66 F5 DD CB 42 5E F5
+@04E0 DD CB 43 56 F5 DD CB 44 4E F5 DD CB 45 46 F5 FD
+@04F0 CB 1C 7E F5 FD CB 1D 76 F5 FD CB 1E 6E F5 FD CB
+@0500 1F 66 F5 FD CB 20 5E F5 FD CB 21 56 F5 FD CB 22
+@0510 4E F5 FD CB 23 46 F5 21 00 01 C3 C0 00
+@7000 00 00 00 00 00 00 00 00
+@7100 FF FF FF FF FF FF FF FF
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+@73FA FF FF FF FF FF FF FF FF
+@7FFE 00 00 00 00 00 00 00 00
+@8480 FF FF FF FF FF FF FF FF
+@8500 80 BF 20 10 F7 40 FD FE
+@8540 00 00 FF FF FF FF 00 00
+@8580 00 FF 00 FF FF 00 FF 00
+@C000 FF 7F FF 40 00 DF 00 10
+
Index: tags/ez80-instructions/mem/int_opsd.vm
===================================================================
--- tags/ez80-instructions/mem/int_opsd.vm (nonexistent)
+++ tags/ez80-instructions/mem/int_opsd.vm (revision 9)
@@ -0,0 +1,11 @@
+@3CC4 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4
+@5A3C 5A
+@966A 03 05 07 09 0B 0D 0F 11 13 15 17 19 1B 1D 1F 21 23 25 27 29
+@FF32 CE 3C 21 84 B7 ED 92 FF 10 D6 78 96 00 2E 00 01 1F 00 44 5A 44 5A 00 69 00 2E 00 01 1F 00 00 DE
+@FF52 00 69 00 2D 00 01 1E 00 00 DD 00 69 00 2C 00 01 1D 00 01 DC 00 69 00 2B 00 01 1C 00 01 DB 16 69
+@FF72 00 2A 00 01 1B 00 00 DA 94 93 00 29 00 01 1A 00 00 D9 04 6A 00 28 00 01 19 00 00 D8 04 42 00 27
+@FF92 00 01 18 00 00 D7 00 55 00 26 00 01 17 00 12 D5 16 00 12 D4 15 00 11 D3 00 55 00 55 14 00 00 D3
+@FFB2 44 00 44 00 13 00 00 D2 12 00 04 D1 11 00 01 D0 10 00 01 CF 0F 00 01 CE 0E 00 FF CC 0D 00 00 CC
+@FFD2 0C 00 00 CB 0B 00 FF C9 0A 00 FF C8 09 00 FE C7 08 00 FE C6 07 00 01 C6 06 00 01 C5 05 00 00 50
+@FFF2 04 00 00 50 03 00 02 C2 02 00 02 C1 01 00
+
Index: tags/ez80-instructions/mem/setup_hl.vm
===================================================================
--- tags/ez80-instructions/mem/setup_hl.vm (nonexistent)
+++ tags/ez80-instructions/mem/setup_hl.vm (revision 9)
@@ -0,0 +1,4 @@
+@0000 C3 00 01
+@00C0 00 18 FD
+@0100 21 00 01 C3 C0 00
+
Index: tags/ez80-instructions/mem/bit_opsd.vm
===================================================================
--- tags/ez80-instructions/mem/bit_opsd.vm (nonexistent)
+++ tags/ez80-instructions/mem/bit_opsd.vm (revision 9)
@@ -0,0 +1,34 @@
+@7000 01 02 04 08 10 20 40 80
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+@71F8 01 80 40 20 10 08 04 02 01 00 00 00 00 00 00 00
+@73FA 7F BF DF EF F7 FB FD FE
+@7FF8 00 00 00 00 00 00 80 40 20 10 08 04 02 01 00 00
+@8480 FE FD FB F7 EF DF BF 7F
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+@BFD0 54 00 54 00 14 00 14 00 54 00 54 00 14 00 14 00
+@BFE0 54 00 54 00 54 00 54 00 14 00 14 00 14 00 14 00
+@BFF0 10 01 50 FD 10 04 50 F7 10 10 50 DF BD 40 FD 7F
+@FEF8 87 84 FF FF FF FF 84 FF 06 84 FF FF FF FF 84 FF
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+@FF18 83 84 FF 7F FF FF 84 FF 82 84 FF FF 7F FF 84 FF
+@FF28 81 84 FF FF FF 7F 84 FF 80 84 FF FF FF FF 84 7F
+@FF38 FE BF DF EF F7 FB 84 FD FD FE BF DF EF F7 84 FB
+@FF48 FB FD FE BF DF EF 84 F7 F7 FB FD FE BF DF 84 EF
+@FF58 EF F7 FB FD FE BF 84 DF DF EF F7 FB FD FE 84 BF
+@FF68 BF DF EF F7 FB FD 84 FE FE 70 01 74 FF FF FF FF
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+@FFC8 10 08 44 04 04 02 01 40 20 10 44 08 08 04 02 01
+@FFD8 40 20 44 10 10 08 04 02 01 40 44 20 20 10 08 04
+@FFE8 02 01 44 40 40 20 10 08 04 02 44 01 01 72 FE 7F
+@FFF8 00 00 00 00 00 00 44 00
+
Index: tags/ez80-instructions/mem/blank_xx.vm
===================================================================
--- tags/ez80-instructions/mem/blank_xx.vm (nonexistent)
+++ tags/ez80-instructions/mem/blank_xx.vm (revision 9)
@@ -0,0 +1,8192 @@
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+@FD30 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FD40 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FD50 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
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+
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+
+@FD80 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FD90 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
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+
+@FDB0 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FDC0 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FDD0 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FDE0 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FDF0 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FE00 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FE10 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FE20 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FE30 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FE40 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FE50 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FE60 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FE70 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FE80 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FE90 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FEA0 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FEB0 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FEC0 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FED0 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FEE0 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FEF0 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FF00 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FF10 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FF20 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FF30 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FF40 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FF50 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FF60 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FF70 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FF80 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FF90 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FFA0 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FFB0 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FFC0 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FFD0 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FFE0 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
+@FFF0 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
+
Index: tags/ez80-instructions/mem/jmp_ops.vm
===================================================================
--- tags/ez80-instructions/mem/jmp_ops.vm (nonexistent)
+++ tags/ez80-instructions/mem/jmp_ops.vm (revision 9)
@@ -0,0 +1,78 @@
+@0000 E9
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+@70A0 C5 03 31 08 03 F1 31 A2 FF CC B0 70 76
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+@7130 C5 03 F2 40 71 76
+@7140 C5 03 31 00 03 F1 3F 21 00 FE 31 00 04 C9
+@7160 71 03 23 31 02 03 F1 3F 31 02 04 C9
+@7170 71 03 23 31 00 03 F1 31 04 04 D8
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+@7240 C5 03 06 05 10 0A
+@7250 C5 03 06 03 10 0A
+@7260 C5 03 06 01 10 0A C5 03 18 16
+@7270 76
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+@728B C5 31 10 03 F1 21 00 01 C3 C0 00
+@7305 C5 03 04 04 10 80 76
+@CCFF C5 03 31 00 03 F1 D2 52 CD 30 48 D4 52 CD D0 F1
+@CD0F DA 52 CD 38 3E DC 52 CD D8 F1 E2 52 CD E4 52 CD
+@CD1F E0 F1 EA 52 CD EC 52 CD E8 F1 C2 52 CD 20 24 C4
+@CD2F 52 CD C0 F1 CA 52 CD 28 1A CC 52 CD C8 F1 F2 52
+@CD3F CD F4 52 CD F0 F1 FA 52 CD FC 52 CD F8 18 05 C5
+@CD4F 03 18 0D 76 31 00 03 F1 3F 31 CE FF C5 03 18 EF
+@CD5F C5 03 C3 FB CE
+@CEFB C5 03 18 7F
+@CF02 C5 03 CD 00 70
+@CF7E C5 03 18 80
+
Index: tags/ez80-instructions/mem/io_ops.vm
===================================================================
--- tags/ez80-instructions/mem/io_ops.vm (nonexistent)
+++ tags/ez80-instructions/mem/io_ops.vm (revision 9)
@@ -0,0 +1,35 @@
+@0000 C3 00 10
+@00C0 00 18 FD
+@00E0 10
+@01E1 13 88
+@02E1 12 17
+@03E1 11 16
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+@05E2 14
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+@1020 ED 48 F5 C5 ED 50 F5 C5 D5 03 ED 58 F5 C5 D5 03
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+@1040 F5 C5 D5 E5 03 ED 41 03 ED 49 03 ED 51 03 ED 59
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+@1070 F5 C5 D5 E5 01 03 00 11 01 A0 21 02 50 ED B0 F5
+@1080 C5 D5 E5 01 04 00 11 FE 9F 21 FD 4F ED B8 F5 C5
+@1090 D5 E5 ED A9 F5 C5 D5 E5 01 07 00 ED B9 F5 C5 D5
+@10A0 E5 01 00 80 21 05 50 ED A1 F5 C5 D5 E5 01 04 00
+@10B0 ED B1 F5 C5 D5 E5 01 E0 00 ED A2 F5 C5 D5 E5 01
+@10C0 E1 03 ED B2 F5 C5 D5 E5 01 E2 05 21 F5 4F ED AA
+@10D0 F5 C5 D5 E5 ED BA F5 C5 D5 E5 01 E3 04 ED AB F5
+@10E0 C5 D5 E5 ED BB F5 C5 D5 E5 01 E4 05 21 0E 50 ED
+@10F0 A3 F5 C5 D5 E5 ED B3 F5 C5 D5 E5 21 00 01 C3 C0
+@1100 00
+@4FE8 FF FF A8 27 26 1C 1B 1A 19 FF FF FF FF FF 43 0A
+@4FF8 09 08 07 06 05 04 FF AA 55 FF 01 02 03 0B 0C 0D
+@5008 0E 0F FF FF FF FF 1D 1E 1F 20 A1 22 23 22 25 FF
+@6600 BC
+@C610 A0 EA 66 00 43
+@C61B 8F
+@C623 10
+@CCF0 5A
+@E123 C6
+
Index: tags/ez80-instructions/mem/jmp_opsd.vm
===================================================================
--- tags/ez80-instructions/mem/jmp_opsd.vm (nonexistent)
+++ tags/ez80-instructions/mem/jmp_opsd.vm (revision 9)
@@ -0,0 +1,11 @@
+@FE00 2D 2E 2F 30 31 32 33 34 35 36
+@FF70 41 02 40 01 3F 00 3E 00 3D 02 3C 04 3B 08 3A 10
+@FF80 39 20 38 40 37 80 2C 00 2B 00 2C 71 2A 00 29 00
+@FF90 0C 71 28 00 27 00 26 00 DC 70 25 00 24 00 23 00
+@FFA0 AC 70 22 00 21 00 8C 70 20 00 1F 00 6C 70 1E 00
+@FFB0 1D 00 1C 00 3C 70 1B 00 1A 00 19 00 0C 70 18 00
+@FFC0 07 CF 17 00 16 00 15 00 14 00 13 00 12 00 11 00
+@FFD0 10 00 74 20 0F 00 0E 00 64 20 0D 00 0C 00 54 20
+@FFE0 0B 00 0A 00 44 20 09 00 08 00 34 20 07 00 06 00
+@FFF0 24 20 05 00 04 00 14 20 03 00 03 20 02 00 01 00
+
Index: tags/ez80-instructions/mem/int_ops.vm
===================================================================
--- tags/ez80-instructions/mem/int_ops.vm (nonexistent)
+++ tags/ez80-instructions/mem/int_ops.vm (revision 9)
@@ -0,0 +1,81 @@
+@0000 E9
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+@0066 03 DD 23 DD 71 00 E9
+@00C0 00 18 FD
+@0100 08 AF 3D 08 D9 01 B7 ED 11 21 84 21 C3 3C D9 AF 01 01 00 11 00 01 21 00 10 DD 21 69 96 FD 21 FE
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+@1200 C5 19 FD 19 FB FD E9
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+@1800 C5 19 FD 19 FB FD E9
+@1900 C5 19 FD 19 FB FD E9
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+@1D00 FF C5 03 2B 19 FD 19 FB FD E9
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+@D410 00 76 C3 00 50
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+@D610 AF 3E 4C DB E3 F5 D3 3C F5 C5 D5 E5 DD E5 FD E5 08 F5 08 D9 C5 D5 E5 D9 21 00 01 C3 C0 00
+@D6FE 00 A9
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+@D8FE 00 8C 00
+@D9FE 00 9C 00
+@DAFE 00 ED 6A 00
+@DBFE 00 ED 6A 00
+@DCFE 00 2B 00
+@DDFE 00 2B 00
+
Index: tags/ez80-instructions/mem/io_opsd.vm
===================================================================
--- tags/ez80-instructions/mem/io_opsd.vm (nonexistent)
+++ tags/ez80-instructions/mem/io_opsd.vm (revision 9)
@@ -0,0 +1,31 @@
+@0000 25
+@00F8 FF A8 27 26 25 24 23 22
+@01E3 1C A1
+@02E3 1B 20
+@03E3 1A 1F
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+@05E4 1D
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+@5A3C 5A
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+@FEE8 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+@FEF8 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
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+@FF48 FA 9F E0 FF 10 43 0A 50 FA 9F 00 00 12 43 06 50
+@FF58 FA 9F FF 7F 16 43 F5 4F FA 9F 04 00 46 43 F8 4F
+@FF68 FA 9F FF FF 16 43 F9 4F FA 9F 00 00 80 43 05 50
+@FF78 04 A0 00 00 80 43 00 50 00 A0 FE 7F 84 43 FF 4F
+@FF88 FF 9F FF 7F 84 43 FF FF FF FF FF FF FF FF FF FF
+@FF98 FF FF FF FF FF FF FF FF FF FF FF FF FF FF 00 66
+@FFA8 EA A0 14 C6 00 43 00 66 EA A0 13 C6 44 FF AA 66
+@FFB8 EA A0 12 C6 04 FF EA A0 11 C6 80 FF 21 A0 10 C6
+@FFC8 84 FF 10 C6 00 FF 23 C6 84 FF FF FF FF FF FF FF
+@FFD8 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+@FFE8 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+@FFF8 FF FF FF FF FF FF 44 5A
+