URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [change.log] - Diff between revs 43 and 45

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`All notable changes to this project will be documented in this file.`	`All notable changes to this project will be documented in this file.`

	`##[1.9.1] -24-07-2019`
	`## changed`
	`- Some bugs are fixed in jtag interface.`

`##[1.9.0] -30-04-2019`	`##[1.9.0] -30-04-2019`
`## Added`	`## Added`
`- add single flit sized packet support`	`- add single flit sized packet support`
`- add new topologies: Fattree, tree, concentrated mesh (Cmesh)`	`- add new topologies: Fattree, tree, concentrated mesh (Cmesh)`
Line 85...	Line 88...

`##[1.5.0] - 13-10-2016`	`##[1.5.0] - 13-10-2016`
`### Added`	`### Added`
`- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.`	`- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.`
`- NoC emulator.`	`- NoC emulator.`
`- Altor processor.`
`- Jtag_wb: allow access to the wishbone bus slave ports via Jtag.`	`- Jtag_wb: allow access to the wishbone bus slave ports via Jtag.`
`- Jtag_main: A C code which allows host PC to have access to the jtag_wb.`	`- Jtag_main: A C code which allows host PC to have access to the jtag_wb.`
`## changed`	`## changed`
`- Memory IP cores are categorized into two IPs: Single and double port.`	`- Memory IP cores are categorized into two IPs: Single and double port.`
`- The access via jtag_wb or Altera In-System Memory Content Editor is added as optional via parameter setting for single port memory.`	`- The access via jtag_wb or Altera In-System Memory Content Editor is added as optional via parameter setting for single port memory.`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [change.log] - Diff between revs 43 and 45