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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_uart.v] - Diff between revs 2 and 25

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Line 14... Line 14... 
////  Author(s):                                                  ////
 
////  Author(s):                                                  ////
 
////      - Simon Teran, simont@opencores.org                     ////
 
////      - Simon Teran, simont@opencores.org                     ////
 
////      - Dinesh Annayya, dinesha@opencores.org                 ////
 
////      - Dinesh Annayya, dinesha@opencores.org                 ////
 
////                                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
 
 
////   v0.0 - Dinesh A, 5th Jan 2017
 
 
 
////        1. Active edge of reset changed from High to Low
 
 
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////                                                              ////
 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
 
////                                                              ////
 
////                                                              ////
 
//// This source file may be used and distributed without         ////
 
//// This source file may be used and distributed without         ////
 
//// restriction provided that this copyright statement is not    ////
 
//// restriction provided that this copyright statement is not    ////
Line 65... Line 68... 
//
 
//
 
//
 
//
 
 
 
 
 
`include "top_defines.v"
 
`include "top_defines.v"
 
 
 
 
 
module oc8051_uart (rst, clk,
 
module oc8051_uart (resetn, clk,
 
             bit_in, data_in,
 
             bit_in, data_in,
 
             wr_addr,
 
             wr_addr,
 
             wr, wr_bit,
 
             wr, wr_bit,
 
             rxd, txd,
 
             rxd, txd,
 
             intr,
 
             intr,
 
             brate2, t1_ow, pres_ow,
 
             brate2, t1_ow, pres_ow,
 
             rclk, tclk,
 
             rclk, tclk,
 
//registers
 
//registers
 
             scon, pcon, sbuf);
 
             scon, pcon, sbuf);
 
 
 
 
 
input        rst,
 
input        resetn,
 
             clk,
 
             clk,
 
             bit_in,
 
             bit_in,
 
             wr,
 
             wr,
 
             rxd,
 
             rxd,
 
             wr_bit,
 
             wr_bit,
Line 129... Line 132... 
assign ren = scon[4];
 
assign ren = scon[4];
 
assign tb8 = scon[3];
 
assign tb8 = scon[3];
 
assign rb8 = scon[2];
 
assign rb8 = scon[2];
 
assign ri  = scon[0];
 
assign ri  = scon[0];
 
 
 
 
 
always @(posedge clk or posedge rst)
 
always @(posedge clk or negedge resetn)
 
begin
 
begin
 
  if (rst)
 
  if (resetn == 1'b0)
 
    scon <= #1 `OC8051_RST_SCON;
 
    scon <= #1 `OC8051_RST_SCON;
 
  else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
 
  else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
 
    scon <= #1 data_in;
 
    scon <= #1 data_in;
 
  else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
 
  else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
 
    scon[wr_addr[2:0]] <= #1 bit_in;
 
    scon[wr_addr[2:0]] <= #1 bit_in;
Line 155... Line 158... 
//
 
//
 
//power control register
 
//power control register
 
//
 
//
 
wire smod;
 
wire smod;
 
assign smod = pcon[7];
 
assign smod = pcon[7];
 
always @(posedge clk or posedge rst)
 
always @(posedge clk or negedge resetn)
 
begin
 
begin
 
  if (rst)
 
  if (resetn == 1'b0)
 
  begin
 
  begin
 
    pcon <= #1 `OC8051_RST_PCON;
 
    pcon <= #1 `OC8051_RST_PCON;
 
  end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
 
  end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
 
    pcon <= #1 data_in;
 
    pcon <= #1 data_in;
 
end
 
end
Line 172... Line 175... 
//
 
//
 
 
 
 
 
wire wr_sbuf;
 
wire wr_sbuf;
 
assign wr_sbuf = (wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit);
 
assign wr_sbuf = (wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit);
 
 
 
 
 
always @(posedge clk or posedge rst)
 
always @(posedge clk or negedge resetn)
 
begin
 
begin
 
  if (rst) begin
 
  if (resetn == 1'b0) begin
 
    txd      <= #1 1'b1;
 
    txd      <= #1 1'b1;
 
    tr_count <= #1 4'd0;
 
    tr_count <= #1 4'd0;
 
    trans    <= #1 1'b0;
 
    trans    <= #1 1'b0;
 
    sbuf_txd <= #1 11'h00;
 
    sbuf_txd <= #1 11'h00;
 
    tx_done  <= #1 1'b0;
 
    tx_done  <= #1 1'b0;
Line 242... Line 245... 
  end else begin //
 
  end else begin //
 
    sc_clk_tr = !t1_ow_buf & t1_ow;
 
    sc_clk_tr = !t1_ow_buf & t1_ow;
 
  end
 
  end
 
end
 
end
 
 
 
 
 
always @(posedge clk or posedge rst)
 
always @(posedge clk or negedge resetn)
 
begin
 
begin
 
  if (rst) begin
 
  if (resetn == 1'b0) begin
 
    smod_clk_tr <= #1 1'b0;
 
    smod_clk_tr <= #1 1'b0;
 
    shift_tr    <= #1 1'b0;
 
    shift_tr    <= #1 1'b0;
 
  end else if (sc_clk_tr) begin
 
  end else if (sc_clk_tr) begin
 
    if (smod) begin
 
    if (smod) begin
 
      shift_tr <= #1 1'b1;
 
      shift_tr <= #1 1'b1;
Line 263... Line 266... 
 
 
 
 
 
 
 
 
//
 
//
 
//serial port buffer (receive)
 
//serial port buffer (receive)
 
//
 
//
 
always @(posedge clk or posedge rst)
 
always @(posedge clk or negedge resetn)
 
begin
 
begin
 
  if (rst) begin
 
  if (resetn == 1'b0) begin
 
    re_count     <= #1 4'd0;
 
    re_count     <= #1 4'd0;
 
    receive      <= #1 1'b0;
 
    receive      <= #1 1'b0;
 
    sbuf_rxd     <= #1 8'h00;
 
    sbuf_rxd     <= #1 8'h00;
 
    sbuf_rxd_tmp <= #1 12'd0;
 
    sbuf_rxd_tmp <= #1 12'd0;
 
    rx_done      <= #1 1'b1;
 
    rx_done      <= #1 1'b1;
Line 323... Line 326... 
  end else begin //
 
  end else begin //
 
    sc_clk_re = !t1_ow_buf & t1_ow;
 
    sc_clk_re = !t1_ow_buf & t1_ow;
 
  end
 
  end
 
end
 
end
 
 
 
 
 
always @(posedge clk or posedge rst)
 
always @(posedge clk or negedge resetn)
 
begin
 
begin
 
  if (rst) begin
 
  if (resetn == 1'b0) begin
 
    smod_clk_re <= #1 1'b0;
 
    smod_clk_re <= #1 1'b0;
 
    shift_re    <= #1 1'b0;
 
    shift_re    <= #1 1'b0;
 
  end else if (sc_clk_re) begin
 
  end else if (sc_clk_re) begin
 
    if (smod) begin
 
    if (smod) begin
 
      shift_re <= #1 1'b1;
 
      shift_re <= #1 1'b1;
Line 346... Line 349... 
 
 
 
 
//
 
//
 
//
 
//
 
//
 
//
 
 
 
 
 
always @(posedge clk or posedge rst)
 
always @(posedge clk or negedge resetn)
 
begin
 
begin
 
  if (rst) begin
 
  if (resetn == 1'b0) begin
 
    t1_ow_buf <= #1 1'b0;
 
    t1_ow_buf <= #1 1'b0;
 
  end else begin
 
  end else begin
 
    t1_ow_buf <= #1 t1_ow;
 
    t1_ow_buf <= #1 t1_ow;
 
  end
 
  end
 
end
 
end

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