//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 cache ram ////
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//// 8051 cache ram ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// http://www.opencores.org/cores/8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// 64x32 dual port ram for instruction cache ////
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//// 64x32 dual port ram for instruction cache ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/10/24 13:37:43 simont
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// Revision 1.2 2002/10/24 13:37:43 simont
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// add parameters
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// add parameters
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//
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//
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// Revision 1.1 2002/10/23 16:58:21 simont
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// Revision 1.1 2002/10/23 16:58:21 simont
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// initial import
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// initial import
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module oc8051_cache_ram (clk, rst, addr0, data0, addr1, data1_i, data1_o, wr1);
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module oc8051_cache_ram (clk, rst, addr0, data0, addr1, data1_i, data1_o, wr1);
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//
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//
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// this module is part of oc8051_icache
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// this module is part of oc8051_icache
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// it's tehnology dependent
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// it's tehnology dependent
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//
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//
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// clk (in) clock
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// clk (in) clock
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// addr0 (in) addres port 0
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// addr0 (in) addres port 0
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// data0 (out) data output port 0
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// data0 (out) data output port 0
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// addr1 (in) address port 1
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// addr1 (in) address port 1
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// data1_i (in) data input port 1
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// data1_i (in) data input port 1
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// data1_o (out) data output port 1
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// data1_o (out) data output port 1
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// wr1 (in) write port 1
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// wr1 (in) write port 1
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//
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//
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parameter ADR_WIDTH = 7; // cache address wihth
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parameter ADR_WIDTH = 7; // cache address wihth
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parameter CACHE_RAM = 128; // cache ram x 32 (2^ADR_WIDTH)
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parameter CACHE_RAM = 128; // cache ram x 32 (2^ADR_WIDTH)
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input clk, wr1, rst;
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input clk, wr1, rst;
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input [ADR_WIDTH-1:0] addr0, addr1;
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input [ADR_WIDTH-1:0] addr0, addr1;
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input [31:0] data1_i;
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input [31:0] data1_i;
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output [31:0] data0, data1_o;
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output [31:0] data0, data1_o;
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`ifdef OC8051_XILINX_RAM
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`ifdef OC8051_XILINX_RAM
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RAMB4_S8_S8 ram1(.DOA(data0[7:0]), .DOB(data1_o[7:0]), .ADDRA({2'b0, addr0}), .DIA(8'h00), .ENA(1'b1), .CLKA(clk), .WEA(1'b0),
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RAMB4_S8_S8 ram1(.DOA(data0[7:0]), .DOB(data1_o[7:0]), .ADDRA({2'b0, addr0}), .DIA(8'h00), .ENA(1'b1), .CLKA(clk), .WEA(1'b0),
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.RSTA(rst), .ADDRB({2'b0, addr1}), .DIB(data1_i[7:0]), .ENB(1'b1), .CLKB(clk), .WEB(wr1), .RSTB(rst));
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.RSTA(rst), .ADDRB({2'b0, addr1}), .DIB(data1_i[7:0]), .ENB(1'b1), .CLKB(clk), .WEB(wr1), .RSTB(rst));
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RAMB4_S8_S8 ram2(.DOA(data0[15:8]), .DOB(data1_o[15:8]), .ADDRA({2'b0, addr0}), .DIA(8'h00), .ENA(1'b1), .CLKA(clk), .WEA(1'b0),
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RAMB4_S8_S8 ram2(.DOA(data0[15:8]), .DOB(data1_o[15:8]), .ADDRA({2'b0, addr0}), .DIA(8'h00), .ENA(1'b1), .CLKA(clk), .WEA(1'b0),
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.RSTA(rst), .ADDRB({2'b0, addr1}), .DIB(data1_i[15:8]), .ENB(1'b1), .CLKB(clk), .WEB(wr1), .RSTB(rst));
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.RSTA(rst), .ADDRB({2'b0, addr1}), .DIB(data1_i[15:8]), .ENB(1'b1), .CLKB(clk), .WEB(wr1), .RSTB(rst));
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RAMB4_S8_S8 ram3(.DOA(data0[23:16]), .DOB(data1_o[23:16]), .ADDRA({2'b0, addr0}), .DIA(8'h00), .ENA(1'b1), .CLKA(clk), .WEA(1'b0),
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RAMB4_S8_S8 ram3(.DOA(data0[23:16]), .DOB(data1_o[23:16]), .ADDRA({2'b0, addr0}), .DIA(8'h00), .ENA(1'b1), .CLKA(clk), .WEA(1'b0),
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.RSTA(rst), .ADDRB({2'b0, addr1}), .DIB(data1_i[23:16]), .ENB(1'b1), .CLKB(clk), .WEB(wr1), .RSTB(rst));
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.RSTA(rst), .ADDRB({2'b0, addr1}), .DIB(data1_i[23:16]), .ENB(1'b1), .CLKB(clk), .WEB(wr1), .RSTB(rst));
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RAMB4_S8_S8 ram4(.DOA(data0[31:24]), .DOB(data1_o[31:24]), .ADDRA({2'b0, addr0}), .DIA(8'h00), .ENA(1'b1), .CLKA(clk), .WEA(1'b0),
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RAMB4_S8_S8 ram4(.DOA(data0[31:24]), .DOB(data1_o[31:24]), .ADDRA({2'b0, addr0}), .DIA(8'h00), .ENA(1'b1), .CLKA(clk), .WEA(1'b0),
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.RSTA(rst), .ADDRB({2'b0, addr1}), .DIB(data1_i[31:24]), .ENB(1'b1), .CLKB(clk), .WEB(wr1), .RSTB(rst));
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.RSTA(rst), .ADDRB({2'b0, addr1}), .DIB(data1_i[31:24]), .ENB(1'b1), .CLKB(clk), .WEB(wr1), .RSTB(rst));
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`else
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`else
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reg [31:0] data0, data1_o;
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reg [31:0] data0, data1_o;
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//
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//
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// buffer
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// buffer
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reg [31:0] buff [0:CACHE_RAM];
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reg [31:0] buff [0:CACHE_RAM];
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//
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//
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// port 1
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// port 1
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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data1_o <= #1 32'h0;
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data1_o <= #1 32'h0;
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else if (wr1) begin
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else if (wr1) begin
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buff[addr1] <= #1 data1_i;
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buff[addr1] <= #1 data1_i;
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data1_o <= #1 data1_i;
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data1_o <= #1 data1_i;
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end else
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end else
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data1_o <= #1 buff[addr1];
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data1_o <= #1 buff[addr1];
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end
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end
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//
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//
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// port 0
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// port 0
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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data0 <= #1 32'h0;
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data0 <= #1 32'h0;
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else if ((addr0==addr1) & wr1)
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else if ((addr0==addr1) & wr1)
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data0 <= #1 data1_i;
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data0 <= #1 data1_i;
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else
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else
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data0 <= #1 buff[addr0];
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data0 <= #1 buff[addr0];
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end
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end
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`endif
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`endif
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endmodule
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endmodule
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