//==============================================================
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//==============================================================
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// Test reset circuit
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// Test reset circuit
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//==============================================================
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//==============================================================
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`timescale 100 ns/ 100 ns
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`timescale 100 ns/ 100 ns
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module test_reset;
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module test_reset;
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// ----------------- CLOCKS AND RESET -----------------
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// ----------------- CLOCKS AND RESET -----------------
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`define T #2
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`define T #2
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bit clk = 1;
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bit clk = 1;
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initial repeat (40) #1 clk = ~clk;
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initial repeat (40) #1 clk = ~clk;
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// Specific to FPGA, some modules in the schematic need to be pre-initialized
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// Specific to FPGA, some modules in the schematic need to be pre-initialized
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reg fpga_reset = 1;
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reg fpga_reset = 1;
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always_latch
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always_latch
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if (clk) fpga_reset <= 0;
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if (clk) fpga_reset <= 0;
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//----------------------------------------------------------
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//----------------------------------------------------------
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// Input reset from the pin; state from the sequencer
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// Input reset from the pin; state from the sequencer
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//----------------------------------------------------------
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//----------------------------------------------------------
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logic reset_in = 0;
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logic reset_in = 0;
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logic M1 = 0;
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logic M1 = 0;
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logic T2 = 0;
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logic T2 = 0;
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wire clrpc; // Load 0 to PC
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wire clrpc; // Load 0 to PC
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wire hold_clk_wait; // Hold clrpc
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wire nreset; // Internal inverted reset signal
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wire nreset; // Internal inverted reset signal
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assign hold_clk_wait = 0; // Will not test this case
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// ----------------- TEST -------------------
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// ----------------- TEST -------------------
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initial begin
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initial begin
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// Test normal reset sequence - 3 clocks long
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// Test normal reset sequence - 3 clocks long
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`T reset_in = 1;
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`T reset_in = 1;
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`T `T `T reset_in = 0;
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`T `T `T reset_in = 0;
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`T assert(nreset==0);
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`T assert(nreset==0);
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// Out of the reset for several more cycles
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// Out of the reset for several more cycles
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// Check that the clrpc is set for the next 2 1/2 cycles (see waveform)
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// Check that the clrpc is set for the next 2 1/2 cycles (see waveform)
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`T assert(nreset==1 && clrpc==1);
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`T assert(nreset==1 && clrpc==1);
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`T assert(nreset==1 && clrpc==1);
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`T assert(nreset==1 && clrpc==1);
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`T assert(nreset==1 && clrpc==0);
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`T assert(nreset==1 && clrpc==0);
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`T assert(nreset==1 && clrpc==0);
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`T assert(nreset==1 && clrpc==0);
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`T assert(nreset==1 && clrpc==0);
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`T assert(nreset==1 && clrpc==0);
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// Test special reset sequence: a reset pin is briefly
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// Test special reset sequence: a reset pin is briefly
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// asserted at M1/T1 and CLRPC should hold until the next
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// asserted at M1/T1 and CLRPC should hold until the next
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// M1/T2
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// M1/T2
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`T reset_in = 1; M1=1;
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`T reset_in = 1; M1=1;
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`T reset_in = 0; M1=1; T2=1;
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`T reset_in = 0; M1=1; T2=1;
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`T M1=1; T2=0;
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`T M1=1; T2=0;
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`T `T
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`T `T
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`T assert(nreset==1 && clrpc==1);
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`T assert(nreset==1 && clrpc==1);
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`T M1=1; T2=1;
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`T M1=1; T2=1;
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`T M1=1; T2=0;
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`T M1=1; T2=0;
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`T assert(nreset==1 && clrpc==0);
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`T assert(nreset==1 && clrpc==0);
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`T $display("End of test");
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`T $display("End of test");
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end
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end
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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// Instantiate DUT
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// Instantiate DUT
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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resets reset_block ( .* );
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resets reset_block ( .* );
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endmodule
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endmodule
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