`timescale 1ns / 10ps
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`timescale 1ns / 10ps
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module tb ();
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module tb ();
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reg clk;
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reg clk;
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reg reset_n;
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reg reset;
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reg [7:0] din;
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reg [7:0] din;
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wire [7:0] dout;
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wire [7:0] dout;
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reg key_start;
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reg key_start;
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reg [255:0] key_in;
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reg [255:0] key_in;
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reg data_in_valid;
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reg data_in_valid;
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reg [127:0] data_in;
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reg [127:0] data_in;
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wire key_ready;
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wire key_ready;
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wire ready_out;
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wire ready_out;
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reg enable;
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reg enable;
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initial
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initial
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begin
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begin
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clk = 1'b1;
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clk = 1'b1;
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key_in = 1'b0;
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key_in = 1'b0;
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key_start = 1'b0;
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key_start = 1'b0;
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data_in_valid = 1'b0;
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data_in_valid = 1'b0;
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reset_n = 1'b0;
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reset = 1'b1;
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enable = 1;
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enable = 1;
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#100;
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#100;
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reset_n = 1'b1;
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reset = 1'b0;
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#100;
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#100;
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din = 8'hae;
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din = 8'hae;
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@ (posedge clk);
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@ (posedge clk);
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key_start <= 1'b1;
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key_start <= 1'b1;
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//key_in[255:128] = 128'h2b7e151628aed2a6abf7158809cf4f3c;
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//key_in[255:128] = 128'h2b7e151628aed2a6abf7158809cf4f3c;
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//key_in[255:64] = 192'h8e73b0f7da0e6452c810f32b809079e562f8ead2522c6b7b;
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//key_in[255:64] = 192'h8e73b0f7da0e6452c810f32b809079e562f8ead2522c6b7b;
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//key_in[255:0] = 256'h603deb1015ca71be2b73aef0857d77811f352c073b6108d72d9810a30914dff4;
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//key_in[255:0] = 256'h603deb1015ca71be2b73aef0857d77811f352c073b6108d72d9810a30914dff4;
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key_in[255:64] = 192'h000102030405060708090a0b0c0d0e0f1011121314151617;
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key_in[255:64] = 192'h000102030405060708090a0b0c0d0e0f1011121314151617;
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//key_in[255:0] = 256'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f;
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//key_in[255:0] = 256'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f;
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@ (posedge clk);
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@ (posedge clk);
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key_start <= 1'b0;
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key_start <= 1'b0;
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wait (key_ready);
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wait (key_ready);
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data_in_valid <= 1'b1;
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data_in_valid <= 1'b1;
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//data_in[127:0] = 128'h3243f6a8885a308d313198a2e0370731;
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//data_in[127:0] = 128'h3243f6a8885a308d313198a2e0370731;
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//data_in[127:0] = 128'h00112233445566778899aabbccddeeff;
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//data_in[127:0] = 128'h00112233445566778899aabbccddeeff;
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//data_in[127:0] = 128'h8ea2b7ca516745bfeafc49904b496089;
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//data_in[127:0] = 128'h8ea2b7ca516745bfeafc49904b496089;
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data_in[127:0] = 128'hdda97ca4864cdfe06eaf70a0ec0d7191;
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data_in[127:0] = 128'hdda97ca4864cdfe06eaf70a0ec0d7191;
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//@ (posedge clk);
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//@ (posedge clk);
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//data_in[127:0] = 128'h3243f6a8885a308d313198a2e0370734;
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//data_in[127:0] = 128'h3243f6a8885a308d313198a2e0370734;
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//@ (posedge clk);
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//@ (posedge clk);
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//data_in_valid <= 1'b0;
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//data_in_valid <= 1'b0;
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//data_in[127:0] = 128'h3243f6a8885a308d313198a2e0370731;
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//data_in[127:0] = 128'h3243f6a8885a308d313198a2e0370731;
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//@ (posedge clk);
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//@ (posedge clk);
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//data_in_valid <= 1'b1;
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//data_in_valid <= 1'b1;
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//data_in[127:0] = 128'h3243f6a8885a308d313198a2e0370734;
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//data_in[127:0] = 128'h3243f6a8885a308d313198a2e0370734;
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//data_in[127:0] = 128'h00112233445566778899aabbccddeeff;
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//data_in[127:0] = 128'h00112233445566778899aabbccddeeff;
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@ (posedge clk);
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@ (posedge clk);
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data_in_valid <= 1'b0;
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data_in_valid <= 1'b0;
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repeat (3) @ (posedge clk);
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repeat (3) @ (posedge clk);
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wait (ready_out);
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wait (ready_out);
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@ (posedge clk);
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@ (posedge clk);
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//data_in_valid <= 1'b1;
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//data_in_valid <= 1'b1;
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@ (posedge clk);
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@ (posedge clk);
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data_in_valid <= 1'b0;
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data_in_valid <= 1'b0;
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repeat (6) @(posedge clk);
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repeat (6) @(posedge clk);
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//enable <= 0;
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//enable <= 0;
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//repeat (15) @(posedge clk);
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//repeat (15) @(posedge clk);
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//enable <= 1;
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//enable <= 1;
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#200;
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#200;
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//$display("dout is %h",dout);
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//$display("dout is %h",dout);
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din = 8'h1e;
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din = 8'h1e;
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#2000;
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#2000;
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//$display("dout is %h",dout);
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//$display("dout is %h",dout);
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#100;
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#100;
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$finish;
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$finish;
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end
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end
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/*sbox u_sbox(
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/*sbox u_sbox(
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.clk(clk),
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.clk(clk),
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.reset_n(reset_n),
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.reset_n(reset_n),
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.din(din),
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.din(din),
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.ende(1'b1),
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.ende(1'b1),
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.dout(dout));*/
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.dout(dout));*/
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//wire wr;
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//wire wr;
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//wire [4:0] wr_addr;
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//wire [4:0] wr_addr;
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//wire [63:0] wr_data;
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//wire [63:0] wr_data;
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wire [127:0] data_out;
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wire [127:0] data_out;
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aes dut(
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aes dut(
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.clk(clk),
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.clk(clk),
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.reset_n(reset_n),
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.reset(reset),
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.i_start(key_start),
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.i_start(key_start),
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.i_enable(enable), //TBD
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.i_enable(enable), //TBD
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.i_ende(1'b1),
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.i_ende(1'b1),
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.i_key(key_in),
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.i_key(key_in),
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.i_key_mode(2'b01),
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.i_key_mode(2'b01),
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.i_data(data_in),
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.i_data(data_in),
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.i_data_valid(data_in_valid),
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.i_data_valid(data_in_valid),
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.o_ready(ready_out),
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.o_ready(ready_out),
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.o_data(data_out),
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.o_data(data_out),
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.o_data_valid(data_out_valid),
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.o_data_valid(data_out_valid),
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.o_key_ready(key_ready)
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.o_key_ready(key_ready)
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);
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);
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/*key_exp u_key_exp (
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/*key_exp u_key_exp (
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.clk(clk),
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.clk(clk),
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.reset_n(reset_n),
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.reset_n(reset_n),
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.key_in(key_in),
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.key_in(key_in),
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.key_mode(2'b10),
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.key_mode(2'b10),
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.key_start(key_start),
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.key_start(key_start),
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.wr(wr),
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.wr(wr),
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.wr_addr(wr_addr),
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.wr_addr(wr_addr),
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.wr_data(wr_data)
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.wr_data(wr_data)
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);*/
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);*/
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always @ (posedge clk)
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always @ (posedge clk)
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if (data_out_valid)
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if (data_out_valid)
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$display("DATA: %16h",data_out);
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$display("DATA: %16h",data_out);
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always
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always
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#10 clk = ~clk;
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#10 clk = ~clk;
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endmodule
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endmodule
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