//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Ram module ////
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//// Ram module ////
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//// ////
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//// ////
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//// Description: ////
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//// Description: ////
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//// this is 16x64, we can use a 16x128 to replace two of this ////
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//// this is 16x64, we can use a 16x128 to replace two of this ////
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//// module, also, can use specific foundry libs instead ////
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//// module, also, can use specific foundry libs instead ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - done ////
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//// - done ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Luo Dongjun, dongjun_luo@hotmail.com ////
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//// - Luo Dongjun, dongjun_luo@hotmail.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module ram_16x64 (clk,wr,wr_addr,wr_data,rd,rd_addr,rd_data);
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module ram_16x64 (clk,wr,wr_addr,wr_data,rd,rd_addr,rd_data);
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input clk,wr,rd;
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input clk,wr,rd;
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input [3:0] wr_addr,rd_addr;
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input [3:0] wr_addr,rd_addr;
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input [63:0] wr_data;
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input [63:0] wr_data;
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output [63:0] rd_data;
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output [63:0] rd_data;
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reg [63:0] mem[15:0];
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reg [63:0] mem[15:0];
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wire [63:0] rd_data;
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wire [63:0] rd_data;
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// behavioral code for 16x64 mem
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// behavioral code for 16x64 mem
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (wr)
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if (wr)
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mem[wr_addr] <= wr_data;
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mem[wr_addr] <= wr_data;
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end
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end
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//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI
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reg [3:0] srd_addr;
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reg [3:0] srd_addr;
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (rd)
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if (rd)
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srd_addr <= rd_addr;
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srd_addr <= rd_addr;
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end
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end
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assign rd_data = mem[srd_addr];
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assign rd_data = mem[srd_addr];
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//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI
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// always @ (posedge clk)
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// begin
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// if (rd)
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// rd_data <= mem[rd_addr];
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// end
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//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI
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endmodule
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endmodule
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