URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
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Rev 17 |
Rev 48 |
$HashRef = bless( {
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$HashRef = bless( {
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'connection_num' => 'multi connection',
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'connection_num' => 'multi connection',
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'name' => 'clk',
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'name' => 'clk',
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'description' => 'clock source',
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'description' => 'clock source',
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'modules' => {
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'modules' => {
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'clk_socket' => {},
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'clk_socket' => {},
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'wb_master_socket' => {},
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'wb_master_socket' => {},
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'wb_slave_socket' => {},
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'wb_slave_socket' => {},
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'reset_socket' => {}
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'reset_socket' => {}
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},
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},
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'ports' => {
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'ports' => {
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'clk_o' => {
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'clk_o' => {
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'outport_type' => 'concatenate',
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'outport_type' => 'concatenate',
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'connect_name' => 'clk_i',
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'connect_name' => 'clk_i',
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'name' => 'clk_o',
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'name' => 'clk_o',
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'range' => '',
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'range' => '',
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'connect_type' => 'input',
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'connect_type' => 'input',
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'connect_range' => '',
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'connect_range' => '',
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'default_out' => 'Active low',
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'default_out' => 'Active low',
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'type' => 'output'
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'type' => 'output'
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}
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}
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},
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},
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'file_name' => '/home/alireza/Mywork/develop/gui/main/lib/verilog/bus.v',
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'file_name' => 'mpsoc/perl_gui/lib/verilog/bus.v',
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'module_name' => 'clk_socket',
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'module_name' => 'clk_socket',
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'type' => 'socket',
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'type' => 'socket',
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'category' => 'source'
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'category' => 'source'
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}, 'intfc_gen' );
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}, 'intfc_gen' );
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