/*********************************************************************
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/*********************************************************************
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File: wb_master.v
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File: wb_master.v
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Copyright (C) 2014 Alireza Monemi
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Copyright (C) 2014 Alireza Monemi
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This program is free software: you can redistribute it and/or modify
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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Purpose:
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Purpose:
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generating the wishbone bus.
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generating the wishbone bus interfaces.
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Info: monemi@fkegraduate.utm.my
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Info: monemi@fkegraduate.utm.my
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****************************************************************/
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****************************************************************/
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module wb_master_socket #(
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module wb_master_socket #(
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parameter Dw = 32, // maximum data width
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parameter Dw = 32, // maximum data width
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parameter Aw = 32, // address width
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parameter Aw = 32, // address width
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parameter SELw = 2,
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parameter SELw = 2,
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parameter TAGw = 3 , //merged {tga,tgb,tgc}
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parameter TAGw = 3 , //merged {tga,tgb,tgc}
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parameter CTIw = 3,
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parameter CTIw = 3,
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parameter BTEw = 2
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parameter BTEw = 2
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)
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)
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(
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(
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//masters interface
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//masters interface
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output [Dw-1 : 0] dat_o,
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output [Dw-1 : 0] dat_o,
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output ack_o,
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output ack_o,
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output err_o,
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output err_o,
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output rty_o,
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output rty_o,
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input [Aw-1 : 0] adr_i,
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input [Aw-1 : 0] adr_i,
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input [Dw-1 : 0] dat_i,
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input [Dw-1 : 0] dat_i,
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input [SELw-1 : 0] sel_i,
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input [SELw-1 : 0] sel_i,
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input [TAGw-1 : 0] tag_i,
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input [TAGw-1 : 0] tag_i,
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input we_i,
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input we_i,
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input stb_i,
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input stb_i,
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input cyc_i,
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input cyc_i,
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input [CTIw-1 : 0] cti_i,
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input [CTIw-1 : 0] cti_i,
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input [BTEw-1 : 0] bte_i
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input [BTEw-1 : 0] bte_i
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//address compar
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//address compar
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//m_grant_addr,
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//m_grant_addr,
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//s_sel_one_hot,
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//s_sel_one_hot,
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);
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);
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endmodule
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endmodule
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module wb_slave_socket #(
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module wb_slave_socket #(
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parameter Dw = 32, // maximum data width
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parameter Dw = 32, // maximum data width
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parameter Aw = 32, // address width
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parameter Aw = 32, // address width
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parameter SELw = 2,
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parameter SELw = 2,
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parameter TAGw = 3, //merged {tga,tgb,tgc}
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parameter TAGw = 3, //merged {tga,tgb,tgc}
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parameter CTIw = 3,
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parameter CTIw = 3,
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parameter BTEw = 2
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parameter BTEw = 2
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)
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)
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(
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(
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output [Aw-1 : 0] adr_o,
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output [Aw-1 : 0] adr_o,
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output [Dw-1 : 0] dat_o,
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output [Dw-1 : 0] dat_o,
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output [SELw-1 : 0] sel_o,
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output [SELw-1 : 0] sel_o,
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output [TAGw-1 : 0] tag_o,
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output [TAGw-1 : 0] tag_o,
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output we_o,
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output we_o,
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output cyc_o,
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output cyc_o,
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output stb_o,
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output stb_o,
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output [CTIw-1 : 0] cti_o,
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output [CTIw-1 : 0] cti_o,
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output [BTEw-1 : 0] bte_o,
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output [BTEw-1 : 0] bte_o,
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input [DwS-1 : 0] dat_i,
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input [DwS-1 : 0] dat_i,
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input ack_i,
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input ack_i,
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input err_i,
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input err_i,
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input rty_i
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input rty_i
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);
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);
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endmodule
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endmodule
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module clk_socket(
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module clk_socket(
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output clk_o
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output clk_o
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);
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);
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endmodule
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endmodule
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module reset_socket(
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module reset_socket(
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output reset_o
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output reset_o
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);
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);
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endmodule
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endmodule
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