`include "pronoc_def.v"
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`include "pronoc_def.v"
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/**********************************************************************
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/**********************************************************************
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** File: header_flit.sv
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** File: header_flit.sv
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** Date:2017-07-11
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** Date:2017-07-11
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**
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**
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** Copyright (C) 2014-2017 Alireza Monemi
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** Copyright (C) 2014-2017 Alireza Monemi
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**
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**
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** This file is part of ProNoC
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** This file is part of ProNoC
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**
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**
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** you can redistribute it and/or modify it under the terms of the GNU
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** you can redistribute it and/or modify it under the terms of the GNU
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** Lesser General Public License as published by the Free Software Foundation,
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** Lesser General Public License as published by the Free Software Foundation,
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** either version 2 of the License, or (at your option) any later version.
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** either version 2 of the License, or (at your option) any later version.
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**
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**
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with ProNoC. If not, see .
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** License along with ProNoC. If not, see .
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**
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**
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**
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**
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** Description:
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** Description:
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** This file contains modules related to header flit
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** This file contains modules related to header flit
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******************************************************************/
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******************************************************************/
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/***************
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/***************
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* header_flit_generator
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* header_flit_generator
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***************/
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***************/
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module header_flit_generator
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module header_flit_generator #(
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import pronoc_pkg::*;
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parameter NOC_ID=0,
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#(
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parameter DATA_w = 9 // header flit can carry Optional data. The data will be placed after control data. Fpay >= DATA_w + CTRL_BITS_w
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parameter DATA_w = 9 // header flit can carry Optional data. The data will be placed after control data. Fpay >= DATA_w + CTRL_BITS_w
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|
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)(
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)(
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flit_out,
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flit_out,
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src_e_addr_in,
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src_e_addr_in,
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dest_e_addr_in,
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dest_e_addr_in,
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destport_in,
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destport_in,
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class_in,
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class_in,
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weight_in,
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weight_in,
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vc_num_in,
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vc_num_in,
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be_in,
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be_in,
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data_in
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data_in
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);
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);
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`NOC_CONF
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function integer log2;
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localparam HDR_FLAG = 2'b10;
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input integer number; begin
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log2=(number <=1) ? 1: 0;
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while(2**log2
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log2=log2+1;
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end
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end
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endfunction // log2
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/* verilator lint_off WIDTH */
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localparam
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Cw = (C>1)? log2(C): 1,
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HDR_FLAG = 2'b10,
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BEw = (BYTE_EN)? log2(Fpay/8) : 1;
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/* verilator lint_on WIDTH */
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localparam
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localparam
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Dw = (DATA_w==0)? 1 : DATA_w,
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Dw = (DATA_w==0)? 1 : DATA_w,
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DATA_LSB= MSB_BE+1, DATA_MSB= (DATA_LSB + DATA_w)
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DATA_LSB= MSB_BE+1, DATA_MSB= (DATA_LSB + DATA_w)
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output [Fw-1 : 0] flit_out;
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output [Fw-1 : 0] flit_out;
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input [Cw-1 : 0] class_in;
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input [Cw-1 : 0] class_in;
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input [DAw-1 : 0] dest_e_addr_in;
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input [DAw-1 : 0] dest_e_addr_in;
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input [EAw-1 : 0] src_e_addr_in;
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input [EAw-1 : 0] src_e_addr_in;
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input [V-1 : 0] vc_num_in;
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input [V-1 : 0] vc_num_in;
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input [WEIGHTw-1 : 0] weight_in;
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input [WEIGHTw-1 : 0] weight_in;
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input [DSTPw-1 : 0] destport_in;
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input [DSTPw-1 : 0] destport_in;
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input [BEw-1 : 0] be_in;
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input [BEw-1 : 0] be_in;
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input [Dw-1 : 0] data_in;
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input [Dw-1 : 0] data_in;
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// assign flit_out [W+Cw+P_1+Xw+Yw+Xw+Yw-1 :0] = {weight_i,class_i,destport_i,x_dst_i,y_dst_i,x_src_i,y_src_i};
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// assign flit_out [W+Cw+P_1+Xw+Yw+Xw+Yw-1 :0] = {weight_i,class_i,destport_i,x_dst_i,y_dst_i,x_src_i,y_src_i};
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assign flit_out [E_SRC_MSB : E_SRC_LSB] = src_e_addr_in;
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assign flit_out [E_SRC_MSB : E_SRC_LSB] = src_e_addr_in;
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assign flit_out [E_DST_MSB : E_DST_LSB] = dest_e_addr_in;
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assign flit_out [E_DST_MSB : E_DST_LSB] = dest_e_addr_in;
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assign flit_out [DST_P_MSB : DST_P_LSB] = destport_in;
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assign flit_out [DST_P_MSB : DST_P_LSB] = destport_in;
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generate
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generate
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if(C>1)begin :have_class
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if(C>1)begin :have_class
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assign flit_out [CLASS_MSB :CLASS_LSB] = class_in;
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assign flit_out [CLASS_MSB :CLASS_LSB] = class_in;
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end
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end
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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if(SWA_ARBITER_TYPE != "RRA")begin : wrra_b
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if(SWA_ARBITER_TYPE != "RRA")begin : wrra_b
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/* verilator lint_on WIDTH */
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/* verilator lint_on WIDTH */
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assign flit_out [WEIGHT_MSB :WEIGHT_LSB] = weight_in;
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assign flit_out [WEIGHT_MSB :WEIGHT_LSB] = weight_in;
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end
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end
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if( BYTE_EN ) begin : be_1
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if( BYTE_EN ) begin : be_1
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assign flit_out [BE_MSB : BE_LSB] = be_in;
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assign flit_out [BE_MSB : BE_LSB] = be_in;
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end
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end
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if (DATA_w ==0) begin :no_data
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if (DATA_w ==0) begin :no_data
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if(FPAYw>DATA_LSB) begin: dontcare
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if(FPAYw>DATA_LSB) begin: dontcare
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assign flit_out [FPAYw-1 : DATA_LSB] = {(FPAYw-DATA_LSB){1'bX}};
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assign flit_out [FPAYw-1 : DATA_LSB] = {(FPAYw-DATA_LSB){1'bX}};
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end
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end
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end else begin :have_data
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end else begin :have_data
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assign flit_out [DATA_MSB : DATA_LSB] = data_in[DATA_MSB-DATA_LSB : 0]; // we have enough space for adding whole of the data
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assign flit_out [DATA_MSB : DATA_LSB] = data_in[DATA_MSB-DATA_LSB : 0]; // we have enough space for adding whole of the data
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end
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end
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endgenerate
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endgenerate
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assign flit_out [FPAYw+V-1 : FPAYw] = vc_num_in;
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assign flit_out [FPAYw+V-1 : FPAYw] = vc_num_in;
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assign flit_out [Fw-1 : Fw-2] = HDR_FLAG;
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assign flit_out [Fw-1 : Fw-2] = HDR_FLAG;
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//synthesis translate_off
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//synthesis translate_off
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//synopsys translate_off
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//synopsys translate_off
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initial begin
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initial begin
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if((DATA_LSB + DATA_w)-1 > FPAYw)begin
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if((DATA_LSB + DATA_w)-1 > FPAYw)begin
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$display("%t: ERROR: The reqired header flit size is %d which is larger than %d payload size ",$time,(DATA_LSB + DATA_w)-1,FPAYw);
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$display("%t: ERROR: The reqired header flit size is %d which is larger than %d payload size ",$time,(DATA_LSB + DATA_w)-1,FPAYw);
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$finish;
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$finish;
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end
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end
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end
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end
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//synopsys translate_on
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//synopsys translate_on
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//synthesis translate_on
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//synthesis translate_on
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endmodule
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endmodule
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module extract_header_flit_info # (
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module extract_header_flit_info
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parameter NOC_ID=0,
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import pronoc_pkg::*;
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#(
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parameter DATA_w = 0
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parameter DATA_w = 0
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)(
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) (
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//inputs
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//inputs
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flit_in,
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flit_in,
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flit_in_wr,
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flit_in_wr,
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//outputs
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//outputs
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src_e_addr_o,
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src_e_addr_o,
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dest_e_addr_o,
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dest_e_addr_o,
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destport_o,
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destport_o,
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class_o,
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class_o,
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weight_o,
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weight_o,
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data_o,
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data_o,
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tail_flg_o,
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tail_flg_o,
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hdr_flg_o,
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hdr_flg_o,
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vc_num_o,
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vc_num_o,
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hdr_flit_wr_o,
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hdr_flit_wr_o,
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be_o
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be_o
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);
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);
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`NOC_CONF
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function integer log2;
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input integer number; begin
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log2=(number <=1) ? 1: 0;
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while(2**log2
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log2=log2+1;
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end
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end
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endfunction // log2
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localparam
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localparam
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Cw = (C>1)? log2(C): 1,
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W = WEIGHTw,
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W = WEIGHTw,
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BEw = (BYTE_EN)? log2(Fpay/8) : 1;
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Dw = (DATA_w==0)? 1 : DATA_w,
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DATA_LSB= MSB_BE+1, DATA_MSB= (DATA_LSB + DATA_w)
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localparam
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OFFSETw = DATA_MSB - DATA_LSB +1;
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Dw = (DATA_w==0)? 1 : DATA_w;
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localparam
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DATA_LSB= MSB_BE+1, DATA_MSB= (DATA_LSB + DATA_w)
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localparam OFFSETw = DATA_MSB - DATA_LSB +1;
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input [Fw-1 : 0] flit_in;
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input [Fw-1 : 0] flit_in;
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input flit_in_wr;
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input flit_in_wr;
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output [EAw-1 : 0] src_e_addr_o;
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output [EAw-1 : 0] src_e_addr_o;
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output [DAw-1 : 0] dest_e_addr_o;
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output [DAw-1 : 0] dest_e_addr_o;
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output [DSTPw-1 : 0] destport_o;
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output [DSTPw-1 : 0] destport_o;
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output [Cw-1 : 0] class_o;
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output [Cw-1 : 0] class_o;
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output [W-1 : 0] weight_o;
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output [W-1 : 0] weight_o;
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output tail_flg_o;
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output tail_flg_o;
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output hdr_flg_o;
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output hdr_flg_o;
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output [V-1 : 0] vc_num_o;
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output [V-1 : 0] vc_num_o;
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output [V-1 : 0] hdr_flit_wr_o;
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output [V-1 : 0] hdr_flit_wr_o;
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output [BEw-1 : 0] be_o;
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output [BEw-1 : 0] be_o;
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output [Dw-1 : 0] data_o;
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output [Dw-1 : 0] data_o;
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wire [OFFSETw-1 : 0 ] offset;
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wire [OFFSETw-1 : 0 ] offset;
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assign src_e_addr_o = flit_in [E_SRC_MSB : E_SRC_LSB];
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assign src_e_addr_o = flit_in [E_SRC_MSB : E_SRC_LSB];
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assign dest_e_addr_o = flit_in [E_DST_MSB : E_DST_LSB];
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assign dest_e_addr_o = flit_in [E_DST_MSB : E_DST_LSB];
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assign destport_o = flit_in [DST_P_MSB : DST_P_LSB];
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assign destport_o = flit_in [DST_P_MSB : DST_P_LSB];
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generate
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generate
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if(C>1)begin :have_class
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if(C>1)begin :have_class
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assign class_o = flit_in [CLASS_MSB : CLASS_LSB];
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assign class_o = flit_in [CLASS_MSB : CLASS_LSB];
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end else begin : no_class
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end else begin : no_class
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assign class_o = {Cw{1'b0}};
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assign class_o = {Cw{1'b0}};
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end
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end
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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if(SWA_ARBITER_TYPE != "RRA")begin : wrra_b
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if(SWA_ARBITER_TYPE != "RRA")begin : wrra_b
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/* verilator lint_on WIDTH */
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/* verilator lint_on WIDTH */
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assign weight_o = flit_in [WEIGHT_MSB : WEIGHT_LSB];
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assign weight_o = flit_in [WEIGHT_MSB : WEIGHT_LSB];
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end else begin : rra_b
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end else begin : rra_b
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assign weight_o = {WEIGHTw{1'bX}};
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assign weight_o = {WEIGHTw{1'bX}};
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end
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end
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if( BYTE_EN ) begin : be_1
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if( BYTE_EN ) begin : be_1
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assign be_o = flit_in [BE_MSB : BE_LSB];
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assign be_o = flit_in [BE_MSB : BE_LSB];
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end else begin : be_0
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end else begin : be_0
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assign be_o = {BEw{1'bX}};
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assign be_o = {BEw{1'bX}};
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end
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end
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assign offset = flit_in [DATA_MSB : DATA_LSB];
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assign offset = flit_in [DATA_MSB : DATA_LSB];
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if(Dw > OFFSETw) begin : if1
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if(Dw > OFFSETw) begin : if1
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assign data_o={{(Dw-OFFSETw){1'b0}},offset};
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assign data_o={{(Dw-OFFSETw){1'b0}},offset};
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end else begin : if2
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end else begin : if2
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assign data_o=offset[Dw-1 : 0];
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assign data_o=offset[Dw-1 : 0];
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end
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end
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endgenerate
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endgenerate
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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assign hdr_flg_o = (PCK_TYPE == "MULTI_FLIT") ? flit_in [Fw-1] : 1'b1;
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assign hdr_flg_o = (PCK_TYPE == "MULTI_FLIT") ? flit_in [Fw-1] : 1'b1;
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assign tail_flg_o = (PCK_TYPE == "MULTI_FLIT") ? flit_in [Fw-2] : 1'b1;
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assign tail_flg_o = (PCK_TYPE == "MULTI_FLIT") ? flit_in [Fw-2] : 1'b1;
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/* verilator lint_on WIDTH */
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/* verilator lint_on WIDTH */
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assign vc_num_o = flit_in [FPAYw+V-1 : FPAYw];
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assign vc_num_o = flit_in [FPAYw+V-1 : FPAYw];
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assign hdr_flit_wr_o= (flit_in_wr & hdr_flg_o )? vc_num_o : {V{1'b0}};
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assign hdr_flit_wr_o= (flit_in_wr & hdr_flg_o )? vc_num_o : {V{1'b0}};
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endmodule
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endmodule
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/***********************************
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/***********************************
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* flit_update
|
* flit_update
|
* update the header flit look ahead routing and output VC
|
* update the header flit look ahead routing and output VC
|
**********************************/
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**********************************/
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|
|
module header_flit_update_lk_route_ovc
|
module header_flit_update_lk_route_ovc #(
|
import pronoc_pkg::*;
|
parameter NOC_ID=0,
|
#(
|
|
parameter P = 5
|
parameter P = 5
|
)(
|
)
|
|
(
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flit_in ,
|
flit_in ,
|
flit_out,
|
flit_out,
|
vc_num_in,
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vc_num_in,
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lk_dest_all_in,
|
lk_dest_all_in,
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assigned_ovc_num,
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assigned_ovc_num,
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any_ivc_sw_request_granted,
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any_ivc_sw_request_granted,
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lk_dest_not_registered,
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lk_dest_not_registered,
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sel,
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sel,
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reset,
|
reset,
|
clk
|
clk
|
);
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);
|
|
|
|
`NOC_CONF
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|
|
localparam
|
localparam
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VDSTPw = V * DSTPw,
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VDSTPw = V * DSTPw,
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VV = V * V;
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VV = V * V;
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|
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|
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input [Fw-1 : 0] flit_in;
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input [Fw-1 : 0] flit_in;
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output reg [Fw-1 : 0] flit_out;
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output reg [Fw-1 : 0] flit_out;
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input [V-1 : 0] vc_num_in;
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input [V-1 : 0] vc_num_in;
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input [VDSTPw-1 : 0] lk_dest_all_in;
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input [VDSTPw-1 : 0] lk_dest_all_in;
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input reset,clk;
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input reset,clk;
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input [VV-1 : 0] assigned_ovc_num;
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input [VV-1 : 0] assigned_ovc_num;
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input [V-1 : 0] sel;
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input [V-1 : 0] sel;
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input any_ivc_sw_request_granted;
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input any_ivc_sw_request_granted;
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input [DSTPw-1 : 0] lk_dest_not_registered;
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input [DSTPw-1 : 0] lk_dest_not_registered;
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|
|
wire hdr_flag;
|
wire hdr_flag;
|
logic [V-1 : 0] vc_num_delayed;
|
logic [V-1 : 0] vc_num_delayed;
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wire [V-1 : 0] ovc_num;
|
wire [V-1 : 0] ovc_num;
|
wire [DSTPw-1 : 0] lk_dest,dest_coded;
|
wire [DSTPw-1 : 0] lk_dest,dest_coded;
|
wire [DSTPw-1 : 0] lk_mux_out;
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wire [DSTPw-1 : 0] lk_mux_out;
|
|
|
pronoc_register #(.W(V)) reg1 (.in(vc_num_in), .out(vc_num_delayed), .reset(reset), .clk(clk));
|
pronoc_register #(.W(V)) reg1 (.in(vc_num_in), .out(vc_num_delayed), .reset(reset), .clk(clk));
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/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
assign hdr_flag = ( PCK_TYPE == "MULTI_FLIT")? flit_in[Fw-1]: 1'b1;
|
assign hdr_flag = ( PCK_TYPE == "MULTI_FLIT")? flit_in[Fw-1]: 1'b1;
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
onehot_mux_1D #(
|
onehot_mux_1D #(
|
.W(DSTPw),
|
.W(DSTPw),
|
.N(V)
|
.N(V)
|
)
|
)
|
lkdest_mux
|
lkdest_mux
|
(
|
(
|
.in(lk_dest_all_in),
|
.in(lk_dest_all_in),
|
.out(lk_mux_out),
|
.out(lk_mux_out),
|
.sel(vc_num_delayed)
|
.sel(vc_num_delayed)
|
);
|
);
|
|
|
generate
|
generate
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if( SSA_EN == "YES" ) begin : predict // bypass the lk fifo when no ivc is granted
|
if( SSA_EN == "YES" ) begin : predict // bypass the lk fifo when no ivc is granted
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
logic ivc_any_delayed;
|
logic ivc_any_delayed;
|
|
|
pronoc_register #(.W(1)) reg2 (.in(any_ivc_sw_request_granted ), .out(ivc_any_delayed), .reset(reset), .clk(clk));
|
pronoc_register #(.W(1)) reg2 (.in(any_ivc_sw_request_granted ), .out(ivc_any_delayed), .reset(reset), .clk(clk));
|
|
|
assign lk_dest = (ivc_any_delayed == 1'b0)? lk_dest_not_registered : lk_mux_out;
|
assign lk_dest = (ivc_any_delayed == 1'b0)? lk_dest_not_registered : lk_mux_out;
|
|
|
end else begin : no_predict
|
end else begin : no_predict
|
assign lk_dest =lk_mux_out;
|
assign lk_dest =lk_mux_out;
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
onehot_mux_1D #(
|
onehot_mux_1D #(
|
.W(V),
|
.W(V),
|
.N(V)
|
.N(V)
|
)
|
)
|
ovc_num_mux
|
ovc_num_mux
|
(
|
(
|
.in(assigned_ovc_num),
|
.in(assigned_ovc_num),
|
.out(ovc_num),
|
.out(ovc_num),
|
.sel(vc_num_delayed)
|
.sel(vc_num_delayed)
|
);
|
);
|
|
|
generate
|
generate
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if((TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "RING") && ROUTE_TYPE != "DETERMINISTIC" )begin :coded
|
if((TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "RING") && ROUTE_TYPE != "DETERMINISTIC" )begin :coded
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
mesh_torus_adaptive_lk_dest_encoder #(
|
mesh_torus_adaptive_lk_dest_encoder #(
|
.V(V),
|
.V(V),
|
.P(P),
|
.P(P),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
.Fw(Fw),
|
.Fw(Fw),
|
.DST_P_MSB(DST_P_MSB),
|
.DST_P_MSB(DST_P_MSB),
|
.DST_P_LSB(DST_P_LSB)
|
.DST_P_LSB(DST_P_LSB)
|
)
|
)
|
dest_encoder
|
dest_encoder
|
(
|
(
|
.sel(sel),
|
.sel(sel),
|
.dest_coded_out(dest_coded),
|
.dest_coded_out(dest_coded),
|
.vc_num_delayed(vc_num_delayed),
|
.vc_num_delayed(vc_num_delayed),
|
.lk_dest(lk_dest),
|
.lk_dest(lk_dest),
|
.flit_in(flit_in)
|
.flit_in(flit_in)
|
);
|
);
|
|
|
|
|
end else begin : dtrmn1
|
end else begin : dtrmn1
|
assign dest_coded = lk_dest;
|
assign dest_coded = lk_dest;
|
/*
|
/*
|
mesh_torus_dtrmn_dest_encoder #(
|
mesh_torus_dtrmn_dest_encoder #(
|
.P(P),
|
.P(P),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
.Fw(Fw),
|
.Fw(Fw),
|
.DST_P_MSB(DST_P_MSB),
|
.DST_P_MSB(DST_P_MSB),
|
.DST_P_LSB(DST_P_LSB)
|
.DST_P_LSB(DST_P_LSB)
|
)
|
)
|
dest_encoder
|
dest_encoder
|
(
|
(
|
.dest_coded_out(dest_coded),
|
.dest_coded_out(dest_coded),
|
.lk_dest(lk_dest),
|
.lk_dest(lk_dest),
|
.flit_in(flit_in)
|
.flit_in(flit_in)
|
);
|
);
|
*/
|
*/
|
end
|
end
|
|
|
always @(*)begin
|
always @(*)begin
|
flit_out = {flit_in[Fw-1 : Fw-2],ovc_num,flit_in[FPAYw-1 :0]};
|
flit_out = {flit_in[Fw-1 : Fw-2],ovc_num,flit_in[FPAYw-1 :0]};
|
if(hdr_flag) flit_out[DST_P_MSB : DST_P_LSB]= dest_coded;
|
if(hdr_flag) flit_out[DST_P_MSB : DST_P_LSB]= dest_coded;
|
end
|
end
|
|
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
/******************
|
/******************
|
* hdr_flit_weight_update
|
* hdr_flit_weight_update
|
* ****************/
|
* ****************/
|
|
|
module hdr_flit_weight_update
|
module hdr_flit_weight_update #(
|
import pronoc_pkg::*;
|
parameter NOC_ID = 0
|
(
|
) (
|
new_weight,
|
new_weight,
|
flit_in,
|
flit_in,
|
flit_out
|
flit_out
|
);
|
);
|
|
|
function integer log2;
|
`NOC_CONF
|
input integer number; begin
|
|
log2=(number <=1) ? 1: 0;
|
|
while(2**log2
|
|
log2=log2+1;
|
|
end
|
|
end
|
|
endfunction // log2
|
|
|
|
|
|
localparam
|
|
|
|
Cw = (C>1)? log2(C): 1;
|
|
|
|
|
|
input [WEIGHTw-1 : 0] new_weight;
|
input [WEIGHTw-1 : 0] new_weight;
|
input [Fw-1 : 0] flit_in;
|
input [Fw-1 : 0] flit_in;
|
output [Fw-1 : 0] flit_out;
|
output [Fw-1 : 0] flit_out;
|
|
|
|
|
|
|
assign flit_out = {flit_in[Fw-1 : WEIGHT_LSB+WEIGHTw ] ,new_weight, flit_in[WEIGHT_LSB-1 : 0] };
|
assign flit_out = {flit_in[Fw-1 : WEIGHT_LSB+WEIGHTw ] ,new_weight, flit_in[WEIGHT_LSB-1 : 0] };
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|