`include "pronoc_def.v"
|
`include "pronoc_def.v"
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/**********************************************************************
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/**********************************************************************
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** File: inout_ports.v
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** File: inout_ports.v
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**
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**
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** Copyright (C) 2014-2017 Alireza Monemi
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** Copyright (C) 2014-2017 Alireza Monemi
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**
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**
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** This file is part of ProNoC
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** This file is part of ProNoC
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**
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**
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** you can redistribute it and/or modify it under the terms of the GNU
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** you can redistribute it and/or modify it under the terms of the GNU
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** Lesser General Public License as published by the Free Software Foundation,
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** Lesser General Public License as published by the Free Software Foundation,
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** either version 2 of the License, or (at your option) any later version.
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** either version 2 of the License, or (at your option) any later version.
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**
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**
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with ProNoC. If not, see .
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** License along with ProNoC. If not, see .
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**
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**
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**
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**
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** Description:
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** Description:
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** NoC router Input/output module
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** NoC router Input/output module
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**
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**
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**************************************************************/
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**************************************************************/
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module inout_ports
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module inout_ports #(
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import pronoc_pkg::*;
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parameter NOC_ID=0,
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#(
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parameter P = 5
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parameter P = 5
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)
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) (
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(
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current_r_addr,
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current_r_addr,
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neighbors_r_addr,
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neighbors_r_addr,
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clk,
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clk,
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reset,
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reset,
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// to/from neighboring router
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// to/from neighboring router
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flit_in_all,
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flit_in_all,
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flit_in_wr_all,
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flit_in_wr_all,
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credit_out_all,
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credit_out_all,
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credit_in_all,
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credit_in_all,
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congestion_in_all,
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congestion_in_all,
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congestion_out_all,
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congestion_out_all,
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credit_init_val_in,
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credit_init_val_in,
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credit_init_val_out,
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credit_init_val_out,
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// from vsa: local vc/sw allocator
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// from vsa: local vc/sw allocator
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vsa_ovc_allocated_all,
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vsa_ovc_allocated_all,
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granted_ovc_num_all,
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granted_ovc_num_all,
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ivc_num_getting_ovc_grant,
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ivc_num_getting_ovc_grant,
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spec_ovc_num_all,
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spec_ovc_num_all,
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nonspec_first_arbiter_granted_ivc_all,
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nonspec_first_arbiter_granted_ivc_all,
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spec_first_arbiter_granted_ivc_all,
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spec_first_arbiter_granted_ivc_all,
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nonspec_granted_dest_port_all,
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nonspec_granted_dest_port_all,
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spec_granted_dest_port_all,
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spec_granted_dest_port_all,
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granted_dest_port_all,
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granted_dest_port_all,
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any_ivc_sw_request_granted_all,
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any_ivc_sw_request_granted_all,
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any_ovc_granted_in_outport_all,
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any_ovc_granted_in_outport_all,
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granted_dst_is_from_a_single_flit_pck,
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granted_dst_is_from_a_single_flit_pck,
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// to vc/sw allocator
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// to vc/sw allocator
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dest_port_all,
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dest_port_all,
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ovc_is_assigned_all,
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ovc_is_assigned_all,
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ivc_request_all,
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ivc_request_all,
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assigned_ovc_not_full_all,
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assigned_ovc_not_full_all,
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masked_ovc_request_all,
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masked_ovc_request_all,
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vc_weight_is_consumed_all,
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vc_weight_is_consumed_all,
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iport_weight_is_consumed_all,
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iport_weight_is_consumed_all,
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flit_is_tail_all,
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flit_is_tail_all,
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// to crossbar
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// to crossbar
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flit_out_all,
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flit_out_all,
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ssa_flit_wr_all,
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ssa_flit_wr_all,
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iport_weight_all,
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iport_weight_all,
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oports_weight_all,
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oports_weight_all,
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refresh_w_counter,
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refresh_w_counter,
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crossbar_flit_out_wr_all,
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crossbar_flit_out_wr_all,
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// status
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// status
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vsa_credit_decreased_all,
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vsa_credit_decreased_all,
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vsa_ovc_released_all,
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vsa_ovc_released_all,
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ivc_info,
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ivc_info,
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ovc_info,
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ovc_info,
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oport_info,
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oport_info,
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vsa_ctrl_in,
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vsa_ctrl_in,
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smart_ctrl_in
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smart_ctrl_in
|
);
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);
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`NOC_CONF
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localparam
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localparam
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PV = V * P,
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PV = V * P,
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PVV = PV * V,
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PVV = PV * V,
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P_1 = ( SELF_LOOP_EN=="NO")? P-1 : P,
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P_1 = ( SELF_LOOP_EN=="NO")? P-1 : P,
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PP_1 = P_1 * P,
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PP_1 = P_1 * P,
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PVP_1 = PV * P_1,
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PVP_1 = PV * P_1,
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PFw = P * Fw,
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PFw = P * Fw,
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CONG_ALw = CONGw*P, // congestion width per router
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CONG_ALw = CONGw*P, // congestion width per router
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W = WEIGHTw,
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W = WEIGHTw,
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WP = W * P,
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WP = W * P,
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WPP = WP * P,
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WPP = WP * P,
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PVDSTPw= PV * DSTPw,
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PVDSTPw= PV * DSTPw,
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PRAw= P * RAw;
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PRAw= P * RAw;
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input [RAw-1 : 0] current_r_addr;
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input [RAw-1 : 0] current_r_addr;
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input [PRAw-1: 0] neighbors_r_addr;
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input [PRAw-1: 0] neighbors_r_addr;
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input [PFw-1 : 0] flit_in_all;
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input [PFw-1 : 0] flit_in_all;
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input [P-1 : 0] flit_in_wr_all;
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input [P-1 : 0] flit_in_wr_all;
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output[PV-1 : 0] credit_out_all;
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output[PV-1 : 0] credit_out_all;
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input [PV-1 : 0] credit_in_all;
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input [PV-1 : 0] credit_in_all;
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input [PV-1 : 0] vsa_ovc_allocated_all;
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input [PV-1 : 0] vsa_ovc_allocated_all;
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input [PVV-1 : 0] granted_ovc_num_all;
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input [PVV-1 : 0] granted_ovc_num_all;
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input [PV-1 : 0] ivc_num_getting_ovc_grant;
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input [PV-1 : 0] ivc_num_getting_ovc_grant;
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input [PVV-1 : 0] spec_ovc_num_all;
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input [PVV-1 : 0] spec_ovc_num_all;
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input [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
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input [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
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input [PV-1 : 0] spec_first_arbiter_granted_ivc_all;
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input [PV-1 : 0] spec_first_arbiter_granted_ivc_all;
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input [PP_1-1 : 0] nonspec_granted_dest_port_all;
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input [PP_1-1 : 0] nonspec_granted_dest_port_all;
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input [PP_1-1 : 0] spec_granted_dest_port_all;
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input [PP_1-1 : 0] spec_granted_dest_port_all;
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input [PP_1-1 : 0] granted_dest_port_all;
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input [PP_1-1 : 0] granted_dest_port_all;
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input [P-1 : 0] any_ivc_sw_request_granted_all;
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input [P-1 : 0] any_ivc_sw_request_granted_all;
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input [P-1 : 0] any_ovc_granted_in_outport_all;
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input [P-1 : 0] any_ovc_granted_in_outport_all;
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input [CONG_ALw-1 : 0] congestion_in_all;
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input [CONG_ALw-1 : 0] congestion_in_all;
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output[CONG_ALw-1 : 0] congestion_out_all;
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output[CONG_ALw-1 : 0] congestion_out_all;
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output[PV-1 : 0] vc_weight_is_consumed_all;
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output[PV-1 : 0] vc_weight_is_consumed_all;
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output[P-1 : 0] iport_weight_is_consumed_all;
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output[P-1 : 0] iport_weight_is_consumed_all;
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input [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
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input [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
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// to vc/sw allocator
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// to vc/sw allocator
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output [PVP_1-1 : 0] dest_port_all;
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output [PVP_1-1 : 0] dest_port_all;
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output [PV-1 : 0] ovc_is_assigned_all;
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output [PV-1 : 0] ovc_is_assigned_all;
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output [PV-1 : 0] ivc_request_all;
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output [PV-1 : 0] ivc_request_all;
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output [PV-1 : 0] assigned_ovc_not_full_all;
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output [PV-1 : 0] assigned_ovc_not_full_all;
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output [PVV-1: 0] masked_ovc_request_all;
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output [PVV-1: 0] masked_ovc_request_all;
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output [PV-1 : 0] flit_is_tail_all;
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output [PV-1 : 0] flit_is_tail_all;
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// to crossbar
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// to crossbar
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output [PFw-1 : 0] flit_out_all;
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output [PFw-1 : 0] flit_out_all;
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output [P-1 : 0] ssa_flit_wr_all;
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output [P-1 : 0] ssa_flit_wr_all;
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output [WP-1: 0] iport_weight_all;
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output [WP-1: 0] iport_weight_all;
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output [WPP-1:0] oports_weight_all;
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output [WPP-1:0] oports_weight_all;
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input refresh_w_counter;
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input refresh_w_counter;
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input [P-1 : 0] crossbar_flit_out_wr_all;
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input [P-1 : 0] crossbar_flit_out_wr_all;
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input clk,reset;
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input clk,reset;
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output [PV-1 : 0] vsa_ovc_released_all;
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output [PV-1 : 0] vsa_ovc_released_all;
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output [PV-1 : 0] vsa_credit_decreased_all;
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output [PV-1 : 0] vsa_credit_decreased_all;
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output ivc_info_t ivc_info [P-1 : 0][V-1 : 0];
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output ivc_info_t ivc_info [P-1 : 0][V-1 : 0];
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output ovc_info_t ovc_info [P-1 : 0][V-1 : 0];
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output ovc_info_t ovc_info [P-1 : 0][V-1 : 0];
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|
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output oport_info_t oport_info [P-1 : 0];
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output oport_info_t oport_info [P-1 : 0];
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input smart_ctrl_t smart_ctrl_in [P-1 : 0];
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input smart_ctrl_t smart_ctrl_in [P-1 : 0];
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input vsa_ctrl_t vsa_ctrl_in [P-1 : 0];
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input vsa_ctrl_t vsa_ctrl_in [P-1 : 0];
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input [CRDTw-1 : 0 ] credit_init_val_in [P-1 : 0][V-1 : 0];
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input [CRDTw-1 : 0 ] credit_init_val_in [P-1 : 0][V-1 : 0];
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output [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];
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output [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];
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wire [PPSw-1 : 0] port_pre_sel;
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wire [PPSw-1 : 0] port_pre_sel;
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wire [PV-1 : 0] swap_port_presel;
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wire [PV-1 : 0] swap_port_presel;
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wire [PV-1 : 0] reset_ivc_all;
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wire [PV-1 : 0] reset_ivc_all;
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wire [PV-1 : 0] sel;
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wire [PV-1 : 0] sel;
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wire [PV-1 : 0] ovc_avalable_all;
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wire [PV-1 : 0] ovc_avalable_all;
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|
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wire [DSTPw-1 : 0] destport_clear [P-1 : 0][V-1 : 0]; // clear non preferable ports in adaptive routing
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wire [DSTPw-1 : 0] destport_clear [P-1 : 0][V-1 : 0]; // clear non preferable ports in adaptive routing
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wire [PV-1 : 0] ivc_num_getting_sw_grant;
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wire [PV-1 : 0] ivc_num_getting_sw_grant;
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|
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ssa_ctrl_t ssa_ctrl [P-1 : 0];
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ssa_ctrl_t ssa_ctrl [P-1 : 0];
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|
|
|
|
|
input_ports #(
|
input_ports
|
.NOC_ID(NOC_ID),
|
#(
|
|
.P(P)
|
.P(P)
|
)
|
) the_input_port (
|
the_input_port
|
|
(
|
|
.current_r_addr (current_r_addr),
|
.current_r_addr (current_r_addr),
|
.neighbors_r_addr(neighbors_r_addr),
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.neighbors_r_addr(neighbors_r_addr),
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.ivc_num_getting_sw_grant (ivc_num_getting_sw_grant ),
|
.ivc_num_getting_sw_grant (ivc_num_getting_sw_grant ),
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.any_ivc_sw_request_granted_all (any_ivc_sw_request_granted_all),
|
.any_ivc_sw_request_granted_all (any_ivc_sw_request_granted_all),
|
.flit_in_all (flit_in_all),
|
.flit_in_all (flit_in_all),
|
.flit_in_wr_all (flit_in_wr_all),
|
.flit_in_wr_all (flit_in_wr_all),
|
.reset_ivc_all (reset_ivc_all),
|
.reset_ivc_all (reset_ivc_all),
|
.flit_is_tail_all (flit_is_tail_all),
|
.flit_is_tail_all (flit_is_tail_all),
|
.ivc_request_all (ivc_request_all),
|
.ivc_request_all (ivc_request_all),
|
.dest_port_all(dest_port_all),
|
.dest_port_all(dest_port_all),
|
.flit_out_all (flit_out_all),
|
.flit_out_all (flit_out_all),
|
.assigned_ovc_not_full_all(assigned_ovc_not_full_all),
|
.assigned_ovc_not_full_all(assigned_ovc_not_full_all),
|
.ovc_is_assigned_all(ovc_is_assigned_all),
|
.ovc_is_assigned_all(ovc_is_assigned_all),
|
.sel (sel),
|
.sel (sel),
|
.port_pre_sel(port_pre_sel),
|
.port_pre_sel(port_pre_sel),
|
.swap_port_presel(swap_port_presel),
|
.swap_port_presel(swap_port_presel),
|
.credit_out_all(credit_out_all),
|
.credit_out_all(credit_out_all),
|
// .lk_destination_encoded_all (lk_destination_encoded_all),
|
// .lk_destination_encoded_all (lk_destination_encoded_all),
|
.nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all),
|
.nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all),
|
.destport_clear (destport_clear),
|
.destport_clear (destport_clear),
|
.vc_weight_is_consumed_all (vc_weight_is_consumed_all),
|
.vc_weight_is_consumed_all (vc_weight_is_consumed_all),
|
.iport_weight_is_consumed_all (iport_weight_is_consumed_all),
|
.iport_weight_is_consumed_all (iport_weight_is_consumed_all),
|
.iport_weight_all(iport_weight_all),
|
.iport_weight_all(iport_weight_all),
|
.oports_weight_all(oports_weight_all),
|
.oports_weight_all(oports_weight_all),
|
.granted_dest_port_all(granted_dest_port_all),
|
.granted_dest_port_all(granted_dest_port_all),
|
.refresh_w_counter(refresh_w_counter),
|
.refresh_w_counter(refresh_w_counter),
|
.ivc_info(ivc_info),
|
.ivc_info(ivc_info),
|
.smart_ctrl_in(smart_ctrl_in),
|
.smart_ctrl_in(smart_ctrl_in),
|
.vsa_ctrl_in(vsa_ctrl_in),
|
.vsa_ctrl_in(vsa_ctrl_in),
|
.ssa_ctrl_in(ssa_ctrl),
|
.ssa_ctrl_in(ssa_ctrl),
|
.credit_init_val_out(credit_init_val_out),
|
.credit_init_val_out(credit_init_val_out),
|
.reset (reset),
|
.reset (reset),
|
.clk (clk)
|
.clk (clk)
|
);
|
);
|
|
|
|
|
output_ports #(
|
output_ports #(
|
|
.NOC_ID(NOC_ID),
|
.P (P)
|
.P (P)
|
)
|
) output_ports (
|
output_ports
|
|
(
|
|
|
|
.vsa_ovc_allocated_all (vsa_ovc_allocated_all),
|
.vsa_ovc_allocated_all (vsa_ovc_allocated_all),
|
.flit_is_tail_all (flit_is_tail_all),
|
.flit_is_tail_all (flit_is_tail_all),
|
.dest_port_all (dest_port_all),
|
.dest_port_all (dest_port_all),
|
.nonspec_granted_dest_port_all (nonspec_granted_dest_port_all),
|
.nonspec_granted_dest_port_all (nonspec_granted_dest_port_all),
|
.credit_in_all (credit_in_all),
|
.credit_in_all (credit_in_all),
|
.nonspec_first_arbiter_granted_ivc_all (nonspec_first_arbiter_granted_ivc_all),
|
.nonspec_first_arbiter_granted_ivc_all (nonspec_first_arbiter_granted_ivc_all),
|
.ivc_num_getting_sw_grant (ivc_num_getting_sw_grant ),
|
.ivc_num_getting_sw_grant (ivc_num_getting_sw_grant ),
|
.ovc_avalable_all (ovc_avalable_all),
|
.ovc_avalable_all (ovc_avalable_all),
|
.assigned_ovc_not_full_all (assigned_ovc_not_full_all),
|
.assigned_ovc_not_full_all (assigned_ovc_not_full_all),
|
.port_pre_sel (port_pre_sel),//only valid for adaptive routing
|
.port_pre_sel (port_pre_sel),//only valid for adaptive routing
|
.congestion_in_all (congestion_in_all),//only valid for adaptive routing
|
.congestion_in_all (congestion_in_all),//only valid for adaptive routing
|
.granted_ovc_num_all (granted_ovc_num_all),
|
.granted_ovc_num_all (granted_ovc_num_all),
|
|
|
.granted_dst_is_from_a_single_flit_pck (granted_dst_is_from_a_single_flit_pck),
|
.granted_dst_is_from_a_single_flit_pck (granted_dst_is_from_a_single_flit_pck),
|
.reset (reset),
|
.reset (reset),
|
.clk (clk),
|
.clk (clk),
|
.crossbar_flit_out_wr_all (crossbar_flit_out_wr_all),
|
.crossbar_flit_out_wr_all (crossbar_flit_out_wr_all),
|
.any_ovc_granted_in_outport_all ( any_ovc_granted_in_outport_all),
|
.any_ovc_granted_in_outport_all ( any_ovc_granted_in_outport_all),
|
.vsa_ovc_released_all (vsa_ovc_released_all),
|
.vsa_ovc_released_all (vsa_ovc_released_all),
|
.vsa_credit_decreased_all(vsa_credit_decreased_all),
|
.vsa_credit_decreased_all(vsa_credit_decreased_all),
|
.oport_info (oport_info),
|
.oport_info (oport_info),
|
.ivc_info(ivc_info),
|
.ivc_info(ivc_info),
|
.ovc_info (ovc_info),
|
.ovc_info (ovc_info),
|
.smart_ctrl_in(smart_ctrl_in),
|
.smart_ctrl_in(smart_ctrl_in),
|
.vsa_ctrl_in(vsa_ctrl_in),
|
.vsa_ctrl_in(vsa_ctrl_in),
|
.ssa_ctrl_in(ssa_ctrl),
|
.ssa_ctrl_in(ssa_ctrl),
|
.credit_init_val_in(credit_init_val_in)
|
.credit_init_val_in(credit_init_val_in)
|
);
|
);
|
|
|
|
|
vc_alloc_request_gen #(
|
vc_alloc_request_gen #(
|
|
.NOC_ID(NOC_ID),
|
.P(P)
|
.P(P)
|
)
|
) vc_alloc_req_gen (
|
vc_alloc_req_gen
|
|
(
|
|
.ivc_info(ivc_info),
|
.ivc_info(ivc_info),
|
.ovc_avalable_all(ovc_avalable_all),
|
.ovc_avalable_all(ovc_avalable_all),
|
.dest_port_decoded_all(dest_port_all),
|
.dest_port_decoded_all(dest_port_all),
|
.masked_ovc_request_all(masked_ovc_request_all),
|
.masked_ovc_request_all(masked_ovc_request_all),
|
|
|
.port_pre_sel(port_pre_sel),
|
.port_pre_sel(port_pre_sel),
|
.swap_port_presel(swap_port_presel),
|
.swap_port_presel(swap_port_presel),
|
.sel(sel),
|
.sel(sel),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.destport_clear(destport_clear),
|
.destport_clear(destport_clear),
|
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
|
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
|
//.ssa_ivc_num_getting_ovc_grant_all(nla_ivc_num_getting_ovc_grant_all),
|
//.ssa_ivc_num_getting_ovc_grant_all(nla_ivc_num_getting_ovc_grant_all),
|
.smart_ctrl_in (smart_ctrl_in),
|
.smart_ctrl_in (smart_ctrl_in),
|
.ssa_ctrl_in (ssa_ctrl)
|
.ssa_ctrl_in (ssa_ctrl)
|
);
|
);
|
|
|
|
|
congestion_out_gen #(
|
congestion_out_gen #(
|
.P(P),
|
.P(P),
|
.V(V),
|
.V(V),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.CONGESTION_INDEX(CONGESTION_INDEX),
|
.CONGESTION_INDEX(CONGESTION_INDEX),
|
.CONGw(CONGw)
|
.CONGw(CONGw)
|
)
|
)
|
congestion_out
|
congestion_out
|
(
|
(
|
.ovc_avalable_all(ovc_avalable_all),
|
.ovc_avalable_all(ovc_avalable_all),
|
.ivc_request_all(ivc_request_all),
|
.ivc_request_all(ivc_request_all),
|
.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant ),
|
.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant ),
|
.congestion_out_all(congestion_out_all),
|
.congestion_out_all(congestion_out_all),
|
.clk(clk),
|
.clk(clk),
|
.reset(reset)
|
.reset(reset)
|
);
|
);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
genvar i;
|
genvar i;
|
generate
|
generate
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if( SSA_EN =="YES" ) begin : ssa
|
if( SSA_EN =="YES" ) begin : ssa
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
ss_allocator #(
|
ss_allocator #(
|
|
.NOC_ID(NOC_ID),
|
.P(P)
|
.P(P)
|
)
|
)
|
the_ssa
|
the_ssa
|
(
|
(
|
.ivc_info(ivc_info),
|
.ivc_info(ivc_info),
|
.ovc_info(ovc_info),
|
.ovc_info(ovc_info),
|
.flit_in_wr_all(flit_in_wr_all),
|
.flit_in_wr_all(flit_in_wr_all),
|
.flit_in_all(flit_in_all),
|
.flit_in_all(flit_in_all),
|
.any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
|
.any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
|
.any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
|
.any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
|
.ovc_avalable_all(ovc_avalable_all),
|
.ovc_avalable_all(ovc_avalable_all),
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.ssa_ctrl_o(ssa_ctrl)
|
.ssa_ctrl_o(ssa_ctrl)
|
);
|
);
|
|
|
end else begin :non_ssa
|
end else begin :non_ssa
|
for(i=0;i< P;i=i+1) begin :p_
|
for(i=0;i< P;i=i+1) begin :p_
|
assign ssa_ctrl[i] = {SSA_CTRL_w{1'b0}};
|
assign ssa_ctrl[i] = {SSA_CTRL_w{1'b0}};
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
for(i=0;i< P;i=i+1) begin :p_
|
for(i=0;i< P;i=i+1) begin :p_
|
assign ssa_flit_wr_all [i] = ssa_ctrl[i].ssa_flit_wr;
|
assign ssa_flit_wr_all [i] = ssa_ctrl[i].ssa_flit_wr;
|
end//for
|
end//for
|
|
|
//synthesis translate_off
|
//synthesis translate_off
|
//synopsys translate_off
|
//synopsys translate_off
|
if(DEBUG_EN && MIN_PCK_SIZE >1 )begin :dbg
|
if(DEBUG_EN && MIN_PCK_SIZE >1 )begin :dbg
|
wire [PV-1 : 0] non_vsa_ivc_num_getting_ovc_grant_all;
|
wire [PV-1 : 0] non_vsa_ivc_num_getting_ovc_grant_all;
|
integer kk;
|
integer kk;
|
for(i=0;i< P;i=i+1) begin :p_
|
for(i=0;i< P;i=i+1) begin :p_
|
assign non_vsa_ivc_num_getting_ovc_grant_all [(i+1)*V-1 : i*V] = ssa_ctrl[i].ivc_num_getting_ovc_grant | smart_ctrl_in[i].ivc_num_getting_ovc_grant;
|
assign non_vsa_ivc_num_getting_ovc_grant_all [(i+1)*V-1 : i*V] = ssa_ctrl[i].ivc_num_getting_ovc_grant | smart_ctrl_in[i].ivc_num_getting_ovc_grant;
|
end//for
|
end//for
|
always @(posedge clk ) begin
|
always @(posedge clk ) begin
|
for(kk=0; kk< PV; kk=kk+1'b1 ) if(reset_ivc_all[kk] & (ivc_num_getting_ovc_grant[kk] | non_vsa_ivc_num_getting_ovc_grant_all[kk])) begin
|
for(kk=0; kk< PV; kk=kk+1'b1 ) if(reset_ivc_all[kk] & (ivc_num_getting_ovc_grant[kk] | non_vsa_ivc_num_getting_ovc_grant_all[kk])) begin
|
$display("%t: ERROR: the ovc %d released and allocat signal is asserted in the same clock cycle : %m",$time,kk);
|
$display("%t: ERROR: the ovc %d released and allocat signal is asserted in the same clock cycle : %m",$time,kk);
|
$finish;
|
$finish;
|
end
|
end
|
end
|
end
|
end
|
end
|
//synopsys translate_on
|
//synopsys translate_on
|
//synthesis translate_on
|
//synthesis translate_on
|
endgenerate
|
endgenerate
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|
|
|
/******************
|
/******************
|
|
|
output_vc_status
|
output_vc_status
|
|
|
******************/
|
******************/
|
|
|
module output_vc_status #(
|
module output_vc_status #(
|
parameter V = 4,
|
parameter V = 4,
|
parameter B = 16,
|
parameter B = 16,
|
parameter CAND_VC_SEL_MODE = 0, // 0: use arbiteration between not full vcs, 1: select the vc with most availble free space
|
parameter CAND_VC_SEL_MODE = 0, // 0: use arbiteration between not full vcs, 1: select the vc with most availble free space
|
parameter CRDTw = 4
|
parameter CRDTw = 4
|
)(
|
)(
|
credit_init_val_in,
|
credit_init_val_in,
|
wr_in,
|
wr_in,
|
credit_in,
|
credit_in,
|
nearly_full_vc,
|
nearly_full_vc,
|
full_vc,
|
full_vc,
|
empty_vc,
|
empty_vc,
|
cand_vc,
|
cand_vc,
|
cand_wr_vc_en,
|
cand_wr_vc_en,
|
clk,
|
clk,
|
reset
|
reset
|
);
|
);
|
|
|
|
|
input [V-1 : 0] [CRDTw-1 : 0 ] credit_init_val_in ;
|
input [V-1 : 0] [CRDTw-1 : 0 ] credit_init_val_in ;
|
input [V-1 :0] wr_in;
|
input [V-1 :0] wr_in;
|
input [V-1 :0] credit_in;
|
input [V-1 :0] credit_in;
|
output [V-1 :0] nearly_full_vc;
|
output [V-1 :0] nearly_full_vc;
|
output [V-1 : 0] full_vc;
|
output [V-1 : 0] full_vc;
|
output [V-1 :0] empty_vc;
|
output [V-1 :0] empty_vc;
|
output [V-1 :0] cand_vc;
|
output [V-1 :0] cand_vc;
|
input cand_wr_vc_en;
|
input cand_wr_vc_en;
|
input clk;
|
input clk;
|
input reset;
|
input reset;
|
|
|
|
|
function integer log2;
|
function integer log2;
|
input integer number; begin
|
input integer number; begin
|
log2=(number <=1) ? 1: 0;
|
log2=(number <=1) ? 1: 0;
|
while(2**log2
|
while(2**log2
|
log2=log2+1;
|
log2=log2+1;
|
end
|
end
|
end
|
end
|
endfunction // log2
|
endfunction // log2
|
|
|
|
|
localparam DEPTH_WIDTH = log2(B+1);
|
localparam DEPTH_WIDTH = log2(B+1);
|
|
|
|
|
logic [DEPTH_WIDTH-1 : 0] credit [V-1 : 0];
|
logic [DEPTH_WIDTH-1 : 0] credit [V-1 : 0];
|
logic [DEPTH_WIDTH-1 : 0] credit_next [V-1 : 0];
|
logic [DEPTH_WIDTH-1 : 0] credit_next [V-1 : 0];
|
wire [V-1 : 0] cand_vc_next;
|
wire [V-1 : 0] cand_vc_next;
|
|
|
wire [V-1 :0] request;
|
wire [V-1 :0] request;
|
|
|
genvar i;
|
genvar i;
|
generate
|
generate
|
for(i=0;i
|
for(i=0;i
|
|
|
|
|
|
|
|
|
pronoc_register_reset_init #(
|
pronoc_register_reset_init #(
|
.W(DEPTH_WIDTH)
|
.W(DEPTH_WIDTH)
|
)reg1(
|
)reg1(
|
.in(credit_next[i]),
|
.in(credit_next[i]),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.out(credit[i]),
|
.out(credit[i]),
|
.reset_to(credit_init_val_in[i][DEPTH_WIDTH-1:0])
|
.reset_to(credit_init_val_in[i][DEPTH_WIDTH-1:0])
|
);
|
);
|
|
|
|
|
|
|
always @ ( * )begin
|
always @ ( * )begin
|
credit_next[i] = credit [i];
|
credit_next[i] = credit [i];
|
if( wr_in[i] && ~credit_in[i]) credit_next[i] = credit[i]-1'b1;
|
if( wr_in[i] && ~credit_in[i]) credit_next[i] = credit[i]-1'b1;
|
if( ~wr_in[i] && credit_in[i]) credit_next[i] = credit[i]+1'b1;
|
if( ~wr_in[i] && credit_in[i]) credit_next[i] = credit[i]+1'b1;
|
end//always
|
end//always
|
|
|
assign full_vc[i] = (credit[i] == {DEPTH_WIDTH{1'b0}});
|
assign full_vc[i] = (credit[i] == {DEPTH_WIDTH{1'b0}});
|
assign nearly_full_vc[i]= (credit[i] == 1) | full_vc[i];
|
assign nearly_full_vc[i]= (credit[i] == 1) | full_vc[i];
|
assign empty_vc[i] = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
|
assign empty_vc[i] = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
|
|
|
assign request[i] = ~ nearly_full_vc[i] & cand_wr_vc_en;
|
assign request[i] = ~ nearly_full_vc[i] & cand_wr_vc_en;
|
end//for
|
end//for
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
arbiter #(
|
arbiter #(
|
.ARBITER_WIDTH (V)
|
.ARBITER_WIDTH (V)
|
)
|
)
|
the_nic_arbiter
|
the_nic_arbiter
|
(
|
(
|
.clk (clk),
|
.clk (clk),
|
.reset (reset),
|
.reset (reset),
|
.request (request),
|
.request (request),
|
.grant (cand_vc_next),
|
.grant (cand_vc_next),
|
.any_grant ()
|
.any_grant ()
|
);
|
);
|
|
|
logic [V-1 : 0] cand_vc_ld_next;
|
logic [V-1 : 0] cand_vc_ld_next;
|
pronoc_register #(.W(V)) reg2 (.in(cand_vc_ld_next ), .out(cand_vc), .reset(reset), .clk(clk));
|
pronoc_register #(.W(V)) reg2 (.in(cand_vc_ld_next ), .out(cand_vc), .reset(reset), .clk(clk));
|
|
|
always @ ( *) begin
|
always @ ( *) begin
|
cand_vc_ld_next = cand_vc;
|
cand_vc_ld_next = cand_vc;
|
if(cand_wr_vc_en) cand_vc_ld_next = cand_vc_next;
|
if(cand_wr_vc_en) cand_vc_ld_next = cand_vc_next;
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
|
|
/*************************
|
/*************************
|
vc_alloc_request_gen
|
vc_alloc_request_gen
|
|
|
************************/
|
************************/
|
|
|
|
|
module vc_alloc_request_gen
|
module vc_alloc_request_gen #(
|
import pronoc_pkg::*;
|
parameter NOC_ID=0,
|
#(
|
|
|
|
parameter P = 5
|
parameter P = 5
|
|
|
)(
|
)(
|
ivc_info,
|
ivc_info,
|
ovc_avalable_all,
|
ovc_avalable_all,
|
dest_port_decoded_all,
|
dest_port_decoded_all,
|
masked_ovc_request_all,
|
masked_ovc_request_all,
|
port_pre_sel,
|
port_pre_sel,
|
swap_port_presel,
|
swap_port_presel,
|
sel,
|
sel,
|
reset,
|
reset,
|
clk,
|
clk,
|
destport_clear,
|
destport_clear,
|
ivc_num_getting_ovc_grant,
|
ivc_num_getting_ovc_grant,
|
smart_ctrl_in,
|
smart_ctrl_in,
|
ssa_ctrl_in
|
ssa_ctrl_in
|
);
|
);
|
|
|
|
`NOC_CONF
|
|
|
localparam P_1 = (SELF_LOOP_EN == "NO")? P-1 : P,
|
localparam P_1 = (SELF_LOOP_EN == "NO")? P-1 : P,
|
PV = V * P,
|
PV = V * P,
|
PVV = PV * V,
|
PVV = PV * V,
|
PVP_1 = PV * P_1,
|
PVP_1 = PV * P_1,
|
PVDSTPw= PV * DSTPw;
|
PVDSTPw= PV * DSTPw;
|
|
|
|
|
|
|
input [PV-1 : 0] ovc_avalable_all;
|
input [PV-1 : 0] ovc_avalable_all;
|
input [PVP_1-1 : 0] dest_port_decoded_all;
|
input [PVP_1-1 : 0] dest_port_decoded_all;
|
output [PVV-1 : 0] masked_ovc_request_all;
|
output [PVV-1 : 0] masked_ovc_request_all;
|
|
|
input [PPSw-1 : 0] port_pre_sel;
|
input [PPSw-1 : 0] port_pre_sel;
|
output [PV-1 : 0] sel;
|
output [PV-1 : 0] sel;
|
output [PV-1 : 0] swap_port_presel;
|
output [PV-1 : 0] swap_port_presel;
|
input reset;
|
input reset;
|
input clk;
|
input clk;
|
output [DSTPw-1 : 0] destport_clear [P-1 : 0][V-1 : 0];
|
output [DSTPw-1 : 0] destport_clear [P-1 : 0][V-1 : 0];
|
|
|
input [PV-1 : 0] ivc_num_getting_ovc_grant;
|
input [PV-1 : 0] ivc_num_getting_ovc_grant;
|
input ssa_ctrl_t ssa_ctrl_in [P-1: 0];
|
input ssa_ctrl_t ssa_ctrl_in [P-1: 0];
|
input smart_ctrl_t smart_ctrl_in [P-1: 0];
|
input smart_ctrl_t smart_ctrl_in [P-1: 0];
|
input ivc_info_t ivc_info [P-1 : 0][V-1 : 0];
|
input ivc_info_t ivc_info [P-1 : 0][V-1 : 0];
|
|
|
wire [PV-1 : 0] ivc_request_all;
|
wire [PV-1 : 0] ivc_request_all;
|
wire [PVDSTPw-1 : 0] dest_port_encoded_all;
|
wire [PVDSTPw-1 : 0] dest_port_encoded_all;
|
wire [PVV-1 : 0] candidate_ovc_all;
|
wire [PVV-1 : 0] candidate_ovc_all;
|
wire [PV-1 : 0] ovc_is_assigned_all;
|
wire [PV-1 : 0] ovc_is_assigned_all;
|
|
|
wire [PV-1 : 0] ovc_avalable_all_masked;
|
wire [PV-1 : 0] ovc_avalable_all_masked;
|
wire [PV-1 : 0] non_vsa_ivc_num_getting_ovc_grant_all;
|
wire [PV-1 : 0] non_vsa_ivc_num_getting_ovc_grant_all;
|
wire [PVDSTPw-1 : 0] destport_clear_all;
|
wire [PVDSTPw-1 : 0] destport_clear_all;
|
|
|
genvar i,j;
|
genvar i,j;
|
generate
|
generate
|
|
|
for(i=0;i< P;i=i+1) begin :p_
|
for(i=0;i< P;i=i+1) begin :p_
|
assign ovc_avalable_all_masked [(i+1)*V-1 : i*V] = (SMART_EN)? ovc_avalable_all [(i+1)*V-1 : i*V] & ~smart_ctrl_in[i].mask_available_ovc : ovc_avalable_all [(i+1)*V-1 : i*V];
|
assign ovc_avalable_all_masked [(i+1)*V-1 : i*V] = (SMART_EN)? ovc_avalable_all [(i+1)*V-1 : i*V] & ~smart_ctrl_in[i].mask_available_ovc : ovc_avalable_all [(i+1)*V-1 : i*V];
|
assign non_vsa_ivc_num_getting_ovc_grant_all [(i+1)*V-1 : i*V] = ssa_ctrl_in[i].ivc_num_getting_ovc_grant | smart_ctrl_in[i].ivc_num_getting_ovc_grant;
|
assign non_vsa_ivc_num_getting_ovc_grant_all [(i+1)*V-1 : i*V] = ssa_ctrl_in[i].ivc_num_getting_ovc_grant | smart_ctrl_in[i].ivc_num_getting_ovc_grant;
|
for(j=0;j< V;j=j+1) begin :V_
|
for(j=0;j< V;j=j+1) begin :V_
|
assign ivc_request_all[i*V+j] = ivc_info[i][j].ivc_req;
|
assign ivc_request_all[i*V+j] = ivc_info[i][j].ivc_req;
|
assign ovc_is_assigned_all[i*V+j] = ivc_info[i][j].ovc_is_assigned;
|
assign ovc_is_assigned_all[i*V+j] = ivc_info[i][j].ovc_is_assigned;
|
assign dest_port_encoded_all [(i*V+j+1)*DSTPw-1 : (i*V+j)*DSTPw]=ivc_info[i][j].dest_port_encoded;
|
assign dest_port_encoded_all [(i*V+j+1)*DSTPw-1 : (i*V+j)*DSTPw]=ivc_info[i][j].dest_port_encoded;
|
assign candidate_ovc_all[(i*V+j+1)*V-1 : (i*V+j)*V]= ivc_info[i][j].candidate_ovc;
|
assign candidate_ovc_all[(i*V+j+1)*V-1 : (i*V+j)*V]= ivc_info[i][j].candidate_ovc;
|
assign destport_clear [i][j]=destport_clear_all [(i*V+j+1)*DSTPw-1 : (i*V+j)*DSTPw];
|
assign destport_clear [i][j]=destport_clear_all [(i*V+j+1)*DSTPw-1 : (i*V+j)*DSTPw];
|
end
|
end
|
end//for
|
end//for
|
|
|
|
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if(ROUTE_TYPE == "DETERMINISTIC") begin : dtrmn
|
if(ROUTE_TYPE == "DETERMINISTIC") begin : dtrmn
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
vc_alloc_request_gen_determinstic #(
|
vc_alloc_request_gen_determinstic #(
|
.P(P),
|
.P(P),
|
.V(V),
|
.V(V),
|
.SELF_LOOP_EN(SELF_LOOP_EN),
|
.SELF_LOOP_EN(SELF_LOOP_EN),
|
.CAST_TYPE(CAST_TYPE)
|
.CAST_TYPE(CAST_TYPE)
|
)
|
)
|
vc_request_gen
|
vc_request_gen
|
(
|
(
|
.ovc_avalable_all(ovc_avalable_all_masked),
|
.ovc_avalable_all(ovc_avalable_all_masked),
|
.ivc_request_all(ivc_request_all),
|
.ivc_request_all(ivc_request_all),
|
.ovc_is_assigned_all(ovc_is_assigned_all),
|
.ovc_is_assigned_all(ovc_is_assigned_all),
|
.dest_port_in_all(dest_port_decoded_all),
|
.dest_port_in_all(dest_port_decoded_all),
|
.masked_ovc_request_all(masked_ovc_request_all),
|
.masked_ovc_request_all(masked_ovc_request_all),
|
.candidate_ovc_all(candidate_ovc_all)
|
.candidate_ovc_all(candidate_ovc_all)
|
);
|
);
|
|
|
assign swap_port_presel = {PV{1'bx}};
|
assign swap_port_presel = {PV{1'bx}};
|
assign destport_clear_all={PVDSTPw{1'b0}};
|
assign destport_clear_all={PVDSTPw{1'b0}};
|
assign sel = {PV{1'bx}};
|
assign sel = {PV{1'bx}};
|
|
|
end else begin: adptv
|
end else begin: adptv
|
|
|
if(P==5 && SELF_LOOP_EN == "NO" )begin:sl_mesh // combine portsel and available VC mux as proposed in ProNoC paper
|
if(P==5 && SELF_LOOP_EN == "NO" )begin:sl_mesh // combine portsel and available VC mux as proposed in ProNoC paper
|
|
|
mesh_torus_vc_alloc_request_gen_adaptive #(
|
mesh_torus_vc_alloc_request_gen_adaptive #(
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.V(V),
|
.V(V),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
.SSA_EN(SSA_EN),
|
.SSA_EN(SSA_EN),
|
.ESCAP_VC_MASK(ESCAP_VC_MASK),
|
.ESCAP_VC_MASK(ESCAP_VC_MASK),
|
.PPSw(PPSw)
|
.PPSw(PPSw)
|
)
|
)
|
vc_alloc_request_gen
|
vc_alloc_request_gen
|
(
|
(
|
.ovc_avalable_all(ovc_avalable_all_masked),
|
.ovc_avalable_all(ovc_avalable_all_masked),
|
.dest_port_coded_all(dest_port_encoded_all),
|
.dest_port_coded_all(dest_port_encoded_all),
|
.ivc_request_all(ivc_request_all),
|
.ivc_request_all(ivc_request_all),
|
.ovc_is_assigned_all(ovc_is_assigned_all),
|
.ovc_is_assigned_all(ovc_is_assigned_all),
|
.masked_ovc_request_all(masked_ovc_request_all),
|
.masked_ovc_request_all(masked_ovc_request_all),
|
.candidate_ovc_all(candidate_ovc_all),
|
.candidate_ovc_all(candidate_ovc_all),
|
.port_pre_sel(port_pre_sel),
|
.port_pre_sel(port_pre_sel),
|
.swap_port_presel(swap_port_presel),
|
.swap_port_presel(swap_port_presel),
|
.sel(sel),
|
.sel(sel),
|
.destport_clear_all(destport_clear_all),
|
.destport_clear_all(destport_clear_all),
|
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
|
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
|
.ssa_ivc_num_getting_ovc_grant_all(non_vsa_ivc_num_getting_ovc_grant_all),
|
.ssa_ivc_num_getting_ovc_grant_all(non_vsa_ivc_num_getting_ovc_grant_all),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
|
|
end else begin :ml_mesh // there are several local ports connected to one router or self loop is enabled
|
end else begin :ml_mesh // there are several local ports connected to one router or self loop is enabled
|
//select the port first then select the available vc
|
//select the port first then select the available vc
|
|
|
|
|
|
|
mesh_torus_dynamic_portsel_control #(
|
mesh_torus_dynamic_portsel_control #(
|
.P(P),
|
.P(P),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.V(V),
|
.V(V),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
.SSA_EN(SSA_EN),
|
.SSA_EN(SSA_EN),
|
.PPSw(PPSw),
|
.PPSw(PPSw),
|
.ESCAP_VC_MASK(ESCAP_VC_MASK)
|
.ESCAP_VC_MASK(ESCAP_VC_MASK)
|
)
|
)
|
dynamic_portsel_control
|
dynamic_portsel_control
|
(
|
(
|
.dest_port_coded_all(dest_port_encoded_all),
|
.dest_port_coded_all(dest_port_encoded_all),
|
.ivc_request_all(ivc_request_all),
|
.ivc_request_all(ivc_request_all),
|
.ovc_is_assigned_all(ovc_is_assigned_all),
|
.ovc_is_assigned_all(ovc_is_assigned_all),
|
.port_pre_sel(port_pre_sel),
|
.port_pre_sel(port_pre_sel),
|
.swap_port_presel(swap_port_presel),
|
.swap_port_presel(swap_port_presel),
|
.masked_ovc_request_all(masked_ovc_request_all),
|
.masked_ovc_request_all(masked_ovc_request_all),
|
.sel(sel),
|
.sel(sel),
|
.destport_clear_all(destport_clear_all),
|
.destport_clear_all(destport_clear_all),
|
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
|
.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
|
.ssa_ivc_num_getting_ovc_grant_all(non_vsa_ivc_num_getting_ovc_grant_all),
|
.ssa_ivc_num_getting_ovc_grant_all(non_vsa_ivc_num_getting_ovc_grant_all),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
|
|
vc_alloc_request_gen_determinstic #(
|
vc_alloc_request_gen_determinstic #(
|
.P(P),
|
.P(P),
|
.V(V),
|
.V(V),
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
.SELF_LOOP_EN(SELF_LOOP_EN)
|
)
|
)
|
vc_request_gen
|
vc_request_gen
|
(
|
(
|
.ovc_avalable_all(ovc_avalable_all_masked),
|
.ovc_avalable_all(ovc_avalable_all_masked),
|
.ivc_request_all(ivc_request_all),
|
.ivc_request_all(ivc_request_all),
|
.ovc_is_assigned_all(ovc_is_assigned_all),
|
.ovc_is_assigned_all(ovc_is_assigned_all),
|
.dest_port_in_all(dest_port_decoded_all),
|
.dest_port_in_all(dest_port_decoded_all),
|
.masked_ovc_request_all(masked_ovc_request_all),
|
.masked_ovc_request_all(masked_ovc_request_all),
|
.candidate_ovc_all(candidate_ovc_all)
|
.candidate_ovc_all(candidate_ovc_all)
|
);
|
);
|
|
|
|
|
end
|
end
|
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
endmodule
|
endmodule
|
|
|
|
|
module vc_alloc_request_gen_determinstic #(
|
module vc_alloc_request_gen_determinstic #(
|
parameter P = 5,
|
parameter P = 5,
|
parameter V = 4,
|
parameter V = 4,
|
parameter SELF_LOOP_EN="NO",
|
parameter SELF_LOOP_EN="NO",
|
parameter CAST_TYPE = "UNICAST"
|
parameter CAST_TYPE = "UNICAST"
|
|
|
)(
|
)(
|
ovc_avalable_all,
|
ovc_avalable_all,
|
candidate_ovc_all,
|
candidate_ovc_all,
|
ivc_request_all,
|
ivc_request_all,
|
ovc_is_assigned_all,
|
ovc_is_assigned_all,
|
dest_port_in_all,
|
dest_port_in_all,
|
masked_ovc_request_all
|
masked_ovc_request_all
|
);
|
);
|
|
|
localparam P_1 = (SELF_LOOP_EN == "NO")? P-1 : P,
|
localparam P_1 = (SELF_LOOP_EN == "NO")? P-1 : P,
|
PV = V * P,
|
PV = V * P,
|
PVV = PV * V,
|
PVV = PV * V,
|
PVP_1 = PV * P_1,
|
PVP_1 = PV * P_1,
|
VP_1 = V * P_1;
|
VP_1 = V * P_1;
|
|
|
input [PV-1 : 0] ovc_avalable_all;
|
input [PV-1 : 0] ovc_avalable_all;
|
input [PV-1 : 0] ivc_request_all;
|
input [PV-1 : 0] ivc_request_all;
|
input [PV-1 : 0] ovc_is_assigned_all;
|
input [PV-1 : 0] ovc_is_assigned_all;
|
input [PVP_1-1 : 0] dest_port_in_all;
|
input [PVP_1-1 : 0] dest_port_in_all;
|
output [PVV-1 : 0] masked_ovc_request_all;
|
output [PVV-1 : 0] masked_ovc_request_all;
|
input [PVV-1 : 0] candidate_ovc_all;
|
input [PVV-1 : 0] candidate_ovc_all;
|
|
|
wire [PV-1 : 0] non_assigned_ovc_request_all;
|
wire [PV-1 : 0] non_assigned_ovc_request_all;
|
wire [VP_1-1 : 0] ovc_avalable_perport [P-1 : 0];
|
wire [VP_1-1 : 0] ovc_avalable_perport [P-1 : 0];
|
wire [VP_1-1 : 0] ovc_avalable_ivc [PV-1 : 0];
|
wire [VP_1-1 : 0] ovc_avalable_ivc [PV-1 : 0];
|
wire [P_1-1 : 0] dest_port_ivc [PV-1 : 0];
|
wire [P_1-1 : 0] dest_port_ivc [PV-1 : 0];
|
wire [V-1 : 0] ovc_avb_muxed [PV-1 : 0];
|
wire [V-1 : 0] ovc_avb_muxed [PV-1 : 0];
|
wire [V-1 : 0] ovc_request_ivc [PV-1 : 0];
|
wire [V-1 : 0] ovc_request_ivc [PV-1 : 0];
|
|
|
assign non_assigned_ovc_request_all = ivc_request_all & ~ovc_is_assigned_all;
|
assign non_assigned_ovc_request_all = ivc_request_all & ~ovc_is_assigned_all;
|
|
|
|
|
genvar i;
|
genvar i;
|
|
|
generate
|
generate
|
if(SELF_LOOP_EN == "NO" ) begin :nslp
|
if(SELF_LOOP_EN == "NO" ) begin :nslp
|
//remove available ovc of receiver port
|
//remove available ovc of receiver port
|
for(i=0;i< P;i=i+1) begin :port_loop
|
for(i=0;i< P;i=i+1) begin :port_loop
|
if(i==0) begin : first assign ovc_avalable_perport[i]=ovc_avalable_all [PV-1 : V]; end
|
if(i==0) begin : first assign ovc_avalable_perport[i]=ovc_avalable_all [PV-1 : V]; end
|
else if(i==(P-1)) begin : last assign ovc_avalable_perport[i]=ovc_avalable_all [PV-V-1 : 0]; end
|
else if(i==(P-1)) begin : last assign ovc_avalable_perport[i]=ovc_avalable_all [PV-V-1 : 0]; end
|
else begin : midle assign ovc_avalable_perport[i]={ovc_avalable_all [PV-1 : (i+1)*V],ovc_avalable_all [(i*V)-1 : 0]}; end
|
else begin : midle assign ovc_avalable_perport[i]={ovc_avalable_all [PV-1 : (i+1)*V],ovc_avalable_all [(i*V)-1 : 0]}; end
|
end
|
end
|
end else begin :slp
|
end else begin :slp
|
for(i=0;i< P;i=i+1) begin :port_loop
|
for(i=0;i< P;i=i+1) begin :port_loop
|
assign ovc_avalable_perport[i]=ovc_avalable_all;
|
assign ovc_avalable_perport[i]=ovc_avalable_all;
|
end
|
end
|
end
|
end
|
// IVC loop
|
// IVC loop
|
for(i=0;i< PV;i=i+1) begin :total_vc_loop
|
for(i=0;i< PV;i=i+1) begin :total_vc_loop
|
//separate input/output
|
//separate input/output
|
assign ovc_avalable_ivc[i] = ovc_avalable_perport[(i/V)];
|
assign ovc_avalable_ivc[i] = ovc_avalable_perport[(i/V)];
|
assign dest_port_ivc [i] = dest_port_in_all [(i+1)*P_1-1 : i*P_1 ];
|
assign dest_port_ivc [i] = dest_port_in_all [(i+1)*P_1-1 : i*P_1 ];
|
assign ovc_request_ivc [i] = (non_assigned_ovc_request_all[i])? candidate_ovc_all [(i+1)*V-1 : i*V ]: {V{1'b0}};
|
assign ovc_request_ivc [i] = (non_assigned_ovc_request_all[i])? candidate_ovc_all [(i+1)*V-1 : i*V ]: {V{1'b0}};
|
|
|
//available ovc multiplexer
|
//available ovc multiplexer
|
onehot_mux_1D #(
|
onehot_mux_1D #(
|
.W (V),
|
.W (V),
|
.N (P_1)
|
.N (P_1)
|
)
|
)
|
multiplexer
|
multiplexer
|
(
|
(
|
.in (ovc_avalable_ivc [i]),
|
.in (ovc_avalable_ivc [i]),
|
.out (ovc_avb_muxed [i]),
|
.out (ovc_avb_muxed [i]),
|
.sel (dest_port_ivc [i])
|
.sel (dest_port_ivc [i])
|
|
|
);
|
);
|
|
|
// mask unavailable ovc from requests
|
// mask unavailable ovc from requests
|
assign masked_ovc_request_all [(i+1)*V-1 : i*V ] = ovc_avb_muxed[i] & ovc_request_ivc [i];
|
assign masked_ovc_request_all [(i+1)*V-1 : i*V ] = ovc_avb_muxed[i] & ovc_request_ivc [i];
|
|
|
end
|
end
|
endgenerate
|
endgenerate
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|