`include "pronoc_def.v"
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`include "pronoc_def.v"
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//`define MONITORE_PATH
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//`define MONITORE_PATH
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/**********************************************************************
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/**********************************************************************
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** File: input_ports.v
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** File: input_ports.v
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**
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**
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** Copyright (C) 2014-2017 Alireza Monemi
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** Copyright (C) 2014-2017 Alireza Monemi
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**
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**
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** This file is part of ProNoC
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** This file is part of ProNoC
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**
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**
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** you can redistribute it and/or modify it under the terms of the GNU
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** you can redistribute it and/or modify it under the terms of the GNU
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** Lesser General Public License as published by the Free Software Foundation,
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** Lesser General Public License as published by the Free Software Foundation,
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** either version 2 of the License, or (at your option) any later version.
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** either version 2 of the License, or (at your option) any later version.
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**
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**
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with ProNoC. If not, see .
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** License along with ProNoC. If not, see .
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**
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**
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**
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**
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** Description:
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** Description:
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** NoC router input Port. It consists of input buffer, control FIFO
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** NoC router input Port. It consists of input buffer, control FIFO
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** and request masking/generation control modules
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** and request masking/generation control modules
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**
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**
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**************************************************************/
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**************************************************************/
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/**************************
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/**************************
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iport_reg_base
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iport_reg_base
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**************************/
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**************************/
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module iport_reg_base #(
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module iport_reg_base #(
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parameter NOC_ID=0,
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parameter PCK_TYPE = "MULTI_FLIT",
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parameter PCK_TYPE = "MULTI_FLIT",
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parameter V = 4, // vc_num_per_port
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parameter V = 4, // vc_num_per_port
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parameter P = 5, // router port num
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parameter P = 5, // router port num
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parameter B = 4, // buffer space :flit per VC
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parameter B = 4, // buffer space :flit per VC
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parameter T1= 8,
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parameter T1= 8,
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parameter T2= 8,
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parameter T2= 8,
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parameter T3= 8,
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parameter T3= 8,
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parameter T4= 8,
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parameter T4= 8,
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parameter RAw = 3,
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parameter RAw = 3,
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parameter EAw = 3,
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parameter EAw = 3,
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parameter C = 4, // number of flit class
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parameter C = 4, // number of flit class
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parameter Fpay = 32,
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parameter Fpay = 32,
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parameter SW_LOC = 0,
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parameter SW_LOC = 0,
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parameter VC_REALLOCATION_TYPE = "ATOMIC",
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parameter VC_REALLOCATION_TYPE = "ATOMIC",
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parameter COMBINATION_TYPE= "BASELINE",// "BASELINE", "COMB_SPEC1", "COMB_SPEC2", "COMB_NONSPEC"
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parameter COMBINATION_TYPE= "BASELINE",// "BASELINE", "COMB_SPEC1", "COMB_SPEC2", "COMB_NONSPEC"
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parameter TOPOLOGY = "MESH",//"MESH","TORUS"
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parameter TOPOLOGY = "MESH",//"MESH","TORUS"
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parameter ROUTE_NAME="XY",// "XY", "TRANC_XY"
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parameter ROUTE_NAME="XY",// "XY", "TRANC_XY"
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parameter ROUTE_TYPE="DETERMINISTIC",// "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE"
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parameter ROUTE_TYPE="DETERMINISTIC",// "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE"
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parameter DEBUG_EN =1,
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parameter DEBUG_EN =1,
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parameter AVC_ATOMIC_EN= 0,
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parameter AVC_ATOMIC_EN= 0,
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parameter CVw=(C==0)? V : C * V,
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parameter CVw=(C==0)? V : C * V,
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parameter [CVw-1: 0] CLASS_SETTING = {CVw{1'b1}}, // shows how each class can use VCs
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parameter [CVw-1: 0] CLASS_SETTING = {CVw{1'b1}}, // shows how each class can use VCs
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parameter [V-1 : 0] ESCAP_VC_MASK = 4'b1000, // mask scape vc, valid only for full adaptive
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parameter [V-1 : 0] ESCAP_VC_MASK = 4'b1000, // mask scape vc, valid only for full adaptive
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parameter DSTPw = P-1,
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parameter DSTPw = P-1,
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parameter SSA_EN="YES", // "YES" , "NO"
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parameter SSA_EN="YES", // "YES" , "NO"
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parameter SWA_ARBITER_TYPE ="RRA",// "RRA","WRRA"
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parameter SWA_ARBITER_TYPE ="RRA",// "RRA","WRRA"
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parameter WEIGHTw=4,
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parameter WEIGHTw=4,
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parameter WRRA_CONFIG_INDEX=0,
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parameter WRRA_CONFIG_INDEX=0,
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parameter PPSw=4,
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parameter PPSw=4,
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parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1.
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parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1.
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parameter BYTE_EN=0
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parameter BYTE_EN=0,
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parameter CAST_TYPE= "UNICAST"
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|
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)(
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)(
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current_r_addr,
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current_r_addr,
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neighbors_r_addr,
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neighbors_r_addr,
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ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
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ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
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any_ivc_sw_request_granted,
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any_ivc_sw_request_granted,
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flit_in,
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flit_in,
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flit_in_wr,
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flit_in_wr,
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reset_ivc,
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reset_ivc,
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flit_is_tail,
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flit_is_tail,
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ivc_request,
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ivc_request,
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dest_port_encoded,
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dest_port_encoded,
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dest_port,
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dest_port,
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candidate_ovcs,
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candidate_ovcs,
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flit_out,
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flit_out,
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assigned_ovc_num,
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assigned_ovc_num,
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sel,
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sel,
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port_pre_sel,
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port_pre_sel,
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swap_port_presel,
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swap_port_presel,
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reset,
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reset,
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clk,
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clk,
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nonspec_first_arbiter_granted_ivc,
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nonspec_first_arbiter_granted_ivc,
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destport_clear,
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destport_clear,
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ssa_ivc_num_getting_sw_grant,
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ssa_ivc_num_getting_sw_grant,
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iport_weight,
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iport_weight,
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oports_weight,
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oports_weight,
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vc_weight_is_consumed,
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vc_weight_is_consumed,
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iport_weight_is_consumed,
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iport_weight_is_consumed,
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refresh_w_counter,
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refresh_w_counter,
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granted_dest_port
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granted_dest_port
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);
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);
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function integer log2;
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function integer log2;
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input integer number; begin
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input integer number; begin
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log2=(number <=1) ? 1: 0;
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log2=(number <=1) ? 1: 0;
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while(2**log2
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while(2**log2
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log2=log2+1;
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log2=log2+1;
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end
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end
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end
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end
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endfunction // log2
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endfunction // log2
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localparam
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localparam
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VV = V * V,
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VV = V * V,
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VDSTPw = V * DSTPw,
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VDSTPw = V * DSTPw,
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Cw = (C>1)? log2(C): 1,
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Cw = (C>1)? log2(C): 1,
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Fw = 2+V+Fpay, //flit width;
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Fw = 2+V+Fpay, //flit width;
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W = WEIGHTw,
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W = WEIGHTw,
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WP = W * P,
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WP = W * P,
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P_1=P-1,
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P_1=P-1,
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VP_1 = V * P_1;
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VP_1 = V * P_1;
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localparam
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localparam
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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OFFSET = (B%MIN_PCK_SIZE)? 1 :0,
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OFFSET = (B%MIN_PCK_SIZE)? 1 :0,
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NON_ATOM_PCKS = (B>MIN_PCK_SIZE)? (B/MIN_PCK_SIZE)+ OFFSET : 1,
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NON_ATOM_PCKS = (B>MIN_PCK_SIZE)? (B/MIN_PCK_SIZE)+ OFFSET : 1,
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MAX_PCK = (VC_REALLOCATION_TYPE== "ATOMIC")? 1 : NON_ATOM_PCKS;// min packet size is two hence the max packet number in buffer is (B/2)
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MAX_PCK = (VC_REALLOCATION_TYPE== "ATOMIC")? 1 : NON_ATOM_PCKS;// min packet size is two hence the max packet number in buffer is (B/2)
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/* verilator lint_on WIDTH */
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/* verilator lint_on WIDTH */
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localparam
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localparam
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ELw = log2(T3),
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ELw = log2(T3),
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VELw= V * ELw,
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VELw= V * ELw,
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PRAw= P * RAw;
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PRAw= P * RAw;
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input reset, clk;
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input reset, clk;
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input [RAw-1 : 0] current_r_addr;
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input [RAw-1 : 0] current_r_addr;
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input [PRAw-1: 0] neighbors_r_addr;
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input [PRAw-1: 0] neighbors_r_addr;
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input [V-1 : 0] ivc_num_getting_sw_grant;
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input [V-1 : 0] ivc_num_getting_sw_grant;
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input any_ivc_sw_request_granted;
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input any_ivc_sw_request_granted;
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input [Fw-1 : 0] flit_in;
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input [Fw-1 : 0] flit_in;
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input flit_in_wr;
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input flit_in_wr;
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input [V-1 : 0] reset_ivc;
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input [V-1 : 0] reset_ivc;
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output [V-1 : 0] flit_is_tail;
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output [V-1 : 0] flit_is_tail;
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output [V-1 : 0] ivc_request;
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output [V-1 : 0] ivc_request;
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output [VDSTPw-1 : 0] dest_port_encoded;
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output [VDSTPw-1 : 0] dest_port_encoded;
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output [VP_1-1 : 0] dest_port;
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output [VP_1-1 : 0] dest_port;
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output [VV-1 : 0] candidate_ovcs;
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output [VV-1 : 0] candidate_ovcs;
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output [Fw-1 : 0] flit_out;
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output [Fw-1 : 0] flit_out;
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input [VV-1 : 0] assigned_ovc_num;
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input [VV-1 : 0] assigned_ovc_num;
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input [V-1 : 0] sel;
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input [V-1 : 0] sel;
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input [V-1 : 0] nonspec_first_arbiter_granted_ivc;
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input [V-1 : 0] nonspec_first_arbiter_granted_ivc;
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input [V-1 : 0] ssa_ivc_num_getting_sw_grant;
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input [V-1 : 0] ssa_ivc_num_getting_sw_grant;
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input [(DSTPw*V)-1 : 0] destport_clear;
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input [(DSTPw*V)-1 : 0] destport_clear;
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output [WEIGHTw-1 : 0] iport_weight;
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output [WEIGHTw-1 : 0] iport_weight;
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output [V-1 : 0] vc_weight_is_consumed;
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output [V-1 : 0] vc_weight_is_consumed;
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output iport_weight_is_consumed;
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output iport_weight_is_consumed;
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input refresh_w_counter;
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input refresh_w_counter;
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input [P_1-1 : 0] granted_dest_port;
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input [P_1-1 : 0] granted_dest_port;
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output [WP-1 : 0] oports_weight;
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output [WP-1 : 0] oports_weight;
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input [PPSw-1 : 0] port_pre_sel;
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input [PPSw-1 : 0] port_pre_sel;
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input [V-1 : 0] swap_port_presel;
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input [V-1 : 0] swap_port_presel;
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wire [Cw-1 : 0] class_in;
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wire [Cw-1 : 0] class_in;
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wire [DSTPw-1 : 0] destport_in,destport_in_encoded;
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wire [DSTPw-1 : 0] destport_in,destport_in_encoded;
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wire [VDSTPw-1 : 0] lk_destination_encoded;
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wire [VDSTPw-1 : 0] lk_destination_encoded;
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wire [EAw-1 : 0] dest_e_addr_in;
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wire [EAw-1 : 0] dest_e_addr_in;
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wire [EAw-1 : 0] src_e_addr_in;
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wire [EAw-1 : 0] src_e_addr_in;
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wire [V-1 : 0] vc_num_in;
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wire [V-1 : 0] vc_num_in;
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wire [V-1 : 0] hdr_flit_wr,flit_wr;
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wire [V-1 : 0] hdr_flit_wr,flit_wr;
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wire [V-1 : 0] hdr_flit_wr_delayed;
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wire [V-1 : 0] hdr_flit_wr_delayed;
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wire [V-1 : 0] class_rd_fifo,dst_rd_fifo;
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wire [V-1 : 0] class_rd_fifo,dst_rd_fifo;
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wire [V-1 : 0] lk_dst_rd_fifo;
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wire [V-1 : 0] lk_dst_rd_fifo;
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wire [DSTPw-1 : 0] lk_destination_in_encoded;
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wire [DSTPw-1 : 0] lk_destination_in_encoded;
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wire [WEIGHTw-1 : 0] weight_in;
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wire [WEIGHTw-1 : 0] weight_in;
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wire [Fw-1 : 0] buffer_out;
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wire [Fw-1 : 0] buffer_out;
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wire hdr_flg_in,tail_flg_in;
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wire hdr_flg_in,tail_flg_in;
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wire [V-1 : 0] ivc_not_empty;
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wire [V-1 : 0] ivc_not_empty;
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wire [Cw-1 : 0] class_out [V-1 : 0];
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wire [Cw-1 : 0] class_out [V-1 : 0];
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wire [VELw-1 : 0] endp_localp_num;
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wire [VELw-1 : 0] endp_localp_num;
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wire [ELw-1 : 0] endp_l_in;
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wire [ELw-1 : 0] endp_l_in;
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logic [WEIGHTw-1 : 0] iport_weight_next;
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logic [WEIGHTw-1 : 0] iport_weight_next;
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//extract header flit info
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//extract header flit info
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extract_header_flit_info #(
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extract_header_flit_info #(
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.NOC_ID(NOC_ID),
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.DATA_w(0)
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.DATA_w(0)
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)
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) header_extractor (
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header_extractor
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(
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.flit_in(flit_in),
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.flit_in(flit_in),
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.flit_in_wr(flit_in_wr),
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.flit_in_wr(flit_in_wr),
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.class_o(class_in),
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.class_o(class_in),
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.destport_o(destport_in),
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.destport_o(destport_in),
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.dest_e_addr_o(dest_e_addr_in),
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.dest_e_addr_o(dest_e_addr_in),
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.src_e_addr_o(src_e_addr_in),
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.src_e_addr_o(src_e_addr_in),
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.vc_num_o(vc_num_in),
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.vc_num_o(vc_num_in),
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.hdr_flit_wr_o(hdr_flit_wr),
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.hdr_flit_wr_o(hdr_flit_wr),
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.hdr_flg_o(hdr_flg_in),
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.hdr_flg_o(hdr_flg_in),
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.tail_flg_o(tail_flg_in),
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.tail_flg_o(tail_flg_in),
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.weight_o(weight_in),
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.weight_o(weight_in),
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.be_o( ),
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.be_o( ),
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.data_o( )
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.data_o( )
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);
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);
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// synopsys translate_off
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// synopsys translate_off
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// synthesis translate_off
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// synthesis translate_off
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`ifdef MONITORE_PATH
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`ifdef MONITORE_PATH
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|
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genvar j;
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genvar j;
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reg[V-1 :0] t1;
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reg[V-1 :0] t1;
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generate
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generate
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for (j=0;j
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for (j=0;j
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always @(posedge clk) begin
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always @(posedge clk) begin
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if(reset)begin
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if(reset)begin
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t1[j]<=1'b0;
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t1[j]<=1'b0;
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end else begin
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end else begin
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if(flit_in_wr >0 && vc_num_in[j] && t1[j]==0)begin
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if(flit_in_wr >0 && vc_num_in[j] && t1[j]==0)begin
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$display("%t : Parser: class_in=%x, destport_in=%x, dest_e_addr_in=%x, src_e_addr_in=%x, vc_num_in=%x,hdr_flit_wr=%x, hdr_flg_in=%x,tail_flg_in=%x ",$time,class_in, destport_in, dest_e_addr_in, src_e_addr_in, vc_num_in,hdr_flit_wr, hdr_flg_in,tail_flg_in);
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$display("%t : Parser: class_in=%x, destport_in=%x, dest_e_addr_in=%x, src_e_addr_in=%x, vc_num_in=%x,hdr_flit_wr=%x, hdr_flg_in=%x,tail_flg_in=%x ",$time,class_in, destport_in, dest_e_addr_in, src_e_addr_in, vc_num_in,hdr_flit_wr, hdr_flg_in,tail_flg_in);
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t1[j]<=1;
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t1[j]<=1;
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end
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end
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end
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end
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end
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end
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end
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end
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endgenerate
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endgenerate
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`endif
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`endif
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// synthesis translate_on
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// synthesis translate_on
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// synopsys translate_on
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// synopsys translate_on
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|
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pronoc_register #(.W(WEIGHTw), .RESET_TO(1)) reg5(
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pronoc_register #(.W(WEIGHTw), .RESET_TO(1)) reg5(
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.in (iport_weight_next ),
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.in (iport_weight_next ),
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.reset (reset ),
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.reset (reset ),
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.clk (clk ),
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.clk (clk ),
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.out (iport_weight ));
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.out (iport_weight ));
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|
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always @ (*)begin
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always @ (*)begin
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iport_weight_next = iport_weight;
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iport_weight_next = iport_weight;
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if(hdr_flit_wr != {V{1'b0}}) iport_weight_next = (weight_in=={WEIGHTw{1'b0}})? 1 : weight_in; // the minimum weight is 1
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if(hdr_flit_wr != {V{1'b0}}) iport_weight_next = (weight_in=={WEIGHTw{1'b0}})? 1 : weight_in; // the minimum weight is 1
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end
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end
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|
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// genrate write enable for lk_routing result with one clock cycle latency after reciveing the flit
|
// genrate write enable for lk_routing result with one clock cycle latency after reciveing the flit
|
|
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pronoc_register #(.W(V)) reg1(
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pronoc_register #(.W(V)) reg1(
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.in (hdr_flit_wr ),
|
.in (hdr_flit_wr ),
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.reset (reset ),
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.reset (reset ),
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.clk (clk ),
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.clk (clk ),
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.out (hdr_flit_wr_delayed ));
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.out (hdr_flit_wr_delayed ));
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genvar i;
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genvar i;
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generate
|
generate
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
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if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1)) begin : multi_local
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if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1)) begin : multi_local
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
mesh_tori_endp_addr_decode #(
|
mesh_tori_endp_addr_decode #(
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.TOPOLOGY("MESH"),
|
.TOPOLOGY("MESH"),
|
.T1(T1),
|
.T1(T1),
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.T2(T2),
|
.T2(T2),
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.T3(T3),
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.T3(T3),
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.EAw(EAw)
|
.EAw(EAw)
|
)
|
)
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endp_addr_decode
|
endp_addr_decode
|
(
|
(
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.e_addr(dest_e_addr_in),
|
.e_addr(dest_e_addr_in),
|
.ex( ),
|
.ex( ),
|
.ey( ),
|
.ey( ),
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.el(endp_l_in),
|
.el(endp_l_in),
|
.valid( )
|
.valid( )
|
);
|
);
|
end
|
end
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if(TOPOLOGY=="FATTREE" && ROUTE_NAME == "NCA_STRAIGHT_UP") begin : fat
|
if(TOPOLOGY=="FATTREE" && ROUTE_NAME == "NCA_STRAIGHT_UP") begin : fat
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
fattree_destport_up_select #(
|
fattree_destport_up_select #(
|
.K(T1),
|
.K(T1),
|
.SW_LOC(SW_LOC)
|
.SW_LOC(SW_LOC)
|
)
|
)
|
static_sel
|
static_sel
|
(
|
(
|
.destport_in(destport_in),
|
.destport_in(destport_in),
|
.destport_o(destport_in_encoded)
|
.destport_o(destport_in_encoded)
|
);
|
);
|
|
|
end else begin : other
|
end else begin : other
|
assign destport_in_encoded = destport_in;
|
assign destport_in_encoded = destport_in;
|
end
|
end
|
|
|
|
|
wire odd_column = current_r_addr[0];
|
wire odd_column = current_r_addr[0];
|
|
|
for (i=0;i
|
for (i=0;i
|
|
|
class_ovc_table #(
|
class_ovc_table #(
|
.CVw(CVw),
|
.CVw(CVw),
|
.CLASS_SETTING(CLASS_SETTING),
|
.CLASS_SETTING(CLASS_SETTING),
|
.C(C),
|
.C(C),
|
.V(V)
|
.V(V)
|
)
|
)
|
class_table
|
class_table
|
(
|
(
|
.class_in(class_out[i]),
|
.class_in(class_out[i]),
|
.candidate_ovcs(candidate_ovcs [(i+1)*V-1 : i*V])
|
.candidate_ovcs(candidate_ovcs [(i+1)*V-1 : i*V])
|
);
|
);
|
|
|
//tail fifo
|
//tail fifo
|
fwft_fifo #(
|
fwft_fifo #(
|
.DATA_WIDTH(1),
|
.DATA_WIDTH(1),
|
.MAX_DEPTH (B),
|
.MAX_DEPTH (B),
|
.IGNORE_SAME_LOC_RD_WR_WARNING(SSA_EN)
|
.IGNORE_SAME_LOC_RD_WR_WARNING(SSA_EN)
|
)
|
)
|
tail_fifo
|
tail_fifo
|
(
|
(
|
.din (tail_flg_in),
|
.din (tail_flg_in),
|
.wr_en (flit_wr[i]), // Write enable
|
.wr_en (flit_wr[i]), // Write enable
|
.rd_en (ivc_num_getting_sw_grant[i]), // Read the next word
|
.rd_en (ivc_num_getting_sw_grant[i]), // Read the next word
|
.dout (flit_is_tail[i]), // Data out
|
.dout (flit_is_tail[i]), // Data out
|
.full ( ),
|
.full ( ),
|
.nearly_full ( ),
|
.nearly_full ( ),
|
.recieve_more_than_0 ( ),
|
.recieve_more_than_0 ( ),
|
.recieve_more_than_1 ( ),
|
.recieve_more_than_1 ( ),
|
.reset (reset),
|
.reset (reset),
|
.clk (clk)
|
.clk (clk)
|
);
|
);
|
|
|
//class_fifo
|
//class_fifo
|
if(C>1)begin :cb1
|
if(C>1)begin :cb1
|
fwft_fifo #(
|
fwft_fifo #(
|
.DATA_WIDTH(Cw),
|
.DATA_WIDTH(Cw),
|
.MAX_DEPTH (MAX_PCK)
|
.MAX_DEPTH (MAX_PCK)
|
)
|
)
|
class_fifo
|
class_fifo
|
(
|
(
|
.din (class_in),
|
.din (class_in),
|
.wr_en (hdr_flit_wr[i]), // Write enable
|
.wr_en (hdr_flit_wr[i]), // Write enable
|
.rd_en (class_rd_fifo[i]), // Read the next word
|
.rd_en (class_rd_fifo[i]), // Read the next word
|
.dout (class_out[i]), // Data out
|
.dout (class_out[i]), // Data out
|
.full ( ),
|
.full ( ),
|
.nearly_full ( ),
|
.nearly_full ( ),
|
.recieve_more_than_0 ( ),
|
.recieve_more_than_0 ( ),
|
.recieve_more_than_1 ( ),
|
.recieve_more_than_1 ( ),
|
.reset (reset),
|
.reset (reset),
|
.clk (clk)
|
.clk (clk)
|
|
|
);
|
);
|
end else begin :c_num_1
|
end else begin :c_num_1
|
assign class_out[i] = 1'b0;
|
assign class_out[i] = 1'b0;
|
end
|
end
|
|
|
//lk_dst_fifo
|
//lk_dst_fifo
|
fwft_fifo #(
|
fwft_fifo #(
|
.DATA_WIDTH(DSTPw),
|
.DATA_WIDTH(DSTPw),
|
.MAX_DEPTH (MAX_PCK)
|
.MAX_DEPTH (MAX_PCK)
|
)
|
)
|
lk_dest_fifo
|
lk_dest_fifo
|
(
|
(
|
.din (lk_destination_in_encoded),
|
.din (lk_destination_in_encoded),
|
.wr_en (hdr_flit_wr_delayed [i]), // Write enable
|
.wr_en (hdr_flit_wr_delayed [i]), // Write enable
|
.rd_en (lk_dst_rd_fifo [i]), // Read the next word
|
.rd_en (lk_dst_rd_fifo [i]), // Read the next word
|
.dout (lk_destination_encoded [(i+1)*DSTPw-1 : i*DSTPw]), // Data out
|
.dout (lk_destination_encoded [(i+1)*DSTPw-1 : i*DSTPw]), // Data out
|
.full (),
|
.full (),
|
.nearly_full (),
|
.nearly_full (),
|
.recieve_more_than_0 (),
|
.recieve_more_than_0 (),
|
.recieve_more_than_1 (),
|
.recieve_more_than_1 (),
|
.reset (reset),
|
.reset (reset),
|
.clk (clk)
|
.clk (clk)
|
|
|
);
|
);
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if( ROUTE_TYPE=="DETERMINISTIC") begin : dtrmn_dest
|
if( ROUTE_TYPE=="DETERMINISTIC") begin : dtrmn_dest
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
//destport_fifo
|
//destport_fifo
|
fwft_fifo #(
|
fwft_fifo #(
|
.DATA_WIDTH(DSTPw),
|
.DATA_WIDTH(DSTPw),
|
.MAX_DEPTH (MAX_PCK)
|
.MAX_DEPTH (MAX_PCK)
|
)
|
)
|
dest_fifo
|
dest_fifo
|
(
|
(
|
.din(destport_in_encoded),
|
.din(destport_in_encoded),
|
.wr_en(hdr_flit_wr[i]), // Write enable
|
.wr_en(hdr_flit_wr[i]), // Write enable
|
.rd_en(dst_rd_fifo[i]), // Read the next word
|
.rd_en(dst_rd_fifo[i]), // Read the next word
|
.dout(dest_port_encoded[(i+1)*DSTPw-1 : i*DSTPw]), // Data out
|
.dout(dest_port_encoded[(i+1)*DSTPw-1 : i*DSTPw]), // Data out
|
.full(),
|
.full(),
|
.nearly_full(),
|
.nearly_full(),
|
.recieve_more_than_0(),
|
.recieve_more_than_0(),
|
.recieve_more_than_1(),
|
.recieve_more_than_1(),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
|
|
end else begin : adptv_dest
|
end else begin : adptv_dest
|
|
|
fwft_fifo_with_output_clear #(
|
fwft_fifo_with_output_clear #(
|
.DATA_WIDTH(DSTPw),
|
.DATA_WIDTH(DSTPw),
|
.MAX_DEPTH (MAX_PCK)
|
.MAX_DEPTH (MAX_PCK)
|
)
|
)
|
dest_fifo
|
dest_fifo
|
(
|
(
|
.din(destport_in_encoded),
|
.din(destport_in_encoded),
|
.wr_en(hdr_flit_wr[i]), // Write enable
|
.wr_en(hdr_flit_wr[i]), // Write enable
|
.rd_en(dst_rd_fifo[i]), // Read the next word
|
.rd_en(dst_rd_fifo[i]), // Read the next word
|
.dout(dest_port_encoded[(i+1)*DSTPw-1 : i*DSTPw]), // Data out
|
.dout(dest_port_encoded[(i+1)*DSTPw-1 : i*DSTPw]), // Data out
|
.full(),
|
.full(),
|
.nearly_full(),
|
.nearly_full(),
|
.recieve_more_than_0(),
|
.recieve_more_than_0(),
|
.recieve_more_than_1(),
|
.recieve_more_than_1(),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.clear(destport_clear[(i+1)*DSTPw-1 : i*DSTPw]) // clear other destination ports once one of them is selected
|
.clear(destport_clear[(i+1)*DSTPw-1 : i*DSTPw]) // clear other destination ports once one of them is selected
|
);
|
);
|
|
|
|
|
end
|
end
|
|
|
|
|
|
|
destp_generator #(
|
destp_generator #(
|
.TOPOLOGY(TOPOLOGY),
|
.TOPOLOGY(TOPOLOGY),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.T1(T1),
|
.T1(T1),
|
.NL(T3),
|
.NL(T3),
|
.P(P),
|
.P(P),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
.ELw(ELw),
|
.ELw(ELw),
|
.PPSw(PPSw),
|
.PPSw(PPSw),
|
.SW_LOC(SW_LOC)
|
.SW_LOC(SW_LOC)
|
)
|
)
|
decoder
|
decoder
|
(
|
(
|
.destport_one_hot(),
|
.destport_one_hot(),
|
.dest_port_encoded(dest_port_encoded[(i+1)*DSTPw-1 : i*DSTPw]),
|
.dest_port_encoded(dest_port_encoded[(i+1)*DSTPw-1 : i*DSTPw]),
|
.dest_port_out(dest_port[(i+1)*P_1-1 : i*P_1]),
|
.dest_port_out(dest_port[(i+1)*P_1-1 : i*P_1]),
|
.endp_localp_num(endp_localp_num[(i+1)*ELw-1 : i*ELw]),
|
.endp_localp_num(endp_localp_num[(i+1)*ELw-1 : i*ELw]),
|
.swap_port_presel(swap_port_presel[i]),
|
.swap_port_presel(swap_port_presel[i]),
|
.port_pre_sel(port_pre_sel),
|
.port_pre_sel(port_pre_sel),
|
.odd_column(odd_column)
|
.odd_column(odd_column)
|
);
|
);
|
|
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1)) begin : multi_local
|
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1)) begin : multi_local
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
// the router has multiple local ports. Save the destination local port
|
// the router has multiple local ports. Save the destination local port
|
|
|
|
|
fwft_fifo #(
|
fwft_fifo #(
|
.DATA_WIDTH(ELw),
|
.DATA_WIDTH(ELw),
|
.MAX_DEPTH (MAX_PCK)
|
.MAX_DEPTH (MAX_PCK)
|
)
|
)
|
local_dest_fifo
|
local_dest_fifo
|
(
|
(
|
.din(endp_l_in),
|
.din(endp_l_in),
|
.wr_en(hdr_flit_wr[i]), // Write enable
|
.wr_en(hdr_flit_wr[i]), // Write enable
|
.rd_en(dst_rd_fifo[i]), // Read the next word
|
.rd_en(dst_rd_fifo[i]), // Read the next word
|
.dout(endp_localp_num[(i+1)*ELw-1 : i*ELw]), // Data out
|
.dout(endp_localp_num[(i+1)*ELw-1 : i*ELw]), // Data out
|
.full( ),
|
.full( ),
|
.nearly_full( ),
|
.nearly_full( ),
|
.recieve_more_than_0(),
|
.recieve_more_than_0(),
|
.recieve_more_than_1(),
|
.recieve_more_than_1(),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
|
|
end else begin : slp
|
end else begin : slp
|
assign endp_localp_num[(i+1)*ELw-1 : i*ELw] = {ELw{1'bx}};
|
assign endp_localp_num[(i+1)*ELw-1 : i*ELw] = {ELw{1'bx}};
|
end
|
end
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if(SWA_ARBITER_TYPE != "RRA")begin : wrra
|
if(SWA_ARBITER_TYPE != "RRA")begin : wrra
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
/*
|
/*
|
weight_control #(
|
weight_control #(
|
.WEIGHTw(WEIGHTw)
|
.WEIGHTw(WEIGHTw)
|
)
|
)
|
wctrl_per_vc
|
wctrl_per_vc
|
(
|
(
|
.sw_is_granted(ivc_num_getting_sw_grant[i]),
|
.sw_is_granted(ivc_num_getting_sw_grant[i]),
|
.flit_is_tail(flit_is_tail[i]),
|
.flit_is_tail(flit_is_tail[i]),
|
.weight_is_consumed_o(vc_weight_is_consumed[i]),
|
.weight_is_consumed_o(vc_weight_is_consumed[i]),
|
.iport_weight(1), //(iport_weight),
|
.iport_weight(1), //(iport_weight),
|
.clk(clk),
|
.clk(clk),
|
.reset(reset)
|
.reset(reset)
|
);
|
);
|
*/
|
*/
|
assign vc_weight_is_consumed[i] = 1'b1;
|
assign vc_weight_is_consumed[i] = 1'b1;
|
end else begin :no_wrra
|
end else begin :no_wrra
|
assign vc_weight_is_consumed[i] = 1'bX;
|
assign vc_weight_is_consumed[i] = 1'bX;
|
end
|
end
|
|
|
end//for i
|
end//for i
|
|
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if(SWA_ARBITER_TYPE != "RRA")begin : wrra
|
if(SWA_ARBITER_TYPE != "RRA")begin : wrra
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
wire granted_flit_is_tail;
|
wire granted_flit_is_tail;
|
|
|
onehot_mux_1D #(
|
onehot_mux_1D #(
|
.W(1),
|
.W(1),
|
.N(V)
|
.N(V)
|
)
|
)
|
onehot_mux(
|
onehot_mux(
|
.in(flit_is_tail),
|
.in(flit_is_tail),
|
.out(granted_flit_is_tail),
|
.out(granted_flit_is_tail),
|
.sel(ivc_num_getting_sw_grant)
|
.sel(ivc_num_getting_sw_grant)
|
);
|
);
|
|
|
weight_control#(
|
weight_control#(
|
.ARBITER_TYPE(SWA_ARBITER_TYPE),
|
.ARBITER_TYPE(SWA_ARBITER_TYPE),
|
.SW_LOC(SW_LOC),
|
.SW_LOC(SW_LOC),
|
.WEIGHTw(WEIGHTw),
|
.WEIGHTw(WEIGHTw),
|
.WRRA_CONFIG_INDEX(WRRA_CONFIG_INDEX),
|
.WRRA_CONFIG_INDEX(WRRA_CONFIG_INDEX),
|
.P(P)
|
.P(P)
|
)
|
)
|
wctrl_iport
|
wctrl_iport
|
(
|
(
|
.sw_is_granted(any_ivc_sw_request_granted),
|
.sw_is_granted(any_ivc_sw_request_granted),
|
.flit_is_tail(granted_flit_is_tail),
|
.flit_is_tail(granted_flit_is_tail),
|
.weight_is_consumed_o(iport_weight_is_consumed),
|
.weight_is_consumed_o(iport_weight_is_consumed),
|
.iport_weight(iport_weight),
|
.iport_weight(iport_weight),
|
.oports_weight(oports_weight),
|
.oports_weight(oports_weight),
|
.granted_dest_port(granted_dest_port),
|
.granted_dest_port(granted_dest_port),
|
.refresh_w_counter(refresh_w_counter),
|
.refresh_w_counter(refresh_w_counter),
|
.clk(clk),
|
.clk(clk),
|
.reset(reset)
|
.reset(reset)
|
);
|
);
|
|
|
end else begin :no_wrra
|
end else begin :no_wrra
|
assign iport_weight_is_consumed=1'bX;
|
assign iport_weight_is_consumed=1'bX;
|
assign oports_weight = {WP{1'bX}};
|
assign oports_weight = {WP{1'bX}};
|
end
|
end
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if(COMBINATION_TYPE == "COMB_NONSPEC") begin : nonspec
|
if(COMBINATION_TYPE == "COMB_NONSPEC") begin : nonspec
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
flit_buffer #(
|
flit_buffer #(
|
|
.V(V),
|
.B(B), // buffer space :flit per VC
|
.B(B), // buffer space :flit per VC
|
.SSA_EN(SSA_EN)
|
.SSA_EN(SSA_EN),
|
|
.Fw(Fw),
|
|
.PCK_TYPE(PCK_TYPE),
|
|
.CAST_TYPE(CAST_TYPE),
|
|
.DEBUG_EN(DEBUG_EN)
|
|
|
)
|
)
|
the_flit_buffer
|
the_flit_buffer
|
(
|
(
|
.din(flit_in), // Data in
|
.din(flit_in), // Data in
|
.vc_num_wr(vc_num_in),//write vertual chanel
|
.vc_num_wr(vc_num_in),//write vertual chanel
|
.vc_num_rd(nonspec_first_arbiter_granted_ivc),//read vertual chanel
|
.vc_num_rd(nonspec_first_arbiter_granted_ivc),//read vertual chanel
|
.wr_en(flit_in_wr), // Write enable
|
.wr_en(flit_in_wr), // Write enable
|
.rd_en(any_ivc_sw_request_granted), // Read the next word
|
.rd_en(any_ivc_sw_request_granted), // Read the next word
|
.dout(buffer_out), // Data out
|
.dout(buffer_out), // Data out
|
.vc_not_empty(ivc_not_empty),
|
.vc_not_empty(ivc_not_empty),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.ssa_rd(ssa_ivc_num_getting_sw_grant),
|
.ssa_rd(ssa_ivc_num_getting_sw_grant),
|
.multiple_dest(),
|
.multiple_dest(),
|
.sub_rd_ptr_ld(),
|
.sub_rd_ptr_ld(),
|
.flit_is_tail()
|
.flit_is_tail()
|
);
|
);
|
|
|
|
|
|
|
localparam VCw = V *Cw;
|
localparam VCw = V *Cw;
|
wire [Fw-1:0] new_buffer_out;
|
wire [Fw-1:0] new_buffer_out;
|
wire [V-1 : 0] new_ivc_not_empty;
|
wire [V-1 : 0] new_ivc_not_empty;
|
wire [VCw-1 : 0] class_all;
|
wire [VCw-1 : 0] class_all;
|
|
|
|
|
|
|
flit_buffer_reg_base #(
|
flit_buffer_reg_base #(
|
.PCK_TYPE(PCK_TYPE),
|
.NOC_ID(NOC_ID),
|
.V(V),
|
.V(V),
|
.B(B),
|
.B(B),
|
|
.SSA_EN(SSA_EN),
|
.Fpay(Fpay),
|
.Fpay(Fpay),
|
.DEBUG_EN(DEBUG_EN),
|
.DEBUG_EN(DEBUG_EN),
|
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw)
|
.PCK_TYPE(PCK_TYPE),
|
|
.CAST_TYPE(CAST_TYPE)
|
)
|
)
|
nn
|
nn
|
(
|
(
|
.din(flit_in),
|
.din(flit_in),
|
.vc_num_wr(vc_num_in),
|
.vc_num_wr(vc_num_in),
|
.wr_en(flit_in_wr),
|
.wr_en(flit_in_wr),
|
.vc_num_rd(nonspec_first_arbiter_granted_ivc),
|
.vc_num_rd(nonspec_first_arbiter_granted_ivc),
|
.rd_en(any_ivc_sw_request_granted),
|
.rd_en(any_ivc_sw_request_granted),
|
.dout(new_buffer_out),
|
.dout(new_buffer_out),
|
.vc_not_empty(new_ivc_not_empty),
|
.vc_not_empty(new_ivc_not_empty),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.class_all()
|
.class_all()
|
);
|
);
|
|
|
//synthesis translate_off
|
//synthesis translate_off
|
//synopsys translate_off
|
//synopsys translate_off
|
reg check_dout;
|
reg check_dout;
|
always @(posedge clk )begin
|
always @(posedge clk )begin
|
check_dout<=any_ivc_sw_request_granted;
|
check_dout<=any_ivc_sw_request_granted;
|
if(new_ivc_not_empty != ivc_not_empty) begin
|
if(new_ivc_not_empty != ivc_not_empty) begin
|
$display("%t: Error: new_iv_not_empty (%h) != iv_not_empty (%h)",$time, new_ivc_not_empty, ivc_not_empty);
|
$display("%t: Error: new_iv_not_empty (%h) != iv_not_empty (%h)",$time, new_ivc_not_empty, ivc_not_empty);
|
$stop;
|
$stop;
|
end
|
end
|
|
|
if( check_dout & ( new_buffer_out[Fpay-1 : 0] != buffer_out[Fpay-1 : 0])) begin
|
if( check_dout & ( new_buffer_out[Fpay-1 : 0] != buffer_out[Fpay-1 : 0])) begin
|
$display("%t: Error: new_buffer_out (%h) != buffer_out (%h)",$time, new_buffer_out, buffer_out);
|
$display("%t: Error: new_buffer_out (%h) != buffer_out (%h)",$time, new_buffer_out, buffer_out);
|
$stop;
|
$stop;
|
end
|
end
|
end
|
end
|
//synopsys translate_on
|
//synopsys translate_on
|
//synthesis translate_on
|
//synthesis translate_on
|
|
|
|
|
|
|
|
|
// for (i=0;i
|
// for (i=0;i
|
|
|
// end
|
// end
|
|
|
|
|
|
|
end else begin :spec//not nonspec comb
|
end else begin :spec//not nonspec comb
|
|
|
|
|
flit_buffer #(
|
flit_buffer #(
|
|
.V(V),
|
.B(B), // buffer space :flit per VC
|
.B(B), // buffer space :flit per VC
|
.SSA_EN(SSA_EN)
|
.SSA_EN(SSA_EN),
|
|
.Fw(Fw),
|
|
.PCK_TYPE(PCK_TYPE),
|
|
.CAST_TYPE(CAST_TYPE),
|
|
.DEBUG_EN(DEBUG_EN)
|
)
|
)
|
the_flit_buffer
|
the_flit_buffer
|
(
|
(
|
.din(flit_in), // Data in
|
.din(flit_in), // Data in
|
.vc_num_wr(vc_num_in),//write vertual chanel
|
.vc_num_wr(vc_num_in),//write vertual chanel
|
.vc_num_rd(ivc_num_getting_sw_grant),//read vertual chanel
|
.vc_num_rd(ivc_num_getting_sw_grant),//read vertual chanel
|
.wr_en(flit_in_wr), // Write enable
|
.wr_en(flit_in_wr), // Write enable
|
.rd_en(any_ivc_sw_request_granted), // Read the next word
|
.rd_en(any_ivc_sw_request_granted), // Read the next word
|
.dout(buffer_out), // Data out
|
.dout(buffer_out), // Data out
|
.vc_not_empty(ivc_not_empty),
|
.vc_not_empty(ivc_not_empty),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.ssa_rd(ssa_ivc_num_getting_sw_grant),
|
.ssa_rd(ssa_ivc_num_getting_sw_grant),
|
.multiple_dest(),
|
.multiple_dest(),
|
.sub_rd_ptr_ld(),
|
.sub_rd_ptr_ld(),
|
.flit_is_tail()
|
.flit_is_tail()
|
|
|
);
|
);
|
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
look_ahead_routing #(
|
look_ahead_routing #(
|
.T1(T1),
|
.T1(T1),
|
.T2(T2),
|
.T2(T2),
|
.T3(T3),
|
.T3(T3),
|
.T4(T4),
|
.T4(T4),
|
.P(P),
|
.P(P),
|
.RAw(RAw),
|
.RAw(RAw),
|
.EAw(EAw),
|
.EAw(EAw),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
.SW_LOC(SW_LOC),
|
.SW_LOC(SW_LOC),
|
.TOPOLOGY(TOPOLOGY),
|
.TOPOLOGY(TOPOLOGY),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_NAME(ROUTE_NAME),
|
.ROUTE_TYPE(ROUTE_TYPE)
|
.ROUTE_TYPE(ROUTE_TYPE)
|
)
|
) lk_routing (
|
lk_routing
|
|
(
|
|
.current_r_addr(current_r_addr),
|
.current_r_addr(current_r_addr),
|
.neighbors_r_addr(neighbors_r_addr),
|
.neighbors_r_addr(neighbors_r_addr),
|
.dest_e_addr(dest_e_addr_in),
|
.dest_e_addr(dest_e_addr_in),
|
.src_e_addr(src_e_addr_in),
|
.src_e_addr(src_e_addr_in),
|
.destport_encoded(destport_in_encoded),
|
.destport_encoded(destport_in_encoded),
|
.lkdestport_encoded(lk_destination_in_encoded),
|
.lkdestport_encoded(lk_destination_in_encoded),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
|
|
header_flit_update_lk_route_ovc #(
|
header_flit_update_lk_route_ovc #(
|
.V(V),
|
.NOC_ID(NOC_ID),
|
.P(P),
|
.P(P)
|
|
) the_flit_update (
|
.TOPOLOGY(TOPOLOGY),
|
|
.EAw(EAw),
|
|
.DSTPw(DSTPw),
|
|
.SSA_EN(SSA_EN),
|
|
.ROUTE_TYPE(ROUTE_TYPE)
|
|
|
|
)
|
|
the_flit_update
|
|
(
|
|
.flit_in (buffer_out),
|
.flit_in (buffer_out),
|
.flit_out (flit_out),
|
.flit_out (flit_out),
|
.vc_num_in(ivc_num_getting_sw_grant),
|
.vc_num_in(ivc_num_getting_sw_grant),
|
.lk_dest_all_in (lk_destination_encoded),
|
.lk_dest_all_in (lk_destination_encoded),
|
.assigned_ovc_num (assigned_ovc_num),
|
.assigned_ovc_num (assigned_ovc_num),
|
.any_ivc_sw_request_granted(any_ivc_sw_request_granted),
|
.any_ivc_sw_request_granted(any_ivc_sw_request_granted),
|
.lk_dest_not_registered(lk_destination_in_encoded),
|
.lk_dest_not_registered(lk_destination_in_encoded),
|
.sel (sel),
|
.sel (sel),
|
.reset (reset),
|
.reset (reset),
|
.clk (clk)
|
.clk (clk)
|
);
|
);
|
|
|
assign flit_wr =(flit_in_wr )? vc_num_in : {V{1'b0}};
|
assign flit_wr =(flit_in_wr )? vc_num_in : {V{1'b0}};
|
|
|
|
|
pronoc_register #(.W(V)) reg2(
|
pronoc_register #(.W(V)) reg2(
|
.in (dst_rd_fifo ),
|
.in (dst_rd_fifo ),
|
.reset (reset ),
|
.reset (reset ),
|
.clk (clk ),
|
.clk (clk ),
|
.out (lk_dst_rd_fifo ));
|
.out (lk_dst_rd_fifo ));
|
|
|
|
|
assign dst_rd_fifo = reset_ivc;
|
assign dst_rd_fifo = reset_ivc;
|
assign class_rd_fifo = (C>1)? reset_ivc : {V{1'bx}};
|
assign class_rd_fifo = (C>1)? reset_ivc : {V{1'bx}};
|
assign ivc_request = ivc_not_empty;
|
assign ivc_request = ivc_not_empty;
|
|
|
//synthesis translate_off
|
//synthesis translate_off
|
//synopsys translate_off
|
//synopsys translate_off
|
generate
|
generate
|
if(DEBUG_EN) begin :dbg
|
if(DEBUG_EN) begin :dbg
|
|
|
debug_IVC_flit_type_order_check #(
|
debug_IVC_flit_type_order_check #(
|
.V(V)
|
.V(V)
|
)
|
)
|
IVC_flit_type_check
|
IVC_flit_type_check
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.hdr_flg_in(hdr_flg_in),
|
.hdr_flg_in(hdr_flg_in),
|
.tail_flg_in(tail_flg_in),
|
.tail_flg_in(tail_flg_in),
|
.flit_in_wr(flit_in_wr),
|
.flit_in_wr(flit_in_wr),
|
.vc_num_in(vc_num_in),
|
.vc_num_in(vc_num_in),
|
.reset_all_errors(1'b0),
|
.reset_all_errors(1'b0),
|
.active_IVC_hdr_flit_received_err( ),
|
.active_IVC_hdr_flit_received_err( ),
|
.inactive_IVC_tail_flit_received_err( ),
|
.inactive_IVC_tail_flit_received_err( ),
|
.inactive_IVC_body_flit_received_err( )
|
.inactive_IVC_body_flit_received_err( )
|
);
|
);
|
|
|
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS")) begin : mesh_based
|
if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS")) begin : mesh_based
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
|
|
debug_mesh_tori_route_ckeck #(
|
debug_mesh_tori_route_ckeck #(
|
.T1(T1),
|
.T1(T1),
|
.T2(T2),
|
.T2(T2),
|
.T3(T3),
|
.T3(T3),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.ROUTE_TYPE(ROUTE_TYPE),
|
.V(V),
|
.V(V),
|
.AVC_ATOMIC_EN(AVC_ATOMIC_EN),
|
.AVC_ATOMIC_EN(AVC_ATOMIC_EN),
|
.SW_LOC(SW_LOC),
|
.SW_LOC(SW_LOC),
|
.ESCAP_VC_MASK(ESCAP_VC_MASK),
|
.ESCAP_VC_MASK(ESCAP_VC_MASK),
|
.TOPOLOGY(TOPOLOGY),
|
.TOPOLOGY(TOPOLOGY),
|
.DSTPw(DSTPw),
|
.DSTPw(DSTPw),
|
.RAw(RAw),
|
.RAw(RAw),
|
.EAw(EAw)
|
.EAw(EAw)
|
)
|
)
|
route_ckeck
|
route_ckeck
|
(
|
(
|
.reset(reset),
|
.reset(reset),
|
.clk(clk),
|
.clk(clk),
|
.hdr_flg_in(hdr_flg_in),
|
.hdr_flg_in(hdr_flg_in),
|
.flit_in_wr(flit_in_wr),
|
.flit_in_wr(flit_in_wr),
|
.vc_num_in(vc_num_in),
|
.vc_num_in(vc_num_in),
|
.flit_is_tail(flit_is_tail),
|
.flit_is_tail(flit_is_tail),
|
.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
|
.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
|
.current_r_addr(current_r_addr),
|
.current_r_addr(current_r_addr),
|
.dest_e_addr_in(dest_e_addr_in),
|
.dest_e_addr_in(dest_e_addr_in),
|
.src_e_addr_in(src_e_addr_in),
|
.src_e_addr_in(src_e_addr_in),
|
.destport_in(destport_in)
|
.destport_in(destport_in)
|
);
|
);
|
end//mesh
|
end//mesh
|
end//DEBUG_EN
|
end//DEBUG_EN
|
endgenerate
|
endgenerate
|
//synopsys translate_on
|
//synopsys translate_on
|
//synthesis translate_on
|
//synthesis translate_on
|
|
|
|
|
endmodule
|
endmodule
|
|
|
