URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
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Rev 48 |
Rev 54 |
+incdir+./
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+incdir+./
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+incdir+./../
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./pronoc_pkg.sv
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./pronoc_pkg.sv
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./../main_comp.v
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./../main_comp.v
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./../arbiter.v
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./../arbiter.v
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./class_table.v
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./class_table.v
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./ss_allocator.sv
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./ss_allocator.sv
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./route_torus.v
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./route_torus.v
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./header_flit.sv
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./header_flit.sv
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./noc_top.sv
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./noc_top.sv
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./fattree_noc_top.sv
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./fattree_noc_top.sv
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./fattree_route.v
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./fattree_route.v
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./comb_nonspec.v
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./comb_nonspec.sv
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./inout_ports.sv
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./inout_ports.sv
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./wrra.v
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./wrra.v
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./input_ports.sv
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./input_ports.sv
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./tree_noc_top.sv
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./tree_noc_top.sv
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./tree_route.v
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./tree_route.v
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./comb-spec1.v
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./comb-spec1.v
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./combined_vc_sw_alloc.v
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./combined_vc_sw_alloc.sv
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./mesh_torus_routting.v
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./mesh_torus_routting.v
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./baseline.v
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./baseline.v
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./comb_spec2.v
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./comb_spec2.v
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./flit_buffer_reg_bas.v
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./flit_buffer_reg_bas.v
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./route_mesh.v
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./route_mesh.v
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./router_bypass.sv
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./router_bypass.sv
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./traffic_gen_top.sv
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./traffic_gen_top.sv
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./congestion_analyzer.v
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./congestion_analyzer.v
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./output_ports.sv
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./output_ports.sv
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./routing.v
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./routing.v
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./router_two_stage.sv
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./router_two_stage.sv
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./crossbar.v
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./crossbar.v
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./iport_reg_base.sv
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./iport_reg_base.sv
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./flit_buffer.v
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./flit_buffer.sv
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./mesh_torus.v
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./mesh_torus.sv
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./debug.v
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./debug.v
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./router_top.sv
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./router_top.sv
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./mesh_torus_noc_top.sv
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./mesh_torus_noc_top.sv
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./star_noc.sv
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./star_noc.sv
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./fmesh.sv
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./fmesh.sv
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./packet_injector.sv
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./packet_injector.sv
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./multicast.sv
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