// synthesis translate_off
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`include "pronoc_def.v"
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`timescale 1ns / 1ps
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// synthesis translate_on
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/**********************************************************************
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/**********************************************************************
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** File: noc_top.sv
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** File: noc_top.sv
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**
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**
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** Copyright (C) 2014-2017 Alireza Monemi
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** Copyright (C) 2014-2017 Alireza Monemi
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**
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**
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** This file is part of ProNoC
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** This file is part of ProNoC
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**
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**
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** you can redistribute it and/or modify it under the terms of the GNU
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** you can redistribute it and/or modify it under the terms of the GNU
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** Lesser General Public License as published by the Free Software Foundation,
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** Lesser General Public License as published by the Free Software Foundation,
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** either version 2 of the License, or (at your option) any later version.
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** either version 2 of the License, or (at your option) any later version.
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**
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**
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with ProNoC. If not, see .
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** License along with ProNoC. If not, see .
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**
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**
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**
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**
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** Description:
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** Description:
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** the NoC top module.
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** the NoC top module.
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**
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**
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**************************************************************/
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**************************************************************/
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module noc_top
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module noc_top
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import pronoc_pkg::*;
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import pronoc_pkg::*;
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(
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(
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reset,
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reset,
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clk,
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clk,
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chan_in_all,
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chan_in_all,
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chan_out_all
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chan_out_all,
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router_event
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);
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);
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input clk,reset;
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input clk,reset;
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//local ports
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//Endpoints ports
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input smartflit_chanel_t chan_in_all [NE-1 : 0];
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input smartflit_chanel_t chan_in_all [NE-1 : 0];
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output smartflit_chanel_t chan_out_all [NE-1 : 0];
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output smartflit_chanel_t chan_out_all [NE-1 : 0];
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//Events
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output router_event_t router_event [NR-1 : 0][MAX_P-1 : 0];
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generate
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generate
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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if (TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin : tori_noc
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if (TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin : tori_noc
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/* verilator lint_on WIDTH */
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/* verilator lint_on WIDTH */
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mesh_torus_noc_top noc_top (
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mesh_torus_noc_top noc_top (
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.reset (reset ),
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.reset (reset ),
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.clk (clk ),
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.clk (clk ),
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.chan_in_all (chan_in_all ),
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.chan_in_all (chan_in_all ),
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.chan_out_all (chan_out_all )
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.chan_out_all (chan_out_all ),
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.router_event (router_event )
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);
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);
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end else if (TOPOLOGY == "FATTREE") begin : fat_
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end else if (TOPOLOGY == "FATTREE") begin : fat_
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fattree_noc_top noc_top (
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fattree_noc_top noc_top (
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.reset (reset ),
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.reset (reset ),
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.clk (clk ),
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.clk (clk ),
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.chan_in_all (chan_in_all ),
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.chan_in_all (chan_in_all ),
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.chan_out_all (chan_out_all )
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.chan_out_all (chan_out_all ),
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.router_event (router_event )
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);
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);
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end else if (TOPOLOGY == "TREE") begin : tree_
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end else if (TOPOLOGY == "TREE") begin : tree_
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tree_noc_top noc_top (
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tree_noc_top noc_top (
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.reset (reset ),
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.reset (reset ),
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.clk (clk ),
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.clk (clk ),
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.chan_in_all (chan_in_all ),
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.chan_in_all (chan_in_all ),
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.chan_out_all (chan_out_all )
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.chan_out_all (chan_out_all ),
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.router_event (router_event )
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);
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);
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end else if (TOPOLOGY == "STAR") begin : star_
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end else if (TOPOLOGY == "STAR") begin : star_
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star_noc_top noc_top (
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star_noc_top noc_top (
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.reset (reset ),
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.reset (reset ),
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.clk (clk ),
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.clk (clk ),
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.chan_in_all (chan_in_all ),
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.chan_in_all (chan_in_all ),
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.chan_out_all (chan_out_all )
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.chan_out_all (chan_out_all ),
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.router_event (router_event )
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);
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);
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end else begin :custom_
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end else begin :custom_
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custom_noc_top noc_top (
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custom_noc_top noc_top (
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.reset (reset ),
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.reset (reset ),
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.clk (clk ),
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.clk (clk ),
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.chan_in_all (chan_in_all ),
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.chan_in_all (chan_in_all ),
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.chan_out_all (chan_out_all )
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.chan_out_all (chan_out_all ),
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.router_event (router_event )
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);
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);
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end
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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/**********************************
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/**********************************
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The noc top module that can be caled in Verilog module.
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The noc top module that can be called in Verilog module.
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***********************************/
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***********************************/
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module noc_top_v
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module noc_top_v
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import pronoc_pkg::*;
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import pronoc_pkg::*;
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(
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(
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flit_out_all,
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flit_out_all,
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flit_out_wr_all,
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flit_out_wr_all,
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credit_in_all,
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credit_in_all,
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flit_in_all,
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flit_in_all,
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flit_in_wr_all,
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flit_in_wr_all,
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credit_out_all,
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credit_out_all,
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reset,
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reset,
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clk
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clk
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);
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);
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input clk,reset;
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input clk,reset;
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output [NEFw-1 : 0] flit_out_all;
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output [NEFw-1 : 0] flit_out_all;
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output [NE-1 : 0] flit_out_wr_all;
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output [NE-1 : 0] flit_out_wr_all;
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input [NEV-1 : 0] credit_in_all;
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input [NEV-1 : 0] credit_in_all;
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input [NEFw-1 : 0] flit_in_all;
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input [NEFw-1 : 0] flit_in_all;
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input [NE-1 : 0] flit_in_wr_all;
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input [NE-1 : 0] flit_in_wr_all;
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output [NEV-1 : 0] credit_out_all;
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output [NEV-1 : 0] credit_out_all;
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//struct typed array ports which cannot be caled in verilog
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//struct typed array ports which cannot be caled in verilog
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smartflit_chanel_t chan_in_all [NE-1 : 0];
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smartflit_chanel_t chan_in_all [NE-1 : 0];
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smartflit_chanel_t chan_out_all [NE-1 : 0];
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smartflit_chanel_t chan_out_all [NE-1 : 0];
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noc_top the_top(
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noc_top the_top(
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.reset(reset),
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.reset(reset),
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.clk(clk),
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.clk(clk),
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.chan_in_all(chan_in_all),
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.chan_in_all(chan_in_all),
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.chan_out_all(chan_out_all)
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.chan_out_all(chan_out_all),
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.router_event ( )
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);
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);
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genvar i;
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genvar i;
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generate
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generate
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for (i=0; i
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for (i=0; i
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assign chan_in_all[i].flit_chanel.flit = flit_in_all [Fw*(i+1)-1 : Fw*i];
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assign chan_in_all[i].flit_chanel.flit = flit_in_all [Fw*(i+1)-1 : Fw*i];
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assign chan_in_all[i].flit_chanel.credit = credit_in_all [V*(i+1)-1 : V*i];
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assign chan_in_all[i].flit_chanel.credit = credit_in_all [V*(i+1)-1 : V*i];
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assign chan_in_all[i].flit_chanel.flit_wr = flit_in_wr_all[i];
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assign chan_in_all[i].flit_chanel.flit_wr = flit_in_wr_all[i];
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assign flit_out_all [Fw*(i+1)-1 : Fw*i] = chan_out_all[i].flit_chanel.flit;
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assign flit_out_all [Fw*(i+1)-1 : Fw*i] = chan_out_all[i].flit_chanel.flit;
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assign credit_out_all [V*(i+1)-1 : V*i] = chan_out_all[i].flit_chanel.credit;
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assign credit_out_all [V*(i+1)-1 : V*i] = chan_out_all[i].flit_chanel.credit;
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assign flit_out_wr_all[i] = chan_out_all[i].flit_chanel.flit_wr;
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assign flit_out_wr_all[i] = chan_out_all[i].flit_chanel.flit_wr;
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end
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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