`timescale 1ns / 1ps
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`include "pronoc_def.v"
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/****************************************************************************
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/****************************************************************************
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* router_top.v
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* router_top.v
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****************************************************************************/
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****************************************************************************/
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/**
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/**
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* Module: router_top
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* Module: router_top
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*
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*
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* add optional bypass links to two stage router.
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* add optional bypass links to two stage router.
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*/
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*/
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module router_top
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module router_top
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import pronoc_pkg::*;
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import pronoc_pkg::*;
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# (
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# (
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parameter P = 5 // router port num
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parameter P = 5 // router port num
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)(
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)(
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current_r_addr,// connected to constant parameter
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current_r_id,
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current_r_addr,
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chan_in,
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chan_in,
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chan_out,
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chan_out,
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router_event,
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clk,
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clk,
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reset
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reset
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);
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);
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localparam DISABLED =P;
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localparam DISABLED =P;
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input [RAw-1 : 0] current_r_addr;
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input [RAw-1 : 0] current_r_addr;
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input [31 : 0] current_r_id;
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input smartflit_chanel_t chan_in [P-1 : 0];
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input smartflit_chanel_t chan_in [P-1 : 0];
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output smartflit_chanel_t chan_out [P-1 : 0];
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output smartflit_chanel_t chan_out [P-1 : 0];
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output router_event_t router_event [P-1 : 0];
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input clk,reset;
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input clk,reset;
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genvar i,j;
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genvar i,j;
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//synthesis translate_off
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//synthesis translate_off
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//synopsys translate_off
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//synopsys translate_off
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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initial begin
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initial begin
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if((SSA_EN=="YES") && (SMART_EN==1'b1) )begin
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if((SSA_EN=="YES") && (SMART_EN==1'b1) )begin
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$display("ERROR: Only one of the SMART or SAA can be enabled at the same time");
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$display("ERROR: Only one of the SMART or SAA can be enabled at the same time");
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$finish;
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$finish;
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end
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end
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if((SMART_EN==1'b1) && COMBINATION_TYPE!="COMB_NONSPEC" )begin
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if((SMART_EN==1'b1) && COMBINATION_TYPE!="COMB_NONSPEC" )begin
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$display("ERROR: SMART only works with non-speculative VSA");
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$display("ERROR: SMART only works with non-speculative VSA");
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$finish;
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$finish;
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end
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end
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if((MIN_PCK_SIZE > 1) && (PCK_TYPE == "SINGLE_FLIT")) begin
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if((MIN_PCK_SIZE > 1) && (PCK_TYPE == "SINGLE_FLIT")) begin
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$display("ERROR: The minimum packet size must be set as one for single-flit packet type NoC");
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$display("ERROR: The minimum packet size must be set as one for single-flit packet type NoC");
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$finish;
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$finish;
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end
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end
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if(((SSA_EN=="YES") || (SMART_EN==1'b1) ) && CAST_TYPE!="UNICAST") begin
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$display("ERROR: SMART or SAA do not support muticast/braodcast packets");
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$finish;
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end
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end
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end
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/* verilator lint_on WIDTH */
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logic report_active_ivcs = 0;
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logic report_active_ivcs = 0;
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generate
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generate
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for (i=0; i
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for (i=0; i
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for (j=0; j
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for (j=0; j
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always @ (posedge report_active_ivcs) begin
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always @ (posedge report_active_ivcs) begin
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if(ivc_info[i][j].ivc_req) $display("%t : The IVC in router[%h] port[%d] VC [%d] is not empty",$time,current_r_addr,i,j);
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if(ivc_info[i][j].ivc_req) $display("%t : The IVC in router[%h] port[%d] VC [%d] is not empty",$time,current_r_addr,i,j);
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end
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end
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end
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end
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end
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end
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endgenerate
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endgenerate
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/* verilator lint_on WIDTH */
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//synopsys translate_on
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//synopsys translate_on
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//synthesis translate_on
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//synthesis translate_on
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generate
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for (i=0; i
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assign router_event[i].flit_wr_i = chan_in[i].flit_chanel.flit_wr;
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assign router_event[i].bypassed_num = chan_in[i].smart_chanel.bypassed_num;
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assign router_event[i].pck_wr_i = chan_in[i].flit_chanel.flit_wr & chan_in[i].flit_chanel.flit.hdr_flag;
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assign router_event[i].flit_wr_o = chan_out[i].flit_chanel.flit_wr;
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assign router_event[i].pck_wr_o = chan_out[i].flit_chanel.flit_wr & chan_out[i].flit_chanel.flit.hdr_flag;
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assign router_event[i].flit_in_bypassed = chan_out[i].smart_chanel.flit_in_bypassed;
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end
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endgenerate
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flit_chanel_t r2_chan_in [P-1 : 0];
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flit_chanel_t r2_chan_in [P-1 : 0];
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flit_chanel_t r2_chan_out [P-1 : 0];
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flit_chanel_t r2_chan_out [P-1 : 0];
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ivc_info_t ivc_info [P-1 : 0][V-1 : 0];
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ivc_info_t ivc_info [P-1 : 0][V-1 : 0];
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ovc_info_t ovc_info [P-1 : 0][V-1 : 0];
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ovc_info_t ovc_info [P-1 : 0][V-1 : 0];
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iport_info_t iport_info [P-1 : 0];
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iport_info_t iport_info [P-1 : 0];
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oport_info_t oport_info [P-1 : 0];
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oport_info_t oport_info [P-1 : 0];
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smart_chanel_t smart_chanel_new [P-1 : 0];
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smart_chanel_t smart_chanel_new [P-1 : 0];
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smart_chanel_t smart_chanel_in [P-1 : 0];
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smart_chanel_t smart_chanel_in [P-1 : 0];
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smart_chanel_t smart_chanel_out [P-1 : 0];
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smart_chanel_t smart_chanel_out [P-1 : 0];
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smart_ctrl_t smart_ctrl [P-1 : 0];
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smart_ctrl_t smart_ctrl [P-1 : 0];
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ctrl_chanel_t ctrl_in [P-1 : 0];
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ctrl_chanel_t ctrl_in [P-1 : 0];
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ctrl_chanel_t ctrl_out [P-1 : 0];
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ctrl_chanel_t ctrl_out [P-1 : 0];
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generate
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generate
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for (i=0; i
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for (i=0; i
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assign ctrl_in [i] = chan_in[i].ctrl_chanel;
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assign ctrl_in [i] = chan_in[i].ctrl_chanel;
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assign chan_out[i].ctrl_chanel= ctrl_out [i];
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assign chan_out[i].ctrl_chanel= ctrl_out [i];
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end
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end
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endgenerate
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endgenerate
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// synthesis translate_off
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// synthesis translate_off
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//header flit info, it is useful for debugin
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//header flit info, it is useful for debugin
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hdr_flit_t hdr_flit_i [P-1 : 0]; // the received packet header flit info
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hdr_flit_t hdr_flit_i [P-1 : 0]; // the received packet header flit info
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hdr_flit_t hdr_flit_o [P-1 : 0]; // the sent packet header flit info
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hdr_flit_t hdr_flit_o [P-1 : 0]; // the sent packet header flit info
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generate
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generate
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for (i=0; i
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for (i=0; i
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header_flit_info in_extract(
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header_flit_info in_extract(
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.flit(chan_in[i].flit_chanel.flit),
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.flit(chan_in[i].flit_chanel.flit),
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.hdr_flit( hdr_flit_i[i]),
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.hdr_flit( hdr_flit_i[i]),
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.data_o()
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.data_o()
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);
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);
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header_flit_info out_extract(
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header_flit_info out_extract(
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.flit(chan_out[i].flit_chanel.flit),
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.flit(chan_out[i].flit_chanel.flit),
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.hdr_flit( hdr_flit_o[i]),
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.hdr_flit( hdr_flit_o[i]),
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.data_o()
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.data_o()
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);
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);
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if(DEBUG_EN) begin :dbg
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if(DEBUG_EN) begin :dbg
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check_flit_chanel_type_is_in_order #(
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check_flit_chanel_type_is_in_order #(
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.V(V),
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.V(V),
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.PCK_TYPE(PCK_TYPE),
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.PCK_TYPE(PCK_TYPE),
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.MIN_PCK_SIZE(MIN_PCK_SIZE)
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.MIN_PCK_SIZE(MIN_PCK_SIZE)
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)
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)
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IVC_flit_type_check
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IVC_flit_type_check
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(
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(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),
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.hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),
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.tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),
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.tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),
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.flit_in_wr(chan_in[i].flit_chanel.flit_wr),
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.flit_in_wr(chan_in[i].flit_chanel.flit_wr),
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.vc_num_in(chan_in[i].flit_chanel.flit.vc)
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.vc_num_in(chan_in[i].flit_chanel.flit.vc)
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);
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);
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check_pck_size #(
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.V(V),
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.MIN_PCK_SIZE(MIN_PCK_SIZE),
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.Fw(Fw),
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.DAw(DAw),
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.CAST_TYPE(CAST_TYPE),
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.NE(NE),
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.B(B),
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.LB(LB)
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)
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check_pck_siz
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(
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.clk(clk),
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.reset(reset),
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.hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),
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.tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),
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.flit_in_wr(chan_in[i].flit_chanel.flit_wr),
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.vc_num_in(chan_in[i].flit_chanel.flit.vc),
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.dest_e_addr_in(chan_in[i].flit_chanel.flit.payload[E_DST_MSB : E_DST_LSB])
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);
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end
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end
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end
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end
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endgenerate
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endgenerate
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// synthesis translate_on
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// synthesis translate_on
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wire [V-1 : 0] ovc_locally_requested [P-1 : 0];
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wire [V-1 : 0] ovc_locally_requested [P-1 : 0];
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flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit bypass link goes to straight port
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flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit bypass link goes to straight port
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router_two_stage #(//r2
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router_two_stage #(//r2
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.P (P)
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.P (P)
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)router_ref (
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)router_ref (
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.ivc_info (ivc_info),
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.ivc_info (ivc_info),
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.ovc_info (ovc_info),
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.ovc_info (ovc_info),
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.iport_info (iport_info),
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.iport_info (iport_info),
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.oport_info (oport_info),
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.oport_info (oport_info),
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.smart_ctrl_in (smart_ctrl),
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.smart_ctrl_in (smart_ctrl),
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.current_r_addr(current_r_addr),
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.current_r_addr(current_r_addr),
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.current_r_id(current_r_id),
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.chan_in (r2_chan_in),
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.chan_in (r2_chan_in),
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.chan_out (r2_chan_out),
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.chan_out (r2_chan_out),
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.ctrl_in (ctrl_in),
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.ctrl_in (ctrl_in),
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.ctrl_out (ctrl_out),
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.ctrl_out (ctrl_out),
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.clk (clk),
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.clk (clk),
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.reset (reset)
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.reset (reset)
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);
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);
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generate
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generate
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if(SMART_EN) begin :smart
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if(SMART_EN) begin :smart
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smart_forward_ivc_info
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smart_forward_ivc_info
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#(
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#(
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.P(P)
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.P(P)
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)forward_ivc(
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)forward_ivc(
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.ivc_info(ivc_info),
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.ivc_info(ivc_info),
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.iport_info(iport_info),
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.iport_info(iport_info),
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.oport_info(oport_info),
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.oport_info(oport_info),
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.smart_chanel(smart_chanel_new),
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.smart_chanel(smart_chanel_new),
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.ovc_locally_requested(ovc_locally_requested),
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.ovc_locally_requested(ovc_locally_requested),
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.reset(reset),
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.reset(reset),
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.clk(clk)
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.clk(clk)
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);
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);
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smart_bypass_chanels
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smart_bypass_chanels
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#(
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#(
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.P(P)
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.P(P)
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)smart_bypass(
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)smart_bypass(
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.ivc_info(ivc_info),
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.ivc_info(ivc_info),
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.iport_info(iport_info),
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.iport_info(iport_info),
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.oport_info(oport_info),
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.oport_info(oport_info),
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.smart_chanel_new(smart_chanel_new),
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.smart_chanel_new(smart_chanel_new),
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.smart_chanel_in(smart_chanel_in),
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.smart_chanel_in(smart_chanel_in),
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.smart_chanel_out(smart_chanel_out),
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.smart_chanel_out(smart_chanel_out),
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.smart_req( ),
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.smart_req( ),
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.reset(reset),
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.reset(reset),
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.clk(clk)
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.clk(clk)
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);
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);
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wire [RAw-1: 0] neighbors_r_addr [P-1: 0];
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wire [RAw-1: 0] neighbors_r_addr [P-1: 0];
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wire [V-1 : 0] credit_out [P-1 : 0];
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wire [V-1 : 0] credit_out [P-1 : 0];
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wire [V-1 : 0] ivc_smart_en [P-1 : 0];
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wire [V-1 : 0] ivc_smart_en [P-1 : 0];
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for (i=0;i
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for (i=0;i
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localparam SS_PORT = strieght_port (P,i);
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localparam SS_PORT = strieght_port (P,i);
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if(SS_PORT == DISABLED) begin: smart_dis
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if(SS_PORT == DISABLED) begin: smart_dis
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assign r2_chan_in[i] = chan_in[i].flit_chanel;
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assign r2_chan_in[i] = chan_in[i].flit_chanel;
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assign chan_out[i].flit_chanel = r2_chan_out[i];
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assign chan_out[i].flit_chanel = r2_chan_out[i];
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assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};
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assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};
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end
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end
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else begin :smart_en
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else begin :smart_en
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assign neighbors_r_addr [i] = chan_in[i].ctrl_chanel.neighbors_r_addr;
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assign neighbors_r_addr [i] = chan_in[i].ctrl_chanel.neighbors_r_addr;
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//smart allocator
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//smart allocator
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smart_allocator_per_iport #(
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smart_allocator_per_iport #(
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.P (P ),
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.P (P ),
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.SW_LOC (i ),
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.SW_LOC (i ),
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.SS_PORT_LOC (SS_PORT )
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.SS_PORT_LOC (SS_PORT )
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) smart_allocator(
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) smart_allocator(
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.clk (clk ),
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.clk (clk ),
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.reset (reset ),
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.reset (reset ),
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.current_r_addr_i (current_r_addr ),
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.current_r_addr_i (current_r_addr ),
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.neighbors_r_addr_i (neighbors_r_addr ),
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.neighbors_r_addr_i (neighbors_r_addr ),
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.smart_chanel_i (chan_in[i].smart_chanel ),
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.smart_chanel_i (chan_in[i].smart_chanel ),
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.flit_chanel_i (chan_in[i].flit_chanel ),
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.flit_chanel_i (chan_in[i].flit_chanel ),
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.ivc_info (ivc_info[i] ),
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.ivc_info (ivc_info[i] ),
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.ss_ovc_info (ovc_info[SS_PORT] ),
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.ss_ovc_info (ovc_info[SS_PORT] ),
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.ovc_locally_requested (ovc_locally_requested[SS_PORT] ),
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.ovc_locally_requested (ovc_locally_requested[SS_PORT] ),
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.ss_smart_chanel_new (smart_chanel_new[SS_PORT]),
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.ss_smart_chanel_new (smart_chanel_new[SS_PORT]),
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.ss_port_link_reg_flit_wr (r2_chan_out[SS_PORT].flit_wr),
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.ss_port_link_reg_flit_wr (r2_chan_out[SS_PORT].flit_wr),
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.smart_ivc_single_flit_pck_o (smart_ctrl[i].ivc_single_flit_pck),
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.smart_ivc_single_flit_pck_o (smart_ctrl[i].ivc_single_flit_pck),
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.smart_destport_o (smart_ctrl[i].destport ),
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.smart_destport_o (smart_ctrl[i].destport ),
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.smart_lk_destport_o (smart_ctrl[i].lk_destport ),
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.smart_lk_destport_o (smart_ctrl[i].lk_destport ),
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.smart_hdr_flit_req_o (smart_ctrl[i].hdr_flit_req ),
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.smart_hdr_flit_req_o (smart_ctrl[i].hdr_flit_req ),
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.smart_ivc_smart_en_o (ivc_smart_en[i] ),
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.smart_ivc_smart_en_o (ivc_smart_en[i] ),
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.smart_credit_o (smart_ctrl[i].credit_out ),
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.smart_credit_o (smart_ctrl[i].credit_out ),
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.smart_buff_space_decreased_o (smart_ctrl[SS_PORT].buff_space_decreased),
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.smart_buff_space_decreased_o (smart_ctrl[SS_PORT].buff_space_decreased),
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.smart_ivc_num_getting_ovc_grant_o(smart_ctrl[i].ivc_num_getting_ovc_grant),
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.smart_ivc_num_getting_ovc_grant_o(smart_ctrl[i].ivc_num_getting_ovc_grant),
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.smart_ivc_reset_o (smart_ctrl[i].ivc_reset),
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.smart_ivc_reset_o (smart_ctrl[i].ivc_reset),
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.smart_ivc_granted_ovc_num_o (smart_ctrl[i].ivc_granted_ovc_num),
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.smart_ivc_granted_ovc_num_o (smart_ctrl[i].ivc_granted_ovc_num),
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.smart_ovc_single_flit_pck_o (smart_ctrl[SS_PORT].ovc_single_flit_pck),
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.smart_ovc_single_flit_pck_o (smart_ctrl[SS_PORT].ovc_single_flit_pck),
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.smart_ss_ovc_is_allocated_o (smart_ctrl[SS_PORT].ovc_is_allocated),
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.smart_ss_ovc_is_allocated_o (smart_ctrl[SS_PORT].ovc_is_allocated),
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.smart_ss_ovc_is_released_o (smart_ctrl[SS_PORT].ovc_is_released),
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.smart_ss_ovc_is_released_o (smart_ctrl[SS_PORT].ovc_is_released),
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.smart_mask_available_ss_ovc_o (smart_ctrl[SS_PORT].mask_available_ovc)
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.smart_mask_available_ss_ovc_o (smart_ctrl[SS_PORT].mask_available_ovc)
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|
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);
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);
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assign smart_ctrl[i].ivc_smart_en = ivc_smart_en[i];
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assign smart_ctrl[i].ivc_smart_en = ivc_smart_en[i];
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assign smart_ctrl[i].smart_en = |ivc_smart_en[i];
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assign smart_ctrl[i].smart_en = |ivc_smart_en[i];
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// synthesis translate_off
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// synthesis translate_off
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//assign chan_out[i].smart_chanel = (smart_chanel[i].requests[0]) ? smart_chanel_new[i] : take ss shifted smart;
|
//assign chan_out[i].smart_chanel = (smart_chanel[i].requests[0]) ? smart_chanel_new[i] : take ss shifted smart;
|
smart_chanel_check check (
|
smart_chanel_check check (
|
.flit_chanel(chan_out[i].flit_chanel),
|
.flit_chanel(chan_out[i].flit_chanel),
|
.smart_chanel(chan_out[i].smart_chanel),
|
.smart_chanel(chan_out[i].smart_chanel),
|
.reset(reset),
|
.reset(reset),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
// synthesis translate_on
|
// synthesis translate_on
|
|
|
assign smart_chanel_in[i] = chan_in[i].smart_chanel;
|
assign smart_chanel_in[i] = chan_in[i].smart_chanel;
|
assign chan_out[i].smart_chanel = smart_chanel_out[i];
|
|
|
|
//r2 demux
|
//r2 demux
|
// flit_in_wr demux
|
// flit_in_wr demux
|
always @(*) begin
|
always @(*) begin
|
|
chan_out[i].smart_chanel = smart_chanel_out[i];
|
|
chan_out[i].smart_chanel.flit_in_bypassed =smart_ctrl[i].smart_en & chan_in[i].flit_chanel.flit_wr ;
|
|
|
|
|
//mask only flit_wr if smart_en is asserted
|
//mask only flit_wr if smart_en is asserted
|
r2_chan_in[i] = chan_in[i].flit_chanel;
|
r2_chan_in[i] = chan_in[i].flit_chanel;
|
//can replace destport here and remove lk rout from internal router
|
//can replace destport here and remove lk rout from internal router
|
if (smart_ctrl[i].smart_en) r2_chan_in[i].flit_wr = 1'b0;
|
if (smart_ctrl[i].smart_en) r2_chan_in[i].flit_wr = 1'b0;
|
|
|
|
|
//send flit_in to straight out port. Replace lk destport in header flit
|
//send flit_in to straight out port. Replace lk destport in header flit
|
ss_flit_chanel[SS_PORT] = chan_in[i].flit_chanel;
|
ss_flit_chanel[SS_PORT] = chan_in[i].flit_chanel;
|
if(smart_ctrl[i].hdr_flit_req) ss_flit_chanel[SS_PORT].flit[DST_P_MSB : DST_P_LSB] = smart_ctrl[i].lk_destport;
|
if(smart_ctrl[i].hdr_flit_req) ss_flit_chanel[SS_PORT].flit[DST_P_MSB : DST_P_LSB] = smart_ctrl[i].lk_destport;
|
end
|
end
|
|
|
always @(*) begin
|
always @(*) begin
|
// mux out flit channel
|
// mux out flit channel
|
chan_out[i].flit_chanel = r2_chan_out[i];
|
chan_out[i].flit_chanel = r2_chan_out[i];
|
chan_out[i].flit_chanel.credit = credit_out[i] ;
|
chan_out[i].flit_chanel.credit = credit_out[i] ;
|
if(smart_ctrl[SS_PORT].smart_en) begin
|
if(smart_ctrl[SS_PORT].smart_en) begin
|
chan_out[i].flit_chanel.flit = ss_flit_chanel[i].flit;
|
chan_out[i].flit_chanel.flit = ss_flit_chanel[i].flit;
|
chan_out[i].flit_chanel.flit_wr = ss_flit_chanel[i].flit_wr;
|
chan_out[i].flit_chanel.flit_wr = ss_flit_chanel[i].flit_wr;
|
|
|
end
|
end
|
end
|
end
|
|
|
smart_credit_manage #(
|
smart_credit_manage #(
|
.V (V ),
|
.V (V ),
|
.B (B )
|
.B (B )
|
) smart_credit_manage (
|
) smart_credit_manage (
|
.credit_in (r2_chan_out[i].credit ),
|
.credit_in (r2_chan_out[i].credit ),
|
.smart_credit_in (smart_ctrl[i].credit_out ),
|
.smart_credit_in (smart_ctrl[i].credit_out ),
|
.credit_out ( credit_out[i] ),
|
.credit_out ( credit_out[i] ),
|
.reset (reset ),
|
.reset (reset ),
|
.clk (clk ));
|
.clk (clk ));
|
|
|
|
|
|
|
end //for
|
end //for
|
end//smart_en
|
end//smart_en
|
|
|
|
|
|
|
end else begin :no_smart
|
end else begin :no_smart
|
for (i=0;i
|
for (i=0;i
|
assign r2_chan_in[i] = chan_in[i].flit_chanel;
|
assign r2_chan_in[i] = chan_in[i].flit_chanel;
|
assign chan_out[i].flit_chanel = r2_chan_out[i];
|
assign chan_out[i].flit_chanel = r2_chan_out[i];
|
assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};
|
assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};
|
end//for
|
end//for
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
//`ifdef VERILATOR
|
//`ifdef VERILATOR
|
// logic nb_router_active [P-1 : 0] /*verilator public_flat_rd*/ ;
|
// logic nb_router_active [P-1 : 0] /*verilator public_flat_rd*/ ;
|
// logic router_is_ideal /*verilator public_flat_rd*/ ;
|
// logic router_is_ideal /*verilator public_flat_rd*/ ;
|
// logic not_ideal_next,not_ideal;
|
// logic not_ideal_next,not_ideal;
|
// integer ii,jj;
|
// integer ii,jj;
|
// always @ (*) begin
|
// always @ (*) begin
|
// router_is_ideal = 1'b1;
|
// router_is_ideal = 1'b1;
|
// not_ideal_next = 1'b0;
|
// not_ideal_next = 1'b0;
|
// for (ii=0; ii
|
// for (ii=0; ii
|
// nb_router_active[ii]= 1'b0;
|
// nb_router_active[ii]= 1'b0;
|
// if (chan_out[ii].flit_chanel.flit_wr) nb_router_active[ii]=1'b1;
|
// if (chan_out[ii].flit_chanel.flit_wr) nb_router_active[ii]=1'b1;
|
// if (chan_out[ii].flit_chanel.credit > {V{1'b0}} ) nb_router_active[ii]=1'b1;
|
// if (chan_out[ii].flit_chanel.credit > {V{1'b0}} ) nb_router_active[ii]=1'b1;
|
// if (chan_out[ii].smart_chanel.requests > {SMART_NUM{1'b0}} ) nb_router_active[ii]=1'b1;
|
// if (chan_out[ii].smart_chanel.requests > {SMART_NUM{1'b0}} ) nb_router_active[ii]=1'b1;
|
//
|
//
|
// for (jj=0; jj
|
// for (jj=0; jj
|
// //no active request is in any input queues
|
// //no active request is in any input queues
|
// if(ivc_info[ii][jj].ivc_req)begin
|
// if(ivc_info[ii][jj].ivc_req)begin
|
// router_is_ideal=1'b0;
|
// router_is_ideal=1'b0;
|
// not_ideal_next=1'b1;
|
// not_ideal_next=1'b1;
|
// end
|
// end
|
// end
|
// end
|
// //no output flit wr
|
// //no output flit wr
|
// if (r2_chan_out[ii].flit_wr) router_is_ideal=1'b0;
|
// if (r2_chan_out[ii].flit_wr) router_is_ideal=1'b0;
|
// end
|
// end
|
// if (not_ideal) router_is_ideal =1'b0; // delay one clock cycle if the input req exist in last clock cycle bot not on the current one
|
// if (not_ideal) router_is_ideal =1'b0; // delay one clock cycle if the input req exist in last clock cycle bot not on the current one
|
// end
|
// end
|
// register #( .W(1)) no_ideal_register (.in(not_ideal_next), .reset (reset), .clk(clk), .out (not_ideal));
|
// pronoc_register #( .W(1)) no_ideal_register (.in(not_ideal_next), .reset (reset), .clk(clk), .out (not_ideal));
|
//`endif
|
//`endif
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
module router_top_v //to be used as top module in veralator
|
module router_top_v //to be used as top module in veralator
|
import pronoc_pkg::*;
|
import pronoc_pkg::*;
|
|
|
# (
|
# (
|
parameter P = 5 // router port num
|
parameter P = 5 // router port num
|
)(
|
)(
|
current_r_addr,
|
current_r_addr,
|
|
current_r_id,
|
|
|
chan_in,
|
chan_in,
|
chan_out,
|
chan_out,
|
|
|
|
router_event,
|
|
|
clk,
|
clk,
|
reset
|
reset
|
|
|
);
|
);
|
|
|
|
|
|
|
input [RAw-1 : 0] current_r_addr;
|
input [RAw-1 : 0] current_r_addr;
|
|
input [31:0] current_r_id;
|
|
|
input smartflit_chanel_t chan_in [P-1 : 0];
|
input smartflit_chanel_t chan_in [P-1 : 0];
|
output smartflit_chanel_t chan_out [P-1 : 0];
|
output smartflit_chanel_t chan_out [P-1 : 0];
|
input reset,clk;
|
input reset,clk;
|
|
|
|
output router_event_t router_event [P-1 : 0];
|
|
|
|
|
router_top # (
|
router_top # (
|
.P(P)
|
.P(P)
|
)
|
)
|
router
|
router
|
(
|
(
|
|
.current_r_id(current_r_id),
|
.current_r_addr(current_r_addr),
|
.current_r_addr(current_r_addr),
|
.chan_in (chan_in),
|
.chan_in (chan_in),
|
.chan_out(chan_out),
|
.chan_out(chan_out),
|
|
.router_event(router_event),
|
.clk(clk),
|
.clk(clk),
|
.reset(reset)
|
.reset(reset)
|
);
|
);
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
