// synthesis translate_off
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// synthesis translate_off
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`timescale 1ns/1ns
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`include "pronoc_def.v"
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module synfull_top;
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module synfull_top;
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parameter NOC_ID=0;
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import pronoc_pkg::*;
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`NOC_CONF
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import dpi_int_pkg::*;
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import dpi_int_pkg::*;
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reg reset ,clk;
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reg reset ,clk;
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reg print_router_st;
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reg print_router_st;
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initial begin
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initial begin
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clk = 1'b0;
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clk = 1'b0;
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forever clk = #10 ~clk;
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forever clk = #10 ~clk;
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end
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end
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smartflit_chanel_t chan_in_all [NE-1 : 0];
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smartflit_chanel_t chan_in_all [NE-1 : 0];
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smartflit_chanel_t chan_out_all [NE-1 : 0];
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smartflit_chanel_t chan_out_all [NE-1 : 0];
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router_event_t router_event [NR-1 : 0] [MAX_P-1 : 0];
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router_event_t router_event [NR-1 : 0] [MAX_P-1 : 0];
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pck_injct_t pck_injct_in [NE-1 : 0];
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pck_injct_t pck_injct_in [NE-1 : 0];
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pck_injct_t _pck_injct_in [NE-1 : 0];
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pck_injct_t _pck_injct_in [NE-1 : 0];
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pck_injct_t pck_injct_out[NE-1 : 0];
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pck_injct_t pck_injct_out[NE-1 : 0];
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logic [NE-1 : 0] NE_ready_all ;
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logic [NE-1 : 0] NE_ready_all ;
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logic [NE-1 : 0] init_socket ;
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logic [NE-1 : 0] init_socket ;
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logic [NE-1 : 0] wakeup_synfull ;
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logic [NE-1 : 0] wakeup_synfull ;
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logic [NE-1 : 0] end_injection ;
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logic [NE-1 : 0] end_injection ;
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logic end_synfull ;
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logic end_synfull ;
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req_t [NE-1 : 0] synfull_pronoc_req_all ;
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req_t [NE-1 : 0] synfull_pronoc_req_all ;
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deliver_t [NE-1 : 0] pronoc_synfull_del_all ;
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deliver_t [NE-1 : 0] pronoc_synfull_del_all ;
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noc_top the_noc
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noc_top #(
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(
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.NOC_ID(NOC_ID)
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) the_noc (
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.reset(reset),
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.reset(reset),
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.clk(clk),
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.clk(clk),
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.chan_in_all(chan_in_all),
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.chan_in_all(chan_in_all),
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.chan_out_all(chan_out_all),
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.chan_out_all(chan_out_all),
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.router_event(router_event)
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.router_event(router_event)
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);
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);
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top_dpi_interface synfull (
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top_dpi_interface synfull (
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.clk_i(clk), .rst_i(reset),
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.clk_i(clk), .rst_i(reset),
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.init_i (init_socket[0] ),
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.init_i (init_socket[0] ),
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.startCom_i (wakeup_synfull[0] ),
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.startCom_i (wakeup_synfull[0] ),
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.pronoc_synfull_del_all_i (pronoc_synfull_del_all ),
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.pronoc_synfull_del_all_i (pronoc_synfull_del_all ),
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.synfull_pronoc_req_all_o (synfull_pronoc_req_all ),
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.synfull_pronoc_req_all_o (synfull_pronoc_req_all ),
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.NE_ready_all_i (NE_ready_all ),
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.NE_ready_all_i (NE_ready_all ),
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.endCom_o (end_injection[0] )
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.endCom_o (end_injection[0] )
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);
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);
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reg [NEw-1 : 0] dest_id [NE-1 : 0];
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reg [NEw-1 : 0] dest_id [NE-1 : 0];
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wire [NEw-1: 0] current_e_addr [NE-1 : 0];
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wire [NEw-1: 0] current_e_addr [NE-1 : 0];
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reg [63 : 0] total_sent_pck_count;
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reg [63 : 0] total_sent_pck_count;
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reg [63 : 0] total_sent_flit_count;
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reg [63 : 0] total_sent_flit_count;
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reg [63 : 0] total_rsv_pck_count;
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reg [63 : 0] total_rsv_pck_count;
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reg [63 : 0] total_rsv_flit_count;
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reg [63 : 0] total_rsv_flit_count;
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reg [63 : 0] total_queued_pck_count;
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reg [63 : 0] total_queued_pck_count;
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reg [63 : 0] clk_count;
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reg [63 : 0] clk_count;
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initial begin
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initial begin
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//print_parameter
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//print_parameter
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display_noc_parameters();
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display_noc_parameters();
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$display ("Simulation parameters-------------");
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$display ("Simulation parameters-------------");
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if(DEBUG_EN)
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if(DEBUG_EN)
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$display ("\tDebuging is enabled");
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$display ("\tDebuging is enabled");
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else
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else
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$display ("\tDebuging is disabled");
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$display ("\tDebuging is disabled");
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end//initial
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end//initial
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wire [31:0] fifo_id [NE-1 : 0];
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wire [31:0] fifo_id [NE-1 : 0];
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wire [PCK_SIZw-1 : 0] fifo_size [NE-1 :0];
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wire [PCK_SIZw-1 : 0] fifo_size [NE-1 :0];
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wire [NEw-1 : 0] fifo_dest [NE-1 : 0];
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wire [NEw-1 : 0] fifo_dest [NE-1 : 0];
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wire [NE-1 : 0] fifo_wr,fifo_rd ,fifo_full,fifo_not_empty;
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wire [NE-1 : 0] fifo_wr,fifo_rd ,fifo_full,fifo_not_empty;
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genvar i;
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genvar i;
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generate
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generate
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for(i=0; i< NE; i=i+1) begin
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for(i=0; i< NE; i=i+1) begin
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assign fifo_wr[i] =
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assign fifo_wr[i] =
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(pck_injct_out[i].ready == 1'b0 && synfull_pronoc_req_all[i].valid==1'b1) ||
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(pck_injct_out[i].ready == 1'b0 && synfull_pronoc_req_all[i].valid==1'b1) ||
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(fifo_not_empty[i]==1'b1 && synfull_pronoc_req_all[i].valid==1'b1);
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(fifo_not_empty[i]==1'b1 && synfull_pronoc_req_all[i].valid==1'b1);
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assign fifo_rd[i] =
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assign fifo_rd[i] =
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(pck_injct_out[i].ready == 1'b1 && fifo_not_empty[i]==1'b1 );
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(pck_injct_out[i].ready == 1'b1 && fifo_not_empty[i]==1'b1 );
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fwft_fifo_bram #(
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fwft_fifo_bram #(
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.DATA_WIDTH(32+PCK_SIZw+NEw),
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.DATA_WIDTH(32+PCK_SIZw+NEw),
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.MAX_DEPTH(1000000),
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.MAX_DEPTH(1000000),
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.IGNORE_SAME_LOC_RD_WR_WARNING("NO")
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.IGNORE_SAME_LOC_RD_WR_WARNING("NO")
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)
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)
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fifo
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fifo
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(
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(
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.din({synfull_pronoc_req_all[i].id,synfull_pronoc_req_all[i].size,synfull_pronoc_req_all[i].dest}), // Data in
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.din({synfull_pronoc_req_all[i].id,synfull_pronoc_req_all[i].size,synfull_pronoc_req_all[i].dest}), // Data in
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.wr_en(fifo_wr[i]), // Write enable
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.wr_en(fifo_wr[i]), // Write enable
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.rd_en(fifo_rd[i]), // Read the next word
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.rd_en(fifo_rd[i]), // Read the next word
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.dout({fifo_id[i],fifo_size[i],fifo_dest[i]}), // Data out
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.dout({fifo_id[i],fifo_size[i],fifo_dest[i]}), // Data out
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.full( fifo_full[i]),
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.full( fifo_full[i]),
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.nearly_full(),
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.nearly_full(),
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.recieve_more_than_0(fifo_not_empty[i]),
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.recieve_more_than_0(fifo_not_empty[i]),
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.recieve_more_than_1(),
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.recieve_more_than_1(),
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.reset(reset),
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.reset(reset),
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.clk (clk)
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.clk (clk)
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);
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);
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//from synfull
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//from synfull
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assign pck_injct_in[i].data = (fifo_not_empty[i])? fifo_id[i] : synfull_pronoc_req_all[i].id;
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assign pck_injct_in[i].data = (fifo_not_empty[i])? fifo_id[i] : synfull_pronoc_req_all[i].id;
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assign pck_injct_in[i].size = (fifo_not_empty[i])? fifo_size[i] : synfull_pronoc_req_all[i].size;
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assign pck_injct_in[i].size = (fifo_not_empty[i])? fifo_size[i] : synfull_pronoc_req_all[i].size;
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assign pck_injct_in[i].pck_wr = (fifo_not_empty[i])? fifo_rd[i] : ( synfull_pronoc_req_all[i].valid & pck_injct_out[i].ready == 1'b1);
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assign pck_injct_in[i].pck_wr = (fifo_not_empty[i])? fifo_rd[i] : ( synfull_pronoc_req_all[i].valid & pck_injct_out[i].ready == 1'b1);
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assign pck_injct_in[i].ready = 1'b1;
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assign pck_injct_in[i].ready = 1'b1;
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assign dest_id[i] =(fifo_not_empty[i])? fifo_dest[i] : synfull_pronoc_req_all[i].dest;
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assign dest_id[i] =(fifo_not_empty[i])? fifo_dest[i] : synfull_pronoc_req_all[i].dest;
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//to synfull
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//to synfull
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assign pronoc_synfull_del_all[i].id = pck_injct_out[i].data ;
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assign pronoc_synfull_del_all[i].id = pck_injct_out[i].data ;
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assign pronoc_synfull_del_all[i].valid = pck_injct_out[i].pck_wr ;
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assign pronoc_synfull_del_all[i].valid = pck_injct_out[i].pck_wr ;
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assign NE_ready_all[i] = 1'b1 ; //pck_injct_out[i].ready;
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assign NE_ready_all[i] = 1'b1 ; //pck_injct_out[i].ready;
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assign pck_injct_in[i].class_num = _pck_injct_in[i].class_num;
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assign pck_injct_in[i].class_num = _pck_injct_in[i].class_num;
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assign pck_injct_in[i].init_weight = _pck_injct_in[i].init_weight;
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assign pck_injct_in[i].init_weight = _pck_injct_in[i].init_weight;
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assign pck_injct_in[i].vc = _pck_injct_in[i].vc;
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assign pck_injct_in[i].vc = _pck_injct_in[i].vc;
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endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode1 ( .id(i[NEw-1 :0]), .code(current_e_addr[i]));
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endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode1 ( .id(i[NEw-1 :0]), .code(current_e_addr[i]));
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packet_injector pck_inj(
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packet_injector #(
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.NOC_ID(NOC_ID)
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) pck_inj(
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//general
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//general
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.current_e_addr(current_e_addr[i]),
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.current_e_addr(current_e_addr[i]),
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.reset(reset),
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.reset(reset),
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.clk(clk),
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.clk(clk),
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//noc port
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//noc port
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.chan_in(chan_out_all[i]),
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.chan_in(chan_out_all[i]),
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.chan_out(chan_in_all[i]),
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.chan_out(chan_in_all[i]),
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//control interafce
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//control interafce
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.pck_injct_in(pck_injct_in[i]),
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.pck_injct_in(pck_injct_in[i]),
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.pck_injct_out(pck_injct_out[i])
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.pck_injct_out(pck_injct_out[i])
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);
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);
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endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode2 ( .id(dest_id[i]), .code(pck_injct_in[i].endp_addr));
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endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw), .NE(NE)) encode2 ( .id(dest_id[i]), .code(pck_injct_in[i].endp_addr));
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reg [31:0]k;
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reg [31:0]k;
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initial begin
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initial begin
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`ifdef ACTIVE_LOW_RESET_MODE
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reset = 1'b0;
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`else
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reset = 1'b1;
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reset = 1'b1;
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`endif
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k=0;
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k=0;
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init_socket[i] = 1'b0;
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init_socket[i] = 1'b0;
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wakeup_synfull[i] = 1'b0;
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wakeup_synfull[i] = 1'b0;
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print_router_st=1'b0;
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print_router_st=1'b0;
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@(posedge clk) #1;
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@(posedge clk) #1;
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_pck_injct_in[i].class_num=0;
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_pck_injct_in[i].class_num=0;
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_pck_injct_in[i].init_weight=1;
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_pck_injct_in[i].init_weight=1;
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_pck_injct_in[i].vc=1;
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_pck_injct_in[i].vc=1;
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#100
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#100
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@(posedge clk) #1;
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@(posedge clk) #1;
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reset=1'b0;
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reset=~reset;
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#100
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#100
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init_socket[i] = 1'b1;
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init_socket[i] = 1'b1;
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@(posedge clk) #1;
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@(posedge clk) #1;
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init_socket[i] = 1'b0;
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init_socket[i] = 1'b0;
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#100
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#100
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wakeup_synfull[i] = 1'b1;
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wakeup_synfull[i] = 1'b1;
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@(posedge clk) #1;
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@(posedge clk) #1;
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while (!end_injection[0]) @(posedge clk) #1;
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while (!end_injection[0]) @(posedge clk) #1;
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// if(i==0) $display ( "All packet are sent. We wait for NoC to be ideal now");
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// if(i==0) $display ( "All packet are sent. We wait for NoC to be ideal now");
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// while (total_sent_pck_count != total_rsv_pck_count) @(posedge clk) #1;
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// while (total_sent_pck_count != total_rsv_pck_count) @(posedge clk) #1;
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print_router_st=1;
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print_router_st=1;
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#1
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#1
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$display ( "Statistics:");
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$display ( "Statistics:");
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$display ( "\t simulation clk count = %d", clk_count);
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$display ( "\t simulation clk count = %d", clk_count);
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$display ( "\t Total queued packets = %d",total_queued_pck_count);
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$display ( "\t Total queued packets = %d",total_queued_pck_count);
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$display ( "\t Total sent packets = %d", total_sent_pck_count);
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$display ( "\t Total sent packets = %d", total_sent_pck_count);
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$display ( "\t Total sent flits = %d", total_sent_flit_count);
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$display ( "\t Total sent flits = %d", total_sent_flit_count);
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$display ( "\t Total received packets = %d", total_rsv_pck_count);
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$display ( "\t Total received packets = %d", total_rsv_pck_count);
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$display ( "\t Total received flits = %d", total_rsv_flit_count);
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$display ( "\t Total received flits = %d", total_rsv_flit_count);
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$finish;
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$finish;
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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if(pck_injct_out[i].pck_wr) begin
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if(pck_injct_out[i].pck_wr) begin
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$display ("%t:pck_inj(%d) got a packet: source=%d, size=%d, data=%h",$time,i,
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$display ("%t:pck_inj(%d) got a packet: source=%d, size=%d, data=%h",$time,i,
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pck_injct_out[i].endp_addr,pck_injct_out[i].size,pck_injct_out[i].data);
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pck_injct_out[i].endp_addr,pck_injct_out[i].size,pck_injct_out[i].data);
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end
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end
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end
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end
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end//for
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end//for
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endgenerate
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endgenerate
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integer k;
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integer k;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if(reset) begin
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if(`pronoc_reset) begin
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clk_count =0;
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clk_count =0;
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total_sent_pck_count =0;
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total_sent_pck_count =0;
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total_sent_flit_count=0;
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total_sent_flit_count=0;
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total_rsv_pck_count =0;
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total_rsv_pck_count =0;
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total_rsv_flit_count =0;
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total_rsv_flit_count =0;
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total_queued_pck_count = 0;
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total_queued_pck_count = 0;
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end else begin
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end else begin
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clk_count++;
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clk_count++;
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for(k=0; k< NE; k=k+1) begin : endpoints
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for(k=0; k< NE; k=k+1) begin : endpoints
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if(pck_injct_out[k].pck_wr) begin
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if(pck_injct_out[k].pck_wr) begin
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total_rsv_pck_count++;
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total_rsv_pck_count++;
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total_rsv_flit_count+=pck_injct_out[k].size;
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total_rsv_flit_count+=pck_injct_out[k].size;
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end
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end
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if(pck_injct_in[k].pck_wr) begin
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if(pck_injct_in[k].pck_wr) begin
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total_sent_pck_count++;
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total_sent_pck_count++;
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total_sent_flit_count+=pck_injct_in[k].size;
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total_sent_flit_count+=pck_injct_in[k].size;
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end
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end
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if(synfull_pronoc_req_all[k].valid) begin
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if(synfull_pronoc_req_all[k].valid) begin
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total_queued_pck_count++;
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total_queued_pck_count++;
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end
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end
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end
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end
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end
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end
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end
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end
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routers_statistic_collector router_stat(
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routers_statistic_collector # (
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.NOC_ID(NOC_ID)
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) router_stat (
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.reset(reset),
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.reset(reset),
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.clk(clk),
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.clk(clk),
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.router_event(router_event),
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.router_event(router_event),
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.print(print_router_st)
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.print(print_router_st)
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);
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);
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endmodule
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endmodule
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// synthesis translate_on
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// synthesis translate_on
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