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/**************************************************************************
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/**************************************************************************
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** WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
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** WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
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** OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
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** OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
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****************************************************************************/
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****************************************************************************/
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/**********************************************************************
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/**********************************************************************
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** File: /home/alireza/work/git/hca_git/ProNoC/mpsoc/rtl/src_topolgy/custom1/Tcustom1Rcustom_conventional_routing.v
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** File: /home/alireza/work/git/hca_git/ProNoC/mpsoc/rtl/src_topolgy/custom1/Tcustom1Rcustom_conventional_routing.v
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**
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**
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** Copyright (C) 2014-2019 Alireza Monemi
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** Copyright (C) 2014-2021 Alireza Monemi
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**
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**
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** This file is part of ProNoC 1.9.1
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** This file is part of ProNoC 2.0.0
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**
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**
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** you can redistribute it and/or modify it under the terms of the GNU
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** you can redistribute it and/or modify it under the terms of the GNU
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** Lesser General Public License as published by the Free Software Foundation,
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** Lesser General Public License as published by the Free Software Foundation,
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** either version 2 of the License, or (at your option) any later version.
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** either version 2 of the License, or (at your option) any later version.
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**
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**
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
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** License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
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******************************************************************************/
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******************************************************************************/
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module Tcustom1Rcustom_conventional_routing #(
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module Tcustom1Rcustom_conventional_routing #(
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parameter RAw = 3,
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parameter RAw = 3,
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parameter EAw = 3,
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parameter EAw = 3,
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parameter DSTPw=4
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parameter DSTPw=4
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)
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)
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(
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(
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dest_e_addr,
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dest_e_addr,
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src_e_addr,
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src_e_addr,
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destport
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destport
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);
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);
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input [EAw-1 :0] dest_e_addr;
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input [EAw-1 :0] dest_e_addr;
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input [EAw-1 :0] src_e_addr;
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input [EAw-1 :0] src_e_addr;
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output reg [DSTPw-1 :0] destport;
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output reg [DSTPw-1 :0] destport;
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always@(*)begin
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always@(*)begin
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destport=0;
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destport=0;
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case(src_e_addr) //source address of each individual NI is fixed. So this CASE will be optimized by the synthesizer for each endpoint.
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case(src_e_addr) //source address of each individual NI is fixed. So this CASE will be optimized by the synthesizer for each endpoint.
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0: begin
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0: begin
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case(dest_e_addr)
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case(dest_e_addr)
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1,2,3,7,10: begin
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1,2,3,7,10: begin
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destport= 1;
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destport= 1;
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end
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end
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4,5,6,8,9,11,12,13,14,15: begin
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4,5,6,8,9,11,12,13,14,15: begin
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destport= 2;
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destport= 2;
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end
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end
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default: begin
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default: begin
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destport= {DSTPw{1'bX}};
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destport= {DSTPw{1'bX}};
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end
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end
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endcase
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endcase
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end//0
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end//0
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1: begin
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1: begin
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case(dest_e_addr)
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case(dest_e_addr)
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0,4,7,8,9,10,12,15: begin
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0,4,7,8,9,10,12,15: begin
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destport= 1;
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destport= 1;
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end
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end
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2,3,5,6,11,13,14: begin
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2,3,5,6,11,13,14: begin
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destport= 2;
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destport= 2;
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end
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end
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default: begin
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default: begin
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destport= {DSTPw{1'bX}};
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destport= {DSTPw{1'bX}};
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end
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end
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endcase
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endcase
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end//1
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end//1
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2: begin
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2: begin
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case(dest_e_addr)
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case(dest_e_addr)
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3,4,5,6,8,11,13,14,15: begin
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3,4,5,6,8,11,13,14,15: begin
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destport= 1;
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destport= 1;
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end
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end
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0,1,7,9,10,12: begin
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0,1,7,9,10,12: begin
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destport= 2;
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destport= 2;
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end
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end
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default: begin
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default: begin
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destport= {DSTPw{1'bX}};
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destport= {DSTPw{1'bX}};
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end
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end
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endcase
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endcase
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end//2
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end//2
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3: begin
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3: begin
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case(dest_e_addr)
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case(dest_e_addr)
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2,10,11,12: begin
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2,10,11,12: begin
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destport= 1;
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destport= 1;
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end
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end
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0,1,4,5,6,7,8,9,13,14,15: begin
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0,1,4,5,6,7,8,9,13,14,15: begin
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destport= 2;
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destport= 2;
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end
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end
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default: begin
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default: begin
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destport= {DSTPw{1'bX}};
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destport= {DSTPw{1'bX}};
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end
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end
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endcase
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endcase
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end//3
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end//3
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4: begin
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4: begin
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case(dest_e_addr)
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case(dest_e_addr)
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1,6,7,8,10,13: begin
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1,6,7,8,10,13: begin
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destport= 1;
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destport= 1;
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end
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end
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3: begin
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3: begin
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destport= 2;
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destport= 2;
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end
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end
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0,2,5,9,11,12,14,15: begin
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0,2,5,9,11,12,14,15: begin
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destport= 3;
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destport= 3;
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end
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end
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default: begin
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default: begin
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destport= {DSTPw{1'bX}};
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destport= {DSTPw{1'bX}};
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end
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end
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endcase
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endcase
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end//4
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end//4
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5: begin
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5: begin
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case(dest_e_addr)
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case(dest_e_addr)
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1,7,8,10,11,12,15: begin
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1,7,8,10,11,12,15: begin
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destport= 1;
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destport= 1;
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end
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end
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2,3,4,6,13,14: begin
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2,3,4,6,13,14: begin
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destport= 2;
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destport= 2;
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end
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end
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0,9: begin
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0,9: begin
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destport= 3;
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destport= 3;
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end
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end
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default: begin
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default: begin
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destport= {DSTPw{1'bX}};
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destport= {DSTPw{1'bX}};
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end
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end
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endcase
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endcase
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end//5
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end//5
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6: begin
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6: begin
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case(dest_e_addr)
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case(dest_e_addr)
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3,4,13: begin
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3,4,13: begin
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destport= 1;
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destport= 1;
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end
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end
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0,1,2,5,7,8,9,10,11,12,14,15: begin
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0,1,2,5,7,8,9,10,11,12,14,15: begin
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destport= 2;
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destport= 2;
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end
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end
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default: begin
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default: begin
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destport= {DSTPw{1'bX}};
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destport= {DSTPw{1'bX}};
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end
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end
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endcase
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endcase
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end//6
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end//6
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7: begin
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7: begin
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case(dest_e_addr)
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case(dest_e_addr)
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2,3,4,5,6,8,9,11,12,13,14,15: begin
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2,3,4,5,6,8,9,11,12,13,14,15: begin
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destport= 1;
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destport= 1;
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end
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end
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0,10: begin
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0,10: begin
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destport= 2;
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destport= 2;
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end
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end
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1: begin
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1: begin
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destport= 3;
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destport= 3;
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end
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end
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default: begin
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default: begin
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destport= {DSTPw{1'bX}};
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destport= {DSTPw{1'bX}};
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end
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end
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endcase
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endcase
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end//7
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end//7
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8: begin
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8: begin
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case(dest_e_addr)
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case(dest_e_addr)
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0,4,5,9,10,12: begin
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0,4,5,9,10,12: begin
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destport= 1;
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destport= 1;
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end
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end
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2,3,6,11,13,14,15: begin
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2,3,6,11,13,14,15: begin
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destport= 2;
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destport= 2;
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end
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end
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1,7: begin
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1,7: begin
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destport= 3;
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destport= 3;
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end
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end
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default: begin
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default: begin
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destport= {DSTPw{1'bX}};
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destport= {DSTPw{1'bX}};
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end
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end
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endcase
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endcase
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end//8
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end//8
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9: begin
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9: begin
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case(dest_e_addr)
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case(dest_e_addr)
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1,7,8,10,12: begin
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1,7,8,10,12: begin
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destport= 1;
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destport= 1;
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end
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end
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2,3,4,5,6,11,13,14,15: begin
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2,3,4,5,6,11,13,14,15: begin
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destport= 2;
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destport= 2;
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end
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end
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0: begin
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0: begin
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destport= 3;
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destport= 3;
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end
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end
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default: begin
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default: begin
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destport= {DSTPw{1'bX}};
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destport= {DSTPw{1'bX}};
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end
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end
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endcase
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endcase
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end//9
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end//9
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10: begin
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10: begin
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case(dest_e_addr)
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case(dest_e_addr)
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2,3,4,5,6,8,9,11,12,13,14,15: begin
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2,3,4,5,6,8,9,11,12,13,14,15: begin
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destport= 1;
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destport= 1;
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end
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end
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1,7: begin
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1,7: begin
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destport= 2;
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destport= 2;
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end
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end
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0: begin
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0: begin
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destport= 3;
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destport= 3;
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end
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end
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default: begin
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default: begin
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destport= {DSTPw{1'bX}};
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destport= {DSTPw{1'bX}};
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end
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end
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endcase
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endcase
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end//10
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end//10
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11: begin
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11: begin
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case(dest_e_addr)
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case(dest_e_addr)
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0,1,4,5,6,7,8,9,10,12,13,14,15: begin
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0,1,4,5,6,7,8,9,10,12,13,14,15: begin
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destport= 1;
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destport= 1;
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end
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end
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2: begin
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2: begin
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destport= 2;
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destport= 2;
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end
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end
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3: begin
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3: begin
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destport= 3;
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destport= 3;
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end
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end
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default: begin
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default: begin
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destport= {DSTPw{1'bX}};
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destport= {DSTPw{1'bX}};
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end
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end
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endcase
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endcase
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end//11
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end//11
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12: begin
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12: begin
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case(dest_e_addr)
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case(dest_e_addr)
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2,3,4,5,6,11,13,14,15: begin
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2,3,4,5,6,11,13,14,15: begin
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destport= 1;
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destport= 1;
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end
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end
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0,9: begin
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0,9: begin
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destport= 2;
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destport= 2;
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end
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end
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1,7,10: begin
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1,7,10: begin
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destport= 3;
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destport= 3;
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end
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end
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8: begin
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8: begin
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destport= 4;
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destport= 4;
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end
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end
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default: begin
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default: begin
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destport= {DSTPw{1'bX}};
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destport= {DSTPw{1'bX}};
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end
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end
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endcase
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endcase
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end//12
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end//12
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13: begin
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13: begin
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case(dest_e_addr)
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case(dest_e_addr)
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3,4: begin
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3,4: begin
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destport= 2;
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destport= 2;
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end
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end
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6: begin
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6: begin
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destport= 3;
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destport= 3;
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end
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end
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0,1,2,5,7,8,9,10,11,12,14,15: begin
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0,1,2,5,7,8,9,10,11,12,14,15: begin
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destport= 4;
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destport= 4;
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end
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end
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default: begin
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default: begin
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destport= {DSTPw{1'bX}};
|
destport= {DSTPw{1'bX}};
|
end
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end
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endcase
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endcase
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end//13
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end//13
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14: begin
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14: begin
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case(dest_e_addr)
|
case(dest_e_addr)
|
5,9,12,15: begin
|
5,9,12,15: begin
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destport= 1;
|
destport= 1;
|
end
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end
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3,4,6,13: begin
|
3,4,6,13: begin
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destport= 2;
|
destport= 2;
|
end
|
end
|
0,1,7,8,10: begin
|
0,1,7,8,10: begin
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destport= 3;
|
destport= 3;
|
end
|
end
|
2,11: begin
|
2,11: begin
|
destport= 4;
|
destport= 4;
|
end
|
end
|
|
|
default: begin
|
default: begin
|
destport= {DSTPw{1'bX}};
|
destport= {DSTPw{1'bX}};
|
end
|
end
|
endcase
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endcase
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end//14
|
end//14
|
15: begin
|
15: begin
|
case(dest_e_addr)
|
case(dest_e_addr)
|
1,7,8,10,12: begin
|
1,7,8,10,12: begin
|
destport= 1;
|
destport= 1;
|
end
|
end
|
2,11,14: begin
|
2,11,14: begin
|
destport= 2;
|
destport= 2;
|
end
|
end
|
3,4,6,13: begin
|
3,4,6,13: begin
|
destport= 3;
|
destport= 3;
|
end
|
end
|
0,5,9: begin
|
0,5,9: begin
|
destport= 4;
|
destport= 4;
|
end
|
end
|
|
|
default: begin
|
default: begin
|
destport= {DSTPw{1'bX}};
|
destport= {DSTPw{1'bX}};
|
end
|
end
|
endcase
|
endcase
|
end//15
|
end//15
|
|
|
default: begin
|
default: begin
|
destport= {DSTPw{1'bX}};
|
destport= {DSTPw{1'bX}};
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
