module vjtag_wb #(
|
module vjtag_wb #(
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parameter VJTAG_INDEX=126,
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parameter VJTAG_INDEX=126,
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parameter DW=32,
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parameter DW=32,
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parameter AW=32,
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parameter AW=32,
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parameter SW=32,
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parameter SW=32,
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|
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//wishbone port parameters
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//wishbone port parameters
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parameter S_Aw = 7,
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parameter S_Aw = 7,
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parameter M_Aw = 32,
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parameter M_Aw = 32,
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parameter TAGw = 3,
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parameter TAGw = 3,
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parameter SELw = 4
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parameter SELw = 4
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|
|
|
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)(
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)(
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clk,
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clk,
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reset,
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reset,
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status_i,
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status_i,
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|
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//wishbone master interface signals
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//wishbone master interface signals
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m_sel_o,
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m_sel_o,
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m_dat_o,
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m_dat_o,
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m_addr_o,
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m_addr_o,
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m_cti_o,
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m_cti_o,
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m_stb_o,
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m_stb_o,
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m_cyc_o,
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m_cyc_o,
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m_we_o,
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m_we_o,
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m_dat_i,
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m_dat_i,
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m_ack_i
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m_ack_i
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|
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);
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);
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//IO declaration
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//IO declaration
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input reset,clk;
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input reset,clk;
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input [SW-1 : 0] status_i;
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input [SW-1 : 0] status_i;
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|
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//wishbone master interface signals
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//wishbone master interface signals
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output [SELw-1 : 0] m_sel_o;
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output [SELw-1 : 0] m_sel_o;
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output [DW-1 : 0] m_dat_o;
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output [DW-1 : 0] m_dat_o;
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output [M_Aw-1 : 0] m_addr_o;
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output [M_Aw-1 : 0] m_addr_o;
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output [TAGw-1 : 0] m_cti_o;
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output [TAGw-1 : 0] m_cti_o;
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output m_stb_o;
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output m_stb_o;
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output m_cyc_o;
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output m_cyc_o;
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output m_we_o;
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output m_we_o;
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input [DW-1 : 0] m_dat_i;
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input [DW-1 : 0] m_dat_i;
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input m_ack_i;
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input m_ack_i;
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localparam STATE_NUM=3,
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localparam STATE_NUM=3,
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IDEAL =1,
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IDEAL =1,
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WB_WR_DATA=2,
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WB_WR_DATA=2,
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WB_RD_DATA=4;
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WB_RD_DATA=4;
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reg [STATE_NUM-1 : 0] ps,ns;
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reg [STATE_NUM-1 : 0] ps,ns;
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|
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wire [DW-1 :0] data_out, data_in;
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wire [DW-1 :0] data_out, data_in;
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wire wb_wr_addr_en, wb_wr_data_en, wb_rd_data_en;
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wire wb_wr_addr_en, wb_wr_data_en, wb_rd_data_en;
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reg wr_mem_en, rd_mem_en, wb_cap_rd;
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reg wr_mem_en, rd_mem_en, wb_cap_rd;
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|
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reg [AW-1 : 0] wb_addr,wb_addr_next;
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reg [AW-1 : 0] wb_addr,wb_addr_next;
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reg [DW-1 : 0] wb_wr_data,wb_rd_data;
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reg [DW-1 : 0] wb_wr_data,wb_rd_data;
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reg wb_addr_inc;
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reg wb_addr_inc;
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assign m_cti_o = 3'b000;
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assign m_cti_o = 3'b000;
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assign m_sel_o = 4'b1111;
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assign m_sel_o = 4'b1111;
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assign m_cyc_o = m_stb_o;
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assign m_cyc_o = m_stb_o;
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assign m_stb_o = wr_mem_en | rd_mem_en;
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assign m_stb_o = wr_mem_en | rd_mem_en;
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assign m_we_o = wr_mem_en;
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assign m_we_o = wr_mem_en;
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assign m_dat_o = wb_wr_data;
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assign m_dat_o = wb_wr_data;
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assign m_addr_o = wb_addr;
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assign m_addr_o = wb_addr;
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assign data_in = wb_rd_data;
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assign data_in = wb_rd_data;
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//vjtag vjtag signals declaration
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//vjtag vjtag signals declaration
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localparam VJ_DW= (DW > AW)? DW : AW;
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localparam VJ_DW= (DW > AW)? DW : AW;
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vjtag_ctrl #(
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vjtag_ctrl #(
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.DW(VJ_DW),
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.DW(VJ_DW),
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.VJTAG_INDEX(VJTAG_INDEX),
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.VJTAG_INDEX(VJTAG_INDEX),
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.STW(SW)
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.STW(SW)
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)
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)
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vjtag_ctrl_inst
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vjtag_ctrl_inst
|
(
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(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.data_out(data_out),
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.data_out(data_out),
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.data_in(data_in),
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.data_in(data_in),
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.wb_wr_addr_en(wb_wr_addr_en),
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.wb_wr_addr_en(wb_wr_addr_en),
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.wb_wr_data_en(wb_wr_data_en),
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.wb_wr_data_en(wb_wr_data_en),
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.wb_rd_data_en(wb_rd_data_en),
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.wb_rd_data_en(wb_rd_data_en),
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.status_i(status_i)
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.status_i(status_i)
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);
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);
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`ifdef SYNC_RESET_MODE
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always @ (posedge clk )begin
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`else
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always @(posedge clk or posedge reset) begin
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always @(posedge clk or posedge reset) begin
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`endif
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if(reset) begin
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if(reset) begin
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wb_addr <= {AW{1'b0}};
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wb_addr <= {AW{1'b0}};
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wb_wr_data <= {DW{1'b0}};
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wb_wr_data <= {DW{1'b0}};
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ps <= IDEAL;
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ps <= IDEAL;
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end else begin
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end else begin
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wb_addr <= wb_addr_next;
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wb_addr <= wb_addr_next;
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ps <= ns;
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ps <= ns;
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if(wb_wr_data_en) wb_wr_data <= data_out;
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if(wb_wr_data_en) wb_wr_data <= data_out;
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if(wb_cap_rd) wb_rd_data <= m_dat_i;
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if(wb_cap_rd) wb_rd_data <= m_dat_i;
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end
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end
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end
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end
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always @(*)begin
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always @(*)begin
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wb_addr_next= wb_addr;
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wb_addr_next= wb_addr;
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if(wb_wr_addr_en) wb_addr_next = data_out [AW-1 : 0];
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if(wb_wr_addr_en) wb_addr_next = data_out [AW-1 : 0];
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else if (wb_addr_inc) wb_addr_next = wb_addr +1'b1;
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else if (wb_addr_inc) wb_addr_next = wb_addr +1'b1;
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end
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end
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always @(*)begin
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always @(*)begin
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ns=ps;
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ns=ps;
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wr_mem_en =1'b0;
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wr_mem_en =1'b0;
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rd_mem_en =1'b0;
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rd_mem_en =1'b0;
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wb_addr_inc=1'b0;
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wb_addr_inc=1'b0;
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wb_cap_rd=1'b0;
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wb_cap_rd=1'b0;
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case(ps)
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case(ps)
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IDEAL : begin
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IDEAL : begin
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if(wb_wr_data_en) ns= WB_WR_DATA;
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if(wb_wr_data_en) ns= WB_WR_DATA;
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if(wb_rd_data_en) ns= WB_RD_DATA;
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if(wb_rd_data_en) ns= WB_RD_DATA;
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end
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end
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WB_WR_DATA: begin
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WB_WR_DATA: begin
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wr_mem_en =1'b1;
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wr_mem_en =1'b1;
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if(m_ack_i) begin
|
if(m_ack_i) begin
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ns=IDEAL;
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ns=IDEAL;
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wb_addr_inc=1'b1;
|
wb_addr_inc=1'b1;
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end
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end
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end
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end
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WB_RD_DATA: begin
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WB_RD_DATA: begin
|
rd_mem_en =1'b1;
|
rd_mem_en =1'b1;
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if(m_ack_i) begin
|
if(m_ack_i) begin
|
wb_cap_rd=1'b1;
|
wb_cap_rd=1'b1;
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ns=IDEAL;
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ns=IDEAL;
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//wb_addr_inc=1'b1;
|
//wb_addr_inc=1'b1;
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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//assign led={wb_addr[7:0], wb_wr_data[7:0]};
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//assign led={wb_addr[7:0], wb_wr_data[7:0]};
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|
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endmodule
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endmodule
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|
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module vjtag_ctrl #(
|
module vjtag_ctrl #(
|
parameter DW=32,
|
parameter DW=32,
|
parameter STW=2, // status width <= DW
|
parameter STW=2, // status width <= DW
|
parameter VJTAG_INDEX=126
|
parameter VJTAG_INDEX=126
|
|
|
)(
|
)(
|
clk,
|
clk,
|
reset,
|
reset,
|
data_out,
|
data_out,
|
data_in,
|
data_in,
|
status_i,
|
status_i,
|
wb_wr_addr_en,
|
wb_wr_addr_en,
|
wb_wr_data_en,
|
wb_wr_data_en,
|
wb_rd_data_en
|
wb_rd_data_en
|
);
|
);
|
|
|
//IO declaration
|
//IO declaration
|
input reset,clk;
|
input reset,clk;
|
output [DW-1 :0] data_out;
|
output [DW-1 :0] data_out;
|
input [DW-1 :0] data_in;
|
input [DW-1 :0] data_in;
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input [STW-1 :0] status_i;
|
input [STW-1 :0] status_i;
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output wb_wr_addr_en, wb_wr_data_en, wb_rd_data_en;
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output wb_wr_addr_en, wb_wr_data_en, wb_rd_data_en;
|
|
|
|
|
//vjtag vjtag signals declaration
|
//vjtag vjtag signals declaration
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wire [2:0] ir_out , ir_in;
|
wire [2:0] ir_out , ir_in;
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wire tdo, tck, tdi;
|
wire tdo, tck, tdi;
|
wire cdr ,cir,e1dr,e2dr,pdr,sdr,udr,uir;
|
wire cdr ,cir,e1dr,e2dr,pdr,sdr,udr,uir;
|
|
|
|
|
vjtag #(
|
vjtag #(
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.VJTAG_INDEX(VJTAG_INDEX)
|
.VJTAG_INDEX(VJTAG_INDEX)
|
)
|
)
|
vjtag_inst (
|
vjtag_inst (
|
.ir_out ( ir_out ),
|
.ir_out ( ir_out ),
|
.tdo ( tdo ),
|
.tdo ( tdo ),
|
.ir_in ( ir_in ),
|
.ir_in ( ir_in ),
|
.tck ( tck ),
|
.tck ( tck ),
|
.tdi ( tdi ),
|
.tdi ( tdi ),
|
.virtual_state_cdr ( cdr ),
|
.virtual_state_cdr ( cdr ),
|
.virtual_state_cir ( cir ),
|
.virtual_state_cir ( cir ),
|
.virtual_state_e1dr ( e1dr ),
|
.virtual_state_e1dr ( e1dr ),
|
.virtual_state_e2dr ( e2dr ),
|
.virtual_state_e2dr ( e2dr ),
|
.virtual_state_pdr ( pdr ),
|
.virtual_state_pdr ( pdr ),
|
.virtual_state_sdr ( sdr ),
|
.virtual_state_sdr ( sdr ),
|
.virtual_state_udr ( udr ),
|
.virtual_state_udr ( udr ),
|
.virtual_state_uir ( uir )
|
.virtual_state_uir ( uir )
|
);
|
);
|
|
|
|
|
// IR states
|
// IR states
|
localparam [2:0] UPDATE_WB_ADDR = 3'b111,
|
localparam [2:0] UPDATE_WB_ADDR = 3'b111,
|
UPDATE_WB_WR_DATA = 3'b110,
|
UPDATE_WB_WR_DATA = 3'b110,
|
UPDATE_WB_RD_DATA = 3'b101,
|
UPDATE_WB_RD_DATA = 3'b101,
|
RD_STATUS =3'b100,
|
RD_STATUS =3'b100,
|
BYPASS = 3'b000;
|
BYPASS = 3'b000;
|
|
|
|
|
// internal registers
|
// internal registers
|
reg [2:0] ir;
|
reg [2:0] ir;
|
reg bypass_reg;
|
reg bypass_reg;
|
reg [DW-1 : 0] shift_buffer,shift_buffer_next;
|
reg [DW-1 : 0] shift_buffer,shift_buffer_next;
|
reg cdr_delayed,sdr_delayed;
|
reg cdr_delayed,sdr_delayed;
|
|
|
|
|
|
|
/*
|
/*
|
always @(negedge tck)
|
always @(negedge tck)
|
begin
|
begin
|
// Delay the CDR signal by one half clock cycle
|
// Delay the CDR signal by one half clock cycle
|
cdr_delayed = cdr;
|
cdr_delayed = cdr;
|
sdr_delayed = sdr;
|
sdr_delayed = sdr;
|
end
|
end
|
*/
|
*/
|
|
|
assign ir_out = ir_in; // Just pass the IR out
|
assign ir_out = ir_in; // Just pass the IR out
|
assign tdo = (ir == BYPASS) ? bypass_reg : shift_buffer[0];
|
assign tdo = (ir == BYPASS) ? bypass_reg : shift_buffer[0];
|
assign data_out = shift_buffer;
|
assign data_out = shift_buffer;
|
|
|
|
|
|
`ifdef SYNC_RESET_MODE
|
|
always @ (posedge tck )begin
|
|
`else
|
|
always @ (posedge tck or posedge reset)begin
|
|
`endif
|
|
|
|
|
always @(posedge tck or posedge reset)
|
|
begin
|
|
if (reset)begin
|
if (reset)begin
|
ir <= 3'b000;
|
ir <= 3'b000;
|
bypass_reg<=1'b0;
|
bypass_reg<=1'b0;
|
shift_buffer<={DW{1'b0}};
|
shift_buffer<={DW{1'b0}};
|
|
|
end else begin
|
end else begin
|
if( uir ) ir <= ir_in; // Capture the instruction provided
|
if( uir ) ir <= ir_in; // Capture the instruction provided
|
bypass_reg <= tdi;
|
bypass_reg <= tdi;
|
shift_buffer<=shift_buffer_next;
|
shift_buffer<=shift_buffer_next;
|
|
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
always @ (*)begin
|
always @ (*)begin
|
shift_buffer_next=shift_buffer;
|
shift_buffer_next=shift_buffer;
|
|
|
if( sdr ) shift_buffer_next={tdi,shift_buffer[DW-1:1]};// shift buffer
|
if( sdr ) shift_buffer_next={tdi,shift_buffer[DW-1:1]};// shift buffer
|
case(ir)
|
case(ir)
|
RD_STATUS:begin
|
RD_STATUS:begin
|
if( cdr ) shift_buffer_next[STW-1 : 0] = status_i;
|
if( cdr ) shift_buffer_next[STW-1 : 0] = status_i;
|
end
|
end
|
default: begin
|
default: begin
|
if( cdr ) shift_buffer_next = data_in;
|
if( cdr ) shift_buffer_next = data_in;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
|
|
reg wb_wr_addr1, wb_wr_data1, wb_rd_data1;
|
reg wb_wr_addr1, wb_wr_data1, wb_rd_data1;
|
//always @(posedge tck or posedge reset)
|
//always @(posedge tck or posedge reset)
|
always @(*)
|
always @(*)
|
begin
|
begin
|
//if( reset ) begin
|
//if( reset ) begin
|
// wb_wr_addr1<=1'b0;
|
// wb_wr_addr1<=1'b0;
|
// wb_wr_data1<=1'b0;
|
// wb_wr_data1<=1'b0;
|
//end else begin
|
//end else begin
|
wb_wr_addr1=(ir== UPDATE_WB_ADDR || ir== UPDATE_WB_RD_DATA) & udr;
|
wb_wr_addr1=(ir== UPDATE_WB_ADDR || ir== UPDATE_WB_RD_DATA) & udr;
|
wb_wr_data1=(ir== UPDATE_WB_WR_DATA && udr );
|
wb_wr_data1=(ir== UPDATE_WB_WR_DATA && udr );
|
wb_rd_data1=(ir==UPDATE_WB_RD_DATA && cdr);
|
wb_rd_data1=(ir==UPDATE_WB_RD_DATA && cdr);
|
//end
|
//end
|
end
|
end
|
|
|
reg wb_wr_addr2, wb_wr_data2, wb_rd_data2;
|
reg wb_wr_addr2, wb_wr_data2, wb_rd_data2;
|
reg wb_wr_addr3, wb_wr_data3, wb_rd_data3;
|
reg wb_wr_addr3, wb_wr_data3, wb_rd_data3;
|
|
|
always @(posedge clk or posedge reset)
|
`ifdef SYNC_RESET_MODE
|
begin
|
always @ (posedge clk )begin
|
|
`else
|
|
always @ (posedge clk or posedge reset)begin
|
|
`endif
|
|
|
if( reset ) begin
|
if( reset ) begin
|
wb_wr_addr2<=1'b0;
|
wb_wr_addr2<=1'b0;
|
wb_wr_data2<=1'b0;
|
wb_wr_data2<=1'b0;
|
wb_wr_addr3<=1'b0;
|
wb_wr_addr3<=1'b0;
|
wb_wr_data3<=1'b0;
|
wb_wr_data3<=1'b0;
|
wb_rd_data2<=1'b0;
|
wb_rd_data2<=1'b0;
|
wb_rd_data3<=1'b0;
|
wb_rd_data3<=1'b0;
|
end else begin
|
end else begin
|
wb_wr_addr2<=wb_wr_addr1;
|
wb_wr_addr2<=wb_wr_addr1;
|
wb_wr_data2<=wb_wr_data1;
|
wb_wr_data2<=wb_wr_data1;
|
wb_wr_addr3<=wb_wr_addr2;
|
wb_wr_addr3<=wb_wr_addr2;
|
wb_wr_data3<=wb_wr_data2;
|
wb_wr_data3<=wb_wr_data2;
|
wb_rd_data2<=wb_rd_data1;
|
wb_rd_data2<=wb_rd_data1;
|
wb_rd_data3<=wb_rd_data2;
|
wb_rd_data3<=wb_rd_data2;
|
end
|
end
|
end
|
end
|
|
|
assign wb_wr_addr_en =(wb_wr_addr2 & ~wb_wr_addr3);
|
assign wb_wr_addr_en =(wb_wr_addr2 & ~wb_wr_addr3);
|
assign wb_wr_data_en =(wb_wr_data2 & ~wb_wr_data3);
|
assign wb_wr_data_en =(wb_wr_data2 & ~wb_wr_data3);
|
assign wb_rd_data_en =(wb_rd_data2 & ~wb_rd_data3);
|
assign wb_rd_data_en =(wb_rd_data2 & ~wb_rd_data3);
|
endmodule
|
endmodule
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