/**********************************************************************
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/**********************************************************************
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** File: wb_dual_port_ram.v
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** File: wb_dual_port_ram.v
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**
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**
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**
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**
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** Copyright (C) 2014-2017 Alireza Monemi
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** Copyright (C) 2014-2017 Alireza Monemi
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**
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**
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** This file is part of ProNoC
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** This file is part of ProNoC
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**
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**
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** you can redistribute it and/or modify it under the terms of the GNU
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** you can redistribute it and/or modify it under the terms of the GNU
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** Lesser General Public License as published by the Free Software Foundation,
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** Lesser General Public License as published by the Free Software Foundation,
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** either version 2 of the License, or (at your option) any later version.
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** either version 2 of the License, or (at your option) any later version.
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**
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**
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
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** License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
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**
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**
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**
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**
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** Description:
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** Description:
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** wishbone based single port ram
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** wishbone based single port ram
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**
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**
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**
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**
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*******************************************************************/
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*******************************************************************/
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module wb_single_port_ram #(
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module wb_single_port_ram #(
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parameter Dw=32, //RAM data_width in bits
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parameter Dw=32, //RAM data_width in bits
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parameter Aw=10, //RAM address width
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parameter Aw=10, //RAM address width
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parameter BYTE_WR_EN= "YES",//"YES","NO"
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parameter BYTE_WR_EN= "YES",//"YES","NO"
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parameter FPGA_VENDOR= "ALTERA",//"ALTERA","GENERIC"
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parameter FPGA_VENDOR= "ALTERA",//"ALTERA","GENERIC"
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parameter JTAG_CONNECT= "JTAG_WB",//"DISABLED", "JTAG_WB" , "ALTERA_IMCE", if not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb
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parameter JTAG_CONNECT= "ALTERA_JTAG_WB",//"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE", if not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb
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parameter JTAG_INDEX= 0,
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parameter JTAG_INDEX= 0,
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parameter INITIAL_EN= "NO",
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parameter INITIAL_EN= "NO",
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parameter MEM_CONTENT_FILE_NAME= "ram0",// ram initial file name
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parameter MEM_CONTENT_FILE_NAME= "ram0",// ram initial file name
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parameter INIT_FILE_PATH = "path_to/sw", // The sw folder path. It will be used for finding initial file. The path will be rewriten by the top module.
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parameter INIT_FILE_PATH = "path_to/sw", // The sw folder path. It will be used for finding initial file. The path will be rewriten by the top module.
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// wishbon bus param
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// wishbon bus param
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parameter BURST_MODE= "DISABLED", // "DISABLED" , "ENABLED" wisbone bus burst mode
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parameter BURST_MODE= "DISABLED", // "DISABLED" , "ENABLED" wisbone bus burst mode
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parameter TAGw = 3,
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parameter TAGw = 3,
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parameter SELw = Dw/8,
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parameter SELw = Dw/8,
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parameter CTIw = 3,
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parameter CTIw = 3,
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parameter BTEw = 2
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parameter BTEw = 2
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)
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)
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(
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(
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clk,
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clk,
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reset,
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reset,
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//wishbone bus interface
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//wishbone bus interface
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sa_dat_i,
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sa_dat_i,
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sa_sel_i,
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sa_sel_i,
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sa_addr_i,
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sa_addr_i,
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sa_tag_i,
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sa_tag_i,
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sa_cti_i,
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sa_cti_i,
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sa_bte_i,
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sa_bte_i,
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sa_stb_i,
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sa_stb_i,
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sa_cyc_i,
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sa_cyc_i,
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sa_we_i,
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sa_we_i,
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sa_dat_o,
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sa_dat_o,
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sa_ack_o,
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sa_ack_o,
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sa_err_o,
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sa_err_o,
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sa_rty_o
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sa_rty_o
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);
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);
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input clk;
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input clk;
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input reset;
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input reset;
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//wishbone bus interface
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//wishbone bus interface
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input [Dw-1 : 0] sa_dat_i;
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input [Dw-1 : 0] sa_dat_i;
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input [SELw-1 : 0] sa_sel_i;
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input [SELw-1 : 0] sa_sel_i;
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input [Aw-1 : 0] sa_addr_i;
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input [Aw-1 : 0] sa_addr_i;
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input [TAGw-1 : 0] sa_tag_i;
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input [TAGw-1 : 0] sa_tag_i;
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input sa_stb_i;
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input sa_stb_i;
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input sa_cyc_i;
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input sa_cyc_i;
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input sa_we_i;
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input sa_we_i;
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input [CTIw-1 : 0] sa_cti_i;
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input [CTIw-1 : 0] sa_cti_i;
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input [BTEw-1 : 0] sa_bte_i;
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input [BTEw-1 : 0] sa_bte_i;
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output [Dw-1 : 0] sa_dat_o;
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output [Dw-1 : 0] sa_dat_o;
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output sa_ack_o;
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output sa_ack_o;
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output sa_err_o;
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output sa_err_o;
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output sa_rty_o;
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output sa_rty_o;
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wire [Dw-1 : 0] d;
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wire [Dw-1 : 0] d;
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wire [Aw-1 : 0] addr;
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wire [Aw-1 : 0] addr;
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wire we;
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wire we;
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wire [Dw-1 : 0] q;
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wire [Dw-1 : 0] q;
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localparam MEM_NAME = (FPGA_VENDOR== "ALTERA")? {MEM_CONTENT_FILE_NAME,".mif"} :
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localparam MEM_NAME = (FPGA_VENDOR== "ALTERA")? {MEM_CONTENT_FILE_NAME,".mif"} :
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{MEM_CONTENT_FILE_NAME,".hex"}; //Generic
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{MEM_CONTENT_FILE_NAME,".hex"}; //Generic
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localparam INIT_FILE = {INIT_FILE_PATH,"/RAM/",MEM_NAME};
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localparam INIT_FILE = {INIT_FILE_PATH,"/RAM/",MEM_NAME};
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wb_bram_ctrl #(
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wb_bram_ctrl #(
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.Dw(Dw),
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.Dw(Dw),
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.Aw(Aw),
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.Aw(Aw),
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.BURST_MODE(BURST_MODE),
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.BURST_MODE(BURST_MODE),
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.SELw(SELw),
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.SELw(SELw),
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.CTIw(CTIw),
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.CTIw(CTIw),
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.BTEw(BTEw)
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.BTEw(BTEw)
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)
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)
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ctrl
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ctrl
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(
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(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.d(d),
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.d(d),
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.addr(addr),
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.addr(addr),
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.we(we),
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.we(we),
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.q(q),
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.q(q),
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.sa_dat_i(sa_dat_i),
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.sa_dat_i(sa_dat_i),
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.sa_sel_i(sa_sel_i),
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.sa_sel_i(sa_sel_i),
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.sa_addr_i(sa_addr_i),
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.sa_addr_i(sa_addr_i),
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.sa_stb_i(sa_stb_i),
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.sa_stb_i(sa_stb_i),
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.sa_cyc_i(sa_cyc_i),
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.sa_cyc_i(sa_cyc_i),
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.sa_we_i(sa_we_i),
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.sa_we_i(sa_we_i),
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.sa_cti_i(sa_cti_i),
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.sa_cti_i(sa_cti_i),
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.sa_bte_i(sa_bte_i),
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.sa_bte_i(sa_bte_i),
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.sa_dat_o(sa_dat_o),
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.sa_dat_o(sa_dat_o),
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.sa_ack_o(sa_ack_o),
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.sa_ack_o(sa_ack_o),
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.sa_err_o(sa_err_o),
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.sa_err_o(sa_err_o),
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.sa_rty_o(sa_rty_o)
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.sa_rty_o(sa_rty_o)
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);
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);
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single_port_ram_top #(
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single_port_ram_top #(
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.Dw(Dw),
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.Dw(Dw),
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.Aw(Aw),
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.Aw(Aw),
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.BYTE_WR_EN(BYTE_WR_EN),
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.BYTE_WR_EN(BYTE_WR_EN),
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.FPGA_VENDOR(FPGA_VENDOR),
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.FPGA_VENDOR(FPGA_VENDOR),
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.JTAG_CONNECT(JTAG_CONNECT),
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.JTAG_CONNECT(JTAG_CONNECT),
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.JTAG_INDEX(JTAG_INDEX),
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.JTAG_INDEX(JTAG_INDEX),
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.INITIAL_EN(INITIAL_EN),
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.INITIAL_EN(INITIAL_EN),
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.INIT_FILE(INIT_FILE)
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.INIT_FILE(INIT_FILE)
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)
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)
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ram_top
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ram_top
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(
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(
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.reset(reset),
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.reset(reset),
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.clk(clk),
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.clk(clk),
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.data_a(d),
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.data_a(d),
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.addr_a(addr),
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.addr_a(addr),
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.we_a(we),
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.we_a(we),
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.q_a(q),
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.q_a(q),
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.byteena_a(sa_sel_i)
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.byteena_a(sa_sel_i)
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);
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);
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endmodule
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endmodule
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module single_port_ram_top #(
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module single_port_ram_top #(
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parameter Dw=32, //RAM data_width in bits
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parameter Dw=32, //RAM data_width in bits
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parameter Aw=10, //RAM address width
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parameter Aw=10, //RAM address width
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parameter BYTE_WR_EN= "YES",//"YES","NO"
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parameter BYTE_WR_EN= "YES",//"YES","NO"
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parameter FPGA_VENDOR= "ALTERA",//"ALTERA","GENERIC"
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parameter FPGA_VENDOR= "ALTERA",//"ALTERA","GENERIC"
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parameter JTAG_CONNECT= "JTAG_WB",//"DISABLED", "JTAG_WB" , "ALTERA_IMCE", if not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb
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parameter JTAG_CONNECT= "ALTERA_JTAG_WB",//"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE", if not disabled then the actual memory implements as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb
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parameter JTAG_INDEX= 0,
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parameter JTAG_INDEX= 0,
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parameter INITIAL_EN= "NO",
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parameter INITIAL_EN= "NO",
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parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file
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parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file
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)
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)
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(
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(
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reset,
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reset,
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clk,
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clk,
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data_a,
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data_a,
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addr_a,
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addr_a,
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byteena_a,
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byteena_a,
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we_a,
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we_a,
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q_a
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q_a
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);
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);
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/* verilator lint_off WIDTH */
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localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;
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localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;
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/* verilator lint_on WIDTH */
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input clk,reset;
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input clk,reset;
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input [Dw-1 : 0] data_a;
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input [Dw-1 : 0] data_a;
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input [Aw-1 : 0] addr_a;
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input [Aw-1 : 0] addr_a;
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input we_a;
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input we_a;
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input [BYTE_ENw-1 : 0] byteena_a;
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input [BYTE_ENw-1 : 0] byteena_a;
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output [Dw-1 : 0] q_a;
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output [Dw-1 : 0] q_a;
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function [15:0]i2s;
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function [15:0]i2s;
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input integer c; integer i; integer tmp; begin
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input integer c; integer i; integer tmp; begin
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tmp =0;
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tmp =0;
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for (i=0; i<2; i=i+1'b1) begin
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for (i=0; i<2; i=i+1'b1) begin
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tmp = tmp + (((c % 10) + 6'd48) << i*8);
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tmp = tmp + (((c % 10) + 6'd48) << i*8);
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c = c/10;
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c = c/10;
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end
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end
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i2s = tmp[15:0];
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i2s = tmp[15:0];
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end
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end
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endfunction //i2s
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endfunction //i2s
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function integer log2;
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function integer log2;
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input integer number; begin
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input integer number; begin
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log2=0;
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log2=0;
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while(2**log2<number) begin
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while(2**log2<number) begin
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log2=log2+1;
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log2=log2+1;
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end
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end
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end
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end
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endfunction // log2
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endfunction // log2
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wire [Dw-1 : 0] data_b;
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wire [Dw-1 : 0] data_b;
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wire [Aw-1 : 0] addr_b;
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wire [Aw-1 : 0] addr_b;
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wire we_b;
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wire we_b;
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wire [Dw-1 : 0] q_b;
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wire [Dw-1 : 0] q_b;
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generate
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generate
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/* verilator lint_off WIDTH */
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if(FPGA_VENDOR=="ALTERA")begin:altera_fpga
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if(FPGA_VENDOR=="ALTERA")begin:altera_fpga
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/* verilator lint_on WIDTH */
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localparam RAM_TAG_STRING=i2s(JTAG_INDEX);
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localparam RAM_TAG_STRING=i2s(JTAG_INDEX);
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localparam RAM_ID =(JTAG_CONNECT== "ALTERA_IMCE") ? {"ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=",RAM_TAG_STRING}
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localparam RAM_ID =(JTAG_CONNECT== "ALTERA_IMCE") ? {"ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=",RAM_TAG_STRING}
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: {"ENABLE_RUNTIME_MOD=NO"};
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: {"ENABLE_RUNTIME_MOD=NO"};
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/* verilator lint_off WIDTH */
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if(JTAG_CONNECT== "JTAG_WB")begin:dual_ram
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if(JTAG_CONNECT== "ALTERA_JTAG_WB")begin:dual_ram
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/* verilator lint_on WIDTH */
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// aletra dual port ram
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// aletra dual port ram
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altsyncram #(
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altsyncram #(
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.operation_mode("BIDIR_DUAL_PORT"),
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.operation_mode("BIDIR_DUAL_PORT"),
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.address_reg_b("CLOCK0"),
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.address_reg_b("CLOCK0"),
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.wrcontrol_wraddress_reg_b("CLOCK0"),
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.wrcontrol_wraddress_reg_b("CLOCK0"),
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.indata_reg_b("CLOCK0"),
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.indata_reg_b("CLOCK0"),
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.outdata_reg_a("UNREGISTERED"),
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.outdata_reg_a("UNREGISTERED"),
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.outdata_reg_b("UNREGISTERED"),
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.outdata_reg_b("UNREGISTERED"),
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.width_a(Dw),
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.width_a(Dw),
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.width_b(Dw),
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.width_b(Dw),
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.lpm_hint(RAM_ID),
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.lpm_hint(RAM_ID),
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.read_during_write_mode_mixed_ports("DONT_CARE"),
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.read_during_write_mode_mixed_ports("DONT_CARE"),
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.widthad_a(Aw),
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.widthad_a(Aw),
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.widthad_b(Aw),
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.widthad_b(Aw),
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.width_byteena_a(BYTE_ENw),
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.width_byteena_a(BYTE_ENw),
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.init_file(INIT_FILE)
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.init_file(INIT_FILE)
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) ram_inst(
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) ram_inst(
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.clock0 (clk),
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.clock0 (clk),
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.address_a (addr_a),
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.address_a (addr_a),
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.wren_a (we_a),
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.wren_a (we_a),
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.data_a (data_a),
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.data_a (data_a),
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.q_a (q_a),
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.q_a (q_a),
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.byteena_a (byteena_a),
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.byteena_a (byteena_a),
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.address_b (addr_b),
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.address_b (addr_b),
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.wren_b (we_b),
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.wren_b (we_b),
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.data_b (data_b),
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.data_b (data_b),
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.q_b (q_b),
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.q_b (q_b),
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.byteena_b (1'b1),
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.byteena_b (1'b1),
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.rden_a (1'b1),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.rden_b (1'b1),
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.clock1 (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.clocken3 (1'b1),
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.aclr0 (1'b0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.addressstall_b (1'b0),
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.eccstatus ( )
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.eccstatus ( )
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);
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);
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// jtag_wb
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// jtag_wb
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end else begin: single_ram //JTAG_CONNECT= "DISABLED", "ALTERA_IMCE"
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end else begin: single_ram //JTAG_CONNECT= "DISABLED", "ALTERA_IMCE"
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altsyncram #(
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altsyncram #(
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.operation_mode("SINGLE_PORT"),
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.operation_mode("SINGLE_PORT"),
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.width_a(Dw),
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.width_a(Dw),
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.lpm_hint(RAM_ID),
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.lpm_hint(RAM_ID),
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.read_during_write_mode_mixed_ports("DONT_CARE"),
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.read_during_write_mode_mixed_ports("DONT_CARE"),
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.widthad_a(Aw),
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.widthad_a(Aw),
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.width_byteena_a(BYTE_ENw),
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.width_byteena_a(BYTE_ENw),
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.init_file(INIT_FILE)
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.init_file(INIT_FILE)
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)
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)
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ram_inst
|
ram_inst
|
(
|
(
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.clock0 (clk),
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.clock0 (clk),
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.address_a (addr_a),
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.address_a (addr_a),
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.wren_a (we_a),
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.wren_a (we_a),
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.data_a (data_a),
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.data_a (data_a),
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.q_a (q_a),
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.q_a (q_a),
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.byteena_a (byteena_a),
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.byteena_a (byteena_a),
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.wren_b ( ),
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.wren_b ( ),
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.rden_a ( ),
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.rden_a ( ),
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.rden_b ( ),
|
.rden_b ( ),
|
.data_b ( ),
|
.data_b ( ),
|
.address_b ( ),
|
.address_b ( ),
|
.clock1 ( ),
|
.clock1 ( ),
|
.clocken0 ( ),
|
.clocken0 ( ),
|
.clocken1 ( ),
|
.clocken1 ( ),
|
.clocken2 ( ),
|
.clocken2 ( ),
|
.clocken3 ( ),
|
.clocken3 ( ),
|
.aclr0 ( ),
|
.aclr0 ( ),
|
.aclr1 ( ),
|
.aclr1 ( ),
|
.byteena_b ( ),
|
.byteena_b ( ),
|
.addressstall_a ( ),
|
.addressstall_a ( ),
|
.addressstall_b ( ),
|
.addressstall_b ( ),
|
.q_b ( ),
|
.q_b ( ),
|
.eccstatus ( )
|
.eccstatus ( )
|
);
|
);
|
|
|
end
|
end
|
end
|
end
|
|
/* verilator lint_off WIDTH */
|
else if(FPGA_VENDOR=="GENERIC")begin:generic_ram
|
else if(FPGA_VENDOR=="GENERIC")begin:generic_ram
|
if(JTAG_CONNECT== "JTAG_WB")begin:dual_ram
|
if(JTAG_CONNECT== "ALTERA_JTAG_WB")begin:dual_ram
|
|
/* verilator lint_on WIDTH */
|
|
|
generic_dual_port_ram #(
|
generic_dual_port_ram #(
|
.Dw(Dw),
|
.Dw(Dw),
|
.Aw(Aw),
|
.Aw(Aw),
|
.BYTE_WR_EN(BYTE_WR_EN),
|
.BYTE_WR_EN(BYTE_WR_EN),
|
.INITIAL_EN(INITIAL_EN),
|
.INITIAL_EN(INITIAL_EN),
|
.INIT_FILE(INIT_FILE)
|
.INIT_FILE(INIT_FILE)
|
)
|
)
|
ram_inst
|
ram_inst
|
(
|
(
|
.data_a (data_a),
|
.data_a (data_a),
|
.data_b (data_b),
|
.data_b (data_b),
|
.addr_a (addr_a),
|
.addr_a (addr_a),
|
.addr_b (addr_b),
|
.addr_b (addr_b),
|
.byteena_a (byteena_a ),
|
.byteena_a (byteena_a ),
|
.byteena_b ({BYTE_ENw{1'b1}}),
|
.byteena_b ({BYTE_ENw{1'b1}}),
|
.we_a (we_a),
|
.we_a (we_a),
|
.we_b (we_b),
|
.we_b (we_b),
|
.clk (clk),
|
.clk (clk),
|
.q_a (q_a),
|
.q_a (q_a),
|
.q_b (q_b)
|
.q_b (q_b)
|
|
|
);
|
);
|
|
|
|
|
end else begin
|
end else begin
|
|
|
|
|
|
|
generic_single_port_ram #(
|
generic_single_port_ram #(
|
.Dw(Dw),
|
.Dw(Dw),
|
.Aw(Aw),
|
.Aw(Aw),
|
.BYTE_WR_EN(BYTE_WR_EN),
|
.BYTE_WR_EN(BYTE_WR_EN),
|
.INITIAL_EN(INITIAL_EN),
|
.INITIAL_EN(INITIAL_EN),
|
.INIT_FILE(INIT_FILE)
|
.INIT_FILE(INIT_FILE)
|
)
|
)
|
ram_inst
|
ram_inst
|
(
|
(
|
.data (data_a),
|
.data (data_a),
|
.addr (addr_a),
|
.addr (addr_a),
|
.byteen (byteena_a ),
|
.byteen (byteena_a ),
|
.we (we_a),
|
.we (we_a),
|
.clk (clk),
|
.clk (clk),
|
.q (q_a)
|
.q (q_a)
|
|
|
);
|
);
|
|
|
end//jtag_wb
|
end//jtag_wb
|
end //Generic
|
end //Generic
|
|
|
|
/* verilator lint_off WIDTH */
|
if(JTAG_CONNECT == "JTAG_WB")begin:jtag_wb
|
if(JTAG_CONNECT == "ALTERA_JTAG_WB")begin:jtag_wb
|
|
/* verilator lint_on WIDTH */
|
reg jtag_ack;
|
reg jtag_ack;
|
wire jtag_we_o, jtag_stb_o;
|
wire jtag_we_o, jtag_stb_o;
|
|
|
localparam Sw= log2(Aw+1);
|
localparam Sw= log2(Aw+1);
|
localparam [Sw-1 : 0] ST = Aw;
|
localparam [Sw-1 : 0] ST = Aw;
|
vjtag_wb #(
|
vjtag_wb #(
|
.VJTAG_INDEX(JTAG_INDEX),
|
.VJTAG_INDEX(JTAG_INDEX),
|
.DW(Dw),
|
.DW(Dw),
|
.AW(Aw),
|
.AW(Aw),
|
.SW(Sw),
|
.SW(Sw),
|
|
|
//wishbone port parameters
|
//wishbone port parameters
|
.M_Aw(Aw),
|
.M_Aw(Aw),
|
.TAGw(3)
|
.TAGw(3)
|
)
|
)
|
vjtag_inst
|
vjtag_inst
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.status_i(ST), // Jtag can read memory size as status
|
.status_i(ST), // Jtag can read memory size as status
|
//wishbone master interface signals
|
//wishbone master interface signals
|
.m_sel_o(),
|
.m_sel_o(),
|
.m_dat_o(data_b),
|
.m_dat_o(data_b),
|
.m_addr_o(addr_b),
|
.m_addr_o(addr_b),
|
.m_cti_o(),
|
.m_cti_o(),
|
.m_stb_o(jtag_stb_o),
|
.m_stb_o(jtag_stb_o),
|
.m_cyc_o(),
|
.m_cyc_o(),
|
.m_we_o(jtag_we_o),
|
.m_we_o(jtag_we_o),
|
.m_dat_i(q_b),
|
.m_dat_i(q_b),
|
.m_ack_i(jtag_ack)
|
.m_ack_i(jtag_ack)
|
|
|
);
|
);
|
|
|
assign we_b = jtag_stb_o & jtag_we_o;
|
assign we_b = jtag_stb_o & jtag_we_o;
|
|
|
always @(posedge clk )begin
|
always @(posedge clk )begin
|
jtag_ack<=jtag_stb_o;
|
jtag_ack<=jtag_stb_o;
|
end
|
end
|
end//jtag_wb
|
end//jtag_wb
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
