/**********************************************************************
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/**********************************************************************
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** File: wishbone_bus.v
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** File: wishbone_bus.v
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**
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**
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**
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**
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** Copyright (C) 2014-2017 Alireza Monemi
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** Copyright (C) 2014-2017 Alireza Monemi
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**
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**
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** This file is part of ProNoC
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** This file is part of ProNoC
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**
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**
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** you can redistribute it and/or modify it under the terms of the GNU
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** you can redistribute it and/or modify it under the terms of the GNU
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** Lesser General Public License as published by the Free Software Foundation,
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** Lesser General Public License as published by the Free Software Foundation,
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** either version 2 of the License, or (at your option) any later version.
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** either version 2 of the License, or (at your option) any later version.
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**
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**
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
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** License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
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**
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**
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**
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**
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** Description:
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** Description:
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** parametrizable wishbone bus
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** parametrizable wishbone bus
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**
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**
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*******************************************************************/
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*******************************************************************/
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`timescale 10ns/1ns
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`timescale 10ns/1ns
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module wishbone_bus #(
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module wishbone_bus #(
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parameter M = 4, //number of master port
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parameter M = 4, //number of master port
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parameter S = 4, //number of slave port
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parameter S = 4, //number of slave port
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parameter Dw = 32, // maximum data width
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parameter Dw = 32, // maximum data width
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parameter Aw = 32, // address width
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parameter Aw = 32, // address width
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parameter SELw = 2,
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parameter SELw = 2,
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parameter TAGw = 3, //merged {tga,tgb,tgc}
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parameter TAGw = 3, //merged {tga,tgb,tgc}
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parameter CTIw = 3,
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parameter CTIw = 3,
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parameter BTEw = 2
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parameter BTEw = 2
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)
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)
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(
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(
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//slaves interface
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//slaves interface
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s_adr_o_all,
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s_adr_o_all,
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s_dat_o_all,
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s_dat_o_all,
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s_sel_o_all,
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s_sel_o_all,
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s_tag_o_all,
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s_tag_o_all,
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s_we_o_all,
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s_we_o_all,
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s_cyc_o_all,
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s_cyc_o_all,
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s_stb_o_all,
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s_stb_o_all,
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s_cti_o_all,
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s_cti_o_all,
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s_bte_o_all,
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s_bte_o_all,
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s_dat_i_all,
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s_dat_i_all,
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s_ack_i_all,
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s_ack_i_all,
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s_err_i_all,
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s_err_i_all,
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s_rty_i_all,
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s_rty_i_all,
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//masters interface
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//masters interface
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m_dat_o_all,
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m_dat_o_all,
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m_ack_o_all,
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m_ack_o_all,
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m_err_o_all,
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m_err_o_all,
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m_rty_o_all,
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m_rty_o_all,
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m_adr_i_all,
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m_adr_i_all,
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m_dat_i_all,
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m_dat_i_all,
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m_sel_i_all,
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m_sel_i_all,
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m_tag_i_all,
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m_tag_i_all,
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m_we_i_all,
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m_we_i_all,
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m_stb_i_all,
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m_stb_i_all,
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m_cyc_i_all,
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m_cyc_i_all,
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m_cti_i_all,
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m_cti_i_all,
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m_bte_i_all,
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m_bte_i_all,
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//address compar
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//address compar
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m_grant_addr,
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m_grant_addr,
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s_sel_one_hot,
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s_sel_one_hot,
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//system signals
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//system signals
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clk,
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clk,
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reset
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reset
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);
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);
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function integer log2;
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function integer log2;
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input integer number; begin
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input integer number; begin
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log2=0;
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log2=0;
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while(2**log2<number) begin
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while(2**log2<number) begin
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log2=log2+1;
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log2=log2+1;
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end
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end
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end
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end
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endfunction // log2
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endfunction // log2
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localparam DwS = Dw * S,
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localparam DwS = Dw * S,
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AwS = Aw * S,
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AwS = Aw * S,
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SELwS = SELw * S,
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SELwS = SELw * S,
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TAGwS = TAGw * S,
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TAGwS = TAGw * S,
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CTIwS = CTIw * S,
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CTIwS = CTIw * S,
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BTEwS = BTEw * S,
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BTEwS = BTEw * S,
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DwM = Dw * M,
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DwM = Dw * M,
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AwM = Aw * M,
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AwM = Aw * M,
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SELwM = SELw * M,
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SELwM = SELw * M,
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TAGwM = TAGw * M,
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TAGwM = TAGw * M,
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Mw = (M>1)? log2(M):1,
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Mw = (M>1)? log2(M):1,
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Sw = (S>1)? log2(S):1,
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Sw = (S>1)? log2(S):1,
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CTIwM = CTIw * M,
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CTIwM = CTIw * M,
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BTEwM = BTEw * M;
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BTEwM = BTEw * M;
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output [AwS-1 : 0] s_adr_o_all;
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output [AwS-1 : 0] s_adr_o_all;
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output [DwS-1 : 0] s_dat_o_all;
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output [DwS-1 : 0] s_dat_o_all;
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output [SELwS-1 : 0] s_sel_o_all;
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output [SELwS-1 : 0] s_sel_o_all;
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output [TAGwS-1 : 0] s_tag_o_all;
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output [TAGwS-1 : 0] s_tag_o_all;
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output [S-1 : 0] s_we_o_all;
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output [S-1 : 0] s_we_o_all;
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output [S-1 : 0] s_cyc_o_all;
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output [S-1 : 0] s_cyc_o_all;
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output [S-1 : 0] s_stb_o_all;
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output [S-1 : 0] s_stb_o_all;
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output [CTIwS-1 : 0] s_cti_o_all;
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output [CTIwS-1 : 0] s_cti_o_all;
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output [BTEwS-1 : 0] s_bte_o_all;
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output [BTEwS-1 : 0] s_bte_o_all;
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input [DwS-1 : 0] s_dat_i_all;
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input [DwS-1 : 0] s_dat_i_all;
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input [S-1 : 0] s_ack_i_all;
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input [S-1 : 0] s_ack_i_all;
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input [S-1 : 0] s_err_i_all;
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input [S-1 : 0] s_err_i_all;
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input [S-1 : 0] s_rty_i_all;
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input [S-1 : 0] s_rty_i_all;
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//masters interface
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//masters interface
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output [DwM-1 : 0] m_dat_o_all;
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output [DwM-1 : 0] m_dat_o_all;
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output [M-1 : 0] m_ack_o_all;
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output [M-1 : 0] m_ack_o_all;
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output [M-1 : 0] m_err_o_all;
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output [M-1 : 0] m_err_o_all;
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output [M-1 : 0] m_rty_o_all;
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output [M-1 : 0] m_rty_o_all;
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input [AwM-1 : 0] m_adr_i_all;
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input [AwM-1 : 0] m_adr_i_all;
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input [DwM-1 : 0] m_dat_i_all;
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input [DwM-1 : 0] m_dat_i_all;
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input [SELwM-1 : 0] m_sel_i_all;
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input [SELwM-1 : 0] m_sel_i_all;
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input [TAGwM-1 : 0] m_tag_i_all;
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input [TAGwM-1 : 0] m_tag_i_all;
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input [M-1 : 0] m_we_i_all;
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input [M-1 : 0] m_we_i_all;
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input [M-1 : 0] m_stb_i_all;
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input [M-1 : 0] m_stb_i_all;
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input [M-1 : 0] m_cyc_i_all;
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input [M-1 : 0] m_cyc_i_all;
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input [CTIwM-1 : 0] m_cti_i_all;
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input [CTIwM-1 : 0] m_cti_i_all;
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input [BTEwM-1 : 0] m_bte_i_all;
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input [BTEwM-1 : 0] m_bte_i_all;
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//
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//
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output [Aw-1 : 0] m_grant_addr;
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output [Aw-1 : 0] m_grant_addr;
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input [S-1 : 0] s_sel_one_hot;
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input [S-1 : 0] s_sel_one_hot;
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//system signals
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//system signals
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input clk, reset;
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input clk, reset;
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wire any_s_ack,any_s_err,any_s_rty;
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wire any_s_ack,any_s_err,any_s_rty;
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wire m_grant_we,m_grant_stb,m_grant_cyc;
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wire m_grant_we,m_grant_stb,m_grant_cyc;
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wire [Dw-1 : 0] m_grant_dat,s_read_dat;
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wire [Dw-1 : 0] m_grant_dat,s_read_dat;
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wire [SELw-1 : 0] m_grant_sel;
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wire [SELw-1 : 0] m_grant_sel;
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wire [BTEw-1 : 0] m_grant_bte;
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wire [BTEw-1 : 0] m_grant_bte;
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wire [CTIw-1 : 0] m_grant_cti;
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wire [CTIw-1 : 0] m_grant_cti;
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wire [TAGw-1 : 0] m_grant_tag;
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wire [TAGw-1 : 0] m_grant_tag;
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wire [Sw-1 : 0] s_sel_bin;
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wire [Sw-1 : 0] s_sel_bin;
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wire [M-1 : 0] m_grant_onehot;
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wire [M-1 : 0] m_grant_onehot;
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wire [Mw-1 : 0] m_grant_bin;
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wire [Mw-1 : 0] m_grant_bin;
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wire [Aw-1 : 0] s_adr_o;
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wire [Aw-1 : 0] s_adr_o;
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wire [Dw-1 : 0] s_dat_o;
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wire [Dw-1 : 0] s_dat_o;
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wire [SELw-1 : 0] s_sel_o;
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wire [SELw-1 : 0] s_sel_o;
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wire [BTEw-1 : 0] s_bte_o;
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wire [BTEw-1 : 0] s_bte_o;
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wire [CTIw-1 : 0] s_cti_o;
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wire [CTIw-1 : 0] s_cti_o;
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wire [TAGw-1 : 0] s_tag_o;
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wire [TAGw-1 : 0] s_tag_o;
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wire s_we_o;
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wire s_we_o;
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wire s_cyc_o;
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wire s_cyc_o;
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wire [Dw-1 : 0] m_dat_o;
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wire [Dw-1 : 0] m_dat_o;
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assign s_adr_o_all = {S{s_adr_o}};
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assign s_adr_o_all = {S{s_adr_o}};
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assign s_dat_o_all = {S{s_dat_o}};
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assign s_dat_o_all = {S{s_dat_o}};
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assign s_sel_o_all = {S{s_sel_o}};
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assign s_sel_o_all = {S{s_sel_o}};
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assign s_cti_o_all = {S{s_cti_o}};
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assign s_cti_o_all = {S{s_cti_o}};
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assign s_bte_o_all = {S{s_bte_o}};
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assign s_bte_o_all = {S{s_bte_o}};
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assign s_tag_o_all = {S{s_tag_o}};
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assign s_tag_o_all = {S{s_tag_o}};
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assign s_we_o_all = {S{s_we_o}};
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assign s_we_o_all = {S{s_we_o}};
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assign s_cyc_o_all = {S{s_cyc_o}};
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assign s_cyc_o_all = {S{s_cyc_o}};
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assign m_dat_o_all= {M{m_dat_o}};
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assign m_dat_o_all= {M{m_dat_o}};
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assign any_s_ack =| s_ack_i_all;
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assign any_s_ack =| s_ack_i_all;
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assign any_s_err =| s_err_i_all;
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assign any_s_err =| s_err_i_all;
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assign any_s_rty =| s_rty_i_all;
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assign any_s_rty =| s_rty_i_all;
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assign s_adr_o = m_grant_addr;
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assign s_adr_o = m_grant_addr;
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assign s_dat_o = m_grant_dat;
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assign s_dat_o = m_grant_dat;
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assign s_sel_o = m_grant_sel;
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assign s_sel_o = m_grant_sel;
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assign s_bte_o = m_grant_bte;
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assign s_bte_o = m_grant_bte;
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assign s_cti_o = m_grant_cti;
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assign s_cti_o = m_grant_cti;
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assign s_tag_o = m_grant_tag;
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assign s_tag_o = m_grant_tag;
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assign s_we_o = m_grant_we;
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assign s_we_o = m_grant_we;
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assign s_cyc_o = m_grant_cyc;
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assign s_cyc_o = m_grant_cyc;
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assign s_stb_o_all = s_sel_one_hot & {S{m_grant_stb & m_grant_cyc}};
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assign s_stb_o_all = s_sel_one_hot & {S{m_grant_stb & m_grant_cyc}};
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//wire [ADDR_PERFIX-1 : 0] m_perfix_addr;
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//wire [ADDR_PERFIX-1 : 0] m_perfix_addr;
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//assign m_perfix_addr = m_grant_addr[Aw-3 : Aw-ADDR_PERFIX-2];
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//assign m_perfix_addr = m_grant_addr[Aw-3 : Aw-ADDR_PERFIX-2];
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assign m_dat_o = s_read_dat;
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assign m_dat_o = s_read_dat;
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assign m_ack_o_all = m_grant_onehot & {M{any_s_ack}};
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assign m_ack_o_all = m_grant_onehot & {M{any_s_ack}};
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assign m_err_o_all = m_grant_onehot & {M{any_s_err}};
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assign m_err_o_all = m_grant_onehot & {M{any_s_err}};
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assign m_rty_o_all = m_grant_onehot & {M{any_s_rty}};
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assign m_rty_o_all = m_grant_onehot & {M{any_s_rty}};
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//convert one hot to bin
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//convert one hot to bin
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one_hot_to_bin #(
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one_hot_to_bin #(
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.ONE_HOT_WIDTH(S)
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.ONE_HOT_WIDTH(S)
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)
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)
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s_sel_conv
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s_sel_conv
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(
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(
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.one_hot_code(s_sel_one_hot),
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.one_hot_code(s_sel_one_hot),
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.bin_code(s_sel_bin)
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.bin_code(s_sel_bin)
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);
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);
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one_hot_to_bin #(
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one_hot_to_bin #(
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.ONE_HOT_WIDTH(M)
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.ONE_HOT_WIDTH(M)
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)
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)
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m_grant_conv
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m_grant_conv
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(
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(
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.one_hot_code (m_grant_onehot),
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.one_hot_code (m_grant_onehot),
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.bin_code (m_grant_bin)
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.bin_code (m_grant_bin)
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);
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);
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//slave multiplexer
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//slave multiplexer
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binary_mux #(
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binary_mux #(
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.IN_WIDTH (DwS),
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.IN_WIDTH (DwS),
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.OUT_WIDTH (Dw)
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.OUT_WIDTH (Dw)
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)
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)
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s_read_data_mux
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s_read_data_mux
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(
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(
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.mux_in (s_dat_i_all),
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.mux_in (s_dat_i_all),
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.mux_out (s_read_dat),
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.mux_out (s_read_dat),
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.sel (s_sel_bin)
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.sel (s_sel_bin)
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);
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);
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//master ports multiplexers
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//master ports multiplexers
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binary_mux #(
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binary_mux #(
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.IN_WIDTH (AwM),
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.IN_WIDTH (AwM),
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.OUT_WIDTH (Aw)
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.OUT_WIDTH (Aw)
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)
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)
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m_adr_mux
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m_adr_mux
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(
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(
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.mux_in (m_adr_i_all),
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.mux_in (m_adr_i_all),
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.mux_out (m_grant_addr),
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.mux_out (m_grant_addr),
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.sel (m_grant_bin)
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.sel (m_grant_bin)
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);
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);
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binary_mux #(
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binary_mux #(
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.IN_WIDTH (DwM),
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.IN_WIDTH (DwM),
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.OUT_WIDTH (Dw)
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.OUT_WIDTH (Dw)
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)
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)
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m_data_mux
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m_data_mux
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(
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(
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.mux_in (m_dat_i_all),
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.mux_in (m_dat_i_all),
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.mux_out (m_grant_dat),
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.mux_out (m_grant_dat),
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.sel (m_grant_bin)
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.sel (m_grant_bin)
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);
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);
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binary_mux #(
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binary_mux #(
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.IN_WIDTH (SELwM),
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.IN_WIDTH (SELwM),
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.OUT_WIDTH (SELw)
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.OUT_WIDTH (SELw)
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)
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)
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m_sel_mux
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m_sel_mux
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(
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(
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.mux_in (m_sel_i_all),
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.mux_in (m_sel_i_all),
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.mux_out (m_grant_sel),
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.mux_out (m_grant_sel),
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.sel (m_grant_bin)
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.sel (m_grant_bin)
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);
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);
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binary_mux #(
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binary_mux #(
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.IN_WIDTH (BTEwM),
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.IN_WIDTH (BTEwM),
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.OUT_WIDTH (BTEw)
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.OUT_WIDTH (BTEw)
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)
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)
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m_bte_mux
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m_bte_mux
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(
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(
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.mux_in (m_bte_i_all),
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.mux_in (m_bte_i_all),
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.mux_out (m_grant_bte),
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.mux_out (m_grant_bte),
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.sel (m_grant_bin)
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.sel (m_grant_bin)
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);
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);
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binary_mux #(
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binary_mux #(
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.IN_WIDTH (CTIwM),
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.IN_WIDTH (CTIwM),
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.OUT_WIDTH (CTIw)
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.OUT_WIDTH (CTIw)
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)
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)
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m_cti_mux
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m_cti_mux
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(
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(
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.mux_in (m_cti_i_all),
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.mux_in (m_cti_i_all),
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.mux_out (m_grant_cti),
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.mux_out (m_grant_cti),
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.sel (m_grant_bin)
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.sel (m_grant_bin)
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);
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);
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binary_mux #(
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binary_mux #(
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.IN_WIDTH (TAGwM),
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.IN_WIDTH (TAGwM),
|
.OUT_WIDTH (TAGw)
|
.OUT_WIDTH (TAGw)
|
)
|
)
|
m_tag_mux
|
m_tag_mux
|
(
|
(
|
.mux_in (m_tag_i_all),
|
.mux_in (m_tag_i_all),
|
.mux_out (m_grant_tag),
|
.mux_out (m_grant_tag),
|
.sel (m_grant_bin)
|
.sel (m_grant_bin)
|
|
|
);
|
);
|
|
|
|
|
binary_mux #(
|
binary_mux #(
|
.IN_WIDTH (M),
|
.IN_WIDTH (M),
|
.OUT_WIDTH (1)
|
.OUT_WIDTH (1)
|
)
|
)
|
m_we_mux
|
m_we_mux
|
(
|
(
|
.mux_in (m_we_i_all),
|
.mux_in (m_we_i_all),
|
.mux_out (m_grant_we),
|
.mux_out (m_grant_we),
|
.sel (m_grant_bin)
|
.sel (m_grant_bin)
|
|
|
);
|
);
|
|
|
|
|
/*
|
/*
|
binary_mux #(
|
binary_mux #(
|
.IN_WIDTH (M),
|
.IN_WIDTH (M),
|
.OUT_WIDTH (1)
|
.OUT_WIDTH (1)
|
)
|
)
|
m_stb_mux
|
m_stb_mux
|
(
|
(
|
.mux_in (m_stb_i_all),
|
.mux_in (m_stb_i_all),
|
.mux_out (m_grant_stb),
|
.mux_out (m_grant_stb),
|
.sel (m_grant_bin)
|
.sel (m_grant_bin)
|
|
|
);
|
);
|
|
|
|
|
|
|
binary_mux #(
|
binary_mux #(
|
.IN_WIDTH (M),
|
.IN_WIDTH (M),
|
.OUT_WIDTH (1)
|
.OUT_WIDTH (1)
|
)
|
)
|
m_cyc_mux
|
m_cyc_mux
|
(
|
(
|
.mux_in (m_cyc_i_all),
|
.mux_in (m_cyc_i_all),
|
.mux_out (m_grant_cyc),
|
.mux_out (m_grant_cyc),
|
.sel (m_grant_bin)
|
.sel (m_grant_bin)
|
|
|
);
|
);
|
*/
|
*/
|
// if m_grant_one_hot is zero the stb and cyc must not be asserted hence have to use one-hot mux
|
// if m_grant_one_hot is zero the stb and cyc must not be asserted hence have to use one-hot mux
|
|
|
|
|
one_hot_mux #(
|
one_hot_mux #(
|
.IN_WIDTH(M),
|
.IN_WIDTH(M),
|
.SEL_WIDTH(M),
|
.SEL_WIDTH(M),
|
.OUT_WIDTH(1)
|
.OUT_WIDTH(1)
|
)
|
)
|
m_stb_mux
|
m_stb_mux
|
(
|
(
|
.mux_in(m_stb_i_all),
|
.mux_in(m_stb_i_all),
|
.mux_out(m_grant_stb),
|
.mux_out(m_grant_stb),
|
.sel(m_grant_onehot)
|
.sel(m_grant_onehot)
|
|
|
);
|
);
|
|
|
|
|
one_hot_mux #(
|
one_hot_mux #(
|
.IN_WIDTH(M),
|
.IN_WIDTH(M),
|
.SEL_WIDTH(M),
|
.SEL_WIDTH(M),
|
.OUT_WIDTH(1)
|
.OUT_WIDTH(1)
|
)
|
)
|
m_cyc_mux
|
m_cyc_mux
|
(
|
(
|
.mux_in(m_cyc_i_all),
|
.mux_in(m_cyc_i_all),
|
.mux_out(m_grant_cyc),
|
.mux_out(m_grant_cyc),
|
.sel(m_grant_onehot)
|
.sel(m_grant_onehot)
|
|
|
);
|
);
|
|
|
|
|
|
|
|
|
|
|
generate
|
generate
|
if(M > 1) begin
|
if(M > 1) begin
|
// round roubin arbiter
|
// round roubin arbiter
|
bus_arbiter # (
|
bus_arbiter # (
|
.M (M)
|
.M (M)
|
)
|
)
|
arbiter
|
arbiter
|
(
|
(
|
.request (m_cyc_i_all),
|
.request (m_cyc_i_all),
|
.grant (m_grant_onehot),
|
.grant (m_grant_onehot),
|
.clk (clk),
|
.clk (clk),
|
.reset (reset)
|
.reset (reset)
|
);
|
);
|
end else begin // if we have just one master there is no needs for arbitration
|
end else begin // if we have just one master there is no needs for arbitration
|
assign m_grant_onehot = m_cyc_i_all;
|
assign m_grant_onehot = m_cyc_i_all;
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|
/**************
|
/**************
|
|
|
bus_arbiter
|
bus_arbiter
|
|
|
**************/
|
**************/
|
|
|
module bus_arbiter # (
|
module bus_arbiter # (
|
parameter M = 4
|
parameter M = 4
|
)
|
)
|
(
|
(
|
request,
|
request,
|
grant,
|
grant,
|
clk,
|
clk,
|
reset
|
reset
|
);
|
);
|
|
|
input [M-1 : 0] request;
|
input [M-1 : 0] request;
|
output [M-1 : 0] grant;
|
output [M-1 : 0] grant;
|
input clk, reset;
|
input clk, reset;
|
|
|
wire comreq;
|
wire comreq;
|
wire [M-1 : 0] one_hot_arb_req, one_hot_arb_grant;
|
wire [M-1 : 0] one_hot_arb_req, one_hot_arb_grant;
|
reg [M-1 : 0] grant_registered;
|
reg [M-1 : 0] grant_registered;
|
|
|
assign one_hot_arb_req = request & {M{~comreq}};
|
assign one_hot_arb_req = request & {M{~comreq}};
|
assign grant = grant_registered;
|
assign grant = grant_registered;
|
|
|
assign comreq = |(grant & request);
|
assign comreq = |(grant & request);
|
|
|
|
`ifdef SYNC_RESET_MODE
|
|
always @ (posedge clk )begin
|
|
`else
|
always @ (posedge clk or posedge reset) begin
|
always @ (posedge clk or posedge reset) begin
|
|
`endif
|
|
|
if (reset) begin
|
if (reset) begin
|
grant_registered <= {M{1'b0}};
|
grant_registered <= {M{1'b0}};
|
end else begin
|
end else begin
|
if(~comreq) grant_registered <= one_hot_arb_grant;
|
if(~comreq) grant_registered <= one_hot_arb_grant;
|
end
|
end
|
end//always
|
end//always
|
|
|
|
|
arbiter #(
|
arbiter #(
|
.ARBITER_WIDTH (M )
|
.ARBITER_WIDTH (M )
|
)
|
)
|
the_combinational_arbiter
|
the_combinational_arbiter
|
(
|
(
|
.request (one_hot_arb_req),
|
.request (one_hot_arb_req),
|
.grant (one_hot_arb_grant),
|
.grant (one_hot_arb_grant),
|
.any_grant (),
|
.any_grant (),
|
.clk (clk),
|
.clk (clk),
|
.reset (reset)
|
.reset (reset)
|
);
|
);
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
