/* $Id: msr.hh,v 1.9 2008-04-28 20:29:15 sybreon Exp $
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/* $Id: msr.hh,v 1.9 2008-04-28 20:29:15 sybreon Exp $
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**
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**
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** AEMB2 HI-PERFORMANCE CPU
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** AEMB2 HI-PERFORMANCE CPU
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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**
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU General Public License as published by
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** under the terms of the GNU General Public License as published by
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** the Free Software Foundation, either version 3 of the License, or
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** the Free Software Foundation, either version 3 of the License, or
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** (at your option) any later version.
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** (at your option) any later version.
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**
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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** License for more details.
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** License for more details.
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**
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**
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** You should have received a copy of the GNU General Public License
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** You should have received a copy of the GNU General Public License
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** along with AEMB. If not, see .
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** along with AEMB. If not, see .
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*/
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*/
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/**
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/**
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Basic MSR functions
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Basic MSR functions
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@file msr.hh
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@file msr.hh
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These functions provide read/write access to the Machine Status
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These functions provide read/write access to the Machine Status
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Register. It also contains the bit definitions of the register.
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Register. It also contains the bit definitions of the register.
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*/
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*/
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#ifndef _AEMB_MSR_HH
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#ifndef _AEMB_MSR_HH
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#define _AEMB_MSR_HH
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#define _AEMB_MSR_HH
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// STANDARD BITS
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// STANDARD BITS
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#define AEMB_MSR_BE (1 << 0) ///< Buslock Enable
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#define AEMB_MSR_BE (1 << 0) ///< Buslock Enable
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#define AEMB_MSR_IE (1 << 1) ///< Interrupt Enable
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#define AEMB_MSR_IE (1 << 1) ///< Interrupt Enable
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#define AEMB_MSR_C (1 << 2) ///< Arithmetic Carry
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#define AEMB_MSR_C (1 << 2) ///< Arithmetic Carry
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#define AEMB_MSR_BIP (1 << 3) ///< Break in Progress
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#define AEMB_MSR_BIP (1 << 3) ///< Break in Progress
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#define AEMB_MSR_EE (1 << 8) ///< Exception Enable
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#define AEMB_MSR_EE (1 << 8) ///< Exception Enable
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#define AEMB_MSR_EIP (1 << 9) ///< Exception in Progress
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#define AEMB_MSR_EIP (1 << 9) ///< Exception in Progress
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#define AEMB_MSR_ITE (1 << 5) ///< Instruction Cache Enable
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#define AEMB_MSR_ITE (1 << 5) ///< Instruction Cache Enable
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#define AEMB_MSR_DZ (1 << 6) ///< Division by Zero
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#define AEMB_MSR_DZ (1 << 6) ///< Division by Zero
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#define AEMB_MSR_DTE (1 << 7) ///< Data Cache Enable
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#define AEMB_MSR_DTE (1 << 7) ///< Data Cache Enable
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// CUSTOM BITS
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// CUSTOM BITS
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#define AEMB_MSR_MTX (1 << 4) ///< Hardware Mutex
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#define AEMB_MSR_MTX (1 << 4) ///< Hardware Mutex
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#define AEMB_MSR_PHA (1 << 29) ///< Hardware Thread Phase
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#define AEMB_MSR_PHA (1 << 29) ///< Hardware Thread Phase
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#define AEMB_MSR_HTX (1 << 30) ///< Hardware Threads Extension
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#define AEMB_MSR_HTX (1 << 30) ///< Hardware Threads Extension
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#define AEMB_MSR_CC (1 << 31) ///< Carry Copy
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#define AEMB_MSR_CC (1 << 31) ///< Carry Copy
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#ifdef __cplusplus
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#ifdef __cplusplus
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extern "C" {
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extern "C" {
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#endif
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#endif
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/**
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/**
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Read the value of the MSR register
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Read the value of the MSR register
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@return register contents
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@return register contents
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*/
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*/
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inline int aembGetMSR()
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static inline int aembGetMSR()
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{
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{
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int rmsr;
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int rmsr;
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asm volatile ("mfs %0, rmsr":"=r"(rmsr));
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asm volatile ("mfs %0, rmsr":"=r"(rmsr));
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return rmsr;
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return rmsr;
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}
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}
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/**
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/**
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Write a value to the MSR register
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Write a value to the MSR register
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@param rmsr value to write
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@param rmsr value to write
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*/
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*/
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inline void aembPutMSR(int rmsr)
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static inline void aembPutMSR(int rmsr)
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{
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{
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asm volatile ("mts rmsr, %0"::"r"(rmsr));
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asm volatile ("mts rmsr, %0"::"r"(rmsr));
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}
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}
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/**
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/**
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Read and clear the MSR
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Read and clear the MSR
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@param rmsk clear mask
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@param rmsk clear mask
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@return msr value
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@return msr value
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*/
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*/
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inline int aembClrMSR(const short rmsk)
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static inline int aembClrMSR(const short rmsk)
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{
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{
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int tmp;
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int tmp;
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//asm volatile ("msrclr %0, %1":"=r"(tmp):"K"(rmsk):"memory");
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//asm volatile ("msrclr %0, %1":"=r"(tmp):"K"(rmsk):"memory");
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return tmp;
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return tmp;
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}
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}
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/**
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/**
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Read and set the MSR
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Read and set the MSR
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@param rmsk set mask
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@param rmsk set mask
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@return msr value
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@return msr value
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*/
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*/
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inline int aembSetMSR(const short rmsk)
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static inline int aembSetMSR(const short rmsk)
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{
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{
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int tmp;
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int tmp;
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//asm volatile ("msrset %0, %1":"=r"(tmp):"K"(rmsk):"memory");
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//asm volatile ("msrset %0, %1":"=r"(tmp):"K"(rmsk):"memory");
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return tmp;
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return tmp;
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}
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}
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/** Enable global interrupts */
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/** Enable global interrupts */
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inline int aembEnableInterrupts()
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static inline int aembEnableInterrupts()
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{
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{
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int msr;
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int msr;
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asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_IE));
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asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_IE));
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return msr;
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return msr;
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}
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}
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/** Disable global interrupts */
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/** Disable global interrupts */
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inline int aembDisableInterrupts()
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static inline int aembDisableInterrupts()
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{
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{
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int msr;
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int msr;
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asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_IE));
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asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_IE));
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return msr;
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return msr;
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}
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}
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/** Enable global exception */
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/** Enable global exception */
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inline int aembEnableException()
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static inline int aembEnableException()
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{
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{
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int msr;
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int msr;
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asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_EE));
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asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_EE));
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return msr;
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return msr;
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}
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}
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/** Disable global exception */
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/** Disable global exception */
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inline int aembDisableException()
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static inline int aembDisableException()
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{
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{
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int msr;
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int msr;
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asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_EE));
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asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_EE));
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return msr;
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return msr;
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}
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}
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/** Enable data caches */
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/** Enable data caches */
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inline int aembEnableDataTag()
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static inline int aembEnableDataTag()
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{
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{
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int msr;
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int msr;
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asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_DTE));
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asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_DTE));
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return msr;
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return msr;
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}
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}
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/** Disable data caches */
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/** Disable data caches */
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inline int aembDisableDataTag()
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static inline int aembDisableDataTag()
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{
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{
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int msr;
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int msr;
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asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_DTE));
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asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_DTE));
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return msr;
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return msr;
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}
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}
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/** Enable inst caches */
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/** Enable inst caches */
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inline int aembEnableInstTag()
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static inline int aembEnableInstTag()
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{
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{
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int msr;
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int msr;
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asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_ITE));
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asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_ITE));
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return msr;
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return msr;
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}
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}
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/** Disable inst caches */
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/** Disable inst caches */
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inline int aembDisableInstTag()
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static inline int aembDisableInstTag()
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{
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{
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int msr;
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int msr;
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asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_ITE));
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asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_ITE));
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return msr;
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return msr;
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}
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}
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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#endif
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#endif
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#endif
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#endif
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