/* $Id: aeMB2_sim.v,v 1.2 2007-12-29 00:31:48 sybreon Exp $
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/* $Id: aeMB2_sim.v,v 1.2 2007-12-29 00:31:48 sybreon Exp $
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**
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**
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** AEMB2 SIMULATION WRAPPER
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** AEMB2 SIMULATION WRAPPER
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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**
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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** License, or (at your option) any later version.
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**
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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** Public License for more details.
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**
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**
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** You should have received a copy of the GNU Lesser General Public
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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*/
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*/
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`timescale 1ns/1ps
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`timescale 1ns/1ps
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module aeMB2_sim (/*AUTOARG*/
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module aeMB2_sim (/*AUTOARG*/
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// Outputs
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// Outputs
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iwb_wre_o, iwb_tga_o, iwb_stb_o, iwb_adr_o, dwb_wre_o, dwb_tga_o,
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iwb_wre_o, iwb_tga_o, iwb_stb_o, iwb_adr_o, dwb_wre_o, dwb_tga_o,
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dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_cyc_o, dwb_adr_o, cwb_wre_o,
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dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_cyc_o, dwb_adr_o, cwb_wre_o,
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cwb_tga_o, cwb_stb_o, cwb_sel_o, cwb_dat_o, cwb_adr_o,
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cwb_tga_o, cwb_stb_o, cwb_sel_o, cwb_dat_o, cwb_adr_o,
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// Inputs
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// Inputs
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sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
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sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
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dwb_ack_i, cwb_dat_i, cwb_ack_i
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dwb_ack_i, cwb_dat_i, cwb_ack_i
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);
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);
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parameter IWB=16;
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parameter IWB=16;
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parameter DWB=16;
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parameter DWB=16;
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parameter TXE = 1; ///< thread execution enable
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parameter TXE = 1; ///< thread execution enable
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parameter MUL = 1; ///< enable hardware multiplier
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parameter MUL = 1; ///< enable hardware multiplier
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parameter BSF = 1; ///< enable barrel shifter
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parameter BSF = 1; ///< enable barrel shifter
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parameter FSL = 1; ///< enable FSL bus
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parameter FSL = 1; ///< enable FSL bus
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parameter DIV = 0; ///< enable hardware divider
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parameter DIV = 0; ///< enable hardware divider
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/*AUTOOUTPUT*/
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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// Beginning of automatic outputs (from unused autoinst outputs)
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output [6:2] cwb_adr_o; // From sim of aeMB2_edk32.v
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output [6:2] cwb_adr_o; // From sim of aeMB2_edk32.v
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output [31:0] cwb_dat_o; // From sim of aeMB2_edk32.v
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output [31:0] cwb_dat_o; // From sim of aeMB2_edk32.v
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output [3:0] cwb_sel_o; // From sim of aeMB2_edk32.v
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output [3:0] cwb_sel_o; // From sim of aeMB2_edk32.v
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output cwb_stb_o; // From sim of aeMB2_edk32.v
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output cwb_stb_o; // From sim of aeMB2_edk32.v
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output [1:0] cwb_tga_o; // From sim of aeMB2_edk32.v
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output [1:0] cwb_tga_o; // From sim of aeMB2_edk32.v
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output cwb_wre_o; // From sim of aeMB2_edk32.v
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output cwb_wre_o; // From sim of aeMB2_edk32.v
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output [DWB-1:2] dwb_adr_o; // From sim of aeMB2_edk32.v
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output [DWB-1:2] dwb_adr_o; // From sim of aeMB2_edk32.v
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output dwb_cyc_o; // From sim of aeMB2_edk32.v
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output dwb_cyc_o; // From sim of aeMB2_edk32.v
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output [31:0] dwb_dat_o; // From sim of aeMB2_edk32.v
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output [31:0] dwb_dat_o; // From sim of aeMB2_edk32.v
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output [3:0] dwb_sel_o; // From sim of aeMB2_edk32.v
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output [3:0] dwb_sel_o; // From sim of aeMB2_edk32.v
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output dwb_stb_o; // From sim of aeMB2_edk32.v
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output dwb_stb_o; // From sim of aeMB2_edk32.v
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output dwb_tga_o; // From sim of aeMB2_edk32.v
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output dwb_tga_o; // From sim of aeMB2_edk32.v
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output dwb_wre_o; // From sim of aeMB2_edk32.v
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output dwb_wre_o; // From sim of aeMB2_edk32.v
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output [IWB-1:2] iwb_adr_o; // From sim of aeMB2_edk32.v
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output [IWB-1:2] iwb_adr_o; // From sim of aeMB2_edk32.v
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output iwb_stb_o; // From sim of aeMB2_edk32.v
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output iwb_stb_o; // From sim of aeMB2_edk32.v
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output iwb_tga_o; // From sim of aeMB2_edk32.v
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output iwb_tga_o; // From sim of aeMB2_edk32.v
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output iwb_wre_o; // From sim of aeMB2_edk32.v
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output iwb_wre_o; // From sim of aeMB2_edk32.v
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// End of automatics
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// End of automatics
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/*AUTOINPUT*/
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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// Beginning of automatic inputs (from unused autoinst inputs)
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input cwb_ack_i; // To sim of aeMB2_edk32.v
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input cwb_ack_i; // To sim of aeMB2_edk32.v
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input [31:0] cwb_dat_i; // To sim of aeMB2_edk32.v
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input [31:0] cwb_dat_i; // To sim of aeMB2_edk32.v
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input dwb_ack_i; // To sim of aeMB2_edk32.v
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input dwb_ack_i; // To sim of aeMB2_edk32.v
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input [31:0] dwb_dat_i; // To sim of aeMB2_edk32.v
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input [31:0] dwb_dat_i; // To sim of aeMB2_edk32.v
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input iwb_ack_i; // To sim of aeMB2_edk32.v
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input iwb_ack_i; // To sim of aeMB2_edk32.v
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input [31:0] iwb_dat_i; // To sim of aeMB2_edk32.v
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input [31:0] iwb_dat_i; // To sim of aeMB2_edk32.v
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input sys_clk_i; // To sim of aeMB2_edk32.v
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input sys_clk_i; // To sim of aeMB2_edk32.v
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input sys_int_i; // To sim of aeMB2_edk32.v
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input sys_int_i; // To sim of aeMB2_edk32.v
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input sys_rst_i; // To sim of aeMB2_edk32.v
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input sys_rst_i; // To sim of aeMB2_edk32.v
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// End of automatics
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// End of automatics
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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aeMB2_edk32
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aeMB2_edk32
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#(/*AUTOINSTPARAM*/
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#(/*AUTOINSTPARAM*/
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// Parameters
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// Parameters
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.IWB (IWB),
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.IWB (IWB),
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.DWB (DWB),
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.DWB (DWB),
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.TXE (TXE),
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.TXE (TXE),
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.MUL (MUL),
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.MUL (MUL),
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.BSF (BSF),
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.BSF (BSF),
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.FSL (FSL))
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.FSL (FSL))
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sim
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sim
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.cwb_adr_o (cwb_adr_o[6:2]),
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.cwb_adr_o (cwb_adr_o[6:2]),
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.cwb_dat_o (cwb_dat_o[31:0]),
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.cwb_dat_o (cwb_dat_o[31:0]),
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.cwb_sel_o (cwb_sel_o[3:0]),
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.cwb_sel_o (cwb_sel_o[3:0]),
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.cwb_stb_o (cwb_stb_o),
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.cwb_stb_o (cwb_stb_o),
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.cwb_tga_o (cwb_tga_o[1:0]),
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.cwb_tga_o (cwb_tga_o[1:0]),
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.cwb_wre_o (cwb_wre_o),
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.cwb_wre_o (cwb_wre_o),
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.dwb_adr_o (dwb_adr_o[DWB-1:2]),
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.dwb_adr_o (dwb_adr_o[DWB-1:2]),
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.dwb_cyc_o (dwb_cyc_o),
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.dwb_cyc_o (dwb_cyc_o),
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.dwb_dat_o (dwb_dat_o[31:0]),
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.dwb_dat_o (dwb_dat_o[31:0]),
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.dwb_sel_o (dwb_sel_o[3:0]),
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.dwb_sel_o (dwb_sel_o[3:0]),
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.dwb_stb_o (dwb_stb_o),
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.dwb_stb_o (dwb_stb_o),
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.dwb_tga_o (dwb_tga_o),
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.dwb_tga_o (dwb_tga_o),
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.dwb_wre_o (dwb_wre_o),
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.dwb_wre_o (dwb_wre_o),
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.iwb_adr_o (iwb_adr_o[IWB-1:2]),
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.iwb_adr_o (iwb_adr_o[IWB-1:2]),
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.iwb_stb_o (iwb_stb_o),
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.iwb_stb_o (iwb_stb_o),
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.iwb_tga_o (iwb_tga_o),
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.iwb_tga_o (iwb_tga_o),
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.iwb_wre_o (iwb_wre_o),
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.iwb_wre_o (iwb_wre_o),
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// Inputs
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// Inputs
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.cwb_ack_i (cwb_ack_i),
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.cwb_ack_i (cwb_ack_i),
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.cwb_dat_i (cwb_dat_i[31:0]),
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.cwb_dat_i (cwb_dat_i[31:0]),
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.dwb_ack_i (dwb_ack_i),
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.dwb_ack_i (dwb_ack_i),
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.dwb_dat_i (dwb_dat_i[31:0]),
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.dwb_dat_i (dwb_dat_i[31:0]),
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.iwb_ack_i (iwb_ack_i),
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.iwb_ack_i (iwb_ack_i),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.sys_clk_i (sys_clk_i),
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.sys_clk_i (sys_clk_i),
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.sys_int_i (sys_int_i),
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.sys_int_i (sys_int_i),
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.sys_rst_i (sys_rst_i));
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.sys_rst_i (sys_rst_i));
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// synopsys translate_off
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// synopsys translate_off
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wire [31:0] iwb_adr = {iwb_adr_o, 2'd0};
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wire [31:0] iwb_adr = {iwb_adr_o, 2'd0};
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wire [31:0] dwb_adr = {dwb_adr_o, 2'd0};
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wire [31:0] dwb_adr = {dwb_adr_o, 2'd0};
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wire [31:0] wMSR = sim.aslu.wMSR[31:0];
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wire [31:0] wMSR = sim.aslu.wMSR[31:0];
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always @(posedge sim.clk_i) if (sim.ena_i) begin
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always @(posedge sim.clk_i) if (sim.ena_i) begin
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$write ("\n", ($stime/10));
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$write ("\n", ($stime/10));
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$writeh (" T", sim.pha_i);
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$write (" T", sim.pha_i);
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$writeh(" PC=", iwb_adr);
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$write(" PC=", iwb_adr);
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$writeh ("\t| ");
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$write ("\t| ");
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case (sim.rOPC_IF)
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case (sim.rOPC_IF)
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6'o00: if (sim.rRD_IF == 0) $write(" "); else $write("ADD");
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6'o00: if (sim.rRD_IF == 0) $write(" "); else $write("ADD");
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6'o01: $write("SUB");
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6'o01: $write("SUB");
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6'o02: $write("ADDC");
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6'o02: $write("ADDC");
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6'o03: $write("SUBC");
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6'o03: $write("SUBC");
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6'o04: $write("ADDK");
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6'o04: $write("ADDK");
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6'o05: case (sim.rIMM_IF[1:0])
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6'o05: case (sim.rIMM_IF[1:0])
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2'o0: $write("SUBK");
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2'o0: $write("SUBK");
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2'o1: $write("CMP");
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2'o1: $write("CMP");
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2'o3: $write("CMPU");
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2'o3: $write("CMPU");
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default: $write("XXX");
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default: $write("XXX");
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endcase // case (sim.rIMM_IF[1:0])
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endcase // case (sim.rIMM_IF[1:0])
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6'o06: $write("ADDKC");
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6'o06: $write("ADDKC");
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6'o07: $write("SUBKC");
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6'o07: $write("SUBKC");
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6'o10: $write("ADDI");
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6'o10: $write("ADDI");
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6'o11: $write("SUBI");
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6'o11: $write("SUBI");
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6'o12: $write("ADDIC");
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6'o12: $write("ADDIC");
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6'o13: $write("SUBIC");
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6'o13: $write("SUBIC");
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6'o14: $write("ADDIK");
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6'o14: $write("ADDIK");
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6'o15: $write("SUBIK");
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6'o15: $write("SUBIK");
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6'o16: $write("ADDIKC");
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6'o16: $write("ADDIKC");
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6'o17: $write("SUBIKC");
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6'o17: $write("SUBIKC");
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6'o20: $write("MUL");
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6'o20: $write("MUL");
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6'o21: case (sim.rALT_IF[10:9])
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6'o21: case (sim.rALT_IF[10:9])
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2'o0: $write("BSRL");
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2'o0: $write("BSRL");
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2'o1: $write("BSRA");
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2'o1: $write("BSRA");
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2'o2: $write("BSLL");
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2'o2: $write("BSLL");
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default: $write("XXX");
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default: $write("XXX");
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endcase // case (sim.rALT_IF[10:9])
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endcase // case (sim.rALT_IF[10:9])
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6'o22: $write("IDIV");
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6'o22: $write("IDIV");
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6'o30: $write("MULI");
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6'o30: $write("MULI");
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6'o31: case (sim.rALT_IF[10:9])
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6'o31: case (sim.rALT_IF[10:9])
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2'o0: $write("BSRLI");
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2'o0: $write("BSRLI");
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2'o1: $write("BSRAI");
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2'o1: $write("BSRAI");
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2'o2: $write("BSLLI");
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2'o2: $write("BSLLI");
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default: $write("XXX");
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default: $write("XXX");
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endcase // case (sim.rALT_IF[10:9])
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endcase // case (sim.rALT_IF[10:9])
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6'o33: case (sim.rRB_IF[4:2])
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6'o33: case (sim.rRB_IF[4:2])
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3'o0: $write("GET");
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3'o0: $write("GET");
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3'o4: $write("PUT");
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3'o4: $write("PUT");
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3'o2: $write("NGET");
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3'o2: $write("NGET");
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3'o6: $write("NPUT");
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3'o6: $write("NPUT");
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3'o1: $write("CGET");
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3'o1: $write("CGET");
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3'o5: $write("CPUT");
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3'o5: $write("CPUT");
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3'o3: $write("NCGET");
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3'o3: $write("NCGET");
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3'o7: $write("NCPUT");
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3'o7: $write("NCPUT");
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endcase // case (sim.rRB_IF[4:2])
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endcase // case (sim.rRB_IF[4:2])
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6'o40: $write("OR");
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6'o40: $write("OR");
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6'o41: $write("AND");
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6'o41: $write("AND");
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6'o42: if (sim.rRD_IF == 0) $write(" "); else $write("XOR");
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6'o42: if (sim.rRD_IF == 0) $write(" "); else $write("XOR");
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6'o43: $write("ANDN");
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6'o43: $write("ANDN");
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6'o44: case (sim.rIMM_IF[6:5])
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6'o44: case (sim.rIMM_IF[6:5])
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2'o0: $write("SRA");
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2'o0: $write("SRA");
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2'o1: $write("SRC");
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2'o1: $write("SRC");
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2'o2: $write("SRL");
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2'o2: $write("SRL");
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2'o3: if (sim.rIMM_IF[0]) $write("SEXT16"); else $write("SEXT8");
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2'o3: if (sim.rIMM_IF[0]) $write("SEXT16"); else $write("SEXT8");
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endcase // case (sim.rIMM_IF[6:5])
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endcase // case (sim.rIMM_IF[6:5])
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6'o45: $write("MOV");
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6'o45: $write("MOV");
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6'o46: case (sim.rRA_IF[3:2])
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6'o46: case (sim.rRA_IF[3:2])
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3'o0: $write("BR");
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3'o0: $write("BR");
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3'o1: $write("BRL");
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3'o1: $write("BRL");
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3'o2: $write("BRA");
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3'o2: $write("BRA");
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3'o3: $write("BRAL");
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3'o3: $write("BRAL");
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endcase // case (sim.rRA_IF[3:2])
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endcase // case (sim.rRA_IF[3:2])
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6'o47: case (sim.rRD_IF[2:0])
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6'o47: case (sim.rRD_IF[2:0])
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3'o0: $write("BEQ");
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3'o0: $write("BEQ");
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3'o1: $write("BNE");
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3'o1: $write("BNE");
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3'o2: $write("BLT");
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3'o2: $write("BLT");
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3'o3: $write("BLE");
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3'o3: $write("BLE");
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3'o4: $write("BGT");
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3'o4: $write("BGT");
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3'o5: $write("BGE");
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3'o5: $write("BGE");
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default: $write("XXX");
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default: $write("XXX");
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endcase // case (sim.rRD_IF[2:0])
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endcase // case (sim.rRD_IF[2:0])
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6'o50: $write("ORI");
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6'o50: $write("ORI");
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6'o51: $write("ANDI");
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6'o51: $write("ANDI");
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6'o52: $write("XORI");
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6'o52: $write("XORI");
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6'o53: $write("ANDNI");
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6'o53: $write("ANDNI");
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6'o54: $write("IMMI");
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6'o54: $write("IMMI");
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6'o55: case (sim.rRD_IF[1:0])
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6'o55: case (sim.rRD_IF[1:0])
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2'o0: $write("RTSD");
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2'o0: $write("RTSD");
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2'o1: $write("RTID");
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2'o1: $write("RTID");
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2'o2: $write("RTBD");
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2'o2: $write("RTBD");
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default: $write("XXX");
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default: $write("XXX");
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endcase // case (sim.rRD_IF[1:0])
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endcase // case (sim.rRD_IF[1:0])
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6'o56: case (sim.rRA_IF[3:2])
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6'o56: case (sim.rRA_IF[3:2])
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3'o0: $write("BRI");
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3'o0: $write("BRI");
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3'o1: $write("BRLI");
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3'o1: $write("BRLI");
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3'o2: $write("BRAI");
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3'o2: $write("BRAI");
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3'o3: $write("BRALI");
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3'o3: $write("BRALI");
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endcase // case (sim.rRA_IF[3:2])
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endcase // case (sim.rRA_IF[3:2])
|
6'o57: case (sim.rRD_IF[2:0])
|
6'o57: case (sim.rRD_IF[2:0])
|
3'o0: $write("BEQI");
|
3'o0: $write("BEQI");
|
3'o1: $write("BNEI");
|
3'o1: $write("BNEI");
|
3'o2: $write("BLTI");
|
3'o2: $write("BLTI");
|
3'o3: $write("BLEI");
|
3'o3: $write("BLEI");
|
3'o4: $write("BGTI");
|
3'o4: $write("BGTI");
|
3'o5: $write("BGEI");
|
3'o5: $write("BGEI");
|
default: $write("XXX");
|
default: $write("XXX");
|
endcase // case (sim.rRD_IF[2:0])
|
endcase // case (sim.rRD_IF[2:0])
|
|
|
6'o60: $write("LBU");
|
6'o60: $write("LBU");
|
6'o61: $write("LHU");
|
6'o61: $write("LHU");
|
6'o62: $write("LW");
|
6'o62: $write("LW");
|
6'o64: $write("SB");
|
6'o64: $write("SB");
|
6'o65: $write("SH");
|
6'o65: $write("SH");
|
6'o66: $write("SW");
|
6'o66: $write("SW");
|
|
|
6'o70: $write("LBUI");
|
6'o70: $write("LBUI");
|
6'o71: $write("LHUI");
|
6'o71: $write("LHUI");
|
6'o72: $write("LWI");
|
6'o72: $write("LWI");
|
6'o74: $write("SBI");
|
6'o74: $write("SBI");
|
6'o75: $write("SHI");
|
6'o75: $write("SHI");
|
6'o76: $write("SWI");
|
6'o76: $write("SWI");
|
|
|
default: $write("XXX");
|
default: $write("XXX");
|
endcase // case (sim.rOPC_IF)
|
endcase // case (sim.rOPC_IF)
|
|
|
case (sim.rOPC_IF[3])
|
case (sim.rOPC_IF[3])
|
1'b1: $writeh("\t r",sim.rRD_IF,", r",sim.rRA_IF,", h",sim.rIMM_IF);
|
1'b1: $write("\t r",sim.rRD_IF,", r",sim.rRA_IF,", h",sim.rIMM_IF);
|
1'b0: $writeh("\t r",sim.rRD_IF,", r",sim.rRA_IF,", r",sim.rRB_IF," ");
|
1'b0: $write("\t r",sim.rRD_IF,", r",sim.rRA_IF,", r",sim.rRB_IF," ");
|
endcase // case (sim.rOPC_IF[3])
|
endcase // case (sim.rOPC_IF[3])
|
|
|
if (sim.bpcu.fHZD)
|
if (sim.bpcu.fHZD)
|
$write ("*");
|
$write ("*");
|
|
|
// ALU
|
// ALU
|
$write("\t|");
|
$write("\t|");
|
$writeh(" A=",sim.rOPA_OF);
|
$write(" A=",sim.rOPA_OF);
|
$writeh(" B=",sim.rOPB_OF);
|
$write(" B=",sim.rOPB_OF);
|
$writeh(" C=",sim.rOPX_OF);
|
$write(" C=",sim.rOPX_OF);
|
$writeh(" M=",sim.rOPM_OF);
|
$write(" M=",sim.rOPM_OF);
|
|
|
$writeh(" MSR=", wMSR," ");
|
$write(" MSR=", wMSR," ");
|
|
|
case (sim.rALU_OF)
|
case (sim.rALU_OF)
|
3'o0: $write(" ADD");
|
3'o0: $write(" ADD");
|
3'o1: $write(" BSF");
|
3'o1: $write(" BSF");
|
3'o2: $write(" SLM");
|
3'o2: $write(" SLM");
|
3'o3: $write(" MOV");
|
3'o3: $write(" MOV");
|
default: $write(" XXX");
|
default: $write(" XXX");
|
endcase // case (sim.rALU_OF)
|
endcase // case (sim.rALU_OF)
|
|
|
// MA
|
// MA
|
$write ("\t| ");
|
$write ("\t| ");
|
if (sim.dwb_stb_o)
|
if (sim.dwb_stb_o)
|
$writeh("@",sim.rRES_EX);
|
$write("@",sim.rRES_EX);
|
else
|
else
|
$writeh("=",sim.rRES_EX);
|
$write("=",sim.rRES_EX);
|
|
|
|
|
case (sim.rBRA)
|
case (sim.rBRA)
|
2'b00: $write(" ");
|
2'b00: $write(" ");
|
2'b01: $write(".");
|
2'b01: $write(".");
|
2'b10: $write("-");
|
2'b10: $write("-");
|
2'b11: $write("+");
|
2'b11: $write("+");
|
endcase // case (sim.rBRA)
|
endcase // case (sim.rBRA)
|
|
|
// WRITEBACK
|
// WRITEBACK
|
$write("\t|");
|
$write("\t|");
|
|
|
if (|sim.rRD_MA) begin
|
if (|sim.rRD_MA) begin
|
case (sim.rOPD_MA)
|
case (sim.rOPD_MA)
|
2'o2: begin
|
2'o2: begin
|
if (sim.rSEL_MA != 4'h0) $writeh("R",sim.rRD_MA,"=RAM(",sim.regf.rREGD,")");
|
if (sim.rSEL_MA != 4'h0) $write("R",sim.rRD_MA,"=RAM(",sim.regf.rREGD,")");
|
if (sim.rSEL_MA == 4'h0) $writeh("R",sim.rRD_MA,"=FSL(",sim.regf.rREGD,")");
|
if (sim.rSEL_MA == 4'h0) $write("R",sim.rRD_MA,"=FSL(",sim.regf.rREGD,")");
|
end
|
end
|
2'o1: $writeh("R",sim.rRD_MA,"=LNK(",sim.regf.rREGD,")");
|
2'o1: $write("R",sim.rRD_MA,"=LNK(",sim.regf.rREGD,")");
|
2'o0: $writeh("R",sim.rRD_MA,"=ALU(",sim.regf.rREGD,")");
|
2'o0: $write("R",sim.rRD_MA,"=ALU(",sim.regf.rREGD,")");
|
endcase // case (sim.rOPD_MA)
|
endcase // case (sim.rOPD_MA)
|
end
|
end
|
|
|
/*
|
/*
|
// STORE
|
// STORE
|
if (dwb_stb_o & dwb_wre_o) begin
|
if (dwb_stb_o & dwb_wre_o) begin
|
$writeh("RAM(", dwb_adr ,")=", dwb_dat_o);
|
$write("RAM(", dwb_adr ,")=", dwb_dat_o);
|
case (dwb_sel_o)
|
case (dwb_sel_o)
|
4'hF: $write(":L");
|
4'hF: $write(":L");
|
4'h3,4'hC: $write(":W");
|
4'h3,4'hC: $write(":W");
|
4'h1,4'h2,4'h4,4'h8: $write(":B");
|
4'h1,4'h2,4'h4,4'h8: $write(":B");
|
endcase // case (dwb_sel_o)
|
endcase // case (dwb_sel_o)
|
|
|
end
|
end
|
*/
|
*/
|
end // if (sim.ena_i)
|
end // if (sim.ena_i)
|
|
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
endmodule // aeMB2_sim
|
endmodule // aeMB2_sim
|
|
|
/* $Log: not supported by cvs2svn $*/
|
/* $Log: not supported by cvs2svn $*/
|
/* Revision 1.1 2007/12/18 18:54:36 sybreon*/
|
/* Revision 1.1 2007/12/18 18:54:36 sybreon*/
|
/* Partitioned simulation model.*/
|
/* Partitioned simulation model.*/
|
/* */
|
/* */
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
