/******************************************************************************
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/******************************************************************************
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This Source Code Form is subject to the terms of the
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This Source Code Form is subject to the terms of the
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Open Hardware Description License, v. 1.0. If a copy
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Open Hardware Description License, v. 1.0. If a copy
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of the OHDL was not distributed with this file, You
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of the OHDL was not distributed with this file, You
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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Description: True dual port ram with single clock
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Description: True dual port ram with single clock
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Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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******************************************************************************/
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******************************************************************************/
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`timescale 1ns/1ps
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module mor1kx_true_dpram_sclk
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module mor1kx_true_dpram_sclk
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#(
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#(
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parameter ADDR_WIDTH = 32,
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parameter ADDR_WIDTH = 32,
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parameter DATA_WIDTH = 32
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parameter DATA_WIDTH = 32
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)
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)
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(
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(
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input clk,
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input clk,
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input [ADDR_WIDTH-1:0] addr_a,
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input [ADDR_WIDTH-1:0] addr_a,
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input we_a,
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input we_a,
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input [DATA_WIDTH-1:0] din_a,
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input [DATA_WIDTH-1:0] din_a,
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output [DATA_WIDTH-1:0] dout_a,
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output [DATA_WIDTH-1:0] dout_a,
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input [ADDR_WIDTH-1:0] addr_b,
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input [ADDR_WIDTH-1:0] addr_b,
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input we_b,
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input we_b,
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input [DATA_WIDTH-1:0] din_b,
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input [DATA_WIDTH-1:0] din_b,
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output [DATA_WIDTH-1:0] dout_b
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output [DATA_WIDTH-1:0] dout_b
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);
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);
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reg [DATA_WIDTH-1:0] mem[(1<<ADDR_WIDTH)-1:0];
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reg [DATA_WIDTH-1:0] mem[(1<<ADDR_WIDTH)-1:0];
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reg [DATA_WIDTH-1:0] rdata_a;
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reg [DATA_WIDTH-1:0] rdata_a;
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reg [DATA_WIDTH-1:0] rdata_b;
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reg [DATA_WIDTH-1:0] rdata_b;
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assign dout_a = rdata_a;
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assign dout_a = rdata_a;
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assign dout_b = rdata_b;
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assign dout_b = rdata_b;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (we_a) begin
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if (we_a) begin
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mem[addr_a] <= din_a;
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mem[addr_a] <= din_a;
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rdata_a <= din_a;
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rdata_a <= din_a;
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end else begin
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end else begin
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rdata_a <= mem[addr_a];
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rdata_a <= mem[addr_a];
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end
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end
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (we_b) begin
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if (we_b) begin
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mem[addr_b] <= din_b;
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mem[addr_b] <= din_b;
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rdata_b <= din_b;
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rdata_b <= din_b;
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end else begin
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end else begin
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rdata_b <= mem[addr_b];
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rdata_b <= mem[addr_b];
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end
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end
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end
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end
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endmodule
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endmodule
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