### aoR3000
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### aoR3000
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The aoR3000 is a MIPS R3000A compatible core capable of booting the Linux kernel version 3.16 in about 3 seconds and with a rating of 48.74 BogoMIPS. It features a compatible MMU, but no FPU.
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The aoR3000 is a MIPS R3000A compatible core capable of booting the Linux kernel version 3.16 in about 3 seconds and with a rating of 48.74 BogoMIPS. It features a compatible MMU, but no FPU.
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### Current status
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### Current status
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- 11 August 2014 - initial version 1.0.
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- 11 August 2014 - initial version 1.0.
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### Features
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### Features
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The aoR3000 soft processor core has the following features:
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The aoR3000 soft processor core has the following features:
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- 5 stage pipeline (single-issue, in-order, forwarding, hazard detection);
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- 5 stage pipeline (single-issue, in-order, forwarding, hazard detection);
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- implements all MIPS I instructions (this includes the privileged coprocessor 0 instructions);
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- implements all MIPS I instructions (this includes the privileged coprocessor 0 instructions);
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- the MMU in coprocessor 0 is compatible with the R3000A but has more micro-TLB entries: 64 TLB entries, 8 micro-TLB entries for data, 4 micro-TLB entries for instructions;
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- the MMU in coprocessor 0 is compatible with the R3000A but has more micro-TLB entries: 64 TLB entries, 8 micro-TLB entries for data, 4 micro-TLB entries for instructions;
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- 2 kB instruction cache (direct map);
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- 2 kB instruction cache (direct map);
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- 2 kB data cache (direct map);
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- 2 kB data cache (direct map);
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- all exceptions are implemented (bus error exceptions are not issued, exceptions in branch delays are supported);
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- all exceptions are implemented (bus error exceptions are not issued, exceptions in branch delays are supported);
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- the core has one combined instruction/data Altera Avalon MM master interface (with burst and pipelined instruction reads, pipelined data reads);
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- the core has one combined instruction/data Altera Avalon MM master interface (with burst and pipelined instruction reads, pipelined data reads);
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- multiplication implemented in hardware using vendor-independent modules (Altera Quartus II infers embedded multipliers);
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- multiplication implemented in hardware using vendor-independent modules (Altera Quartus II infers embedded multipliers);
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- division implemented in hardware using long division (33 clock cycles required);
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- division implemented in hardware using long division (33 clock cycles required);
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- the core uses 7700 LE and runs at 50 MHz on a Altera Cyclone IV EP4CE115F29C7;
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- the core uses 7700 LE and runs at 50 MHz on a Altera Cyclone IV EP4CE115F29C7;
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- the core is modeled in a vendor-independent subset of Verilog consistent with the requirements of Verilator (fully synchronous design, no vendor specific module instances);
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- the core is modeled in a vendor-independent subset of Verilog consistent with the requirements of Verilator (fully synchronous design, no vendor specific module instances);
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- a Verilator generated executable C++ model is available;
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- a Verilator generated executable C++ model is available;
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- the core was tested and compared with the vmips software R3000 emulator;
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- the core was tested and compared with the vmips software R3000 emulator;
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- the core is chosen to be little-endian and can not be changed by software;
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- the core is chosen to be little-endian and can not be changed by software;
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### Resource usage
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### Resource usage
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The following table shows the result of synthesis using a balanced area/speed optimization:
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The following table shows the result of synthesis using a balanced area/speed optimization:
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+---------------------------------------------------------------------------------+
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+---------------------------------------------------------------------------------+
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; Flow Summary ;
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; Flow Summary ;
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+------------------------------------+--------------------------------------------+
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+------------------------------------+--------------------------------------------+
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; Flow Status ; Successful - Mon Aug 11 21:46:48 2014 ;
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; Flow Status ; Successful - Mon Aug 11 21:46:48 2014 ;
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; Quartus II 64-Bit Version ; 14.0.0 Build 200 06/17/2014 SJ Web Edition ;
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; Quartus II 64-Bit Version ; 14.0.0 Build 200 06/17/2014 SJ Web Edition ;
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; Revision Name ; aoR3000 ;
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; Revision Name ; aoR3000 ;
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; Top-level Entity Name ; aoR3000 ;
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; Top-level Entity Name ; aoR3000 ;
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; Family ; Cyclone IV E ;
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; Family ; Cyclone IV E ;
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; Device ; EP4CE115F29C7 ;
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; Device ; EP4CE115F29C7 ;
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; Timing Models ; Final ;
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; Timing Models ; Final ;
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; Total logic elements ; 7,660 / 114,480 ( 7 % ) ;
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; Total logic elements ; 7,660 / 114,480 ( 7 % ) ;
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; Total combinational functions ; 7,174 / 114,480 ( 6 % ) ;
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; Total combinational functions ; 7,174 / 114,480 ( 6 % ) ;
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; Dedicated logic registers ; 2,633 / 114,480 ( 2 % ) ;
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; Dedicated logic registers ; 2,633 / 114,480 ( 2 % ) ;
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; Total registers ; 2633 ;
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; Total registers ; 2633 ;
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; Total pins ; 115 / 529 ( 22 % ) ;
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; Total pins ; 115 / 529 ( 22 % ) ;
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; Total virtual pins ; 0 ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 61,616 / 3,981,312 ( 2 % ) ;
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; Total memory bits ; 61,616 / 3,981,312 ( 2 % ) ;
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; Embedded Multiplier 9-bit elements ; 8 / 532 ( 2 % ) ;
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; Embedded Multiplier 9-bit elements ; 8 / 532 ( 2 % ) ;
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; Total PLLs ; 0 / 4 ( 0 % ) ;
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; Total PLLs ; 0 / 4 ( 0 % ) ;
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+------------------------------------+--------------------------------------------+
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+------------------------------------+--------------------------------------------+
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+-------------------------------------------------+
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+-------------------------------------------------+
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; Slow 1200mV 85C Model Fmax Summary ;
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; Slow 1200mV 85C Model Fmax Summary ;
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+-----------+-----------------+------------+------+
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+-----------+-----------------+------------+------+
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; Fmax ; Restricted Fmax ; Clock Name ; Note ;
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; Fmax ; Restricted Fmax ; Clock Name ; Note ;
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+-----------+-----------------+------------+------+
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+-----------+-----------------+------------+------+
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; 52.58 MHz ; 52.58 MHz ; clk ; ;
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; 52.58 MHz ; 52.58 MHz ; clk ; ;
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+-----------+-----------------+------------+------+
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+-----------+-----------------+------------+------+
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### Implemented instructions
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### Implemented instructions
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All the MIPS I instructions are implemented:
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All the MIPS I instructions are implemented:
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- ADD, ADDI, ADDIU, ADDU, AND, ANDI, NOR, OR, ORI, SLL, SLLV, SLT, SLTI, SLTIU, SLTU, SRA, SRAV, SRL, SRLV, SUB, SUBU, XOR, XORI, LUI;
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- ADD, ADDI, ADDIU, ADDU, AND, ANDI, NOR, OR, ORI, SLL, SLLV, SLT, SLTI, SLTIU, SLTU, SRA, SRAV, SRL, SRLV, SUB, SUBU, XOR, XORI, LUI;
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- DIV, DIVU, MULT, MULTU, MTHI, MTLO, MFHI, MFLO;
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- DIV, DIVU, MULT, MULTU, MTHI, MTLO, MFHI, MFLO;
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- BREAK, SYSCALL;
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- BREAK, SYSCALL;
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- CFCz, CTCz, LWCz, SWCz;
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- CFCz, CTCz, LWCz, SWCz;
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- MFCz, MTCz;
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- MFCz, MTCz;
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- COPz, RFE, TLBP, TLBR, TLBWI, TLBWR;
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- COPz, RFE, TLBP, TLBR, TLBWI, TLBWR;
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- BEQ, BGEZ, BGEZAL, BGTZ, BLEZ, BLTZ, BLTZAL, BNE, J, JAL, JALR, JR;
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- BEQ, BGEZ, BGEZAL, BGTZ, BLEZ, BLTZ, BLTZAL, BNE, J, JAL, JALR, JR;
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- LB, LBU, LH, LHU, LW, LWL, LWR, SB, SH, SW, SWL, SWR;
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- LB, LBU, LH, LHU, LW, LWL, LWR, SB, SH, SW, SWL, SWR;
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### Running the tests
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### Running the tests
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The aoR3000 core can be converted by Verilator to a C++ executable model. This executable model was compared with the vmips software R3000 emulator (http://vmips.sourceforge.net/) in simulation.
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The aoR3000 core can be converted by Verilator to a C++ executable model. This executable model was compared with the vmips software R3000 emulator (http://vmips.sourceforge.net/) in simulation.
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All instructions were simulated with random register and memory contents. After every instruction the register contents are compared.
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All instructions were simulated with random register and memory contents. After every instruction the register contents are compared.
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To run the test the following steps have to be taken:
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To run the test the following steps have to be taken:
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- compile the vmips emulator in sim/vmips/ by 'make tester';
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- compile the vmips emulator in sim/vmips/ by 'make tester';
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- compile the Verilator aoR3000 model in sim/aoR3000/ by 'make tester';
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- compile the Verilator aoR3000 model in sim/aoR3000/ by 'make tester';
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- choose the test to be run in sim/tester/main_tester.cpp by setting the pointer 'tst_t *tst_current =';
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- choose the test to be run in sim/tester/main_tester.cpp by setting the pointer 'tst_t *tst_current =';
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- compile the tester in sim/tester/ by 'make tester';
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- compile the tester in sim/tester/ by 'make tester';
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- run the tester in sim/tester/ by './main_tester';
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- run the tester in sim/tester/ by './main_tester';
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### GNU toolchain
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### GNU toolchain
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To run programs on the aoR3000 a standard GNU toolchain in required. I used the following options during compilation of the toolchain:
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To run programs on the aoR3000 a standard GNU toolchain in required. I used the following options during compilation of the toolchain:
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- for GNU binutils: './../binutils-2.24.51/configure --prefix= --target=mipsel-unknown-linux-gnu';
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- for GNU binutils: './../binutils-2.24.51/configure --prefix= --target=mipsel-unknown-linux-gnu';
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- for GCC: './../gcc-4.9.1/configure --prefix= --target=mipsel-unknown-linux-gnu --enable-languages=c --disable-threads --disable-shared --disable-libssp --disable-libquadmath --disable-libgomp --disable-libatomic';
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- for GCC: './../gcc-4.9.1/configure --prefix= --target=mipsel-unknown-linux-gnu --enable-languages=c --disable-threads --disable-shared --disable-libssp --disable-libquadmath --disable-libgomp --disable-libatomic';
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The target 'mipsel-unknown-elf' can also be used, but more changes are required to the Linux kernel in that case.
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The target 'mipsel-unknown-elf' can also be used, but more changes are required to the Linux kernel in that case.
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### Building a minimal Linux kernel
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### Building a minimal Linux kernel
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In the directory linux/ there is a minimal set of files required to add the aoR3000 SoC platform to the kernel sources version 3.16. To compile the kernel with these changes just copy/overwrite the files in
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In the directory linux/ there is a minimal set of files required to add the aoR3000 SoC platform to the kernel sources version 3.16. To compile the kernel with these changes just copy/overwrite the files in
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a Linux source tree. After that 'make ARCH=mips CROSS_COMPILE=mipsel-unknown-linux-gnu- vmlinux.bin' to build the kernel.
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a Linux source tree. After that 'make ARCH=mips CROSS_COMPILE=mipsel-unknown-linux-gnu- vmlinux.bin' to build the kernel.
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### Booting the Linux kernel in simulation on a Verilator executable model of the aoR3000
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### Booting the Linux kernel in simulation on a Verilator executable model of the aoR3000
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The booting of the Linux kernel is performed in a similar method like the tests described above. The Verilator executable model of the aoR3000 is run together with the vmips R3000 software simulator to verify
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The booting of the Linux kernel is performed in a similar method like the tests described above. The Verilator executable model of the aoR3000 is run together with the vmips R3000 software simulator to verify
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the correctness of the aoR3000. Every write to memory is checked to confirm that both of the models write the same data at the same time and in the same order.
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the correctness of the aoR3000. Every write to memory is checked to confirm that both of the models write the same data at the same time and in the same order.
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To boot the Linux kernel in simulation the following steps have to be taken:
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To boot the Linux kernel in simulation the following steps have to be taken:
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- compile the vmips emulator in sim/vmips/ by 'make linux';
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- compile the vmips emulator in sim/vmips/ by 'make linux';
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- compile the Verilator aoR3000 model in sim/aoR3000/ by 'make linux';
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- compile the Verilator aoR3000 model in sim/aoR3000/ by 'make linux';
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- compile the tester in sim/tester/ by 'make linux';
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- compile the tester in sim/tester/ by 'make linux';
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- compile the Linux kernel to get the 'vmlinux.bin' file in the arch/mips/boot/ directory;
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- compile the Linux kernel to get the 'vmlinux.bin' file in the arch/mips/boot/ directory;
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- run the tester in sim/tester/ by './main_linux ';
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- run the tester in sim/tester/ by './main_linux ';
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The booting of the Linux kernel takes about 12 minutes on a modern PC (more than 46 milion instructions have to be executed/simulated).
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The booting of the Linux kernel takes about 12 minutes on a modern PC (more than 46 milion instructions have to be executed/simulated).
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The tester simulates the following hardware devices:
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The tester simulates the following hardware devices:
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- an eary Linux console that outputs the data written to that console to the file 'tester/early_console.txt';
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- an eary Linux console that outputs the data written to that console to the file 'tester/early_console.txt';
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- a simple hardware time interrupt device that signals IRQ 0 every 10 miliseconds;
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- a simple hardware time interrupt device that signals IRQ 0 every 10 miliseconds;
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- an Altera JTAG UART connected to a pseudo terminal (Unix PTY). The terminal name is printed just after executing the tester (for example: 'slave pty: /dev/pts/9');
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- an Altera JTAG UART connected to a pseudo terminal (Unix PTY). The terminal name is printed just after executing the tester (for example: 'slave pty: /dev/pts/9');
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To connect to this terminal one can use the following command: 'picocom --nolock /dev/pts/9'. Data can be read and written to this terminal.
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To connect to this terminal one can use the following command: 'picocom --nolock /dev/pts/9'. Data can be read and written to this terminal.
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### Booting the Linux kernel on a FPGA with a synthesized aoR3000
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### Booting the Linux kernel on a FPGA with a synthesized aoR3000
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Together with the aoR3000 core there is also a example SoC in the syn/soc/ directory. It consists of:
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Together with the aoR3000 core there is also a example SoC in the syn/soc/ directory. It consists of:
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- the aoR3000 core;
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- the aoR3000 core;
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- an Altera JTAG UART;
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- an Altera JTAG UART;
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- an Altera SDRAM controller;
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- an Altera SDRAM controller;
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- a simple time interrupt device;
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- a simple time interrupt device;
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- onchip memory for the boot code of the aoR3000;
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- onchip memory for the boot code of the aoR3000;
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- a Altera JTAG to Avalon Master Bridge to upload the Linux kernel;
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- an Altera JTAG to Avalon Master Bridge to upload the Linux kernel;
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The SoC is designed for the Terasic DE2-115 board.
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The SoC is designed for the Terasic DE2-115 board.
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To compile the SoC the following steps have to be taken:
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To compile the SoC the following steps have to be taken:
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- open the Altera Quartus II project in syn/soc/;
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- open the Altera Quartus II project in syn/soc/;
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- open the Qsys tool and generate the HDL;
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- open the Qsys tool and generate the HDL;
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- compile the project;
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- compile the project;
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- program the FPGA with the compiled project;
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- program the FPGA with the compiled project;
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- in the Altera Nios2 Command Shell enter the directory arch/mips/boot/ of the Linux kernel and run 'system-console -cli';
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- in the Altera Nios2 Command Shell enter the directory arch/mips/boot/ of the Linux kernel and run 'system-console -cli';
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- load the Linux kernel binary using the system-console by entering the following TCL commands at the system-console prompt:
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- load the Linux kernel binary using the system-console by entering the following TCL commands at the system-console prompt:
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---
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---
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set srv [claim_service "master" [lindex [get_service_paths "master"] 0] ""];
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set srv [claim_service "master" [lindex [get_service_paths "master"] 0] ""];
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master_write_from_file $srv vmlinux.bin 0;
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master_write_from_file $srv vmlinux.bin 0;
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close_service master $srv;
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close_service master $srv;
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---
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---
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- open the nios2-terminal in a Altera Nios2 Command Shell;
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- open the nios2-terminal in a Altera Nios2 Command Shell;
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- verify that the following text is displayed in the terminal: 'Press any key to boot kernel...';
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- verify that the following text is displayed in the terminal: 'Press any key to boot kernel...';
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- press any key to boot the kernel;
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- press any key to boot the kernel;
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The kernel is booted with the following output displayed on the nios2-terminal:
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The kernel is booted with the following output displayed on the nios2-terminal:
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---
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---
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Press any key to boot kernel...
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Press any key to boot kernel...
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Booting kernel...
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Booting kernel...
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console [ttyJ0] enabled
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console [ttyJ0] enabled
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bootconsole [early0] disabled
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bootconsole [early0] disabled
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Freeing unused kernel memory: 176K (80204000 - 80230000)
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Freeing unused kernel memory: 176K (80204000 - 80230000)
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#
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#
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---
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---
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A shell is run as init in the early root-fs. The early root-fs is the compiled klibc project.
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A shell is run as init in the early root-fs. The early root-fs is the compiled klibc project.
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After running the command dmesg the following output is displayed:
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After running the command dmesg the following output is displayed:
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---
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---
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Linux version 3.16.0 (alek@duke) (gcc version 4.9.1 (GCC) ) #4 Mon Aug 11 23:49:07 CEST 2014
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Linux version 3.16.0 (alek@duke) (gcc version 4.9.1 (GCC) ) #4 Mon Aug 11 23:49:07 CEST 2014
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bootconsole [early0] enabled
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bootconsole [early0] enabled
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CPU0 revision is: 00000230 (R3000A)
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CPU0 revision is: 00000230 (R3000A)
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Determined physical RAM map:
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Determined physical RAM map:
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memory: 08000000 @ 00000000 (usable)
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memory: 08000000 @ 00000000 (usable)
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Initrd not found or empty - disabling initrd
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Initrd not found or empty - disabling initrd
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Zone ranges:
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Zone ranges:
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Normal [mem 0x00000000-0x07ffffff]
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Normal [mem 0x00000000-0x07ffffff]
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Movable zone start for each node
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Movable zone start for each node
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Early memory node ranges
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Early memory node ranges
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node 0: [mem 0x00000000-0x07ffffff]
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node 0: [mem 0x00000000-0x07ffffff]
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On node 0 totalpages: 32768
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On node 0 totalpages: 32768
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free_area_init_node: node 0, pgdat 80203600, node_mem_map 81000000
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free_area_init_node: node 0, pgdat 80203600, node_mem_map 81000000
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Normal zone: 256 pages used for memmap
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Normal zone: 256 pages used for memmap
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Normal zone: 0 pages reserved
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Normal zone: 0 pages reserved
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Normal zone: 32768 pages, LIFO batch:7
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Normal zone: 32768 pages, LIFO batch:7
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Primary instruction cache 2kB, linesize 4 bytes.
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Primary instruction cache 2kB, linesize 4 bytes.
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Primary data cache 2kB, linesize 4 bytes.
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Primary data cache 2kB, linesize 4 bytes.
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pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
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pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
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pcpu-alloc: [0] 0
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pcpu-alloc: [0] 0
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Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512
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Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512
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Kernel command line: console=ttyJ0,115200
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Kernel command line: console=ttyJ0,115200
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PID hash table entries: 512 (order: -1, 2048 bytes)
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PID hash table entries: 512 (order: -1, 2048 bytes)
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Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
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Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
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Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
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Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
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Memory: 127492K/131072K available (1741K kernel code, 101K rwdata, 212K rodata, 176K init, 171K bss, 3580K reserved)
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Memory: 127492K/131072K available (1741K kernel code, 101K rwdata, 212K rodata, 176K init, 171K bss, 3580K reserved)
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SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
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SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
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NR_IRQS:128
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NR_IRQS:128
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Console: colour dummy device 80x25
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Console: colour dummy device 80x25
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Calibrating delay loop... 48.74 BogoMIPS (lpj=243712)
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Calibrating delay loop... 48.74 BogoMIPS (lpj=243712)
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pid_max: default: 32768 minimum: 301
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pid_max: default: 32768 minimum: 301
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Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
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Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
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Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
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Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
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futex hash table entries: 256 (order: -1, 3072 bytes)
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futex hash table entries: 256 (order: -1, 3072 bytes)
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io scheduler noop registered
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io scheduler noop registered
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io scheduler deadline registered
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io scheduler deadline registered
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io scheduler cfq registered (default)
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io scheduler cfq registered (default)
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ttyJ0 at MMIO 0x1ffffff0 (irq = 3, base_baud = 0) is a Altera JTAG UART
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ttyJ0 at MMIO 0x1ffffff0 (irq = 3, base_baud = 0) is a Altera JTAG UART
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console [ttyJ0] enabled
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console [ttyJ0] enabled
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bootconsole [early0] disabled
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bootconsole [early0] disabled
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Freeing unused kernel memory: 176K (80204000 - 80230000)
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Freeing unused kernel memory: 176K (80204000 - 80230000)
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---
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---
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### License
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### License
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Most of the files in this project are under the BSD license. All the Verilog code for the aoR3000 core is under the BSD license.
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Most of the files in this project are under the BSD license. All the Verilog code for the aoR3000 core is under the BSD license.
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A few files are under the GPL license. These files are:
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A few files are under the GPL license. These files are:
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- all files in the sim/vmips/ directory;
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- all files in the sim/vmips/ directory;
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- all files in the linux/ directory;
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- all files in the linux/ directory;
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See the LICENSE file for details.
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See the LICENSE file for details.
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