<##//////////////////////////////////////////////////////////////////
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<##//////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Author: Eyal Hochberg ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// eyal@provartec.com ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////##>
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//////////////////////////////////////////////////////////////////##>
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INCLUDE def_axi2apb.txt
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INCLUDE def_axi2apb.txt
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OUTFILE PREFIX_mux.v
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OUTFILE PREFIX_mux.v
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ITER SX
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ITER SX
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module PREFIX_mux (PORTS);
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module PREFIX_mux (PORTS);
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input clk;
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input clk;
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input reset;
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input reset;
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input [ADDR_BITS-1:0] cmd_addr;
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input [ADDR_BITS-1:0] cmd_addr;
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input psel;
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input psel;
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output [31:0] prdata;
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output [31:0] prdata;
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output pready;
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output pready;
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output pslverr;
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output pslverr;
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output pselSX;
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output pselSX;
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input preadySX;
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input preadySX;
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input pslverrSX;
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input pslverrSX;
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input [31:0] prdataSX;
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input [31:0] prdataSX;
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parameter ADDR_MSB = EXPR(ADDR_BITS-1);
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parameter ADDR_MSB = EXPR(ADDR_BITS-1);
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parameter ADDR_LSB = EXPR(ADDR_BITS-DEC_BITS);
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parameter ADDR_LSB = EXPR(ADDR_BITS-DEC_BITS);
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reg pready;
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reg pready;
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reg pslverr_pre;
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reg pslverr_pre;
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reg pslverr;
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reg pslverr;
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reg [31:0] prdata_pre;
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reg [31:0] prdata_pre;
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reg [31:0] prdata;
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reg [31:0] prdata;
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reg [SLV_BITS-1:0] slave_num;
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reg [SLV_BITS-1:0] slave_num;
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always @(*)
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always @(*)
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begin
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begin
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casex (cmd_addr[ADDR_MSB:ADDR_LSB])
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casex (cmd_addr[ADDR_MSB:ADDR_LSB])
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DEC_BITSDEC_ADDRSX : slave_num = SLV_BITS'dSX;
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DEC_BITSDEC_ADDRSX : slave_num = SLV_BITS'dSX;
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default : slave_num = SLV_BITS'dSLAVE_NUM; //decode error
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default : slave_num = SLV_BITS'dSLAVE_NUM; //decode error
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endcase
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endcase
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end
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end
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assign pselSX = psel & (slave_num == SLV_BITS'dSX);
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assign pselSX = psel & (slave_num == SLV_BITS'dSX);
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always @(*)
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always @(*)
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begin
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begin
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case (slave_num)
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case (slave_num)
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SLV_BITS'dSX: pready = preadySX;
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SLV_BITS'dSX: pready = preadySX;
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default : pready = 1'b1; //decode error
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default : pready = 1'b1; //decode error
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endcase
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endcase
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end
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end
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always @(*)
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always @(*)
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begin
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begin
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case (slave_num)
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case (slave_num)
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SLV_BITS'dSX: pslverr_pre = pslverrSX;
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SLV_BITS'dSX: pslverr_pre = pslverrSX;
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default : pslverr_pre = 1'b1; //decode error
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default : pslverr_pre = 1'b1; //decode error
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endcase
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endcase
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end
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end
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always @(*)
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always @(*)
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begin
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begin
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case (slave_num)
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case (slave_num)
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SLV_BITS'dSX: prdata_pre = prdataSX;
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SLV_BITS'dSX: prdata_pre = prdataSX;
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default : prdata_pre = {32{1'b0}};
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default : prdata_pre = {32{1'b0}};
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endcase
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endcase
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end
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end
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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begin
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begin
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prdata <= #FFD {32{1'b0}};
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prdata <= #FFD {32{1'b0}};
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pslverr <= #FFD 1'b0;
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pslverr <= #FFD 1'b0;
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end
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end
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else if (psel & pready)
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else if (psel & pready)
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begin
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begin
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prdata <= #FFD prdata_pre;
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prdata <= #FFD prdata_pre;
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pslverr <= #FFD pslverr_pre;
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pslverr <= #FFD pslverr_pre;
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end
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end
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else if (~psel)
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else if (~psel)
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begin
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begin
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prdata <= #FFD {32{1'b0}};
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prdata <= #FFD {32{1'b0}};
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pslverr <= #FFD 1'b0;
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pslverr <= #FFD 1'b0;
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end
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end
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endmodule
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endmodule
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