`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Company: M. A. Morris & Associates
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// Company: M. A. Morris & Associates
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// Engineer: Michael A. Morris
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// Engineer: Michael A. Morris
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//
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//
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// Create Date: 17:33:56 07/27/2008
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// Create Date: 17:33:56 07/27/2008
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// Design Name: BRSFmnCE
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// Design Name: BRSFmnCE
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// Module Name: C:/XProjects/ISE10.1i/BRAMFIFO/tb_BRSFmnCE.v
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// Module Name: C:/XProjects/ISE10.1i/BRAMFIFO/tb_BRSFmnCE.v
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// Project Name: BRAMFIFO
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// Project Name: BRAMFIFO
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// Target Device: SRAM-based FPGA: XC3S1400AN-4FGG656I, XC3S700AN-4FGG484I
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// Target Device: SRAM-based FPGA: XC3S1400AN-4FGG656I, XC3S700AN-4FGG484I
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// Tool versions: ISE 10.1i SP3
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// Tool versions: ISE 10.1i SP3
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// Description:
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// Description:
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//
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//
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// Verilog Test Fixture created by ISE for module: BRSFmnCE
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// Verilog Test Fixture created by ISE for module: BRSFmnCE
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//
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//
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// Dependencies: None
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// Dependencies: None
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//
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//
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// Revision:
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// Revision:
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//
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//
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// 1.00 08F27 MAM File Created
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// 1.00 08F27 MAM File Created
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//
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//
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// 1.10 13G12 MAM Prepared for release on Opencore.com.
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// 1.10 13G12 MAM Prepared for release on Opencore.com.
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//
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//
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// Additional Comments:
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// Additional Comments:
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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module tb_BRSFmnCE;
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module tb_BRSFmnCE;
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// Inputs
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// Inputs
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reg Rst;
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reg Rst;
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reg Clk;
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reg Clk;
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reg Clr;
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reg WE;
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reg WE;
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reg RE;
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reg [7:0] DI;
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reg [7:0] DI;
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// Outputs
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reg RE;
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wire [7:0] DO;
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wire [7:0] DO;
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wire ACK;
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wire ACK;
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wire FF;
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wire FF;
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wire AF;
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wire AF;
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wire HF;
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wire HF;
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wire AE;
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wire AE;
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wire EF;
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wire EF;
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wire [10:0] Cnt;
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wire [10:0] Cnt;
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integer i;
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integer i;
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// Instantiate the Unit Under Test (UUT)
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// Instantiate the Unit Under Test (UUT)
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BRSFmnCE uut (
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BRSFmnCE uut (
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.Rst(Rst),
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.Rst(Rst),
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.Clk(Clk),
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.Clk(Clk),
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.Clr(Clr),
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.WE(WE),
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.WE(WE),
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.DI(DI),
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.DI(DI),
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.RE(RE),
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.RE(RE),
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.DO(DO),
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.DO(DO),
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.ACK(ACK),
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.ACK(ACK),
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.FF(FF),
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.FF(FF),
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.AF(AF),
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.AF(AF),
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.HF(HF),
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.HF(HF),
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.AE(AE),
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.AE(AE),
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.EF(EF),
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.EF(EF),
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.Cnt(Cnt)
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.Cnt(Cnt)
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);
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);
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initial begin
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initial begin
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// Initialize Inputs
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// Initialize Inputs
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Rst = 1;
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Rst = 1;
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Clk = 1;
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Clk = 1;
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Clr = 0;
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WE = 0;
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WE = 0;
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RE = 0;
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RE = 0;
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DI = $random(5);
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DI = $random(5);
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i = 0;
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i = 0;
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// Wait 100 ns for global reset to finish
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// Wait 100 ns for global reset to finish
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#106 Rst = 0;
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#101 Rst = 0;
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// Add stimulus here
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// Add stimulus here
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while (AF != 1) begin
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while (AF != 1) begin
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@(posedge Clk) #1;
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@(posedge Clk) #1;
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if(AF != 1) begin
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if(AF != 1) begin
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DI = $random;
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DI = $random;
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WE = ~FF;
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WE = ~FF;
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i = i + 1;
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i = i + 1;
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end
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end
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end
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end
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WE = 0; DI = 0;
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WE = 0; DI = 0;
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RE = ~EF;
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RE = ~EF;
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while (AE != 1) begin
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while (AE != 1) begin
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@(posedge Clk) #1;
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@(posedge Clk) #1;
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if (AE != 1) begin
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if (AE != 1) begin
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RE = ~EF;
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RE = ~EF;
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i = i - 1;
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i = i - 1;
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end
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end
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end
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end
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RE = 0; i = i - 1;
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RE = 0; i = i - 1;
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@(negedge ACK);
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@(negedge ACK);
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@(posedge Clk) #1; WE = 1; DI = $random; i = i + 1;
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@(posedge Clk) #1; WE = 1; DI = $random; i = i + 1;
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@(posedge Clk) #1; WE = 0;
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@(posedge Clk) #1; WE = 0;
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@(posedge Clk) #1; RE = 1;
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@(posedge Clk) #1; RE = 1;
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@(posedge Clk) #1; RE = 0; i = i - 1;
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@(posedge Clk) #1; RE = 0; i = i - 1;
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end
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end
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Clock
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// Clock
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//
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//
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always #5 Clk = ~Clk;
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always #5 Clk = ~Clk;
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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endmodule
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endmodule
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