//**************************************************************
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//**************************************************************
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// Module : virtual_jtag_adda_trig.v
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// Module : virtual_jtag_adda_trig.v
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// Platform : Windows xp sp2
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// Platform : Windows xp sp2
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// Simulator : Modelsim 6.5b
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// Simulator : Modelsim 6.5b
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// Synthesizer : QuartusII 10.1 sp1
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// Synthesizer : QuartusII 10.1 sp1
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// Place and Route : QuartusII 10.1 sp1
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// Place and Route : QuartusII 10.1 sp1
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// Targets device : Cyclone III
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// Targets device : Cyclone III
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Organization : www.opencores.org
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// Organization : www.opencores.org
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// Revision : 2.1
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// Revision : 2.1
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// Date : 2012/03/15
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// Date : 2012/03/15
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// Description : addr/data trigger input from debug host
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// Description : addr/data trigger input from debug host
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// via Virtual JTAG.
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// via Virtual JTAG.
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//**************************************************************
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//**************************************************************
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`include "../../sim/altera/jtag_sim_define.h"
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`include "jtag_sim_define.h"
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module virtual_jtag_adda_trig(trig_out);
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module virtual_jtag_adda_trig(trig_out);
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parameter trig_width = 32;
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parameter trig_width = 32;
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output [trig_width-1:0] trig_out;
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output [trig_width-1:0] trig_out;
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reg [trig_width-1:0] trig_out;
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reg [trig_width-1:0] trig_out;
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wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
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wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
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reg tdo;
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reg tdo;
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reg [trig_width-1:0] trig_instr_reg;
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reg [trig_width-1:0] trig_instr_reg;
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reg bypass_reg;
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reg bypass_reg;
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wire [1:0] ir_in;
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wire [1:0] ir_in;
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wire trig_instr = ~ir_in[1] & ir_in[0]; // 1
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wire trig_instr = ~ir_in[1] & ir_in[0]; // 1
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always @(posedge tck)
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always @(posedge tck)
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begin
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begin
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if (trig_instr && e1dr)
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if (trig_instr && e1dr)
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trig_out <= trig_instr_reg;
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trig_out <= trig_instr_reg;
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end
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end
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/* trig_instr Instruction Handler */
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/* trig_instr Instruction Handler */
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always @ (posedge tck)
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always @ (posedge tck)
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if ( trig_instr && cdr )
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if ( trig_instr && cdr )
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trig_instr_reg <= trig_instr_reg;
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trig_instr_reg <= trig_instr_reg;
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else if ( trig_instr && sdr )
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else if ( trig_instr && sdr )
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trig_instr_reg <= {tdi, trig_instr_reg[trig_width-1:1]};
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trig_instr_reg <= {tdi, trig_instr_reg[trig_width-1:1]};
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/* Bypass register */
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/* Bypass register */
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always @ (posedge tck)
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always @ (posedge tck)
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bypass_reg <= tdi;
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bypass_reg <= tdi;
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/* Node TDO Output */
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/* Node TDO Output */
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always @ ( trig_instr, trig_instr_reg, bypass_reg )
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always @ ( trig_instr, trig_instr_reg, bypass_reg )
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begin
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begin
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if (trig_instr)
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if (trig_instr)
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tdo <= trig_instr_reg[0];
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tdo <= trig_instr_reg[0];
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else
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else
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tdo <= bypass_reg;// Used to maintain the continuity of the scan chain.
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tdo <= bypass_reg;// Used to maintain the continuity of the scan chain.
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end
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end
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sld_virtual_jtag sld_virtual_jtag_component (
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sld_virtual_jtag sld_virtual_jtag_component (
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.ir_in (ir_in),
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.ir_in (ir_in),
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.ir_out (2'b0),
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.ir_out (2'b0),
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.tdo (tdo),
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.tdo (tdo),
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.tdi (tdi),
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.tdi (tdi),
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.tms (),
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.tms (),
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.tck (tck),
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.tck (tck),
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.virtual_state_cir (cir),
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.virtual_state_cir (cir),
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.virtual_state_pdr (pdr),
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.virtual_state_pdr (pdr),
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.virtual_state_uir (uir),
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.virtual_state_uir (uir),
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.virtual_state_sdr (sdr),
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.virtual_state_sdr (sdr),
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.virtual_state_cdr (cdr),
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.virtual_state_cdr (cdr),
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.virtual_state_udr (udr),
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.virtual_state_udr (udr),
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.virtual_state_e1dr (e1dr),
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.virtual_state_e1dr (e1dr),
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.virtual_state_e2dr (e2dr),
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.virtual_state_e2dr (e2dr),
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.jtag_state_rti (),
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.jtag_state_rti (),
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.jtag_state_e1dr (),
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.jtag_state_e1dr (),
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.jtag_state_e2dr (),
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.jtag_state_e2dr (),
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.jtag_state_pir (),
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.jtag_state_pir (),
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.jtag_state_tlr (),
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.jtag_state_tlr (),
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.jtag_state_sir (),
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.jtag_state_sir (),
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.jtag_state_cir (),
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.jtag_state_cir (),
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.jtag_state_uir (),
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.jtag_state_uir (),
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.jtag_state_pdr (),
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.jtag_state_pdr (),
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.jtag_state_sdrs (),
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.jtag_state_sdrs (),
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.jtag_state_sdr (),
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.jtag_state_sdr (),
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.jtag_state_cdr (),
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.jtag_state_cdr (),
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.jtag_state_udr (),
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.jtag_state_udr (),
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.jtag_state_sirs (),
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.jtag_state_sirs (),
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.jtag_state_e1ir (),
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.jtag_state_e1ir (),
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.jtag_state_e2ir ());
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.jtag_state_e2ir ());
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defparam
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defparam
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sld_virtual_jtag_component.sld_auto_instance_index = "NO",
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sld_virtual_jtag_component.sld_auto_instance_index = "NO",
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sld_virtual_jtag_component.sld_instance_index = 2,
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sld_virtual_jtag_component.sld_instance_index = 2,
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sld_virtual_jtag_component.sld_ir_width = 2,
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sld_virtual_jtag_component.sld_ir_width = 2,
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`ifdef USE_SIM_STIMULUS
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sld_virtual_jtag_component.sld_sim_action = `TRIG_SLD_SIM_ACTION,
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sld_virtual_jtag_component.sld_sim_action = `TRIG_SLD_SIM_ACTION,
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sld_virtual_jtag_component.sld_sim_n_scan = `TRIG_SLD_SIM_N_SCAN,
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sld_virtual_jtag_component.sld_sim_n_scan = `TRIG_SLD_SIM_N_SCAN,
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sld_virtual_jtag_component.sld_sim_total_length = `TRIG_SLD_SIM_T_LENG;
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sld_virtual_jtag_component.sld_sim_total_length = `TRIG_SLD_SIM_T_LENG;
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`else
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sld_virtual_jtag_component.sld_sim_action = "((1,1,1,2))",
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sld_virtual_jtag_component.sld_sim_n_scan = 1,
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sld_virtual_jtag_component.sld_sim_total_length = 2;
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`endif
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endmodule
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endmodule
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