//**************************************************************
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//**************************************************************
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// Module : virtual_jtag_addr_mask.v
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// Module : virtual_jtag_addr_mask.v
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// Platform : Windows xp sp2
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// Platform : Windows xp sp2
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// Simulator : Modelsim 6.5b
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// Simulator : Modelsim 6.5b
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// Synthesizer : QuartusII 10.1 sp1
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// Synthesizer : QuartusII 10.1 sp1
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// Place and Route : QuartusII 10.1 sp1
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// Place and Route : QuartusII 10.1 sp1
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// Targets device : Cyclone III
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// Targets device : Cyclone III
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Organization : www.opencores.org
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// Organization : www.opencores.org
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// Revision : 2.1
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// Revision : 2.1
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// Date : 2012/03/15
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// Date : 2012/03/15
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// Description : addr mask input from debug host via
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// Description : addr mask input from debug host via
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// Virtual JTAG.
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// Virtual JTAG.
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//**************************************************************
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//**************************************************************
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`include "../../sim/altera/jtag_sim_define.h"
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module virtual_jtag_addr_mask(mask_out0 ,mask_out1 ,mask_out2 ,mask_out3 ,
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module virtual_jtag_addr_mask(mask_out0 ,mask_out1 ,mask_out2 ,mask_out3 ,
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mask_out4 ,mask_out5 ,mask_out6 ,mask_out7 ,
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mask_out4 ,mask_out5 ,mask_out6 ,mask_out7 ,
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mask_out8 ,mask_out9 ,mask_out10,mask_out11,
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mask_out8 ,mask_out9 ,mask_out10,mask_out11,
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mask_out12,mask_out13,mask_out14,mask_out15
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mask_out12,mask_out13,mask_out14,mask_out15
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);
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);
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parameter mask_index = 4, //2**mask_index=mask_num
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parameter mask_index = 4, //2**mask_index=mask_num
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mask_enabl = 4,
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mask_enabl = 4,
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addr_width = 32;
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addr_width = 32;
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output [mask_enabl+addr_width-1:0] mask_out0;
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output [mask_enabl+addr_width-1:0] mask_out0;
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output [mask_enabl+addr_width-1:0] mask_out1;
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output [mask_enabl+addr_width-1:0] mask_out1;
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output [mask_enabl+addr_width-1:0] mask_out2;
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output [mask_enabl+addr_width-1:0] mask_out2;
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output [mask_enabl+addr_width-1:0] mask_out3;
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output [mask_enabl+addr_width-1:0] mask_out3;
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output [mask_enabl+addr_width-1:0] mask_out4;
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output [mask_enabl+addr_width-1:0] mask_out4;
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output [mask_enabl+addr_width-1:0] mask_out5;
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output [mask_enabl+addr_width-1:0] mask_out5;
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output [mask_enabl+addr_width-1:0] mask_out6;
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output [mask_enabl+addr_width-1:0] mask_out6;
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output [mask_enabl+addr_width-1:0] mask_out7;
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output [mask_enabl+addr_width-1:0] mask_out7;
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output [mask_enabl+addr_width-1:0] mask_out8;
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output [mask_enabl+addr_width-1:0] mask_out8;
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output [mask_enabl+addr_width-1:0] mask_out9;
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output [mask_enabl+addr_width-1:0] mask_out9;
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output [mask_enabl+addr_width-1:0] mask_out10;
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output [mask_enabl+addr_width-1:0] mask_out10;
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output [mask_enabl+addr_width-1:0] mask_out11;
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output [mask_enabl+addr_width-1:0] mask_out11;
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output [mask_enabl+addr_width-1:0] mask_out12;
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output [mask_enabl+addr_width-1:0] mask_out12;
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output [mask_enabl+addr_width-1:0] mask_out13;
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output [mask_enabl+addr_width-1:0] mask_out13;
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output [mask_enabl+addr_width-1:0] mask_out14;
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output [mask_enabl+addr_width-1:0] mask_out14;
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output [mask_enabl+addr_width-1:0] mask_out15;
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output [mask_enabl+addr_width-1:0] mask_out15;
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reg [mask_enabl+addr_width-1:0] mask_out0;
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reg [mask_enabl+addr_width-1:0] mask_out0;
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reg [mask_enabl+addr_width-1:0] mask_out1;
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reg [mask_enabl+addr_width-1:0] mask_out1;
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reg [mask_enabl+addr_width-1:0] mask_out2;
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reg [mask_enabl+addr_width-1:0] mask_out2;
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reg [mask_enabl+addr_width-1:0] mask_out3;
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reg [mask_enabl+addr_width-1:0] mask_out3;
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reg [mask_enabl+addr_width-1:0] mask_out4;
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reg [mask_enabl+addr_width-1:0] mask_out4;
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reg [mask_enabl+addr_width-1:0] mask_out5;
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reg [mask_enabl+addr_width-1:0] mask_out5;
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reg [mask_enabl+addr_width-1:0] mask_out6;
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reg [mask_enabl+addr_width-1:0] mask_out6;
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reg [mask_enabl+addr_width-1:0] mask_out7;
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reg [mask_enabl+addr_width-1:0] mask_out7;
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reg [mask_enabl+addr_width-1:0] mask_out8;
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reg [mask_enabl+addr_width-1:0] mask_out8;
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reg [mask_enabl+addr_width-1:0] mask_out9;
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reg [mask_enabl+addr_width-1:0] mask_out9;
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reg [mask_enabl+addr_width-1:0] mask_out10;
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reg [mask_enabl+addr_width-1:0] mask_out10;
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reg [mask_enabl+addr_width-1:0] mask_out11;
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reg [mask_enabl+addr_width-1:0] mask_out11;
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reg [mask_enabl+addr_width-1:0] mask_out12;
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reg [mask_enabl+addr_width-1:0] mask_out12;
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reg [mask_enabl+addr_width-1:0] mask_out13;
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reg [mask_enabl+addr_width-1:0] mask_out13;
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reg [mask_enabl+addr_width-1:0] mask_out14;
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reg [mask_enabl+addr_width-1:0] mask_out14;
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reg [mask_enabl+addr_width-1:0] mask_out15;
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reg [mask_enabl+addr_width-1:0] mask_out15;
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wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
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wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
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reg tdo;
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reg tdo;
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reg [mask_index+mask_enabl+addr_width-1:0] mask_instr_reg;
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reg [mask_index+mask_enabl+addr_width-1:0] mask_instr_reg;
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reg bypass_reg;
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reg bypass_reg;
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wire [1:0] ir_in;
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wire [1:0] ir_in;
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wire mask_instr = ~ir_in[1] & ir_in[0]; // 1
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wire mask_instr = ~ir_in[1] & ir_in[0]; // 1
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wire [mask_index-1 :0] mask_id = mask_instr_reg[(mask_index+mask_enabl+addr_width-1):(mask_enabl+addr_width)];
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wire [mask_index-1 :0] mask_id = mask_instr_reg[(mask_index+mask_enabl+addr_width-1):(mask_enabl+addr_width)];
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wire [mask_enabl+addr_width-1:0] mask_is = mask_instr_reg[ (mask_enabl+addr_width-1):0];
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wire [mask_enabl+addr_width-1:0] mask_is = mask_instr_reg[ (mask_enabl+addr_width-1):0];
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always @(posedge tck)
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always @(posedge tck)
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begin
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begin
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if (mask_instr && e1dr)
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if (mask_instr && e1dr)
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case (mask_id)
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case (mask_id)
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4'd0 :
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4'd0 :
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mask_out0 <= mask_is;
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mask_out0 <= mask_is;
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4'd1 :
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4'd1 :
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mask_out1 <= mask_is;
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mask_out1 <= mask_is;
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4'd2 :
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4'd2 :
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mask_out2 <= mask_is;
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mask_out2 <= mask_is;
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4'd3 :
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4'd3 :
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mask_out3 <= mask_is;
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mask_out3 <= mask_is;
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4'd4 :
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4'd4 :
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mask_out4 <= mask_is;
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mask_out4 <= mask_is;
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4'd5 :
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4'd5 :
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mask_out5 <= mask_is;
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mask_out5 <= mask_is;
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4'd6 :
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4'd6 :
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mask_out6 <= mask_is;
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mask_out6 <= mask_is;
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4'd7 :
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4'd7 :
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mask_out7 <= mask_is;
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mask_out7 <= mask_is;
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4'd8 :
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4'd8 :
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mask_out8 <= mask_is;
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mask_out8 <= mask_is;
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4'd9 :
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4'd9 :
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mask_out9 <= mask_is;
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mask_out9 <= mask_is;
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4'd10 :
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4'd10 :
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mask_out10 <= mask_is;
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mask_out10 <= mask_is;
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4'd11 :
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4'd11 :
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mask_out11 <= mask_is;
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mask_out11 <= mask_is;
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4'd12 :
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4'd12 :
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mask_out12 <= mask_is;
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mask_out12 <= mask_is;
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4'd13 :
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4'd13 :
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mask_out13 <= mask_is;
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mask_out13 <= mask_is;
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4'd14 :
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4'd14 :
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mask_out14 <= mask_is;
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mask_out14 <= mask_is;
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4'd15 :
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4'd15 :
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mask_out15 <= mask_is;
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mask_out15 <= mask_is;
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endcase
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endcase
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end
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end
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/* mask_instr Instruction Handler */
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/* mask_instr Instruction Handler */
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always @ (posedge tck)
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always @ (posedge tck)
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if ( mask_instr && cdr )
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if ( mask_instr && cdr )
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mask_instr_reg <= mask_instr_reg;
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mask_instr_reg <= mask_instr_reg;
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else if ( mask_instr && sdr )
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else if ( mask_instr && sdr )
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mask_instr_reg <= {tdi, mask_instr_reg[mask_index+mask_enabl+addr_width-1:1]};
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mask_instr_reg <= {tdi, mask_instr_reg[mask_index+mask_enabl+addr_width-1:1]};
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/* Bypass register */
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/* Bypass register */
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always @ (posedge tck)
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always @ (posedge tck)
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bypass_reg = tdi;
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bypass_reg = tdi;
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/* Node TDO Output */
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/* Node TDO Output */
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always @ ( mask_instr, mask_instr_reg, bypass_reg )
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always @ ( mask_instr, mask_instr_reg, bypass_reg )
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begin
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begin
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if (mask_instr)
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if (mask_instr)
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tdo <= mask_instr_reg[0];
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tdo <= mask_instr_reg[0];
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else
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else
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tdo <= bypass_reg;// Used to maintain the continuity of the scan chain.
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tdo <= bypass_reg;// Used to maintain the continuity of the scan chain.
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end
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end
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sld_virtual_jtag sld_virtual_jtag_component (
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sld_virtual_jtag sld_virtual_jtag_component (
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.ir_in (ir_in),
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.ir_in (ir_in),
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.ir_out (2'b0),
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.ir_out (2'b0),
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.tdo (tdo),
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.tdo (tdo),
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.tdi (tdi),
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.tdi (tdi),
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.tms (),
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.tms (),
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.tck (tck),
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.tck (tck),
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.virtual_state_cir (cir),
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.virtual_state_cir (cir),
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.virtual_state_pdr (pdr),
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.virtual_state_pdr (pdr),
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.virtual_state_uir (uir),
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.virtual_state_uir (uir),
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.virtual_state_sdr (sdr),
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.virtual_state_sdr (sdr),
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.virtual_state_cdr (cdr),
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.virtual_state_cdr (cdr),
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.virtual_state_udr (udr),
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.virtual_state_udr (udr),
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.virtual_state_e1dr (e1dr),
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.virtual_state_e1dr (e1dr),
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.virtual_state_e2dr (e2dr),
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.virtual_state_e2dr (e2dr),
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.jtag_state_rti (),
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.jtag_state_rti (),
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.jtag_state_e1dr (),
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.jtag_state_e1dr (),
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.jtag_state_e2dr (),
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.jtag_state_e2dr (),
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.jtag_state_pir (),
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.jtag_state_pir (),
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.jtag_state_tlr (),
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.jtag_state_tlr (),
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.jtag_state_sir (),
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.jtag_state_sir (),
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.jtag_state_cir (),
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.jtag_state_cir (),
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.jtag_state_uir (),
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.jtag_state_uir (),
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.jtag_state_pdr (),
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.jtag_state_pdr (),
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.jtag_state_sdrs (),
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.jtag_state_sdrs (),
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.jtag_state_sdr (),
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.jtag_state_sdr (),
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.jtag_state_cdr (),
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.jtag_state_cdr (),
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.jtag_state_udr (),
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.jtag_state_udr (),
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.jtag_state_sirs (),
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.jtag_state_sirs (),
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.jtag_state_e1ir (),
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.jtag_state_e1ir (),
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.jtag_state_e2ir ());
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.jtag_state_e2ir ());
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defparam
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defparam
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sld_virtual_jtag_component.sld_auto_instance_index = "NO",
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sld_virtual_jtag_component.sld_auto_instance_index = "NO",
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sld_virtual_jtag_component.sld_instance_index = 1,
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sld_virtual_jtag_component.sld_instance_index = 1,
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sld_virtual_jtag_component.sld_ir_width = 2,
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sld_virtual_jtag_component.sld_ir_width = 2,
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sld_virtual_jtag_component.sld_sim_action = "((1,1,1,2))",
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sld_virtual_jtag_component.sld_sim_action = `ADDR_SLD_SIM_ACTION,
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sld_virtual_jtag_component.sld_sim_n_scan = 1,
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sld_virtual_jtag_component.sld_sim_n_scan = `ADDR_SLD_SIM_N_SCAN,
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sld_virtual_jtag_component.sld_sim_total_length = 2;
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sld_virtual_jtag_component.sld_sim_total_length = `ADDR_SLD_SIM_T_LENG;
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endmodule
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endmodule
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