// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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module qaz_system(
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module qaz_system(
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input [31:0] sys_data_i,
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input [31:0] sys_data_i,
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output [31:0] sys_data_o,
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output [31:0] sys_data_o,
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input [31:0] sys_addr_i,
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input [31:0] sys_addr_i,
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input [3:0] sys_sel_i,
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input [3:0] sys_sel_i,
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input sys_we_i,
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input sys_we_i,
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input sys_cyc_i,
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input sys_cyc_i,
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input sys_stb_i,
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input sys_stb_i,
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output sys_ack_o,
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output sys_ack_o,
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output sys_err_o,
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output sys_err_o,
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output sys_rty_o,
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output sys_rty_o,
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input async_rst_i,
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input async_rst_i,
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output reg sys_audio_clk_en,
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output [6:0] hex0,
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output [6:0] hex0,
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output [6:0] hex1,
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output [6:0] hex1,
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output [6:0] hex2,
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output [6:0] hex2,
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output [6:0] hex3,
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output [6:0] hex3,
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input sys_clk_i,
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input sys_clk_i,
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output sys_rst_o
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output sys_rst_o
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);
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);
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//---------------------------------------------------
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//---------------------------------------------------
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// register encoder
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// register encoder
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reg [3:0] register_offset_r;
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reg [3:0] register_offset_r;
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always @(*)
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always @(*)
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case( sys_addr_i[19:0] )
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case( sys_addr_i[19:0] )
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20'h0_0000: register_offset_r = 4'h0;
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20'h0_0000: register_offset_r = 4'h0;
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20'h0_0004: register_offset_r = 4'h4;
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20'h0_0004: register_offset_r = 4'h4;
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default: register_offset_r = 4'hf;
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default: register_offset_r = 4'hf;
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endcase
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endcase
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//---------------------------------------------------
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//---------------------------------------------------
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// register offset 0x0 -- system control register
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// register offset 0x0 -- system control register
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reg sys_rst_r;
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reg sys_rst_r;
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always @( posedge sys_clk_i )
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always @( posedge sys_clk_i )
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if( sys_rst_o )
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if( sys_rst_o )
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sys_rst_r <= 1'h0;
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sys_rst_r <= 1'h0;
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else if( (sys_cyc_i & sys_stb_i & sys_we_i) & (register_offset_r == 4'h0) )
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else if( (sys_cyc_i & sys_stb_i & sys_we_i) & (register_offset_r == 4'h0) )
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sys_rst_r <= sys_data_i[0];
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sys_rst_r <= sys_data_i[0];
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wire [31:0] sys_register_0 = { 31'b0, sys_rst_r };
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always @( posedge sys_clk_i )
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if( sys_rst_o )
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sys_audio_clk_en <= 1'h0;
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else if( (sys_cyc_i & sys_stb_i & sys_we_i) & (register_offset_r == 4'h0) )
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sys_audio_clk_en <= sys_data_i[4];
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wire [31:0] sys_register_0 = {
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27'b0,
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sys_audio_clk_en,
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3'b000,
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sys_rst_r
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};
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//---------------------------------------------------
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//---------------------------------------------------
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// register offset 0x4 -- hex led display register
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// register offset 0x4 -- hex led display register
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reg [31:0] sys_register_4;
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reg [31:0] sys_register_4;
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always @( posedge sys_clk_i )
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always @( posedge sys_clk_i )
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if( sys_rst_o )
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if( sys_rst_o )
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sys_register_4 <= 32'h0000ffff;
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sys_register_4 <= 32'h0000ffff;
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else if( (sys_cyc_i & sys_stb_i & sys_we_i) & (register_offset_r == 4'h4) )
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else if( (sys_cyc_i & sys_stb_i & sys_we_i) & (register_offset_r == 4'h4) )
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sys_register_4 <= sys_data_i;
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sys_register_4 <= sys_data_i;
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//---------------------------------------------------
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//---------------------------------------------------
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// register mux
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// register mux
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reg [31:0] sys_data_o_r;
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reg [31:0] sys_data_o_r;
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always @(*)
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always @(*)
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case( register_offset_r )
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case( register_offset_r )
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4'h0: sys_data_o_r = sys_register_0;
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4'h0: sys_data_o_r = sys_register_0;
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4'h4: sys_data_o_r = sys_register_4;
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4'h4: sys_data_o_r = sys_register_4;
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4'hf: sys_data_o_r = 32'h1bad_c0de;
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4'hf: sys_data_o_r = 32'h1bad_c0de;
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default: sys_data_o_r = 32'h1bad_c0de;
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default: sys_data_o_r = 32'h1bad_c0de;
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endcase
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endcase
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//---------------------------------------------------
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//---------------------------------------------------
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// sync reset
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// sync reset
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sync
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sync
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i_sync_reset(
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i_sync_reset(
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.async_sig( async_rst_i | sys_rst_r ),
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.async_sig( async_rst_i | sys_rst_r ),
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.sync_out(sys_rst_o),
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.sync_out(sys_rst_o),
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.clk(sys_clk_i)
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.clk(sys_clk_i)
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);
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);
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//---------------------------------------------------
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//---------------------------------------------------
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// hex led encoders
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// hex led encoders
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hex_led_encoder
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hex_led_encoder
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i_hex0(
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i_hex0(
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.encoder(hex0),
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.encoder(hex0),
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.nibble(sys_register_4[3:0])
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.nibble(sys_register_4[3:0])
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);
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);
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hex_led_encoder
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hex_led_encoder
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i_hex1(
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i_hex1(
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.encoder(hex1),
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.encoder(hex1),
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.nibble(sys_register_4[7:4])
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.nibble(sys_register_4[7:4])
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);
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);
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hex_led_encoder
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hex_led_encoder
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i_hex2(
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i_hex2(
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.encoder(hex2),
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.encoder(hex2),
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.nibble(sys_register_4[11:8])
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.nibble(sys_register_4[11:8])
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);
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);
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hex_led_encoder
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hex_led_encoder
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i_hex3(
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i_hex3(
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.encoder(hex3),
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.encoder(hex3),
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.nibble(sys_register_4[15:12])
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.nibble(sys_register_4[15:12])
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);
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);
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//---------------------------------------------------
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//---------------------------------------------------
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// outputs
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// outputs
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assign sys_data_o = sys_data_o_r;
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assign sys_data_o = sys_data_o_r;
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assign sys_ack_o = sys_cyc_i & sys_stb_i;
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assign sys_ack_o = sys_cyc_i & sys_stb_i;
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assign sys_err_o = 1'b0;
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assign sys_err_o = 1'b0;
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assign sys_rty_o = 1'b0;
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assign sys_rty_o = 1'b0;
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endmodule
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endmodule
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