----------------------------------------------------------------------------------
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-- Company:
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-- Copyright (c) 2013 Antonio de la Piedra
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-- Engineer:
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--
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-- This program is free software: you can redistribute it and/or modify
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-- Create Date: 09:30:59 02/20/2013
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-- it under the terms of the GNU General Public License as published by
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-- Design Name:
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-- the Free Software Foundation, either version 3 of the License, or
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-- Module Name: des - Behavioral
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-- (at your option) any later version.
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-- Project Name:
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-- Target Devices:
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-- This program is distributed in the hope that it will be useful,
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-- Tool versions:
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- Description:
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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--
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-- GNU General Public License for more details.
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-- Dependencies:
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--
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-- You should have received a copy of the GNU General Public License
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-- Revision:
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity des_loop is
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entity des_loop is
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port(clk : in std_logic;
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port(clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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mode : in std_logic; -- 0 encrypt, 1 decrypt
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mode : in std_logic; -- 0 encrypt, 1 decrypt
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key_in : in std_logic_vector(55 downto 0);
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key_in : in std_logic_vector(55 downto 0);
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blk_in : in std_logic_vector(63 downto 0);
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blk_in : in std_logic_vector(63 downto 0);
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blk_out : out std_logic_vector(63 downto 0));
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blk_out : out std_logic_vector(63 downto 0));
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end des_loop;
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end des_loop;
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architecture Behavioral of des_loop is
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architecture Behavioral of des_loop is
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signal after_ip_s : std_logic_vector(63 downto 0);
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signal after_ip_s : std_logic_vector(63 downto 0);
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signal after_ip_minus_one_s : std_logic_vector(63 downto 0);
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signal after_ip_minus_one_s : std_logic_vector(63 downto 0);
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signal after_f_s : std_logic_vector(31 downto 0);
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signal after_f_s : std_logic_vector(31 downto 0);
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signal final_s : std_logic_vector(63 downto 0);
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signal final_s : std_logic_vector(63 downto 0);
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component des_round is
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component des_round is
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port(clk : in std_logic;
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port(clk : in std_logic;
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l_0 : in std_logic_vector(31 downto 0);
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l_0 : in std_logic_vector(31 downto 0);
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r_0 : in std_logic_vector(31 downto 0);
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r_0 : in std_logic_vector(31 downto 0);
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k_i : in std_logic_vector(47 downto 0);
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k_i : in std_logic_vector(47 downto 0);
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l_1 : out std_logic_vector(31 downto 0);
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l_1 : out std_logic_vector(31 downto 0);
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r_1 : out std_logic_vector(31 downto 0));
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r_1 : out std_logic_vector(31 downto 0));
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end component;
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end component;
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component key_schedule is
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component key_schedule is
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port(clk : in std_logic;
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port(clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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mode : in std_logic; -- 0 encrypt, 1 decrypt
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mode : in std_logic; -- 0 encrypt, 1 decrypt
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key : in std_logic_vector(55 downto 0);
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key : in std_logic_vector(55 downto 0);
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key_out : out std_logic_vector(47 downto 0));
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key_out : out std_logic_vector(47 downto 0));
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end component;
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end component;
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signal key_s : std_logic_vector(47 downto 0);
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signal key_s : std_logic_vector(47 downto 0);
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signal l_0_s : std_logic_vector(31 downto 0);
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signal l_0_s : std_logic_vector(31 downto 0);
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signal l_1_s : std_logic_vector(31 downto 0);
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signal l_1_s : std_logic_vector(31 downto 0);
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signal r_0_s : std_logic_vector(31 downto 0);
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signal r_0_s : std_logic_vector(31 downto 0);
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signal r_1_s : std_logic_vector(31 downto 0);
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signal r_1_s : std_logic_vector(31 downto 0);
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signal rst_s : std_logic;
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signal rst_s : std_logic;
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begin
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begin
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pr_rst_delay : process(clk, rst)
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pr_rst_delay : process(clk, rst)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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rst_s <= rst;
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rst_s <= rst;
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end if;
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end if;
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end process;
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end process;
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pr_seq: process(clk, rst_s, blk_in)
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pr_seq: process(clk, rst_s, blk_in)
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begin
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begin
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if rst_s = '1' then
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if rst_s = '1' then
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l_0_s <= blk_in(63 downto 32);
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l_0_s <= blk_in(63 downto 32);
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r_0_s <= blk_in(31 downto 0);
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r_0_s <= blk_in(31 downto 0);
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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l_0_s <= l_1_s;
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l_0_s <= l_1_s;
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r_0_s <= r_1_s;
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r_0_s <= r_1_s;
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end if;
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end if;
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end process;
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end process;
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DES_ROUND_0 : des_round port map (clk, l_0_s, r_0_s, key_s, l_1_s, r_1_s);
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DES_ROUND_0 : des_round port map (clk, l_0_s, r_0_s, key_s, l_1_s, r_1_s);
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blk_out <= r_1_s & l_1_s;
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blk_out <= r_1_s & l_1_s;
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KEY_SCHEDULE_0 : key_schedule port map (clk, rst, mode, key_in, key_s);
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KEY_SCHEDULE_0 : key_schedule port map (clk, rst, mode, key_in, key_s);
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end Behavioral;
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end Behavioral;
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