--------------------------------------------------------------------------------
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-- Company:
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-- Copyright (c) 2013 Antonio de la Piedra
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-- Engineer:
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--
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-- This program is free software: you can redistribute it and/or modify
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-- Create Date: 11:47:33 02/21/2013
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-- it under the terms of the GNU General Public License as published by
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-- Design Name:
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-- the Free Software Foundation, either version 3 of the License, or
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-- Module Name: C:/Users/vmr/Desktop/crypto_ng/des/dram/desl/tb_des_loop.vhd
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-- (at your option) any later version.
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-- Project Name: desl
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-- Target Device:
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-- This program is distributed in the hope that it will be useful,
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-- Tool versions:
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- Description:
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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--
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-- GNU General Public License for more details.
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-- VHDL Test Bench Created by ISE for module: des_loop
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--
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-- You should have received a copy of the GNU General Public License
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-- Dependencies:
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY tb_des_loop IS
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ENTITY tb_des_loop IS
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END tb_des_loop;
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END tb_des_loop;
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ARCHITECTURE behavior OF tb_des_loop IS
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ARCHITECTURE behavior OF tb_des_loop IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT des_loop
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COMPONENT des_loop
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PORT(
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PORT(
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clk : IN std_logic;
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clk : IN std_logic;
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rst : IN std_logic;
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rst : IN std_logic;
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mode : IN std_logic;
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mode : IN std_logic;
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key_in : IN std_logic_vector(55 downto 0);
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key_in : IN std_logic_vector(55 downto 0);
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blk_in : IN std_logic_vector(63 downto 0);
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blk_in : IN std_logic_vector(63 downto 0);
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blk_out : OUT std_logic_vector(63 downto 0)
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blk_out : OUT std_logic_vector(63 downto 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal clk : std_logic := '0';
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signal clk : std_logic := '0';
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signal rst : std_logic := '0';
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signal rst : std_logic := '0';
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signal mode : std_logic := '0';
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signal mode : std_logic := '0';
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signal key_in : std_logic_vector(55 downto 0) := (others => '0');
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signal key_in : std_logic_vector(55 downto 0) := (others => '0');
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signal blk_in : std_logic_vector(63 downto 0) := (others => '0');
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signal blk_in : std_logic_vector(63 downto 0) := (others => '0');
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--Outputs
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--Outputs
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signal blk_out : std_logic_vector(63 downto 0);
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signal blk_out : std_logic_vector(63 downto 0);
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-- Clock period definitions
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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constant clk_period : time := 10 ns;
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: des_loop PORT MAP (
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uut: des_loop PORT MAP (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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mode => mode,
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mode => mode,
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key_in => key_in,
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key_in => key_in,
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blk_in => blk_in,
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blk_in => blk_in,
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blk_out => blk_out
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blk_out => blk_out
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clk_process :process
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clk_process :process
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begin
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begin
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clk <= '0';
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clk <= '0';
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wait for clk_period/2;
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wait for clk_period/2;
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clk <= '1';
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clk <= '1';
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wait for clk_period/2;
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wait for clk_period/2;
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end process;
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end process;
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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begin
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begin
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wait for clk_period/2 + clk_period;
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wait for clk_period/2 + clk_period;
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mode <= '0';
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mode <= '0';
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blk_in <= X"4E45565251554954";
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blk_in <= X"4E45565251554954";
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key_in <= "00000000111111110000000000101010010100000000000110010100";
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key_in <= "00000000111111110000000000101010010100000000000110010100";
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rst <= '1';
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rst <= '1';
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wait for clk_period;
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wait for clk_period;
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rst <= '0';
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rst <= '0';
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wait for clk_period*16;
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wait for clk_period*16;
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assert blk_out = X"72c6e3c6d2168e78"
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assert blk_out = X"72c6e3c6d2168e78"
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report "ENCRYPT ERROR" severity FAILURE;
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report "ENCRYPT ERROR" severity FAILURE;
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wait for clk_period;
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wait for clk_period;
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mode <= '1';
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mode <= '1';
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blk_in <= X"72c6e3c6d2168e78";
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blk_in <= X"72c6e3c6d2168e78";
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key_in <= "00000000111111110000000000101010010100000000000110010100";
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key_in <= "00000000111111110000000000101010010100000000000110010100";
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rst <= '1';
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rst <= '1';
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wait for clk_period;
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wait for clk_period;
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rst <= '0';
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rst <= '0';
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wait for clk_period*16;
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wait for clk_period*16;
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assert blk_out = X"4E45565251554954"
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assert blk_out = X"4E45565251554954"
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report "DECRYPT ERROR" severity FAILURE;
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report "DECRYPT ERROR" severity FAILURE;
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wait;
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wait;
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end process;
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end process;
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END;
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END;
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